In a semiconductor device having an element isolation region including a LOCOS type field oxide film formed in a surface of a silicon substrate and a U-trench isolation region provided in the silicon substrate, the U-trench isolation region is constituted with a U-trench provided such that it penetrates the field oxide film, a channel stopper provided in a portion of the silicon substrate exposed on a bottom face of the U-trench, a first film in a form of a silicon oxide film formed by thermal oxidation of an exposed portion of the silicon substrate in the U-trench, a second film comprising a buried layer having thermal reflow characteristics and burying the U-trench, a third film having non-thermal reflow characteristics and having a top face substantially coplanar with a top face of the field oxide film and a bottom face connected to a top face of the second films and a fourth film in a form of an insulating film connected to the top face of the third film at an upper end of said U-trench and covering the U-trench. In the element isolation region having this structure, there is no leakage current produced due to thermal oxidation of a polysilicon film buried in the U-trench, contrary to the conventional U-trench isolation region having buried polysilicon film. Further, increase of parasitic capacitance which is caused by thermal oxidation of the buried polysilicon layer can be also restricted.

1. Field of the Invention
The present invention relates to a semiconductor device and, particularly, to an element isolation region of a semiconductor device, which is composed of a LOCOS type field oxide film and a U-trench isolation region.
2. Description of the Prior Art
The LSI of semiconductor device on a silicon substrate has been realized by providing element isolation regions each between adjacent ones of a plurality of transistors. Such element isolation region to be used in a semiconductor device includes P-N junction isolation region, field oxide film such as LOCOS field oxide film and U-trench isolation region, etc. The P-N junction isolation region and the U-trench isolation region are isolation regions for elements having such deep P-N junction as in a collector region of a bipolar transistor. On the other hand, the field oxide film provides an isolation region for elements having shallow P-N junction such as between an element formed on a silicon substrate surface and a wiring formed on the substrate or between a source-drain region of a MOS transistor.
Thus, for the element isolation region of a semiconductor device comprising MOS transistor, the field oxide film is used and, for the element isolation of semiconductor device comprising bipolar transistor, combination of the P-N junction or U-trench isolation and the field oxide film. With decrease of element size, the LOCOS type field oxide film and the combination of the LOCOS type field oxide film and the U-trench isolation region is used mainly for a semiconductor device comprising MOS transistor and for a semiconductor device comprising bipolar transistor, respectively, in views of self-alignment and reduction of element isolation region.
In a semiconductor device including a MOS transistor, the MOS transistor was a P channel MOS transistor, firstly, and, then, an N channel MOS transistor was used and, currently, a MOS transistor is used mainly. The semiconductor device using a CMOS transistor employed initially an N well or a P well and now employs an N well and a P well. Therefore, in the semiconductor device including MOS transistor, an element isolation region for isolating the N well from the P well, both having deep P-N junctions, is necessary and, further, for latch-up problem, the use of a U-trench isolation region is becoming considered. Further, in view of a BICMOS transistor composed of a CMOS transistor and a bipolar transistor which is becoming popular, the necessity of element isolation region including a LOCOS type field oxide film and a U-trench isolation region is increasing.
Now, a conventional element isolation region including a LOCOS type field oxide film and a U-trench isolation region will be described. Such element isolation region comprises a field oxide film formed on a silicon substrate surface by a LOCOS process, a U-trench penetrating the field oxide film into the silicon substrate, a channel stopper provided on a surface portion of the silicon substrate which is a bottom face of the U-trench, an insulating film covering a surface of the silicon substrate portion constituting a wall of the U-trench, a filler in the U-trench and an insulating film filling the U-trench up to an upper end of the U-trench. The filler is usually of a polysilicon film. In this structure, the insulating film burying the U-trench to close the upper end thereof is formed by thermal oxidation of this polysilicon film which is connected to the field oxide film. With the connection of these oxide films, a surface flatness of the element isolation region is maintained to some extent which will be described later. The insulating film covering the wall of the U-trench comprise a silicon oxide film obtained by, for example, oxidizing a surface of silicon substrate. The channel stopper is formed by impurity ion injection of the same conductivity type as that of the silicon substrate to the bottom face of the U-trench, after the latter is formed by etching.
There are two typical methods for fabrication of such element isolation region. These methods will be described by taking an element isolation region for a NPN bipolar transistor as an example.
The first method comprises the following steps: An N.sup.+ buried layer is formed in a surface of a P type silicon substrate and an N type epitaxial layer is formed on the P type silicon substrate surface including an N.sup.+ type buried layer. A field oxide film of LOCOS type is formed on a surface of the epitaxial layer. Then, a U-trench penetrating the field oxide film, the N.sup.+ type epitaxial layer and the N type buried layer is formed by etching. A silicon oxide film covering portions of the N type epitaxial layer and the N.sup.+ type buried layer and a surface portion of the P type silicon substrate exposed on a wall of the U-trench is formed by thermal oxidation. A P type channel stopper is formed on a surface portion of the P type silicon substrate exposed on a surface portion of the P type silicon substrate exposed on a bottom face of the U-trench, by ion-injection of boron. On the whole surface of this wafer, a non-doped polysilicon film is deposited by a CVD process. The polysilicon film is etched back, leaving a portion thereof within the U-trench. On a top face of the polysilicon film, a silicon oxide film is formed by thermal oxidation by which the upper end of the U-trench is closed.
According to the second method, an N.sup.+ type buried layer is formed in a surface of a P type silicon substrate and, then, an N type epitaxial layer is formed on the surface of the P type silicon substrate including the N.sup.+ type buried layer. A silicon oxide film is formed on a surface of the N type epitaxial layer by a CVD process. Portions of the silicon oxide film on a region in which a U-trench is to be formed are removed. With using the silicon oxide film as an etch mask, the N type epitacial layer, the N.sup.+ type buried layer and the P type silicon substrate are etched in the order, resulting in a U-trench. A P type channel stopper is formed on the P type silicon substrate exposed on a bottom face of the U-trench by ion injection of boron. The silicon oxide film used as the mask in the etching step is removed. A silicon oxide film is formed on the N.sup.+ type buried layer, the P type silicon substrate and the N type epitaxial layer which are exposed on the wall of the U-trench, by thermal oxidation. On the whole surface, a non-doped polysilicon film is deposited by a CVD process. The polysilicon film is etched back, leaving a portion thereof within the U-trench. On the whole surface, a pad oxide film and a silicon nitride film are formed. A portion of the silicon nitride film on an area in which a field oxide film is to be formed is removed. The field oxide film is formed on the N type epitaxial layer by a LOCOS process, and a silicon oxide film is formed on an upper end of the U-trench by thermal oxidation of the polysilicon film surface. The remaining silicon nitride film and the pad oxide film are removed.
In the first method, the top face of the silicon oxide film formed by thermal oxidation of the polysilicon film buring the U-trench and closing the upper end of the U-trench, hardly becomes coplanar with the top face of the field oxide film, resulting in a step at a joining portion therebetween. In the second method, a recess is formed at a junction between the silicon oxide film closing the upper end of the U-trench and the field oxide film. That is, in these methods, it is difficult to obtain a complete flatness at the junction of these oxide films. In this case, breakage of a wiring formed on the junction area tends to occur.
In order to solve these problems, a third method has been proposed by y.-C. Simon Yu, et al. on J. Elecytochem. Soc., Vol. 137, No. 6, pp 1942-1950, (1990). According to this proposal, the LOCOS field oxide film is formed in two steps. First, a first field oxide film is formed on a top face of the polysilicon film burying the U-trench. Then, a second field oxide film is formed in an area adjacent to the first field oxide film.
In detail, in the third method, an N.sup.+ buried layer is formed on a P type silicon substrate and an N type epitaxial layer is formed on the P type silicon substrate surface including the N.sup.+ type buried layer. A pad oxide film and a silicon nitride film are formed on a surface of the N type epitaxial layer. Portions of the silicon nitride film and the pad oxide film on an area in which the U-trench is to be formed are removed by etching and, then, the N type epitaxial layer, the N.sup.+ type buried layer and the P type silicon substrate in the same area are etched in sequence, resulting in the U-trench. In this series of etching steps, the pad oxide film is under cut. A channel stopper is formed on a surface of the P type silicon substrate exposed on bottom face of the U-trench by ion injection of boron. A silicon oxide film is formed on the surfaces of the N type epitaxial layer, the N.sup.+ type buried layer and the P type silicon substrate exposed on a wall of the U-trench by thermal oxidation. This silicon oxide film is connected to the pad oxide film in the vicinity of the upper end of the U-trench. On the whole surface, a non-doped polysilicon film is deposited by a CVD process. The polysilicon film is etched back such that the portion thereof within the U-trench is left as it is. The first field oxide film is formed on the surface of the polysilicon film by a LOCOS process using the silicon nitride film as a mask. A portion of the silicon nitride film on an area in which the second field oxide film is to be formed is removed by etching and, then, by using a LOCOS process again, the second field oxide film connected to the first film oxide film is formed on the N type epitaxial layer. In the junction between the first and second field oxide films, there is no step or recess formed. Therefore, it is possible to obtain a substantially complete flatness in the junction area.
In the conventional element isolation region including the LOCOS type field oxide film and the U-trench isolation region which is buried with the polysilicon film, the flatness of the surface of element isolation region including the junction area of these two isolation regions is maintained. However, there is a problem in the U-trench isolation region which is buried with the polysilicon film, regardless of the the structure and formation of the field insulating film. That is, the problem resides in the formation of the silicon oxide film on the upper end of the U-trench by the thermal oxidation of the top face of the polysilicon film burying the U-trench. In the thermal oxidation, the polysilicon film expands in volume with expansion coefficient of about 1.5 times that of the surrounding silicon, so that stress is exerted on silicon crystal surrounding the polysilicon film and crystal defects may be formed, resulting in leakage current. Further, parasitic capacitance between regions adjacent to each other through the U-trench is not reduced by the presence of the polysilicon film burying the U-trench. The parasitic capacitance may be increased if the polysilicon film which is non-doped, is doped with conductive impurity.
N. Sugiyama et al. propose in 1989 Symposium on VLSI Technology Digest papers, pp 59-60, a method for solving the problem caused by the volume expansion of polysilicon in a U-trench isolation region. In this article, a LOCOS type field oxide film is not used, and, instead thereof, a field insulating film is formed on a silicon substrate surface by a CVD process after a U-trench is formed. The U-trench is buried with a BPSG film. A bipolar transistor is formed by using the U-trench isolation region filled with the BPSG film and an emitter-collector leakage current was measured. A result showed a substantial improvement of leakage current, compared with a bipolar transistor with the U-trench isolation region filled with a polysilicon film.
The formation of the U-trench isolation region buried with BPSG film is summarized as below: A U-trench is formed in a predetermined portion of a silicon substrate by etching the portion. On a silicon surface including the silicon substrate exposed on a wall of the U-trench is thermally oxidized to form a silicon oxide film. A silicon nitride film is deposited thereon. A BPSG film is deposited thereon by a CVD process and a surface of the BPSG film is flattened by heat treatment. The BPSG film is etched back to make a top face thereof and an upper end of the U-trench coplanar. The purpose of the silicon oxide film is to obtain a good contact of the silicon nitride film and the purpose of the silicon nitride film is to protect the silicon substrate against the etch back of the BPSG film. Further the silicon oxide film and the silicon nitride film serve to prevent diffusion of boron and phosphor from the BPSG film to the silicon substrate during the heat-treatment of the BPSG film. This formation utilizes the thermal reflow characteristics of the BPSG film.
The element isolation of proposed by M. Sugiyama et al. is not advantageous in reducing the size of semiconductor element. For example, when a bipolar transistor is formed, it is necessary to separately form a hole of a field insulating film for forming a collector plug region and holes of the field oxide film for forming an emitter region and a base region. This means that it is impossible to use a self-alignment scheme. Thus, the number of photolithographic steps is increased and the alignment margin of photo masks is increased. These problems become severe when a semiconductor includes MOS transistor.
It is not practical to merely combine a U-trench isolation region according to Sugiyama et al, and a LOCOS field oxide film. That is, when such combination is used, a pad oxide film and a silicon nitride film are formed on a surface of a silicon substrate. Then, a portion of the silicon nitride film on an area of the substrate surface in which a field oxide film is to be formed is etched away. After the field oxide film is formed thereon by a LOCOS process, portions of the field oxide film and the silicon substrate in an area in which a U-trench is to be formed are etched away, resulting a U-trench. Then, a silicon oxide film is formed on a portion of the silicon substrate exposed on the wall of the U-trench by thermal oxidation and, thereafter, a BPSG film is deposited on the whole surface by a CVD process and its surface is flattened by the heat treatment. Then, the BPSG film is etched back to make a top face of the BPSG film substantially coplanar with an upper end of the U-trench, leaving the BPSG film on the pad oxide film. In order to completely remove the BPSG film on the pad oxide film by etch back thereof, the top face of the BPSG film becomes lower than the upper end of the U-trench. As such, even if an insulating film covering the top face of the BPSG film is formed, there is a step between the field oxide film and the BPSG film, causing a wiring passing over the U-trench isolation region to be easily broken.

Semiconductor device including a locos type field oxide film and a U trench penetrating the locos film


Banknotes emerging from a checking machine are caused to advance singly in succession along an outfeed duct of which the runout connects with a stacking channel; the banknotes come to rest on a companion element operating along the channel and capable of movement between a first receiving position, in which the banknotes are allowed to accumulate until formed into a group of given number that corresponds to one stack, and a second release position within the operating compass of a compactor with hinged arms, of which the function is to compress and hold the stack against the companion element. The compacted stack of banknotes is picked up finally by a gripper and transferred from the companion element to a bundling machine, which binds it with a wrapping band.

The present invention relates to a device for forming and transferring ordered stacks of sheets, in particular banknotes.
The present invention is employable to advantage in machines by which banknotes are first ordered and then wrapped in bundles, or in groups of bundles, and, indeed, reference is made herein specifically to this type of application, albeit no limitation in general scope being implied.
The prior art embraces machines for checking the quality or condition of banknotes. In operation, a succession of banknotes of whatever type is introduced into an infeed end of a prior art machine, which, having checked the notes and eliminated any that are found to be defective, divides up the good notes according to denomination and/or type, directing them toward respective outlets of the machine, which are independent one of another.
In this way, groups of respective same denomination or same-type, banknotes are formed at each of the respective outlets; once a predetermined number of banknotes per group has accumulated, the groups are picked-up manually and transferred to a machine by which each of the groups is bound individually with at least one wrapping band to create a respective bundle.

Device for forming and transferring ordered stacks of sheets, in particular banknotes


Aminocyclohexylester compounds, including thioesters, are disclosed. The compounds of the present invention may be incorporated in compositions and kits. The present invention also discloses a variety of in vitro and in vivo uses for the compounds and compositions, including the blockade of ion channels and the treatment of arrhythmias.

Arrhythmia is a variation from the normal rhythm of the heart beat. The major cause of fatalities due to cardiac arrhythmias is the subtype of arrhythmias known as ventricular fibrillation. Conservative estimates indicate that, in the U.S. alone, approximately 300,000 individuals per year suffer heart attacks. Approximately half of these die from sudden cardiac death, the major cause of which is ventricular fibrillation.
Antiarrhythmic agents have been developed to prevent or alleviate cardiac arrhythmia. For example, Class I antiarrhythmic compounds have been used to treat supraventricular arrhythmias and ventricular arrhythmias. Treatment of ventricular arrhythmia is very important since such an arrhythmia, especially ventricular fibrillation, can be fatal. Serious ventricular arrhythmias (ventricular tachycardia and ventricular fibrillation) occur most often in the presence of myocardial ischemia and/or infarction. Ventricular fibrillation often occurs in the setting of acute myocardial ischemia, before infarction fully develops. At present, lidocaine is the current drug of choice for prevention of ventricular fibrillation. However, many Class I antiarrhythmic compounds may actually increase mortality in patients who have had a myocardial infarction. Therefore, there is a need in the art to identify new antiarrhythmic treatments, particularly treatments for ventricular arrhythmias. The present invention fulfills this need, and further provides other related advantages.


Provided is a post-treatment method of a lithium secondary battery including: an activation step of charging a heated lithium secondary battery to an activation voltage and maintaining the battery at the voltage, in a state in which the lithium secondary battery including a positive electrode including a nickel-rich (Ni-rich) lithium-transition metal composite oxide having a layered structure containing 0.8 moles or more of Ni based on a total of 1 mole of transition metals as a positive electrode active material; a negative electrode; a separator interposed between the positive electrode and the negative electrode; and an electrolyte solution, which are built in a battery case, is heated, the activation voltage being equal to or higher than a voltage generating phase transition of the lithium-transition metal composite oxide.

A nickel-rich lithium-transition metal compound having a layered structure has a merit of having a high energy density and a competitive price and having reversible discharge capacity increased in proportion to a Ni content.
In particular, since a nickel-rich lithium-transition metal oxide having a nickel content of 80% or more in transition metals may have an average discharge potential of about 3.9 V (vs. Li+/Li) and an average discharge capacity up to about 200 mAh/g, it has received attention as a next-generation high-capacity active material which may achieve a mileage of 500 km or more.
However, the nickel-rich lithium-transition metal compound having a nickel content of 80% or more in transition metals has problems of undergoing phase transition of the crystal structure at a high voltage of 4.15 V and generating gas by an oxidation reaction, and the gas generation has a bad influence on a battery, like deterioration of life performance at a high temperature and battery life shortening.
Meanwhile, a technique in which gas is intentionally generated by charging a battery at a voltage of 4.4 V to 5.0 V in a post-treatment process and then removed, for increasing a capacity and solving the gas generation problem due to phase transition in a manganese-based positive electrode active material, has been suggested, for example, in U.S. Pat. No. 9,324,994.
However, in the nickel-rich lithium-transition metal compound having a nickel content of 80% or more in transition metals, thermal runaway occurs at a relatively low voltage, and it is difficult to apply a high voltage in a post-treatment process to completely remove a gas phase due to phase transition. Furthermore, the nickel-rich lithium-transition metal compound having a nickel content of 80% or more in transition metals undergoes a severe decrease in a discharge capacity by a high-voltage application process for removing a gas phase due to phase transition, thereby damaging the intrinsic merits of the high-capacity active material.

Post-treatment method of lithium secondary battery


A flexible hose having an inner tube member made from a thermoplastic elastomer material and an outer tube member made from a non-elastic polyester material. The inner tube member is secured to the outer tube member only at an inlet coupler and an outlet coupler. The inlet coupler is constructed to secure to a water supply provided from a conventional household water spigot. The outlet coupler incorporates a flow restrictor allowing the inner tube member to equalize in pressure with pressurized water received from the water supply. Pressurized water expands the elongated inner tube member longitudinally along a length of the inner tube member and laterally across a width of the inner tube member thereby substantially increasing the length of the hose to an expanded condition wherein the hose contracts to a substantially decreased length when there is a decrease in pressurized water.

Conventional hoses are typically constructed from rubber or other resilient flexible material such as synthetic rubber, thermo plastic rubber or the like photochemical derivatives. A notable problem encountered with conventional garden hoses relates to the storage of the hose when not in use. Garden hoses can be stored on a hose reel, placed within a storage container, or simply left on the ground. While storage devices are practical in certain situations, in many instances the consumer cannot use or has no desire to employ a storage container. For example, a consumer may live in an apartment or small condo and would like to have the benefit of a garden hose for plant watering, car washing, or the like but does not have room for a garden hose storage device. The hose might be left in the trunk of a vehicle or coiled up in the corner of a patio with an effort to consume as little space as possible. Another example would be the owner of a boat, RV or plane who may wish to leave the hose with the vehicle. Such places are impractical for hose storage containers.
There are many situations where it is beneficial to store a hose in as little a space as possible. If the consumer does not have a device for storing the hose then they must try to organize the hose on the ground in a way as to not entangle the hose within itself. If improperly organized, the hose will tend to kink when uncoiled. This problem is typically encountered by the average homeowner who uses the hose infrequently wherein improper storage of a hose can result in the development of kinks. Garden hoses can be made with thick sidewalls to prevent kinking but result in heavy and cumbersome water hoses. Fiber reinforcements can also be used, such as woven tapes or knitting followed by the addition of an outer coating, all of which add to the weight of a garden hose and do not have a shortened length for storage. For this reason, it is of great benefit to have a garden hose that is light in weight, contractible in length, and kink resistant.
Retractable hoses are known to use steel wires formed in a coiled shape with a vinyl tube, the steel wires wind through the vinyl tube so that it will normally be in a coiled or rolled configuration when not in use. When pressurized water is introduced into the hose, the hose is unwound. When the pressurized water is removed, the water hose is recoiled to a rolled position. Examples of such hoses include U.S. Pat. No. 2,814,529; U.S. Pat. No. 3,035,779 and U.S. Pat. No. 3,966,121.
U.S. Pat. No. 6,523,539 discloses a self elongating oxygen hose for stowable aviation crew oxygen mask. The supplemental gas assembly such as used for aircraft crews is provided which includes a mask adapted to fit over at least the nose and mouth of a wearer, together with a flexible, self-elongating hose assembly and a stowage box for receiving the mask and hose assembly.
The transition zone between a garden hose and pressurized source of water, or the garden hose and delivery point, is accomplished by a coupling. Conventional couplings provide a fluid connection between a spigot and a garden hose. However the prior art fails to disclose a coupling capable of attaching to a flexible garden hose having an expandable inner tube member made of a flexible fluid carrying material and an outer sleeve made of a fixed length fabric material. For instance, U.S. Pat. No. 4,895,185 discloses a flexible hose reinforced by armature layers made of flexible cables disposed helically and is attached at least at one end by compression of said layers against rigid pieces, characterized by the supporting elements and gripping elements, which are coaxial, having non-adhesive conical compression surfaces which diverge toward the end and by at least one wedge provided with slits being driven between reinforcing layers to ensure compression. The tubular sleeve is attached to a rigid assembly wherein ends of the layered pairs are engaged in the conical annular space between the coaxial supporting element and gripping elements.
U.S. Pat. No. 5,816,622 discloses a garden hose having a protective shell section and a flexible strain relief section releasably attached to the shell section. The hose is sealably attached to a stem portion of a coupling by a brass ferrule, the manner by which the hose is attached to the stem portion is stated as being well known in the art. After the end of the hose having the ferrule slipped over the stem portion so that the end of the hose abuts the receive portion, a device is inserted into the stem portion for expanding it thereby sandwiching the hose between the stem portion and the ferrule for locking the hose to the coupling.
U.S. Pat. No. 5,894,866 discloses a garden hose assembly having a deformable section that allows a portion of the hose to be coiled around a support for holding the end of the hose in a desired position. Connectors have coupling stems which are inserted within a base tube and such coupling stems are then radially expanded into ferrules or corrugations.
U.S. Pat. No. 6,209,800 discloses a flexible tube formed so that adjacent coils are formed while in a contracted position, the tube is extendible by straightening of the coils. A fitting is formed from an elongate, substantially cylindrical externally barbed portion and a disk shaped head. A bore extends through the fitting which is smaller than the inner diameter of the tubing. The fitting portion is inserted into an end of the tube and held therein by an interference fit with barbs inhibiting removal axially of the tube.
U.S. Pat. No. 6,568,610 discloses a flexible water spray wand for connection to a standard garden hose, having a housing connectable at a lower end to the garden hose and at an upper end to a flexible tube assembly connected at an opposite end to a spray nozzle. The flexible tube has an outlet fitting which comprises an externally barbed portion and an externally threaded portion with an annular shoulder therebetween. The barbed portion fits snugly within outlet end portion of the hose with annular shoulder which abuts an outlet end portion of the ribbed tube, which can be affixed by silver soldering or adhesives.
U.S. Pat. No. 6,948,527 and U.S. Pat. No. 7,549,448 disclose a linearly self-actuated hose for use in transporting fluids. A hose has a biasing spring that extends along the full length, and can comprise single or multiple springs and/or multiple diameter spring coils. The spring is covered with hose cover material on the outside and hose cover material on the inside to form a sealed hose and are bowed inward or outward radially between the individual spring coils depending on the intended use of hose. On the end of the hose is mounted a nozzle end which can be designed with standard garden hose threads. The nozzle end comprises an inner crimp ring, and outer crimp ring which also provides threads, and a water restriction ring. The hose can be trapped between crimp rings to provide a compression fit. Crimp rings are also crimped onto each other so that they form a right unit that will not fall apart during use.
U.S. Pat. No. 6,955,189 discloses a garden hose assembly that includes an elongated and flexible tubular member that includes an open first end, an open second end and a peripheral wall extending between the first and second open ends. A cross-section taken traversely to a longitudinal axis of the tubular member has a generally oblong shape when the tubular member is filled with a fluid and a substantially flattened shape when the tubular member is not filled with a fluid. Male and female couplers are defined as conventional hose couplers.
Therefore, what is needed in the art is a commercial grade flexible hose that can be coupled to a conventional water spigot and will extend in length when water is introduced into the hose and pressurized at an outlet of the hose.

This patent is subject to a terminal disclaimer.


A system includes a managing center transmitting a data stream encrypted by control words included in control messages. The data stream is received by at least one user unit linked to a security module identified by a unique address. The security module contains a credit which is deducted according to the consumption of data from the stream. The security module can deduct the credit of an amount related to a product or an amount related to a duration, this amount and/or this duration being defined in the control message or in a management message. The user transmits to the managing center an identifier identifying the unique address and a value code representing an amount of credit to reload, the managing center dealing with and checking the value code and transmitting an encrypted message having the unique address and the amount to reload the credit with, to the security module.

The present invention concerns the domain of receivers/decoders of conditional access services, in particular an access system to an encrypted data stream calculated by a unit of time.
As an example of such data stream, we mean an information service about the stock exchange, weather forecast, general interest television, a sports event or others. These contents can be broadcasted on user units such as a pay-TV decoder, a computer, a portable phone, a "palm-top", a PDA, a radio, a television, or a multimedia terminal.
The digital stream is encrypted in order to be able to control use and define conditions for such use. This encryption is carried out thanks to control words, which are changed at regular intervals (between 5 and 30 seconds) in order to dissuade any attack aiming to find such a control word.
In order to allow the user unit to decode the stream encrypted by a control word, the latter is sent to it independently of the stream, in a control message (ECM) encrypted by a key suitable for the transmission system between the managing center (CAS) and the security module of the user unit.
In fact, the security operations are carried out in a security module (SC), which is generally in the form of an inviolably reputed microchip card. This unit can be either of a removable type or directly integrated to the user unit dealing with signals such as a paying TV decoder or a DAB receiver. In fact, the functioning of the invention authorizes the use of a user unit without a removable security module.
At the time of decrypting the control message (ECM), it is verified, in the security module (SC), that the right to accede to the considered stream is present.
This right can be managed by authorization messages (EMM), which load such a right into the unit (SC). Other possibilities are also possible such as the sending of decrypting keys.
The accounting of the use of such contents is today based on the principle of subscription, of purchasing events or of paying by time unit.
The subscription allows defining a right associated to one or several diffusion channels and allows the user to obtain these channels unscrambled if the right is present in his security module.
At the same time, it is possible to define rights specific to some contents, such as a film or a football match. The user can acquire this right (purchase for example) and these contents will be specifically managed by this right. This method is known under the denomination "pay-per-view" (PPV).
With regard to payment by the time unit, the security user unit comprises a credit that is debited according to the real consumption of the user. So for example, a unit will be debited each minute to this credit whichever the watched channel. It is possible according to the technical implementations, to vary the accounting unit, either in length, or in value per allowed time, even by combining these two parameters to adapt the invoicing to the kind of transmitted product.
At the time of decrypting the control words, it will be verified if an associated right to access conditions is present in the security module.
The control word is returned in a decrypted form to the user unit only when the comparison is positive.
This way of functioning demands that the managing center knows the user, his physical address, his bank details as well as all the payment traffic which allows him to renew his rights.
In fact, the principle of the subscription is based on the renewal obligation that is to say that a right cancels itself if it is not renewed. This way of proceeding avoids that anyone who subscribes to all the channels available terminates their subscription and arranges it so that the termination message does not ever reach its user unit. That is why such a right includes a time limit and its right for all the channels, if it is not renewed, cancels automatically at the end of a month for example.
One imagines thus the work necessary to follow the thousands of subscribers who regularly settle their invoices and to whom it is necessary to send a renewal message each month. Furthermore, such a message must be repeated for several days because the managing system does not know if the user unit is powered on.
It frequently happens that a user who was on holiday and who had switched off his apparatus finds on his return his user unit blocked. It is then necessary for him to call the managing center so that a personalized renewal message is sent to him.
So, a great part of the resources and the costs connected to the management of a center is allocated to the management of the subscribers.
A first solution using an electronic purse is described in document U.S. Pat. No. 6,282,293. The chip card contains a credit that is debited when an encrypted content is accessed. The accounting information is included in the transmitted signal and allows this accounting. To reload the credit, the user unit calls a managing center in order to send the consumed events and to reload the credit according to the terms agreed with this user, for example through a credit card.
In a large number of cases, on the one hand the user unit has no communication channel towards a managing center and on the other hand, one wish to avoid recording all users in a database with their payment means. Thus, this document do not allow to solve the aims of the invention, namely the creation of a set of user units without back channel and without the knowledge of each unit's owner.


A nonvolatile semiconductor memory comprising: a plurality of memory cell blocks each including a plurality of memory cells serially connected to each other; a word line that is connected to corresponding ones of the plurality of memory cells each included in respective one of the plurality of memory cellblocks; and a pair of drive circuits each configured to apply a voltage to the word line, wherein the corresponding ones of the plurality of memory cells are connected to the word line between the pair of drive circuits.

One embodiment of the invention relates to a nonvolatile semiconductor storage device which is electrically rewritable.
Among nonvolatile semiconductor storage devices are ones that enable electrical rewriting of information, one example of which is disclosed in Patent document JP-A-2005-190665.
Such nonvolatile semiconductor storage devices include ones that are provided with plural memory blocks (NAND cell blocks). Each memory cell block has plural NAND cells. And each NAND cell has plural memory cells, that is, each NAND cell has a series connection of plural memory cells.
The plural NAND cells in each memory cell block are connected together by a word line.
In such nonvolatile semiconductor storage devices, a pair of row decoders is opposed to each other with each memory cell blocks interposed in between. And each of the pair of row decoders is connected to word lines. When a pair of row decoders applies voltages to word lines, the word lines are activated and the memory cell block connected to the activated word lines is driven.

Nonvolatile semiconductor storage device


A motor casing of a driving device has a cylindrical wall portion, a bottom wall portion and a bearing holding portion formed in the bottom wall portion. An electric motor has a stator, a shaft and a rotor. A motor control unit controls operation of the electric motor. A first frame, to which the motor control unit is fixed, is provided between the motor control unit and the bottom wall portion of the motor casing. A first contacting portion is formed in the bottom wall portion and projected toward the first frame. The first contacting portion is in contact with the first frame at a front-side surface of the first contacting portion. A contacting surface area between the motor casing and the first frame is limitedly reduced, to thereby reduce noise caused by vibration. In addition, since a sufficient surface pressure can be obtained, strength of the driving device in its axial direction is increased.

An electric motor is known in the art, according to which a motor control unit is coaxially arranged with the electric motor. In an electric motor, for example, as disclosed in Japanese Patent Publication No. 2010-028925, a motor control unit is attached to a cover member, which is fitted to fitting portions formed on a motor housing so as to coaxially arrange the motor control unit with the electric motor.
In the above prior art (JP 2010-028925), the motor control unit is arranged in the cover member fitted to the motor housing in a faucet joint structure. An axial position of the cover member is positioned by a flanged portion, which is made of a thin metal plate and formed at the motor housing. According to the above structure, mechanical strength in the axial direction of the electric motor is not large.
In a case that the cover member or another member fixed to the cover member is brought into contact with the motor housing at its whole surface area for the purpose of increasing the mechanical strength, it is difficult to uniformly bring the cover member into contact with the motor housing at the whole surface area in view of processing accuracy and so on. As a result, noise may be generated by vibration or the like.


Fuel injection rate shaping is integrated into the pressure intensification stage of a hydraulically actuated fuel injector having a pressure intensifier. In a first embodiment, the pressure intensification plunger is formed of two parts creating a damping chamber therebetween from which fluid is forced out through orifices in a lower one of the plunger parts during an initial phase of displacement of the upper part. Thus, injection will be performed initially at a lower pressure and rate, which increases once the plunger parts make contact. In a second embodiment, a throttled flow is set via a restrictor housing that telescopingly receives the upper plunger part, so that a lower injection rate occurs while fluid is bled off through a restricted flow path between the restrictor housing and the upper plunger part, and a higher injection rate is produced once a port in the upper plunger clears the restrictor housing. In a third embodiment, the two plunger parts of the intensifier have different areas relative to each other. In a fourth embodiment, flow to the intensifier plunger is varied by the intensifier plunger co-acting with a shaped inlet port increasing the effective area of the inlet port through which flow enters the intensifier as the intensifier plunger is displaced during its injection stroke. In a fifth embodiment, a throttling effect produced by a clearance between a protrusion on the intensifier plunger and a receiving bore in the intensifier body is used reduce the intensification effect during the initial phase of injection.

1. Field of the Invention
The present invention relates to hydraulically actuated fuel injectors of the type having a pressure intensifier, and to the use of rate shaping in fuel injectors for obtaining reduced emissions.
2. Description of Related Art
The use of injection rate shaping (i.e., changing of the injection rate during the injection of fuel by a fuel injector into an engine) for reducing NO.sub.x emissions is known. For example, in U.S. Pat. Nos. 4,718,384, 4,627,571, and 3,669,360, injection rate shaping, producing a lower initial rate of injection and a higher subsequent rate of injection, is achieved by varying the pressure acting on a needle valve at the outlet end of the injector so as to initially restrict the extent that the needle valve opens and then allowing it to open to a greater extent for increased fuel flow. However, these arrangements are not in hydraulically actuated fuel injectors having pressure intensifiers and they are limited to use with closed nozzle fuel injectors, i.e., those having a needle valve at the outlet end thereof. Furthermore, if highly pressurized fuel (for example, 15-20 kpsi) is delivered to these injectors, obtaining of a precise flow rate control will be difficult to achieve.
Likewise, known techniques for producing a two stage (preliminary and main injection) process (e.g., U.S. Pat. Nos. 4,601,269 and 3,404,861) as well as for producing an initially restricted flow of fuel followed by an unrestricted flow of fuel to the injector (e.g., U.S. Pat. No. 3,747,857) also possess deficiencies with respect to the supplying of precisely metered quantities of fuel at very high pressures in a way applicable to a variety of different types of injectors.

Hydraulically actuated fuel injector with injection rate shaping pressure intensifier


A winding unit for connecting to a high-voltage grid or network includes a winding embedded in a solid insulating body and a first main connection terminal connected to a first winding end of the winding and disposed on a first support formed on the insulating body. A second main connection terminal is connected to a second winding end of the winding. The winding has partial windings and taps for adjusting the number of windings of the partial windings connected in series. Outgoing lines extending in the insulating body connect the taps to a tap connection terminal accessible from the outside. The tap connection terminals are formed on the support in order to encapsulate the higher voltage in a resin block over the entire periphery by using a shielding cage.

Field of the Invention:
The invention relates to a winding unit for connecting to a high-voltage grid, having a winding which is embedded in a solid insulating body, a first connection terminal which is connected to a first winding end of the winding and is arranged on a first support which is formed on the insulating body, and a second connection terminal which is connected to a second winding end of the winding, wherein the winding comprises partial windings and taps, by means of which the number of series-connected turns of the partial windings can be adjusted, and which are respectively connected, by means of an outgoing line which extends in the insulating body, to a tap connection terminal which is accessible from the exterior.
In practice, a winding unit of this type will be known to a person skilled in the art, wherein the known winding unit is illustrated in an end face view in FIG. 1, and in a sectional side view in FIG. 2. The known winding unit 10 comprises an insulating body which is configured in the form of a resin block 11, in which a higher-voltage winding 12 is arranged. The higher-voltage winding 12 is comprised of a first partial winding 13 and a second partial winding 14, the mutually facing winding ends of which are connected to tap connection terminals 5 or 6 by means of outgoing lines 15 and 16 which extend through the resin block 11, and are contact-connectable from the exterior. Moreover, four further tap connections 17 can be seen, which are likewise connected by means of outgoing lines 18 to the tap connection terminals 3, 4, 7 and 8. Hereinafter, the term "tap connection" describes the location in the winding at which the respective turn thereof is contact-connected with the respective outgoing line 18.
An upper main connection terminal 19 can be seen at the free end of a support 1 which is formed on the resin block 11. A lower main connection terminal 20 is correspondingly configured at the free end of a support 2 which is likewise formed on the resin block 11. In order to interconnect the main connection terminals 19 and 20, it is necessary for two tap connection terminals to be connected to one another. By the connection of the tap connection terminals 5 and 6, the number of series-connected turns of the higher-voltage winding 12 is at a maximum. Connection of the tap connection terminals 4 and 7 results in the series connection of an intermediate number of turns, whereas a connection of the tap connection terminals 3 and 8 results in the series connection of turns, the number of which is comparatively the smallest.
In FIG. 1, the tap connection terminals 3 and 8 are interconnected by means of a terminal strip 21. Accordingly, in the example represented, approximately −5% of the nominal voltage can be tapped off at the main connection terminals 19 and 20. By the connection of the tap connection terminals 3 and 7, the prevailing voltage on the latter would be of the order of −2.5% whereas, by the connection of the tap connection terminals 4 and 6, the voltage which can be tapped off would be of the order of +2.5%.
The known winding unit is handicapped by a disadvantage, in that the outgoing lines 15, 16 and 18 which are centrally routed through the resin block prevent the enclosure of the higher-voltage winding in a shielding cage over its entire periphery. In order to permit the passage of the outgoing lines 15, 16 and 18, the shielding cage would be required to incorporate an opening, as a result of which the shielding effect would be negated.

Winding unit having taps configured on the support


An adjustable fluid flow regulator that can be adjusted for operating at two different operating pressures includes a casing having a chamber therein, an inlet and an outlet communicating with the chamber, and a valve for controlling fluid flow between the inlet and the outlet. A flexible diaphragm in the casing is connected to the valve for operating the valve in response to pressure changes in the chamber. The fluid flow regulator further includes a spring, a removable hollow cap aligned with the spring, and a link adapted to fit in the cap. The link, when installed in the cap, engages the spring to cause the spring to apply a biasing force against the diaphragm that is higher than when the link is not in the cap. According to the method of this invention, the adjustable fluid flow regulator is adjusted for use at two different operating pressures by installing or removing the link from the hollow, removable cap.

Natural gas and L.P. gas are each frequently used in commercial and residential settings. Rather than having equipment that is limited in use to just one type of gas, it is desirable to have equipment that can be used with both types of gas, or at least which can be quickly and safely converted for use with each type of gas. Because natural gas and L.P. gas are typically delivered at different pressures, a number of attempts have been made to make a pressure regulator that is capable of operating in the different pressure ranges typical for the two types of gas. Examples of these attempts include Wolfehope, U.S. Pat. No. 3,128,086; Vicenzi et al., U.S. Pat. No. 3,451,421; Dykzeul et al., U.S. Pat. No. 3,338,264; Bauman U.S. Pat. No. 3,747,629; Murrell, U.S. Pat. No. 3,603,214; Gotthelf, U.S. Pat. No. 5,381,819; Buezis, U.S. Pat. No. 5,435,343. Most of these devices employ a diaphragm member for controlling a valve, and a spring which does not bias the diaphragm during operation at a first pressure, but which is manipulated in some way to engage and thus bias the diaphragm during operation at a second pressure. For example, in Bauman, U.S. Pat. No. 3,747,629, a conversion member is attached in one way so as not to engage a spring and is flipped over and attached another way so as to bias the spring. While of simple construction, this type of device presents the risk that the conversion member can be installed incorrectly.
The principal difficulties with the prior adjustable fluid flow regulators has either been the complexity of their construction and operation, or the risk that the regulator could be inadvertently switched from one mode of operation to the other, which poses the risk of appliance failure.


A system having multiple on-chip logic analyzers (OCLA), each on-chip logic analyzer includes one or more word recognizers. The word recognizer includes a great deal of flexibility for the user, while being capable of implementation with very few gates. The word recognizer includes a Boolean logic portion in which a plurality of conditions can be dynamically segregated into a mutually exclusive set of groups. The conditions in each group are combined by means of a single Boolean function that is programmable. The resultant term (or product) from each group is combined with those of the other groups by a fixed selection of Boolean functions. The output of the Boolean logic section is provided to a counter/timer.

1. Field of the Invention
The present invention relates generally to logic analyzers that are used to facilitate the design of digital logic devices. More preferably, the present invention relates to an on-chip logic analyzer capable of receiving internal state data of a digital logic device, and of selecting a portion of that internal state data for storage in a historical log. Still, more particularly, the invention relates to a word recognizer for an economical on-chip logic analyzer, which permits filtering of internal state data to select information for storage that is of particular interest during debugging operations.
2. Background of the Invention
The design and development of digital logic circuits has become increasingly complex, due in large measure to the ever-increasing functionality offered in such circuits. Integrated circuits are constantly surpassing milestones in performance, as more and more functionality is packaged into smaller sizes. This enhanced functionality requires that a greater number of transistors be included in an integrated circuit, which in turn requires more rigorous testing requirements to insure reliability once the device is released. Integrated circuit designs are repeatedly tested and debugged during the development phase to minimize the number and severity of errors that may subsequently arise. In addition, chips may be tested to determine the performance characteristics of the device, including the speed or throughput of the chip, software running on the chip, or the aggregate performance of the system.
As integrated circuits become more complex, the length of the increases, requiring a greater lead-time before product release. In addition, as the complexity of integrated circuits increase, it becomes necessary to fabricate more prototype iterations of the silicon (or "spins" of silicon) in order to remove successive layers of bugs from the design, thereby increasing the engineering and material cost of the released product. It would be desirable to reduce these engineering and material costs and speed up the product cycle. Moreover, if the most relevant state data was available for analysis by the debugging team, the debugging phase for products could be reduced significantly, thereby minimizing cost, and enabling an earlier product launch.
One of the chief difficulties encountered during the debug phase of a product is identifying the source of an error, and obtaining relevant data regarding the conditions existing at the time of the error. This can be extremely difficult because the error may make it impossible to obtain state information from the integrated circuit. For example, in a processor, an error may cause the processor to quit executing, thus making it impossible to obtain the state data necessary to identify the source of the error. As a result, the debug process often unfortunately requires that the debug team infer the source of the error by looking at external transactions at the time of the error, instead of being able to look at the internal state data. The normal technique for probing external busses is to solder a wire onto a terminal or trace. Unfortunately, merely adding a soldered wire to a terminal or trace can create signal reflections, which may distort the data being monitored. Thus, the manual probing of bus terminals and traces is impractical and inaccurate, especially those attached to high speed, highly complex chips. More sophisticated techniques are also used, but are expensive and suffer, albeit to a lesser degree, from the same effects. Further, because the state information available on these busses is typically a small subset of the processor's state, the debug team must make guesses regarding the state of data internal to the processor. If the internal state of the processor could be acquired and stored, these inferences would be replaced by solid data. By reducing the designer's uncertainty and increasing the available data, this would be beneficial in solving problems with the processor hardware or software.
In certain products under development, such as new microprocessors under development by the assignee of the present invention, the number of transistors is exceedingly large and their dimensions are exceedingly small. Both of these factors make it practically impossible to probe internal terminals of the chip or internal wire traces. Moreover, to the extent that certain internal terminals and traces could be probed, the conventional methods for conducting such a probing operation are extremely expensive, and some might potentially corrupt the state of the terminals and traces being probed. Consequently, the only common technique currently available to test or probe the state of terminals and traces in highly complex chips is to route signals through the chip's external output terminals, to some external interface. This approach, however, suffers in several respects.
First, as noted above, the signals obtained from the external output terminals are removed from the signal states of the internal terminals and traces. Thus, this technique requires the debugging team to infer the state of the internal terminals and traces from signals appearing on an external bus. Second, routing the desired state to external terminals often requires more wiring, silicon, drivers, pads and power than is affordable. Attempts to do so can compromise the normal functioning of the chip. And costs escalate throughout the design, often impacting the micropackaging and system board as well as the die. Third, oftentimes the internal clock rate of the chip operates at a much higher rate than the external logic analyzers that receive and process the data. As an example, processor designs currently under development operate at clock speeds up to and exceeding 2.0 GHz. The fastest commercial logic analyzers, despite their expense, are incapable of operating at GHz frequencies. Thus, either certain data must be ignored, or some other mechanism must be employed to capture the high-speed data being generated on the chip. The typical approach is to run the chip at a slower clock speed so the data can be captured by external test equipment. This solution, however, makes it more difficult to detect the bugs and errors that occur when the chip is running at full clock speeds. Some errors that occur at full clock speed will not be detected when the clock speed if reduced to accommodate the off-chip logic analyzers. Also, increasingly the processor connects to external components that have a minimum speed, below which they will not operate. These speeds require the processor to operate faster than the external logic analyzer can accommodate.
As an alternative to sending data off-chip, attempts have been made to capture certain state data on chip, thereby reducing the problems of interfacing slower speed test equipment with high-speed devices. In the past, to the extent that designers sought to incorporate memory onto the chip for debug and test purposes, dedicated memory devices (usually RAM) were used. Thus, in prior art designs that attempted to capture debug and test information on-chip, a dedicated memory structure was incorporated into the chip design solely to store data for the debug and test modes. The problem with this approach, however, is that it requires the allocation of a significant amount of chip space to incorporate such dedicated memory devices, and these memory devices, while used extensively during the design and development phase of the chip, add little or nothing to the performance of the chip once it is released into production. Thus, the inclusion of dedicated memory space on the chip represents an opportunity cost, and means that functionality and/or performance is sacrificed to include this dedicated memory on the chip. Consequently, the inclusion of memory for debug purposes, while helpful in the debug and test phase, is generally viewed as undesirable because of the accompanying loss of performance and functionality that must be sacrificed. If a dedicated memory device is included on the chip, system designers normally require that such a memory be very small in size to minimize the cost increase (silicon cost is an exponential function of area, and memories are large structures), as well as the performance and functionality loss that accompanies the inclusion of such a dedicated memory. As the size of the dedicated memory becomes smaller, so too does the prospect that the state information stored in the dedicated memory will be sufficient to assist in the debug process. Thus, as the dedicated memory space becomes smaller, so too does the probability that useful debug data will be captured. In relative terms, the largest dedicated on-chip memories typically are incapable of storing very much data.
In assignee's co-pending application entitled Method And Apparatus For Efficiently Implementing Trace And/Or Logic Analysis Mechanisms On A Processor Chip, (Invention Disclosure P01–3848), the teachings of which are incorporated herein, the on-chip cache memory is used to store data from the on-chip logic analyzer. The use of the on-chip cache memory as a storage device for the on-chip logic analyzer permits the storage of a relatively large amount of state data on the chip as compared to previous designs. While the use of the on-chip cache memory greatly expands the amount of state data that can be stored on-chip, the extent of data that can be stored is not limitless. For a processor operating at 2 GHZ, the amount of data that can be stored in a 256 Kbyte cache represents only a few microseconds of data. Consequently, if the OCLA stores all incoming internal state data in the cache, the cache would quickly overflow, and potentially relevant data would be overwritten, or ignored.
External logic analyzers often include a word recognizer that functions a filter to select samples and/or operates as a trigger to start or stop acquisition. The word recognizer usually is implemented as a programmable logic device, which permits a system debugger to input state equations of interest, and the programmable logic device then compares incoming test data for matching state conditions. Internal state data occurring immediately after such a match can then be stored for later analysis. The ability to automatically monitor for certain conditions or events is beneficial because of the huge quantities of information that are generated by complex integrated circuits, and the high clock speeds of those devices. By the time that a user detects an interesting condition and presses a button, a processor may have generated gigabytes of data. The word recognizer thus provides a powerful tool for a system debugger because it permits a historical log to be generated almost instantaneously with the occurrence of a particular condition. More advanced word recognizers may provide selective masking of user-programmed values and counters and timers The ability to have such multi-level word recognizers and counter and timers is important for effective debug of complex logic, such as high-speed processors. Unfortunately, implementing a full-feature word recognizer and associated counters and timers has been viewed as unfeasible on the chip itself because of the large number of wires, logic devices and processing time that such devices would require. Thus, a full-feature word recognizer, capable of implementing arbitrary Boolean equations, typically is viewed as cost prohibitive to include on-chip. The absence of a full-feature word recognizer in existing on-chip logic analyzers makes it much more difficult to debug a design, thus introducing additional time and money to the development of new processors and complex integrated circuits. As an example, a system debugger may want to analyze state data being generated in the chip when certain combination of events occur—such as when a particular software instruction is executing (which can be determined by the address of the executing instructions), and when write transactions are occurring to a particular chip resource. If a device could be implemented that could examine internal state data, and only store state data on-chip when both conditions occur, then highly relevant state data would be available for the system debugger to use in analyzing and correcting the error.
It would be desirable if a system or technique was developed that would permit most of the useful features of a word recognizer to be included as part of an on-chip logic analyzer. It would also be advantageous if an economical, yet powerful, word recognizer could be developed that could be included on-chip without unduly raising the cost of the final product. Despite the apparent advantages such a design would offer, to date no such product has developed.

Efficient word recognizer for a logic analyzer

Hewlett-Packard Development Company, L.P.


A method and structure to optimize computational efficiency in a low-power environment. The method includes determining an optimal point for maximizing computational efficiency in a low-power environment, and selectively controlling operation of at least one processing unit of a plurality of processing units in accordance with the determined optimal point. The structure includes a plurality of processing units, a load manager controlling selective parallel operation of at least one processing unit of the plurality of processing units, and an unregulated power source.

Computational efficiency is defined as a computational rate per available power. Classic design approaches do not always achieve optimal efficiency due to thermal losses of voltage regulation and non-optimal load-matching for variable power sources. Furthermore, the classic design approaches may include components, e.g., voltage regulators, that have a high cost.
In low-power environments, e.g., a solar power environment, not only may the power supply be low, but the power supply may vary as the environmental conditions generating the power vary. For example, the sun may move behind clouds, thus reducing the amount of power generated by a solar cell. Under these conditions, classic design approaches utilize voltage regulation to output a constant voltage, to minimize the variable power of the power source. However, voltage regulation requires the use of voltage regulators, which have a high associated cost. Additionally, voltage regulation has an associated thermal power loss. Power losses, e.g., thermal losses, in low-power environments may be intolerable, as in low-power environments, by definition, there is not much excess power available.
Additionally, classic design approaches do not always achieve optimal efficiency due to non-optimal load-matching for variable power sources. As low-power environments may produce varying amounts of power under different operating conditions, or environmental conditions, non-optimal load-matching may occur. For example, on a day with scattered clouds, a solar cell may produce varying amounts of power as the clouds move in and out between the sun and the solar cell. Classic design approaches may not prevent non-optimal load matching that may occur under these dynamic conditions
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.

Structure and method to optimize computational efficiency in low-power environments

International Business Machines Corporation


A distance measuring method and an apparatus therefor, in which used are first and second pseudo random signals which are equal to each other in pattern but slight different from each other in frequency. A first time-series pattern obtained by multiplying the first pseudo random signal by the second pseudo random signal is generated, laser light intensity-modulated with the first pseudo random signal is radiated to a target, the light reflected from the target is received, and a intensity change of the received reflected-light is converted into an electric signal. A second time-series pattern is obtained by multiplying the electric signal as a reception signal with the second pseudo random signal. The distance to the target is measured by calculating the time difference between the first and second time-series patterns.

The present invention relates to a laser distance measuring method for measuring the distance to a target by using laser light, and relates to an apparatus therefor. In particular, it relates to distance measurement using laser light modulated with a pseudo random signal.
The method of this type for measuring the absolute distance to a target by using laser light has been widely applied to the distance measurement in the field of civil engineering and construction industry. Some Examples are the distance measurement for the prevention of collision with moving substances, the distance measurement as visual information for remote control of robots, the distance measurement for examining the degree of damage or fatigue of refractories in the inside of a convertor or a pouring ladle used in an iron-manufacturing process, etc.
The distance measuring methods using laser light are generally classified into three, namely, a phase comparing method, a pulse modulating method, and a pseudo random signal modulating method. The outline of these methods will be described hereinbelow.
(1) Phase Comparing Method
As the phase comparing method, for example, there is such a method as disclosed in Japanese Patent Unexamined Publication No. Sho-62-75363. This method will be described hereinbelow with reference to FIG. 1.
Laser light emitted from a laser oscillator 21 is distributed into two light paths by a half mirror 27. Laser light on one light path enters into an acoustoopic modulator 22. The acoustooptic modulator 22 generates diffraction light having a frequency shifted by an interaction with a high-frequency signal from a high-frequency oscillator 23. The diffraction light is transmitted to a target 17 via a reflection mirror 44. A detector 43 monitors the diffraction light, that is, laser light. Light reflected on the target 17 enters into a heterodyne detector 40 through a half mirror 28.
On the other hand, laser light on the other light path provided from the half mirror 27 enters into the heterodyne detector 40 through the half mirror 28 to serve as reference light. The heterodyne detector 40 heterodyne-detects a differential frequency signal representing the frequency difference between the reflected wave from the target and the reference light from the half mirror 28. Because the phase of the differential frequency signal is delayed proportionally to the distance to the target, the distance to the target can be measured through the phase detector 42 which detects the phase difference between the reference signal from the high-frequency oscillator 23 and the differential frequency signal.
Because the phase comparing method employs a continuous wave sending system, reflected light from the target cannot be discriminated from unnecessary light, such as reflected light, leakage light, etc. from other places than the target, so that a large error may arise. In particular, when sensitivity is so high that weak reflected light can be detected, weak leakage light from an optical system related to radiation laser light may be detected by an optical system related to reception of light and may be superposed on the reflected light from the target to interfere therewith to thereby bring phase disorder, resulting in a large error.
(2) Pulse Modulating Method
For example, a pulse modulating method has been described in Japanese Patent Unexamined Publication No. Sho-58-76784. The method will be described hereinbelow with reference to FIG. 2.
Laser light from a laser oscillator 21 is distributed into two light paths by a half mirror 27. Light on one light path enters into an acoustooptic modulator 22 driven by a high-frequency oscillator 23. In the acoustooptic modulator 22, laser light is modulated to diffraction light having the frequency shifted. The diffraction light is passed through a slit 29, converged by a lens 54 and then enters into a light modulator 24. In the light modulator 24, the incident laser light is pulse-modulated with a pulse signal from a pulse generator 50. The pulse-modulated laser light is passed through a transmission optical system 11 and radiated toward a target 17. The reflected wave from the target 17 is passed through a reception optical system 12 and a half mirror 28 and enters into a light detector element 25.
Laser light on the other light path from the half mirror 27 is reflected on the half mirror 28 and then enters into the light detector element 25 so as to serve as reference light. The light detector element 25 heterodyne-detects the pulse-like reflected wave from the target 17 on the basis of the reference light to thereby generate a differential frequency signal pulse waveform representing the frequency difference between the reflected light and the reference light. The differential frequency signal pulse waveform is amplified by an intermediate-frequency amplifier 51 and then detected by a detector 52 so as to be a detection pulse waveform.
Because this detection pulse waveform is delayed by the propagation time of the laser light required for reciprocating the distance to the target, an information processing circuit 53 calculates the distance to the target 17 by measuring the time difference between a point of time when a pulse is generated by the pulse generator 50 and a point of time when the detection pulse waveform is obtained by the reception of the reflected light from the target 17.
Because the pulse modulating method uses an intermittent wave transmitting system, the reflected light from the target can be timely discriminated from unnecessary light reflected from obstacles even though such unnecessary light reflected from obstacles is present. In the pulse modulating method, however, not only is power of pulse-like light small on an average but the peak power of laser light to be transmitted is restricted because of problems of device configuration and safety. Accordingly, when the target is low in light reflectivity, the distance to the target cannot be measured. Therefore, when the target is low in light reflectivity, for example, a reflection tape having a large number of fine reflection substances on a surface thereof may be stuck to the target to increase the quantity of reflected light. However, the process for sticking such a reflection tape to the target is complex.
(3) Pseudo Random Signal Modulating Method
For example, a pseudo random signal modulating method has been described in Japanese Patent Unexamined Publication No. Sho-58-166281. This method will be described hereinbelow with reference to FIG. 3.
In a modulator 24, laser light generated by a laser oscillator 21 is subjected to intensity-modulation with a pseudo random signal generated by a pseudo random signal generator 60. The modulated laser light is radiated toward a target 17. Light reflected on the target 17 is received by a light detector element 25 and converted into an electric signal. Here, the waveform of the electric signal is stored in a high-speed storage device 62. In a delay correlation device 61, the correlation between the pseudo random signal generated by the pseudo random signal generator 60 and the reception pseudo random signal stored in the high-speed storage device 62 is calculated while delaying the pseudo random signal successively. The result of the correlation processing is given to a display recorder 63.
Because the phase of the pseudo random signal received as reflected light from the target 17 is delayed by the propagation time of light to the target 17, the correlation between the two signals is increased when a delay for the propagation time is given to the phase of the pseudo random signal generated by the pseudo random signal 60 so as to be used as a transmission signal. Accordingly, the distance to the target can be measured by measuring the delay time which maximizes the correlation.
Because the pseudo random modulating method uses a continuous wave transmitting system, the reflected wave from the target can be discriminated from the reflected wave from obstacles on the basis of the delay time for correlation processing even though such unnecessary reflected wave from obstacles is present. However, the pseudo random modulating method is complex in apparatus configuration and long in signal processing time. Specifically, the high-speed storage device and the delay correlation circuit may be constituted by analogue circuits or may be constituted by digital circuits. In the former case, the number of elements used is so large that the apparatus becomes complex in configuration. In the latter case, the operation processing is so complex that the processing speed becomes slow.

Distance measuring method and apparatus therefor


A night vision device having a power supply which delivers a high voltage level to its microchannel plate (MCP) through a variable resistance device. The voltage to the MCP is monitored and used to control the resistance to the variable resistance device such that the voltage on the MCP remains substantially at an established level, notwithstanding variations in the current being drawn by the MCP.

Even on a night which is too dark for diurnal vision, invisible infrared light is richly provided by the stars. Human vision cannot utilize this infrared night time light from the stars because the so-called near-infrared portion of the spectrum is invisible for humans. A night vision device of the light amplification type can provide a visible image replicating the night time scene. Such night vision devices generally include an objective lens which focuses invisible infrared light from the night time scene onto the transparent light-receiving face of an I.sup.2 T. At its opposite image-face, the image intensifier tube provides an image in visible yellow-green phosphorescent light, which is then presented to a user of the device via an eye piece lens.
A contemporary night vision device will generally use an I.sup.2 T with a photocathode behind the light-receiving face of the tube. The photocathode is responsive to photons of infrared light to liberate photoelectrons. These photoelectrons are moved by an electrostatic field to a microchannel plate (MCP) having a great multitude of dynodes, or microchannels, with an interior surface substantially defined by a material having a high coefficient of secondary electron emissivity. The photoelectrons entering the microchannels cause a cascade of secondary emission electrons to move along the microchannels so that a spatial output pattern of electrons which replicate an input pattern, and at a considerably higher electron density than the input pattern results. This pattern of electrons is moved from the microchannel plate to a phosphorescent screen by another electrostatic field to produce a visible image.
A power supply for the I.sup.2 T provides the electrostatic field potentials referred to above, and also provides a field and current flow to the microchannel plate(s). Conventional night vision devices (i.e., since the 1970's and to the present day) provide automatic brightness control (ABC) and bright source protection (BSP). ABC maintains the brightness of the image provided to the user substantially constant despite changes in the brightness (in infrared and the near-infrared portion of the spectrum) of the scene being viewed. BSP prevents the I.sup.2 T from being damaged by an excessively high current level in the event that a bright source, such as a flare or fire, comes into the field of view.
The current drawn by the MCP varies as a function of the average brightness of the image. The output impedance of the power supply for most MCPs is also quite high. As a consequence, the voltage applied to the MCP will vary as a function of average image intensity, unless the voltage to the MCP is regulated.
The voltage delivered to the MCP is also often adjusted to obtain a desired amount of ABC and BSP. For bright image intensities, for example, it is often desirable to reduce the voltage to the MCP.
The conventional method of developing the high voltage needed to drive a MCP has been to generate an oscillating signal from the electricity supplied by a DC battery, to feed that oscillating signal into a step-up transformer, and to direct the output of the transformer into a voltage-multiplying circuit. The output of the voltage-multiplying circuit is then delivered to the MCP.
The conventional method of regulating the voltage to the MCP has been to sense the voltage on the MCP, to generate an error if the voltage on the MCP is other than as desired, and to direct that error into a circuit which adjusts the amplitude of the high voltage AC waveform that is rectified and multiplied by the multiplier to correct for that error.
This conventional approach, however, has several drawbacks. One drawback is that it usually requires the use of a separate transformer to generate and control the amplitude of the voltage delivered to the MCP. Because the power supply for the typical night vision device must also generate and control voltages for other segments of the system, this generally requires the power supply to have several transformers. This multiplicity of transformers increases costs, reduces reliability, and reduces overall power supply efficiency.
Another problem with this type of prior art feedback system is that the reactance, in the transformer often causes the response of the system to be slow and unstable.

Night vision device having series regulator in power supply for MCP voltage control


An attachment for a weight stack type exercise machine to pull the weight stack down while it is being lowered, so that the eccentric exercise force required to lower the stack is greater than the concentric exercise force required to raise it. Such asymmetric exercise forces more closely match muscle strengths, which are normally greater for eccentric exercise than for concentric exercise. The attachment has an electric motor and a control unit including a keypad, a display and a microcontroller. The motor is coupled to the weight stack by an eccentric force control cable. The keypad allows the user to select the amount of force added during the eccentric phase of exercise, when the weight stack is moving down and part of a lifting cable connected to a handle or engageable member on the weight stack type machine is moving in. A sensor enables the controller to determine whether the weight stack is moving up or down. As the weights in the stack are being raised, no significant force is generated by the motor and eccentric force control cable. As the weights are being lowered, an amount of additional (i.e. in addition to gravity) eccentric force selected by the user via the keypad is applied to the weight stack by the motor via the eccentric force control cable.

This invention relates to a device especially suited for, but not limited to, use as an attachment to a weight stack type exercise machine, for generating greater exercise resistance when the weight stack is moving in one direction (corresponding to eccentric muscle movements) than when the stack is moving in the opposite direction (corresponding to concentric muscle movements).
Weight stack type exercise machines have a stack of weights with a pin or other device to connect a selected number of the weights to one end of a lifting cable, the other end of the lifting cable being connected through one or more pulleys to a handlebar, pivotally mounted leg bar, or other movable member for engaging part of the body. Large numbers of such machines are currently in use.
Such conventional weight stack type exercise machines require the user exert the same amount of force to gradually lift the weight stack as to gradually lower the weight stack. During the weight stack lifting phase of an exercise the muscles involved contract or shorten, involving concentric muscle movements; whereas during the weight stack lowering phase the muscles involved lengthen, involving eccentric muscle movements.
Therefore such conventional weight stack type exercise machines are limited to presenting the same resistance to eccentric muscle movements as to concentric muscle movements.
However, muscles can generate significantly greater force during eccentric (muscle lengthening) exercise motions than during concentric (muscle shortening) exercise motions.
This difference between concentric and eccentric movements has been recognized, and various approaches have been taken to provide increased resistance during eccentric movements.
In one approach athletes work out in pairs on weight stack type and other exercise machines, or simply by lifting weights without a machine. The person who is exercising raises and lowers the weights. The second person either assists during the concentric phase or presses down on the weight to add force during the eccentric phase.
Machines are known in the art which are capable of applying greater forces during eccentric movements than the forces applied during the opposite, or concentric movements. Such machines are relatively complex and expensive, and have not been well accepted.
In FIGS. 5 and 6 of U.S. Pat. No. 5,011,142 to Eckler entitled Exercise Control System, a weight stack 88 is supported by a piston rod 76 of a pneumatic cylinder 92, the piston rod being connected to a double acting piston 90 within the cylinder. A bidirectional valve 60 controls the air pressure supplied to the upper and lower surfaces of the piston 90, to add or subtract resistance to the exerciser's effort to raise or lower the weight stack 88. This arrangement, however, is unduly mechanically complex and limited by piston stroke length; and cannot readily be incorporated in existing weight stack type exercise machines.
U.S. Pat. No. 5,015,926 to Casler, entitled Electronically Controlled Force Application Mechanism For Exercise Machines, does not utilize a weight stack, but rather employs a continuously running DC motor, the motor being coupled to an exercise member via a variable torque magnetic particle clutch controlled by a microprocessor to vary the exercise resistance in response to the exercise force, speed and direction of motion. This system is mechanically complex and not suited for incorporation in existing weight stack type exercise machines.
U.S. Pat. No. 4,765,613 to Voris, entitled Progressive Resistance Exercise Device, provides progressively increasing exercise resistance in the (concentric) exercise direction, while reducing the resistance to zero in the opposite (eccentric) direction.
U.S. Pat. No. 5,117,170 to Keane et al., entitled Motor Control Circuit For A Simulated Weight Stack, employs a DC motor to simulate a weight stack, providing exercise resistance which is electrically controllable.
U.S. Pat. No. 5,133,545 to Moschetti et al., entitled Progressive Accommodating Resistance Exercise Device, has cables which can be pulled by the user in order to exercise. FIG. 6 of this reference shows a drum 158 around which is wound a cable 162, with a governor and friction brake mechanism for varying the resistance presented to rotation of the drum as the cable winds on or unwinds from the drum. The faster the cable is pulled, the faster the governor spins and the harder it presses on the brake.
Other references of interest are:
______________________________________ U.S. Pat. No. Inventor Title ______________________________________ 3,912,261 Lambert, Sr. Exercise Machine 4,511,137 Jones Compound Weight Lifting Exercising Machine 4,609,189 Brasher Operator Controlled Variable Force Exercis- ing Machine 4,623,146 Jackson Exercise Machine 4,650,185 Cartwright Exercise Machine With Improved Load Varying Arrangement 4,846,466 Stima, III Microprocessor Control- led Electro-Hydraulic Exercise System 5,037,089 Spagnuolo Exercise Device Having et al. Variable Resistance Capability 5,106,081 Webb Leg Exercise Machine 3,869,121 Flavell Proportioned Resistance Exercise Servo System 4,261,562 Flavell Electromagnetically Regulated Exerciser ______________________________________
None of the aforementioned references is capable of, or suitable for installation on existing weight stack type exercise equipment at reasonable cost without limiting the range of movement of the weight, so as to provide eccentric resistance which is adjustably greater than the concentric resistance of the equipment.
Accordingly, an object of the present invention is to provide apparatus suitable for use as an attachment to a weight stack type exercise machine, for generating greater exercise resistance in one direction (corresponding to eccentric muscle movements) than in the opposite direction (corresponding to concentric muscle movements).

Asymmetric force applicator attachment for weight stack type exercise machines