Systems and methods for encoding and decoding are disclosed. The systems and methods include multimedia decoder instantiation systems and multimedia processing engines which are capable of being upgraded or reconfigured to support a new or previously-unsupported compression format, without the need for platform-specific software or hardware upgrades.

1. Field
The present technology relates to systems and methods of encoding and decoding audio, video and other multimedia data. More particularly, the technology relates to computer architecture and operating methods that can allow for reconfiguration of a multimedia decoder without interrupting multimedia playback.
2. Description of the Related Art
Digital multimedia capabilities can be incorporated into a wide range of devices, including digital televisions, digital direct broadcast systems, wireless communication devices such as radio telephone handsets, wireless broadcast systems, personal digital assistants (PDAs), laptop or desktop computers, digital cameras, digital recording devices, video gaming devices, video game consoles, and the like. Digital multimedia devices implement video encoding techniques, such as MPEG-2, MPEG-4, or H.264/MPEG-4, Part 10, Advanced Video Coding (AVC), in order to store, transmit, and receive digital video efficiently. Digital devices implement audio encoding techniques or formats such as AAC, MP3, and WAV to store, transmit, and receive digital audio efficiently. Digital devices further implement additional data and graphics encoding techniques or formats such as IGES, 3DT, PS, MNG ODF and SVG
Encoding is predominantly proprietary or standards-based. Accordingly, multimedia is generally encoded in a fixed format. While current methods may provide some adaptation to changes in characteristics such as content, this adaptation is limited, e.g., in the case of video to the selection between a handful of modes in H.264/AVC. In existing protocols, there is no true content adaptation; once a standard is fixed, modification to the coding algorithms or data tables is not permitted. Further, devices that incorporate digital multimedia capabilities generally must conform to these standards. As a result, these devices have fixed decoders that are configured to decode only multimedia encoded in the fixed format(s). Selection between pre-determined formats, e.g. MPEG-2, MPEG-4, and H.263, has been suggested as in U.S. Pat. No. 7,085,320 and US Patent Application 2003/0182544. Similarly, utilization and selection between scalable coding layers within standards at the encoder was suggested in U.S. Pat. No. 6,553,072 and a corresponding decoder proposed. In these cases the utilized formats and their components are known at the encoder and the decoder. Hence there is still no true content adaptation, since the characteristics of the coding algorithms are fixed by the pre-determined coding formats.
In certain instances, it would be beneficial to utilize encoding or decoding algorithms generated based on the content to be encoded or parameters of the system, as doing so may more efficiently encode or decode multimedia data. However, decoders in devices for receiving such encoded multimedia data may not be configured to decode content encoded using such generated encoding methods. This lack of configuration may be due to reasons such as a limit on the number of decoders able to be implemented in a device, no support for legacy decoders, and no support for new encoders. Solutions to this problem have been explored by permitting either selection between sub-algorithms or codec components or reconfiguration of portions of the decoder. FIG. 1(a) illustrates selection between known decoder sub-algorithms or elements. Various selection strategies and targets have been suggested, such as variable-length decoder tables as in US Patent Application 2004/0028141 or code rates, interleaving techniques, and error control techniques as in U.S. Pat. No. 5,666,170. Alternatively, FIG. 1(b) illustrates reconfiguration of decoder elements in hardware or software in response to control signals. Reconfiguration can be performed via methods such as dynamically interconnecting elements such as in US Patent Application 2003/0182544, US Patent Application 2011/0032985, and US Patent Application 2008/0130742. Further reconfiguration methods are to dynamically reconfigure portions of decoder processes or elements, such as adder arrays as in US Patent Application 2008/0130742 and caches as in US Patent Application 2007/0064006. In U.S. Pat. No. 7,385,532 a purely hardware decoder is reconfigured in response to bitstream commands.
Alternatively, software configuration or reconfiguration of portions of the decoder in response to configuration commands has been proposed. These have been predominantly toolbox-based. FIG. 2 shows a system from U.S. Pat. No. 5,987,181 which illustrates that a set of tools is known to both the encoder and decoder each of which can draw upon this set. The choice of tools used at the encoder is then transmitted to the decoder and the decoder reconfigures based upon the tools in the local toolbox. A similar solution was proposed in O. Avaro, P. A. Chou, A. Eleftheriadis, C. Herpel, C. Reader and J. Signès, "The MPEG-4 Systems and Description Language: A Way Ahead in Audio Visual Information Representation" and then more recently implemented in the MPEG Reconfigurable Video Coding (RVC) initiative as discussed in S. Lee, E. S. Jang, M. Mattavelli, C.-J. Tsai, "Working Draft 5 of ISO/IEC 23001-4: Codec Configuration Representation", ISO/IEC JTCI/SC20/WG11 document N9223 and E. S. Jang, J. Ohm, and M. Mattavelli, "Whitepaper on Reconfigurable Video Coding (RVC)", ISO/IEC JTCI/SC20/WG11 document N9586. The RVC decoder solution is illustrated in FIG. 3. Although only the decoder will be specified when then standard is developed, a set of toolboxes is available to both the encoder and decoder. The decoder constructs a model from the indicated tools, called functional units, by accessing the toolbox, and then instantiates a decoder by linking the selected functional units to the current decoder. This use of set toolboxes or tool libraries is further discussed in US Patent Application 2011/0032985 and well as in U.S. Pat. No. 7,385,832.
Reconfiguring a single sub-algorithm without the use of a toolbox at the decoder was proposed in M. Bystrom, I. Richardson, S. Kannangara, and M. de-Frutos-Lopez, "Dynamic Replacement of Video Coding Elements" and in C. S. Kannangara, J. Philp, I. Richardson, M. Bystrom, and M. de-Frutos-Lopez, "A Syntax for Defining, Communicating, and Implementing Video Decoder Function and Structure". In these cases, the single element, a backwards transform, was encoded and transmitted to the decoder where it replaced the existing backwards transform either through the well-known binary patching method or code replacement and just-in-time compilation.


A GePD having uniform sensitivity in C and L bands is provided and a photodetector in which deterioration of a common-mode rejection ratio is curbed is provided. A photodetector according to an embodiment includes one or a plurality of sets of two photodiodes to which a differential signal is input, a monitor connected to each of the two photodiodes and configured to measure a photocurrent, and a voltage supply configured to control a voltage applied to each of the two photodiodes, and the voltage supply controls the voltage applied to each of the two photodiodes so that the photocurrent measured by the monitor connected to one of the two photodiodes is equal to the photocurrent measured by the monitor connected to another one of the two photodiodes.

With the spread of optical communication in recent years, there is a demand for cost reduction of optical communication devices. As one of solutions thereto, a method of forming an optical circuit constituting an optical communication device on a silicon wafer having a large diameter using a micro optical circuit technique based on silicon photonics is known. Thus, a material cost per chip can be dramatically reduced, and a cost of the optical communication device can be reduced. A photodetector formed on a silicon (Si) substrate using such a technique includes a germanium photodiode (GePD) capable of monolithic integration.
FIG. 1 illustrates a structure of a waveguide-coupled vertical GePD of the related art. FIG. 2 is a cross-sectional view taken along a reference sign II-II of FIG. 1. A vertical GePD 100 is formed on a silicon on insulator (SOI) substrate including a Si substrate, a Si oxide film, and a surface Si layer using a lithography technique or the like. The vertical GePD 100 includes a Si substrate 101, a lower clad layer 102 formed of a Si oxide film on the Si substrate, a core layer 110 that guides signal light, a Ge layer 114 that absorbs light formed on the core layer 110, and an upper clad layer 103 formed on the core layer 110 and the Ge layer 114. The core layer 110 is divided into a waveguide layer 141 and a silicon slab 142.
In the silicon slab 142, a p-type Si slab 111 doped with impurity ions having a first conductivity type and silicon electrode portions 112 and 113 doped with impurity ions having a first conductivity type at a high concentration and acting as electrodes are formed. The Ge layer 114 is stacked by epitaxial growth, and a Ge region 115 doped with impurity ions having a second conductivity type is formed on the Ge layer 114. The Ge layer 114 may be of a germanium compound. Electrodes 116 to 118 are included on the silicon electrode portions 112 and 113 and the Ge region 115, respectively, to come into contact with the silicon electrode portions 112 and 113 and the Ge region 115.
In order to make a structure easy to understand, the clad layer 103 is omitted and only positions at which the electrodes 116 to 118 come into contact with the silicon electrode portions 112 and 113 and the Ge region 115 are shown in FIG. 1.
In the vertical GePD 100, when light is incident on the silicon slab 142 from the waveguide layer 141 and is absorbed by the Ge layer 114, a photocurrent flows between an electrode 117 and the electrodes 116 and 118. The light is detected by detecting this photocurrent.
FIG. 3 illustrates a first example of a waveguide-coupled horizontal GePD of the related art. The horizontal GePD 100 includes a germanium region 121 doped with impurity ions having a first conductivity type and a germanium region 122 doped with impurity ions having a second conductivity type, instead of the p-type Si slab 111 and the Ge region 115 illustrated in FIG. 2.
FIG. 4 illustrates a second example of a waveguide-coupled horizontal GePD of the related art. The horizontal GePD 100 includes a silicon region 131 doped with impurity ions having a first conductivity type, a silicon region 132 doped with impurity ions having a second conductivity type, and a silicon electrode portion 133 doped with second impurities at a high concentration and acting as an electrode, instead of the p-type Si slab 111 and the Ge region 115 illustrated in FIG. 2.
FIG. 5 illustrates temperature and wavelength dependent characteristics of sensitivity of a GePD of the related art. The GePD of the related art has characteristics that temperature characteristics of sensitivity are not constant. Here, the sensitivity is a characteristic of a current output with respect to optical input power, and has units of A/W. FIG. 5 is a diagram obtained by plotting sensitivity to temperature in a C band and an L band (wavelengths 1530 to 1565 nm and 1565 to 1625 nm, respectively) of a communication wavelength band when a reverse bias of 1.6 V is applied to a GePD. For example, the sensitivity at 31° C. is substantially constant up to the vicinity of the C band, but the sensitivity decreases in the L band. This change in sensitivity is caused by a change in a light absorption spectrum of germanium. At −5° C., the sensitivity tends to decrease even in the C band.
FIG. 6 illustrates temperature dependent characteristics of the light absorption spectrum of Ge. A horizontal axis indicates photon energy, and a vertical axis indicates a square root of an absorption coefficient (see, for example, Non Patent Literature 1). When a temperature becomes low, a bandgap of the germanium shifts to the high energy side. That is, an edge of the light absorption spectrum shifts to a short wavelength side. The edge of the light absorption spectrum of germanium that is used for a GePD is just around 1565 nm on the long wavelength side of the C band at 31° C. Therefore, even when a GePD shows constant sensitivity over the entire C band at 31° C., the sensitivity gradually decreases from the long wavelength side as the temperature decreases. This tendency is illustrated in FIG. 5 and the sensitivity tends to decrease at −5° C., which is a low temperature, when the wavelength becomes longer.
In order to incorporate a GePD the sensitivity of which changes depending on the temperature and the wavelength into an optical communication system, a circuit that compensates for change in sensitivity is required, which increases a manufacturing cost. A means for solving this includes a means for controlling a voltage that is applied to a GePD according to the temperature and the wavelength (see, for example, Patent Literature 1).
On the other hand, in a photodetector in an optical communication system or an optical information processing system, using GePDs, a single GePD is rarely used and about 2 to 8 GePDs are generally used side by side. This is because a system adopting a wavelength division multiplexing (WDM) scheme using multiple wavelengths requires as many GePDs as the number of wavelengths, and a system adopting an optical digital coherent communication technology uses as a balanced PD.
FIG. 7 illustrates an example of a configuration of a receiver that is used in the optical digital coherent communication technology. The receiver is a dual-polarization multiplex quadrature phase shift keying (DP-QPSK) receiver, and received light is separated into two orthogonal polarized waves by a polarized wave separator 11. In optical hybrids 13a and 13b, the two polarized waves are caused to interfere with local light from a local light emitting source 12, intensity and phase information is detected, and two sets of differential signals are converted to electrical signals by four GePDs 14 and 15. In such a receiver, when temperature control is performed, it is necessary for a heater to be included in each of the GePDs 14 and 15. In particular, because the GePDs connected to the same optical hybrid receive differential signals in pairs, the paired GePDs are required to have uniform sensitivity.

NIPPON TELEGRAPH AND TELEPHONE CORPORATION


An ion implanter including an ion beam generator for irradiating an ion beam toward a rotary drum having a front surface with a number of substrates fixed and equally spaced circumferentially thereof. The rotary drum is supported for rotation and reciprocation so that the substrates are exposed in succession to the ion beam. A plurality of surface potential sensors are positioned adjacent the front surface of the rotary drum. The surface potential sensors are positioned at different angular distances with respect to the ion beam for generating surface potential signals in response to surface potentials on the respective substrates. The surface potential sensors may be positioned on a line extending in a direction of reciprocation of the rotary disc for producing surface potential signals in response to surface potentials at different positions on each of the substrates.

This invention relates to an ion implanter of the type rotating a rotary disc with a number of substrates fixed thereon to expose the substrates in succession to an ion beam.
Ion implanters have been used in producing semiconductor devices or liquid crystal display (LCD) devices. A conventional ion implanter includes a rotary disc having a number of substrates fixed thereon. During ion implantation, the rotary disc is rotated and reciprocated to expose the substrates in succession to an ion beam. Positive charges are induced in the substrate surface exposed to the ion beam. If the positive charges are accumulated to an excessive extent, a crack or a dielectric breakdown will occur in the substrate surface. In order to avoid such crack or dielectric breakdown, it is required to monitor the charge-up phenomenon in terms of the charges accumulated in the substrate surface by measuring the surface potential during the ion implantation. However, the conventional ion implanter employs a single surface potential sensor and cannot measure the surface potential with high accuracy.

Ion implanter with plural surface potential sensors


A storage device includes: a read/write mechanism which is actuated in accordance with a selected one of two or more sets of control data so that a read/write operation is carried out to read data from or write data onto a recording medium; a detection unit for detecting a source voltage from a host system, and for detecting whether one of source voltages from the host system has been switched to another source voltage; a control unit for controlling the read/write operation of the read/write mechanism in accordance with the detected source voltage; and a reset unit for resetting the control unit to an initial condition when the switching from the one of the source voltages to the another source voltage is detected as being in process, so that the controlling of the read/write mechanism is withheld until the end of the switching.

(1) Field of the Invention
The present invention generally relates to a storage device, and more particularly to a storage device in which a source power is supplied from a power supply of a host system and an access is sent from the host system to read data from or write data onto a recording medium within the storage device.
(2) Description of the Prior Art
Storage devices such as magnetic disk drives have been connected to host computers for a purpose of storing information. Recently, a computer system in which a storage device is connected as the external storage having a smaller size and a lighter weight has been developed and put into practical use. In addition, a small-size computer system including such a small-size storage device is powered by a battery, instead of by being plugged into an electric outlet.
Generally, the magnetic disk drives are provided with a read/write mechanism which includes a SPM (spindle motor) used to rotate a magnetic disk and a VCM (voice coil motor) used to move a magnetic head. This read/write mechanism is actuated by using a source power supplied from the battery-powered host computer, so that a read/write operation is carried out to read data from or write data onto a magnetic disk within the magnetic disk drive.
The battery-powered host computer mentioned above supplies the source power to the external devices, including the storage device, which are connected to the host computer.
In the above storage device which is connected to the battery-powered host computer, when the source power supplied from the host computer is varied, an electric current flowing through the read/write mechanism is also varied. If the remaining quantity of electric power contained in the battery is small, the source voltage supplied to the storage device becomes low and the electric current through the read/write mechanism becomes too small to carry out a read/write control procedure.
When the source power supplied from the battery to the read/write mechanism is low, the storage device will lack sufficient electric energy to start or continue the rotation of the VCM or the SPM of the read/write mechanism. When the storage device lacks a sufficient supplied source power, it is impossible to carry out a seek control procedure of the VCM on the read/write mechanism, for example, in accordance with seek control data.
Japanese Laid-Open Patent Application Nos.5-137393 and 5-258488 disclose a VCM speed control of a storage device, proposed as an optimum VCM speed control, wherein one of predetermined source voltages (e.g., 3 V and 5 V), supplied to the storage device, is selected by detecting a change in the source voltage from the host computer. In the storage device disclosed in the above publications, a VCM speed control procedure of the read/write mechanism is carried out in accordance with control data of a VCM speed control table related to the selected source voltage.
Generally, a rated quantity of source power is supplied to the magnetic disk drive. However, the host computer may not recognize a consumption power actually used by the magnetic disk drive. When the remaining quantity of electric energy contained in the battery of the host computer is small, a warning related to the lack of electric energy in the battery is displayed on the host computer. When the remaining quantity of the electric energy contained in the battery is smaller than a lower electricity limit that allows the host computer to normally run, the operations of the host computer and the storage device are stopped.
In the case of the conventional storage device mentioned above, one of the predetermined source voltages, supplied to the storage device, is selected by detecting a change in the source voltage from the host computer, and a switching of one of the source voltages to another source voltage is abruptly performed. There is a problem that the contents of a register of a control unit of the host computer or data stored in a memory of the host computer might be changed at random or completely lost due to the abrupt switching of the source voltage. In addition, noises might be produced due to the abrupt switching to cause a read/write error or another malfunction of the storage device.
In the case of the above conventional storage device, when the remaining quantity of electric power contained in the battery of the host computer becomes small, the storage device might be unable to continue to run a normal operation. The conventional storage device under such a condition has a problem that data which is to be written onto the recording medium abnormally resides on a memory of the host computer due to the lack of electric power contained in the battery. In addition, there is a problem that the conventional storage device is not capable of performing a reduced consumption power mode when the remaining electric power of the battery is small.

Storage device in which read/write operation is controlled in response to source voltage


A lighting system is provided whereby long operating life can be reasonably ensured by taking into account requirements of the application, characteristics of the LEDs, characteristics of the fixture containing said LEDs, the desired number of operating hours, and—via developed relationships—taking an iterative approach to supplying power to the LEDs. Through the envisioned compensation methodology and effective luminaire design, a relatively constant light level can be assured for a predetermined number of operating hours (possibly longer); this is true even if operating conditions change, known behavior of LEDs proves untrue over untested period of time, or some other condition occurs which would otherwise cause end-of-life prematurely and prevent the system from meeting the desired number of operating hours.

The present invention generally relates to light-emitting diodes (LEDs), and more particularly, to the design of a lighting apparatus and lighting system using such in a manner that maximizes the benefits of LEDs to satisfy difficult lighting requirements.
By now it is well known that the use of LEDs in general lighting applications yields substantial benefits: long operating life, high efficacy, and precise control of light are at the forefront. However, it is also well known that to get the most out of LEDs a number of factors must be considered: temperature (both ambient and junction) and luminaire design, for example. LEDs are quickly becoming the light source of choice for architectural or aesthetic lighting applications (e.g., façade lighting, holiday lighting, indoor track lighting, etc.), but their usefulness in long-term, large-scale lighting applications has been more slowly realized. This is due, at least in part, to the tremendous efforts needed to control such things as ambient and junction temperature, as well as the efficiency of the luminaire design. In essence, because the benefits of operating LEDs are so closely coupled to the particulars of the lighting application, there is no such thing as a standard large-scale LED lighting fixture. Couple this with only a rudimentary understanding the industry has of how long LEDs can be operated effectively, and it can be seen that there is significant room for improvement in the art.
Consider an outdoor bridge spanning some length and accommodating some number of lanes of traffic in both directions; assume this bridge is used heavily both day and night. For the safety of nighttime drivers, the road on the bridge must be illuminated; here lies an application that exemplifies the challenges faced by today's lighting designers. Cost effectiveness suggests lighting fixtures should be affixed to existing structural features (e.g., to avoid the cost of support structures and the cost to shut down multiple lanes of traffic to erect said structures); however, mounting height and aiming of said fixtures must be considered so not to cause glare or create other adverse driving conditions (the difficulty of which is exacerbated because traffic flows in both directions). The lighting designer must take into account placement of the fixtures, weight of the fixtures, and outward design of the fixtures to ensure both adequate distribution of light on and about the target area, and distribution of stresses on the poles (e.g., because of wind loading). At all times, there are competing design considerations. For example, LEDs offer the benefit of long life (a boon to cost effectiveness), but must be used in great quantity to produce the light needed (a detriment to cost effectiveness). A plurality of light sources means the composite light projected therefrom can be precisely controlled to suit the target area, but it also means additional optical elements for each light source (adding to the cost and weight of each fixture).
Additionally, there is a vested interest in designing the lighting system at the onset for long-term use; in the aforementioned example, it is simply not economically feasible to shut down multiple lanes of traffic over the life of the system to perform maintenance, re-lamp, etc. Thus, LEDs are a natural choice; their long life removes some concerns with long-term maintenance. However, because LEDs have such a long life they have not been fully tested; thus, there are no definitive answers as to how long LEDs can operate and how severely the light output will degrade over time due to thermal losses and lumen depreciation (not to mention initial efficiency losses due to driver inefficiencies and luminaire design). The Illuminating Engineering Society of North America (IESNA) has recently recommended standards for testing LEDs (see IES LM-79) and measuring lumen depreciation (see IES LM-80), but the scope is limited and does not define or provide estimations for the lifespan of LEDs.
The art is at a loss; in the time it would take to fully test an LED, the technology will have advanced and the data will not be particularly useful. In the meantime, there are lighting applications that may benefit from the long life of LEDs provided that long life can be assured. What is needed are means for reasonably assuring the long life of LEDs in a manner that is reliable and, unlike current maintenance strategies, cost-effective for applications like the aforementioned bridge. Further, what is needed are means for reasonably assuring an acceptable light level over said life; there is little benefit to maintaining an LED lighting system long-term if the light is allowed to degrade to the point of uselessness. Still further, what is needed is a standardized approach to developing large-scale LED fixtures—particularly ones for outdoor use—that can be used with said means for assuring the long life of LEDs so to address current needs. Thus, there is room for improvement in the art.

Compact and adjustable LED lighting apparatus, and method and system for operating such long-term


A method and a device for the production of a green tire, in which at least two materials in strip form are positioned on a tire building drum. At least two cores are set in place. The tire building drum is equipped both with a core clamping device and with a core fixing device. The tire building drum is composed of a central part and of two drum halves arranged adjacent to the central part on both sides. The drum halves are arranged such that they can be positioned in an axial direction. The central part is equipped with a variable diameter in a radial direction. A radial enlargement of the diameter of the central part is performed before the cores are set in place.

The invention relates to a method for producing a green tire, in which method at least two materials in strip form are positioned on a tire building drum, and in which method at least two cores are set in place.
The invention also relates to a device for producing a green tire, in the case of which at least two materials in strip form can be positioned on a tire drum and in the case of which at least two cores can be positioned.
In the production of green tires, materials in strip form are positioned on a tire building drum. Filiform materials are commonly inlaid into the elastomer materials for reinforcement purposes. In lateral regions, in each case one core for reinforcement is set in place.
In the known prior art, the material that is used is laid onto a device which is composed of central and side parts. Cores that are used are positioned and clamped from the inside. The inner side of the cores is supported by a shoulder, and the core clamping remains active during the entire process. Owing to said permanent core clamping, ply fold-over is possible only in an upward direction.
A further disadvantage of the prior art consists in that a filament length between the cores is not clearly defined. It is furthermore not possible to work the material under the core.
Until now, the demands for accuracy in the positioning of the cores have not yet been satisfied in a fully satisfactory manner.

Method and device for producing green tires


An apparatus for generating a recipe for an inspection tool includes an extracting module extracting recipe parameters to be set to the inspection tool from among a group of recipe, a recipe candidate generator generating recipe candidates by combining settings of recipe parameters, a calculator calculating detecting parameters for each of the recipe candidates by inspecting a product using the inspection tool to which each of the recipe candidate is applied; and a recipe selecting module selecting a recipe candidate as a recipe for the inspection tool from among the recipe candidates.

1. Field of the Invention
The present invention relates to an apparatus, a method, and a program for generating a recipe for an inspection tool used to inspect a product.
2. Description of the Related Art
Recipe parameters, which specify operations of an inspection tool used in each inspection process, are set to inspection tools for inspecting a product. A combination of a plurality of recipe parameter settings is referred to as a 'recipe'. An engineer combines many recipe parameters and repeats inspection and defect review so as to generate a recipe. 'Defect review' is a process to confirm defects by examining the defects detected by an inspection tool using a microscope or the like. A combination of recipe parameter settings, which satisfy an inspection condition required of the inspection tool, is selected as a recipe. Inspection conditions include size of defects to be detected and inspection time or the like.
However, a trial-and-error method for generating a recipe by an engineer is inefficient. In addition, recipes may often be generated from subjective judgments of an engineer based on his/her knowledge and experience. This creates a difference in recipe quality due to the skills of engineers. As a result, a serious defect may not be detected.

Apparatus, method and program for generating a recipe for an inspection tool


Disclosed is a resin paste made from a maleimide having at least two maleimide groups and a liquid diamine. The paste can optionally contain fillers, thickeners, defoamers, coupling agents, and solid epoxies. The resin paste has a long pot life and a short cure time and is dispensable through a syringe.

This invention relates to a resinous paste that can be dispensed from a syringe and cured with heat to form a coating or an adhesive. In particular, it relates to a resin paste prepared from a maleimide and a liquid diamine.
Fast curing liquid systems are used extensively in the microelectronics industry as adhesives, sealants, and encapsulants. These liquid systems are typically applied to parts moving on an assembly line and therefore they must be able to cure rapidly. A system must also have a pot life at room temperature that is long enough so that over at least one entire working day its viscosity does not increase so much that it can no longer be dispensed. In addition, of course, it must provide good adhesion to various types of materials. High thermal stability at temperatures above 200.degree. C. is also required in order to withstand downstream processes such as wirebonding. Low water adsorption is desirable so that blisters do not form on heating.
At the present time, epoxy resins are often used for these applications. While epoxy resins have good adhesion, they tend to be rigid and often crack and fail on temperature cycling. In addition, they are not re-workable because they do not remelt upon heating.


Time-slot interchange (TSI) switches and a pipelined data memory address generation circuit are provided. The TSI switches and the pipelined data memory address generation circuit include a first pipeline stage that reads data from a connection memory. A second pipeline stage compares the data read from the connection memory to provide a bank selection value. Optionally, a third pipeline stage reads data from a data memory based on the bank selection value and the data read from connection memory. The timing of the pipeline stages may be adjusted such that the duration of the first pipeline stage is extended and the duration of the second pipeline stage shortened.

Conventional time-slot interchange switches utilize a data memory and a connection memory to control how data passes through the switch. Examples of time-slot interchange (TSI) switch include those described in U.S. Pat. No. 4,510,597 and U.S. Pat. No. 4,093,827. In particular, the connection memory provides addresses to read data from the data memory so as to control the flow of data from inputs of the TSI switch to outputs of the TSI switch.
A circuit for providing data memory addresses in a TSI switch is illustrated in FIG. 1. In FIG. 1, a connection memory read counter 10 and an MPU address buffer 12 provide address values to a multiplexer 14. The MPU address buffer 12 is provided to allow microprocessor access to the connection memory 22. The multiplexer 14 provides a selected one of the output of the connection memory read counter 10 and the MPU address buffer 12 to a predecoder circuit 16. The predecoder provides an address which is clocked into the register 18 on a first clock cycle. The address stored in the register 18 is decoded by decoder 20 and a read of the connection memory 22 is initiated. The data read from the connection memory is stored in a temporary register 24 for use if a microprocessor access is being performed. The output of the connection memory 22 and the temporary register 24 are provided to the multiplexer 26. The temporary register 24 output, however, is only used on a cycle following a microprocessor tick and is not selected by the multiplexer 26 on two subsequent clock cycles. The multiplexer 26 is, therefore, controlled to select the output of the connection memory 22 on cycles other than the cycle immediately following a microprocessor tick and to select the output of the temporary register 24 on the cycle after a clock tick corresponding to a microprocessor access (a microprocessor tick). The output of the mutliplexer 26 is provided to the mutliplexer 30. The multiplexer 30 also receives the output of the MPU address buffer 12. The multiplexer 30 is controlled to select the output of the MPU address buffer during the microprocessor tick and, otherwise, to select the output of the mutliplexer 26.
During operations when a microprocessor access is not performed, the multiplexer 26 provides the direct output of the connection memory 22 or the output of the temporary register 24 to the multiplexer-30. The multiplexer 32 and the comparator 34 receive the output of the multiplexer 30 which provides either the output of a MPU Address buffer 12 or the selected output of the multiplexer 26. For data memory write operations where a microprocessor access is not performed, the multiplexer 32 provides the output of the data memory counter 28. For data memory read operations where a microprocessor access is not performed, the multiplexer 32 provides the output of multiplexer 30 to the register 40.
The address comparator 34 compares the output of the connection memory 22 and the data memory counter 28 and provides a bank selection value that is stored in the bank register 38. Similarly, the output of the connection memory 22 is provided to the register 40 that provides its contents to the predecoder 36. The predecoder 36 provides a pre-decoded address to the decoder 42. The bank register 38 and the register 40 are both clocked during a second clock cycle which is a next subsequent clock cycle to the first clock cycle during which the register 18 is clocked. Thus, the address decode, the connection memory read access and the address compare take less than one clock cycle.
The output of the register 40 is provided to the predecoder 36 that provides its output to a decoder 42, the output of which is provided to the data memory 44. The bank register 38 output is also provided to the data memory 44 for the read operation. The output of the data memory 44 is provided to a parallel-to-serial converter to provide the output of the TSI switch.
As seen in FIG. 1, the data memory read address generation circuit may be considered as including two pipeline stages 50 and 60. As used herein, the term "pipeline stage" refers to operations that are performed between a clock which initiates operations of a first portion of a circuit and a separate clock that initiates operations of a second portion of the circuit. Thus, a pipeline stage may have a duration from a first clock that initiates operations of the pipeline stage to a second clock that initiations operations of the next subsequent pipeline stage. Operations of the pipeline stage are, therefore, initiated with each occurrence of the clock associated with the pipeline stage and terminated upon each occurrence of the clock of the next subsequent pipeline stage. Thus, in FIG. 1, a first pipeline stage 50 is provided between the register 18 and the bank register 38 and register 40. A second pipeline stage 60 is provided from the bank register 38 and address 40. Thus, the first pipeline stage 50 provides for the read of the connection memory, the address compare and the predecode of the data memory read address. The second pipeline stage 60 provides for the decode of the data memory read address and the read of the data memory.
Furthermore, in the system illustrated in FIG. 1, the clocks of the two pipeline stages are synchronized such that the two pipeline stages have equal duration corresponding to one period of the synchronized clocks.
While the system of FIG. 1 provides for reads of the data memory 44 based on the output of the connection memory 22, as the speed and/or size of the TSI switch increases, the time provided for the operations of any of the particular pipeline stages, such as the first pipeline stage 50, may decrease. Such timing constraints may limit the speed and/or size of the TSI switch. Thus, notwithstanding conventional techniques to provide data memory addresses from a connection memory, such techniques may be insufficient as the speed and/or size of TSI switches increase.

Data memory address generation for time-slot interchange switches


A miniaturized VHV transformer/rectifier for surface mounting on a screen-printed ceramic substrate. The primary winding and secondary windings are wound on separate limbs of the magnetic circuit which are sufficiently far apart to obtain a considerable leakage self-inductance. The secondary winding is formed by a stack of pancake coils each including a respective winding and the associated diode bridge along with their respective connections. The primary is cemented to a ceramic interface plate which is metallized on its rim to make a transfer plate coinciding with the surface of the receiving substrate.

1. Field of the Invention
The present invention relates to a miniaturized VHV (Very High Voltage) transformer/rectifier for surface mounting on a screen-printed ceramic substrate.
2. Discussion of the Background
A specific example of an environment in which a VHV transformer/rectifier according to the invention is typically incorporated is represented in the electrical diagram of the attached FIG. 1.
This FIG. 1 concerns a dc step-up voltage converter which, for a dc input voltage VE which is typically a few hundred volts, delivers a dc output voltage Vs which is for example of the order of a few kilovolts.
This circuit includes a chopper 1, in itself very conventional, which includes four static switches of the MOS transistor type, labelled 2 to 5, mounted as a bridge whose input diagonal is supplied with the dc input voltage VE as represented. The four transistors 2, 3, 4, 5 are turned on respectively by the recurrent pulsed signal trains Q1, Q2, Q1, Q2, the signal trains Q1 and Q2 being offset from one another as represented in the attached FIGS. 2A and 2B, and having a high frequency, for example of the order of a few hundred kilohertz.
As a result, on the output diagonal of this bridge, there is a voltage Vp, represented in FIG. 2C, which is made up of a string of relatively short pulses (of width equal to the offset between the pulse trains Q1 and Q2), which are spaced apart and are alternately positive and negative.
To obtain a rectified voltage Vs of absolute value of much greater amplitude (or "VHV") than that of the voltage Vp, use is made of a transformer/rectifier 6 which includes a low-voltage primary winding 7 and a plurality of secondary windings N1, N2, N3, . . . , Nn. Each of these secondary windings supplies a respective diode bridge P1, P2, P3, . . . Pn, the rectified outputs of this plurality of bridges being connected in series as represented in order to obtain the output voltage Vs.
Present-day techniques for constructing transformers do not allow them to be miniaturized without reducing the power which they transmit, on account of problems with the cooling of these transformers.


An optical synchronization system uses a stationary binary diffractive optical element and a rotating disc with alternating scattering binary diffractive optical elements and transmissive elements to create a moire pattern for a synchronization signal for a pixel clock.

This invention relates to an optical synchronization system for a rotating disc, and, more particularly, to an optical synchronization system with binary diffractive optical elements for a rotating disc.
The propagation of a light beam can be changed by three basic means: reflection by a mirror, refraction by a lens and diffraction by a grating. Optical systems traditionally rely on reflection and refraction to achieve the desired optical transformation. Optical design, based on mirror and lens elements, is a well-established and refined process. Until recently, the problems with diffraction and fabricating high efficiency diffractive elements have made diffractive elements unfeasible components of optical systems.
The diffractive process does not simply redirect a light beam. Diffraction, unlike refraction and reflection, splits a light beam into many beams--each of which is redirected at a different angle or order. The percentage of the incident light redirected by the desired angle is referred to as the diffraction efficiency. The diffraction efficiency of a diffractive element is determined by the element's surface profile. If the light that is not redirected by the desired angle is substantial, the result will be an intolerable amount of scatter in the image or output plane of the optical system.
Theoretically, diffractive phase elements can achieve 100 percent diffraction efficiency at a given wavelength. To achieve this efficiency, however, a continuous phase profile is necessary. The theoretical diffraction efficiency of this surface profile is also relatively sensitive to a change in wavelength. By contrast, refractive elements are wavelength insensitive. The technology for producing high quality, high efficiency, continuous phase profiles does not presently exist.
A compromise that results in a relatively high diffraction efficiency and ease of fabrication is a multi-level phase grating. The larger the number of discrete phase levels, the better the approximation of the continuous phase function. These multi-level phase profiles can be fabricated using standard semiconductor integrated circuit fabrication techniques.
As disclosed in Binary Optics Technology: The Theory and Design of Multi-level Diffractive Optical Elements by G. J. Swanson of the Lincoln Laboratory at the Massachusetts Institute of Technology, (Technical Report 854, Aug. 14, 1989) and the resulting U.S. Pat. No. 4,895,790, a fabrication process for a binary diffractive optical element or multi-level phase profile diffraction grating starts with a mathematical phase description of a diffractive phase profile and results in a fabricated multi-level diffractive surface. The first step is to take the mathematical phase expression and generate from it a set of masks that contain the phase profile information. The second step is to transfer the phase profile information from the masks into the surface of the element specified by the lens design.
The first step involved in fabricating the multi-level element is to mathematically describe the ideal diffractive phase profile that is to be approximated in a multi-level fashion. The next step in the fabrication process is to create a set of lithographic masks which are produced by standard pattern generators used in the integrated circuit industry.
A substrate of the desired material is coated with a thin layer of photoresist. The lithographic mask is then placed in intimate contact with the substrate and illuminated from above with an ultraviolet exposure lamp. Alternately, pattern generators, either optical or electron beam, can expose the thin layer of photoresist. The photoresist is developed, washing away the exposed resist and leaving the binary grating pattern in the remaining photoresist. This photoresist will act as an etch stop.
The most reliable and accurate way to etch many optical materials is to use reactive ion etching. The process of reactive ion etching anisotropically etches material at very repeatable rates. The desired etch depth can be obtained very accurately. The anisotropic nature of the process assures a vertical etch, resulting in a true binary surface relief profile. Once the substrate has been reactively ion etched to the desired depth, the remaining photoresist is stripped away, leaving a binary phase surface relief grating.
The process is repeated using a lithographic mask having half the period of the first mask. The binary phase element is recoated with photoresist and exposed using the second lithographic mask which has half the period of the first mask. After developing and washing away the exposed photoresist, the substrate is reactively ion etched to a depth half that of the first etch. Removal of the remaining photoresist results in a 4 level approximation to the desired profile. The process is repeated a third and fourth time with lithographic masks having periods of one-quarter and one-eighth that of the first mask, and etching the substrates to depths of one-quarter and one-eighth that of the first etch. The successive etches result in elements having 8 and 16 phase levels.
This process is repeated to produce a multilevel phase relief structure in the substrate. The result is a discrete, computer-generated structure approximating the original idealized diffractive surface. For each additional mask used in the fabrication process, the number of discrete phase levels is doubled, hence the name "binary" optical element or, more precisely, a binary diffractive optical element.
After only four processing iterations, a 16 phase level approximation to the continuous case can be obtained. This mask and etch fabrication process can be carried out in parallel, producing many elements simultaneously, in a cost-effective manner.
A 16 phase level structure achieves 99 percent diffraction efficiency. The residual 1 percent of the light is diffracted into higher orders and manifests itself as scatter. In many optical systems, this is a tolerable amount of scatter. The fabrication of the 16 phase level structure is relatively efficient due to the fact that only four processing iterations are required to produce the element.
The photolithographic etch steps can be done in any order. Alternatively, the highest pitch, shallowest level is processed first since this level is more difficult to control if etched following deeper etches.
After the first etching step, the second and subsequent lithographic masks have to be accurately aligned to the existing pattern on the substrate. Alignment is accomplished using another tool standard to the integrated circuit industry, a mask aligner.
As noted, the photoresist on the substrate can be exposed with an electron-beam pattern generator. The e-beam direct-write process eliminates masks and their corresponding alignment and exposure problems. Binary optics have also been reproduced using epoxy casting, solgel casting, embossing, injection molding and holographic reproduction.
Binary optical elements have a number of advantages over conventional optics. Because they are computer-generated, these elements can perform more generalized wavefront shaping than conventional lenses or mirrors. Elements need only be mathematically defined: no reference surface is necessary. Therefore, wildly asymmetric binary optics are able to correct aberrations in complex optical systems, and elements can be made wavelength-sensitive for special laser systems.
The diffractive optical elements are generally thinner, lighter and can correct for many types of aberrations and distortions. It is possible to approximate a continuous phase profile with a stepwise profile of discrete phase levels.
Optical scanning systems are used to scan a spot of light along a predetermined pattern such as a scan line on a photoreceptor. Optical elements such as refractive lens or diffractive holograms or gratings can be disposed circumferentially in annular sectors around a rotating disc to generate a scan line and function as an optical scanning system. Even binary diffractive optical elements can be used as the scanning elements in a rotating disc optical scanner as taught in copending patent applications Ser. Nos. 07/989,445 and 07/989,320, commonly assigned with the present application and herein incorporated by reference.
One of the problems inherent in any optical scanning system is monitoring and synchronizing the scanning point of light along the scan line and from scan line to scan line. This is typically done with photodetectors located on a photoreceptor located at the start of scan and the end of scan. But these photodetectors do not monitor and synchronize the entire continuous scan, only the ends.
An alternate system would remove a portion of the scanning beam itself to provide the monitoring and synchronizing function.
It is an object of this invention to provide an optical synchronization system for a rotating disc using binary diffractive optical elements.
It is another object of this invention to provide an optical synchronization system over the entire continuous scan line.
It is another object of this invention to provide an optical synchronization system which does not use the scanning beam itself.

Rotating disc optical synchronization system using binary diffractive optical elements


In one example, a comparator circuit includes a differential stage adapted to receive a differential input signal. The comparator circuit includes first and second diodes coupled to the differential stage. The first and second diodes are adapted to selectively switch on and off to provide a differential output signal at first and second differential output nodes in response to the differential input signal. The comparator circuit includes a current steering circuit adapted to selectively provide a reference current from a current source to the first or second diode in an off state to reduce a voltage swing of the first or second diode between the off state and an on state. The comparator circuit includes an output stage coupled to the first and second diodes at the first and second differential output nodes. The output stage is adapted to convert the differential output signal to a single ended output signal.

Conventional high speed comparators typically receive a differential input signal at a differential pair of transistors biased by a reference current (e.g., a tail current). In response to the differential input signal, the transistors selectively pass the tail current to one or the other of a pair of diodes. The diode receiving the tail current turns on and the remaining diode turns off. The resulting voltages at the diodes typically feed a gain stage that provides a single ended output signal.
If the differential input signal does not rapidly change, the voltage at the diode in the off state may slowly decay to a very low voltage level well below the threshold voltage of the diode. As a result, if the comparator attempts to switch on the diode (e.g., in response to a change in the differential input signal), the diode voltage may be required to swing from a very low voltage up to its threshold voltage. In contrast, if the differential input signal does rapidly change, the voltage of the diode in the off state may not decay far below its threshold voltage.
The different voltage swings of the diodes associated with different data patterns in the differential input signal may cause conventional comparators to exhibit varying data propagation delays which appear as data dependent jitter (e.g., duty cycle distortion) in the single ended output signal. Such jitter is particularly problematic for high speed comparators. As a result, there is a need for an improved approach to comparator design that reduces data dependent jitter associated with conventional comparators.


An overlap amount definition section defines an amount of overlap between divided regions when a shape prediction objective region in a polished surface formed by chemical mechanical polishing is divided into a plurality of regions. A shape prediction computation processing section divides the objective region into the plurality of regions each of which includes a region corresponding to the overlap amount defined by the overlap amount definition section, and performs computation for shape prediction on each divided region by distributed processing. A merging processing section combines the results of shape prediction on the divided regions that are calculated by the shape prediction computation processing section.

(1) Field of the Invention
The present invention relates to a polishing technique and, more particularly, to a shape prediction simulator technique for predicting the shape of a polished surface formed by chemical mechanical polishing (CMP).
(2) Description of Related Art
CMP processes are being put to greater use as a flattening technique and a wiring forming technique for semiconductor devices (see Japanese Patent Laid-Open No. 2003-282495). Also, shape prediction simulator techniques for predicting a flattened shape or a wiring forming shape in a CMP process are being established in recent years.
The operation of a CMP shape prediction simulator will be described as an art related to the present invention.
Referring to FIG. 1, conditions for computation of the pattern density in a semiconductor device are set (step S10). In this pattern density computation condition setting, an analysis area on which a shape prediction is to be made is designated on the basis of layout data (a design drawing) which is information on the design of the semiconductor device, and a computation resolution is determined. The whole or part of the design drawing can be designated as the analysis area.
Subsequently, the pattern density in the designated analysis area is extracted. For this pattern density extraction processing, high-efficiency computation processing can be performed by using distributed processing, because there is no need to consider the influence from adjacent device patterns. In the example shown in FIG. 1, local processing in step S11 or distributed processing in step S12 is performed as pattern density extraction processing.
In local processing, as shown in FIG. 2, one processor (central processing unit (CPU)) performs processing for computing the pattern density in the entire objective region on which computation processing is to be performed. The CPU divides the entire objective region into a plurality of regions in grid form and computes the pattern density in each divided region. For a grid division, the grid size is determined by the computation resolution.
On the other hand, in distributed processing, as shown in FIG. 3, the region on which computation processing is to be performed is divided into four regions, and the divided regions are respectively assigned to four processors (CPUs). Each CPU divides the assigned region into a plurality of regions in grid form and computes the pattern density in each divided region.
After pattern density computation processing in step S11 or S12 is performed, process conditions are set. In this process condition setting, process conditions such as a model selection and a processing time for making a shape prediction are set (step S13). Shape prediction computation is then performed (step S14) according to the computation resolution set in step S10, the pattern densities extracted in step S11 or S12 and the process conditions set in step S13, and hot spot analysis is thereafter performed (step S15).
The inventor of the present invention recognized a problem described below with the CMP shape prediction simulator described above as a related art.
In a CMP process, polishing is performed by using physical contact among a pattern of a device, a polishing pad and slurry (abrasive grains) and, therefore, the shape of the polished device depends largely on the device pattern density. The shape formed by polishing is also influenced by an adjacent device pattern.
FIG. 4 shows the results of comparison between a case where shape prediction computation processing is performed by one CPU (local processing) and a case where shape prediction computation processing is performed by four CPUs (distributed processing). In a section on the left-hand side of FIG. 4, an example of local processing and an example of distributed processing are shown together with objective figures on which the processing is performed. On the right-hand side, a graph is shown which shows the results of shape prediction by local processing and distributed processing and values actually measured. The objective figure on which local processing is performed and the objective figure on which distributed processing is performed are identical to each other. In the graph, the ordinate represents the height of a polished portion and the abscissa represents the range of analysis (scan length). In the graph, the thickest line indicates variations in height of a polished portion in a-a′ of the objective figure on which local processing is performed, and the second thickest line indicates variations in height of a polished portion in b-b′ of the objective figure on which distributed processing is performed. The thinnest line indicates the actually measured values of the actually polished portion.
The computation processing time in the case of local processing is 6720 seconds, while the computation processing time in the case of distributed processing is 1700 seconds. Speed-up by about four times can be achieved by applying distributed processing to shape prediction computation processing. However, this distributed processing is processing in which computation is performed by simply dividing an analysis area into four, such that shape prediction is not performed by considering the influence of device pattern elements extending across the figure boundaries and the influence of device pattern elements in the vicinity of the boundaries. As a result, when distributed processing is used, the difference between the prediction result and the actually measured value is increased in the vicinity of the figure boundary portion (b-b′) to considerably reduce the shape prediction accuracy, as shown in the graph of FIG. 4.
For this reason, local processing is applied to shape prediction computation processing in the above-described CMP shape prediction simulator. Therefore, a considerably long time is required for shape prediction computation processing, depending on conditions including the analysis area and the computation resolution.

Shape prediction simulator, method and program


Hydroxyaromatic compounds such as phenol are converted to diaryl carbonates by reaction with oxygen and carbon monoxide in the presence of a catalyst package which comprises a Group VIIIB metal, preferably palladium, salt of at least one aliphatic .beta.-diketone such as 2,4-pentanedione. The catalyst package also preferably comprises an inorganic cocatalyst, an organic cocatalyst and a bromide or chloride, preferably bromide, source such as a hexaalkylguanidinium bromide. The use of the .beta.-diketone salt confers such advantages as long shelf life under normal storage conditions, high activity upon recycle and capability of carbonylation at relatively low temperatures.

This invention relates to the preparation of diaryl carbonates by carbonylation. More particularly, it relates to the improvement of shelf life and activity of the catalysts employed in the carbonylation reaction.
Diaryl carbonates are valuable intermediates for the preparation of polycarbonates by transesterification with bisphenols in the melt. This method of polycarbonate preparation has environmental advantages over methods which employ phosgene, a toxic gas, as a reagent and environmentally detrimental chlorinated aliphatic hydrocarbons such as methylene chloride as solvents.
Various methods for the preparation of diaryl carbonates by a carbonylation reaction of hydroxyaromatic compounds with carbon monoxide and oxygen have been disclosed. In general, the carbonylation reaction requires a rather complex catalyst. Reference is made, for example, to U.S. Pat. No. 4,187,242, in which the catalyst may be Group VIIIB metal compound, i.e., a compound of a metal selected from the group consisting of ruthenium, rhodium, palladium, osmium, iridium and platinum.
Further developments in the carbonylation reaction, including the use of palladium(II) acetate in combination with such cocatalysts as cobalt pentadentate complexes and terpyridines, are disclosed in U.S. Pat. Nos. 5,231,210, 5,284,964 and 5,399,734. These patents also disclose the use of quaternary ammonium or phosphonium halides, as illustrated by tetra-n-butylammonium bromide, as part of the catalyst package. The use of hexaalkylguanidinium chlorides or bromides in place of the quaternary salts is disclosed in copending provisional application Ser. No. 60/40,300.
The use of such Group VIIIB metal salts as the acetates is accompanied by certain disadvantages relating to the shelf life and activity of the catalyst mixture. It would be convenient to store the catalyst as a feed solution in the reactant hydroxyaromatic compound, said feed solution including the Group VIIIB metal salt in combination with at least one and preferably all of the other catalyst components. However, such feed solutions have extremely limited shelf life since the Group VIIIB metal precipitates therefrom on storage.
It would also be convenient to recycle the catalyst after use. Typically, the diaryl carbonate is recovered as an adduct with the hydroxyaromatic compound leaving the catalyst constituents in solution in further hydroxyaromatic compound. As noted herein-above, however, such solutions have very short shelf life.
Finally, temperatures for the carbonylation reaction on the order of 60-150.degree. C. are disclosed in the aforementioned patents. It is generally found, however, that the divalent Group VIIIB metal acetates such as palladium(II) acetate afford diary carbonate in high yield only at temperatures in excess of about 100.degree. C. Therefore, it would be desirable to employ a catalyst having a high degree of activity over a wider range of temperatures, including temperatures substantially below 100.degree. C.

Method for preparing diaryl carbonates employing .beta.-diketone salts


A toilet plunger assembly having telescopic features is disclosed. The plunger assembly includes a cup assembly, a tubular member and an elongated rod. The tubular member has a first end portion and a second end portion. The second end portion is fixed to the cup assembly. The elongated rod has a first end portion, a second end portion, and an outer diameter. The rod is slideably engaged within the tubular member such that the rod is moveable between a collapsed position and an extended position. In the collapsed position, the rod second end portion is removably joined to the cup assembly, while in the extended position, the rod second end portion is removably joined to the tubular member first end portion.

Toilet plungers are well known and widely used in bathrooms of residences, office buildings, retail establishments and restaurants. Most conventional plungers include a plunger cup mounted to a fixed length handle. It is further known and appreciated that the conventional use of a plunger is to unclog the exit piping leading from a toilet to a sewer system or other types of collection system. This use inherently creates both sanitary and aesthetic issues for any party responsible for bathroom maintenance.
It is common to store a plunger on the floor adjacent to a toilet in a conveniently locatable site. However, a plunger is unsightly and may contrast to the decorum of certain bathrooms. As a result, some plungers are stored in closets or in other enclosed areas. However, the length of a typical plunger handle prohibits storage of a plunger in many areas. Further, the conventional size of a plunger makes its presence in most bathrooms quite apparent, i.e., it is difficult to hide in a corner, for example.
In light of the prior art problems discussed, it would be desirable to have a toilet plunger that features a telescopic handle. Further, it would be advantageous to have a telescopic plunger that is operational without a user having to touch the toilet plunger cup.
The present invention provides a new and improved toilet plunger having a telescopic handle. The present invention uses a two part handle design wherein the device is transferable between an extended position and a collapsed position by manipulation of the handle.


A semantic query may refer to a logical rule, where the rule is defined in terms of constituent expressions. In order to execute the semantic query efficiently, occurrences of the rule may be expanded by replacing the rule with its constituent expressions. Expansion may be performed repeatedly, until only grounded expressions remain. Expressions are grounded when they refer to tables or views that are represented in an underlying database. Once the rule has been reduced to grounded expressions, the semantic query processor may formulate a relational query in terms of the grounded expressions. If the relational query takes into account the various grounded expressions to which the rule reduces, then the portion of the semantic query that refers to the rule may be processed without an excessive number of round trips to the relational database.

In some data models, such as the Resource Description Framework (RDF), data is represented in the form of triples having a subject, an object, and a predicate. In this model, data is a set of logical facts, in which the subject and object are each some entity, and a predicate is a relation that exists between the entities. For example, give a list of people (the entities), predicates could be used to define family relations among the people—e.g., "Alan is a brother of Bob," "Bob is a father of Charlie," etc. These relations could be written in a predicate/argument format, such as that used in Prolog or Datalog—e.g., "brother(Alan,Bob)", "Father(Bob,Charlies)", etc. In fact, many systems that store data in this manner are coupled to, or incorporate, logic programming languages, and can perform sophisticated logical reasoning on the facts represented by the triples.
In one example, a system implements a semantic query language such as SPARQL (which stands, recursively, for "SPARQL Protocol and RDF Query Language"), which allows the client to specify declarative queries in terms of logical reasoning to be performed on the triples. A logic engine, such as a Datalog engine, may be used to carry out the reasoning. However, the actual information on which the reasoning is to be performed—e.g., the subject/predicate/object triples—may be stored in a relational database. When the client processes a semantic query such as a SPARQL query, it may issue relational queries (e.g., Structured Query language, or "SQL," queries) to the relational database to retrieve the appropriate triples from the relational database, and then may perform logical reasoning on the retrieved triples.
Since the client includes an implementation of logic, such as a Datalog engine, logical rules may be defined, and base facts (e.g., triples that are stored in a database) may be used as part of the rule definition. For example, even if there are no underlying "uncle" triples in the database, one might define a rule such as "Uncle(A,B):-Brother(A,C); Father(C,B)". (In other words, "A is the uncle of B, if A is the brother of C and C is the father of B.") A client that responds to semantic queries (e.g., a SPARQL engine) could issue relational queries to obtain the underlying Brother and Father relations from the database, and could then perform the appropriate reasoning on the obtained information. However, some naïve implementations of the semantic query engine neglect certain opportunities to optimize use of the underlying relational database and its relational query processor.

Execution of semantic queries using rule expansion


A color filter of an image sensor, an image sensor and a method for manufacturing the image sensor are disclosed, wherein shapes of respective unit color cells closely form various color patterns, such as a red color pattern, a green color pattern and a blue color pattern, within each unit color cell in a stripe type, and various colors such as red, green and blue required for image generation are produced, without interdependence of the respective unit color cells, are normally realized to induce a finished color filter array to smoothly express more colors, so that the resolution of a generated image in an optimal state is achieved.

1. Field of the Invention
The present invention generally relates to image sensors, and particularly to a color filter of an image sensor, capable of improving shapes of respective unit color cells to closely form various color patterns (such as, a red color pattern, a green color pattern and a blue color pattern) within each unit color cell in a stripe type, thereby normally realizing various colors (such as, red, green and blue) required for image generation by itself without interdependence of the respective unit color cells, so that it is possible to induce a finally finished color filter array to smoothly express more colors within a given condition. Further, the present invention relates to an image sensor using such a color filter and a method for manufacturing an image sensor.
2. Description of the Related Art
Recently, with a rapid development of the electric/electronic technologies, various electronics, such as video cameras, digital still cameras, minicams adapted to personal computers (PC), minicams adapted to mobile phones and so forth, employing image sensor technologies have been widely developed and used.
Traditionally, charge coupled devices (CCDs) have been used in conventional image sensors. However, CCDs can involve drawbacks which may include high driving voltages, separate additional support circuits, and high per-unit prices. As a result, their usage in imaging sensors recently has been declining.
Recently, attention has turned to Complementary Metal Oxide Semiconductor (CMOS) image sensors for overcoming the disadvantages of the CCD. Since CMOS image sensors are manufactured based on CMOS circuit technologies, contrary to existing CCDs, they may have advantages including low driving voltage, lack of additional support circuits, low per-unit price, etc.
As shown in FIG. 1, a CMOS image sensor 10 according to the conventional art for realizing a color image may be constructed in the following manner. Photosensitive pixel units, 30 may be combined with a color filter array CA, wherein the photosensitive pixel units 30 may be disposed on a semiconductor substrate 40 and receive light L to generate and accumulate photocharges, and the color filter array CA may force the received light L to be colorized and transmitted to the photosensitive pixel units 30. In this case, in order to transmit light L to the photosensitive pixel units 30 through the color filter array CA, an intermediate layer 20 is interposed between the photosensitive pixel units 30 and the color filter array CA.
Here, as shown in the FIG. 1, the color filter array CA may be combined by a plurality of unit color cells C1, C2, and C3, which may be associated with various colors, such as red, green and blue (in FIG. 1, for the sake of convenience, only four unit color cells are shown). Each of the unit color cells C1, C2 and C3 may be arranged on the top of the intermediate layer 20 in a mosaic type.
Various processes may be performed in conjunction with the use of CMOS image sensor 10. For example, first, the green unit color cell C3, the red unit color cell C1 and the blue unit color cell C2 may colorize light incident L into green, red and blue light, respectively, and then may pass the colorized light to the photosensitive pixel units 30. Subsequently, the respective photosensitive pixel units 30, which may correspond to the green unit color cell C3, the red unit color cell C1 and the blue unit color cell C2, generate photocharges corresponding to the colorized light and then transmit the generated photocharges to signal processing circuits (e.g., interpolation circuits which are not shown). The interpolation circuits then may interpolate the colors of green, red and blue in a proper manner to generate an image having a predefined resolution.
Human visual perception is generally more sensitive to green than the other primary colors. For this reason, CMOS image sensor 10 may be fabricated so that the green unit color cell C3 occurs with greater frequency compared with the red and blue unit color cells C1 and C2, respectively.
With systems using conventional CMOS image sensor 10, the green unit color cell C3, the red unit color cell C1, and the blue unit color cell C2, all of which may constitute the cell array CA, may display only one color associated with the respective photosensitive pixel 30 (i.e., any one of green, red and blue). Thus, as long as each cell does not depend on a differing adjacent color filter cells, it is impractical to realize a variety of colors associated with any single photosensitive pixel 30.
In other words, with conventional imaging systems, only when the red unit color cell C1 is processed with different unit color cells C2 and C3, is it practical to express a variety of colors required for image generation. However, when the red unit color cell C1 is isolated from different unit color cells C2 and C3, imagery representing only the color red can be produced.
In this manner, images expressing all of the colors associated with respective unit color cells C1, C2 and C3 can be produced. However, the processing produces pixels in the final image which are mutually dependent upon light collected from neighboring unit color cells. Because of this mutually dependent relationship, the production of images by photosensitive pixel units 30 can be inefficient. As a result, a final resolution of the image obtained by the image sensor 10 may be greatly reduced over the total number of arranged unit color cells C1, C2 and C3.
That is to say, with conventional systems, even though relatively many unit color cells C1, C2 and C3 are provided, it is impractical for CMOS image sensor 10 to normally obtain a high resolution image which is proportional to the total number of arranged unit color cells.
Obtaining higher resolution images using conventional CMOS sensor 10 would typically entail increasing the number of unit color cells C1, C2, and C3, unless other measures are taken. Consequently, CMOS image sensor 10 may encounter various problems, such as an increased price, increase in size, etc.
Furthermore, in situations where the corresponding image requires a more precise color pattern, the conventional techniques as described above may not be sufficient.
Moreover, conventional CMOS image sensor 10 may be constructed in a manner so that the respective unit color cells C1, C2 and C3 are arranged on the top of intermediate layer 20 in a mosaic type without a separate reinforcement. In this case, when processes for forming additional unit color cells are undertaken without taking separate measures, such as, for example, a process for laminating photoresist, a process for patterning photoresist, etc., the unit color cells C1, C2 and C3 formed previously may be peeled off from the intermediate layer by an impact applied during construction, i.e., the unit color cells may experience peeling phenomena. As a result, the finished color filter array CA takes an abnormal form in which some unit color cells may be sparsely omitted. In this case, it is impractical for the final finished CMOS image sensor 10 to generate a normal image.
Of course, when reinforcements are additionally arranged between the respective unit color cells C1, C2 and C3, the peeling phenomenon of the unit color cells may be prevented to a certain extent, but because the color filter array CA is generally formed on a very small scale, it is almost impossible to additionally provide separate reinforcements between the respective unit color cells C1, C2 and C3 using present process standards. Therefore, the foregoing peeling phenomenon is recognized as a serious shortcoming in the field of known CMOS image sensor fabrication.

Color filter of image sensor, image sensor, and method for manufacturing the image sensor


A method for communicating data within a wireless network includes receiving an indication of a measurement type from a wireless communication device and receiving a first wireless transmission pertaining to a first measurement performed by the wireless communication device. The method also includes, in response to the received transmission, obtaining a value of a second measurement of the measurement type. The second measurement is performed by a sensor associated with the base station. In addition, the method includes determining a value of the first measurement based on the received transmission and a value of a second measurement performed by the sensor associated with the base station.

Machine-to-machine (M2M) communication, also known as machine type communication (MTC), is becoming an increasingly critical consideration in the design of future communication technologies. By comparison to traditional services such as voice and web streaming, M2M services often place very different requirements on the wireless network due to the specific requirements specified for these services by Third Generation Partnership's (3GPP's) Long Term Evolution standard and other communication standards. Additionally, wireless networks providing M2M communication services may be expected to serve a significantly greater number of MTC user equipment (UEs) than typical wireless networks. Because of these constraints, there is an increasing need to support efficient and cost-effective wireless M2M communications and to develop a cost-, spectrum-, and energy-efficient radio access technology for M2M applications.
In M2M communications, various types of MTC communication devices such as smart meters, signboards, cameras, remote sensors, laptops, and appliances may be connected to the network. While the functionality and normal operation of these devices may vary, there are several characteristics that many MTC devices share. For example, many MTC devices often transmit information primarily in sporadic bursts of one or a few short packets. These packets often contain information such as measurements, reports and triggers, such as temperature readings, humidity measurements, and wind speed calculations. In many cases, MTC devices are static or have low mobility. MTC devices are typically expected to be low-complexity device that target low-end (low average revenue per user, low data rate, high latency tolerance) applications. The power/energy consumption for MTC devices are normally expected to be lower than typical communication devices as well.
In order to provide effective M2M communication service on a large scale, will require improvements to existing wireless networks. To provide coverage to a large number of MTC devices, a network operator could install a very dense deployment of base stations (including various combinations of macro, micro, pico and femto stations) and relay nodes to increase capacity, or could build very powerful base stations, having advanced receivers and several receiver antennas collecting weak signals from MTC devices. However, these solutions would require significant financial investment and installation efforts. As a result, new techniques are needed that can leverage and/or overcome characteristics that are common in MTC devices to provide efficient solutions for supporting M2M communications.

System and method for processing received data in a wireless network


The invention relates to a device for integrally processing a housing of a Computing, Communication, and Consumer (3C) product. The device includes a loading frame and an upper frame, where a material receiving device is arranged in the loading frame, a width of the loading frame is greater than that of the housing, a grinding device is arranged below the upper frame, and the grinding device includes a grinding movement device; the grinding movement device is connected to a grinding installation block, an outer side of the grinding installation block is provided with grinding lifting balls, a grinding arc block is embedded in an inner side of an upper portion of the grinding installation block, and the upper frame is provided with a material pressing device. An outer side of the loading frame is provided with a feeding and discharging device.

The 3C products mean the combination of Computer, Communication and Consumer electronics. They are also called information appliances. Mobile phones are common 3C products, and housings thereof are mostly made of metal materials and formed by casting. One of the housings is shown in FIG. 2. An upper portion is a top view and a lower portion is a sectional view. It can be seen from the figure that both sides are arc-shaped. Therefore, the arc needs to be polished during processing. Most of the existing polishing is conducted manually. When the arc-shaped surface is mechanically polished, the arc-shaped surface needs positioning and clamping. However, most of clamping and positioning operations of existing carriers need manual feeding and adjustment, which is inefficient.

Device for integrally processing housing of 3C product


A partitioned processing system is disclosed wherein a workload calculation is implemented for at least one partition. CPU utilization and I/O throughput information is used in calculating resource control parameters which is indicative of resource usage for the partition. The system collects and analyzes the computer system capacity data in a partition which determines a sizing metric. The system includes a manager in the computer system which issues a command to obtain throughput information of a computer system first partition, and issues a command to obtain resource utilization information of the computer system first partition. The manager then calculates a resource control parameter using the information obtained. The system includes a monitor which indicates resource allocation responsive to the resource control.

Most modern medium to large enterprises have evolved their IT infrastructure to extend the reach of their once centralized "glass house" data center throughout, and in fact beyond the bounds of their organization. The impetus for such evolution is rooted, in part, in the desire to interconnect heretofore disparate departmental operations, to communicate with suppliers and customers on a real-time basis, and is fueled by the burgeoning growth of the Internet as a medium for electronic commerce and the concomitant access to interconnection and business-to-business solutions that are increasingly being made available to provide such connectivity.
Attendant to this recent evolution is the need for modern enterprises to dynamically link many different operating platforms to create a seamless interconnected system. Enterprises are often characterized by a heterogeneous information systems infrastructure owing to such factors as non-centralized purchasing operations, application-based requirements and the creation of disparate technology platforms arising from merger related activities. Moreover, the desire to facilitate real-time extra-enterprise connectivity between suppliers, partners and customers presents a further compelling incentive for providing connectivity in a heterogeneous environment.
In response to a rapidly growing set of customer requirements, information technology providers have begun to devise data processing solutions that address these needs for extended connectivity for the enterprise data center.
Background information related to subject matter in this specification includes: U.S. patent Ser. No. 09/183,961 "COMPUTATIONAL WORKLOAD-BASED HARDWARE SIZER METHOD, SYSTEM AND PROGRAM PRODUCT" Ruffin et al. which describes analyzing the activity of a computer system; U.S. patent Ser. No. 09/584,276 "INTER-PARTITION SHARED MEMORY METHOD, SYSTEM AND PROGRAM PRODUCT FOR A PARTITIONED PROCESSING ENVIRONMENT" Temple et al. which describes shared memory between logical partitions; U.S. patent Ser. No. 09/253,246 "A METHOD OF PROVIDING DIRECT DATA PROCESSING ACCESS USING QUEUED DIRECT INPUT-OUTPUT DEVICE" Baskey et al which describes high bandwidth integrated adapters; U.S. patent Ser. No. 09/583,501 "Heterogeneous Client Server Method, System and Program Product For A Partitioned Processing Environment" Temple et al. which describes partitioning two different client servers in a system; IBM document SG24-5326-00 "OS/390 Workload Manager Implementation and Exploitation" ISBN: 0738413070 which describes managing workload of multiple partitions; and IBM document SA22-7201-06 ESA/390 Principles of Operation which describes the ESA/390 Instruction set architecture. These documents are incorporated herein by reference.
Initially, the need to supply an integrated system which simultaneously provides processing support for various applications which may have operational interdependencies, has led to an expansion in the market for partitioned multiprocessing systems. Once the sole province of the mainframe computer (such as the IBM S/390 system), these partitioned systems, which provide the capability to support multiple operating system images within a single physical computing system, have become available from a broadening spectrum of suppliers. For example, Sun Microsystems, Inc. has recently begun offering a form of system partitioning in the Ultra Enterprise 10000 high-end server which is described in detail in U.S. Pat. No. 5,931,938 to Drogichen et al. for "Multiprocessor Computer Having Configurable Hardware System Domains" filed Dec. 12, 1996 issued Aug. 3, 1999 and assigned to Sun Microsystems, Inc. Other companies have issued statements of direction indicating their interest in this type of system as well.
This industry adoption underscores the "systems within a system" benefits of system partitioning in consolidating various computational workloads within an enterprise onto one (or a few) physical server computers, and for simultaneously implementing test and production level codes in a dynamically reconfigurable hardware environment. Moreover, in certain partitioned multiprocessing systems such as the IBM S/390 computer system as described in the aforementioned cross-referenced patent applications, resources (including processors, memory and I/O) may be dynamically allocated within and between logical partitions depending upon the priorities assigned to the workload(s) being performed therein (IBM and S/390 are registered trademarks of International Business Machines Corporation). This ability to enable dynamic resource allocation based on workload priorities addresses long-standing capacity planning problems which have historically led data center managers to intentionally designate an excessive amount resources to their anticipated computational workloads to manage transient workload spikes.
While these partitioned systems facilitate the extension of the data center to include disparate systems throughout the enterprise, currently these solutions do not offer a straightforward mechanism for functionally integrating heterogeneous or homogeneous partitioned platforms into a single inter operating partitioned system. In fact, while these new servers enable consolidation of operating system images within a single physical hardware platform, they have not adequately addressed the need for inter-operability among the operating systems residing within the partitions of the server. This inter-operability concern is further exacerbated in heterogeneous systems having disparate operating systems in their various partitions. Additionally, these systems typically have not addressed the type of inter-partition resource sharing between such heterogeneous platforms which would enable a high-bandwidth, low-latency interconnection between the partitions. It is important to address these inter-operability issues since a system incorporating solutions to such issues would enable a more robust facility for communications between processes running in distinct partitions so as to leverage the fact that while such application are running on separate operating system, they are, in fact, local with respect to one another.
In the aforementioned U.S. patent Ser. No. 09/584,276 "INTER-PARTITION SHARED MEMORY METHOD, SYSTEM AND PROGRAM PRODUCT FOR A PARTITIONED PROCESSING ENVIRONMENT" by Temple et al., extensions to the "kernels" of the several operating systems facilitate the use of shared storage to implement cross partition memory sharing. A "kernel" is the core system services code in an operating system. While network message passage protocols can be implemented on the interface thus created, it is often desirable to enable efficient inter process communication without resorting to modification of one or more of the operating systems. It is also often desirable to avoid limiting the isolation of partitions in order to share memory regions as in aforementioned U.S. patent Ser. No. 09/584,276 by Temple et al. or as in the Sun Microsystems Ultra Enterprise 10000 high end server, as described in U.S. Pat. No. 5,931,938. At the same time it is desirable to pass information between partitions at memory speed instead of network speed. Thus a way to move memory between partition memories without sharing addresses is desired.
The IBM S/390 Gbit Ethernet (Asynchronous Coprocessor Data Mover Method and Means, U.S. Pat. No. 5,442,802, issued Aug. 15, 1995 and assigned to IBM) I/O adapter can be used to move data from one partition's kernel memory to another, but the data is moved from the first kernel memory to a queue buffer on the adapter and then transferred to a second queue buffer on the adapter before being transferred to a second kernel memory. This means that there is a total of three data movements in the transfer from memory to memory. In any message passing communications scheme, it is desirable to minimize the number of data movement operations so that the latency of data access approaches that of a single store and fetch to and from a shared storage. A move function has three data move operations for each block of data transferred. A way to remove one or two of these operations is desired.
Similarly, the IBM S/390 Parallel Sysplex Coupling Facility machine can and is used to facilitate inter partition message passing. However, in this case the transfer of data is from a first Kernel Memory to the coupling facility and then from the coupling facility to a second Kernel Memory. This requires two data operations rather than the single movement desired.
In many computer systems it is desirable to validate the identity of a user so that improper use of the data and applications on the machine through unauthorized or unwarranted access is prevented. Various operating and application systems have user authentication and other security services for this purpose. It is desirable to have users entering the partitioned system or indeed any cluster or network of systems to be validated only once on entry or at critical checkpoints such as request for critical resources, or execution of critical system maintenance functions. This desire is known as the "Single Sign on" requirement. Because of this the security servers of the various partitions must interact or be consolidated. Examples of this are the enhancement of the OS/390 SAF (RACF) interface to handle "digital certificates" received from the web, mapping them to the traditional user ID and password validation and entitlement within OS/390, Kerberos security servers, and the emerging LDAP standard for directory services.
Furthermore, because of the competitive nature of e-Commerce the performance of user authentication and entitlement is more important than in traditional systems. While a worker may expect to wait to be authenticated at the start of the day, a customer may simply go elsewhere if authentication takes too long. The use of encryption, because of the public nature of the web, exacerbates this problem. It is also often the case, that a device driver exists in one operating system that has not been written for others. In such cases it is desirable to interface to the device driver in one partition from another partition in an efficient manner. Only network connections are available for this type of operation today.
One of the problems with distributed systems is the management of "white space" or under utilized resources in one system, while other systems are over utilized. There are workload balancers such as IBM's LoadLeveler or Parallel Sysplex features of the OS/390 operating system workload manager which move work between systems or system images. It is possible and desirable in a partitioned computing system to shift resources rather than work between partitions. This is desirable because it avoids the massive context switching and data movement that comes with function shifting.
The "Sysplex Sockets" for IBM S/390 which uses the external clustering connections of the Sysplex to implement a UNIX operating system socket-to-socket connection is an example of some of the prior art. There, a service indicates the level of security available and sets up the connection based on the application's indication of security level required. However, in that case, encryption is provided for higher levels of security, and the Sysplex connection itself has a physical transport layer which was much deeper than the memory connections implemented by the present invention.
Similarly, a web server providing SSL authentication and providing certificate information (as a proxy) to a web application server can be seen as another example where sharing memory or direct memory to memory messages of the present invention are used to advantage. Here the proxy does not have to re-encrypt the data to be passed to the security server, and furthermore does not have a deep connection interface to manage. In fact it will be seen by those skilled in the art that in this embodiment of our invention the proxy server essentially communicates with the security server through a process which is essentially the same as a proxy server running under the same operating system as the security server. U.S. patent Ser. No. 09/411,417 "Methods, Systems and Computer Program Products for Enhanced Security Identity Utilizing an SSL Proxy" Baskey et al. discusses the use of proxy server to perform the secure sockets layer (SSL) in the secure HTTP protocol.

Inter-partition message passing method, system and program product for throughput measurement in a partitioned processing environment