A compensated voltage regulator of the type used in programming non-volatile memory cells of a memory cell matrix that is divided into sectors. The voltage regulator includes a comparator that is connected to a supply voltage. A first input terminal of the comparator is supplied a reference voltage, and a second input terminal is feedback connected to a program line. The control terminal of an output transistor is connected to an output terminal of the comparator, and a conduction terminal of the output transistor is connected to the memory cells by the program line. An output current is passed through a conduction terminal of the output transistor. Further, a compensation circuit is powered by the supply voltage. An input of the compensation circuit is connected to the output terminal of the comparator and to the output transistor, and an output of the compensation circuit is also connected to the output terminal of the comparator. This causes the duplication of a current that is suitably attenuated with respect to the output current and is useful in modifying the output voltage of the comparator.

1. Field of the Invention
The present invention relates to voltage regulators, and more specifically to a compensated voltage regulator for biasing the terminals of electrically-programmable non-volatile memory cells.
2. Description of the Related Art
A conventional electrically-programmable non-volatile memory is constructed as matrices of memory cells that each include a floating gate MOS transistor having drain and source regions. The floating gate is formed over the semiconductor substrate and is isolated from the substrate by a thin layer of gate oxide, and a control gate is capacitively coupled through a dielectric layer to the floating gate. Metal electrodes are provided for contacting the drain, source, and control gate terminals to allow predetermined voltages to be applied to the memory cell. A semiconductor integrated circuit non-volatile memory device typically has a very large number of such cells organized into a matrix of rows (or word lines) and columns (or bit lines). All of the memory cells in one word line have a common drive line connected to their control gates, and the memory cells in one bit line have their drain terminals connected in common.
In conventional non-volatile memory cells, the amount of charge present on the floating gate can be varied by suitably biasing the terminals of the cell. Charge is stored on the floating gate through a "programming" operation in which the drain terminal and the control gate are biased to a predetermined voltage that is higher than the voltage at the source terminal. In particular, the programming or writing of an individual memory cell is based on the well-known phenomenon of hot electron injection in which cell programming is enabled by an injection of hot electrons onto the floating gate.
During programming, hot electrons are generated in the channel of the floating gate transistor in proximity to the drain region when there are present electric fields of such strength that the electrons are given a much different mobility than that caused by normal thermal agitation. For such an electron injection to occur, the electrons must be supplied kinetic energy of a greater magnitude than the potential energy existing between the channel and the gate region. This is achieved by biasing the gate and drain terminals of the memory cell at relatively high voltages (e.g., 12.5V and 6.5V, respectively).
Such memory cell biasing involves considerable dissipation of current and it is vital that the memory cell accessing resistors do not produce voltage drops sufficient to degrade the potential of the bias voltage being applied. If such a degradation does occur in non-volatile memory cells of the flash type for example, the reduced potential of the drain voltage Vpd causes an insufficient or slow programming of the memory cell. On the other hand, too large of a potential for the drain voltage Vpd can cause a destructive snap-back phenomena or the memory cell to be soft erased (i.e., become partially erased). Thus, the optimum range for the drain voltage Vpd is fairly limited with variations on the order of 200 mV to 300 mV from the reference potential being typically dictated by the technology. In this respect, the writing rate and snap-back phenomenon respectively set the lower and upper limits of the drain voltage range that is acceptable for proper programming of the memory cell.
In order to insure that programming voltages fall within the required range, conventional memory devices are provided with a sophisticated type of voltage regulator that is adapted to supply the bit lines of the cell matrix with an accurately regulated drain voltage during programming. However, advanced miniaturizing technologies make it increasingly more difficult to provide programming circuitry that is capable of generating the appropriate bias voltages. In particular, reduced width and thickness interconnect lines result in higher resistance for the conduction paths used for applying the drain voltage to the memory cells. Further, the current dissipation of each memory cell increases as a result of reduced oxide thicknesses.
Such problems become even more acute at the testing stage in which multiple memory cells are simultaneously programmed in parallel in order to lower the cost and time of the operation. More specifically, the simultaneous programming causes increased voltage drops across the conduction paths used for accessing the drain terminals of the memory cells. Furthermore, the reduced channel length brought about by the ongoing miniaturization process significantly restricts the permissible range for the drain voltage mainly because of a lowered snap-back voltage.
A number of programming circuits have been proposed to solve the problems described above. According to one solution that is disclosed in European Patent Application No. 93-830545.5, a drain voltage regulator outputs a slightly higher voltage than the voltage desired for the bit line. This voltage difference is instantaneously dependent on the current actually flowing through the bit line select transistors. A voltage regulator of this type is formed through an adaptive bias technique using a positive feedback structure. The feedback structure employs a "central" generator that includes an average voltage drop compensator for the access lines to the cell drains, and the voltage is regulated using a feedback circuit of the cascode-compensator type.
Additionally, in such a regulator, an outer feedback loop also exists so as to modify the system reference voltage according to the output current. Thus, the generator supplies a higher output voltage with larger output currents to compensate for the voltage drop across the memory cell access lines. However, the bias variation caused by the number and location of memory cells being programmed remains quite high. While being somewhat advantageous, such a regulator applies its voltage control operation to the whole of the memory cells and does not allow the high programming parallelism that is necessary to speed up the testing of the memory device.
In a more recent solution that is disclosed in European Patent Application No. 96-830192.9, local drain voltage generators are employed for each output sector of the memory matrix. An example of programming circuitry incorporating local generators for the drain voltage Vpd is shown in FIG. 1, and a more detailed diagram of the programming circuitry is shown in FIG. 2. In the circuitry of FIG. 2, the Vpp line supplies the high voltage (e.g., 12.5V) for the programming operation and is used to generate a reference voltage Vref (e.g., 6.5V by dividing the program voltage Vpp). The reference voltage Vref potential is "duplicated" with low output resistance by multiple drain voltage Vpd generators.
The drain voltage generators are located adjacent to the memory matrix so that the access path to the memory cell drains is much shorter than in device arrangements having a "central" generator and providing long signal distribution paths and transistors for accessing the matrix sectors containing memory cells to be programmed. Furthermore, with this arrangement, the memory cell biasing is not affected by the number and location of the output sectors that are involved in the programming. This advantage also holds true for parallel programming because it is possible to activate several independent paths at the output of each generator by acting on column selection.
The structure used in FIG. 2 includes a negative feedback regulator that can smooth out the output voltage Vyms to close to the reference voltage Vref for even large output currents. The high differential gain of the comparator, the ample dynamic range of its output signal, and the high transconductance of the cascodes ensure regulation even in situations of considerable drift of the technological parameters and degradation of the supply voltage Vpp. Further, a capacitor at the comparator output creates a dominant time constant in the feedback network that prevents overshooting at both the transient and the regulation phases, and enable transistors controlled by a program signal inhibit the generator action when the data to be written into the memory cell is the same as the state of a virgin memory cell.
Although this solution provides such advantages, it may also be unsatisfactory where the resistance downstream of the generators becomes too high. For example, a voltage drop can occur across the whole of Vpp line in a device having very long bit lines or when the current drain of the memory cells is quite large (e.g., in parallel programming). Such an overall voltage drop causes the reference voltages to be degraded and thus results in an unacceptable variation in the programming voltage.


This application describes systems and techniques for adjusting one or more setting(s) of a vehicle based on detected condition(s) to avoid damage due to contact of the tires with a body, chassis, or other components of the vehicle. In some instances, the vehicle may determine a ride height of the vehicle, determine a limited range of steering angles based at least in part on the ride height, and control operation of the steering system of the vehicle based at least in part on the limited range of steering angles. In some instances, the vehicle may determine a steering angle of the vehicle, determine a limited range of ride heights based at least in part on the steering angle, and control operation of the suspension system of the vehicle based at least in part on the limited range of ride heights.

Vehicles often include a steering system and a suspension system for controlling maneuvering of the vehicle. The steering system may be used to maneuver the vehicle along roads, causing the vehicle to travel through curves and provide general maneuverability, and the suspension system may be used to smooth out a ride, causing the vehicle to travel through road bumps and other kinetic impacts safely. Used in combination with a powertrain, the steering and suspension systems of the vehicle may be used to control the vehicle to maneuver between locations and provide a comfortable ride experience to users. Steering systems are typically designed so that the tires of the vehicle do not rub against a body or chassis of the vehicle during normal operation of the vehicle. Some conventional steering systems use mechanical steering stops to limit a range of steering angles to prevent the tires from contacting the chassis of the vehicle.

Dynamic vehicle steering and/or suspension constraints


An example apparatus is caused to receive a message inviting a user equipment (UE) to participate in an emergency communication session with an originating node, where the user equipment is registered with an Internet Protocol Multimedia Subsystem (IMS). The apparatus is caused to identify a type of registration of the UE with the IMS, and select a transfer function of the IMS to anchor the emergency communication session based on the identified type of registration of the user equipment with the IMS. The transfer function may be a domain transfer function or emergency access transfer function of the IMS. The apparatus is also caused to prepare the message for transmission to the selected transfer function to thereby enable the selected transfer function to anchor the emergency communication session and further communicate with one or more other components of the IMS to establish the emergency communication session with the user equipment.

The modern communications era has brought about a tremendous expansion of wireline and wireless networks. Computer networks, television networks and telephony networks are experiencing an unprecedented technological expansion, fueled by consumer demand. Wireless and mobile networking technologies have addressed related consumer demands, while providing more flexibility and immediacy of information transfer.
Current and future networking technologies continue to facilitate ease of information transfer and convenience to users. In order to provide easier or faster information transfer and convenience, telecommunication industry service providers are developing improvements to existing networks. For example, the Evolved Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access Network (E-UTRAN) is currently under development. The E-UTRAN, which is also known as Long Term Evolution (LTE), is aimed at upgrading prior technologies by improving efficiency, lowering costs, improving services, making use of new spectrum opportunities, and providing better integration with other open standards. A number of these new networking technologies include packet-switched (PS) networks, such as the 3rd Generation Partnership Program (3GPP) IP Multimedia Subsystem (IMS) network, which has adopted the Session Initiation Protocol (SIP) as the signaling protocol.
As these new networking technologies are deployed, coverage by the new networking technology may not be universal. In order to assure quality of service and avoid dropping of calls, the new networking technologies may be configured to coexist with legacy networking technologies, such as circuit-switched (CS) networks. In this regard, a mobile terminal (for example, user equipment—UE) may be handed over between, for example, an LTE network and a CS network. Single radio voice call continuity (SRVCC) functionality is being defined to enable a UE to perform an inter-domain handover from LTE to CS such that a voice over Internet Protocol (VoIP) session over IMS over the LTE access may be transferred to the CS network, such as when the LTE coverage is lost.

Single radio voice call continuity for emergency callback or click-to-dial sessions


Method and apparatus for providing percussive ventilation therapy to a patient airway preferably includes at least one driver unit configured to provide pressurized, non-pulsate gas. At least one patient interface device preferably has structure configured to (i) receive the pressurized, non-pulsate gas from the at least one driver unit and transform it into a pulsed and pressurized gas, and (ii) supply at least one sub tidal volume of pulsed and pressurized gas to a patient through a patient connection orifice. At least one flexible tube is preferably configured to provide pressurized, non-pulsate gas from the at least one driver unit to the at least one patient interface device. Preferably, at least one portion of the patient interface device is disposable, and another portion may be reusable. Preferably, the invention uses Adaptive Dynamic Subtidal Ventilation technology.

The respiratory airways employ tiny hairs, called motile cilia, which beat in coordinated waves to facilitate removal of pulmonary mucus by directing it to the back of the throat. Illness such as Chronic Obstructive Pulmonary Disease (COPD) are indications of damage to the respiratory surfaces, causing inflammation (which affect the cilia's ability to mobilize secretions), increased mucus production, and swollen passageways which restrict airflow, further reducing the body's ability to remove mucus.
With the ageing populations, the prevalence of lung disease is increasing, particularly in those countries with a high smoking incidence.
Acute and chronic lung diseases management remains an important health problem with substantial mortality and morbidity. Beside smoking, infections and pollution, other factors as population density and urbanization, migration and global travel, can lead to the increase in the prevalence of lung diseases.
Ventilators that supply small bursts of high frequency air pulses are becoming increasingly recognized as an effective therapeutic treatment to facilitate alveoli recruitment (hence lung volume) and aid in the removal of mucus secretions from the lung. The pulses of air provide kinetic energy to the air column within the patient's airway without triggering the Hering-Breuer pulmonary stretch reflex, and provide an average positive airway pressure (PAP) effect. The average positive airway pressure and oscillating column of air help mobilize mucus, especially when combined with medicated aerosols, although the exact mechanism of operation is not known.
Unfortunately, there are few effective devices able to deliver percussive ventilation therapy, and those which are proven effective are expensive.
U.S. Pat. No. 4,592,349 discloses a distal (to the patient) Driver Unit which comprises a pressure reduction regulator and pneumatic oscillating air interrupter valve to supply pulses of air via a hose to a proximal Patient Interface Device, which comprises a sliding venturi mechanism to provide an enhanced percussive effect. However, the Driver Unit employs a pneumatic air interrupter valve which requires high pressure (up to 40 psi) to reliably provide a high-frequency percussive effect, resulting in a large, noisy Driver unit that is power inefficient, must be operated from mains, and is costly to manufacture.
U.S. Pat. No. 7,191,780 discloses a low cost apparatus for delivering high frequency pulses of air to a patient. This includes a distal Driver Unit which comprises a pressure reduction regulator to stabilize a source of compressed air, and configurable flow interrupter valve which supplies pulses of air via a hose to a proximal Patient Interface Device.
U.S. Pat. No. 8,365,727 discloses a distal base unit comprising at least one electronic air interrupter valve, which may be supplied from a compressed air source and pressure reduction regulator within the Driver unit, or may be supplied from a regulated pressure source e.g. from hospital air supply outlet. The Driver unit outlet then supplies a proximal Patient Interface Device with pulses of air via a hose.
However, any approach to generate percussive ventilation which employs an air interrupter valve in a distal Driver feeding pulses of air to a proximal Patient Interface Device will suffer from lessening of the percussive effect caused by both the compressibility and inertia of the air contained within the hose from the distal Driver unit to the Patient Interface Device, and also dampening effects due to the elastic compliance of the hose itself. In addition, the air interrupter valve must endure millions of cycles of operation during the Driver unit lifetime, is prone to wear and requires expensive maintenance to replace.
U.S. Pat. No. 4,592,349 additionally discloses how to enhance damped percussive pulses by employing an air operated servo assisted sliding venturi shuttle to enhance percussive pressure pulse waveforms applied to the patient. However, as in the case of the pneumatic air interrupter valve, but also this requires high working pressure in the Driver Unit (up to 40 psi, with associated bulk, noise, and low efficiency), whereas the jet pressure applied to the venturi inlet is typically less than 10 psi. In addition, the sliding venturi shuttle is only activated in one direction, whereas double acting sliding venturi shuttle will improve the sharpness of pressure waveforms applied to the patient's pulmonary airway, and hence improve the percussive effect.
In light of this, a need exists for a low cost, low power, low noise, efficacious percussive therapy system which operates in conjunction with a low cost Patient Interface Device.


The present invention is directed to an imaging tool to introduce a vibrational force into an object. The imaging tool includes a pair of flywheels that are driven by a motor in opposing rotational paths so as to introduce a harmonic mechanical excitation to the object. The imaging tool is constructed to be of handheld size so as to be suitable for ultrasound and is RF-compatible with MR scanners.

The present invention relates generally to diagnostic imaging and, more particularly, to an imaging tool that induces harmonic excitation within an object. Accordingly, the present invention is particularly applicable to elastography.
Increasingly, there has been a desire to image the elastic properties of tissue either through ultrasound or magnetic resonance imaging or other imaging techniques. Specifically, elastography has been identified as an effective tool in identifying malignant tumors within an object. That is, it is well known that malignant tumors are stiffer relative to their surrounding tissue when such tumors reach a requisite size. As such, by gathering information about the elastic properties of tissue, either through elastic field parameters, e.g., mechanical strain, or from elastic material parameters, e.g., Young's modulus, malignant tumors may be readily identified.
To perform such an elastography, it is necessary to apply a mechanical force to the object under investigation and measure the resulting mechanical displacement or strain field, from which other parameters may be determined. As referenced above, the observation of displacement is typically carried out either by ultrasound or another imaging technique, such as magnetic resonance (MR) imaging.
The drawback of current techniques of elastography lies in the poor signal-to-noise ratio of the displacement measurements, especially in case of freehand approaches. Accordingly, it is desirable to apply a harmonic mechanical excitation to the object, so that the resulting displacements will have a harmonic character. However, it is desirable for such a solution to fall within other desirable constraints; namely, excitation to an object in the range of 1-600 Hz as well as incorporation in a handheld tool for ultrasound or a tool that is RF-compatible for MR imaging.


A semiconductor memory apparatus may include a refresh mode control circuit configured to enable a row address increase signal when all banks capable of being designated by a bank address in a refresh operation are all designated. The semiconductor memory apparatus may also include and a row address generation circuit configured to increase a value of a row address when the row address increase signal is enabled.

1. Technical Field
Various embodiments generally relate to semiconductor integrated circuits, and more particularly, to a semiconductor memory apparatuses.
2. Related Art
Semiconductor memory apparatuses are configured to store data. The data stored in the semiconductor memory apparatuses may also be outputted to other devices located externally from the semiconductor memory apparatus. Depending on the type of scheme used for storing data, semiconductor memory apparatuses may be classified into volatile memory or nonvolatile memory. Volatile memory must perform an operation for retaining data and nonvolatile memory does not need to perform the operation for retaining data.
The semiconductor memory apparatuses that include volatile memory retain their data by performing a refresh operation.
The development of a refresh operation for allowing a semiconductor memory apparatus to stably retain data is in progress.

Semiconductor memory apparatus performing a refresh operation


A transmitter includes a time/frequency-domain converter that converts a time-domain data signal to a frequency-domain data signal of a fixed number; a subcarrier allocator that allocates the obtained frequency-domain data signal to any of subcarriers, the number of which exceeds the fixed number, the subcarriers being allocated in a predetermined transmission frequency band; and a controller that controls the subcarrier allocator to allocate signals other than the data signal to subcarriers in an idle band to which the data signal is not allocated. By this, without the need for a plurality of time/frequency-domain conversion circuits with a large size, such as DFTs, frequency utilization efficiency (data transmission efficiency) is improved.

(1) Field of the Invention
The present invention relates to a transmitter and a transmission method. The present invention relates to a technique suitable for use in radio communication techniques such as mobile communication systems that use a DFT-S-OFDM (Discrete Fourier Transform-Spread-Orthogonal Frequency Division Multiplexing) scheme, for example.
(2) Description of Related Art
At present, in 3GPP (3rd Generation Partnership Project), standardization of enhancement (Long Term Evolution) of third generation mobile communication systems is under consideration. For an uplink access scheme, adoption of SC-FDMA (Single Carrier-Frequency Division Multiple Access) is considered and a method of implementing the SC-FDMA using the DFT-S-OFDM is one of the promising approaches.
FIG. 8 shows a configuration that focuses attention on an essential part of a transmitter that adopts the DFT-S-OFDM. The transmitter shown in FIG. 8 includes, for example, a modulator 101, a DFT (Discrete Fourier Transformer) 102, a subcarrier mapper 103, an IFFT (Inverse Fast Fourier Transformer) 104, and a CP (Cyclic Prefix) inserter 105. The following describes, as an example, parameters for the case in which the transmission frequency band is 5 MHz.
In the transmitter having the above-described configuration, a transmission data signal is modulated by the modulator 101 by a required modulation scheme such as QPSK or 16 QAM. The modulated data signal has a symbol rate of 4.5 MHz.
The modulated data signal is subjected to a DFT processing for every 300 symbols (which is called a block) in the NDFT (e.g., 300)-point DFT 102, whereby the signal is converted from a time-domain signal to a frequency-domain signal. That is, the DFT-processed modulated data signal is converted to a signal composed of NDFT (=300) subcarriers.
The subcarrier mapper 103 maps the 300-subcarrier signal onto an NIFFT (e.g., 512)-point IFFT (IFFT 104), thereby performing a frequency-domain arrangement. Depending on the subcarrier mapping method, the transmission bandwidth is extended in form and thus this subcarrier mapping is called a spread.
The subcarrier-mapped signal is subjected to an IFFT processing in the IFFT 104, whereby the signal is converted from the frequency-domain signal to a time-domain signal again. An example of FIG. 8 shows an operation in which an output from the 300-point DFT 102 is continuously arranged on the 512-point IFFT and a zero signal is inserted in the remaining 212 points.
By this, the signal of 300 points per block prior to the DFT is converted to a signal of 512 points per block after the IFFT. That is, the signal of 4.5 MHz prior to the DFT is over sampled to 7.68 MHz after the IFFT.
To every block of the IFFT-processed signal, a CP (Cyclic Prefix) is added by the CP inserter 105. Gathering, for example, seven CP-added blocks composes one frame. An example of the frame is shown in FIG. 9. In this case, two blocks (see hatched portions) in one frame are allocated as pilot bocks for pilot symbols. Note that the pilot symbols (hereinafter also simply refereed to as "pilots") are signals known by a receiving end and are used for channel estimation for demodulation of a data channel, for example.
Meanwhile, reasons that the DFT-S-OFDM scheme is considered in the 3GPP include an improvement in frequency utilization efficiency. In third generation mobile communication schemes (hereinafter also referred to as the "3G schemes") such as W-CDMA, for a band limitation method, time-domain FIR (Finite Impulse Response) filter is used. With this method, it is difficult to perform steep band limitation and thus there is a need to perform band limitation by an FIR filter with a high roll-off rate. For example, in the 3G schemes, the symbol rate of a signal to be transmitted in a bandwidth of 5 MHz is limited to 3.84 MHz.
On the other hand, in the DFT-S-OFDM, as described above, a DFT-processed frequency-domain signal is converted to a time-domain signal using an IFFT which is larger in size than the DFT, whereby over sampling and band limitation are performed at the same time. In the configuration in FIG. 8, waveform shaping is not performed and thus it is equivalent to performing band limitation using a window function (rectangular filter) with the roll-off rate α being 0; however, as shown in FIG. 10, for example, it is also possible to perform gradual band limitation using a waveform shaping filter 106 with the roll-off rate being α>0. In an example of FIG. 10, in the case where it is assumed that the transmission bandwidth is 5 MHz, the symbol rate is lowered to 4.08 MHz and the DFT size is reduced to 272. As such, by allowing a signal which is DFT-processed by the DFT 102 to pass through the waveform shaping filter 106, gradual band limitation is performed.
An operation of a waveform shaping processing by the waveform shaping filter 106 is shown in FIG. 11. In FIG. 11, part of a DFT-processed 272-subcarrier signal (14 subcarriers at each end) is cyclically copied, whereby a signal of 300 subcarriers in total is generated. Then, by multiplying the signal by a coefficient of a raised cosine function with the roll-off rate α being 0.1, waveform shaping is performed.
As such, in the DFT-S-OFDM, merely by performing multiplication by a coefficient in a frequency-domain, waveform shaping can be performed and thus the roll-off rate α can be relatively easily changed (controlled).
Advantages of performing gradual band limitation by increasing the roll-off rate α include an effect of reduction of a PAPR (Peak to Average Power Ratio). For example, as shown in FIGS. 10 and 11, in the case where band limitation with the roll-off rate α being 0.1 is performed, the PAPR is reduced by the order of 0.5 dB as compared with the case where band limitation is performed by a rectangular filter with the roll-off rate α being 0, as shown in FIG. 8. In an uplink where transmission is performed from a terminal, by reducing the PAPR, the maximum transmission power can be increased and thus advantages such as an increase in radio wave reaching distance and an improvement in amplifier efficiency can be obtained. As such, the frequency utilization efficiency and the PAPR have a trade-off relationship.
In the DFT-S-OFDM, a DFT computation processing is required and thus generally there is a problem of an increase in circuit size. If an FFT whose number of points is a power of two can be used for a DFT, a significant reduction in circuit size is achieved; however, in practice, since parameters are designed to obtain optimum frequency utilization efficiency and PAPR characteristics, the DFT size is not always a power of two. Thus, in the DFT-S-OFDM scheme, there is a tendency that the circuit size increases.
The following Non-Patent Documents 1, 2, and 3 relate to the DFT-S-OFDM scheme which is under consideration in the 3GPP. The Non-Patent Document 1 is a document prepared at an early stage when the DFT-S-OFDM system is proposed in the 3GPP and describes basic matters regarding the DFT-S-OFDM technique. The Non-Patent Document 2 introduces a band limitation method and results of consideration of PAPR characteristics in the DFT-S-OFDM scheme. The Non-Patent Document 3 proposes adaptive control of the roll-off rate and the size of a DFT.
[Non-Patent Document 1] 3GPP, R1-050584, Motorola, "EUTRA Uplink Numerology and Design", Jun. 20-21, 2005
[Non-Patent Document 2] 3GPP, R1-050702, NTT DoCoMo, et al., "DFT-Spread OFDM with Pulse Shaping Filter in Frequency Domain in Evolved UTRA Uplink", Aug. 29-Sep. 2, 2005
[Non-Patent Document 3] 3GPP, R1-060993, NTT DoCoMo, et al., "Investigation on Adaptive Control of Roll-off Factor for DFT-Spread OFDM Based SC-FDMA in Uplink", Mar. 27-31, 2006
As described above, in the DFT-S-OFDM scheme, the PAPR and the frequency utilization efficiency have a trade-off relationship. The PAPR characteristics are known to greatly depend also on a modulation scheme. For example, in 16 QAM, the PAPR is higher than QPSK by the order of 1.0 dB.
Hence, in the case where the modulation scheme for transmission data frequently changes depending on adaptive modulation, the PAPR significantly changes and thus there is a need to perform control to suppress the PAPR to a level lower than a certain level. For example, a method may be considered in which for 16 QAM-modulated data, the PAPR is actively reduced, and for QPSK-modulated data, the frequency utilization efficiency is actively improved rather than reducing the PAPR, whereby the transmission efficiency of the entire system is improved.
Specifically, as proposed also by the Non-Patent Document 3, in the case where the modulation scheme is 16 QAM, to actively reduce the PAPR, the roll-off rate α is increased and the DFT size is reduced (e.g., as shown in FIGS. 10 and 11, the roll-off rate is set to 0.1 and the DFT size is set to 272). On the other hand, in the case where the modulation scheme is QPSK, there is no need to further reduce the PAPR and thus the roll-off rate α is reduced and the DFT size is increased (e.g., as shown in FIG. 8, the roll-off rate α is set to 0 and the DFT size is set to 300).
As such, in the DFT-S-OFDM scheme, by changing the roll-off rate α and the DFT size according to the modulation scheme, data transmission efficiency can be improved.
However, as described above, there is a problem that the circuit size of a DFT is large as compared with that of an FFT. Thus, in the case where the DFT size is changed according to the modulation scheme, a plurality of types of DFT circuits with a large size need to be provided on hardware, further increasing the impact of circuit size.


A device for correcting the phase of a vertically distorted digital picture receives picture data and a vertical phase correction signal, and assigns lines of the digital picture to a first half picture and to a second half picture. The lines of the second half picture are phase corrected with respect to the first half picture and the first and second half pictures are displayed sequentially. The phase correction is determined in response an increment signal that describes the change of an imaging factor in the veritcal direction of the digital picture on a line-by-line basis and a picture position signal indicative of whether the first half picture or the second half picture is being output.

The present invention relates to the field of video image processing, and in particular to correcting the phase of a vertically distorted digital picture, such as a digital television picture.
Television signals are often displayed using interlaced scanning. As is shown in FIG. 4, the interlaced scanning method is characterized in that the picture being displayed (full picture) is decomposed into lines, such that the lines of this full picture are divided into two temporally sequential half pictures. The lines with an originally odd line number are displayed in the first half picture, and the lines with an originally even line number are displayed in the second half picture. The standard for displaying the picture is specified in the guideline ITU-R 601.
As shown in FIG. 4, the number of lines of each of the two half pictures is half the number of lines of the full picture. A vertical decimation factor (VDEC) can be defined for the interlaced scanning method. This factor corresponds to the ratio of the number of lines of the full picture to the number of lines of the half pictures. In the example of FIG. 4, the vertical decimation factor is two (2).
FIG. 4 also shows that a phase offset PHS exists between the lines of the first half picture and those of the second half picture. This phase offset amounts to one line. In general, the phase offset is calculated as follows:
                    PHS        =                  VDEC          2                                    (        1        )            This phase offset must be taken into account at the beginning, when generating the second picture.
The preceding description assumes a vertical decimation factor VDEC that is constant over the full picture or the half picture. However, for certain applications and for displaying certain effects, it may be desirable to create digital pictures by the interlaced scanning method, with a vertical distortion that changes as a function of vertical position. For example, expansion or compression of a picture or the display of a vertical panorama effect requires a change of the vertical decimation factor or expansion factor over the picture. The vertical decimation factor VDEC thus becomes a function of the line of the half picture, i.e. VDEC=VDEC(L), where L designates the particular line of the half picture. For displaying other effects, it is also conceivable to make the vertical decimation factor also dependent on other parameters, for example the pixel position, et cetera. However, to calculate a phase correction factor for the second half picture, so as to take into account the phase offset between the second half picture and the first half picture, only the vertical decimation factor VDEC on the line is relevant. The following therefore holds for the phase offset:
                              PHS                                (            1            )                          =                              VDEC                                      (              1              )                                2                                    (        2        )            It is necessary to perform a phase correction for the second half picture, since otherwise an undesirable picture distortion, which is perceived as interference, occurs in the vertical direction during the course of the picture.
There is a need for a system and method of correcting the phase of a vertically distorted digital picture.

Method and device for phase correction of a vertically distorted digital image


An organic vehicle for electronic paste compositions is provided. The organic vehicle contains organo-soluble hydroxyalkyl substituted polysaccharide, a solvent for the polysaccharide, two hydrogen bonding components and inorganic oxide particulates having a surface area of at least 50 m.sup.2 /g.

The electronics industry uses particulate-based high-solids pastes in a variety of applications to ultimately provide conductive or dielectric capability in an electronic component. These pastes typically contain inorganic particles and an organic medium or vehicle. The inorganic particles provide the electrical functionality in the ultimate application, i.e., insulative or non-conducting inorganic particles form dielectric parts and conductive inorganic particles, primarily metals, form conductive parts. The organic medium facilitates application and control of the location of the inorganic particles.
After application of the paste, the organic medium is removed by heating and the inorganic particles are sintered or reflowed to form the electrically functional part. To apply the paste to the desired locations in the desired patterns, it is necessary that the paste flow well with the application method employed, such as stencil or screen printing, pressure dispensing etc.
A flow modifying agent or agents is typically included in the paste formulation for the paste to have the appropriate rheology or flow characteristics. Particularly desirable rheological characteristics of the paste include high viscosity, which precludes separation or settling of the inorganic particulate in the paste, dripping, stringiness, and slumping or sagging; plastic flow, which provides shear thinning with a well defined yield point for improved printing characteristics; sufficient tackiness to hold components; good transfer through the printing pattern; and clean release from the screen or stencil.
Effective amounts of flow modifiers, other organic ingredients, and acidic and/or basic activators, are typically so high that the organic ingredients leave a substantial residue on the solder after reflow. For example, rosin is typically present in a solder paste in the amount of by weight 25% or greater by weight in a solder paste vehicle. For thick film paste, ethyl cellulose, as a flow modifier, is typically present in the amount of 1-3% by weight of the paste. This amount of flow modifier leaves a substantial, readily visible and potentially solder-coating residue. It is necessary to wash off the residues since the residues contain various ionic contaminants and other chemical agents which can cause shorting and product failures over time.
Despite the undesirability of these residues, they have been of little concern until recently because chlorofluorocarbon solvents effectively and easily remove the residues. Today, however, considerable efforts are being made to replace such chlorofluorocarbon solvents due to their environmental impact upon the stratosphere. In addition, the failure of cleaning agents to completely remove residues from tight, hard-to-reach spots, and from under components in surface mount or fine pitch assembly operations, makes current methods and proposed alternative cleaners less effective.
Electronic pastes have been disclosed containing a polysaccharide, polysaccharide solvent and polyhydroxylated polysaccharide non-solvent, and optionally, an activator. However, these compositions have been known to be unsatisfactory due to screen plugging, slumping or poor print definition.
Therefore, it is an object of this invention to provide an electronic paste composition in which desirable rheological and flow properties of the paste are achieved with controllable intermolecular interactions. It is also an object of this invention to provide a vehicle for a solder paste which after the solder paste is reflowed leaves a residue that is negligible and innocuous so that no cleaning is necessary.


The display driver includes an image memory which is configured by including a plurality of memory mats, a plurality of power supply switches which can perform an ON and OFF control of power supply to each of the plurality of memory mats, and a control circuit which turns on or off the power supply switches. The control circuit turns on the plurality of power supply switches in such a manner that the power supply to the memory mat to which the image data is written at an initial time, among the plurality of memory mats, becomes stable earlier than the power supply to the other memory mats.

1. Field of the Invention
The present invention relates to a display driver, and particularly to a display driver which can be appropriately used in a display driver Integrated Circuit (IC) with a built-in image memory.
2. Background Art
In a display driver, on which a Static Random Access Memory (SRAM) that is an image memory is mounted, for example, a Liquid Crystal Display (LCD) driver, and in a product to which a process rule using a process technology equal to or greater than 130 nm is applied, an off-leakage of a Metal Oxide Semiconductor (MOS) transistor is small enough, and a leakage current flowing through the whole SRAM is small enough compared to operation power of the LCD driver, and thus influence on a consumption current of the whole LCD driver is small to a negligible degree. Recently, as the number of pixels of the LCD panel is increased, memory capacity of the SRAM mounted on the LCD driver is increased in class by several tens of Mbit, and process shrinking is underway for chip size reduction. For example, in case that a process moves from a 130 nm process to a 90 nm process, a power supply voltage is lowered from 1.5 V to 1.3 V in relation to a breakdown voltage of the MOS transistor, but at the same time, the MOS transistor performance is maintained, and thus a threshold voltage (Vth) is also required to decrease. As a result, a problem happens that the off-leakage current of the SRAM increases and the consumption current of the whole LCD driver increases to a degree that cannot be ignored.
In JP-A-2008-191442, a technology is disclosed which decreases the off-leakage current of a memory mounted on the display driver IC and makes stable a normal operation of the memory. Depending on which operation mode of a normal operation mode and a stand-by mode is selected for the display driver IC, an ON and OFF control of a switch transistor connected to a power supply of the memory is performed, power supply delivery to an unnecessary portion is cut off, and the off-leakage current is reduced. In the switch transistor, the power supply of a voltage which is higher to a degree where a voltage drop generated by the switch transistor can be compensated for, is connected thereto, and thereby the power supply of the memory itself can be maintained to a high value, and the normal operation of the memory can become stable.


An ironing ring for use in a press for ironing pressing or drawing of a workpiece. The ironing ring has a work surface which, upon deforming the workpiece, contacts the workpiece, and causes flowing of the workpiece material. In order to prevent friction deposits in the region of the work surface of the ironing ring, a microstructure, differing from the roughness of the work surface, is introduced into the work surface, which forms elevations and/or recesses in the work surface. Material particles remaining on the work surface after the deforming of a workpiece thus adhere less strongly to the work surface and can be stripped off during the next deforming process.

The invention relates to an ironing ring for use in a press for ironing pressing of a workpiece.
Such ironing rings have been known per se. In a press for ironing pressing or drawing a workpiece, for example a cup, several such ironing rings are successively arranged, as a rule, in the direction of the working stroke in order to intermittently or incrementally reduce the outside diameter of the workpiece. As a result of this, it is possible, for example, to ultimately form a hollow cylindrical can body from a cup.
During the deforming process, a radially inward facing work surface of the ironing ring comes into contact with the workpiece. Depending on the material of the workpiece, more or less viscous, smeary material build-up or friction deposits occurs. This phenomenon is known. Nowadays, the ironing rings are therefore deinstalled from the press after a certain number of deforming processes, cleaned and subsequently reinstalled. This is labor-intensive and expensive and has caused the shutdown of the press.
In order to avoid friction deposits, publication DE 22 56 334 A1 discloses the possibility of applying a special lubricant to the ironing ring or the workpiece. However, such lubricants must subsequently be removed again from the deformed workpiece. This option is labor-intensive and expensive as well. Publication DE 22 56 334 A1 suggests that the ironing ring be made of ceramic material. However, if pressure is suddenly removed from the ceramic ironing ring, fissures may form, this being prevented according to DE 22 56 334 A1 in that the end region of the workpiece may immerse into a recess on the ironing stamp in order to avoid the sudden removal of pressure from the ceramic ironing ring.
Considering this, the object of the present invention may be viewed to be an ironing ring in which the risk of friction deposits is reduced and which does not require any design changes on other press components.


A semiconductor device is disclosed that can form contacts with ease even if the distance between adjacent gate electrodes is reduced in accordance with larger scale integration of semiconductor devices. The semiconductor device includes a polysilicon pad 8c connected to impurity implanted layers 5a and 7a, formed over sidewalls 6a and 6b of gate electrodes 3a and 3b and insulating films 4a and 4b; and a polysilicon pad 11a connected to impurity implanted layers 5b and 7b, formed over polysilicon pad 8c with an insulating film 9 and sidewalls 10b therebetween. Even if elements are miniaturized to have reduced gate electrode length and gate electrode distance in accordance with larger scale integration of a semiconductor device, polysilicon pads 8c and 11a can be formed with ease between impurity implanted layers 5a, 7a and an upper layer wiring 13a, and between impurity implanted layers 5b, 7b and an upper layer wiring 13b, respectively. Thus, contact holes 15a and 15b can be formed without difficulty for forming upper layer wirings 13a and 13b, even if semiconductor devices are increased to larger scale integration.

1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device applicable to a peripheral circuit of a DRAM (Dynamic Random Access Memory), and a method of manufacturing thereof.
2. Description of the Background Art
In recent years, the demand for semiconductor memory devices are rapidly increasing due to the remarkable spread of information equipment of computers. Semiconductor memory devices having large functional storage capacity and capable of high speed operation are required. Accordingly, developments in techniques are carried out regarding high density integration, quick response, and high reliability of semiconductor memory devices.
A DRAM in semiconductor memory devices is known as being capable of random input/output of storage information. A DRAM usually comprises a memory cell array which is the storage region for storing a plurality of storage information, and a peripheral circuit required for input from and output to an external source. FIG. 3 is a block diagram showing a general DRAM structure. Referring to FIG. 3, a DRAM 50 comprises a memory cell array 51 for storing data signal of storage information, a row-and-column address buffer 52 for receiving external address signals to select memory cells forming a unit storage circuit, a row decoder 53 and a column decoder 54 for specifying a memory cell by decoding the address signal, a sense refresh amplifier 55 for amplifying and reading out the signal stored in the specified memory cell, a data-in buffer 56 and a data-out buffer 57 for data input/output, and a clock generator 58 for generating a clock signal.
The memory cell array 51 occupying a large area on the semiconductor chip has a plurality of memory cells for storing unit storage information arranged in a matrix manner. A memory cell is generally implemented with one MOS transistor and one capacitor connected thereof. This memory cell is well known as a one-transistor one-capacitor type memory cell. Such memory cells are widely used for large capacity DRAMs because of its simple structure contributing to the improvement in integration of the memory cell array.
According to the large storage capacity of DRAMs, high integration is required in memory cell array 51. Row decoder 53 adjacent to memory cell array 51, sense refresh amplifier 55, and column decoder 54 of the peripheral circuit are formed to comply with the dimension of memory cell array 51. Therefore, larger scale integration is required in the above mentioned row decoder 53 and the like according to the increased scale of integration of memory cell array 51. Great increase in integration density is not required for row-and-column address buffer 52 of the peripheral circuit which is not adjacent to memory cell array 51, even if memory cell array 51 is increased in integration density.
FIG. 4 is a sectional view showing a contact structure of a row decoder forming a peripheral circuit of a conventional DRAM. Referring to FIG. 4, a row decoder 53 forming a peripheral circuit of a DRAM comprises a semiconductor substrate 1; element isolation regions 2a and 2b for isolating elements formed on semiconductor substrate 1; impurity implanted layers 5a, 7a and 5b, 7b formed in the region enclosed by element isolation regions 2a and 2b with a predetermined distance therebetween; gate electrodes 3a and 3c formed directly on element isolation regions 2a and 2b, respectively; a gate electrode 3b formed between impurity implanted layers 5a, 7a and 5b and 7b with a gate insulating film 14 thereunder; sidewalls 6a, 6b, and 6c formed at the sidewalls of gate electrodes 3a, 3b and 3c; insulating films 4a, 4b and 4c formed over gate electrodes 3a, 3b and 3c, respectively; a polysilicon pad 8a of electrode material connected to impurity implanted layers 5a and 7a, and formed at the sides of and over gate electrodes 3a and 3b with sidewalls 6a and 6b and insulating films 4a and 4b therebetween; a polysilicon pad 8b connected to impurity implanted layers 5b and 7b, and formed at the sidewalls of and over gate electrodes 3b and 3c with sidewalls 6b and 6c and insulating films 4b and 4c therebetween; an interlayer insulating film 12 formed all over semiconductor substrate 1 with contact holes 15a and 15b formed above polysilicon pads 8a and 8b, respectively; an upper layer wiring 13a formed on interlayer insulating film 12 and within contact hole 15a to contact polysilicon pad 8a; and an upper layer wiring 13b formed on interlayer insulating film 12 and within contact hole 15b to contact polysilicon pad 8b.
Row decoder 53 implementing the peripheral circuit of a conventional DRAM is provided with polysilicon pads 8a and 8b between upper layer wirings 13a and 13b and impurity implanted layers 5a, 7a, and 5b, 7b, respectively. The formation of polysilicon pads 8a and 8b simplifies the process of forming upper layer wirings 13a and 13b to solve difficulties encountered in the manufacturing process.
If polysilicon pads 8a and 8b are not provided, it is necessary to contact upper layer wirings 13a and 13b directly to impurity implanted layers 7a and 7b, respectively. The surface area of the connecting region between impurity implanted layers 7a and 7b and upper layer wirings 13a and 13b are reduced in accordance with the scale of element integration increased. The magnitude of contact holes 15a and 15b that can be formed in interlayer insulating film 12 is limited due to manufacturing techniques. It is difficult to form contact holes 15a and 15b smaller than a certain dimension. If the area of the above-mentioned connecting region becomes smaller than the most minimum contact holes 15a and 15b allowable under the manufacturing technology, it is difficult to form contact holes 15a and 15b through to the surface of the connecting regions. This also results in difficulty in forming upper layer wirings 13a and 13b. This problem is overcome by forming polysilicon pads 8a and 8b between upper layer wirings 13a and 13b and impurity implanted layers 7a and 7b, respectively, to assist the formation of contact holes 15a and 15b above polysilicon pads 8a and 8b, whereby upper layer wirings 13a and 13b can be formed with ease. Polysilicon pads 8a and 8b are indispensable where elements are highly integrated to reduce the surface area of the connecting region between upper layer wirings 13a and 13b and impurity implanted layers 7a and 7b.
FIGS. 5A-5F are sectional views of the structure of the row decoder of the DRAM of FIG. 4 for explaining the manufacturing process.
Referring to FIG. 5A, element isolation regions 2a and 2b are selectively formed on semiconductor substrate 1. Referring to FIG. 5B, gate insulating film 14 is formed by thermal oxidation. An electrode material 3 such as of polysilicon doped with impurities is deposited on gate insulating film 14. Insulating film 4 such as of silicon oxide film is deposited over electrode material 3. Electrode material 3 and insulating film 4 are removed by photolithography and etching, leaving only the portion where gate electrodes 3a, 3b and 3c are formed. Ions having a conductivity type opposite to that of semiconductor substrate 1 are implanted into semiconductor substrate 1 to form impurity implanted layers 5a and 5b. Referring to FIG. 5d, an insulating film (not shown) such as of silicon oxide film is deposited all over semiconductor substrate 1 and etched back to form sidewalls 6a, 6b and 6c. Then, ions of a conductivity type opposite to that of semiconductor substrate 1 are implanted between the adjacent gate electrodes on semiconductor substrate 1 to form impurity implanted layers 7a and 7b. Referring to FIG. 5E, a material 8 having conductivity is formed over impurity implanted layers 5a, 7a and 5b, 7b. Referring to FIG. 5F, polysilicon pads 8a and 8b are formed by patterning material 8 having conductivity. Interlayer insulating film 12 is deposited all over the surface, and contact holes 15a and 15b are formed. Lastly, upper layer wirings 13a and 13b are formed above interlayer insulating film 12 and within contact holes 15a and 15b, as shown in FIG. 4.
As mentioned in the foregoing, the row decoder forming the peripheral circuit of a conventional DRAM is provided with polysilicon pads 8a and 8b between upper layer wirings 13a and 13b and impurity implanted layers 5a, 7a, and 5b, 7b to ease the formation of upper layer wirings 13a and 13b. High integration is required for row decoders according to the scale of integration increased in DRAMs. Therefore, elements implementing a row decoder are miniaturized to shorten the length of the gate electrode itself and the distance between adjacent gate electrodes. This causes an inconvenience that the conventional manner of photolithographing and etching polysilicon pads 8a and 8b above gate electrode 3b becomes difficult to carry out. The miniaturization of elements led to a problem that polysilicon pads can be formed only with difficulty. Even if polysilicon pads could be formed in cases where elements are miniaturized, it was difficult to accurately form the upper layer wirings on the polysilicon pads, resulting in the following inconvenience. That is to say, there was possibility of the upper layer wiring and the gate electrode being short-circuited due to one portion of the upper layer wiring formed directly on the gate electrode. There was also an inconvenience that it was necessary to reduce the contact inside diameter of the contact hole when silicon pads can not be formed. This resulted in difficulty in performing photolithography and etching for forming contact holes.
In conventional DRAMs, it was difficult to form a polysilicon pad as a conductive layer between a wiring layer and an impurity region, whereby contacts could not be formed with ease when elements are miniaturized according to larger scale integration of semiconductor device with reduced distance between adjacent gate electrodes.

Semiconductor device having contact between wiring layer and impurity region


A system includes multiple protection modules. Each protection module includes monitoring terminals that monitor battery cells' status, an output terminal that outputs a protection signal if an abnormal condition in the cells is detected, a switching terminal that receives a switching signal, and detection circuitry that switches from a normal-working mode to a fast-test mode if receiving the switching signal, delays outputting the protection signal for a first time interval if the abnormal condition is detected in the normal-working mode, and delays outputting the protection signal for a second time interval, less than the first time interval, if the abnormal condition is detected in the fast-test mode. In the protection modules, the switching terminal of a first protection module and a monitoring terminal of the first protection module are coupled to a second protection module and receive a protection signal from the output terminal of the second protection module.

FIG. 1 illustrates a circuit diagram of a conventional battery protection system 100. As shown in FIG. 1, the protection system 100 includes a primary protection module 108 and a secondary protection module 102. The primary protection module 108 protects the battery cells 104 from an over- or under-voltage condition, over-current condition, short circuit condition, and over- or under-temperature condition. If the primary protection module 108 does not function, e.g., it breaks down, then the secondary protection module 102 provides backup protection to the battery cells 104. For example, when the battery cells 104 are charged by a charger (not shown) that is coupled to the terminals PACK+ and PACK−, if the secondary protection module 102 detects an abnormal condition in the battery cells 104, then the protection module 102 generates a protection signal 110 to turn on the switch MN1 to burn the fuse 106 such that the battery cells 104 are disconnected from the charger. Additionally, in order to avoid a false indication of an abnormal condition, when the protection module 102 detects a sign of an abnormal condition in the battery cells 104, the protection module 102 delays outputting the protection signal 110 for a preset time interval ΔT1 (e.g., one, two, or four seconds). If the protection module 102 determines that the abnormal status lasts for the preset time interval ΔT1, then the protection module 102 confirms that an abnormal condition has occurred in the battery cells 104.
The protection system 100 is used to protect a battery pack that includes a small number, e.g., five, of battery cells. In order to protect a battery pack that includes more than five battery cells, two or more of the secondary protection modules 102 are used.
FIG. 2A illustrates a circuit diagram of a conventional battery protection system 200A that includes secondary protection modules 202 and 212. As shown in FIG. 2A, the protection module 202 (hereinafter, the low-side module) monitors the battery cells 204, and the protection module 212 (hereinafter, the high-side module) monitors the battery cells 214. If a sign of an abnormal condition in the battery cells 204 is detected, then the low-side module 202 starts to count time. After a preset time interval ΔT1 (e.g., one, two, or four seconds), if the low-side module 202 confirms that an abnormal condition is present in the battery cells 204, then the low-side module 202 outputs a protection signal 210 to burn the fuse 206. Similarly, if a sign of an abnormal condition in the other set of battery cells 214 is detected, then the high-side module 212 outputs a protection signal 216 after the preset time interval ΔT1. As shown in FIG. 2A, the low-side module 202 receives, at its monitoring terminal BAT5, the protection signal 216 from the high-side module 212, and generates the protection signal 210 to burn the fuse 206 in response to the protection signal 216. Thus, the battery protection system 200A can protect both sets of the battery cells 204 and 214 from an abnormal condition.
However, when the low-side module 202 receives the protection signal 216 from the high-side module 212, the low-side module 202 also delays outputting the protection signal 210 for the preset time interval ΔT1. Thus, there is a time delay ΔT2 that is twice the preset time interval ΔT1 (ΔT2=2*ΔT1) from the detection of an abnormal condition in the battery cells 214 until the protection signal 210 is output. The time delay ΔT2 may be too long, and consequently the protection system 200A may not be able to protect the battery cells 214 in time.
FIG. 2B illustrates a circuit diagram of another conventional battery protection system 200B. The battery protection system 200B is similar to the battery protection system 200A except that in the battery protection system 200B, the protection signal 216 from the high-side module 212 is output to control a switch MN2, instead of being output to the low-side module 202. Thus, if an abnormal condition in the battery cells 214 is detected, then the high-side module 212 outputs a protection signal 216 to turn on the switch MN2 to burn the fuse 206. The high-side module 212 delays outputting the protection signal 216 for a preset time interval ΔT1. Additionally, the battery protection system 200B includes resistors R1, R2, R4, R5, R6, and switches MN1 and MP1, and these elements constitute a level shifter. More specifically, if an abnormal condition in the battery cells 204 is detected, then the low-side module 202 outputs a protection signal 210. The level shifter shifts a voltage level of the protection signal 210 to a higher voltage level to turn on the switch MN2 to burn the fuse 206. For example, the protection signal 210 turns on the switch MN1 to pull down a gate voltage of the switch MP1. Accordingly, the switch MP1 is turned on to pull up a gate voltage of the switch MN2. Thus, the switch MN2 is turned on to burn the fuse 206. The low-side module 202 also delays outputting the protection signal 210 for the preset time interval ΔT1. Thus, compared with the battery protection system 200A in FIG. 2A, the battery protection system 200B may better protect the battery cells 214.
However, because the level shifter includes the resistors R1, R2, R4, R5, R6, and the switches MN1 and MP1, the cost, size, and power consumption of the PCB (printed circuit board) for the protection system 200B are increased.
Thus, a battery protection system that addresses the abovementioned shortcomings would be beneficial.


An overlay mark is described, including a portion of a lower layer having two x-directional and two y-directional bar-like patterns therein, and two x-directional and two y-directional photoresist bars defined by the lithography process for defining an upper layer and surrounded by the bar-like patterns. At least one of the patterning process for defining the lower layer and the above lithography process includes two exposure steps respectively for defining a first device area and a second device area. When the patterning process includes two exposure steps, one x-directional and one y-directional bar-like patterns are defined simultaneously and the other x-directional and the other y-directional bar-like patterns are defined simultaneously. When the lithography process includes two exposure steps, one x-directional and one y-directional photoresist bars are defined simultaneously and the other x-directional and the other y-directional photoresist bars are defined simultaneously.

1. Field of the Invention
This invention relates to an overlay mark used in IC processes, and more particularly, to an overlay mark for checking the alignment accuracy between a lower layer and a lithography process for defining an upper layer, a method for forming the same, and the application of the same in alignment accuracy checking.
2. Description of the Related Art
As the linewidth of the IC process continuously gets narrower, the alignment accuracy between a lower layer and an upper layer becomes more and more important. Therefore, an overlay mark is generally formed on a wafer for checking the alignment accuracy, wherein the most popular type of overlay mark is the so-called box-in-box (BIB) overlay mark.
A conventional BIB overlay mark is applied to cases where the lower and the upper layers each is defined by a single photomask, including four trenches in a portion of the lower layer that define a first rectangle, and four photoresist bars on the portion of the lower layer that define a second rectangle and are formed in the lithography process for defining the upper layer and surrounded by the four trenches. The four trenches are defined by a single photomask having thereon a corresponding 4-trench pattern, the four photoresist bars are defined by another single photomask having thereon a corresponding 4-bar pattern. By measuring the position of the center of the first rectangle relative to that of the second rectangle, the alignment accuracy between the lower and the upper layers can be derived.
On the other hand, as the process window gets narrower, it is more important to control the critical dimension of the semiconductor device. When an IC process need to form two areas of different pattern arrangements for a layer, two exposure steps constituting a double exposure process are usually performed to the photoresist layer in respective areas to assure that the two areas are defined in predetermined critical dimensions. When at least one of the two patterning process respectively for defining the above lower and upper layers includes two exposure steps using two photomasks, the above-mentioned conventional overlay mark is no longer suitable to use.

Overlay mark, and fabrication and application of the same


Data to be transmitted is converted into symbols using a plurality of data-to-symbol conversion processes. The symbols from these processes are then time-division multiplexed. Advantageously, at least one of these conversion processes incorporate coding in a manner which provides the same degree of error protection for each process. In the disclosed embodiments, the data originates from two independent sources and the data from each source is converted into symbols using a different data-to-symbol conversion process.

In many digital data applications, the transmitted data is converted into symbols in accordance with a predetermined process and the resulting set of all possible symbols from such a conversion process forms a signal constellation. There are many different conversion processes and signal constellations. For a symbol transmission rate, the data-carrying capacity of the data-to-symbol conversion process is directly proportional to amount of data represented by one symbol. Moreover, the greater the amount of digital data represented by one symbol, the greater the number of possible symbols. In most communications applications, the maximum power which can be transmitted is constrained and, as a result, as the number of possible symbols increases the separation between symbols decreases. Without the use of error correction schemes, the ability to recover the data after transmission through a noisy channel generally decreases with a decrease in the separation between symbols.
Many communications systems utilize a single data-to-symbol conversion process after a communications connection is established. For example, in most modems, during the "handshaking" process prior to data transmission, a particular data-to-symbol conversion process is agreed upon between the communicating modems and this process is maintained for the duration of the communications connection. In other system applications, the data-to-symbol conversion process may be varied during the communications connection in response to a determination of the data recovery error rate. That is, if the data error rate increases, the data-to-symbol conversion process can be altered so as to increase the separation between symbols and, therefore, decrease the likelihood of data recovery errors. In such arrangements, the change from one data-to-symbol conversion process to another occurs aperiodically.
More recently, in U.S. Pat. No. 5,214,656, issued May 25, 1993, two data-to-symbol conversion processes are used. More specifically, certain bits, which are deemed more important than other bits, are converted into symbols lying in a first signal constellation using a first data-to-symbol conversion process. This process provides greater error protection than a second data-to-symbol conversion process which converts the other bits into symbols in a second signal constellation. The symbols generated by each process are then transmitted in a time-division-multiplexed fashion. While this technique works satisfactorily, there are systems applications, such as the Asymmetric Digital Subscriber Line (ADSL), which require equal error protection for all transmitted data and which impose maximum delay requirements on certain transmitted data. In light of the expected widespread use of systems such as ADSL, it would be highly desirable if the above-described shortcomings of the prior art could be eliminated.

Signal constellation time division multiplexing arrangement