A high density plasma chemical vapor deposition (HDPCVD) process is disclosed. First, a first deposition step is performed on a wafer. Then, the wafer is rotated with an angle. A second deposition step is performed for completing the deposition. By the rotation of the wafer, the thin film is formed with a desired uniformity.

1. Field of the Invention
The present invention relates to a semiconductor process, and more particularly to a high density plasma chemical vapor deposition process and a method for improving uniformity of thickness of a thin film.
2. Description of the Related Art
In semiconductor manufacturing process, chemical vapor deposition (CVD) is a widely used technique for forming thin films. It usually includes atmospheric CVD (APCVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD) and high density plasma CVD (HDPCVD). The film formed by HDPCVD is denser, more capable of preventing moisture penetration and more uniform than those formed by the other techniques. With the advancement of semiconductor technology, devices in integrated circuits becomes more compact. The gap-fill ability of HDPCVD for devices is better than those of the other techniques. Accordingly, HDPCVD has become a core technique for sub-micron semiconductor technology.
HDPCVD process should be performed at the deposition systems in the reaction chambers. During a thin film deposition, reaction gases are released from gas output holes and diffuse to the wafer for forming a thin film thereon. For example, a deposition system manufactured by Novellus, Corp. comprises eight gas output holes. These gas output holes are allocated in the chamber around the wafer. During the thin film deposition, reaction gases are released from these eight gas output holes for forming the thin film on the wafer.
Due to different distances from these gas output holes to different areas of the wafer, the thickness of the thin film formed by the deposition system manufactured by Novellus Corp. is not uniform at the edge of the wafer, i.e. near to these gas output holes. The non-uniformity of thickness results in wave patterns at the edge of the wafer as shown in FIG. 1. The reason of causing the wave patterns is that the reaction gases cannot uniformly diffuse to different areas of the wafer and the non-uniformity leads to different accumulations of the reaction gases on different areas of the wafer. Accordingly, a thinner film is formed along the direction 100 of the gas output holes as shown in FIG. 1. A thicker film, however, is formed on the other areas 102 as shown in FIG. 1. The wave-pattern issue becomes worsen at the region closer to these gas output holes. The wave-pattern issue causes non-uniformity of thickness of the thin film and affects the characteristics of the thin film.

HDPCVD process and method for improving uniformity of film thickness


A portable computing device has a computer programmed to store and communicate information and a housing configured to house the computer. A communications device, provided in the housing, is controlled by the computer and configured to communicate information between the computing device and a remote computer. An antenna is carried by the housing and is configurable to electrically couple with the communications device for communicating radio frequency information with the remote computer. A signal coupling device is carried by the housing and is configured to removably mate in signal transmitting relation with an external antenna via a complementary mating signal coupling device. A switch provided with the device is constructed and arranged to selectively connect the communications device with one of the dedicated antenna and the external antenna. According to one aspect, this invention comprises a portable electronic communications device, comprising a radio frequency modem, wireless communications circuitry, and an antenna operable to communicate over a wireless communications link with one of a local area network and a wide area network; and a proximity detection device operable to detect proximity of the device with the local area network, the wireless communications circuitry responsive to detection of the device within suitable signal communication proximity with the local area network to couple the communications circuitry with the local area network.

Portable electronic devices, such as laptop and notebook computers, dataform readers, barcode readers, portable data terminals, work slates, pen computers, portable electrical testing devices, and touch screen displays typically require the ability to communicate data with an external device. Due to the portability of these devices, they are typically remotely powered by a battery pack, enabling their use without connection to power supply or communication lines. Typically, such devices are equipped with one or more forms of memory and an I/O port, enabling intermittent hook-up to a data communications network for transmitting and receiving information therebetween. Additionally, an AC power supply is frequently provided via a power supply port for intermittently connecting the device to a separate power supply during operation, or for recharging batteries contained therein.
One technique for transferring data and/or verbally communicating with an electronic device such as a computer system involves connecting the device to a public switched telephone network (PSTN) via a telephone modem. For example, a telephone modem, short for modulator/demodulator, is often used on a computer and consists of a communications device that enables the computer to transmit information over a standard telephone line. An RJ-11 jack and connector enable coupling of the computer and modem with a telephone line. The modem converts the digitally formatted information of a computer into an analog signal that is capable of being carried over the telephone line to another computer. The receiving computer has a modem that transfers the analog signal transmitted over the telephone line back into a digital signal usable by the receiving computer. Typically, the modem modulates a computer's digital signal onto a continuous carrier frequency over the telephone line. When receiving, the modem demodulates the information from the carrier, transferring it into digital form for use by the computer. However, it is sometimes inconvenient to utilize a telephone line for coupling together computer systems. In some cases, a hard wire telephone line is not available to a user for use with the computer. For other cases, the computer or electronic device is required to communicate frequently and intermittently with another computer, which would require frequent coupling and decoupling of a telephone line with a jack on the computer to enable portable movement of the computer and subsequent connection after each cycle of use.
According to another way, some portable electronic devices have a dedicated antenna, a cellular radio telephone, and a cellular radio modem configured to enable communication between the device and an external communication device. For example, portable cellular telephones have self-contained antennas for enabling communication with other similar devices via a cellular network. Additionally, laptop and notebook computers have been configured to couple with a cellular telephone via a PCMCIA slot and a connector to enable transmission of data via a cellular modem between the notebook computer and another communications device. However, cellular telephone airtime can be very expensive. Therefore, there is a need for a way to reduce cellular airtime when sending and receiving data in order to reduce cellular airtime charges.
One attempt to reduce cellular airtime costs, or charges, when sending data has been to implement packet data service for first and second generation cellular systems such as the Cellular Digital Packet Data (CDPD) standard. CDPD provides mobile packet data connectivity via an AMPS channel on a shared basis. Since users are charged on a packet-by-packet basis, CDPD typically transfers data at reduced cost. CDPD coexists with a conventional voice-only cellular system such as AMPS, but it capitalizes on the unused air time which occurs between successive radio channel assignments by the Mobile Switching Center (MSC). However, many applications still require that a considerable amount of data and/or voice communication be implemented. For example, warehouse personnel performing inventory analysis and/or processing orders in a warehouse with portable computing devices having wireless communications capabilities still must transfer a large amount of data, incurring substantial cellular connection charges. Therefore, there is a need to reduce commercial cellular connection charges when performing data/voice transmissions within a defined geographic location such as a warehouse or factory.
The present invention relates to an improved portable electronic device having wireless communications features that minimize use of commercial cellular networks when transmitting data/voice between the device and another device.

Portable electronic communications device having switchable LAN/WAN wireless communications features


A golf head includes a hollow head body defining a front opening and having a reinforcing portion that is made from a non-metal material, a striking plate received in the front opening and secured to the head body, and a plurality of first reinforcing metal ribs embedded securely in the reinforcing portion of the head body.

1. Field of the Invention
This invention relates to a golf head, more particularly to a golf head with a plurality of reinforcing metal ribs embedded in a non-metal portion of the golf head.
2. Description of the Related Art
Conventional golf heads can be classified into iron head, wood head, and putter head. The body of the wood head is normally made from carbon fiber which tends to deform undesirably after a period of use. In addition, due to a relatively high absorption of sound by the carbon fiber, the striking sound produced by striking a golf ball is too low and is not appealing to the user.


To estimate an amount of reducing agent adsorbed to a selective reduction type NOx catalyst with a higher degree of precision, an amount of variation over a predetermined time in a reducing agent amount adsorbed to a selective reduction type NOx catalyst is calculated from an upper limit value of a reducing agent amount that is adsorbed to the selective reduction type NOx catalyst when the reducing agent is supplied continuously by a supply unit, which is calculated on the basis of a temperature of the selective reduction type NOx catalyst, and the reducing agent amount adsorbed to the selective reduction type NOx catalyst, whereupon a reducing agent amount adsorbed to the selective reduction type NOx catalyst following the elapse of the predetermined time is estimated by adding the variation amount to the reducing agent amount adsorbed to the selective reduction type NOx catalyst.

Patent Document 1 describes providing a selective reduction type NOx catalyst (also referred to hereafter as an SCR catalyst) that selectively reduces NOx contained in exhaust gas by adsorbing ammonia (NH3) in an exhaust passage of an internal combustion engine, and calculating an amount of ammonia consumed by the SCR catalyst on the basis of an amount of NOx discharged from the internal combustion engine and a NOx purification ratio of the SCR catalyst. Further, Patent Document 1 describes calculating an amount of ammonia adsorbed to the SCR catalyst in accordance with the amount of consumed ammonia and an amount of added reducing agent, and adjusting the amount of added reducing agent in accordance with the adsorption amount.
Incidentally, the ammonia adsorbed to the SCR catalyst may decrease even when NOx is not purified thereby. For example, when a temperature of the SCR catalyst increases, ammonia is desorbed from the SCR catalyst, and therefore the amount of ammonia adsorbed to the SCR catalyst decreases. Hence, an estimated value of the amount of ammonia adsorbed to the SCR catalyst may be larger than an actual value. When the amount of added reducing agent is adjusted in accordance with the estimated value, therefore, the amount of added reducing agent may be inappropriate.

Exhaust gas purification apparatus for internal combustion engine


Silicon fins are formed in a bulk silicon substrate and thereafter trench isolation regions are formed between each silicon fin. The silicon fins in nFET and pFET device regions are then recessed. A relaxed silicon germanium alloy fin portion is formed on a topmost surface of each recessed silicon fin portion or on exposed surface of the substrate. A compressively strained silicon germanium alloy fin portion is formed on each relaxed silicon germanium alloy fin portion within the pFET device region, and a strained silicon-containing fin portion is formed on each relaxed silicon germanium alloy fin portion within the nFET device region. Sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile strained silicon-containing fin portion are then exposed. A functional gate structure is provided on the exposed sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile strained silicon-containing fin portion.

The present application relates to a non-planar semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure containing tensile strained silicon-containing fins for n-type FETs and compressive strained silicon germanium alloy fins for p-type FETs.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (finFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Semiconductor fin field effect transistors (FETs) can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs. In order to extend these devices for multiple technology nodes, there is a need to boost the performance with high mobility channels and stressor elements.

Dual channel material for finFET for high performance CMOS

International Business Machines Corporation


A method for controlling current fluctuations during read and program operations in a memory structure is provided. The method includes applying a first voltage to a first gate of a word line decoder transistor. The method further includes applying a second voltage to a second gate of a bit line decoder transistor such that the first voltage is greater than the second voltage. The method also includes maintaining the source voltage of the bit line decoder transistor at about zero.

The present invention relates generally to memory devices and, more particularly, to a method for controlling current fluctuation during read and program operations.
Conventional memory architectures employ word lines and bit lines to access the memory cells defined by the memory architecture. Three dimensional (3D) memory structures include several memory layers that are stacked one on top of the other. FIG. 1 illustrates a 3 dimensional memory structure. The memory structure includes word lines 12 and bit lines 10. The word lines (WL) and the bit lines (BL) are connected to word line and bit line decoder transistors 14. The bit lines 10 are connected to programmable diodes 16. During read and program operations the decoder transistors 14 select the bit line and the read line corresponding to a memory cell to be accessed (not shown). In a 3D memory structure as shown in FIG. 1, the layer decoder transistors are employed in both the WL and the BL for the selection layers. Therefore, the equivalent circuit can be treated as two MOSFETs connected by a programmable diode 16 and a series resistor (not shown). Generally, the decoder transistors 14 act as switches. When the transistor is turned on, a high gate voltage (VG) is applied so that the MOSFET will be in a low-resistance status. As a result, the MOSFET will act like a switch.
Generally, a read or program operation is carried out by applying constant high voltages to the selected WL and BL. However, the diode-current during the read operation varies exponentially with the voltage. Hence, a small device variation or the loading effect due to the series resistance of WL and BL may cause large variations in the current during the read operation. In such situations, the voltage required for the read operation must be increased to ensure that the current through all the programmable diodes are larger than a predetermined current required for the read operation. This may cause some of the diodes to undergo large stresses, due to the high current, during read and program operations. This stress can cause reliability problems as the programmable diode has a tendency to go into an un-programmed state where the diode acts as an open-circuit.
FIGS. 2 and 3 graphically illustrates the relatively large variations in current during read operations when there are small changes in voltage. FIG. 2 is a graph showing the overall current applied during read operations. The overall current is shown on the y-axis while the applied voltage is shown on the x-axis. As can be seen, there is a two orders of magnitude difference in the overall current due to loading effect and diode variation, as shown in region 22.
FIG. 3 is a graph further illustrating a condition where there is a large variation in diode current as a result of small fluctuations in voltage. In FIG. 3, the voltage during the read operation is represented on the x-axis and the current during the read operation is represented on the y-axis. In this case, the minimum required read current is indicated by line 32. According to FIG. 3, the voltage required for the minimum current is VR. The choice of VR is to ensure that all diodes can be correctly read. However, in this case for the same VR value, the current required by some of the diodes during the read operation is illustrated by current values corresponding to lines 34 and 36 so that the current through the diodes during the read operation remains larger than a minimum required value. The current values corresponding to lines 34 and 36 are relatively high compared to the current value at line 32. As described above, the diodes with such high current values are likely to undergo large stress.
Similarly, the ON state characteristics of the programmable diode are strongly dependent on the current required for the program operation. Therefore, the current on the diodes during the program operation must be kept at a constant in order to prevent device-characteristic variation.
In the past a constant voltage has been applied to both the word line and the bit line during the read and program operations. However, this approach was not proven to be effective, as it did not address the issue of large current fluctuations in the diodes during read operations.
In light of the foregoing, there is a need to minimize fluctuations in current value during read and program operations.

Method for controlling current during read and program operations of programmable diode


A design verification system utilizing programmable logic devices having varying numbers of logic processors, macro processors, memory processors and general purpose processors programmed therein is disclosed. These various processors can execute Boolean functions, macro operations, memory operations, and other computer instructions. This avoids either the need to implement logic or the need to compile the design into many gate-level Boolean logic operations for logic processors. Improved efficiency in the form of lower cost, lower power and/or higher speeds are the result when verifying certain types of designs.

Hardware logic emulation systems and acceleration systems are used for functional verification of integrated circuit designs. A logic emulator is typically used with the testing environment provided through an in-circuit connection to other hardware, while an accelerator is typically used with or like a software simulator, with the testing environment provided through software testbenches or test vectors. Often the same core machine is used in either application. Hardware logic emulators and accelerators are known devices that implement a user's design in a plurality of programmable integrated circuits. Such logic emulators and accelerators are available from various vendors, including Cadence Design Systems, Inc., San Jose, Calif., United States of America, and others. Typical systems utilize either programmable logic chips, which are programmably interconnected or a system of special-purpose processor chips.
In programmable logic chip (e.g., field programmable gate array, or FPGA) based systems, the logic contained in the user's design (referred to herein as the "design under verification", or "DUV") is modeled directly in programmable logic form. Examples of hardware logic emulation systems using programmable logic devices can be seen in, e.g., U.S. Pat. Nos. 5,109,353, 5,036,473, 5,475,830 and 5,960,191. U.S. Pat. Nos. 5,109,353, 5,036,473, 5,475,830 and 5,960,191 are incorporated herein by reference. FPGA based emulators and accelerators require FPGA placement and routing, may suffer from timing-induced errors, can present difficult modeling problems for complex memories, and suffer from low performance due to insufficient FPGA package pins.
In processor-based emulation and acceleration systems, the user's design is processed so that its functionality appears to be created in the processors by calculating the outputs of the design. The logic itself is not implemented in a processor-based emulation system, meaning that the DUV does not take actual operating form in the processors. Exemplary processor-based accelerators have been built in large-scale multi-million-gate ASIC-based implementations. These machines are very powerful, but can be too large and expensive for many designs. Further, due to their ASIC implementation of the processor modules, such machines cannot allow macro-level function processors, general-purpose (CPU-based) processors and other specialized functions since the required mix among different types varies widely from design to design. Examples of hardware logic emulation and acceleration systems using processor chips can be seen in, e.g., U.S. Pat. Nos. 4,306,286, 4,656,580, 4,914,612, 5,551,013, 6,035,117, 6,051,030. U.S. Pat. Nos. 4,306,286, 4,656,580, 4,914,612, 5,551,013, 6,035,117, 6,051,030 are incorporated herein by reference.
In processor based acceleration or emulation systems, massively parallel multiprocessors are used for accelerating the simulation of or emulating logic designs. Frequently, these logic designs are expressed at the register-transfer-level and are not limited to gate-level Boolean logic. These designs also include macro operations such as multi-bit addition, multiplication and selection. Accelerated logic simulation is needed since software logic simulation, the most common form of functional verification, is not fast enough to execute software or process large datasets on designs with 500K gates and above. For example, prior event-based gate-level simulation accelerators such as NSim operate at the gate level with full timing simulation, which prevents enough performance to be meaningful.
Thus, there is a need for a design verification system that can flexibly implement various different types of processors depending upon the design being verified.

Logic multiprocessor for FPGA implementation


A gambling card game played in three main stages: initial betting and dealing, bet adjustment, and band checking and payouts. In the first stage, each player places an initial bet and is dealt a three-card hand, and the dealer is dealt a single card. In the second stage, each player increases his initial bet by a multiple (within predetermined limits) chosen by the player in dependence on the hand dealt him. A player can also place a Bonus bet if his hand is all court cards. In the third stage, the dealer pays out on bets on hands for which any card in the hand matches the dealer's card in suit and exceeds it in value, and also on Bonus belts (at the same odds) for winning hands.

There is a wide variety of gambling card games. In some, all participants are on an essentially equal footing; others are of the casino type in which there is a dealer or "house" which operates the game and against which the players play. The present invention is concerned with the latter type of game (although, of course, it may be agreed that different players can become dealer as the session progresses).
Different types of games can involve different degrees of complexity and skill. It is desirable for a game to have the right degree of complexity; if it is too complex then many potential players will be put off, whereas if it is too simple, then potential players will soon lose interest. The same applies to skill; if little or no skill is involved (eg simply cutting for the highest card for fixed stakes) then potential players will soon lose interest, whereas if it appears to demand a high level of skill, then many potential players will be put off.
The object of the present invention is to provide a game which is novel and attractive (ie involves intermediate levels of complexity and skill).


In a processor where separate integer and floating point units are utilized, conditions generated in the integer unit are transferred and made compatible for use in the floating point unit by floating point conditional branch and move operations. Conversely, conditions generated in the floating point unit are transferred and made compatible for use in the integer unit by integer conditional branch and move operations. By providing semantic compatibility of conditions with conditional operations in both integer and floating point units, conditions can be generated in one numeric unit and operated in the other.

1. Field of the Invention
The present invention relates to the field of processors and, more particularly, to a technique for sharing the results of compare instructions between integer and floating point operations.
2. Related Application
The present invention is related to a copending patent application titled "Moderately Coupled Floating Point And Integer Units;" Ser. No. 08/563,499; filed Nov. 28, 1995 now U.S. Pat. No. 5,805,486.
3. Background of the Related Art
The use of integer and floating point units within or in conjunction with a processor is well-known in the art. The integer unit operates on numbers in a format capable of representing only integers (zero, positive or negative numbers without a fractional part). A typical integer unit is comprised of a number of registers for storing information and one or more execution units for operating on the stored information. A collection of registers that are accessed in a like fashion is called a register file. Typically, not all of the execution units in the integer unit will treat the contents of a register as an integer. For example, a shift execution unit operates on bit fields. Apart from the integer execution unit(s), the registers are also coupled to a bus for transfer of information to and from other units, such as memory. Thus, information can be loaded into a register of a register file from a unit such as memory, be operated on by an integer execution unit and the result stored in one of the registers, which result is typically transferred to storage elsewhere, such as in memory.
The floating point unit is configured similarly to the integer unit, but operates on numbers in a format capable of representing numbers with a fractional part. This format is incompatible with the format used to represent integer numbers. Due to the incompatible number formats, integer and floating point units typically have separate register files. The floating point format partitions a number into sign, exponent and significand (also referred to as mantissa) fields. Thus, the difference in number formats also requires a separate set of instructions for operating on integer and floating point numbers.
Processor architectures typically provide a mechanism to allow the conversion from one number format to the other, which involves the movement of data between the integer and floating point register files. For those processor architectures with separate integer and floating point register files, the processors implemented in these architectures typically have functionally separate integer and floating point units coupled to their corresponding register file. Thus, one or more integer execution units are coupled to the integer register file and one or more floating point execution units are coupled to the floating point register file. As part of the process of executing instructions, the processor routes integer instructions to the integer execution unit(s) and routes floating point instructions to the floating point execution unit(s).
The separation of the integer and floating point functions has significant advantages in performance, but has implications on conditional branch and conditional move operations in some instances. These implications generally take the form of transfers of data between the integer and floating point register files. Due to the difference between the integer register file format and the floating point register file format, these transfers may add significant overhead to certain conditional branch and conditional move operations, adversely impacting processor performance. One instance is in supplying a condition to a conditional branch (such as a conditional jump). This condition is typically generated by a compare instruction. It is useful to perform a conditional branch based on either integer or floating point data. In the case where two separate conditional branch instructions are defined in the architecture, one based on integer registers and one based on floating point registers, then the situation where a conditional branch is based on both integer and floating point data will require a data transfer due to the separation of the integer and floating point register files. In the case where the architecture defines only a single conditional branch based on integer registers, and where the floating point compare instruction is defined to write floating point registers, then the situation where a conditional branch is based on floating point data will also require the transfer of data.
Another instance is supplying a condition to a conditional move operation in which the condition is typically generated by a compare instruction. (See, for example, patent applications titled "Method For Conditionally Selecting Data;" Ser. No. 08/623,960; filed Mar. 29, 1996 and "Conditional Move Using A Compare Instruction Generating A Condition Field;" Ser. No. 08/660,094; filed Jun. 6, 1996).
It is useful to be able to perform a conditional move of floating point data based on the result of comparing integer data. It is also useful to be able to perform a conditional move of integer data based on the result of comparing floating point data. For those architectures that define two separate conditional move operations, one based on integer registers and one based on floating point registers, the two conditional move scenarios stated above will require a transfer of data. In the case where the architecture defines only a single conditional move based on integer registers and where the floating point compare instruction is defined to write floating point registers, then data transfer will be required for the case of conditionally moving floating point data based on the result of comparing integer data. Lastly, in an architecture that defines only a single conditional move based on integer registers and where the floating point compare instruction is defined to write integer registers, a conditional move of floating point data based on the result of comparing either integer or floating point data will require a transfer of data.
It is appreciated that architectural definitions other than those mentioned above are possible. For example, an architecture could be defined to have a single register file for storing both integer and floating point data rather than two separate register files. However each of these alternative architectural definitions typically has unique disadvantages in performance as compared to the architecture of the present invention.
Accordingly, the present invention describes a technique for allowing such conditional branching and conditional moving to be practiced on various combinations of integer and floating point data.

Floating point and integer condition compatibility for conditional branches and conditional moves


The invention is directed to alkylquinoline and alkylquinazoline compounds of Formula I:

The present invention relates to quinolines and quinazolines as inhibitors of tyrosine kinases, including FLT3, c-kit and TrkB. Quinazolines have been reported with useful therapeutic properties: U.S. Pat. No. 4,001,422 (DE 2530894) and U.S. Pat. No. 4,542,132 (EP 135318) describe quinazolines as cardiac stimulants, and U.S. Pat. No. 3,517,005 discloses quinazolines with hypotensive and bronchodilation activity. Cardiotonic quinazolines have also been reported, see Chemical & Pharmaceutical Bulletin (1990), 38(11), 3014-19. Quinolines have been reported to possess utility for the inhibition of autophosphorylation of FLT3, see PCT International Application WO2004039782, and for the treatment of amnesia and stroke, as well as a variety of other conditions, see U.S. Pat. Nos. 5,300,515 (EP 497303) and 5,866,562; and PCT International Applications WO2004/002960 and WO2002/088107. Also of note are WO2004058727 (substituted 3,5-dihydro-4H-imidazol-4-ones for the treatment of obesity); WO 2000013681 (4-quinolinemethanol derivatives as purine receptor antagonists); DE 19756388 (U.S. Pat. No. 6,613,772) (substituted 2-aryl-4-amino-quinazolines); JP 59076082 (piperidine derivatives); WO 1999031086 (quinolinepiperazine and quinolinepiperidine derivatives and their use as combined 5-HT1A, 5-HT1B, and 5-HT1D receptor antagonists); U.S. Pat. No. 5,948,786 (piperidinylpyrimidines tumor necrosis factor inhibitors); WO 1997038992 (piperidinylpyrimidine derivatives useful as inhibitors of tumor necrosis factor); Ivan, Marius G. et al. Photochemistry and Photobiology (2003), 78(4), 416-419; Sadykov, T. et al. Khimiya Geterotsiklicheskikh Soedinenii (1985), (4), 563; Erzhanov, K. B. et al. Zhurnal Organicheskoi Khimii (1989), 25(8), 1729-32; Fujiwara, Norio et al. Bioorganic & Medicinal Chemistry Letters (2000), 10(12), 1317-1320; Takai, Haruki et al. Chemical & Pharmaceutical Bulletin (1986), 34(5), 1907-16; WO 2002069972 ((triazolylpiperazinyl)isoquinolines for treatment of neurodegenerative diseases, brain injury and cerebral ischemia); and GB 2295387 (quinazoline derivatives as adrenergic 1C receptor antagonists).
Protein kinases are enzymatic components of the signal transduction pathways which catalyze the transfer of the terminal phosphate from ATP to the hydroxy group of tyrosine, serine and/or threonine residues of proteins. Thus, compounds which inhibit protein kinase functions are valuable tools for assessing the physiological consequences of protein kinase activation. The overexpression or inappropriate expression of normal or mutant protein kinases in mammals has been a topic of extensive study and has been demonstrated to play a significant role in the development of many diseases, including diabetes, angiogenesis, psoriasis, restenosis, ocular diseases, schizophrenia, rheumatoid arthritis, atherosclerosis, cardiovascular disease and cancer. The cardiotonic benefits of kinase inhibition has also been studied. In sum, inhibitors of protein kinases have particular utility in the treatment of human and animal disease.
The Trk family receptor tyrosine kinases, TrkA, TrkB, and TrkC, are the signaling receptors that mediate the biological actions of the peptide hormones of the neurotrophin family. This family of growth factors includes nerve growth factor (NGF), brain-derived neurotrophic factor (BDNF), and two neurotrophins (NT), NT-3, and NT-4. TrkB serves as a receptor for both BDNF and NT-4. BDNF promotes the proliferation, differentiation and survival of normal neural components such as retinal cells and glial cells.
It has recently been reported (see, Nature 2004 Aug. 26; 430(7003):973-4; 1034-40) that TrkB activation is a potent and specific suppressor of anchorage independent cell death (anoikis). Anchorage independent cell survival allows tumor cells to migrate through the systemic circulation and grow at distant organs. This metastatic process is often responsible for the failure of cancer treatment and the cause of mortality in cancer. Other studies (see, Cancer Lett. 2003 Apr. 10; 193(1):109-14) have also suggested that BDNF agonism of TrkB is capable of blocking cisplatin induced cell death. Taken together, these results suggest that TrkB modulation is an attractive target for treatment of benign and malignant proliferative diseases, especially tumor diseases.
The receptor tyrosine kinase c-kit and its ligand Stem Cell Factor (SCF) are essential for hemoatpoiesis, melanogenesis and fertility. SCF acts at multiple levels of the hemoatpoietic hierarchy to promote cell survival, proliferation, differentiation, adhesion and functional activation. It is of particular importance in the mast cell and erythroid lineages, but also acts on multipotential stem and progenitor cells, megakaryocytes, and a subset of lymphoid progenitors (see, Int J Biochem Cell Biol. 1999 October; 31(10):1037-51). Sporadic mutations of c-kit as well as autocrine/paracrine activation mechanisms of the SCF/c-kit pathway have been implicated in a variety of malignancies. Activation of c-kit contributes to metastases by enhancing tumor growth and reducing apoptosis. Additionally, c-kit is frequently mutated and activated in gastrointestinal stromal tumors (GISTs), and ligand-mediated activation of c-kit is present in some lung cancers (see, Leuk Res. 2004 May; 28 Suppl 1:S11-20). The c-kit receptor also is expressed on more than 10% of blasts in 64% of de novo acute myelogenous leukemias (AMLs) and 95% of relapsed AMLs. C-kit mediates proliferation and anti-apoptotic effects in AML (see, Curr Hematol Rep. 2005 January; 4(1):51-8).
C-Kit expression has been documented in a wide variety of human malignancies, including mastocytosis, mast cell leukemia, gastrointestinal stromal tumour, sinonasal natural killer/T-cell lymphoma, seminoma, dysgerminoma, thyroid carcinoma; small-cell lung carcinoma, malignant melanoma, adenoid cystic carcinoma, ovarian carcinoma, acute myelogenous leukemia, anaplastic large cell lymphoma, angiosarcoma, endometrial carcinoma, pediatric T-cell ALL, lymphoma, breast carcinoma and prostate carcinoma. See, Heinrich, Michael C. et al. Review Article: Inhibition of KIT Tyrosine Kinase Activity: A Novel Molecular Approach to the Treatment of KIT-Positive Malignancies.
The fms-like tyrosine kinase 3 (FLT3) ligand (FLT3L) is one of the cytokines that affects the development of multiple hematopoietic lineages. These effects occur through the binding of FLT3L to the FLT3 receptor, also referred to as fetal liver kinase-2 (flk-2) and STK-1, a receptor tyrosine kinase (RTK) expressed on hematopoietic stem and progenitor cells. The FLT3 gene encodes a membrane-bound RTK that plays an important role in proliferation, differentiation and apoptosis of cells during normal hematopoiesis. The FLT3 gene is mainly expressed by early meyloid and lymphoid progenitor cells. See McKenna, Hilary J. et al. Mice lacking flt3 ligand have deficient hematopoiesis affecting hematopoietic progenitor cells, dendritic cells, and natural killer cells. Blood. June 2000; 95: 3489-3497; Drexler, H. G. and H. Quentmeier (2004). "FLT3: receptor and ligand." Growth Factors 22(2): 71-3.
The ligand for FLT3 is expressed by the marrow stromal cells and other cells and synergizes with other growth factors to stimulate proliferation of stem cells, progenitor cells, dendritic cells, and natural killer cells.
Hematopoietic disorders are pre-malignant disorders of these systems and include, for instance, the myeloproliferative disorders, such as thrombocythemia, essential thrombocytosis (ET), angiogenic myeloid metaplasia, myelofibrosis (MF), myelofibrosis with myeloid metaplasia (MMM), chronic idiopathic myelofibrosis (IMF), and polycythemia vera (PV), the cytopenias, and pre-malignant myelodysplastic syndromes. See Stirewalt, D. L. and J. P. Radich (2003). "The role of FLT3 in haematopoietic malignancies." Nat Rev Cancer 3(9): 650-65; Scheijen, B. and J. D. Griffin (2002). "Tyrosine kinase oncogenes in normal hematopoiesis and hematological disease." Oncogene 21(21): 3314-33.
Hematological malignancies are cancers of the body's blood forming and immune systems, the bone marrow and lymphatic tissues. Whereas in normal bone marrow, FLT3 expression is restricted to early progenitor cells, in hematological malignancies, FLT3 is expressed at high levels or FLT3 mutations cause an uncontrolled induction of the FLT3 receptor and downstream molecular pathway, possibly Ras activation. Hematological malignancies include leukemias, lymphomas (non-Hodgkin's lymphoma), Hodgkin's disease (also called Hodgkin's lymphoma), and myeloma—for instance, acute lymphocytic leukemia (ALL), acute myeloid leukemia (AML), acute promyelocytic leukemia (APL), chronic lymphocytic leukemia (CLL), chronic myeloid leukemia (CML), chronic neutrophilic leukemia (CNL), acute undifferentiated leukemia (AUL), anaplastic large-cell lymphoma (ALCL), prolymphocytic leukemia (PML), juvenile myelomonocyctic leukemia (JMML), adult T-cell ALL, AML with trilineage myelodysplasia (AML/TMDS), mixed lineage leukemia (MLL), myelodysplastic syndromes (MDSs), myeloproliferative disorders (MPD), multiple myeloma, (MM) and myeloid sarcoma. See Kottaridis, P. D., R. E. Gale, et al. (2003). "Flt3 mutations and leukaemia." Br J Haematol 122(4): 523-38. Myeloid sarcoma is also associated with FLT3 mutations. See Ansari-Lari, Ali et al. FLT3 mutations in myeloid sarcoma. British Journal of Haematology. 2004 Sep. 126(6):785-91.
Mutations of FLT3 have been detected in about 30% of patients with acute myelogenous leukemia and a small number of patients with acute lymphomatic leukemia or myelodysplastic syndrome. Patients with FLT3 mutations tend to have a poor prognosis, with decreased remission times and disease free survival. There are two known types of activating mutations of FLT3. One is a duplication of 4-40 amino acids in the juxtamembrane region (ITD mutation) of the receptor (25-30% of patients) and the other is a point mutation in the kinase domain (5-7% of patients).
The mutations most often involve small tandem duplications of amino acids within the juxtamembrane domain of the receptor and result in tyrosine kinase activity. Expression of a mutant FLT3 receptor in murine marrow cells results in a lethal myeloproliferative syndrome, and preliminary studies (Blood. 2002; 100: 1532-42) suggest that mutant FLT3 cooperates with other leukemia oncogenes to confer a more aggressive phenotype.
Taken together, these results suggest that specific inhibitors of the individual kinases FLT3 and c-kit, and especially of the group of kinases comprising FLT3 and c-kit, present an attractive target for the treatment of hematopoietic disorders and hematological malignancies.
FLT3 kinase inhibitors known in the art include AG1295 and AG1296; Lestaurtinib (also known as CEP 701, formerly KT-5555, Kyowa Hakko, licensed to Cephalon); CEP-5214 and CEP-7055 (Cephalon); CHIR-258 (Chiron Corp.); EB-10 and IMC-EB10 (ImClone Systems Inc.); GTP 14564 (Merk Biosciences UK). Midostaurin (also known as PKC 412 Novartis AG); MLN 608 (Millennium USA); MLN-518 (formerly CT53518, COR Therapeutics Inc., licensed to Millennium Pharmaceuticals Inc.); MLN-608 (Millennium Pharmaceuticals Inc.); SU-11248 (Pfizer USA); SU-11657 (Pfizer USA); SU-5416 and SU 5614; THRX-165724 (Theravance Inc.); AMI-10706 (Theravance Inc.); VX-528 and VX-680 (Vertex Pharmaceuticals USA, licensed to Novartis (Switzerland), Merck & Co USA); and XL 999 (Exelixis USA). The following PCT International Applications and US patent applications disclose additional kinase modulators, including modulators of FLT3: WO 2002032861, WO 2002092599, WO 2003035009, WO 2003024931, WO 2003037347, WO 2003057690, WO 2003099771, WO 2004005281, WO 2004016597, WO 2004018419, WO 2004039782, WO 2004043389, WO 2004046120, WO 2004058749, WO 2004058749, WO 2003024969 and US Patent Application No. 20040049032.
See also Levis, M., K. F. Tse, et al. 2001 "A FLT3 tyrosine kinase inhibitor is selectively cytotoxic to acute myeloid leukemia blasts harboring FLT3 internal tandem duplication mutations." Blood 98(3): 885-7; Tse K F, et al. Inhibition of FLT3-mediated transformation by use of a tyrosine kinase inhibitor. Leukemia. 2001 July; 15(7): 1001-10; Smith, B. Douglas et al. Single-agent CEP-701, a novel FLT3 inhibitor, shows biologic and clinical activity in patients with relapsed or refractory acute myeloid leukemia Blood, May 2004; 103: 3669-3676; Griswold, Ian J. et al. Effects of MLN518, A Dual FLT3 and KIT Inhibitor, on Normal and Malignant Hematopoiesis. Blood, July 2004; [Epub ahead of print]; Yee, Kevin W. H. et al. SU5416 and SU5614 inhibit kinase activity of wild-type and mutant FLT3 receptor tyrosine kinase. Blood, September 2002; 100: 2941-294; O'Farrell, Anne-Marie et al. SU11248 is a novel FLT3 tyrosine kinase inhibitor with potent activity in vitro and in vivo. Blood, May 2003; 101: 3597-3605; Stone, R. M. et al. PKC 412 FLT3 inhibitor therapy in AML: results of a phase II trial. Ann Hematol. 2004; 83 Suppl 1:S89-90; and Murata, K. et al. Selective cytotoxic mechanism of GTP-14564, a novel tyrosine kinase inhibitor in leukemia cells expressing a constitutively active Fms-like tyrosine kinase 3 (FLT3). J Biol Chem. 2003 Aug. 29; 278(35):32892-8; Levis, Mark et al. Novel FLT3 tyrosine kinase inhibitors. Expert Opin. Investing. Drugs (2003) 12(12) 1951-1962; Levis, Mark et al. Small Molecule FLT3 Tyrosine Kinase Inhibitors. Current Pharmaceutical Design, 2004, 10, 1183-1193.

Alkylquinoline and alkylquinazoline kinase modulators

Abstract: wherein R1, R2, R3, B, Z, G, Q and X are as defined herein, the use of such compounds as protein tyrosine kinase modulators, particularly inhibitors of FLT3 and/or c-kit and/or TrkB, the use of such compounds to reduce or inhibit kinase activity of FLT3 and/or c-kit and/or TrkB in a cell or a subject, and the use of such compounds for preventing or treating in a subject a cell proliferative disorder and/or disorders related to FLT3 and/or c-kit and/or TrkB. The present invention is further directed to pharmaceutical compositions comprising the compounds of the present invention and to methods for treating conditions such as cancers and other cell proliferative disorders.


The invention relates to a device for determining a measurement of mass flow of fluid for a combustion chamber comprising a fluid metering device and a means of measuring the position of the metering device being measured. This device comprises:                a mass flow meter,        a hybridisation device for determining an actual mass flow of fluid comprising:                    a first input comprising a set-point value (WF set-point, Xset-point),            a prediction unit (26) capable of determining, from the first input and variables of state comprising the actual mass flow (WF actual) and parametric unknowns (IP), estimated values (^WF flow meter, ^Xmetering device),            a second input comprising the measured position of the metering device (Xmetering device) and the measured mass flow of fluid (WF flow meter),            a calculator of residues (30, 22, 20) for determining a first residue (Rmetering device) between the measured position of the metering device and the estimated position of the metering device and a second residue (Rflow meter) between the measured mass flow of fluid and the estimated mass flow of fluid,            a correction unit (24) for determining, from the first and second residues corrections capable of being applied to variables of state (WF actual, IP).

In the case of aeroplane turbojets, it is crucial to determine precisely the mass flow of fuel being injected into the combustion chamber of the turbojet. This is because by estimating the mass flow the mass flow of reduced fuel can be calculated, as well as the richness of the air/kerosene mix. The more precise this estimate of mass flow, the more precise the calculation of mass flow of reduced fuel as well as the richness of the air-kerosene mix. Since the acceleration and deceleration limits are generally expressed as a function of the mass flow of reduced fuel, the lack of accuracy in calculating this flow reduces the performance of the engine. Moreover, the control of polluting emissions requires knowledge of the richness of the air/kerosene mix of the chamber, and the lack of precision in calculating this richness reduces the quality of this control. In general, control of the engine is made possible by estimating the mass flow of fuel injected.
It is currently known to estimate the mass flow of fuel injected into the combustion chamber in two different ways. The mass flow of fuel injected may be measured from the measurement of the position of the fuel metering device and from an associated equation. However, since the measurement is a random signal, the mass flow calculated is subject to interference. Moreover, the equation linking the position of the metering device to the mass flow passing through the same contains some unknowns in its parameters. These unknowns are due in particular to the variability of the density and viscosity of the fuel, to manufacturing tolerances in the geometric features of the metering device, to the precision of hydromechanical control of the pressure differential through the metering device and to the precision of electromechanical control of the position of the slide valve of the metering device.
The mass flow of fuel injected may also be measured from the measurement of mass flow by a conventional flow meter. However, the dynamics of a mass flow meter are too poor for use in the control of an engine.

Device for estimating the mass flow of fuel


A hydraulic control system for an automatic transmission includes a hydraulic pressure source, a line pressure controller for constantly controlling hydraulic pressure from the hydraulic pressure source, a reducing pressure controller for generating reduced pressure, a damper clutch controller for supplying hydraulic pressure fed from the line pressure controller to a torque converter, a shift controller for converting hydraulic pressure from the line pressure controller into drive pressure corresponding to each speed stage, a hydraulic controller for controlling drive pressure from the shift controller; and a pressure distributer for distributing hydraulic pressure from the hydraulic controller to each friction member for each speed stage by being controlled by drive pressure from the shift controller. The line pressure controller includes a regulator valve controlling hydraulic pressure from the hydraulic pressure source to line pressure and a high-low control valve controlled by reduced pressure from the reducing controller, control pressure from the damper clutch controller, and third speed drive pressure from the shift controller, and supplying second drive pressure from the shift controller to the regulator valve, thereby controlling an operation of the regulator valve together with forward/reverse drive pressure fed from the shift controller to the regulator valve.

The present invention relates to a hydraulic control system for an automotive automatic transmission and a line pressure control method.
Generally, a conventional automatic transmission includes a torque convertor, a multi-stage gear shift mechanism connected to the torque convertor, and a hydraulic control system which selects a gear stage of the gear shift mechanism according to a driving state of the vehicle.
The above hydraulic control system includes a regulator valve for regulating line pressure to be in high or low state. The regulator valve is designed so that it regulates line pressure to be in a low state only when a damper clutch is operated in third and fourth speeds. As a result, the ability to achieve low line pressure is limited such that shift efficiency deteriorates.

Hydraulic control system of an automatic transmission with high-low control valve controlled by three pressures


A semiconductor device has a semiconductor substrate and a conductor layer provided over the semiconductor substrate. The conductor layer includes a first linear part extending in a first direction and provided with slits extending in the first direction, a second linear part extending in a second direction at an angle with the first direction and provided with slits extending in the second direction, and a junction part formed where the first and second linear parts are connected and provided with slits shorter than the slits in the first and second linear parts.

1. Field of the Invention
The present invention relates to a semiconductor device having a semiconductor substrate and a conductor layer formed thereon, and a method for making such a semiconductor device.
2. Background Information
A prior-art semiconductor device, shown in Japanese Patent Kokai Publication No. 174948/1987, uses a conductor layer of which a wide part in the periphery of the chip is provided with slits in order to prevent or reduce sliding or disconnection due to an internal stress of plastic packaging or a thermal stress during thermal cycle tests.
The slits are normally provided to extend in the direction in which the conductor extends. At a junction 20 where two conductor parts are connected or branched as shown in FIG. 11, the directions of the slits 21 in the respective conductor parts are made parallel with the edges of the conductor parts in which the slits are provided. A problem associated with the pattern off slits shown in FIG. 11 is that electric currents concentrate in the hatched area 22, and electromigration tends to occur. This degrades the reliability of the conductor layer.
Moreover, in the past, the insertion or disposition of the slits was made manually, in accordance with slit introduction standards determined for each LSI vendor, so the designing of the slit insertion was time-consuming. Furthermore, there is an increasing demand for the layout to be performed by LSI developers rather than LSI vendors. But as the LSI developers have little experience with layout designing, it is very difficult for them to carry out the slit insertion designing using a layout editor.
It is therefore desirable to be able to provide automatic insertion of slits in the conductor patterns.
Another prior-art publication, Japanese Patent Kokoku Publication No. 46981/1988 shows a method of disposition of slits at a corner of a conductor pattern. But it does not teach methods or rules of deposition which can be applied to various types of junction parts.

Semiconductor device having a conductor layer provided over a semiconductor substrate


A chemiluminescent label compound and conjugate containing the same, in which the compound involves a fused ring system comprising a. (i) hetercyclic ring as a fused member thereof in which the heterocyclic ring contains PA0 (ii) a leaving group coupled to the heterocyclic ring through a carbon adjacent to a fused ring carbon such that the leaving group and heterocyclic ring join to form a difunctional carboxy-containing linkage in which the carboxy carbon is directly bonded to the carbon of the heterocyclic ring adjacent to a fused ring carbon,. (a) one or more nitrogen heteroatoms in the ring; PA1 (b) at least one saturated or unsaturated ring in fused state with the heterocyclic ring; PA1 (c) an available carbon atom in the heterocyclic ring that is adjacent to a carbon forming a fused ring with the heterocyclic ring; and PA1 (d) at least one substituent that is peri relative said available carbon of the heterocyclic ring, which substituent serves to enhance the hydrolytic stability of the chemiluminescent label compound; and PA1 (a) the linkage being an ester, thiolester or amide of a carboxylic acid, and PA1 (b) said linkage substituted heterocyclic ring is susceptible to chemical attack to dissociate the heterocyclic ring to a transient compound by first cleaving the linkage to dissociate the leaving group from the heterocyclic ring system followed by dissociation of the residual carbonyl from the linkage.. Also described are assays and assay kits that employ such label compounds.

The literature describes classes of compounds that give off light or "luminesce" by reaction through chemical treatment. The compounds that have this capability are termed chemiluminescent materials. Their dissociation is typically caused by treatment with peroxide or molecular oxygen at high pH. Light is produced by the decay of the transient ("intermediate") structure formed by peroxide or molecular oxygen reaction at an sp.sup.2 or sp.sup.3 hybridized carbon in the compound that is part of a chain or a ring or ring system.
As the literature indicates, any series of reactions which produce the intermediate: ##STR1## will lead to moderate to strong chemiluminescence. F is a structure such that the product carbonyl derivative ##STR2## is fluorescent and X is a good leaving group, usually with XH, for efficient chemiluminescence, having a pK.sub.a of about .ltoreq.11, preferably <11, and most preferably, from about 5 to about 8. The reaction may require base catalysis.
The intermediate can be prepared (in isolable or transient form, depending on F) from species such as: ##STR3## See Endeavour, 23, No. 117 (1973) p. 140, The Chemistry of Bioluminescence in "Bioluminescence in Action" (P. J. Herring, ed.), Academic Press, London, 1978 (pp. 64-5), Proc. R. Soc. Lond., B 215, p. 256 (1982), Progress in Organic Chemistry, (W. Carruthers and J. K. Sutherland, eds.), Butterworth, London (1973), p. 261, all authored by F. McCapra.
For example, chemiluminescent aryl esters that contain such hybridized carbon, termed a labeling compound, react according to the following general reaction: ##STR4## where A is an aryl ring or ring system and B is a heterocyclic ring or ring system. In this reaction, --O--A, the leaving group, is cleaved by perhydrolysis resulting in steps leading to the transient intermediate, B.dbd.O, that proceeds to decay generating luminescence.
The characteristics of some of these chemiluminescent compounds, their chemistry of manufacture, and other factors relating to them, are more fully described by McCapra, "Chemiluminescence of Organic Compounds," in Progress in Organic Chemistry, vol. 8, Carruthers and Sutherland ed., Wiley & Sons (1973); Kohen, Bayer, Wilechek, Barnard, Kim, Colleins, Beheshti, Richardson and McCapra, "Development Of Luminescence-Based Immunoassays For Haptens And For Peptide Hormones," pp. 149-158, in Analytical Applications Of Bioluminescence and Chemiluminescence, Academic Press, Inc. (1984); Richardson, Kim, Barnard, Collins and McCapra, Clinical Chemistry, vol. 31, no. 10, pp. 1664-1668 (1985); McCapra, "The Application of Chemiluminescence in Diagnostics," 40th Conference of the American Association of Clinical Chemists, New Orleans, La., Jul. 28, 1988; McCapra, "The Chemiluminescence Of Organic Compounds," Quarterly Reviews, vol. 20, pp. 485-510 (1966); McCapra, "The Chemiluminescence Of Organic Compounds," Pure and Applied Chemistry, vol. 24, pp. 611-629 (1970); McCapra, "The chemistry of bioluninescence," Proceedings Of Royal Society, vol. B215, pp. 247-278 (1982); McCapra and Behesti, "Selected Chemical Reactions That Produce Light," Bioluminescence and Chemiluminescence; Instruments and Applications, CRC Press, vol. 1, Chapter 2, pp. 9-37 (1985); McCapra, "Chemiluminescent Reactions of Acridines," Chapt. IX, Acridines, R. M. Acheson, Ed., pp. 615-630, John Wiley & Sons, Inc. (1973); McCapra, "Chemical Mechanisms in Bioluminescence," Accounts Of Chemical Research, vol. 9, no. 6, pp. 201-208 (June 1976); and in many other publications and presentations on the subject.
As noted in the above literature, chemiluminescent compounds of a variety of structures have been projected as labels in a variety of assays including immunoassays (in this respect, see U.S. Pat. Nos. 4,383,031, 4,380,580 and 4,226,993). The esters, thiolesters and amides, alone or conjugated (i.e., chemically coupled to another material), are especially desirable forms of chemiluminescent labels. However, they lose their luminescence capability over time in an aqueous system because they hydrolyze to products that are not available to the assay. Until recently, these compounds have not been used in commercial assays. Until the invention of copending application Ser. No. 07/859,995, now U.S. Pat. No. 5,284,952 the ester, thiolester and amide forms of this class of materials lacked sufficient hydrolytic stability to be stored in the most convenient form, which is as a component of an aqueous system.
Carboxylic acid esters, thiolesters and amides are susceptable to hydrolytic attack resulting in the formation of the carboxylic acid and the hydroxy, mercapto or amino component that is the theoretical or actual precursor to the ester, thiolester or amide. It is recognized that some amount of hydrolytic attack can be inhibited by the inclusion of bulky groups that chemically sterically hinder those linkages, see Nishioka, et al., J. Org. Chem., vol. 40, no. 17, pp. 2520-2525 (1975), Fujita et al., "The Analysis of the Ortho Effect," Progress in Physical Organic Chemistry, 8, pp. 49-89 (1976), Morrison and Boyd, Organic Chemistry, 5th Ed., pp. 842-843 (1987) and March, Advanced Organic Chemistry, 3rd Ed., page 240 (1985). According to March:
"Another example of steric hindrance is found in 2,6-disubstituted benzoic acids, which are difficult to esterify no matter what the resonance or field effects of the groups in the 2 or the 6 position. Similarly, once the 2,6-disubstituted benzoic acids are esterified, the esters are difficult to hydrolyze." (Emphasis in the original) PA1 (1) the carbonyl carbon of (a) is covalently bonded to a carbon atom (x) of (c) and the remaining free valence of (a) is carbon bonded to (b), and PA1 (4) (c) contains PA1 (1) the carbonyl carbon of (a) is covalently bonded to a carbon atom (x) of (c) and the remaining free valence of (a) is carbon bonded to (b), and PA1 (4) (c) contains
The difficulty in esterification is not the same in making esters from 2,6-substituted phenols, but the general principles described by March are applicable to enhancing the hydrolytic stability of the resultant ester so long as the ortho substitutions are electron donating.
The position of the bulky sterically hindering group relative to the linkage is important for retarding hydrolysis. Groups that may be dormant to any other reaction may not provide steric hindrance because of its chemical nature. For example, a group in a position alpha to a carbonyl moiety of an ester group that is electron withdrawing (such as an alpha chloro group) could adversely affect the hydrolytic stability of the ester group. Thus, the relative position of the bulky group and its chemical nature is important if steric hindrance depends on the presence of such group in the molecule.
The function of chemiluminescent labels in assay applications involves the coupling of the label compound to a substrate molecule. Such coupling can be achieved by solvent interraction (e.g., molecular compatibility), any heterolytic or homolytic mechanism induced by chemical means and influenced by physical effects, such as time, temperature and/or mass action. For example, the reaction can be nucleophilic or electrophilic, or it can involve free radical mechanisms. In the broadest perspective, the coupling can be viewed as achievable via strong to weak bonding forces.
A chemiluminescent label in assays is an associated moiety of a binding material. The moiety is derived from a chemical compound which, as such, possesses chemiluminescent capabilities. Hereinafter, the term moiety as applied to the label as such, is a reference to the compound prior to being associated with a binding material. The term associated is intended to include all or any of the mechanisms for coupling the label to the substrate molecule.
The term "functional" in chemistry typically refers to a group that influences the performance of a chemical or constitutes the site for homolytic or heterolytic reactions. For example, a functional alkyl substituent, used in the context of interreactions through that substituent, means an alkyl group substituted so that it can effect that reaction. But an alkyl group termed functional for the electronic effects it induces in the molecule is a reference to the alkyl group per se.

Peri substituted fused ring chemiluminescent labels and their conjugates, and assays therefrom


This invention provides a management device and method for managing a update of software programs having functionally close relations each other installed in a print system, such as a printer driver and a control program. In the print system comprising a host computer and a printer for receiving and printing a print job from the host computer, provided is adaptability information indicative of adaptability between control programs and printer drivers in several versions. With reference to the adaptability information, it is determined that adaptability between the printer driver and the control program which have already been installed, and newer versions of printer driver and the control program. When those software programs have the adaptability therebetween, the printer driver and the control program which have already been installed are updated to have the newer versions.

1. Field of the Invention
The present invention relates to a management device and method for a print system comprising a data processor and a printer for printing a print job sent from the data processor, and more particularly to management of update process of software programs installed in the print system.
2. Description of the Related Art
In recent years, office automation has been promoted in enterprise offices and a print system through a network has been spread with the development of an information processing apparatus. More specifically, there has been a system in which a plurality of host computers are connected to a printer through a network such as a LAN and a print job sent from the host computer is printed and output from the printer.
In such a print system, a software program adapted to a printer and generating a print job, that is, a printer driver is installed in a host computer, and a control program which is a software program for controlling the operation is installed in the printer. The printer driver and the control program have functionally close relations with each other, and therefore it is necessary to install the printer driver functionally adapted to the control program of the printer into the host computer.
The printer driver and the control program which are to be installed in these apparatuses are revised at any time to eliminate drawbacks such as a program bug or extend functions. In general, such revision of a software program is referred to as "version up" and identification indicative of the degree of the revision is referred to as "version".
With the version up of the software program, a user reinstalls a software program having the latest version into the host computer and the printer. Consequently, the user can eliminate the drawbacks and can utilize new functions.
However, the user needs to always observe the version up for each software program, and furthermore, needs to confirm the adaptability of the software program to carry out an install work. These works are a burden to the user.
In order to solve such a problem, Japanese Laid-Open Patent Publication No. 10-340163 has disclosed the art in which the control program of a printer, the software program of personal computer terminals and the like are automatically updated individually. More specifically, there has been disclosed a method for downloading a software program through a network to carry out version up.
In two or more software programs having functionally close relations, however, even if one of the software programs is updated, effects cannot be obtained or a normal operation cannot be carried out if the other software program is not updated. In the conventional invention, such software programs having functionally close relations have not been taken into consideration and cannot cope with the above-mentioned problem.

Management device and method of print system for updating software programs installed in the print system


An injection molded plastic rod suitable for use in a battery hydrometer. Stress-relieving formations are provided symmetrically arranged on opposite sides of an injection gate of the rod. The formations distribute injection stresses and shield the gate vestige.

Simple plastic rods are used in many devices and apparatuses. One use for molded plastic rods is in battery hydrometers. An elongated transparent plastic rod extends downwardly from the top of the battery into one or more cells of the battery. The rod has attached thereto a cage that encloses or suspends one or more spherical balls within the battery fluid. The hydrometer can monitor both the battery fluid level and the specific gravity of the battery fluid. Incident light rays are transmitted through the transparent rod, and various patterns or colors are transmitted to the viewing surface of the rod on the outer top level of the battery. The patterns or colors indicate whether or not the rod is immersed in battery fluid, indicating the battery fluid level, and whether or not the ball of a predetermined specific gravity is buoyant within the battery fluid, indicating the specific gravity of the fluid. An example of such a cage for suspending balls within the battery fluid can be found in U.S. Pat. No. 6,393,910 "One Piece Battery Charge Indicator Cage," which is commonly assigned herewith.
It is known that the plastic rod by which the cage is suspended in the battery can be manufactured by injection molding processes. It has been observed that such injection-molded rods are susceptible to inborn stresses that are concentrated at the injection point. The concentration of inborn stresses at the injection point weakens the overall strength of the rod, resulting in much reduced overall break strength. The concentration of stresses in a relatively small area can cause cracks to form easily, which can then propagate quickly. As a result, prior rods have been known to break during shipment or installation, and a cracked or weakened rod may even fail during use.
Another problem with known rods of this type is that a sharp point or edge may be developed at the injection point (gate), with residual material (gate vestige) extending above the surface of the rod. A sharp or pointed gate vestige has the potential of damaging any product or item that comes in contact with it. Removing the sharp point or edge involves a subsequent process to the molding process, which can be time consuming and may significantly increase the cost for the rod.
What is needed in the art is an improved injection process and rod design whereby the overall strength of an injection molded rod is increased, particularly at the injection point, and in which the sharp edge or point that may remain after injection molding is shielded from contact with other items or things.

Molded plastic rod with improved break strength


Device and method for wavefront measurement of an optical imaging system by means of phase-shifting interferometry, having a mask structure (6a) to be arranged on the object side, and/or a grating structure (7a) to be arranged on the image side. The object-side mask structure includes one or more one-dimensional mask structure patterns, and the image-side grating structure includes one or more two-dimensional grating structure patterns. Alternatively, conversely, the mask structure includes one or more two-dimensional patterns, and the grating structure includes one or more one-dimensional patterns. Additionally or alternatively, a pupil position offset caused by a lateral relative movement of the mask structure and detector element can be taken into account by back calculating the interferogram, respectively recorded by the detector element, using an associated phase-shift characteristic, or by a computational correction of wavefront derivatives, obtained from the recorded interferograms, in the direction of lateral movement. The method and/or the device can by used, for example, for determining aberration in the case of high-resolution projection objectives of microlithography exposure machines using shearing or point interferometry.

Devices and methods of this type serve the purpose, for example, of determining the imaging quality and/or image errors of high-resolution optical imaging systems interferometrically with high precision. An important field of application is the corresponding measurement of projection objectives in microlithography exposure machines for semiconductor component patterning. Interferometry techniques used for this purpose are shearing interferometry, by means of which the wavefront measurement device disclosed in Laid-open Patent Application DE 101 09 929 A1, for example, operates, and point diffraction interferometry. In this case, the device can be integrated in the system in which the imaging system is used in its normal operation, and it can use for measurement the same radiation of a radiation source present in the system as it is used in normal operation of the imaging system. In this case, the interferometer is denoted as an operational interferometer or OI device.
It is known in the case of these phase-shifting interferometry techniques for wavefront measurement that the phase-shifting structure, for example a diffraction grating, to be arranged on the image side, with a one-dimensional or two-dimensional diffraction grating structure, or a so-called coherence mask, to be arranged on the object side, with a one-dimensional or two-dimensional coherence mask structure, is moved laterally relative to the optical imaging system to be measured, in order to determine the spatial derivative of the measured wavefront in the relevant lateral direction, from which it is then possible to obtain image error information relating to the imaging system, in particular spatially resolved image error information relating to the entire pupil of the imaging system, typically in the form of so-called Zernike coefficients. Here, the designation "one- or two-dimensional" means structures which are periodic in one or in two non-parallel directions, and consequently lead in the diffraction diagram to the diffraction patterns in one or in two non-parallel directions.
For this purpose, for example, spatial derivatives in two mutually orthogonal directions such as the x- and y-directions of an xyz coordinate system with a z-axis pointing in the direction of the optical axis of the system are determined by using a two-dimensional coherence mask to be arranged on the object side, and a two-dimensional diffraction grating structure corresponding thereto. In addition to the stepwise, relatively slow lateral displacement, for example of the diffraction grating structure for the purpose of effecting the phase shift in the direction in which the spatial derivative of the interferogram or of the wavefront is to be measured, for example in the x-direction, it is preferred to provide an in contrast much faster lateral movement of the phase-shifting structure in the direction perpendicular thereto, such as the y-direction, in order to suppress effects by interference between undesired diffraction orders in this orthogonal direction. The interferogram image recorded by the detector element on the detection plane during this fast movement is integrated such that the undesired interference is averaged out as far as possible.
Frequently the downstream detection part and, in particular, the image recording detector element are also laterally displaced synchronously with the phase-shifting structure, for example in a fashion implemented by a design with a motionally rigid coupling of the phase-shifting structure and detector element. This fixed coupling permits a relatively compact design of the wavefront-measuring interferometer part. Particularly for this type of system with motionally rigid coupling of the phase-shifting structure and detector element, however, when use is made of the method, conventional for this purpose of evaluating the wavefront interoferograms, it is observed that there is a limitation of the accuracy which can be achieved for the wavefront measurement, and this is to be ascribed to the fact that the image of the pupil of the imaging system to be measured migrates during the measurement operation in the detection plane of the detector element in conjunction with the synchronous lateral movement of the phase-shifting structure and detector element. This is the case, specifically, with systems which do not use a sine corrected imaging optical system between the phase-shifting structure and the detector element, and holds both for the abovementioned slow lateral movement in the direction to be measured, and for the fast movement in the direction, orthogonal thereto, for suppressing the undesired interference. The pupil migration also occurs when the object-side mask structure is laterally displaced, while the detector element remains undisplaced, and leads with the conventional evaluation methods to a spatial "blurring" of the measured wavefronts, and thus to a so-called "crosstalk" between different Zernike coefficients, in particular Zernike coefficients with large radial powers are underweighted.
The technical problem on which the invention is based is to provide a device and a method of the type mentioned at the beginning which specifically permits comparatively accurate wavefront measurement of an optical imaging system even when the pupil image of the measured imaging system migrates on the detection plane of the detector element owing to a coupled lateral movement of the phase-shifting structure and detector element, or a lateral movement of an object-side mask relative to the detector element.


IC card of the present invention consists of a frame including a rectangular bottom plate and a U-shaped side wall along the three edges of the bottom plate; a connector fixed to the open side of the frame with the U-shaped side wall; a board module at least one including printed-circuit boards with electronic components mounted thereon, combined with the connector, and inserted in the frame; and a metal panel for sealing off the board module inside the frame with the connector fixed thereto.

1. Field of the Invention
The present invention generally relates to an IC card, more particularly to a thinner IC card which accommodates more electronic components more compactly.
2. Description of the Prior Art
IC cards based on PCMCIA specification have been now widely used.
FIG. 14 is a perspective view showing an external appearance of a conventional IC card. FIG. 15 is an exploded view of the IC card shown in FIG. 14. FIG. 16 is a cross section of the IC card shown in FIG. 14 cut along the plane XVI--XVI.
In FIGS. 14-16, an IC card 50 includes a U-shaped frame 51 made of plastic for example, metal panels 52a and 52b, a connector 53, made of plastic for example, which has a plurality of terminals 54 insert-molded therein so as to protrude inside of IC card 50, and a printed-circuit board 55 with electronic components 56 mounted on both surfaces thereof.
Inner tip ends of terminals 54 of connector 53 are formed so as to insert one side of board 55 along which a plurality of connecting tips are printed and, when inserted, electrically connect lines of board 55 with those of the external system, respectively. The combined connector 53 and printed-circuit board 55 are coupled with frame 51 so that the connector and the frame contain the printed-circuit board. Combined frame 51 and connector 53 containing printed-circuit board 55 connected to terminals 54 of the connector are sandwiched between metal panels 52a and 52b through adhesive sheets 57a and 57b, respectively.
Upon assembling an IC card as shown in FIGS. 14-16, printed-circuit board 55, with electronic components mounted on it, is connected to connector 53 by means of connector terminals 54, and then connector 53 is fit to frame 51. Then adhesive sheets 57a and 57b are pasted to metal panels 52a and 52b, respectively. Metal panels 52a and 52b are fixed, with heat and pressure, by means of adhesive sheets 57a and 57b, respectively, to frame 51 combined with connector 53 and printed-circuit board 55 from the top and the bottom. In the process of assembling IC cards adhesive sheets 57a and 57b must be pasted to metal panels 52a and 52b in considerable precision. Further, the amount of heat and pressure required to fix the metal panels to the frame must also be controlled precisely. Thus, manufacturing conventional IC cards requires the greatest attention in the assembly process, which results in higher manufacturing cost.
As increasingly more electronic components are mounted on a conventional IC card of a fixed size of 85.6 mm.times.54.0 mm.times.3.3 mm, for example, a multilayer printed-circuit board has been used to accommodate them. The structure of a multilayer printed-circuit board with electronic components mounted thereon and the mounting method are disclosed in Japanese Patent Laid-Open Publication HEI 3-280496. The structure disclosed in that publication includes stacked printed-circuit boards with common through holes in them and a plurality of electronic components which are inserted in each through hole and mounted on top of one another. Only "bonding" is allowed in this configuration, and an electronic component with a molded package cannot be mounted. Ordinary soldering such as reflow soldering cannot be used either. This structure does not allow printed-circuit boards to have electronic components initially mounted on them and then to be stacked on top of one another.


An emergency indicator system which comprises a telephone located within a building and a visual display unit. A facility electrically connected to the telephone is for activating the visual display unit, when a person dials 911 on the telephone during an emergency, so that the building can be quickly located, such as by an emergency rescue vehicle, the police, etc.

1. Field of the Invention
The instant invention relates generally to locator devices and more specifically it relates to an emergency indicator system.
2. Description of the Prior Art
Numerous locator devices have been provided in prior art that are adapted to help people find different places and various objects that are lost or in need of help. While these units may be suitable for the particular purpose to which they address, they would not be as suitable for the purposes of the present invention as heretofore described.


A processor equipped with a pre-fetch function comprises: first layer cache memory having a first line size; second layer cache memory that is on the under layer of the first layer cache memory and that has a second line size different from the first line size; and a pre-fetch control unit for issuing a pre-fetch request from the first layer cache memory to the second layer cache memory so as to pre-fetch a block equivalent to the first line size for each second line size.

1. Field of the Invention
The present invention relates to a processor comprising cache memory having two or more layers of which the line sizes are mutually different, and, in particular, to a technique related to a processor equipped with a pre-fetch function applicable to the cache memory.
2. Description of the Related Art
A pre-fetch technique has conventionally been applied to a cache register in a computer executing a continuous access to memory used for a scientific calculation, such as a high performance computing (HPC), and the like.
The pre-fetch is a method for predicting instructions or data required in the near future and for reading them in cache memory or the like, and thereby a cache miss of the cache memory can be reduced.
Reference document 1 has disclosed a cache system equipped with a pre-fetch function. The system according to reference patent document 1 is configured to register, in a queue, a predicted address to be accessed next in the future distanced by a line size in a continuous access due to a cache miss when accessing memory data continuously and is configured to issue a pre-fetch instruction to the address to be accessed next in the future distanced by the line size by deciding that it is an event of continuous access, if the actual access address hits the queue, thus proving the prediction being correct.
If the line sizes between the upper layer cache memory and lower layer cache memory in multi-layered cache memory are different, the data size moved resulting from a cache miss in the lowest layer is any of the line size of the higher layer and of the lower layer. Further, in the case of a continuous access in which the function of a hardware fetch works, the case of the move-in data size being the lower layer line size of which the data size being the maximum exerts the highest performance and therefore the move-in data size is most possibly the data size of the lower layer cache memory in the above described case.
For example, in a memory system, the data size moved in by a cache miss is the line size of the lower cache in a memory access, while the data size is the line size of the higher cache in the case of a copy back.
In an HPC-series Job in which continuous access occurs in the majority of cases, a copy-back ratio is low, and therefore a move-in data size is highly possibly the line size of the lowest cache in the case of the above described continuous access.
Carrying out a pre-fetch in a cache memory system having different line sizes between the upper layer cache memory and lower layer cache memory causes the problem as follows.
If a data size moved in due to a cache miss in the lower layer is the line size of the lower layer cache, a request for a hardware pre-fetching issued from the upper layer cache to the lower layer cache (i.e., a request for a move-in to the lower layer cache) is only required for the line size of the lower layer cache. In the conventional cache system, however, the request is actually issued for each line size of the higher layer cache, resulting in the consuming of an extraneous lower layer cache access pipeline.
If a data size moved in due to a cache miss in the lower layer is the line size of the lower layer cache, a request for a hardware pre-fetching issued to the lower layer cache is only required for the line size of the lower layer cache. A hardware pre-fetching, however, sometimes loses a pre-fetch request due to implementation limitations, and in such a case of losing the request, only one issue of the pre-fetch request causes a failure in issuing a request for moving memory data into the lower layer cache.
If a data size moved in due to a cache miss in the lower layer cache register is the line size of the lower layer cache, a request for a hardware pre-fetching issued to the lower layer cache is only required for the line size of the lower layer cache memory. Therefore, if the address of a destination, which is next to upper layer cache memory by the line size thereof relative to the address which has been missed in the upper layer cache register is designated as the initial value of the pre-fetch address of a pre-fetch request, a lower layer cache access pipeline is wasted because of an extraneous pre-fetch request because there is a possibility that the address is the same line for the lower layer cache memory.
In the case of a continuous access to memory, in which a pre-fetch function works, a data size moved into the lower layer cache memory is highly possibly the line size of the lower layer cache and also possibly a data size different from the line size of the lower layer cache in some cases.
Patent document 1: Laid-Open Japanese Patent Application Publication No. 2004-38345

Processor equipped with a pre-fetch function and pre-fetch control method


An aerial refueling assembly includes, for example, a pressure transducer, a processor, and one or more light sources. The processor is coupled to the pressure transducer. The one or more light sources are coupled to the processor. The pressure transducer is configured to sense a fuel pressure inside the aerial refueling assembly and to provide a signal that is indicative of the sensed fuel pressure inside the aerial refueling assembly. The processor is configured to receive the signal and to cause the one or more light sources to flash in a manner that relates to the sensed fuel pressure.

During aerial refueling between two aircraft such as a tanker and a receiver, it is difficult to obtain real-time information about the aerial fueling process. If data is collected during the aerial fueling process, it is stored on a storage device mounted on the tanker. The data stored on the storage device can only be accessed and analyzed after the tanker has landed. The storage device is dismounted (e.g., unscrewed) from the tanker or the data is downloaded from the storage device by a technician on the ground. The analysis of the data might occur much later.

System and method for indicating pressure in aerial refueling assembly