The present invention relates to a semiconductor device, comprising a plurality of word lines arranged on a semiconductor substrate, wherein plurality of word lines are grouped into groups of two word lines, a spacer dielectric layer formed between each group of two word lines, and an interlayer dielectric layer formed so as to fill the area between the word lines in each group of two word lines and cover the word lines and the spacer dielectric layers.

This application claims the benefit of Korean Patent Application No. 10-2006-0137360, filed on Dec. 29, 2006, which is hereby incorporated by reference as if fully set forth herein.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same. More specifically, the present invention relates to a semiconductor device and a method of fabricating a semiconductor device with gap-filling and an interlayer dielectric layer between word lines.
2. Discussion of the Related Art
As the high integration of a semiconductor device is progressed, the spaces between patterns have become narrower, meaning that the process of filling an interlayer dielectric layer for the interlayer insulation between metal-wirings in the spaces has become increasingly difficult.
In particular, the cell arrays of semiconductor devices are formed with a minimum line width and pitch, meaning that the gap between the word lines is often too narrow to facilitate a sufficient filling of the gap formed at the both sides of the word line.
In flash memory devices, the vertical size of the word line is large enough that the gap between the word lines has a high aspect ratio compared to other devices. Further, since the width of the lower portion word line is larger than the upper portion of the word line, the gap between the word lines at the area close to the substrate is small, meaning that the interlayer dielectric layer may not completely fill the gap, creating a void in the gap.
FIG. 1 is a cross-sectional view of a semiconductor device of the current art. FIG. 1 describes a flash memory device as an example of a semiconductor device. The flash memory device includes a device isolating layer 12 formed on the semiconductor substrate 10 which defines active areas 18 and a plurality of word lines 14 arranged across the top of the active areas 18 of the device isolating layer 12. The gaps between adjacent word lines 14 alternate between relatively narrow gaps 26 and wide gaps 28. The area in the relatively narrow gap 26 forms a source area 22, while the portion in the relatively wide gap 28 forms a drain area 24 which may be connected to a bit line contact (not shown).
In order to connect the source areas 22 in a direction parallel with the word lines 14, a portion of the device isolating layer 12 between the word lines 14 below each narrow gap 26 is removed, and the sides of the word lines 14 are formed with spacer dielectric layers 16s and 16d. The spacer dielectric layer 16s is formed between alternating adjacent word lines 14 in order to fill the narrow gap 26, and the spacer dielectric layer 16d is formed between in the remaining word lines 14 in order to reduce the size of the wide gap 28.
Typically, an interlayer dielectric layer 20 is subsequently formed over the substrate 10, word lines 14, and the spacer dielectric layers 16s and 16d, so as to completely fill the gaps 26 and 28 between the word lines. Unfortunately, however, because of the small size and the shape of the resulting gap 20a between the word lines 14, which often has a wider base than top, it is often difficult to sufficiently fill the resulting gap 20a with the interlayer dielectric layer 20, leaving voids or bubbles in the resulting gap 20a near the substrate 10.

Semiconductor device and method of fabricating the same


Method and device for extracting a specified image subject including an extracting condition of an extracting algorithm of a subsequent stage so as to be adapted to an extraction result by the extracting algorithm of a precedent stage, when specified image subject extracting algorithms are successively implemented. At the time of performing the specified image subject extracting algorithms in each stage by parallel processing, the method and device manage extraction states of each step and qualify extraction processing conditions in the subsequent stage in accordance with the extraction states in the precedent stages. The method and device perform a vote in an N-dimensional space of image characteristic quantity for each extraction area by the specified image subject extracting algorithm and then perform weighting of degree of certainty as the specified image subject based on an aggregation value of the vote within a section area for aggregation in the N-dimensional space.

The present invention relates to a method and a device for extracting specified image subjects and, more particularly, to a method and a device for extracting a specified image subject which is capable of maintaining extraction performance of specified image subject, for example, a human face in an ordinary scene and enhancing extraction performance of a specified image subject, for example, a human face in a scene shot with a close-up electronic flash or back-light.
Heretofore, the images recorded on photographic films such as negatives and reversals (which are hereunder referred to simply as "films") have been commonly printed on light-sensitive materials (photographic paper) by means of direct (analog) exposure in which the film image is projected onto the light-sensitive material to achieve its areal exposure.
A new technology has recently been introduced and this is a printer that relies upon digital exposure. Briefly, the image recorded on a film is read photoelectrically, converted to digital signals and subjected to various image processing operations to produce image data for recording purposes; recording light that has been modulated in accordance with the image data is used to scan and expose a light-sensitive material to record a latent image, which is subsequently developed to produce a (finished) print. The printer operating on this principle has been commercialized as a digital photoprinter.
In the digital photoprinter, images can be processed as digital image data to determine the exposing conditions for printing; therefore, the digital photoprinter is capable of performing effective image processing operations such as the correction of washed-out highlights or flat shadows due to the taking of pictures with backlight or an electronic flash, sharpening and the correction of color or density failures and this enables the production of high-quality prints that reproduce images of the quality that has been impossible to achieve by the conventional direct exposure technique. In addition, not only the assembling of images and the splitting of a single image into plural images but also the compositing of characters can be performed by processing the image data and, as a result, prints can be outputted after various editing and/or processing operations have been performed in accordance with specific uses.
Outputting images as prints is not the sole capability of the digital photoprinter; the image data can be supplied into a computer or the like and stored in recording media such as a floppy disk; hence, the image data can be put to various non-photographic uses.
Having these features, the digital photoprinter is basically composed of an image input machine and an image output machine. The image input machine has a scanner (image reading apparatus) that reads the image on a film photoelectrically and an image processing apparatus that processes the captured image to produce output image data (exposing condition). The image output machine has a printer (image recording apparatus) that records a latent image on a light-sensitive material by scan exposing it in accordance with the image data supplied from the image input unit and a processor (developing apparatus) that performs development and other necessary processing on the exposed light-sensitive material to produce a print.
In the scanner, reading light issuing from a light source is allowed to be incident on a film, from which projected light bearing the image recorded on the film is produced and focused by an imaging lens to form a sharp image on an image sensor such as a CCD sensor; the image is then captured by photoelectric conversion and sent to the image processing apparatus as data for the image on the film (as image data signals) after being optionally subjected to various image processing steps.
In the image processing apparatus, image processing conditions are set on the basis of the image data captured with the scanner and image processing as determined by the thus set conditions is performed on the captured image data and the resulting output image data for image recording (i.e., exposing conditions) are sent to the printer.
In the printer, if it is of a type that relies upon exposure by scanning with an optical beam, the latter is modulated in accordance with the image data sent from the image processing apparatus and deflected in a main scanning direction as the light-sensitive material is transported in an auxiliary scanning direction perpendicular to the main scanning direction, whereby a latent image is formed as the result of exposure (printing) of the light-sensitive material with the image bearing optical beam. In the processor, development and other processing as determined by the light-sensitive material are performed to produce a print reproducing the image that was recorded on the film.
If the original image contains a human individual, his or her face is the most important when the original image is reproduced by the photoprinters whether they are digital or of the conventional analog type (the two types are hereinafter collectively referred to as "photoprinters") and the quality and evaluation of the reproduced image, or print, are greatly affected by how beautifully the face of the human individual is finished.
To deal with this problem, the conventional photoprinters extract the face (face region) of a human individual from the image on a film and determines exposing conditions (image processing conditions for producing output image data in the case of a digital photoprinter, and the amount of exposing light and the amounts by which color filters are to be inserted in the case of an analog photoprinter and the like) that enable the face to be finished in the desired way.
Particularly in the case of a digital photoprinter which is capable of very flexible image processing through the processing of image data, the information on the face is important for setting image-dependent optimal image processing conditions and performing the appropriate face extraction is the way that enables high-quality prints to be produced in a more consistent manner.
Under these circumstances, various methods of subject extraction have so far been proposed for extracting various kinds of specified image subjects such as principal image subjects inclusive of the face and the like. To mention a few examples, skin color extraction using the color hues and chromas of an image and contour extraction by detecting the edge portions of an image are known.
However, the state of the images on films varies with the shooting conditions under which the images were taken, such as whether they were shot with an electronic flash or backlight, or whether the films were overexposed or underexposed or whether color failure occurred. Hence, each of these methods of extraction that has been proposed to date cannot ensure consistent and precise face extraction from various states of images.
The precision of face extraction can be improved by combining a plurality of methods of extracting image subjects. However, in order to perform consistent and precise face extraction from various states of images, many methods of extraction have to be combined and the time of performing the necessary processing and calculations to extract the desired image subject will inevitably increase to cause undesired effects such as the decrease in the efficiency of print production.

Method and device for extracting specified image subjects


A DRAM controller is incorporated onto an existing microcontroller architecture. Existing chip select signals or other signals on the microcontroller are multiplexed with RAS and CAS signals. The RAS and CAS signals are asserted when an address is within a specific programmable address range and DRAM mode is enabled. The pins selected for RAS and CAS provide regular signals such as chip selects when not in DRAM mode. The timing of the chip select signal signals are adjusted when the chip select signals are utilized as column and row address strobes. Additionally, multiplexed addresses are provided from the microcontroller as well as refresh control. The microcontroller can provide high byte and low byte access by providing an upper column address strobe signal (UCAS) to support access for high byte and word access and a lower column address strobe signal (LCAS) to support low byte and word access. Mid range chip selects provide the UCAS and LCAS signals. A lower chip select signal (LCS) may provide a first RAS signal which is active in a first DRAM mode. The LCS signal is asserted as a first RAS signal when an address within a programmable memory range and the first DRAM mode is enabled. A second RAS signal provides access to a DRAM mapped into the upper half of memory. A mid range chip select pin is multiplexed with the second RAS signal.

1. Field of the Invention
This invention relates to computers and more particularly to integrating a dynamic random access memory (DRAM) controller onto a microcontroller.
2. Description of the Related Art
Controllers for DRAMs are known in the art. In microcontrollers, various level of support for DRAMs has been provided. For example, the AM186.TM.ES microcontroller provides support logic for refresh. Refreshing DRAMs is necessary to maintain the integrity of the DRAM contents, as is known in the art. However, DRAMs also typically require the address bus to be mulitplexed between rows and columns and require row and column address strobes (RAS and CAS), respectively indicating the presence of the row and column address on the bus. While prior art processors may include DRAM controllers, integrating a DRAM controller onto an existing microcontroller architecture that did not previously provide DRAM support can cause problems in, e.g., maintaining pin compatability with the existing microcontroller design. In the AM186.TM.ES microcontroller, DRAM support logic external to the microcontroller is still required to provide, e.g., RAS/CAS signals and multiplexed address bits to the DRAM. Externally provided DRAM control logic requires additional parts and space. Further, externally provided DRAM support logic can result in slower access time to the DRAMs. Such slower access time can be accommodated by incorporating wait states into the bus cycles to give the external device time to, e.g., provide requested data. For example, the AM186.TM.ES processor must insert wait states for DRAM access when the externally supplied clock speed of the microcontroller is, e.g., 40 MHz.

Multiplexing DRAM control signals and chip select on a processor


A system recognizes an occurrence of offline action when a state in which a person-to-be-recorded does not perform a computer operation continues for or longer than a predetermined time. Then, action related information such as action schedule information about a person-to-be-recorded, movement position information indicating the position of a person-to-be-recorded, immobile target position information indicating the position of an immobile target such as a building, a point on a map, etc., position-action correspondence associating the immobile target position information with the content of offline action, etc. is acquired. According to the information, the content of the offline action is estimated. When a next computer operation is detected, the estimated content is displayed for confirmation by the person-to-be-recorded. The system accepts and records the input of supplement, amend, approve, etc. from the person-to-be-recorded.

1. Field of the Invention
The present invention relates to the technology of supporting recording the action of a person.
2. Description of the Related Art
Conventionally, a system for improving an operation has been well known. For example, when the current operation procedure and work time are input, the system analyzes the current situation and outputs an improvement proposition. It is necessary for the analysis of the current situation to detect the time taken for each task constituting the operation. As a result of the analysis, the point where waste resides is detected and the improvement proposition is output.
The system of the patent document 1 is an example of the conventional operation analysis support system. When the current operation procedure, etc. is input, the system quantifies the operation, compares it with a predetermined operation feature pattern and generates a model, and displays the feature of the operation, the model, and the improvement proposition. The form of input data is a table form for comprehensibility of a user. However, relating to data, it is necessary for the user to grasp and input the operation contents, process target, etc. by a hearing against operators, etc.
The conventional system is suitable for operations whose operation procedure is prepared. For example, it is suitable for a case such as a production line in a factory, etc. where the procedure of an operation is definite, an observer can visually confirm what an operator is doing, etc. because the observer can easily measure the time for each operation using a watch, etc. However, since correctly grasping and inputting an operation procedure of a non-prepared operation through a hearing, etc. is restricted, it is not expected to correctly analyze a non-prepared operation.
On the other hand, in an operation mainly performed as desk work, the procedure of the operation is not definite. Additionally, when a plurality of operations to be concurrently performed are included, the action itself is hardly measured externally. For example, a system engineer, a researcher, etc. who are engaged in knowledge work always think about their work, but can hardly be understood visually. At present, for the operations performed using computers in the desk work, the operation contents and the work time can be automatically grasped and analyzed to some extent by monitoring the computer operations. For the work not including computer operations, there is no system capable of grasping offline action even for a comparatively long time such as 30 minutes, 1 hour, etc. However, since a long recording time is required and it degrades the efficiency of the entire operation, it is not preferable to keep a record by allowing an operator to manually input a description of the operation contents and work time or select an option only because it is necessary to grasp the offline action to improve the operation. Therefore, it is desired to develop a system for automatically or semi-automatically recording the operation contents and operation procedure of an operator who is mainly engaged in desk work regardless of whether or not the operation includes a computer operation.
The operation not including a computer operation can include an operation which includes moving of a person such as going out and having a meeting with a client, etc. The patent documents 2 through 5 disclose systems which detect moving of a person.
The system of the patent document 2 performs the process depending on whether or not a user is present at his or her desk (for example, a message is accepted when the user is absent). A user can explicitly instruct the computer on his or her desk that he or she is absent or present, and the system can estimate the presence/absence state. The estimation is performed based on the location of a user detected by a camera, etc., schedule information, presence state history, etc.
The system of the patent document 3 estimates the action and the position of a user from a personal schedule table, and when a user terminal has the GPS (global positioning system) function, an estimated position is amended according to the GPS information, and a Web screen on which a map and store information, etc. relating to the position is displayed in a user-selectable manner is transmitted to the user terminal.
The system of the patent document 4 analyzes the movement of a user according to the position information and the time information noticed from a mobile terminal. In this system, the transportation, etc. used for travel is estimated based on the moving speed and a locus.
The patent document 5 discloses a terminal for recording a predetermined operation contents by a user pressing a predetermined key of the terminal and managing an operation. The movement such as a walk, etc. is a large factor of a loss in work. However, since it is repeated at a high frequency, it is not desired to input data to a terminal each time travel is performed because it is a laborious process. Therefore, the terminal further includes a vibration sensor, and automatically detects and records the movement of a walk, etc. of a person who carries the terminal.
However, the above-mentioned systems have the problems that they concentrate on the position and movement of a person, does not associate them with actual action, cannot correspond to a non-prepared operation, etc. Therefore, they are not suitable for use in automatically recording or supporting a user for semi-automatically recording in a unified method operation contents and a work time of work which includes an operation performed with a computer operation and an operation performed without a computer operation, and can be hardly prepared in a form.                [Patent Document 1] Japanese Patent Application Laid-open No. 2002-352064        [Patent Document 2] Japanese Patent Application Laid-open No. H10-268959        [Patent Document 3] Japanese Patent Application Laid-open No. 2002-189656        [Patent Document 4] Japanese Patent Application Laid-open No. H10-111877        [Patent Document 5] Japanese Patent Application Laid-open No. H11-143935

Action record support program, system, device, and method


A radio frequency antenna for use with a wall mounted transmitter and/or receiver for receiving and/or transmitting signals adapted to control a control device and/or indicate status of the control device. The antenna includes an insulating substrate sized to fit within an area defined by a faceplate sized to cover an outwardly facing opening of an electrical wallbox. Conductors are disposed on both sides of the substrate forming a capacitive component. At least one of the conductors is adapted to radiate radio frequency energy into the environment. The one conductor is electrically coupled to the other conductor, and the one conductor has a pattern such that the conductor is absent in areas so as to provide the antenna with an inductive component. The at least one conductor further provides a connection to the transmitter and/or receiver. The antenna provides an antenna near-field which is substantially at the edges of the substrate and which provides insubstantial electromagnetic field coupling to an electronic circuit disposed adjacent the antenna connected to the antenna and further provides a radiated field substantially isotropic in the antenna far-field.

The present invention relates to antennas and, in particular, to radio frequency antennas for transmitting and receiving radio frequency signals. Even more particularly, the present invention relates to a compact antenna which is provided for use in connection with a radio frequency controlled lighting control system. In particular, the present invention relates to an antenna which is provided on a lighting control device, for example, a light dimmer, and which receives and transmits radio frequency signals for controlling a lamp and communicating status of the lamp e.g., on, off and intensity level. The radio frequency signals are used to control from a remote location the status of the lamp connected to the light dimmer and also to provide information back to a master location concerning the status of the controlled lamp. The device at the master location may also employ the antenna according to the invention.
The invention also relates to a control device employing the antenna that can be mounted in a standard electrical wall box. In particular, the invention also relates to a local electrical control device capable of remotely controlling one or more electric lamps and adapted to be mounted in a standard electrical wall box and receiving and transmitting signals via the antenna. The invention further relates to a master control device capable of remotely controlling one or more electrical control devices and adapted to be mounted in a standard electrical wall box and employing the antenna to transmit to and receive signals from a local electrical control device which responds to the control signals from the master device.
Although the present invention is directed to an antenna for use in a lighting control system, the antenna of the present invention can be applied to the communication of signals relating to the control and status of other devices, for example, communication equipment, motors, security systems, appliances, HVAC systems (heating, ventilating and air conditioning).
The present invention is directed to an antenna of compact design which can be included within the lighting control device, for example, a light dimmer, and which fits into standard electrical wall boxes. The invention is also directed to the lighting control device itself, whether a master or local (remote) unit. The invention is of particular use in a system using radio frequency signals to control the status of lamps. In such a system, the conventional manually controlled hardwired lighting control devices, for example, wall switches and dimmers, are replaced by a dimmer having a control circuit and an antenna according to the present invention. The system in which the antenna according to the present invention is used is thus provided to enable an existing building lighting system (or other electrical/electronic devices) to be controlled remotely from various locations, without requiring hardwiring of the building to incorporate the necessary control system to accomplish remote control of lighting fixtures or other devices. Accordingly, in the system in which the antenna or lighting control device of the present invention is used, the lighting control device, e.g., a light dimmer which replaces a conventional light switch/dimmer, contains an antenna according to the present invention, the necessary actuators for accomplishing manual control of the light fixture, as well as a control circuit and RF circuit for allowing remote control via signals received and transmitted by the antenna of the lighting control device. The antenna and control device fit within a standard electrical wall box (or the antenna is sized so that it fits within the area defined by the faceplate of the wallbox), allowing the conventional lighting control device to be removed and replaced by the lighting control device according to the invention. Similarly, a master unit according to the invention having actuators thereon and an antenna for transmitting signals to the local control devices and receiving status signals from the local control devices is also adapted, according to one embodiment of the invention, to be disposed in a conventional electrical wall box. The antenna can be disposed completely or partly within the wallbox or it is sized so as to fit partly or completely outside the wall box at the wallbox opening but within the area defined by the faceplate of the wallbox.
In accordance with the present invention, the antenna is of compact size, fits within a standard electrical wall box or within the area defined by the faceplate of the wallbox and is a part of the electrical control device for controlling the lamp. The electrical control device also fits substantially within the standard electrical wall box.
There are various systems known in the prior art which allow for remote control of lamps without hardwiring control lines to the lighting control devices.
In one prior art system, a user can install a so called three-way electrical switch, i.e., an additional light control switch to an existing hardwired single control system by replacing an existing manually operated lighting control device with a lighting control device having a radio frequency receiver incorporated therein. The replacement lighting control device is hardwired into the electrical system in the same way as the conventional device to control the lamp. The radio frequency receiver is responsive to radio frequency signals generated by a remote battery powered switching device having a transmitter which can be conveniently affixed to a building wall at another location, thereby to provide the three-way switch circuit. The additional battery powered lighting control device has a manually operated lever, which when operated, sends an RF signal to the other electrical control device which is hardwired into the building's electrical system. The hardwired device will then toggle in response from its present state to the opposite state, i.e., from on to off or off to on. Thus, either switching device, the hardwired replacement or the battery powered device, can operate the lamp. Accordingly, a three-way electrical switch can be provided into an existing electrical system without hardwiring the three-way switch into the system.
In this prior art system, having the battery powered transmitting switch and the hardwired switch including a receiver, the hardwired receiving switch includes a whip antenna made from a piece of insulated wire which is allowed to dangle out of the electrical box either outside the building wall or inside the wall. In the case where the whip antenna is allowed to dangle outside the wall, an unattractive, aesthetically displeasing appearance is obtained. In the case where the whip antenna is allowed to dangle inside the wall, although hidden, the wire creates reception and installation problems as well as a danger that the wire may become shorted to other cables or grounds, presenting an electrical hazard or preventing the antenna from working.
In this prior art system, the battery powered transmitter generally includes a printed circuit board loop antenna. Another problem with this system is that the battery powered switch and hardwired switch must be located within a certain distance of each other in order for the system to operate.
In another prior art system, known as the X10 system, standard lighting control devices are replaced by lighting control devices operating via a power line carrier (PLC) communication system, i.e., information for operating the lighting control devices is provided over the building's existing power line by a power line carrier (PLC). In addition, in some of these systems, an RF communications link is also provided so that a hand-held remote control master device can be used to operate the various lighting control devices. In these systems, an RF repeater may also be provided. In the X10 system, only one-way communications is provided so that a master unit is not apprised by a lighting control device of the status of the controlled light fixtures.
In the X10 system, a radio frequency to PLC bridge is provided to convert radio frequency signals into power line carrier (PLC) communications signals. The RF to PLC bridge plugs into an existing wall outlet and provides the PLC carrier onto the electrical power line to be received by the controlled lighting control device. The antenna of the RF to PLC bridge is also, as in the case of the three-way switch described above, visible. Typically, the RF to PLC bridge comprises a box which is plugged into an existing wall electrical outlet, and has an antenna for receiving signals from the master controller or a repeater.
In addition to the X10 system, there are also known two-way communications links for providing, in general, home automation. These include the Electronic Industries Association Consumer Electronics Bus (CEBus) (EIAIS-60) protocols for radio frequency media, power line carrier media, infrared media and twisted pair media, and the Echelon Corporation LONworks. Intellon Corporation provides transceivers that comply with the CEBus standards for radio frequency and power line carrier. Echelon provides transceivers that comply with their communication protocol. None of these radio frequency transceivers package easily within the allowed area of a device as described by NEMA standards that fit in an electrical wallbox.
In addition to the above, a system known as the Smart House supplied by Smart House LP is also available. This system comprises a wired system and, accordingly, would entail expensive alteration and dislocation if applied to the control of electrical devices, particularly lighting in a home.
In addition to the above, the assignee of the present application offers systems known as HomeWorks, NetWorks and LuMaster which are hard-wired control systems controlling lighting devices. Although these systems are suitable for new construction, they entail major alteration and dislocation when applied to existing homes.
Also becoming available are wireless local area networks (LANs) for computer systems, which employ radio frequency communication methods ensuring that all nodes of the network can communicate with each other. See, for example, Electronic Design, Jun. 26, 1995, page 55.

Compact radio frequency transmitting and receiving antenna and control device employing same


Methods and systems are disclosed for assessing a quantitative image volume from an individual subject comprising comparing the image from the subject to images from a control group of subjects using voxel-wise comparison. The methods allow detection of pathologies or lesions in the individual subject being assessed.

Throughout this application various publications are referred to in parentheses. Full citations for these references may be found at the end of each section of Experimental Details. The disclosures of these publications are hereby incorporated by reference in their entireties into the subject application to more fully describe the art to which the subject application pertains.
Group-wise analyses of imaging have demonstrated evidence of injuries or pathologies associated with adverse clinical outcomes. Although the injury or pathology is likely to have a unique spatial pattern in each patient, group analyses implicitly assume that location of injury will be the same across patients.
Diffusion Tensor Imaging (DTI), for example, reveals white matter abnormalities in mild traumatic brain injury (mTBI), consistent with traumatic axonal injury (TAI), the presumptive pathologic substrate of adverse clinical outcomes after TBI (e.g., 1-9). Analyses comparing groups of mTBI patients and controls, employed almost universally in mTBI research, implicitly assume location of injury will be the same across subjects. This approach is inherently insensitive to intersubject variation in location of pathology, a highly questionable assumption, given the wide variation in mechanism of injury and patient characteristics (10, 11). Furthermore, clinical use of DTI requires assessment of individual patients. An approach to identifying loci of brain injury in individual mTBI patients is needed to fully understand the nature and extent of mTBI pathology toward personalizing and improving clinical practice.
Few studies have assessed DTI in individuals (4, 8, 12, 13). Viviani, et al. used cross-validation, a resampling technique, to estimate the distribution of extreme values across the whole brain in stroke and glioblastoma (12). They proposed empirical and calibrated thresholds, based on the Family-Wise Error Rate (FWER). FWER for control of Type-I error rate in neuroimaging data may be overly conservative, however (14). Singh, et al. employed a "one vs. many" T-test, comparing TBI patients to a control group, utilizing a priori thresholds (individual voxel and cluster level), but not reporting validation or effectiveness testing of the thresholds (8). The "one vs. many" T-test approach has also been applied to chronic mTBI (4). Importantly, none of the published studies included validation to address efficacy or clinical utility of DTI as a diagnostic test.
At present, no method is available that allows quantitative detection of imaging abnormalities on a voxelwise basis in individual patients. The imaging methods themselves exist and are approved for human use, but are not utilized because no methods exist to extract meaningful information from the images. The ready availability of such an approach would open the door to quantitative imaging in clinical use. The present invention addresses the need for a personalized approach for detecting pathology or injury in individual patients, which could detect inter-individual differences and be applied in the clinical setting, where patients must be assessed as individuals.

Methods for quantitative assessment of volumetric image from a subject and uses therof

Albert Einstein College of Medicine, Inc.


This invention involves an electronic cigarette atomizer, including an oil-guiding element and a heating wire wound around the oil-guiding element; the oil-guiding element is a strip of fiber textile, which is derived from fibers via weaving and glue-removing processes. The invention further provides an electronic cigarette, including an atomizer, a nozzle at one end of the atomizer and a battery assembly at the other end thereof, the atomizer including the oil-guiding element and heating wire around it, the oil-guiding element being a strip of fiber textile, being derived from fibers via weaving and glue-removing process. The oil-guiding element of the invention is the strip of fiber textile via weaving and glue-putting process, the fibers are closely combined which effectively avoids loosened slim fibers inhaled into the human body, is more helpful to users' health; moreover the fiber textile has a heat-resistance up to 400 degrees Celsius, and better security.

The existing electronic cigarette usually includes an atomizer, an oil reservoir, and a nozzle and a battery assembly respectively connected to two ends of the atomizer. Among this, the atomizer comprises an atomizing tube, an oil-guiding element configured within the atomizing tube, and a heating wire wound around the oil-guiding element, while the oil storage element can be configured within the nozzle or the atomizing tube.
Commonly used oil-guiding elements are glass fiber bundles or other fiber bundles, since the used fiber bundles have not been effectively fastened and thus are easy to loose, in the use of the electronic cigarettes, small fibers are easy to be inhaled into the human body, and thus adversely affect the health of the human body. In addition, the existing fiber bundles usually only resist a temperature of no higher than 200 degrees Celsius, while the electronic cigarettes work, the heating wire is heated up easily to more than 200 degrees Celsius, so there are serious security risks.

HUIZHOU KIMREE TECHNOLOGY CO., LTD., SHENZHEN BRANCH


A plurality of elongated, substantially planar, elastomeric members are assembled together in a stack such that the members are generally aligned with each other. The members are made of tire treads. An elongated, substantially planar, rigid first plate is positioned on top of and aligned with the stack of members. An elongated, substantially planar, rigid second plate is positioned beneath and aligned with the stack of members. Fastening apparatus is provided for holding the first plate, the second plate and the stack of members together. The fastening apparatus includes bolts or rivets which penetrate the plates and the stack of members, forming a non-perpendicular angle with a longitudinal axis of the members. An anchoring apparatus is provided for anchoring a first rail to a first end of the crosstie, and for anchoring a second rail to a second end of the crosstie.

1. Field of the Invention
The present invention relates to railroad crossties.
2. Description of the Related Art
Conventional, treated wooden crossties eventually rot and must be replaced. Concrete crossties have a history of breaking. Rotted and broken ties can lead to train derailments. What is needed is an inexpensive, long lasting railroad crosstie which does not rot or break.


An electrical discharge surface treatment method for forming a coating film by generating a pulsed electrical discharge between an electrode and a workpiece in working fluid or gas using a green compact obtained by molding metal powder or metal alloy powder or a molded body obtained by heating the green compact as the electrode, and by melting an electrode material by an energy of the pulsed electrical discharge, forming a coating of the electrode material or a coating of a material obtained by a reaction of the electrode material by the energy of the pulsed electrical discharge on a surface of the workpiece, the electrical discharge surface treatment method includes generating the pulsed electrical discharge by mixing together two or more types of pulsed electrical discharges having different energies.

A technique for enhancing corrosion resistance and wearing resistance by coating a surface of a metal material by a submerged electrical discharge processing method is heretofore known. An example of the technique is as follows. For example, a method has been disclosed in which a pulsed electrical discharge is performed in working fluid with an electrode obtained by compression molding a mixture of fine particles of WC (tungsten carbide) and Co (cobalt) to deposit the electrode material on a workpiece, and thereafter re-melt discharge processing is performed with another electrode (for example, a copper electrode or a graphite electrode) to obtain even higher hardness and enhanced adhesion (see, for example, Patent Document 1). In Patent Document 1, electrical discharge processing is performed on a workpiece (a base material S50C) in working fluid using a WC—Co mixed green compact electrode to deposit the WC—Co on the workpiece (primary processing), and subsequently, re-melt processing (secondary processing) is performed using an electrode that is not relatively susceptible to wearing, such as a copper electrode. As a result, although the deposited structure has a hardness (Vickers hardness Hv) of about Hv=1410 with a considerable amount of voids after the primary processing, the voids of the coating layer disappear with enhanced hardness of Hv=1750 by the secondary processing of the re-melt processing. With this method, a coating layer having a great hardness with enhanced adhesion is obtained for steel as the workpiece.
However, with the above method, it is not possible to form a coating layer having robust adhesion on a surface of a sintered material, such as cemented carbide, as the workpiece. In regard to this point, researches performed by present inventors have shown that a robust hard coating can be formed on a metal surface of a workpiece without performing the re-melt processing by generating electrical discharge between an electrode and the workpiece, using a material such as Ti (titanium), which forms hard carbide, as the electrode. This is because the electrode material worn by the electrical discharge and C (carbon) in the working fluid react with each other, and as a result, TiC (titanium carbide) is produced.
Furthermore, a technique has been disclosed in which a hard coating film can be formed with good adhesion faster than a case of using materials such as Ti and the like by generating electrical discharge between a workpiece and an electrode by using a green compact obtained from a metal hydride such as TiH2 (titanium hydride) as the electrode (see, for example, Patent Document 2). In addition, another technique has been disclosed in which a hard coating film having properties of hardness, wearing resistance and the like is formed in a rapid manner by generating electrical discharge between a workpiece and an electrode by using a green compact obtained from a mixture of the metal hydride such as TiH2 and the like and metal or ceramic.
Further, still another technique has been disclosed in which an even stronger surface treatment electrode can be manufactured by pre-sintering (see, for example, Patent Document 3). That is, when manufacturing an electrical-discharge surface-treatment electrode made of a mixed powder of the WC powder and the Co powder, although a green compact can be obtained by simply compression molding the mixture of the WC powder and the Co powder, if it is compression molding after mixing wax, the molding property of the green compact is enhanced. In this case, because the wax is a dielectric material, when a considerable amount of wax remains in the electrode, an electrical resistance of the electrode increases, resulting in degradation of the discharge property. Therefore, the green compact electrode is heated in a vacuum furnace to remove the wax.
At this time, when the heating temperature is too low, the wax is not completely removed, and when the heating temperature is too high, the wax turns into soot, which degrades purity of the electrode. Therefore, the heating temperature needs to be maintained between a temperature at which the wax is melted or higher and a temperature lower than the wax is dissolved to turn into the soot. By heating the green compact in the vacuum furnace using a high-frequency coil and the like, it is baked until it has a hardness of about, for example, a chalk, and giving a strength to resist a machining process, paying attention not to harden excessively. This state is referred to as a pre-sintering state. In this case, although a bonding is progressed in an area of contact between carbides in the green compact, the bonding is weak because the sintering temperature is relatively low not reaching regular sintering. It has been proved that a dense and homogeneous coating film can be formed by performing electrical discharge surface treatment using an electrode formed in the above manner.
However, the conventional techniques described above need a further improvement because, although they are featured in points of the hardness and adhesion of the coating film, the wearing resistance and the swiftness of forming the coating film, and the density and homogeneity of the coating film, all the techniques fail to obtain sufficient thickness of the coating film.
A common technique for obtaining a thick coating film is so-called welding/thermal spraying. The welding (which means cladding by welding in this context) is a method of depositing a material of a welding electrode on a workpiece by melting the welding electrode with electrical discharge between them. The thermal spraying is a method of forming a coating film on a workpiece by melting a metal material and spraying it onto the workpiece. Because both methods are done by a human, requiring a skilled workforce, it is difficult to make the work a line operation, having a disadvantage of high manufacturing cost. Particularly, because the welding is a method in which the heat is applied to the workpiece in a concentrated manner, it causes a problem that a weld cracking occurs and a yield rate is low when processing a thin or fragile material.
Although it is described that a thick coating film of about 3 millimeters has been obtained using a WC—Co (9:1) electrode in electrical discharge surface treatment in a document based on the researches conducted by the present inventors (see Nonpatent Literature 1), it does not reach a level that can be practically applicable because of problems that the reproduction of the coating film is difficult because the formation of the coating film is unstable, the coating film is brittle having a considerable amount of voids although it is seemingly dense with a metallic gloss, and the coating film is so weak that it is removed when it is scratched hard with a metal piece and the like.
Subsequent researches have shown that a dense and thick coating film can be formed by electrical discharge surface treatment by mixing a predetermined amount or more of a metal material that does not form carbide or hardly forms carbide in the electrode material. That is, a thick coating film can be formed by increasing materials such as Co (cobalt), Ni (nickel), and Fe (iron) in the electrode material, reaching a level that can be practically applicable as a thick coating film (see Patent Document 4).    Patent Document 1: Japanese Patent Application Laid-open No. H5-148615    Patent Document 2: Japanese Patent Application Laid-open No. H9-192937    Patent Document 3: Japanese Patent No. 3227454    Patent Document 4: International Publication No. WO 04/011696 pamphlet    Nonpatent Literature 1: Technique of "Formation of Thick Layer by Electrical Discharge Coating (EDC)" Akihiro GOTO et al., (1999), THE NIKKAN KOGYO SHIMBUN, LTD.

Electrical discharge surface treatment method


An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a semiconductor substrate containing a chip area and a peripheral pad area surrounding the chip area, wherein a conductive pad and a through hole exposing the conductive pad are formed in the peripheral pad area; a protection layer covering a bottom surface of the semiconductor substrate and the through hole; a packaging layer formed on an upper surface of the semiconductor substrate; and a spacing layer formed between the packaging layer and the semiconductor substrate, wherein the chip packaging has a main side surface constituted of side surfaces of the semiconductor substrate, the protecting layer, the packaging layer and the spacing layer, and wherein the main side surface has at least one recess portion.

1. Field of the Invention
The present invention relates to a chip package, and in particular relates to a chip package having reduced stress at the interface between layers and a method for fabricating the same.
2. Description of the Related Art
Wafer level packaging techniques have been developed for chip packaging. A semiconductor wafer is usually bonded to a glass substrate with a spacing layer disposed therebetween. After a wafer level package is accomplished, a dicing step is performed between chips to divide them into individual chips.
An ordinary chip package may comprise a semiconductor substrate, a protection layer, a spacing layer and a glass substrate. There are some interfaces between them. However, the materials and their expansion coefficients of the above layers are different from each other. Thus, delamination may occur at the interface between any two adjacent layers of the semiconductor substrate, the protection layer, the spacing layers and the glass substrate. Therefore, moisture and air will penetrate into the chip package and result in poor electrical characteristics of the chip package.
A novel chip package and a fabrication method thereof are needed to address the above issues.

Chip package and fabrication method thereof


A method and an apparatus for verification of arithmetic digital circuits is disclosed, wherein a first circuit, called a specification, is compared for equivalence with a further circuit called an implementation, with equivalence occurring when and only when the specification and implementation always produce the same output signals for the same input signals. The gate level description of the specification and implementation are converted to a network of elementary arithmetic 1-bit operations (XOR, half-adders, full adders) and the equivalence of the specification and implementation is identified in that a comparison of the resultant networks from elementary arithmetic 1-bit operations is carried out directly.

1. The Field of the Invention
The invention relates to a method for verification of digital arithmetic circuits by means of an equivalence comparison between a specification circuit and an implementation circuit. Furthermore, the invention relates to an apparatus for carrying out this method.
2. The Relevant Technology
Procedures are known in which a so-called equivalence comparison is carried out (equivalence checking). On the one hand, this may be done by simulating all the possible combinations of input signals with the corresponding circuits. This exhaustive simulation has the disadvantage that, as the complexity of the circuits increases, the number of necessary computation operations rises correspondingly steeply. Although the use of graphical representations of Boolean functions according to R. Bryant, "Graph-based algorithms for Boolean function manipulation" (IEEE Transactions on Computers, C-35(8), 1986, and their further developments, allow considerably larger circuits to be handled than in the exhaustive simulation, even this procedure reaches its limits with most circuits of industrial size.
Attempts have thus likewise been made to investigate the circuits first of all on the basis of their structure. In this case, in two circuits which are to be compared,internal points which are equivalent are sought. This means that the logical signals which are present at these points in response to identical input signals are the same. In this way, it is possible to compare subregions of the circuits with one another. If it can be verified that these subregions are equivalent, this knowledge can be used directly in the subsequent investigation of further areas, thus allowing step-by-step equivalence comparison of the entire circuit. The input and output points of these internal subregions are in this case referred to as internal equivalence points (internal equivalences) or cut points. As an example of such methods, which are also referred to as "structural equivalence comparison", reference should be made to D. Brand, "Verification of Large Synthesized Designs" in Proc. Intl. Conf. on Computer-Aided Design (ICCAD-93), pp. 543–547, 1993 and to W. Kunz, "An Efficient Tool for Logic Verification Based on Recursive Learning", in Proc. Intl. Conference on Computer-Aided Design (ICCAD-93), 538–543, November 1993 and, in addition, to A. Kühlmann and F. Krohm, "Equivalence Checking Using Cuts and Heaps", in Proc. Design Automation Conference (DAC-97), pp. 263–268, November 1997.
Methods for carrying out equivalence comparisons are used during circuit design. In this case, based on a first design (specification) which represents a desired circuit behaviour, this design is made specific by means of computer-assisted aids and by manual intervention by the designer in the corresponding circuit. In order to avoid faults from being introduced during this process, checks should be carried out during the synthesis of the circuit to determine whether the implementation at that time has the same behaviour as the specification at the higher level. It is therefore necessary during the equivalence comparison to determine the internal equivalence points or cut points between the design at the higher level and the circuit at that time.
This procedure has been found to be problematic in the case of circuit parts which relate to multiplication. The implementation is produced (after application of the relevant synthesis tools and possible manual actions) at gate level. In order now to allow the specification, which is at the register transfer level, to be compared with the implementation, it must be converted by the equivalence checker to a description at the gate level. In this case, it has been found to be problematic that the circuit derived from the design at the register transfer level has very major differences at the gate level in comparison with the design at gate level derived by means of the synthesis tools. This is essentially because different multiplication architectures are usual and there are a large number of implementation options for each individual architecture, so that in practice there are no equivalence points between the two circuits to be compared.
Methods which are based on decision diagrams at word level are known for equivalence comparison of arithmetic circuits. In this context, reference should be made, for example, to Bryant (TCAD85), Chen (ASP-DAC01). Since, however, the implementation is generally produced as a gate level description and there is too little information from the word level, the generation of these decision diagrams at word level is in practice often extremely complex in terms of computation and memory space.
Multipliers may be represented as a combination of two function blocks. In the first function block, the partial products of the multiplicand and the (binary) digits of the multiplier are formed. The partial products are designed to be dependent on whether the numbers to be multiplied may or may not have a negative mathematical sign, and also to be dependent on whether Booth recoding is used.

Method and apparatus for verification of digital arithmetic circuits by means of an equivalence comparison


An optical sensor circuit comprises an optical sensor adapted to sense a position of a component in a semiconductor manufacturing apparatus according to the presence or absence of a flag and output a signal indicative of the position. A position sensing driver receives the signal via a path selected by a plurality of switches and then drives an output signal in response to the signal. The path selected by the plurality of switches causes the optical sensor circuit to act as either a close-type optical sensor circuit or an open-type optical sensor circuit.

1. Field of the Invention
The present invention relates generally to an optical sensor circuit for a semiconductor manufacturing device. More particularly, the invention relates to an optical sensor circuit that combines the functions of both "open-type" and "close-type" optical sensor circuits into a single optical sensor circuit.
A claim of priority is made to Korean Patent Application No. 10-2004-0110967 filed Dec. 23, 2004, the disclosure of which is hereby incorporated by reference in its entirety.
2. Discussion of Related Art
Optical sensors are commonly used to detect the positions and/or orientations of various components within a piece of semiconductor manufacturing equipment. For instance, optical sensors may be used to detect whether a printed circuit board is properly positioned or whether parts of the equipment such as doors, valves, and so forth, are properly positioned (e.g., open, closed, tilted, rotated, etc.). The optical sensors are generally coupled to or associated with actuators such as pivot motors, door motors, and air springs, which are used to adjust the positions and/or orientations of the various components.
An ion-implantation apparatus is one type of equipment that uses optical sensors. In an ion implantation apparatus, components such as isolation valves, faradays, and load lock chambers, are monitored by optical sensors. For example, the optical sensors may detect whether the load lock chambers or the or the isolation valves are properly opened or closed. In addition, the optical sensors may be used to determine whether an ion source or a substrate is in a proper position for ion-implantation to take place.
In a "close-type" optical sensor circuit, when an obstruction, or "flag", prevents a light emitting diode (LED) from transmitting light to a light receiving transistor, the optical sensor circuit outputs a signal with a logic state "low" (i.e., a "low signal"). In contrast, in an "open-type" optical sensor circuit, when a flag prevents the LED from transmitting light to the light receiving transistor, the optical sensor circuit outputs a signal with a logic state "high" (i.e., a "high signal").
FIG. 1 is a circuit diagram of a conventional "close-type" optical sensor circuit and FIG. 2 is a circuit diagram of a conventional "open-type" optical sensor circuit.
Referring to FIG. 1, the conventional close-type optical sensor circuit comprises an optical sensor 10, a position sensing driver 12, and a LED "LED1". The close-type optical sensor circuit further comprises a first resistor R1 and a second resistor R2 connected to optical sensor 10.
Optical sensor 10 comprises a LED D1 and a light receiving transistor TR1 that is turned on in response to light emitted from LED D1. A flag "FLAG" is inserted or input between LED D1 and light receiving transistor TR1 to prevent the light emitted from LED D1 from turning on light receiving transistor TR1.
Position sensing driver 12 comprises a transistor 12 having a base connected to an emitter of light receiving transistor TR1, a collector connected to an output of LED "LED1", and an emitter connected to an output of the close-type optical sensor circuit.
The operation of the close-type optical sensor circuit is as follows. Where flag "FLAG" is not interposed between LED D1 and light receiving transistor T1, the emitter of light receiving transistor T1 assumes logic state "high", causing transistor Q1 to turn on. Accordingly, current flows through LED "LED1", causing it to turn on, and as a result, the emitter of transistor Q1 assumes logic state "high". In contrast, where flag "FLAG" is interposed between LED D1 and light receiving transistor T1, the emitter of light receiving transistor T1 assumes logic state "low", causing transistor Q1 to turn off. Accordingly, no current flows through LED "LED1", and as a result, the emitter of transistor Q1 assumes logic state "low".
The operation of the close-type optical sensor circuit is illustrated by Table 1 below.
TABLE 1FLAG POSITIONTR1Q1LED1Q1 EMITTERFLAG INOFFOFFOFFLOWFLAG OUTONONONHIGH
Referring now to FIG. 2, the open-type optical sensor circuit comprises an optical sensor 20, a position sensing driver 22, a LED "LED2", and first and second resistors R1 and R12. Optical sensor 20 comprises a LED "D2" and a light receiving transistor TR2 that is turned on in response to light emitted by LED D2. A flag "FLAG" is inserted or input between LED D2 and light receiving transistor TR2 to prevent the light emitted from LED D2 from turning on light receiving transistor TR2. Position sensing driver 22 comprises a transistor Q2 having a base connected to a collector of light receiving transistor TR2, a collector connected to an output of LED "LED2", and an emitter connected to an output of the open-type optical sensor.
The operation of the open-type optical sensor circuit is as follows. Where flag "FLAG" is not interposed between LED D2 and light receiving transistor T2, the collector of light receiving transistor T2 assumes logic state "low", causing transistor Q2 to turn off. Accordingly, no current flows through LED "LED2", and as a result, the emitter of transistor Q2 assumes logic state "low". In contrast, where flag "FLAG" is interposed between LED D2 and light receiving transistor T2, the collector of light receiving transistor T2 assumes logic state "high", causing transistor Q1 to turn on. Accordingly, current flows through LED "LED2", thus turning it on, and as a result, the emitter of transistor Q2 assumes logic state "high".
The operation of the close-type optical sensor circuit is illustrated by Table 2 below.
TABLE 2FLAG POSITIONTR2Q2LED2Q2 EMITTERFLAG INOFFONONHIGHFLAG OUTONOFFOFFLOW
In the description above, the close-type optical sensor circuit outputs a high signal when no flag is input to optical sensor 10, and the open-type optical sensor circuit outputs a low signal when no flag is input to optical sensor 20. Conversely, where a flag is input to optical sensor 10, the close-type optical sensor circuit outputs a low signal and where a flag is input to optical sensor 20, the open-type optical sensor circuit outputs a high signal.
The output of the closed or open type optical sensor generally provides an indication of the state of some component in a semiconductor manufacturing device. For example, the output may represent whether a door in the device is open or closed. The optical sensor typically detects the state of the component by the presence or absence of the flag.
The optical sensor circuits described above are commonly employed in semiconductor manufacturing equipment. For example, in a semiconductor manufacturing apparatus comprising a processing chamber and a plurality of load lock chambers connected to the process chamber, optical sensor circuits may be used to determine whether the load-lock chambers are properly closed or whether an air bearing in the processing chamber is properly oriented.
Where a close-type or open-type optical sensor circuit is used in the load lock chambers of a semiconductor manufacturing apparatus, malfunctions in one optical sensor circuit can be addressed without interrupting semiconductor manufacturing processes in the processing chamber. This can be accomplished, for example, by removing the malfunctioning optical sensor circuit from its respective load lock chamber and using a different load lock chamber to perform process steps. However, where a close-type or open-type optical sensor circuit is used in the processing chamber, malfunctions in the optical sensor circuit cannot be addressed without interrupting semiconductor manufacturing processes performed therein.

Optical sensor circuit combining functions of open and close type optical sensor circuits


Non-linear model with disturbance rejection. A method for training a non linear model for predicting an output parameter of a system is disclosed that operates in an environment having associated therewith slow varying and unmeasurable disturbances. An input layer is provided having a plurality of inputs and an output layer is provided having at least one output for providing the output parameter. A data set of historical data taken over a time line at periodic intervals is generated for use in training the model. The model is operable to map the input layer through a stored representation to the output layer. Training of the model involves training the stored representation on the historical data set to provide rejection of the disturbances in the stored representation.

Non-linear models have long been used for the purpose of predicting the operation of a plant or system. Empirical nonlinear models are trained on a historical data set that is collected over long periods of time during the operation of the plant or system. This historical data set only covers a limited portion of the "input space" of the plant, i.e., only that associated with data that is collected within the operating range of the plant when the data was sampled. The plant or system typically has a set of manipulatable variables (MV) that can be controlled by the operator. There are also some variables that are referred to as "disturbance variables" (DV) which are variables that cannot be changed by the operator, such as temperature, humidity, fuel composition, etc. Although these DVs have an affect on the operation of the plant or system, they cannot be controlled and some can not be measured. The plant will typically have one or more outputs that are a function of the various inputs, the manipulatable variables and the disturbance variables. These outputs are sometimes referred to as "controlled variables" (CVs). If the historical data set constitutes a collection of the measured output values of the plant/system and the associated input values thereto, a non-linear network can be trained on this data set to provide a training model that can predict the output based upon the inputs. One type of such non-linear model is a neural network that is comprised of an input layer and an output layer with a hidden layer disposed there between, which hidden layer stores a representation of the plant or system, wherein the input layer is mapped to the output layer through the stored representation in the hidden layer. Another is a support vector machine (SVM). These are conventional networks. However, since the unmeasurable disturbances cannot be measured, the model can not be trained on these variables as a discrete input thereto; rather, the data itself embodies these errors.
One application of a non-linear model is that associated with a control system for controlling a power plant to optimize the operation thereof in view of desired output variables. One output variable that is of major concern in present day power plants is nitrogen oxide (NOx). Nitrogen oxides lead to ozone formation in the lower atmosphere which is a measurable component of urban photochemical smog, acid rain, and human health problems such as lung damage and people with lung disease. NOx levels are subject to strict guidelines for the NOx emissions throughout the various industrialized areas of the country. For example, the current U.S. administration has proposed legislation to reduce NOx emissions from power plants by 50% over the next decade.
These Nitrogen oxides are formed during combustion and emitted into the atmosphere as a component of the exit flue gas. The level of NOx formation is dependent upon the local fuel/air stochiometric ratio in the furnace of a coal fired plant, as well as the amount of nitrogen in the fuel. A fuel rich environment (high fuel/air stochiometric ratio) leads to low NOx formation but high carbon monoxide (CO) amounts, another regulated gas. Therefore, an optimal fuel/air ratio needs to be determined to minimize NOx while maintaining CO below a specified constraint. In a coal fired plant, both fuel and air are input into the furnace at multiple points. Furthermore, a non-linear relationship between fuel and air inputs and NOx formation has been observed, such that optimization of the NOx levels, while observing the CO constraint, requires a non-linear, multiple input, multiple output (MIMO) controller. These optimizers typically utilize a nonlinear neural network model, such as one that models NOx formation, such that prediction of future set points for the purpose of optimizing the operation of the plant or system is facilitated given a cost function, constraints, etc.
As noted herein above, to develop accurate models for NOx, it is necessary to collect actual operating data from the power plant over the feasible range of operation. Since plants typically operate in a rather narrow range, historical data does not provide a rich data set over a large portion of the input space of the power plant for developing empirical models. To obtain a valid data set, it is necessary to perform a series of tests at the plan. Each test involves initially moving approximately five to ten inputs of the furnace to a designated set point. This set point is then held for 30–60 minutes until the process has obtained a stable steady state value. This is due to the fact that the desired nonlinear model is a steady state model. At that time, the NOx and input set points are recorded, this forming a single input-output pattern in the historical data set. It may take two engineers three to four weeks of round-the-clock testing to collect roughly 200–400 data points needed to build a model.
The training of the model utilizes a standard feed-forward neural network using a steepest descent approach. Since only data from steady state data points are used, the model is an approximation of the steady state mapping from the input to the output. Utilizing a standard back propagation approach, the accuracy of the model is affected by the level of the unmeasured disturbance inherent to any process. Because the major source of nitrogen for the formation of NOx in a combustion process at coal fired plants is the fuel, variations in the amount of nitrogen in the coal can cause slow variations in the amount of NOx emissions. Furthermore, most power plants do not have on-line coal analysis instruments needed to measure the nitrogen content of the coal. Thus, the variation of nitrogen content along with other constituents introduces a significant, long-term, unmeasured disturbance into the process that affects the formation of NOx.


A display device includes a plurality of pixel areas and a thin film transistor disposed on a substrate. A first light blocking member is disposed on the thin film transistor, and a contact hole is disposed in the first light blocking member to expose a portion of the thin film transistor. A pixel electrode is disposed on the first light blocking member, and connected with the thin film transistor through the contact hole. A second light blocking member is disposed on the pixel electrode overlapping with the contact hole. A roof layer is disposed spaced apart from the pixel electrode with a microcavity interposed therebetween. An injection hole is disposed below the roof layer to expose a portion of the microcavity, and a liquid crystal layer is disposed in the microcavity. An encapsulation layer is disposed on the roof layer covering the injection hole so as to seal the microcavity.

(a) Technical Field
The present disclosure relates to a display device and a method of manufacturing the display device. More particularly, the present disclosure relates to a display device having a structure that improves the flow of an aligning agent and a liquid crystal material into a microcavity of the display device.
(b) Description of the Related Art
A liquid crystal display is commonly used in flat panel displays. The liquid crystal display typically includes two display panels on which field generating electrodes (such as a pixel electrode and a common electrode) are formed and a liquid crystal layer interposed therebetween. When a voltage is applied to the field generating electrodes, an electric field is generated in the liquid crystal layer. The electric field determines the alignment of liquid crystal molecules in the liquid crystal layer and controls polarization of incident light, thereby allowing images to be displayed on the display panels.
The two display panels in the liquid crystal display may include a thin film transistor array panel and an opposing display panel. The thin film transistor array panel may include a gate line (for transferring a gate signal) and a data line (for transferring a data signal) formed crossing each other, a thin film transistor connected with the gate line and the data line, and a pixel electrode connected with the thin film transistor. The opposing display panel may include a light blocking member, a color filter, and a common electrode. In some cases, the light blocking member, the color filter, and the common electrode may be formed on the thin film transistor array panel.
In a conventional liquid crystal display device, the two display panels are typically formed on two separate substrates. For example, a first substrate is used for the thin film transistor array panel, and a second substrate is used for the opposing display panel. However, using two separate substrates for the display panels may increase the weight and form factor of the liquid crystal display device, as well as process costs and turn-around time.
In some liquid crystal display devices, the two display panels may be integrated onto a single substrate. In those liquid crystal display devices, a light blocking member may be disposed near an injection hole to a microcavity of the display device. When the light blocking member and the injection hole have substantially the same height, flow of an aligning agent and liquid crystal material into the microcavity may be obstructed by the light blocking member, which may lead to an increase in filling time or incomplete filling of the microcavity.

Display device and manufacturing method thereof


A phase synchronization circuit comprises: a measurement delay line which includes a plurality of delay elements having different delay times and to which a first clock signal is inputted; a phase comparator line which includes a plurality of phase comparators in accordance with the measurement delay line and to which a signal from the measurement delay line and a second clock signal are inputted so as to measure a transition timing difference between the first clock signal and the second clock signal; and a generation delay line which includes a plurality of delay elements having different delay times in accordance with the measurement delay line and to which a signal from the phase comparator line and a third clock signal are inputted. The delay time of the respective delay elements is fixed.

In general, in semiconductor integrated circuit devices, signals inside and outside a semiconductor chip should be synchronized in time in order to accurately transmit/receive the signals inside and outside the semiconductor chip. In such synchronization, usually, an internal clock (or internal strobe) signal whose transition timing is accurately controlled is generated in order to maintain a constant timing relationship with transition timing of a clock (or strobe) signal inputted from the outside of the semiconductor chip, and the internal clock signal is utilized for acquiring a data signal.
An object, of the phase synchronization circuit mentioned above is to adjust the timing at the transmission/reception of the signals inside and outside the chip to minimize an undesired influence such as miss-acquisition of data value. In general, as to the time until phases are synchronized, it is desired that the phase synchronization is completed in a shorter time.
Meanwhile, for the purpose of reducing the semiconductor chip cost, it is preferable that the circuit is realized with the smallest possible occupying area on the chip or with the smallest possible number of elements and gates.
When applications to mobile devices or utilization of low-cost package are considered, it is desirable that the circuit is operated by lower electric power (electric power at the time of operation and standby).
As a technology relating to such a phase synchronization circuit, for example, the following technologies are disclosed.
In "IEEE Journal of Solid-State Circuits" (U.S.), November 1996, vol. 31, No. 11, pp. 1656-1668 (Non-Patent Document 1), two delay lines FDA and BDA are arranged in parallel in opposite directions, a control circuit MCC is arranged therebetween in parallel with them, and a load circuit having the same delay time as that of a clock driver connected to an output of the delay line BDA is designed as a dummy in advance so as to connect with an input of the delay line FDA. This circuit detects a position where phases are synchronized in the delay line FDA based on the delay line FDA and the control circuit MCC, and inputs a clock from the same position in the delay line BDA to transmit the clock in a direction opposite to the delay line FDA. As a result, high-speed synchronization where phases are synchronized in the delay of two cycles is realized.
Japanese Patent Application Laid-Open Publication No. 2002-152018 (Patent Document 1) discloses an example where a variable delay element and a fixed delay element are combined to form a synchronization circuit with a small number of delay tiers. The variable delay element controls a power source voltage so as to change its delay time.
In both Non-Patent Document 1 and Patent Document 1, the delay time created in the synchronization circuit is controlled so that transition (rise or fall) timings of signals of inside and outside are aligned only at a timing equal to a clock cycle of a reference signal given as an input or a timing which is integral multiple of the clock cycle.

Phase synchronization circuit and semiconductor integrated circuit


A system for converting an image into a hologram formed from diffraction gratings includes obtaining image data for each pixel in an image to be converted, putting it into digital form and using the image data to control portions of a laser beam split into a reference beam and at least one object beam. The diffraction gratings are formed by an interference pattern of a reference beam and at least one object beam intersecting on the surface of a photoresist material on a pixel-by-pixel basis. Modulation of at least one object beam and adjustment of the angle at which that beam interferes with the reference beam on the photoresist material is used to reflect image data for each pixel of the image being converted into a hologram consisting of diffraction gratings. By using this technique and selecting the spacings between pixel pairs on the photosensitive surface, the angle at which a viewer will see a predetermined image or reflecting light from the hologram is determined, as well as the apparent position of the image created by reflecting light from the hologram constituted by the spaced diffraction gratings.

The present invention relates generally to the manufacture of holographic substrates or holograms, and more particularly to the manufacture of holograms of images by manipulating laser beams to reflect image data.
Holograms composed of gratings formed by light interference patterns generated using coherent monochromatic light from the laser are used in a variety of applications. One such application is the provision of holograms as identity or security devices on credit cards. In order to provide holograms on large numbers of credit cards, it is necessary that a master copy of the hologram be made so that multiple copies can be duplicated in a process similar to that of xe2x80x9cstamping outxe2x80x9d records. One example of a procedure for the conversion of a photograph into a hologram is found in U.S. Pat. No. 3,832,027. This patent includes a disclosure describing a procedure in which a two-dimensional photograph is converted into a hologram by means of computer data processing. Multiple views of the photograph are aggregated to provide the ultimate view which image upon which the holographic gratings constituting the hologram are formed.
Additional background regarding the manufacture of holograms is found in an article entitled xe2x80x9cDiffraction Gratingsxe2x80x9d published at page E-29 of the 1984 edition of the xe2x80x9cOptical Industry and Systems Purchasing Directoryxe2x80x9d. This publication describes the manufacture of holographic gratings by the interference of two beams of coherent monochromatic light altering a photosensitive material which is used as the master for turning out copies of the hologram. The interference fringes of the two light beams are formed where the two coherent light beams come together to cancel or reinforce the peaks and valleys of each of the beams. These interference fringes result in a physical altering of the photosensitive material so that a series of grooves are formed. The ultimate image formed by reflecting light from the holographic gratings is determined by the spacing of those gratings.
Another method for making a chromatic holographic image is found in U.S. Pat. No. 4,498,729. The method includes the steps of making a monochromatic hologram on a first photographic plate, then making a diffraction grating by exposing a second photographic plate to a series of co-linear point sources of mutually coherent monochromatic light. Then the exposed plate is developed and bleached to produce the diffraction grating. A second hologram is made by exposing a third photographic plate to an image from a narrow elongated strip of the first hologram with the diffraction grating in the optical path. The achromatical ray is made by holographically recording the image produced by eliminating the second hologram with monochromatic light on a fourth photographic plate.
Because of the complexity of handling multiple overlapping images computer aided holography such as that disclosed in U.S. Pat. No. 4,778,262 has been required in the conventional art for precise holography. In this patent, an illumination model is provided to specify sources of light rays and dispersion particles of the object. Each light ray being specified by a path and an intensity function is traceable from a source via the object to a set of points and space by the computer. The hologram is synthesized from a plurality of smaller hologram elements. Each individual element sustains a field of view of the object. The light rays from the object line within the field of view and along the lines of sight are sampled by the computer. Optical means are employed to physically reproduce the sample light rays using coherent radiation. The reproduced coherent light rays are then interfered with a coherent reference beam to form the hologram element. In the alternative, the hologram elements are calculated using a computer. Using this technique, the holographic surface is logically partitioned into a grid within the computer, where the contribution of light from the object to each grid element is envisioned as a bundle of light rays emanating from each part of the object and converging onto each grid element. The intensity of each ray of light arriving at a given grid element is determined by the computer by tracing the light ray from its source to the associate part of the object and then onto the grid element in accordance with the given illumination model. Thus, a xe2x80x9ctreexe2x80x9d of light rays, each in terms of direction and intensity is generated for each grid element. Since the illumination model can be manipulated on the computer, the rendering of the object can easily be modified. This enables complicated lighting of the object not readily practical by physical means. The entire hologram is synthesized by forming, in turn, the hologram element at each grid element on the holographic surface. This is done by either reproducing the associated xe2x80x9ctreexe2x80x9d of light rays associated with a predetermined grid using coherent radiation and made to interfere with a coherent reference beam, or simulating the same on the computer.
Multiple exposures of images is a necessary expedient in the conventional art. As indicated in U.S. Pat. No. 3,615,123, a holographic system for recording multiple-exposure holograms requires the use of a pulsed laser. Using this technique, each repetitive reference beam is deflected so that it reaches the recording material at a plurality of discrete different angles. Each of the multiple-exposure recordings of the hologram may be produced by a reference beam having the same angle as that at which it was taken. A reference beam may, for example, be deflected by utilizing an electro-optical retarder followed by a birefringent crystal for deflecting the beam in accordance with its direction of polarization. The paths of the reference beams for each discrete angle may be equalized by the provision of a plurality of reflectors disposed along in ellipse having the recording material in a first reflector as its focal points.
In order to distinguish and phase and amplitude differences, the system of U.S. Pat. No. 4,212,536 used a technique of holographic subtraction with phase modulation. In this technique, two substantially identically patterned transparencies, i.e., a master photo mask and a copy thereof are compared with each other by transluminating the master with an object beam, producing a hologram of that master by letting the object beam interfere with a reference beam from a common source of coherent light such as a laser. The copy is placed in the path of the object beam formerly occupied by the master and the developed hologram is positioned at the intersection of the two beams to generate a compound beam of zero intensity if the two transparencies are identical. The luminous energy of the compound beam thus varies inversely with the degree of equivalency of the two transparencies. The compound beam may be imaged onto a receiving surface with certain areas thereof blocked out to eliminate error indications from marginal zones.
The conventional technology also encompasses the use of holograms for information storage. In U.S. Pat. No. 4,111,519, a bite of binary of data to be stored is recorded as a synthetic Fourier transformed hologram of the bite of data. A time varying control signal representing the synthetic hologram is used to intensity modulate a coherent light beam as the beam scans transversely across a photosensitive recording film. The amplitudes of different spatial frequencies in the data band are differently altered to compensate for signal-to-noise roll-off over the data band. The thus compensated signals are also modified to compensate for non-linear gain characteristics. The thus modified signals are also processed to provide the modulating control signal. During the read-out process, an inverse Fourier transformation is performed optically on the light diffracted by the synthetic hologram in order to produce the original bite of data in the form of an optical intensity pattern. This pattern is transversely distributed on an array of photosensitive detectors which converts the optical intensity pattern to an electrical data signal. During this read-out process, a tapered neutral density filter, i.e., a wedge filter, is employed in front of the photosensitive detectors to provide attenuation or gain across a spatial frequency bandwidth to compensate for system modulation transfer function.
Data along the Z axis is also encompassed by the conventional art as indicated by U.S. Pat. No. 4,498,740. In this system, a hologram is written from X, Y and Z data by representing an information beam at a holographic medium with X and Y coordinates represented by X and Y position on the medium and Z coordinates represented by distance between the holographic medium and a point position of the beam close to the medium, while simultaneously presenting a reference beam in interference with the information beam. The size of the reference beam is comparable to the size of the information beam at the holographic medium. In this system, the area of the information beam and the reference beam at any position on the holographic medium is a small fraction of the total area of the hologram.
Conventional art techniques are able to transfer only limited amounts of image information (or other data) into the control of the process for forming diffraction gratings. Consequently, there are severe limitations as to the clarity and accuracy of the images that can be produced from conventionally made holograms.
One object of the present invention is to provide an accurate pixel-by-pixel representation of a copied image on a hologram constituted by diffraction gratings.
Another object of the present invention is to provide a system for quickly and accurately conveying image information on a pixel-by-pixel basis to a holographic grating.
Yet another object of the present invention is to provide a system for making holograms in which the image is adjusted based upon the angle of a viewer with respect to the hologram.
Still a further object of the present invention is to provide a system in which the apparent position of an image for a viewer in a predetermined position is based upon pixel playback angle.
These objects are accomplished according to the present invention in which positional data (using an X-Y coordinates system) and image data for each pixel of a plurality of pixels representing an image is obtained, stored, and used to control an apparatus for making a hologram composed of diffraction gratings. The apparatus is controlled so that a laser beam is split into a reference beam and at least one object beam used to represent image data for a corresponding pixel. The reference beam and other beam(s) are recombined at a photoresist material to form an interference pattern. The angle of the object beam(s) with respect to the photoresist surface and the duration of the object beam(s) interfering with the reference beam are used to convey data regarding the corresponding pixel. Additional pixel data can be conveyed by multiple exposures of the single object beam (with the reference beam) or by exposures of a plurality of object beams for each pixel. A movable table is used to move the photoresist from one pixel location to another in accordance with the X-Y coordinate system by which the pixel locations of the original image were determined.
Data in the Z-axis direction including the apparent position of an image reflected from the hologram can be adjusted by adjusting the playback angle of xe2x80x9csteroscopicxe2x80x9d pixel pairs when forming the diffraction gratings constituting the pixels.

System for making a hologram of an image by manipulating object beam characteristics to reflect image data


An indwelling needle is provided with an inner needle hub; an inner needle fixedly supported by the inner needle hub; a cover configured to cover the inner needle after use; and a flexible blood monitor being absorptive to blood, an end of which is linked with the inner needle hub.

1. Field of the Invention
The present invention relates to an indwelling needle for an infusion set, which has a down-sized constitution and is capable of regulating the amount of a blood back-flow.
2. Description of the Related Art
Indwelling needles are used to infuse various medicinal fluids into vascular systems. In some case, an indwelling needle is provided with an inner needle for being stuck into a vascular system and an outer needle coaxially fit on the inner needle. After sticking, the inner needle may be extracted but the outer needle is left inserted and used for infusion.
Japanese Patent Application Laid-open JP2002-102347 discloses an art of an indwelling needle assembly provided with a needle cover and blood monitoring means. The needle cover is configured to cover the inner needle and the blood monitoring means and hence assures safe disposal thereof without accidental sticking after use. The blood monitoring means is movably housed in the needle cover and provided with a chamber for receiving back-flow of blood. When the inner needle is inserted in the vascular system, an operator can observe the back-flow of the blood pooled in the chamber from the exterior so as to verify the inner needle is regularly inserted in the vascular system.


An interconnection element for a multi-phase winding (11) that is made up of coils (12) and belongs to an electric machine, in particular a brushless mini motor, having a support (20) made of insulating material and conducting strips that are disposed on the support (20) for producing interconnections among the coils (12). In order to reduce materials costs, the conducting strips are embodied in the form of bent wires (27-30) that are preferably contained in channels embodied in the support (20) and are fixed in place by means of two annular cover elements (31, 32) made of insulating material.

The invention is based on an interconnection element for a multiphase winding that is comprised of coils and is part of an electrical machine, in particular a brushless mini motor.
In a known interconnection element of this type (EP 1 062 720 B1), the support made of insulating material is embodied in the form of a supporting plate, which, together with a stator body that is embodied in the form of a lamination bundle and supports the winding, is fastened by means of a hub to a bearing support tube that is in turn attached to a motor flange. The electrical conducting strips for producing interconnections among the coils are embodied as conductor rails that are manufactured as stamped parts and are fastened to the supporting plate, concentric to the hub. A first conductor rail, which has tabs extending at angles in relation to the conductor rail to form a star point, is connected to the coil ends of all of the winding phases. Three other conductor rails are attached to the supporting plate, arranged concentrically around the first conductor rail, their tabs arrayed for connection to the coil beginnings. In order to avoid crossing points between the concentric rails and the tabs protruding from them, the tabs of the second conductor rail are routed under the third conductor rail and the fourth conductor rail by means of sunken guides in the supporting plate and the tabs of the third conductor rail are also routed under the fourth conductor rail by means of sunken guides. When manufacturing the conductor rails that are comprised of stamped material, in order to keep waste within limits, the first and third conductor rails are manufactured in a first stamping die and the second and fourth conductor rails are manufactured in a second stamping die, each in its own stamping procedure, the second, third, and fourth conductor rails each being provided with a connecting tab for litz-connections.

Connecting element for a winding of an electric machine