The invention relates to a method for determining the reactive state of a chemical reaction process in a reaction mixture (110), in particular an amplification reaction for nucleic acids. The method comprises a viscosity determination, which preferably uses a dynamic viscometer (1). The invention also relates to an improved dynamic viscometer (1) for carrying out said method. The viscometer is characterised by an appropriate choice of material for the resonator (101) and optimised geometric ratios.

It is usually desired in chemical reactions to quantify the result of the reaction by measuring suitable variables or to follow the progress of the reaction by means of such a variable. A well-known example is following the changes in color of a colored indicator which has been added to a reaction mixture.
In a process for amplifying nucleic acids, in contrast to usual chemical reactions, a precursor is not converted into a completely different product, but one part of a molecule is copied with the aid of other precursors. In the specific case of methods for amplifying nucleic acids, especially the polymerase chain reaction (PCR), the result of the reaction is nowadays frequently quantified by staining with ethidium bromide and detecting the fluorescent signal. It has also been proposed to detect the hybridization process itself by fluorescence. Such a method is disclosed in U.S. Pat. No. 6,174,670. The detected fluorescent signal results from a fluorescence resonance energy transfer (FRET) between two fluorophores on excitation of the donor fluorophore with light. The DNA can be genotyped by analyzing specific melting and solidification curves.
Monitoring the progress of a reaction by fluorescence is relatively complicated, because a sensitive optical system must be provided for detection. In addition, such a method is costly to use because of the fluorescence markers necessary therefor.
It is also known to examine the progress of viscosity-altering reactions, e.g. polymerization reactions, by means of viscometry. A reaction is viscosity-altering if the viscosity of the product of the mixture of the products differs from the viscosity of the mixture of the precursors. The viscosity of the mixture will then approach the viscosity of the products as the reaction increasingly advances. Measurement of viscosity then provides a measure of the advancing of the reaction. The viscometers employed for this purpose are, however, ordinarily optimized for industrial production plants and unsuitable for examining small reaction volumes.

Chemical analysis using dynamic viscometry


A portable filter assembly for providing filtered air to an enclosed space includes a housing having an exhaust port connected to the enclosed space, an internal air intake port connected to the enclosed space, and an external air intake port connected to the outside of the enclosed space. A fan provides a partial vacuum to the internal and external air intake ports. A filter is located in the housing and the assembly is arranged such that the assembly simultaneously filters re-circulated air from the enclosed space through the internal air intake port and filters external air from the outside of the enclosed space through the external air intake port and filters the air to the enclosed space through the exhaust port.

Due to the growing concerns regarding potential biological or chemical terrorist attacks, a need exists in the state of the art for an inexpensive and simple-to-use filter which could effectively remove dangerous contaminated particles from the air within an enclosed space, such as a room in a home, a school class room, an office, and a vehicle, for example, while simultaneously providing a positive pressure within the enclosed space sufficient to prevent migration of the contaminated particles through small cracks or openings that may be present between the enclosed space and outside of the space.
Duct tape and plastic sheeting covering doors and windows provide some protection from airborne contaminants; however, such measures will not provide an airtight seal for particles as small as about 1.0 micron in diameter (about the size of an anthrax spore, for example)). Thus, creating a positive pressure within the enclosed space, in accordance with the present invention, minimizes the introduction of such contaminants into the enclosed space.


There are provided a plurality of etalon filters arranged in concatenation, a light output portion for outputting a light to the etalon filters, and a light input portion to which a light transmitting the etalon filters is inputted, and the plurality of etalon filters have mutually different free spectrum regions. A plurality of etalon plates applied with semipermeable films to both surfaces of a thin glass plate and having mutually different periods and amplitudes are cascade-connected. By combining a plurality of etalon films having different characteristics with one another, it is possible to realize an optical equalizer having low loss polarized light dependency and capable of compensating optional gain wavelength dependency. By using such an optical equalizer as a repeater by combining the optical equalizer with an optical amplifier, a level difference caused by the difference of the gain among wavelengths of optical signals is neither produced in a wavelength multiple optical transmission apparatus. It is possible to realize an optical equalizer for compensating gain wavelength dependency of an optical fiber amplifier, which compensates for optional gain wavelength dependency and has low loss polarized light dependency.

1. Field of the Invention
The present invention relates to an optical equalizer and an optical amplifier and a wavelength multiple optical transmission apparatus using the optical equalizer, and more particularly to an optical equalizer for flattening gain wavelength dependence characteristics of an optical amplifier and an optical amplifier to which the optical equalizer is applied.
2. Description of Related Art
There is an optical wavelength multiple transmission system as one of the techniques for realizing a large capacity of an optical communication system. This is a system that transmission is made after a plurality of optical signals having mutually different wavelengths are multiplexed on one line of optical fiber.
On the other hand, an optical fiber amplifier using a rare earth element doped optical fiber as an amplification medium which has been realized rapidly in recent years can amplify the signals having different wavelengths collectively. When this optical fiber amplifier is applied to an optical wavelength multiple transmission system, a large capacity long distance transmission system can be realized.
Now, the gain is generally different depending on the wavelength of an optical signal with respect to either an optical fiber amplifier and an optical semiconductor amplifier. Accordingly, when a plurality of wavelength multiplexed signal lights are amplified collectively, the optical output level of the optical amplifier is different depending on the wavelength. Moreover, when optical amplifiers are connected on multistages, the level difference of the optical output is accumulated.
When reception is made after wavelength branching on a receiver side, problems of stroke deterioration among respective wavelengths and in point of setting a light receiving level of a receiver are produced since the optical output level is different depending on the wavelength. Thus, an optical equalizer for compensating gain wavelength dependency of an optical amplifier becomes necessary.
There has been heretofore a method of inserting an equalizing optical filter for flattening the gain wavelength dependency into an optical fiber amplifier as one of the methods for compensating the gain wavelength dependency of an optical fiber amplifier. Such a technique is described in Japanese Patent Application No. Hei 01-177985 for instance. Further, as another method, there is a method of providing an optical fiber coupler such as described in Japanese Patent Application No. Hei 05-109975.
Further, as one of equalizing optical filters, a grating type (such as M. Tachibana, R. I. Laming, P. R. Morkel and D. N. Payne "Gain-shaped Erbium-doped fibre amplifier with broad spectral bandwidth", Technical Digest on Optical Amplifiers and their Applications, pp. 44-47, 1990) and a Mach-Zehnder type (such as disclosed in Japanese Patent Application No. Hei 2-270766) are proposed.
Furthermore, as an improved type of a Mach-Zehnder type optical equalizer, that in which Mach-Zehnder type optical filters having mutually different variation periods of loss depending on wavelength of wave-length dependency of transmittance are cascade-connected on multistages has been proposed (such as disclosed in Japanese Patent Application No. Hei 5-60047).
The above-mentioned conventional examples have drawbacks shown hereunder, respectively.
Namely, an optical fiber coupler is produced by fusing and stretching two lines of optical fibers, in which evanescent coupling among optical fibers is utilized. In this sort of coupler, when a variation period of wavelength dependency of the loss is shortened, it is required in point of principle to produce a fusion coupling portion long, and the manufacturing reproducibility of loss wavelength characteristics is lowered with the length of the fusion coupling portion.
In a band of wavelength 1,550 nm used in an optical fiber amplifier at present, when the gain to wavelength characteristics of an optical fiber amplifier is going to be compensated, it is required to shorten the period of a loss to wavelength characteristic curve of an optical fiber coupler to approximately 100 nm or lower, and it is attended with technical difficulties to manufacture such characteristics stably.
Generally, when the gain to wavelength characteristics of an optical amplifier is going to be compensated with an optical filter, the transmission wavelength characteristics of an optical filter have to be made double-humped in many cases. When characteritics of transmission wavelength including such a plurality of peaks are obtained, it becomes required to produce a wavelength interval between two transmission peaks and transmittance strictly with high reproducibility. In an example in which an interference filter by a multilayer dielectric film is used, it is very difficult to produce such double-humped transmission characteristics strictly and stably.
Further, in an example in which a grating (a fiber type grating or a grating provided on a glass substrate) is used, the wavelength dependency of the loss has a steep peak at a specific wavelength and has a large lag from the gain wavelength curve of the opticalamplifier. Therefore, when it is used for compensation of the gain wavelength dependency, there is such a drawback that a compensation error becomes larger in point of principle.
There is a Mach-Zehnder type optical filter as another conventional example. In this filter, a Mach-Zehnder type waveguide is formed on a quartz waveguide substrate, and a thermal optical effect is used for respective phase adjustments. In this Mach-Zehnder type optical filter, a refractive index change by the thermal optical effect is generated by adjusting the voltage applied to an electrode, thereby to change the phase so as to adjust the transmittance wavelength dependency in a wavelength direction. The Mach-Zehnder type optical filter is described in detail in Japanese Patent Application No. Hei 5-60047 for instance.
In the case of a Mach-Zehnder type optical filter, however, phase adjustment of a transmission light is made by generation of heat in an electrode provided on a waveguide. Therefore, there is such a drawback that a distortion inside the waveguide is liable to be generated, which generates polarization dependency of insertion loss.

Optical equalizer and optical amplifier and wavelength multiple optical transmission apparatus using optical equalizer


Through selecting machines from groups of equipment, determine a line composition for producing a specific product so that a tact time of the line may not exceed an initial set tact time. Give a priority order to the machines based on machines' features, thereby grouping the machines. Store information including the priority order within each group, the priority order between the groups, mounting tact time of the loadable parts, and the tact times proper to each machine into an external storage 1 as control information 2. Supplement the machines according to the priority order to the line composition from the equipment until all the parts are loaded, and calculate the tact time of the line with a CPU 3. Supplement the machines successively from the groups of equipment until the line tact time becomes not more than the initial set tact time. The line tact time is calculated with the CPU 3.

In a mounting process of electronic parts, an assembly line has been composed by utilizing individual feature of each mounting machine, and thereby manufacturing a PCB. For example, in a mounting process of micro-chip parts, a high-speed surface mounting machine mounts the parts, and when mounting QFP (quad flat package) and others having so narrow spacing between pathways of leads or pins that a precise mounting is required a robot type machine featuring precise mounting is employed after the process using the high-speed machine. Such an operation of combining different types of machines improves a quality of an efficiency of the entire assembly line. It is also a well-known operation method that a plurality of the same machines is placed in one assembly line in order to shorten a tact time of the assembly line. When determining compositions of these conventional assembly lines, a line manager has to do the following jobs manually.
1. Collect such data from the parts list for the specific PCB as numbers of parts, available machines for mounting the parts, individual tact time for mounting each part of each machine, maximum loadable numbers of parts into each machine.
2. Determine whether plural assembly lines are necessary for manufacturing this type of PCB, e.g. determine whether independent lines are necessary for insertion process, surface mounting process, and semiconductor mounting process. Then, assign each part to a line, and the following policy must be considered when a line composition is determined.
2-1. In general, assign a maximum loadable parts into a machine of the highest mounting speed among the group of machines. Surplus parts from the machine, or non-loadable parts into the machine are assigned to another machine of next higher mounting speed. The same procedure follows until all parts are assigned.
2-2. Reassign the parts within each line in order to smooth out the load to each machine so that a specific machine may not take an exceptionally longer tact time. For this purpose, an optimizing simulation using a computer are already available as a prior art.
2-3. After smoothing out, if the tact time of each line satisfies the desirable level, this line composition is finalized as an actual mounting line. If the tact time of each line could not satisfy the desirable level, a next possible machine is supplemented to the line composition so that the total tact time of the line may satisfy the desirable level. This procedure follows until the total tact time of the lines satisfies the desirable level.
The above procedure, however, leaves several problems to factory staff;
(1) This kind of manual procedure requires a great deal of time and labor for finalizing a desirable line composition, in particular, when planning an annual business plan, a common line composition must be finalized for plural types of PCBs. In this case, try & error calculations are repeated until every tact time of lines for each type of PCBs becomes not more than a desirable time. When any PCBs encounter some changes in a trial production, or due to specific changes, the same kind of calculation must be repeated.
(2) When a factory is equipped with sizable equipment, it is not an optimal operation for the entire factory if there is dispersion between each tact time of lines after finalizing the line compositions for plural types of PCBs. In this case, a line composition of each type of PCBs could not be finalized manually because calculations should be in too many numbers of combinations between sizable equipment and plural types of PCBs.
(3) Only specific line managers who know in detail about mounting conditions of equipment, e.g. each tact time of all equipment, can manage the above procedures and calculations, and ordinary workers cannot follow the procedure nor manage the calculations.

Matsushita Electric Industrial Co., Ltd.


A composition comprising (A) an organopolysiloxane having a unit of the formula: R.sup.1 SiO.sub.3/2 wherein R.sup.1 is methyl, phenyl or vinyl in its molecule and having at least 0.05 alkenyl groups each directly attached to a silicon atom per silicon atom, (B) an organohydrogenpolysiloxane having at least 2 hydrogen atoms each directly attached to a silicon atom per molecule, (C) a platinum catalyst, and (D) an organosilane or organopolysiloxane of the formula: R.sup.2.sub.a (R.sup.3 O).sub.b SiO.sub.(4-a-b)/2 wherein R.sup.2 and R.sup.3 are hydrogen, methyl, phenyl or vinyl maintains good light transmission in cured form when exposed to humidity and is thus suitable for forming cores of optical fibers. Similar benefits are obtained with a composition comprising components (A) and (B), (C') a platinum catalyst and/or a radical polymerization initiator, and (E) a carboxylate.

As is well known in the art, optical fibers include glass base optical fibers using quartz glass and multi component glass as core and clad components and plastic optical fibers using plastics as core and clad components. As compared with the former, the plastic optical fibers have some drawbacks including an increased transmission loss undesirable for long distance communications, but some advantages including an increase of numerical aperture, ease of handling, and low cost.
Conventional plastic optical fibers generally include cores formed of organic polymers having high light transmittance and clads formed of highly transparent organic polymers having a lower index of refraction than the core polymers. The organic polymers having high light transmittance suitable as the core are typically poly(methyl methacrylate), polystyrene, and polycarbonate. It was recently proposed to use organopolysiloxane elastomers as the core material as disclosed in Japanese Patent Application Kokai No. 43613/1985. Advantageously, plastic optical fibers using such elastomer cores have higher flexibility and higher thermal resistance than those using poly(methyl methacrylate) and other conventional core materials.
Nevertheless, the organopolysiloxane elastomers applied as the plastic optical fiber core have a drawback that light transmission loss is increased within a short period of time when exposed to high humidity conditions. It is thus desired to eliminate this drawback.

Optical fibers and core - forming compositions


In order to provide a hybrid drive system that suppresses a useless change of a pump driving path and that has a high durability, a plurality of drive sources, an output mechanism that outputs rotational power to an outside on the basis of those operation states, a control device that controls the operation states of the drive sources, an oil pump, and a pump input selecting mechanism that causes the oil pump to be driven with one of a plurality of rotary shafts to which power from the corresponding drive sources is inputable, are included, and the control device controls the rotation speeds (V1, V2) of the plurality of rotary shafts to unequal speeds by controlling the operation state of one of the plurality of drive sources.

A hybrid drive system including a plurality of drive sources is, for example, employed for a traveling drive system of a vehicle, and drives the vehicle by using rotational power from at least one of an internal combustion engine and an electric motor. In such a hybrid drive system, oil for lubrication of gears in an incorporated power split mechanism, and the like, cooling of a generator-motor, or the like, is pressurized and circulated by an oil pump.
As an existing hybrid drive system including an oil pump, there is, for example, the one in which, in order to make it possible to supply oil even during EV (electric vehicle) running, an input shaft of a power split mechanism to which power from an engine is input and an output shaft of the power split mechanism that outputs power from at least one of the engine and a motor to a traveling drive system are respectively coupled to the oil pump via one-way clutches such that power is inputable, and the oil pump is driven by one of both shafts, having a higher rotation speed (see Patent Documents 1, 2).


The present invention relates to stable novel salt forms of N-(cyanomethyl)-4-(2-(4-morpholinophenylamino)pyrimidin-4-yl)benzamide that are suitable for the preparation of pharmaceutical formulations thereof, and their therapeutic use.

The inhibition to Janus kinase (JAK) has been evaluated in treating hyperproliferative diseases. Several JAK inhibitors have been developed: ruxolitinib, tofacitinib, baricitinib, lestaurtinib, pacritinib, fedratinib, XL019, SB1518 and AZD1480 have been developed (Sonbol, Ther. Adv. Hematol. 4: 15-35, 2013). The compound N-(cyanomethyl)-4-(2-(4-morpholinophenylamino)pyrimidin-4-yl)benzamide (CYT-0387) is a JAK kinase inhibitor
In clinical studies, CYT-0387 is effective in treating hyperproliferative diseases such as polycythemia vera (PV), essential thrombocythemia (ET), and primary myelofibrosis (PMF). Also, the patients having myelofibrosis who received CYT-0387 exhibited the improvement in the anemia and/or spleen responses (see U.S. Pat. No. 8,486,941 and Application Publication No. 2014-0073643, each of which is incorporated herein by reference in its entirety).
It is desired to have different forms of the compound that are suitable for the preparation of pharmaceutical formulations containing CYT-0387 and their therapeutic use.


An optical system has an illumination optical assembly, a detection optical assembly, a wavefront shaping device, and a controller. The illumination optical assembly focuses interrogating optical radiation to a focal point on or in a sample. The interrogating optical radiation propagates to the focal point along a first optical axis. The detection optical assembly direct optical radiation emanating from the focal point to a detector. The emanating optical radiation propagates from the focal point along a second optical axis. The wavefront shaping device is disposed in an optical path of the interrogating optical radiation or in an optical path of the emanating optical radiation. The controller sets a configuration of the wavefront shaping device to correct for aberration. The first optical axis is at a non-zero angle with respect to the second optical axis.

Optical imaging systems often suffer from degraded performance due to aberration, for example, due to optical elements, sample inhomogeneity, and refractive index mismatches within the optical path. Adaptive optics has been used to shape the wavefront of the optical radiation (e.g., light interrogating the sample) to help correct for aberrations introduced by optical elements or the sample itself. In many existing applications of adaptive optics, the optical system has access to a guide-star, which is a point-like structure that is smaller than the diffraction limit. The guide-star is used as a beacon for the tuning the adaptive optics to provide the desired correction of the aberration.
However, in some optical systems (e.g., certain microscopy or spectroscopy applications), the properties of the interrogated sample or the optical system may prevent or interfere with the use of a guide-star, thereby degrading the correction offered by adaptive optics. For example, in microscopy applications where the fluorescent labeling is diffused within a sample (e.g., a densely labeled sample that creates a fluorescent "sea"), it may be difficult to ensure the existence of a single fluorescent bead within the illumination path to use as a guide-star. Moreover, in some spectroscopic measurements, a signal may arise from any location within the illumination path. For example, the signal in Brillouin light scattering spectroscopy arises from the full extended region of the illuminated voxel, such that implementation of wavefront correction to a single location within the sample is not straightforward. As a result, performance of such spectroscopy systems is rapidly degraded by optical aberrations, and such spectroscopy systems have been limited to homogenous transparent samples.
Embodiments of the disclosed subject matter may address one or more of the above-noted problems and disadvantages, among other things.

Methods and arrangements to enhance optical signals within aberrated or scattering samples


A clock recovery circuit includes a first pulse circuit, a second pulse circuit, a state change circuit connected to the first pulse circuit and the second pulse circuit and a first delay circuit connected to the state change circuit and each of the first pulse circuit and the second pulse circuit. The first pulse circuit receives data inputs to generate a first pulse signal. The second pulse circuit receives the data inputs to generate a second pulse signal. The state change circuit receives the first pulse signal and the second pulse signal and generate a first clock signal for a first transition of one of the data inputs in a first unit interval (UI). The first delay circuit receives the generated first clock signal and mask other transitions of the data inputs in the first UI.

Advancements in the field of analog and digital circuits have increased the utilization of clock recovery circuits in different applications. Typically, in digital communication related circuits, transmitted signals need to be recovered at a receiving end to accurately decode information embedded in the transmitted signals. Such recovery of the transmitted signals may be done based on the clock recovery circuits. In certain situations, due to transitions of multiple digital signals in a particular unit interval, the conventional clock recovery circuits may not be effective to timely generate a clock signal for accurate recovering of the information embedded in the transmitted signals.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of described systems with some aspects of the present disclosure, as set forth in the remainder of the present application and with reference to the drawings.


An embedded metal heat sink for a semiconductor device is described. The embedded metal heat sink for a semiconductor device comprises a metal thin layer, a metal heat sink and two bonding pads. The metal thin layer including a first surface and a second surface on opposite sides, wherein at least one semiconductor device is embedded in the first surface of the metal thin layer, and the semiconductor device has two electrodes with different conductivity types. The metal heat sink is deposited on the second surface of the metal thin layer. The bonding pads are deposed on the first surface of the metal thin layer around the semiconductor device and are respectively corresponding to the electrodes, wherein the electrodes are electrically and respectively connected to the corresponding bonding pads by at least two wires, and the bonding pads are electrically connected to an outer circuit.

When small solid state opto-electrical devices, such as light-emitting diodes (LEDs) or laser diodes (LDs), are applied in a large or small backlight module or illumination module, many opto-electrical devices are needed to generate sufficient brightness or illumination for the modules. However, when the opto-electrical devices are operated at high power, the temperature of the module composed of the opto-electrical devices increases, thereby degrading the operational quality of the module and ultimately burning out the opto-electrical devices.
To resolve this high temperature issue, the module composed of the opto-electrical devices is typically cooled by fans set in the module or by increasing the heat dissipation area. However, regarding setting fans in the module, the vibration caused by the operation of the fans results in the lights flickering, and the fans consume additional power. Regarding increasing the heat dissipation area, although the heat sinks can be composed of metal with high thermal conductivity, glue mixed with metal is used to connect the opto-electrical device and the heat sinks, and the thermal conductivity of the glue is much lower than that of the pure metal. As a result, the heat generated during the operation of the opto-electrical device mostly accumulates at the connection interface, so that the heat sinks cannot transfer heat well, thereby making the heat sinks less effective, and easily damaging the opto-electrical devices during long-term operation or ultimately making the opto-electrical devices being operated with larger input power usage.
In addition, the heat sinks are typically connected to a circuit board with glue for electrically connecting the opto-electrical device and an outer circuit. Accordingly, the heat generated during the operation of the device accumulates at the glue, and the thermal conductivity of the circuit board composed of the plastic material is low, so the heat conductivity rate is low and greatly decreases the heat dissipation efficiency of the heat sinks.
Therefore, with the increasing demand for opto-electrical devices, such as light-emitting diodes and laser diodes, for backlight modules and illumination modules, a technique for manufacturing an opto-electrical device with high heat-sinking efficiency is required.

Embedded metal heat sink for semiconductor


Within audio telecommunications for audio-visual conferencing a means of reliable double-talk detection is required for several reasons, including control of residual echo, and control of adaptive algorithms used to estimate the echo. Existing techniques tend to either fail when echo return loss is very low or require highly complex algorithms to increase the range of detecting whether double-talk is occurring. The invention is based upon a new method of estimating the power envelope of the double-talk signal. This estimation is then employed in conjunction with a slightly modified version of an echo return loss enhancement (ERLE) based statistic, to form a double-talk decision based on a combination of the two statistics. The resulting decision rule works for both low-ERLE and high-ERLE situations, which is useful when there can be large variations in the magnitude of the echo path seen by the algorithms, or where near-end noise prevents the achievement of high ERLE.

In audio communication, there is a known problem of echo. Echo is particularly problematic when speakerphone functionality is used because voice data from both ends of a communication path is incident on a microphone at either end. To solve the echo problem, digital signal processing is used to subtract what is perceived by the digital signal processing to be echo related noise. To this end, converging processes have been designed to converge over time on an echoless or near echoless communication. As new processes have been designed, a time to converge and a quality of echoless communication have greatly improved.
Distinguishing echo signals from desired signals is often difficult due to double-talk situations. Double-talk occurs when two people, one on the receiving side of the network and one on the transmitting side of the network, speak simultaneously. The dual transmission and reception of signals disrupts echo canceller adaptation, and as a result, the echo canceller often performs poorly when a robust double-talk detector is not employed. When no double-talk exists, the echo canceller properly adapts its model of the echo signal path since the echo canceller only receives a signal that contains the echo. But during double-talk, the receiving side also transmits signals along a return signal path. Therefore, the echo canceller receives both return echo signals and signals transmitted from the receiving end simultaneously, and therefore may adapt improperly. Thus, a problem arises if the echo canceller erroneously adapts its model of the estimated echo signal according to a transmitted signal rather than according to an echo signal. The echo canceller may begin to distort transmitted signals.
Reliable double-talk detection is also important for echo cancellers that employ Non-Linear Processors (NLP) to improve echo canceller performance. In such architectures, a non-linear impediment is introduced in the transmit path when only the receive direction carries speech. This impediment is designed to remove residual echo (echo not cancelled by the adaptive filter), while passing the background noise from the transmitting end, or a reasonable-sounding imitation thereof. In many NLP implementations, it is necessary to turn off the NLP during double-talk, in order to allow transmitted (near-end) speech to pass unimpeded.
Reliable double-talk detection is required for various reasons, including control of residual echo, and control of adaptive algorithms used to estimate the echo. One existing technique for detecting double-talk uses changes in echo return loss enhancement (ERLE′) to distinguish between when a near-end signal is residual echo and when a near end signal comprises near-end speech. Since the echo canceller filter is for reducing the echo—far end speech received at the near-end microphone and the far end speech is affected by the room impulse response, a value E1 is determinable such thatE1=SIN/SOUT  (1)where SIN is the envelope (short-term average power) of an input signal provided from the microphone and SOUT is the envelope of an output signal provided from the echo canceller circuit. In theory, provided the echo canceller filter is reasonably well converged, then E1>1.0 (linear scale).
Obviously, in the absence of near-end speech, echo cancellation is easily evaluated. When the echo canceller has converged and there is no near-end speech, E1>>1.0, approaching infinity as noise approaches zero and the echo canceller filter approaches the RIR. This is a natural result of SOUT being in the denominator since when echo cancellation has converged without near-end speech SOUT should approach zero. As seen so far, E1 should be quite large when there is no double-talk and the echo canceller has converged.
As a result, double-talk may be determined to exist when the far-end is known to be active as determined by a voice activity detector, and hence:E1<E1Thresh  (2)where E1Thresh is a statistical value—either constant or pseudoconstant—which is established with respect to echo return loss enhancement (ERLE) by the relationship below in Equation 3.ERLE′>E1Thresh>1.0  (3)where ERLE is an estimate of average ERLE′ when there is no near-end speech, thereby making ERLE easy to evaluate. In actuality, ERLE′ varies with the signal, i.e. the far-end speech. In order to address these changes in ERLE′ either one of a long-term average, a minimum, or a recent estimate based on previous far-end speech without double-talk is often used to establish ERLE′. Many techniques for addressing changes in ERLE′ are proposed in the prior art.
Thus, in such a system the selection of E1Thresh is essential to ensure that double-talk is correctly identified. For very large values of ERLE, there are large ranges of potential E1Thresh values. However, as ERLE decreases, then E1Thresh is restricted to a much narrower range which can be problematic. In practice, this situation arises when the uncancelled echo return loss (ERL) is high—since most adaptive algorithms only cancel echo to a degree that is limited by the near-end noise floor, and hence the achieved ERLE depends on how much echo there is to cancel in the first place. High echo return losses (without cancellation) are characteristic of systems in which speakers and microphone are spatially separated from each other.
One such prior art approach is the so-called "Geigel algorithm" presented by Duttweiler (see D. L. Duttweiler, "A Twelve-Channel Digital Echo Canceller," IEEE Trans. On Communications, Vol. COM-26, No. 5, pp. 647-653, May 1978). The Geigel algorithm presents a means to detect double talk, and compares the magnitude of the current sample of reference echo with a current value of the input signal. If the magnitude of the reference echo is least −6 dB higher than the input signal, then double-talk is determined to be present. The Geigel algorithm is simple and fast. However, when the magnitude of the reference echo is lower than −6 dB higher than the input signal during double talk, the Geigel algorithm fails to detect the double-talk. The Geigel algorithm is also sensitive to near-end noise interference.
Yet another method for detecting doubletalk is outlined in U.S. Pat. No. 6,944,288 (Seibert, "Double-talk and Path Change Detection using a Matrix of Correlation Coefficients", hereinafter Seibert). Seibert teaches a process of generating matrix coefficients using zero-lag auto-correlation and cross-correlations from signals commonly found within echo cancellers. From these double-talk and path changes are then detected using matrix operations such as determinants, eigendecompositions, or singular value decompositions. In a preferred embodiment, the determinant of the correlation-based matrix is compared against predetermined threshold values. Seibert whilst improving over the Geigel algorithm is a processor intensive approach using matrix calculations.
It would be advantageous to provide a straightforward and effective method of detecting doubletalk.
It would be advantageous to provide a voice communication system that provides robust and effective doubletalk detection even when ERLE and/or ERLE′ has a low value—for example, for systems in which the ERL is high.


Embodiments of the present invention provide apparatus and methods for announcing a BSS parameter updates for a wireless link that can be received by a MLD even when the MLD is not listening for parameter updates on that specific link by employing a different wireless link to broadcast, receive, and/or signal the BSS parameter update. An MLD can update the BSS parameters of the wireless link and use the wireless link according to the updated BSS parameters (e.g., after performing a channel switch). According to some embodiments, an STA within an AP MLD transmits an information elements (IE) including BSS parameter updates associated with a different STA (operating on a different wireless link) within the AP MLD.

Modern electronic devices typically send and receive data with other electronic devices wirelessly using Wi-Fi, and many of these devices are "dual band" or multi-link devices (MLD) that include at least two wireless transceivers capable of operating in different frequency bands, e.g., 2.4 GHz, 5 GHz, and 6 GHz. In most cases, a wireless device will communicate over only a single band at a time. For example, older and low-power devices, e.g., battery powered devices, often operate on the 2.4 GHz band. Newer devices and devices that require greater bandwidth often operate on the 5 GHz band. The availability of the 6 GHz band is a recent advancement and can provide higher performance, lower latency, and faster data rates.
In some cases, the use of a single band may not satisfy the bandwidth needs of certain devices. Therefore, some developing approaches to wireless communication increase communication bandwidth by operating on multiple bands concurrently (technically called link aggregation or multi-link operation). Multi-link operations can provide higher network throughput and improved network flexibility compared to traditional techniques for wireless communication.
In most cases, a non-AP MLD will not enable all links at a given time to conserve power unless traffic requirements are relatively high. A non-AP MLD may operate on different channels depending on channel conditions, such as traffic, channel capabilities, bandwidth, etc., and may switch between the channels as necessary. An MLD can monitor the different links and perform basic operations, such as traffic indication and BSS parameter updates.
For these reasons, while a non-AP MLD may be associated with a wireless AP over multiple links, at a given time, the non-AP MLD however may only be actively listening for parameter updates on a single link. For example, the non-AP MLD may only have a single link enabled that is monitored for updates and used to perform basic operations while other links are in a reduced power or doze state. When a BSS parameter update is transmitted on one of these links, the non-AP MLD may not receive the parameter update and may not be able to use the wireless link associated with the parameter update, which is problematic.

Apparatus and methods for EHT multi-link BBS parameter update


Low speed switches operated under the common control of a global scheduler can be used to switch high speed data while preserving packet ordering if the incoming packets are queued in a temporal order. By operating several low speed switches in parallel, a high-speed switching capacity can be realized.

The Internet and its ever-increasing use, by a rapidly growing number of users continues to test the limits of switching equipment. Data networks that comprise the Internet are required to carry greater amounts of data, faster and faster. As a result, the data switches from which the networks are assembled are becoming increasingly complex and expensive.
Internet protocol (IP) data networks now routinely carry data at rates that are well over 1 gigabit per second. Switching equipment that is fast enough to handle such data rates, needs to be able to decode, among other things, address information embedded within an IP data packet and then, route packets to the appropriate destination. In managing the growth of data networks that carry high-speed data, a switching system architecture that is able to switch high-speed data at relatively low cost would provide a significant advantage to network service providers, in part, by providing them with the equipment to maintain service levels albeit at a relatively low cost.
The cross-bar switch is a well-known data switch. A cross bar switch is a switching system with some number of inputs and a comparable number of outputs. A connection between an input port and one of the output ports is established using switching techniques that functionally couple one of the inputs to one of the outputs much like a relay matrix.
Cross bar switching system technology is well known and such switching systems are relatively inexpensive to manufacture. A method and apparatus by which several of such systems could be operated in parallel to provide enhanced switching speeds would be an improvement over the prior art.


A system resource enable apparatus for enabling operations on a system resource including a register representing current and future operations on the resource, a pattern generator that applies a pattern corresponding to a requested resource operation to each of a plurality of requests for resource operations in a queue, compare logic that determines for each of the plurality of requests if the request will conflict with other resource operations by comparing the pattern applied to the request with the register, priority grant logic that grants priority to a request in the queue if no conflict is determined and to update the register according to the pattern applied to the request, and resource enable logic that enables operations on the resource according to the register. An automatic wake-up mechanism may also be provided to keep the array active during extended periods of non-use.

The present invention relates to controls for system resources and, more particularly, to controls for shared system resources providing for power conservation.
In semiconductor chips with large cache arrays, a substantial amount of the available power is used by the array. In one attempt to reduce array power consumption, lower-power array cells have been utilized. Such low-power array cells, however, may degrade system performance.
In another attempt to reduce array power consumption, arrays have been designed which allow the clock input to be shut off providing an array "standby" mode. These arrays, however, often suffer performance degradation resulting from turning on the array in the cycle that it is needed.
In the prior art is U.S. Pat. No. 5,339,445 to Gasztonyi which describes a further attempt to reduce array power consumption. Gasztonyi maintains a data table with historical information on power consumption and uses the data to regulate power for future operations. Operating on historical data, however, can lead to inaccuracies in power application and correspondingly to inefficient operation of the array.
Thus, there is a need in the art for a method and apparatus for controlling power application to an array that conserves power while optimizing array performance.

System resource enable apparatus with wake-up feature

International Business Machines Corporation


The present application is directed to vertebral rods and methods of use. In one embodiment, the rod includes upper and lower sections that are separated by an intermediate section. The intermediate section may include one or more members, and may have a variety of configurations. An elastic member may be positioned within the intermediate section. The intermediate section and the elastic member may provide for variable resistance during movement of the upper and lower sections. In one embodiment, the resistance increases the further away the upper and lower sections move from a first orientation.

Vertebral rods are often used in the surgical treatment of spinal disorders such as degenerative disc disease, disc herniations, scoliosis or other curvature abnormalities, and fractures. Different types of surgical treatments are used. In some cases, spinal fusion is indicated to inhibit relative motion between vertebral members. In other cases, dynamic implants are used to preserve motion between vertebral members. For either type of surgical treatment, one or more rods may be attached to the exterior of two or more vertebral members, whether it is at a posterior, anterior, or lateral side of the vertebral members. In other embodiments, rods are attached to the vertebral members without the use of dynamic implants or spinal fusion.
Rods may redirect stresses over a wider area away from a damaged or defective region and restore the spine to its proper alignment. Rods may also increase loading on interbody constructs, decrease stress transfer to adjacent vertebral members while bone-graft healing takes place, and generally support the vertebral members.


An apparatus for use with a vehicle dynamic characteristic control system employing a vehicle speed sensor, a steering handle position sensor and a steering handle neutral position sensor to control the dynamic characteristics of an automotive vehicle. The vehicle speed sensor is sensitive to vehicle speed for producing a vehicle speed signal indicative of a sensed vehicle speed. The steering handle position sensor is sensitive to steering handle position for producing a steering handle position signal indicative of a sensed steering handle position. The steering handle neutral position sensor is sensitive to steering handle position for producing a steering handle neutral position signal having a first level when the sensed steering handle position is in a predetermined neutral range and a second level when the sensed steering handle position is out of the predetermined neutral range. A steering handle neutral position is estimated based upon the steering handle position signal and the steering handle neutral position signal. A steering angle, which corresponds to an absolute value of a difference of the sensed steering handle position from the estimated steering handle neutral position, is calculated. A failure signal is produced to indicate that at least one of the steering handle position sensor and the steering handle neutral position sensor is subject to failure when the calculated steering angle is equal to or greater than a predetermined value and when the vehicle speed is held above a predetermined value normal for vehicle running in an urban area for a predetermined interval of about 60 seconds.

This invention relates to an apparatus for producing a failure signal in the event of failure of a steering handle position sensor which may be used in controlling vehicle dynamic characteristics including yaw velocity, side velocity, roll velocity, etc. Although the invention will be described in connection with a rear wheel steering control system, it should be understood that the invention is equally applicable to other vehicle dynamic characteristic control systems including active suspension control systems and the like utilizing information on steering handle position to control the dynamic characteristics of motor vehicles.
For example, U.S. patent application Ser. No. 07/284,414, filed Dec. 14, 1988, now abandoned, discloses a rear wheel steering control system for controlling the angle of steering of the rear wheels based on a rear wheel steering angle calculated as a function of vehicle speed and front wheel steering angle. For the purpose of calculating the front wheel steering angle, which corresponds to a deviation of the existing steering handle position from a steering handle neutral position indicating a driver's demand for straight ahead driving, the rear wheel steering control system includes a steering handle position sensor for sensing the existing steering handle position and a steering handle neutral position sensor for producing a steering wheel neutral position signal having a first level when the steering handle position is within a predetermined range and a second level when the steering handle position is out of the predetermined range. The rear wheel steering control system estimates the steering handle neutral position by calculating an average value of the steering wheel position sensed when the steering wheel neutral position signal changes from the second level to the first level and the steering handle position sensed when the steering wheel neutral position signal changes from the first level to the second level. Japanese Patent Kokai No. 59-26341 also discloses an apparatus which employs a steering handle position sensor and a steering handle neutral position sensor to estimate a steering handle neutral position. The estimated steering handle neutral position is used to provide information used in controlling a four wheel steering system.
With such conventional control systems, however, the estimated steering handle neutral position will be diviated to a great extent from a correct neutral position, causing the rear wheels to be turned in response to a driver's demand for straight ahead driving when a failure occurs in the steering wheel position sensor or the circuit associated therewith to maintain the steering handle neutral position signal at one of the first and second levels.
An indication of failure in the steering handle position sensor or the circuit associated therewith has been provided when the two conditions are fulfilled, that is, when the vehicle speed exceeds a predetermined value, for example, 60 Km/h, and the steering handle position signal produced from the steering handle position does not indicate a steering angle equal to or greater than a predetermined value, for example, 1 degree, for a predetermined interval of time, for example, 180 sec. However, controls will be made based upon the steering handle position sensed when the steering handle position sensor or the circuit associated therewith is subject to failure until the predetermined period of time has been elapsed. That is, the conventional failure indication has a slow response to an event of failure of the steering handle position sensor. Furthermore, the failure indication cannot be produced when the vehicle is running at a speed, about 50 Km/h, which is normal for vehicle running in an urban area.

Steering handle position sensor checking apparatus


A curing agent for epoxy resins that is comprised of the reaction product of an amine, an epoxy resin, and an elastomer-epoxy adduct; compositions containing the curing agent and an epoxy resin; the compositions are useful in electronic displays, circuit boards, semi conductor devices, flip chips and other applications.

Epoxy adhesives have been known for over 50 years and were one of the first high temperature adhesives to become commercialized. Once cured, the material retains its adhesive properties over a large range of temperatures, has high shear strengths, and is resistant to weathering, oil, solvents, and moisture. The adhesive is available commercially as either a 1-part adhesive or 2-part adhesive and is available in several forms, such as pastes, solvent solutions, and supported films. Of the three forms, the 1-part adhesive film generally provides good adhesive strength with better thickness uniformity and has found practical use in the development of anisotropic conducting films for electronics, most notably flat panel displays.
To construct a 1-part adhesive film, one typically combines all at once, a latent hardener, multi-functional epoxy resins, phenoxy resins, additives, and optionally fillers. This composition is then cast as a film on a release layer. During the bonding process, the adhesive is transferred to one particular surface and the release layer removed. Another surface is brought into contact with the film, and the adhesive hardened or cured into a strong thermosetting adhesive through the application of heat and/or pressure. In this example, the two components of the adhesive that enable the material to cure into a thermoset adhesive are the hardener and the multi-functional epoxy. It is the later, that sets up the cross-linked network, but it is the former that enables this to happen. During the curing process, the latent hardener initiates the polymerization of the multi-functional epoxy by first forming ring-opened adducts with the oxiranes of the epoxy resin. Once produced, the addition products cause a cascade of ring-opened species that propagate through the adhesive, finally producing a cross-linked thermoset material.
The active ingredient of the hardener is usually comprised of the reaction product of an amine compound, like an imidazole, and an epoxy resin. Such adducts are known to initiate and accelerate the cure of epoxy resins (Heise, M. S.; Martin, G. C. Macromolecules, 1989, 22 99-104; Heise, M. S.; Martin, G. C. J. Poly. Sci.: Part C: Polym. Lett. 1988, 26, 153-157; Barton, J. M; Shepherd, P. M.; Die Makromolekular Chemie 1975 176, 919-930). One drawback of these however is that they are so effective as curatives they cannot be used directly into a 1-part adhesive because once added, they would start to kick-off the cure in a relative short period of time. What one would see therefore is a slow increase in the viscosity of the composition, while one is attempting to make the adhesive and its film, as the hardener continues to accelerate the ring-opening polymerization of the epoxy moieties. This phenomenon is most commonly referred to as reduced workable lifetime, in other words, the time available to assemble the adhesive and make the film was dramatically reduced because of premature hardening. Therefore, to stop this from happening, one usually does not use amine-epoxy adducts themselves as hardeners, but instead what is typically done is to encapsulate or coat the amine-epoxy adduct with a protective shell of material that sequesters the amine-epoxy adduct from the adhesive environment. Once incorporated into the adhesive, the amine-epoxy adduct is released from its protective shell through the application of heat and/or pressure. Such latent hardeners described here are commonly called to as a core-shell latent hardener, where the core in this case is an amine-epoxy adduct and the shell is the protective shell.
There is one significant trade-off often encountered with core-shell latent hardeners, which is the cure speed is often slowed and the cure temperature often increased because of the inclusion of a protective shell, which must be broken or rendered permeable in order to allow the core material to be released into the adhesive environment or matrix. Without being bound by any particular theory, it is well known that as one increases the barrier properties of the shell material using such means, like increasing the thickness of the shell, cross-linking density, or Tg of the shell, or by increasing the degree of incompatibility between the shell and the core material or the adhesive matrix, it takes more energy to release the amine-epoxy adduct into the adhesive environment. What one has therefore is a hardener that when formulated into a 1-part adhesive has the desired property of increased shelf life stability, but at the expense of a lower curing temperature and a reduction of cure speed. Therefore, it continues to be a constant balance to prepare a core-shell latent hardener that has just enough of a protective shell to protect the core material at normal storage conditions, but not too much as to slow down the cure speed of the adhesive. Also, the release of the core material may be triggered at a reasonably low temperature and completed within a narrow temperature range.
One of the most frequently used core-shell latent hardeners are those comprised of core-shell materials, as described in U.S. Pat. Nos. 4,833,226, 5,219,956, US 2006/0128835, US 2007/0010636, US 2007/0055039, US 2007/0244268, EP 1,557,438, EP 1,731,545, EP 1,852, 452, and EP 1,980,580. The hardeners described here are obtained, first by the synthesis of a lump of core material, which is then pulverized into micro-sized particles that are irregular in shape. The core material is the reaction product of an amine compound and an epoxy resin and said core material functions as a hardener for epoxy compositions, such as that found in adhesives and coatings. To improve the storage stability of the core material and prevent premature curing, it is encapsulated with a shell of a material that is impervious to components of the epoxy composition, such as solvent, diluent, low molecular weight epoxides and additives. To accomplish this, the pulverized solid is added to a mixture of polyfunctional isocyanate, an active hydrogen compound, like water, and an epoxy resin. The chemistry of said encapsulation procedure relies on the cross-linking reactions and/or hydrolysis of the polyisocyanate compound to form a cross-linked shell coating around the particles. Typical cross-linking structures of the shell include, but are not limited to, urea, urethane, carbamate, biuret, allophanate, etc. However, the crosslinking reactions take places randomly without discrimination in the continuous phase and at the interface. It is highly likely that some core particles are not fully encapsulated, while unwanted byproducts such as crosslinked polyurea particles are produced in the continuous phase. Moreover, the core particles prepared by this process are of irregular shape with a very broad distribution of shape and particle size, the uniformity of the thickness and crosslinking density of the shell formed thereon is very poor. As a result, the encapsulated hardener particles typically show a very broad distribution of release property and the 1-part adhesive formulated with this type of hardener capsules often shows poor shelf-life stability and a sluggish curing profile or a high curing temperature.
There is another group of inventions, namely EP 459,745, EP 552,976, U.S. Pat. Nos. 5,357,008, 5,480,957, 5,548,058, 5,554,714, 5,561,204, 5,567,792, and 5,591,814, that also describe core shell latent hardeners, which unlike those above are spherical in shape. The core material is obtained as a spherical particle and is synthesized from the reaction of an amine with an active hydrogen atom (e.g., imidazole) and an epoxy resin, in an organic medium and in the presence of a dispersant. The amine, epoxy resin, and dispersant are soluble in the organic medium, while the reaction product, the core material, is not, and as a result the core particle precipitates out from solution as a stable dispersion with a relatively narrow size distribution. The most important factor to make a stable dispersion of desirable particle size with a narrow size distribution is the nature of the dispersant and the inventors show examples that use dispersants from the class of graft of polyacrylates, polyacrylamides, polyvinyl acetates, polyethylene oxides, polystyrenes, and polyvinyl chlorides. Once isolated, the spherical core material is encapsulated with an isocyanate to prepare a spherical core-shell latent hardener.
One disadvantage of the aforementioned latent hardeners is the need of the shell material to be free of defects, such as such as holes, voids, thin areas, or areas comprised of insufficient cross-link density. These defects would enable the core to escape from the protective shell prematurely, either during processing or storage of the finished article. Either way, this premature release of core from the encapsulated latent hardener would show up as a loss of storage stability and shelf-life (in the case of a 1-part epoxy adhesive). This deficiency; however, can be overcome by the application of additional and successive layers of the shell material over the preexisting shell, thus filling in and coating the defects with an additional layers shell material.
Another limitation of the prior art is that in an attempt to make the protective shell more impervious and thereby improving its barrier properties, the compatibility of the shell with the surrounding epoxy composition was neglected. The prior art teaches encapsulation in the presence of an isocyanate, and optionally water and additional epoxy. What one then obtains is a shell comprised of a cross-linked polyurethane and optionally a polyurea. When formulated into an epoxy adhesive, the now hard and highly cross-linked shell could have poor capability with the surrounding epoxy. An example of this would be a mismatch of surface tensions between the surface of the shell and the epoxy; which would show up as a dewetting phenomenon in which the epoxy fails to adequately wet and spread over the surface of the shell material. As a consequence therefore one would see that after curing, the adhesive would contain voids and regions of inhomogeneous curing, both of which would lead to a reduction of adhesive strength.
There remains a need for core-shell latent hardeners with improved barrier properties to prevent premature cure. Additionally, there is a need of encapsulated latent hardeners with improved epoxy compatibility.

This patent is subject to a terminal disclaimer.

Latent hardener with improved barrier properties and compatibility


An active type display panel comprises a plurality of pixel sections each having a series circuit constituted by a light emitting element and a drive element for supplying a drive current to the light emitting element, a pair of power supply lines which connect the series circuits of the pixel sections in parallel, and a plurality of measurement lines. Each of the pixel sections includes a switch element between a point connecting the light emitting element and the drive element, and one line of the measurement lines. A display device, in which the display panel is used, detects the voltage across the terminals of the light emitting element and controls the drive element such that the voltage across these terminals is a predetermined voltage.

1. Field of the Invention
The present invention relates to an active type display panel in which light emitting elements such as organic electroluminescence elements are disposed, a display device in which the display panel is used, and a display panel driving method thereof.
2. Description of the Related Art
Electroluminescence display devices (referred to as EL display devices hereinafter) mounted with a display panel employing organic electroluminescence elements (referred to simply as EL elements hereinafter) in the form of light emitting elements carrying pixels are currently attracting attention. Known systems for driving display panels by means of these EL display devices include simple matrix type and active matrix type systems. In comparison with simple matrix type systems, active matrix type EL display devices consume very little electrical power and afford advantages such as low cross-talk between pixels, and are particularly suitable as large screen display devices and high definition display devices, and so forth.
As shown in FIG. 1, EL display devices are constituted by a display panel 1, and a driving device 2 for driving the display panel 1 in accordance with an image signal.
The display panel 1 is formed having an anode power supply line 3, a cathode power supply line 4, m data lines (data electrodes) A1 to Am arranged in parallel so as to extend in the perpendicular (vertical) direction of one screen, and n horizontal scan lines (scan electrodes) B1 to Bn for one screen which are orthogonal to the data lines A1 to Am. A drive voltage Vc is applied to the anode power supply line 3 and a ground potential GND is applied to the cathode power supply line 4. Further, pixel sections E1.1 to Em.n each carrying one pixel are formed at the points of intersection between the data lines A1 to Am and the scan lines B1 to Bn of the display panel 1.
The pixel sections E1.1 to Em.n have the same constitution and are constituted as shown in FIG. 2. That is, the scan line B is connected to the gate G of a scan line selection FET (Field Effect Transistors) 11, and the data line A is connected to the drain D thereof. The gate G of a FET 12, which is a light emission drive transistor, is connected to the source S of the FET 11. When the drive voltage Vc is applied via the anode power supply line 3 to the source S of the FET 12, a capacitor 13 is connected between this gate G and source S. In addition, the anode terminal of the EL element 15 is connected to the drain D of the FET 12. A ground potential GND is applied through the cathode power supply line 4 to the cathode terminal of the EL element 15.
The driving device 2 applies a scan pulse sequentially and alternatively to the scan lines B1 to Bn of the display panel 1. In addition, the driving device 2 generates, in sync with the application timing of the scan pulse, pixel data pulses DP1 to DPm which are dependent on the input image signals corresponding to the horizontal scan lines, and applies these pulses to the data lines A1 to Am respectively. The pixel data pulses DP each have a pulse voltage which is dependent on the luminance level indicated by the corresponding input image signal. The pixel sections which are connected on the scan line B to which the scan pulse is applied are the write targets of this pixel data. The FET 11 in a pixel section E which is the write target of this pixel data assumes an on state in accordance with the scan pulse such that the pixel data pulse DP supplied via the data line A is applied to the gate G and to the capacitor 13 of the FET 12. The FET 12 generates a light emission drive current which is dependent on the pulse voltage of this pixel data pulse DP and supplies this drive current to the EL element 15. In response to this light emission drive current, the EL element 15 emits light at a luminance which is dependent on the pulse voltage of the pixel data pulse DP. Meanwhile, the capacitor 13 is charged by the pulse voltage of the pixel data pulse DP. As a result of this recharging operation, a voltage that depends on the luminance level indicated by the input image signal is stored in the capacitor 13 and so-called pixel data writing is then executed. Here, when discharge from the pixel data write target takes place, the FET 11 enters an off state, and the supply of the pixel data pulse DP to the gate G of the FET 12 is halted. However, because the voltage stored in the capacitor 13 as described above is continuously applied to the gate G of the FET 12, the FET 12 continues to cause a light emission drive current to flow to the EL element 15.
The light emission luminance of the EL elements 15 of each of the pixel sections E1.1 to Em.n depends on the voltage which is stored in the capacitor 13 as described above according to the pulse voltage of the pixel data pulse DP. In other words, the voltage stored in the capacitor 13 is the gate voltage of the FET 12 and therefore the FET 12 causes a drive current (drain current Id) that is dependent on the gate-source voltage Vgs to flow to the EL element 15. The relationship between the gate-source voltage Vgs of the FET 12 and the drain current Id is as shown in FIG. 3, for example. The flow of drive current through the EL element 15, which current is at a level that is dependent on the level of the voltage stored in the capacitor 13, constitutes the light emission luminance that depends on the level of the voltage stored in the capacitor 13. Thus, the EL display device is capable of a gray level display.
In a drive transistor such as the FET 12, the characteristic for the relationship between the gate-source voltage Vgs and the drain current Id changes according to temperature changes and inconsistencies in the transistor itself. For example, in cases where characteristics (characteristics indicated by solid lines) deviate from the standard characteristic (broken line) as shown in FIG. 4, the respective drain currents Id are different for the same gate-source voltage Vgs, and therefore the EL element cannot be caused to emit light at the desired luminance.
A voltage change range for the gate-source voltage Vgs with respect to the luminance change range which is required for the gray level display is established beforehand. If the characteristic for the relationship between the gate-source voltage Vgs and the drain current Id is standard, the current change range of the drain current Id with respect to the voltage change range of the gate-source voltage Vgs is as shown in FIG. 5A. The current change range of the drain current Id shown in FIG. 5A is a range that corresponds to the luminance change range required for the gray level display. On the other hand, in cases where there is a change in the relationship characteristic, the current change range of the drain current Id with respect to the pre-established voltage change range of the gate-source voltage Vgs differs from the luminance change range required for the gray level display shown in FIG. 5A, as shown in FIGS. 5B and 5C. Therefore, when there is a variation in the drive current characteristic with respect to the input control voltage as a result of a drive transistor temperature variation and inconsistencies in the transistor itself, a correct gray level display is not possible.


Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling compensation includes determining a state of a memory cell using a voltage that is changed in accordance with a first memory cell coupling compensation voltage, performing an error check on the state of the memory cell, and determining the state of the memory cell using a voltage that is changed in accordance with a second memory cell coupling compensation voltage in response to the error check failing.

Memory devices are typically provided as internal, semiconductor, integrated circuits and/or external removable devices in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change random access memory (PCRAM), and flash memory, among others.
Flash memory devices can be utilized as volatile and non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Uses for flash memory include memory for solid state drives (SSDs), personal computers, personal digital assistants (PDAs), digital cameras, cellular telephones, portable music players, e.g., MP3 players, and movie players, among other electronic devices. Data, such as program code, user data, and/or system data, such as a basic input/output system (BIOS), are typically stored in flash memory devices.
Two common types of flash memory array architectures are the "NAND" and "NOR" architectures, so called for the logical form in which the basic memory cell configuration of each is arranged. A NAND array architecture arranges its array of memory cells in a matrix such that the control gates of each memory cell in a "row" of the array are coupled to (and in some cases form) an access line, which is commonly referred to in the art as a "word line". However each memory cell is not directly coupled to a data line (which is commonly referred to as a digit line, e.g., a bit line, in the art) by its drain. Instead, the memory cells of the array are coupled together in series, source to drain, between a common source and a data line, where the memory cells commonly coupled to a particular data line are referred to as a "column".
Memory cells in a NAND array architecture can be programmed to a target, e.g., desired, state. For example, electric charge can be placed on or removed from a charge storage structure of a memory cell to put the cell into one of a number of program states. For example, a single level cell (SLC) can represent two states, e.g., 1 or 0. Flash memory cells can also store more than two states, e.g., 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 0000, 1000, 1010, 0010, 0110, and 1110. Such cells can be referred to as multilevel cells (MLCs). MLCs can allow the manufacture of higher density memories without increasing the number of memory cells since each cell can represent more than one digit, e.g., more than one bit. For example, a cell capable of representing four digits can have sixteen program states.
Capacitive coupling can exist between charge storage structures, e.g., floating gates, of flash memory cells. As an example, the threshold voltage (Vt) of a cell programmed to a target state can change, e.g., increase, due to capacitive coupling associated with floating gates of adjacent cells. The amount of Vt change, e.g., Vt shift, associated with a cell programmed to a target state due to capacitive coupling can depend on the Vt of one or more adjacent cells. For instance, adjacent cells programmed to a higher program state, e.g., a state associated with a higher Vt, may have a greater effect on the Vt of the target cell than adjacent cells programmed to a lower program state, e.g., a state associated with a lower Vt. In some instances, the Vt shift of a target cell, e.g., due to programming of an adjacent cell, can lead to erroneous sensing of the target cell. For instance, the Vt shift may be sufficient such that a sensing operation performed on the target cell results in a determined sensed state other than the target state of the target cell.
One approach to compensating, e.g., tracking, for changes in the Vt of a memory cell, e.g., due to capacitive coupling, can include using a reference cell during a sensing, e.g., read, operation on the memory cell. However, the use of reference cells can increase the area of the memory array, decrease the quantity of memory cells in the array, and/or increase the amount of circuitry associated with the memory device.


In a semiconductor device constituted using a borderless contact technique, for example, when a wiring layer with a damascene structure is connected to its underlying contact portion, a trench connecting with the contact portion is formed in the second interlayer insulation film. After that, the contact portion protruded from the bottom of the trench is selectively etched to flatten the bottom of the trench to remove a very small recess from that bottom of the trench which corresponds to a contact face between the contact portion and wiring layer. Thus, both a barrier metal layer and a metal layer for forming the wiring layer can be formed in the trench with higher reliability and accordingly the wiring layer and contact portion can be brought into reliable contact with each other. In a DRAM using a simple stacked capacitor, the storage electrode and plug portion can be put into reliable contact with each other.

The present invention relates to a semiconductor device and a method for manufacturing the same and, more specifically, to a DRAM (dynamic random access memory) including a semiconductor device having a wiring structure adopting a borderless contact technique and a stacked capacitor.
Semiconductor devices have recently been miniaturized in accordance with progress in semiconductor processing techniques and dramatically improved in degree of integration.
In a prior art semiconductor device having a structure of connecting wiring layers through a contact via, the wiring layers are increased in width at the contact portion since there are variations in pattern alignment in the lithographic process, measurements, and etching depths of contact holes. The increase in width of the wiring layers necessitates a margin for alignment, which makes the chip area larger and hinders the device from being miniaturized. Therefore, a borderless contact technique not requiring the alignment margin, has recently been used widely in which an interlayer insulation film between upper and lower wirings is flattened completely using a polishing technique such as CMP (chemical mechanical polishing) to make uniform an amount of etching of the insulation film.
FIG. 1 is a cross-sectional view illustrating the major part of a typical prior art semiconductor device constituted by the borderless contact technique described above.
In the prior art semiconductor device, for example, an element isolation insulation film 102, which is a silicon oxide film, is selectively buried in a surface portion of a p-type silicon substrate 101 to form an element isolation region 101a. In this region 101a, a gate electrode 103A is provided on the silicon substrate 101. In an element region 101b other than the region 101a, a gate electrode 103B is formed on the substrate 101 with a gate oxide film 104 interposed therebetween. The gate electrodes 103A and 103B each have a layered structure of polysilicon 103a and tungsten silicide 103b. An on-gate insulation film 105, which is a silicon nitride film, is formed on the upper surface of each of the gate electrodes 103a and 103b, and a gate side-wall insulation film 106, which is also a silicon nitride film, is formed on the side-wall thereof.
Furthermore, shallow n-type diffusion layers 107a and 107b serving as source and drain regions, are formed in the surface portion of the silicon substrate 101 in the element region 101b, using the gate electrode 103B as a mask.
A plug portion 109A connecting with the gate electrode 103A and a contact portion 109B connecting with one of the diffusion layers 107a and 107b are provided in a first interlayer insulation film 108 formed all over the surface of the substrate 101 including the surfaces of the gate electrodes 103A and 103B. Each of the portions 109A and 109B is so constituted that a contact hole 108a is formed in the first interlayer insulation film 108, a barrier metal layer 109a of Ti/TiN is formed at least on the bottom and side of the hole 108a, and a metal layer l09b of tungsten or aluminum is formed on the layer 109a.
A second interlayer insulation film 110 is formed all over the surface of the first interlayer insulation film 108, including the surfaces of the plug portion 109A and contact portion 109B, and both a plug portion 111A connecting with the plug portion 109A and a wiring layer 111B connecting with the contact portion 109B are formed on the film 110. Each of the plug portion 111A and wiring layer 111B is so constituted that both a contact hole 110a and a trench 110b are formed in the second interlayer insulation film 110, a barrier metal layer 111a of Ti/TiN is formed on at least the bottom and side of each of the hole 110a and trench 110b, and a metal layer 111b of tungsten or aluminum is formed on the layer 111a.
In the semiconductor device so constituted, for example, when the second interlayer insulation film 110 is processed selectively by RIE (reactive ion etching) to form the above contact hole 110a and trench 110b, an amount of etching for the RIE is set larger in consideration of variations in pattern alignment in the lithographic process, measurements, thickness of the second interlayer insulation film 110, etc. For this reason, when the film 110 is processed, that part of the first interlayer insulation film 108 which contacts the plug and contact portions 109A and 109B, is over-etched to obtain recesses 112a and 112b. Usually these recesses have various measurements since they are influenced complexly and randomly by the above-described variations.
The recess 112b having a large area may not cause a serious problem, whereas the recess 112a having a very small area has a drawback in which the barrier metal layer 111a and metal layer 111b are formed incompletely to cause a void, and a conductive film cannot be covered sufficiently. The drawback will be disadvantageous to suppressing an increase in contact resistance, a variation, and a decrease in wiring reliability. Further, the drawback is not limited to the formation of the plug portion 111A and wiring layer 111B, but is true of the formation of the contact via for connecting the upper and lower wiring layers and that of a storage electrode in a DRAM using a stacked capacitor.
For example, in the layout of cells of the DRAM, the borderless contact technique has been employed in order to reduce the chip area. Even though the area per bit is decreased in accordance with miniaturization of the DRAM, several tens of femto-farads (fF) of the storage capacitance of the capacitor have to be secured. For this reason, a three-dimensional structure such as a stacked structure and a trenched structure, is adopted in the capacitor of the DRAM which is progressing in miniaturization.
It is considered to employ not only a silicon oxide film and a silicon nitride film, but also a high dielectric thin film, such as tantalum pentaoxide (Ta.sub.2 O.sub.5), strontium titanic acid (SrTiO.sub.3 (STO)), strontium barium titanic acid ((Ba, Sr) TiO.sub.3 (BSTO)), as the capacitor insulation film.
In order to apply the high dielectric thin film to a highly-integrated semiconductor device appearing after a 1-Gbit DRAM, in which the high dielectric thin film is formed by the minimum processing measurements of 0.2 .mu.m or less, the thin film has to be formed uniformly and at high grade on a storage electrode. Thus, the advantage of the storage electrode, to which a complicated processing of forming a fin type storage electrode and making the surface of the electrode coarse is applied, will be lost. The high dielectric thin film is thin in comparison with the oxide film, but its actual thickness is relatively large, which will not take effect too much.
In particular, when the storage electrode has a complicated shape, the leak current of the capacitor increases, the breakdown voltage thereof lowers, and the reliability thereof deteriorates. It is thus desirable to form a storage electrode having a simple shape when a high dielectric thin film is employed in the capacitor insulation film.
FIG. 2 is a cross-sectional view illustrating the structure of a prior art DRAM cell using a simple, stacked capacitor.
For example, an element isolation trench portion 202 is formed selectively in a surface portion of an p-type silicon substrate 201, and n-type diffusion layers 204 serving as source and drain regions are formed therein using a gate electrode 203 as a mask, thus obtaining a plurality of MOS transistors. The gate electrode 203 is constituted of polysilicon and tungsten silicide and formed on the silicon substrate 201, with a gate oxide film 205 interposed therebetween. The top and side of the gate electrode 203 are covered with an insulation film 206.
A bit line 207 formed of both polysilicon and tungsten is connected to one of the diffusion layers 204 of the source and drain regions. An interlayer insulation film 208 is formed on the entire surface of the substrate 201 including the surface of the bit line 207, and a plug portion 209 connecting with the other diffusion layer 204, is provided in the interlayer insulation film 208. Furthermore, an interlayer insulation film 301 is deposited on the layer 208 to form a storage electrode 210 connecting with the plug portion 209 and provide a plate electrode 212 with a capacitor insulation film 211 interposed therebetween. In this case, if an Ru film is used as both the storage electrode 210 and plate electrode 212 and a BSTO film is employed as the capacitor insulation film 211, the structure of a stacked capacitor can be simplified.
Forming the interlayer insulation film 301 on the interlayer insulation film 208 prevents the plug portion 209 from being exposed after the storage electrode 210 is formed. The exposure of the plug portion 209 is caused by variations in pattern alignment in the lithographic process and in measurements, when the short side of the storage electrode 210 is almost equal to the width of the plug portion 209. In other words, if the BSTO film is formed with the plug portion 209 exposed from the surface, a capacitor is to be formed between the storage electrode 210 and plug portion 209 the matter of which differs from that of the storage electrode 210. This capacitor causes an increase in leak current, decrease in breakdown voltage, and degrades the reliability.
In order to prevent a capacitor from being formed between the capacitor insulation film 211 and plug portion 209, the interlayer insulation film 301 is deposited further on the interlayer insulation film 208 including the surface of the plug portion 209, a trench 302 is formed in that area of the film 301 where the capacitor is to be formed, and the storage electrode 210 is formed in the trench 302 and connected to the plug portion 209 at the bottom of the trench 302.
However, the capacitor having the above constitution has to be formed by setting the short side of each of the plug portion 209 and trench 302 to the minimum. Due to both a variation in pattern alignment in the lithographic process and over-etching in the region where the capacitor is to be formed, not only the interlayer insulation film 301 on the plug portion 209, but also part of the interlayer insulation film 208 is etched to excess, and a recess 303 is formed alongside the plug portion 209. The recess 303 varies in size and aspect ratio because of variations in pattern alignment and an amount of over-etching.
If, in particular, the recess 303 is very small, the storage electrode 210 is formed incompletely therein. Therefore, neither the capacitor insulation film 211 nor the plate electrode 212 formed on the storage electrode 210 is sufficiently covered with an Ru film. With such a capacitor, an increase in leak current occurs and thus a decrease in reliability also occurs.

Semiconductor device and method for manufacturing the same


The present application discloses a system for video storage and method for video data transmission based on the same. The system for video storage in the present application includes a first control node, a second control node and at least two storage nodes. Each control node includes a signal agent module, and each storage node includes a data agent module. The second control node is configured for starting the signal agent module of the second control node after determining that the first control node is unavailable. The signal agent module of the second control node is configured for transmitting an instruction to the data agent module of a designated storage node based on a service request through a preset virtual IP address. The data agent module of the designated storage node is configured for transmitting video data to the third-party platform according to the received instruction and based on the predetermined signal protocol. This can effectively avoid the single point of failure and ensure the stability of the system.

GB/T28181 is a surveillance signal transmission standard protocol based on Session Initiation Protocol (SIP). The applicant of the present application finds that in the GB/T28181 protocol, a system establishes a communication with a SIP server through a SIP agent device. Once the SIP agent device goes down, the system cannot communicate with the SIP server. The entire interaction process cannot proceed because of a single point of failure.

Video storage system, and video data transmission method for same

Hangzhou Hikvision Digital Technology Co., Ltd.


Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for detecting deviations from targeted design performance in accelerator/emulator environment. In an embodiment, the method comprises loading target vales for a performance metric onto a hardware-accelerated simulator; setting breakpoints to pause the simulator at defined intervals; simulating, by the hardware-accelerated simulator, execution of a circuit design. The method further comprises during the simulating, using said breakpoints to pause the simulating at the defined intervals, and during each pause, comparing a measured value for the performance metric to the target value for the performance metric; and ending the simulation when a specified condition based on said comparing is met. In embodiments, when a difference between the measured value for the performance metric and the target value for the performance metric is within a preset tolerance, the pause is ended and the simulation continues.

This invention, generally, relates to simulation environments, and more specifically, to hardware accelerated simulation environments.
Accelerator/Emulator environments are often used to verify the performance of processors and other circuits. This environment allows running long and complex performance benchmarks. But at the same time detecting performance bugs is harder due to limited visibility into the simulation.

Detecting deviations from targeted design performance in accelerator/emulator environment

International Business Machines Corporation


A digital data propagation delay margin monitoring circuit that includes (a) a digital data propagation unit having a send flip-flop, a combinatorial delay, and a receive flip-flop; and (b) a margin detection circuit having a test flip-flop that receives the same input as the receive flip-flop and is configured to have a set up time margin or a hold time margin that is less than the set up margin or hold time margin of the receive flip-flop by a predetermined amount, depending upon which margin is being monitored. The outputs of the receive flip-flop and the test flip-flop are compared by a comparison circuit which provides an indication of when the outputs of the receive flip-flop and the test flip-flop are different, which indicates that the monitored margin of the receive flip-flop has been reduced to a predetermined margin or less. For set up margin monitoring, the data propagation unit is the actual system path that is a worst case for set up, or a surrogate for such actual system path, and the test flip-flop is configured to have a reduced set up margin by a delay at its input or by an advanced clock signal. For hold margin monitoring, the data propagation unit is the actual system path that is a worst case for hold time, or a surrogate for such actual system path, and the test flip-flop is configured to have a reduced hold time margin by a delay clock signal.

The disclosed invention is directed generally to synchronous digital circuit performance monitoring circuits, and more particularly to circuits for monitoring speed performance degradation in synchronous digital integrated circuits.
During the lifetime of a digital integrated circuit, its speed performance varies due to changing environmental conditions and aging. Speed of operation (i.e., clocking rate) of digital integrated circuits is typically based on worst case design parameters whereby a digital integrated circuit is clocked at a rate that will provide proper operation at the worst case condition. If a digital integrated circuit should operate outside its worst case design point, the system in which it operates will fail.
There are basically two types of speed failures: set-up failure which occurs when the input data to a flip-flop is not stable for a predetermined amount of time prior to the active clock transition, and hold time failure which occurs when the input data to a flip-flop is not stable for a predetermined amount of time after the active clock transition.
Presently, proper speed operation of synchronous digital integrated circuits can be verified by running tests. Set-up time margins can be evaluated by increasing clock frequency to set-up failure, and then comparing that frequency to the desired operating frequencies. However, set-up margin cannot be evaluated during actual in-system operation. Hold-time margin cannot be measured at all, since hold time margin is independent of clock frequency, and any test as to hold time can only provide a pass/fail indication.
It would be desirable to not only test for speed, but also to assure that finite speed margins exist in a design. Speed margins are an extra increment of speed performance in devices over what is used in system. For example, sufficient set up margin might be designed so that the digital integrated circuits could clock 10% faster than the system clock rate; sufficient hold time margin might be designed so that data would be held at flip-flop inputs 10% longer than required. The use of margins is sound design practice that assures reliable operation over the lifetime of a digital system.

Method for continuously measuring delay margins in digital systems


A multi-band antenna, made by an integral plate and comprises a radiating element, a grounding element, a slit formed as part of the plate, and a feeding line; wherein horizontal conductive portion of said plate are separated from each other with said slit between them and serve as the radiating element and the ground element respectively; the feeding line, comprising an inner conductor connected with the radiating element and an outer conductor connected with the grounding element; wherein said radiating element comprising at least two radiating portions defining at least one radiating arm with gradually increasing width, and at least two radiating portion cooperatively acting to achieve a Ultra Wide Band antenna.

1. Field of the Invention
The present invention relates generally to a multi-band antenna, and more particularly to a Ultra Wide Band antenna (UWB) used for electronic devices, such as notebooks.
2. Description of the Prior Art
At present, the Bluetooth and the IEEE802.11a/g are two of main wire network technologies. However, both the two wire network technologies have disadvantage that transmitting rate of signals fall down with the increase of transmitting distance. A new technology, Ultra Wide Band (UWB) interknit technology, is used in short-haul signal high-speed transmission and signal low-speed transmission among over 100 m even to 1 km distance. The system in electronic device sends low-intensity and narrow pulse signal but not carrier signal to achieve high quality and high-speed transfer. For this reason, this signal transmission has strong anti-jamming capability, and smaller loss of power and electric. Besides, UWB has a big advantage of big capacity to transmit more data. In Feb. 14, 2002, FCC in USA allowed UWB interknit technology used on consumer electrical products. To achieve Ultra Wide Band transmission, an UWB antenna is designed. The band width of the antenna lies on the impedance matching degree, so the UWB antennas need higher requirement of impedance. In current technique, most of UWB antennas are monopole antennas or dipole antennas. However, present electric devices require small-size, so smaller antenna therein is needed. Plane inverted F antennas, a kind of antennas with small size, are used more and more. U.S. Pat. No. 7,042,414 discloses an UWB antenna with small size as shown by FIG. 1 with label of this patent. The antenna comprises two different radiating elements working on two bands having across frequency band to achieve Ultra Wide band. The first radiating element 31 of the antenna is a plate with a cutout in the middle of itself, and the second radiating element 32 is made by a kind of material different from that of the first radiating element. The second radiating element 32 is located in the cutout of the first radiating element 31, and separated from the first radiating element 31. The UWB antenna has better radiation properties, but the radiating elements of the antenna and the grounding element are divided into two parts which are not connected with each other. So the radiating elements and the grounding element must be fastened through a PCB, thus, the structure of the antenna is complex. U.S. Pat. No. 5,828,340 discloses a wide band antenna as shown by its FIG. 1 with label. The wide band antenna comprises a plate 10 with a cone shape angle 20 and being located on the substrate 4, a grounding element 14 and a feeding line 12. The wide band antenna 2 is able to achieve frequencies lower or higher than the center frequency 40%. However, the radiating element of the wide band antenna is made of an integral planar plate 10 resulted in the volume of the antenna is big.
Hence, an improved antenna is desired to overcome the above-mentioned shortcomings of the existing antennas.