An image display device having improved image retention capability by analyzing the mechanism behind the creation of an unwanted electric field applied to an element after a power supply is turned off, and devising a drive method and so forth for compensating for the same, is provided. Electrophoretic particles contain three types of charged particles, C (cyan), M (magenta), and Y (yellow) that are mutually different in color and threshold voltage for starting electrophoresis. When the threshold voltages of C (cyan), M (magenta) and Y (yellow) are respectively Vth3, Vth2, and Vth3, these satisfy the relationship |Vth3|<|Vth2|<|Vth1|. Further, a voltage application unit applies a voltage (VE) different from a reference potential during the final period of image update period. The voltage (VE) is a compensation voltage that suppresses the movement of charged particles.

As a display device with which an act of "reading" can be done without feeling stress, electronic paper display devices called electronic books, electronic newspapers, and the like are being developed. This kind of electronic paper display device is required to be thin, light, hard to be smashed, and low in power consumption. Thus, it is preferable to be formed with a display element with a memory. As a display element used for a display device with a memory, an electrophoretic display element, a cholesteric liquid crystal, and the like are known. Recently, an electrophoretic display element using two or more kinds of charged particles has drawn an attention.
A monochrome display active matrix drive type electrophoretic display device will be described. This electrophoretic display device is constituted by stacking a TFT glass substrate, an electrophoretic display element film, and a counter substrate in this order. TFTs (Thin Film Transistors) that are a great number of switching elements arranged in matrix, pixel electrodes, gate lines, and data lines connected to each of the TFTs are provided on the TFT glass substrate. The electrophoretic display element film is formed by spreading microcapsules of about 40 μm all over in a polymer binder. A solvent is injected inside the microcapsules. In the solvent, two kinds of nanoparticles charged plus and minus, i.e., a white pigment such as oxide titanium particles charged minus and a black pigment such as carbon particles charged plus, are sealed in a dispersedly floated manner. Further, as the counter electrode, a counter electrode giving a reference potential is formed.
The electrophoretic display device operates by moving the white pigment and the black pigment vertically through applying a voltage corresponding to pixel data between a pixel electrode and a counter electrode. That is, when a plus voltage is applied to the pixel electrode, the white pigment charged minus is gathered to the pixel electrode while the black pigment charged plus is gathered to the counter electrode. Thus, provided that the counter electrode side is the display face, black is displayed on the screen (all the examples provided hereinafter will be described while assuming that the counter electrode side is the display face). In the meantime, when a minus voltage is applied to the pixel electrode, the black pigment charged plus is gathered to the pixel electrode while the white pigment charged minus is gathered to the counter electrode. Therefore, white is displayed on the screen.
That is, a plus signal voltage is applied to the pixel electrode when switching the image from white display to black display, a minus signal voltage is applied to the pixel electrode when switching from black display to white display, and 0 (V) is applied when maintaining the current image, i.e., when switching display from white display to white display and from black display to black display. As described, the electrophoretic display device has a memory, so that the signal to be applied is determined by comparing the current image (previous screen) with the next image (updated screen).
While the monochrome display microcapsule type electrophoretic display device has been described above, electrophoretic display devices capable of providing color display without losing a monochrome excellent display performance of the electrophoretic display device close to paper have been developed recently. These devices provide monochrome and color displays by displaying colors of uncharged particles and colors of each of charged particles by using uncharged (or weak charged) particles having no sensitivity in the electric fields and a plurality of particles of same polarity or inverse polarities having sensitivity in the electric field in a solvent (see Patent Documents 1 and 2).
For example, the color electrophoretic display device described in Patent Document 1 is constituted with: a pair of substrates; a solvent sealed in the gap between the pair of substrates; and three different colors (e.g., cyan C, magenta M, and yellow Y) of electrophoretic particles charged plus or minus as well as uncharged white particles (W) contained in the solvent. The threshold voltages of the three different colors of electrophoretic particles when starting migration are different from each other. Thus, it is possible with a single cell to display not only white (W) and black (K) but also cyan (C), magenta (M), yellow (Y) as well as secondary colors and tertiary colors of CMY through applying a voltage by using the difference in each of the threshold voltages.
A driving method for providing color display by using the difference in the threshold voltages through placing the charged particles C, M, Y and the white particles W on the same pixel electrode will be described by referring to FIG. 18. Hereinafter, the threshold voltages of the charged particles C, M, and Y are defined as Vth(c), Vth(m), and Vth(y) and assumed to be in a relation of |Vth(c)|<|Vth(m)|<Vth(y). Further, the applied voltages V1, V2, and V3 are assumed to satisfy relations of |Vth(c)|<|V3|<|Vth(m)|, |Vth(m)|<|V2|<|Vth(y)|, and |Vth(y)|<|V1|.
FIG. 18 is a hysteresis loop of the charged particles C, M, and Y, which shows the relation between the applied voltage (threshold voltage) and the relative color density. In this chart, for simplifying the explanation, the moving time in which the charged particles Y, M, and C migrate from the back face to the display face is set to be different time from each other so that the slopes of each hysteresis Y, nY, M, nM, C, and nC become constant. For example, when the material design of the charged particles is done in such a manner that the drive voltage at least satisfies the demand for low power consumption, the voltages are |Vth(c)|≈7 (V), |Vth(m)|≈12 (V), |Vth(y)|≈28 (V), and the drive voltages are required to be set as |V3|=10 (V), |V2|=15 (V), and |V1|=30 (V).
In FIG. 18, the first (previous) screen is defined as white (W). When a voltage +V3 is applied, the electrophoretic particles of cyan (C) migrate to the display face side, so that cyan is displayed. When a voltage +V2 is applied, the electrophoretic particles of cyan (C) and magenta (M) migrate to the display face side, so that blue (B) is displayed. When a voltage +V1 is applied, the electrophoretic particles of cyan (C), magenta (M), and yellow (Y) migrate to the display face side, so that black (K) is displayed. Further, when the previous screen is white (W) and a minus voltage is applied, no color particle is on the display face side so that the screen remains as white (W).
In the meantime, when the previous screen is black (K) and a voltage −V3 is applied, the electrophoretic particles of cyan (C) migrate to the back face substrate side and the electrophoretic particles of magenta (M) and yellow (Y) remain on the display face side so that red (R) is displayed. When the previous screen is black (K) and a voltage −V2 is applied, the electrophoretic particles of cyan (C) and magenta (M) migrate to the back face substrate side and the electrophoretic particles of yellow (Y) remain on the display face side so that yellow (Y) is displayed. When the previous screen is black (K) and a voltage −V1 is applied, all the electrophoretic particles of cyan (C), magenta (M), and yellow (Y) migrate to the back face substrate side so that white (W) is displayed. Further, for displaying magenta (M), a voltage +V2 is applied and the displayed color is changed once from white (W) display to blue (B). Then, a voltage −V3 is applied to move the electrophoretic particles of cyan (C) to the back face so as to display magenta (M).
This operation can be expressed as follows. Assuming that the color density of the charged particles C in each pixel constituting a next screen to be updated is Rc, the color density of the charged particles M is Rm, and the color density of the charged particles Y is Ry, applied is a drive waveform that is constituted with:
a reset period where a reset voltage is applied to reset to a white or black base state;
a first voltage applying period where a first voltage V1 (or −V1) or/and 0 (V) voltage is applied to transit the base state into a first intermediate transition state where the color density of the charged particles C, M, and Y become Ry;
a second voltage applying period where a second voltage V2 (or −V2) or/and 0 (V) voltage is applied to transit the first intermediate transition state into a second intermediate transition state where the color density of the charged particles C and M become Rm while maintaining the color density of the charged particles Y as Ry; anda third voltage applying period where a third voltage V3 (or −V3) or/and 0 (V) voltage is applied to transit the base state into a third intermediate transition state where the color density of the charged particles C become Rc while maintaining the color density of the charged particles M and Y as Rm and Ry.
Methods for controlling particles that are not able to migrate or particles migrate again from the fixed positions in a typical electrophoretic display device are disclosed in Patent Documents 4 and 5.
Patent Document 4 describes a method which applies a first data input pulse or a second data input pulse whose data width is narrower or data strength is smaller than that of the first data input pulse in an image rewrite period in an electrophoretic display element of two-particle type with different polarities. As described, disclosed is a technique which improves the image quality through applying a prescribed voltage to the electrophoretic particles for the time required to migrate a prescribed distance between the electrodes and then applying a pulse for a shorter time or of a lower voltage than that between the electrodes to move the particles that were not able to migrate, the particles re-migrated from the fixed positions, and the like to the fixed position again.
Further, Patent Document 5 discloses a means for improving the screen retention capability (memory) through adding additional signals whose voltage changes gradually to the base potential after applying signals for displaying images on a display unit so as to suppress migration of the charged particles in the electrophoretic display element of two-particle type with different polarities. The above is done to apply an additional correction pulse for increasing the retention capability of the screen.
Patent Document 6 mentions that re-migration of the charged particles occurred during the transition from a screen update period to a retention period is caused due to an electric field by feed-through (to be described later). All the active matrix displays are subjected to an action called feed-through with which the voltage reaching the pixel electrodes changes from a corresponding data voltage input by a certain extent (normally 0.5 to 2.0 (V)). The feed-through effect is generated from scanning of the gate lines via a coupling electric circuit net between the gate lines which scan TFT and the pixel electrodes. That is, described in Patent Document 6 is as follows. The voltage actually applied to the pixel electrodes is shifted in a minus direction from the data voltage written to the pixel electrodes for the feed-through at the time of scanning Normally, for corresponding to the feed-through, the counter electrode is offset to the minus side from the reference potential (normally, ground GND) by a specific extent. Further, when scanning is stopped, there is an offset generated between the pixel electrodes and the counter electrode for the amount of the feed-through voltage.
As a countermeasure thereof, disclosed in Patent Document 6 is not to apply an unnecessary DC offset voltage through stopping scanning by fixing the scanning lines to a gate-off voltage and instantly switching the counter electrode voltage to GND from the feed-through voltage −Vfd by an analog switch in a non-wiring mode between a writing mode and power-off (retention).
Further, as the known technique described in Patent Document 7 and also employed in Patent Documents 5, 6, generally known is a technique with which the input pulse before turning off the power terminates at 0 (V). However, migration of the charged particles occurs also when the power is turned off from a screen update period where the display device is driven and an unnecessary electric field is applied to the elements. As will be described later in details, it is not possible to deal with such case with an additional correction pulse even if a correction pulse that terminates at 0 (V) is applied. Further, a mechanism with which the charged particles migrate when the power is turned off has not been analyzed. Furthermore, a waveform to be employed when multi-particles of different threshold values of Patent Documents 1 and 2 is not specifically disclosed therein.    Patent Document 1: Japanese Patent No. 4049202    Patent Document 2: Japanese Patent No. 4385438    Patent Document 3: Japanese Patent No. 4269605    Patent Document 4: Japanese Unexamined Patent Publication 2007-316594    Patent Document 5: Japanese Patent No. 4811510    Patent Document 6: Japanese Patent No. 4806634    Patent Document 7: Japanese Unexamined Patent Publication 2005-326883    Patent Document 8: Japanese Unexamined Patent Publication 2010-210806    Patent Document 9: Japanese Unexamined Patent Publication 2010-210660
There are following issues with the related techniques described above.
With the color electrophoretic display elements depicted in Patent Documents 1 and 2, the electric field sensitivity of the charged particles (C in the above-described case) with the lowest threshold voltage is extremely high so that the migration occurs even with the extent of about Vth(C)≈1 (V). Thus, after the screen update driving period (from a reset period to a third voltage applying period) ends and a voltage is continuously applied during a period from the point where the power supply voltage that is applied for driving the panel is turned off to a retention period, the charged particles migrated to the display face or the opposite face thereof leave from the substrate after update of the screen and mixed with W particles that are uncharged particles. Thereby, the colors may become unclear and variations in the color density are generated between pixels and recognized as unevenness, which result in deteriorating the display quality. Therefore, with the color electrophoretic display devices, it is necessary to control the layout of the charged particles after the screen update period.
In other words, when the power supplied for driving the panel is turned off with this driving method in the color electrophoretic display element using the charged particles which are mutually different in colors and threshold voltage for starting electrophoresis disclosed in Patent Documents 1 and 2, a weak voltage is continuously applied to the element by a difference in the discharge speeds between the pixel electrode voltage and the counter electrode voltage (to be described later). Thus, the large charged particles with the lowest threshold voltage migrate and the particles disposed once on the display face or the opposite face thereof leave from the substrate, so that there is an issue of deterioration in the retention capability (memory) with which the display image becomes unclear.
The techniques of Patent Documents 4 and 5 apply an additional correction pulse for improving the retention capability of the screen. However, migration of the charged particles occurs also when the power is turned off from a screen update period where the display device is driven and an unnecessary electric field is applied to the elements so that it is not possible to deal with such case with the additional correction pulse. Further, a mechanism with which the charged particles migrate when the power is turned off has not been analyzed. Furthermore, a waveform to be employed when multiple particles of different threshold values of Patent Documents 1 and 2 is not specifically disclosed therein.
In other words, while Patent Documents 4 and 5 disclose a technique for improving the retention capability of the screen by applying an additional correction pulse, the correction pulse is terminated at 0 (V) in the final sub-frame so that the unnecessary electric field applied to the element after the power is turned off cannot be eliminated. Therefore, the issue cannot be overcome substantially.
With the technique of Patent Document 6, it is not possible to perfectly follow the signal source even if the counter electrode voltage is changed instantly since the counter electrode is connected to the signal source via transfer resistance or sheet resistance of ITO (Indium Tin Oxide). Further, the pixel electrode is connected to the data line not via floating but via leak resistance of TFT, so that the pixel electrode voltage does not perfectly follow the change in the counter electrode voltage. Thus, the transit voltage of the counter electrode voltage and the transit voltage of the pixel electrode at the time of switching are different, and the DC offset generated due to the voltage difference cannot be eliminated completely. In particular, cyan particles (C) whose threshold voltage is small and the charged amount is large are to re-migrate because of the DC offset.
It is therefore an object of the present invention to overcome the above-described issues and to provide an image display device whose screen retention capability is improved by analyzing the mechanism with which the unnecessary electric field applied to the element after the power is turned off is generated and by devising the driving method and the like for enabling compensation thereof.


In some embodiments, a comparator compares an incoming memory address with a memory address currently being copied by a memory copy operation. A holding buffer holds the incoming address prior to forwarding it to a memory read/write queue if the incoming memory address is the same as the memory address currently being copied by the memory copy operation, forwards the buffered incoming memory address to the read/write queue once the memory copy operation for the memory address currently being copied has finished. Other embodiments are described and claimed.

Memory Reliability Availability and Serviceability (Memory RAS) features can include features such as memory mirroring, memory sparing, memory RAID (Redundant Array of Independent Disks), etc. Memory RAS features are increasingly becoming more important in various computer related market segments such as server market segments, including low end server market segments. Memory RAS features help server application availability by providing mechanisms to recover and/or reconstruct memory data without bringing the system down in cases where erroneous data is supplied by the memory devices. Such memory RAS features need to be enabled in server platforms without severely impacting the performance of the system.
In memory RAS flows such as memory sparing, memory mirroring, memory hot plug, etc. there is a need to copy memory data from one memory device such as a Dual In-Line Memory Module (DIMM) to another spare memory device such as a DIMM without interfering with regular memory accesses. Such RAS memory operations (flows) occur at the same time as regular memory accesses. Using software copy schemes can reduce the cost of implementing the memory RAS flows, but the copy process itself must be atomic in order to guarantee data integrity. As is known in the art, the atomicity of a process means that the process must complete without any interruptions. This means that during an atomic copy process the read from one device and the write to the spare device must happen without any interruptions.
One way to ensure the atomicity of a software copy process is to use software locking/fencing operations. However, there are problems with using such operations. For example, locking/fencing operations are not applicable to all memory regions such as the Write Combine (WC) memory region. When copying data from such a region a memory access to the same address can occur between the read/write operations and potentially corrupt the data. Therefore, it would be beneficial to synchronize the copy process with other memory accesses, particularly in a system with a point-to-point (unordered) interconnect.

Synchronizing memory copy operations with memory accesses


A request-to-exit (REX) switch comprises an injection-molded plastic body that can snap into the access hole of a mortise lock mechanism to provide a request-to-exit contact generation. A micro-switch mounts to a distal end of the injection-molded plastic body. Such is precisely oriented, positioned, and secured by pressing onto two posts molded into the distal end. The installation is accomplished without tools, and two snap locking tabs in the injection-molded plastic body automatically secure to the access hole of the mortise lock mechanism. An orienting lip on a front cap of the injection-molded plastic body allows only one possible fit. A strain relief for wiring to the micro-switch is a part of the injection-molded plastic body.

1. Field of the Invention
The present invention relates to door lock hardware, and in particular to snap-in request-to-exit switches that can be installed in electrified lock sets and other door latch mechanisms in the field.
2. Description of the Prior Art
Some security doors are normally kept locked and a card access or keypad system is required to gain entry. An electromechanical device in the door is energized at the presentation of a valid card, key fob, or entry code, and the door lock is temporarily released. During this time, the electromechanical device can be heard to buzz or click and most people know that such security doors can then be pushed or pulled open.
Sometimes the alarm system will have to be signaled to call attention to the fact a user wants to go through a locked security door from the inside out, or in an egress situation. So, request-to-exit switches have been installed in special models by the lock manufacturers. These can sense when a user turns a door knob wanting to egress, thereby shunting, or stopping an alarm from sounding, since there is no perceived threat to the system integrity for an authorized, or requested exit.
Special orders are required for these models of door locks, and the costs are significant. Installers must either order a supply of specially equipped locks, or return the originals for retrofitting, or install difficult and complex field switches which require lock disassembly and/or modification. Either way can be expensive and time consuming.
So what is needed is an easy-to-install switch that can be added in later to only those electrified locks that actually require a request-to-exit function. The switch should be simple and easy to install correctly, and it should function properly without needing adjustments. An economic construction should be used so that keeping inventories of a variety of switches for a variety of matching electrified locks is practical and affordable by the average installer.


The present invention relates to a treatment device using a magnetic field, which includes a coil generating a pulse magnetic field and a cooling unit.

In general, a treatment device using a magnetic field induces a magnetic field by applying a pulse-type current and stimulates an affected area by inducing a current caused by the generated magnetic field into a human tissue. The treatment device using a magnetic field includes a coil generating a magnetic field by using a current applied from a main body and generates a magnetic field having a desired intensity by applying a current of several thousands amperes for a short time (50 μs to 300 μs).
Heat is inevitably generated when a current flows through the coil, and the heat increases an internal resistance of the coil and an inductance of the coil. Thus, a typical treatment device using a magnetic field essentially includes a cooling unit capable of cooling the coil.
The cooling unit uses various methods including a water-cooling method using water, an air-cooling method that discharges heat by using a heat dissipation plate, etc., and then cools the discharged heat through a fan, etc., and an oil-cooling method that allows an oil to pass around the coil and then cools the heat absorbed oil.
The typically used water-cooling method is easily maintained and has a cooling efficiency greater than that of each of the air-cooling method and the oil-cooling method. However, the water-cooling method has a limitation of a low cooling efficiency because cooling water may not directly contact the coil through which a high-voltage current flows but indirectly flows around the coil to cool the coil. Also, the water-cooling method has a limitation in that since a risk of leakage and external case damage exists, a complete insulation process is required.
On the other hand, the typically used air-cooling method has a limitation of a lower cooling efficiency, and the oil-cooling method has a limitation of a low cooling efficiency because a high risk of leakage exists, and an oil has a property of slowly heated and slowly cooled. Also, although some treatment devices adopt a compressor or radiator method as the cooling unit, the compressor or radiator method has a great limitation of vibrations and noises and may not exactly control a temperature.

Abstract: The treatment device using a magnetic field in accordance with an embodiment of the present invention includes: a magnetic field generating coil disposed below a contact surface that closely contacts a portion of a body; a cooling unit configured to supply a fluid that cools the magnetic field generating coil; and a duct configured to guide the fluid between the cooling unit and the magnetic field generating coil. Here, the cooling unit is disposed below the magnetic field generating coil and disposed so that an angle between a fluid supply direction from the cooling unit and a central axis of the magnetic field generating coil is equal to or less than the right angle.


A method, system, and computer program product for system-wide power conservation using memory cache are provided. A memory access request is received at a location in a memory architecture where processing the memory access request has to use a last level of cache before reaching a memory device holding a requested data. Using a memory controller, the memory access request is caused to wait, omitting adding the memory access request to a queue of existing memory access requests accepted for processing using the last level of cache. All the existing memory access requests in the queue are processed using the last level of cache. The last level of cache is purged to the memory device. The memory access request is processed using an alternative path to the memory device that avoids the last level of cache. A cache device used as the last level of cache is powered down.

1. Technical Field
The present invention relates generally to a method, system, and computer program product for managing the use of electrical power in a data processing environment. More particularly, the present invention relates to a method, system, and computer program product for system-wide power conservation using memory cache.
2. Description of the Related Art
Memory in a data processing system includes one or more solid-state memory devices, such as a Dual Inline Memory Module (DIMM). Not only the processors or processing cores, but also many other components and subsystems in the data processing system need access to the memory.
Access to the memory in a direct way is slower than acceptable in most cases. A cache memory (cache) is a faster but smaller memory device used for speeding up access to the most used or recently used data from the memory.
Various types of caches are presently in use. A particular type of cache is configured and located in a certain way depending on the nature of the use expected from that cache. For example, certain caches, such as level-1 (L1), level-2 (L2), and level-3 (L3) caches known as CPU-caches, and are used by processors for reading and writing data during instruction execution. L1, L2, and L3 caches are fast but small memory devices, typically formed on the same chip as the processor core for fast operation in close proximity to the processor.
Other levels of caches are not exclusively for use by the processor only. For example, a level-4 (L4) cache is a cache that is accessible to any subsystem in a data processing system, and any subsystem can read or write the memory via L4 cache. As with other caches, L4 cache includes faster devices but of smaller capacity as compared to the memory, and expedites access to recently used or frequently used data in the memory. As an example, a networking subsystem, e.g., comprising a network adapter, or an input/output (I/O) subsystem, e.g., comprising an I/O controller, or a partition management subsystem, e.g., in a multi-partitioned data processing system, can each access the memory via an L4 cache in a given configuration.
Electronic components, including memory devices used for main memory or cache memory, consume electrical power. A system-wide power saving condition is a condition that indicates that the power consumption of the data processing system as a whole has to be reduced.

System-wide power conservation using memory cache

INTERNATIONAL BUSINESS MACHINES CORPORATION


A chip package includes a flat plate body or carrier with a plurality of leads embedded therein but exposed at the first and second surfaces, e.g., the top and bottom surfaces, of the plate body. The body has a predetermined shape and may include a recess formed in the upper surface of the body to a prescribed depth. A semiconductor chip is mounted on the upper surface of the plate body or carrier. Metallic bonding wires electrically connect the leads of the body with the bonding pads of the chip, and an epoxy molding compound seals a predetermined portion including the chip, the leads, and the metallic wires. A plurality of like chip packages may be vertically stacked. Instead of epoxy molding, a thin lid having leads similarly embedded therein may be attached to the upper surface of the body.

FIG. 1 shows a cross-sectional view of a Quad Flat Package, in which a semiconductor chip 3 is mounted on a paddle 2 of a lead frame 1. The chip 3 is electrically connected to inner leads 1a of the lead frame 1 by bonding wires 4, and the entire whole body 5 except for outer leads 1b is encapsulated by an epoxy molding compound.
The Quad Flat Package is disadvantageous since precise alignment of the outer leads 1b onto the bonding pads of a printed circuit board (PCB) is difficult. Further, the outer leads 16 may be damaged or deformed due to external impacts during the lead-forming process in which the outer leads 16 are bent into prescribed shapes. The repairing of the chip package defects when mounted on a PCB has been troublesome, and simplification of the process, as well as the increase in the number of package pins, has suffered limitation.

Chip carrier with embedded leads and chip package using same


Methods and apparatus for prioritizing network selection for overlapping networks. Overlapping networks include multiple networks with, for instance, different bandwidth limitations. For example, a Wi-Fi Access Point (AP) can broadcast two (2) overlapping networks in the same location: (i) a public network, and (ii) a private network. In one exemplary embodiment, a Wi-Fi client device performs fast scans to quickly locate one or more preferred networks (e.g., the last connected to public network). If the located preferred network is also identified as an overlapping network (e.g., based on location information, etc.), then the client device performs a comprehensive scan to identify all available networks, and applies a prioritization scheme to determine the highest priority network available (e.g., a private network).

1. Field of Use
The present disclosure relates generally to the field of network selection within wireless networks. More particularly, in one exemplary embodiment, the present disclosure is directed to schemes for selecting and/or prioritizing one network from a number of available networks.
2. Description of Related Technology
Data and communications networks are of increasing importance in modern society. Particularly important are wireless networks, which are characterized generally by: (i) one or more access points or base stations, and (ii) a plurality of users with wireless-enabled devices that can communicate with the access points or base stations.
One wireless network technology of particular interest and ubiquity is so-called "Wi-Fi™" technology. Wi-Fi™ (also "Wifi" or "WiFi") is a wireless local area network (WLAN) technology based on the Institute of Electrical and Electronics Engineers' (IEEE) 802.11 standards. As used herein, the terms "Wi-Fi", "Wifi" and "802.11" refer without limitation to IEEE Stds. 802.11a,b,g,n,s,u,v and/or 802.11-2012. Wi-Fi devices can exchange data over a wireless connection to other Wi-Fi devices (ad hoc peer-to-peer networks), or alternately to a Wi-Fi Access Point (AP) which may connect to an Internet Protocol (IP) Gateway (to access the Internet or other networked devices). They may also be part of so-called "mesh networks" such as those described in 802.11s/u. Generally, a Wi-Fi AP provides a so-called "hotspot" of coverage; hotspots can vary in size greatly e.g., from very localized (e.g., within a residential address, or small business) to multiple square miles (e.g., by coordinating multiple overlapping APs).
Recently, several Network Internet Service Providers (ISPs) have initiated new networking infrastructure models which enable subscribers the option to share their home Wi-Fi hotspot, in exchange for reciprocal coverage outside their home. Existing solutions require that a participating subscriber's home AP will broadcast two (2) overlapping networks in the same location; i.e., (i) a public network, and (ii) a private network. The public network is characterized by a public/open security protocol controlled by the ISP, and a relatively low bandwidth capability. The private network provides a secure, higher bandwidth home network that is administered by the subscriber (or proxy administrator). Ideally, any other "roaming" subscriber can receive roaming access via the public network portion of the participating subscriber's home AP. However, due to bandwidth limitations on the roaming subscriber's use, the participating home network subscriber is minimally impacted.
Existing network selection techniques are not optimized for overlapping network operation such as that of the exemplary 802.11 context discussed above. Specifically, existing network selection techniques are based on minimizing network search time, and are unsuitable for handling the various complexities introduced by overlapping network operation. Accordingly, improved methods and apparatus for selection of, and operation within, such overlapping networks are needed.

Methods and apparatus for network selection in overlapping network environments


The present invention aims at providing a diagonal flow fan or a silencer for the diagonal flow fan, which have the same outer shape as a suction port and are compact, and can also obtain an effective sound absorbing effect of a moderate frequency range. In the diagonal flow fan comprising a diagonal flow impeller 1 disposed with a blade 1a so as to obliquely send an air to an axis of rotation 21, a fan casing 2 for covering this diagonal flow impeller 1, and a suction port 3 for sucking the fluid in the direction to the axis of rotation of this fan casing 2, the open front side of the suction port 3 is provided with a silencing portion comprising a shield 4 and a punching metal 5, so that the noise of the moderate frequency range of 500 to 1000 Hz generated in the diagonal flow fan was suppressed.

(1) Field of the Invention
The present invention relates to a diagonal flow fan.
(2) Description of Related Art
Heretofore, various methods for reducing the noise of the fans have been proposed, and for example, there are some fans disclosed in Patent Document 1 (JP-A-11-201099) and Patent Document 2 (JP-A-2001-115821). Any of these fans is configured to reduce the noise by a silencer. The Patent Document 1 discloses a fan having a sound absorbing structure on the upper stream side of the fan for diminishing the noise and sucking not from an axial direction but from a radial direction. The Patent Document 2 discloses an air blower having a cylindrical main body configured to suck from a radial direction, in which noise absorbing part bodies are disposed in the suction port directly opposite one another retaining predetermined spacing.
In general, a diagonal flow fan is characterized in that, comparing with a centrifugal fan, the air pressure is low and the quantity is much, and comparing with an axial flow fan, the air pressure is high and the quantity is little, whereas the diagonal flow fan targeted by the present invention is designed such that a specific speed Ns in the vicinity of the best efficiency point defined by the following formula (1) is 800 to 1400.Specific speed Ns=N×Q0.5×H−0.75  Formula (1)                N: number of revolutions (min−1)        Q: quantity (m3/min)        H: head (m)=pressure/acceleration of gravity g/γ        γ: fluid density
This is a dimensionless quantity issuing a guide line for designing whether it is the pressure type or the quantity type when the standard state of the air is 1.2 kg/m3 and the specific speed Ns is considered based on the outer diameter of the same impeller, and shows that the higher the specific speed Ns is, the more the quantity is. Hence, a flow noise of the flow becomes a main component in the noise of the diagonal flow fan. That is, when a frequency analysis is conducted, the component of frequency of 500 to 1000 Hz (hereinafter, this frequency range is referred to as moderate frequency range) becomes loud. One example of the noise characteristic of the diagonal flow fan in which the specific speed Ns is 1000 is shown in FIG. 4.
In the technique disclosed in the Patent Document 1, when the silencer is configured to suck from a radial direction, a fan casing rather than a suction port becomes larger in the centrifugal fan, which is required to provide a scroll or a fluid recovery flow channel around the impeller. Consequently, though the entire configuration does not become large by the configuration itself of the silencer, in the case of the diagonal flow fan, since the suction port and the fan casing have approximately the same size in outer shape, there has been a problem that the outer shape of the entire fan becomes large due to the configuration of the silencer.
In the Patent Document 1, sound absorption of the noise depends on the characteristic and the surface area of a sound absorbing material as well as the shape such as a thickness. The sound absorbing characteristic of the sound absorbing material can obtain high sound absorption coefficient in the high frequency of or above 1000 Hz, whereas in the case of a fan having specific speed Ns of 800 to 1400 such as the diagonal flow fan, rather than the noise of the high frequency range, the noise of the moderate frequency range is liable to be generated, and there has been a problem that the noise is not sufficiently absorbed.
That is, in the diagonal flow fan, since a pressure interfered sound with the fan casing is low in noise characteristic, the noise of the moderate frequency range of 500 to 1000 Hz generated by the turbulence of the flow at the suction time becomes loud, and there has been a problem that the noise in this moderate frequency range is required to be reduced.
Similarly in the technique disclosed in the Patent Document 2, though the silencer is configured to suck from the radial direction, it is configured to depend on the sound absorbing material similarly to the Patent Document 1. That is, the air blower of the Patent Document 2 is not the diagonal flow fan, and for this reason, it is different in the noise characteristic, and does not give consideration to the noise of the moderate frequency range.

Hitachi Industrial Equipment Systems Co., Ltd.


An electrode structure is located at least partially in a via opening having a small feature size and containing a fuse element which is composed of a fuse element-containing seed layer that is subjected to a reflow anneal. The electrode structure is composed of a material having a higher electromigration (EM) resistance than the material that provides the fuse element. Prior to programming, the fuse element is present along sidewalls and a bottom wall of the electrode structure. After programming, a void is formed in the fuse element along at least one sidewall of the electrode structure and the resistance of the device will increase sharply.

The present application relates to back-end-of-the-line (BEOL) electrical fuses (eFuses) and a method of forming the same.
eFuses are used in semiconductor industry to implement array redundancy, field programmable arrays, analog component trimming circuits and even as chip identification circuits. Dog-bone shaped eFuses containing a fuse link are known. In such conventional dog-bone shaped eFuses, the fuse link dimension is limited by the allowable photolithographic minimal dimensions.
While eFuses are thus desirable within semiconductor device design and fabrication and provide an essential tool for cost effective and efficient semiconductor device design and fabrication, eFuses are not entirely without problems. For example, programming of prior art eFuses typically takes a substantial amount of current, which is undesirable in current technology node devices using low driving current. In addition, programming transistors takes up space in a semiconductor chip as well as power consumption.
There is a need to provide BEOL eFuses in which the fuse link is much smaller than conventional photolithographic minimum dimensions and thus the amount of electrical current that is needed to blow the eFuse can be substantially reduced as compared to a conventional eFuse design.

International Business Machines Corporation


A portable generator set (1) comprises an engine (6), a generator (7), a fuel tank (8), and a housing (5). The engine (6), the generator (7), and the fuel tank (8) are accommodated in the housing (5). The fuel tank (8) is constructed by a fuel tank housing (805), a fuel tank port (801), a fuel tank cap (802), and a fuel tank top surface (808). A protrusion structure protruding outward is provided on the fuel tank top surface (808). A hollow cavity (809) communicated with the inner cavity of the fuel tank (8) is formed on the inner side of the protrusion structure, such that fuel in the fuel tank (8) can enter the hollow cavity (809) when the generator set (1) is obliquely reclined. The generator set can be obliquely reclined, thereby improving security and facilitating transportation and storage of the generator set.

A generator set mainly includes an engine, a generator and an electronic control system, and can convert chemical energy of fuel into electrical energy. Accordingly, the generator set is used in many applications, such as field work, emergency power supply, disaster rescue, outdoor life and travel, self-contained power supply for yachts and vehicles, mobile communication base station or other applications.
Compared with a traditional power frequency synchronous generator set, an inverter generator set equipped with a multi-pole permanent magnet generator has advantages of high efficiency, small size and light weight. The weight and size of such inverter generator set is about 50% of those of the traditional generator set. Therefore, it is a generator set by which a "portable" generator set can be really achieved.
However, an inverter generator set with a power of 2 kw generally has a weight of more than 20 kg, which still leads to inconvenience in transportation and carrying. As shown in FIG. 1a, according to an existing solution, a rotary pull rod 202 is arranged at the front side of a generator set 2, and wheels 201 are arranged at the bottom of the rear side of the generator set 2 in the transverse direction of the generator set. When the generator set 2 needs to be transported, the rotary pull rod 202 can be rotated upward to a highest position, and an operator can hold the handle to lift the front of the generator set to recline the generator set rearward and pull forward the generator set 2. However, many drawbacks exist in such design. When the operator lifts the front of the generator set 2 and pull forward it, since the generator set 2 is reclined rearward (opposite to advancing direction), the portion below the front of the generator set is very close to the feet and legs of the operator, and is easy to bump into, even hurt in severe case, the operator, which greatly hinders the operator to pull the generator set quickly. Furthermore, the opening and retracting of the rotary pull rod 202 is complex, which leads to inconvenience in operation and low efficiency. On the other hand, during pulling the generator set 2, the operator has to always apply an upward force to overcome the weight of the generator set in order to lift the front of the generator set. Since the length L of the generator 2 is larger (than the width W), the distance in the horizontal direction between the center of gravity of the generator set 2 and the center of the wheels 201 is large, therefore it is still very laborious for the operator to transport the generator set 2. In addition, the two wheels 201 of the existing generator set 2 share one axle. The axle passing through the entire generator set 2 occupies the space within the housing. Therefore, only wheels with small diameter can be used. However, the wheels with small diameter will lead to large resistance force between the wheels and the ground, and have poor adaptability for road conditions, thereby leading to poor passing ability of the generator set during the transportation.
In addition, since the existing generator set 2 has a height H larger than the width W, it has a high center of gravity. Therefore, it is easy to be fallen down toward left or right. When it is arranged in a moving transport, such as a car or a yacht, it is easy to be fallen down, which leads to fuel leak or other issues. Not only will the environment be polluted, but also safety hazards will be caused.
The portable generator set of the present disclosure intents to overcome the drawbacks of the existing generator set. A more suitable pull rod device and wheel devices, and a fuel tank which will not leak the fuel after falling down, are provided for the generator set. Accordingly, the efficiency and safety for transporting the generator set of the present disclosure are greatly increased, the labour for manually transporting the generator set is significantly reduced, and excellent portability can be obtained by the generator set. Furthermore, the generator set can be obliquely reclined toward a left side or right side, which greatly increases the safety and provides great convenience for the transportation and storage of the generator set.

SUZHOU YUANNENG DONGLI TECHNOLOGY CO., LTD.


An improved rheometer of the present invention includes an adjustable gap through which a flowing system is forced. The inner cavity dimension of the gap is variable so as to give a user of the rheometer an ability to vary the separation gap and the length over diameter ratio. This, in turn, allows the user to determine the shear rate and shear stress along the wall of the cavity for varying deformation rates. Thus, the shear viscosity of the flowing system can be characterized for non-Newtonian systems without varying the volumetric flow rate. One of the preferred embodiments of the adjustable gap rheometer is a slit rheometer in which the flowing system is forced through a slit having generally more length than width and more width than gap. The slit rheometer is made adjustable by holding the body of the rheometer stationary while moving an adjustable wall which forms one of the sides of the slit. Another preferred embodiment of the adjustable gap rheometer includes two concentric portions comprising a mandrel portion and a bushing portion. Axial movement of one of the portions relative to the other varies the separation between the components.

This invention relates to the characterization of a flowing system such as a fluid or a mixture of fluids or a mixture of liquids with gases and/or solids by determining the rheological properties of the flowing system. More particularly, the invention relates to an improved rheometer having an adjustable inner cavity dimension so that properties of the flowing system are easily varied and the flowing system can be characterized without altering the volumetric flow rate of the flowing system.
Generally, rheometers operate by forcing the flowing system to be characterized through a die at a constant volumetric flow rate and determining specific properties of the flowing system such as the shear rate and shear stress of the flowing system at the wall of the die in order to determine the shear viscosity. These properties are characteristic of the flow and deformation behavior of the flowing system. The shear viscosity, in particular, is the most important rheological property.
The flow and deformation behavior are related to primary characteristics of the flowing system such as molecular weight, molecular weight distribution, extent of chain branching in polymer melts, degree of cure or conversion in a reacting system, and various microstructural distributions in multiphase systems. The microstructural distributions include the size distributions, locations and orientations of solid components in the flow, the concentration, shape, surface and size distributions of liquid droplets and the content and size distributions of gaseous components. Thus, characterization of the rheological behavior of a flowing system provides information on the structure of the system.
The rheological properties of the flowing system are characterized by employing material functions such as wall shear stress versus deformation rate at the wall or shear viscosity versus deformation rate determined on the basis of well-defined steady flows.
Rheometers of the prior art include capillary or slit rheometers. They operate by forcing the flowing system through a capillary die or a slit die at a specified volumetric flow rate with a drive mechanism such as a piston or a gear mechanism.
Because shear viscosity of a non-Newtonian flowing system is dependent on the deformation rate of the system, characterization of a non-Newtonian flowing system requires that shear rate and shear stress values be determined at multiple deformation rates to determine the viscosity over the deformation range of interest. Conventional rheometers achieve this by altering the volumetric flow rate into the rheometer. In this way, properties of the flowing system such as the shear rate and shear stress values are altered, and it is possible to determine the viscosity of the particular flowing system of interest over the deformation range of interest. However, altering the flow rate can change the structure and, hence, the rheological properties of the flowing system if a continuous process is used to deliver the flowing system to the rheometer. This distorts the results of the rheological study. Further, generating multiple flow rates requires equipment which is both cumbersome and expensive. Thus, a need exists for a rheometer which can determine the shear viscosity of non-Newtonian flowing systems from a constant flow rate through the rheometer.


An internal voltage generator of a semiconductor device includes a charge pumping unit for performing a charge pumping operation on the basis of the voltage level of a reference voltage to generate a charge pumped voltage having a voltage level higher than the external power supply voltage; and an internal voltage generating unit for performing a charge pumping operation on the basis of an internal voltage level that is linear with respect to a temperature change in a first temperature range to generate an internal voltage, and to perform a charge pumping operation on the basis of an internal voltage clamping level that is constant independent of a temperature change in a second temperature range to generate the internal voltage.

The present invention relates to semiconductor design technology, and in particular, to an internal voltage generator of a semiconductor device that operates stably even in a low power supply voltage environment. More particularly, the present invention relates to a voltage detecting circuit of an internal voltage generator that operates stably even in a low power supply voltage environment.
Most semiconductor devices, including dynamic random access memories (DRAMs), generate and use not only an external power supply voltage (e.g., VDD and VSS) but also an internal voltage having a different level than the power supply voltage. In general, the internal voltage is generated by a charge pumping mode or a voltage down converting mode by using an external power supply voltage VDD, an external ground voltage VSS and a reference voltage corresponding to the target level of the internal voltage.
A high-level voltage VPP and a back-bias voltage VBB are examples of the internal voltage of the DRAM generated by the charge pumping mode. Also, a core voltage VCORE and a bitline precharge voltage VBLP are examples of the internal voltage of the DRAM generated by the voltage down converting mode.
The high-level voltage VPP has a higher voltage level than the external power supply voltage VDD, which is generally used to drive a wordline. On the other hand, the back-bias voltage VBB is a negative voltage lower than the external ground voltage VSS, which is generally used as a body (or bulk) bias of a cell transistor (e.g., an NMOS transistor).
FIG. 1 is a block diagram of a conventional back-bias voltage (VBB) generator. Referring to FIG. 1, the conventional back-bias voltage generator includes a back-bias reference voltage generating unit 50, a back-bias voltage detector 10, an oscillator 20, a pump controller 30, and a charge pump 40. The back-bias reference voltage generating unit 50 is configured to receive an external power supply voltage VDD to perform a voltage down converting operation on the basis of the voltage level of a reference voltage VREF to generate a back-bias reference voltage VREFB that maintains a predetermined target level. The back-bias voltage detector 10 is configured to receive the back-bias reference voltage VREFB and a back-bias voltage VBB, which is fed back from a back-bias voltage output terminal, to output an enable signal BBEb. The oscillator 20 is configured to output an oscillation signal OSC with a predetermined oscillation frequency in response to the enable signal BBEb. The pump controller 30 is configured to receive the oscillation signal OSC to generate a pump control signal PUMP_CTRL. The charge pump 40 is configured to perform a negative charge pumping operation on the back-bias voltage output terminal in response to the pump control signal PUMP_CTRL.
Herein, the reference voltage VREF always maintains the predetermined target level regardless of a temperature change and a voltage level change of the external power supply voltage VDD. In general, the reference voltage VREF is generated by a bandgap reference circuit that operates by receiving the external power supply voltage VDD.
When a power supply voltage is externally applied to stabilize the voltage level of the external power supply voltage VDD above a predetermined level, a power-up signal is activated to initiate the voltage generating operation of all the internal voltage generators including the back-bias voltage generator and the bandgap reference circuit. The back-bias voltage output terminal has a ground voltage (VSS) level before the initiation of the voltage generating operation of the back-bias voltage generator. The back-bias voltage detector 10 detects the ground voltage level of the back-bias voltage output terminal to activate the enable signal BBEb to a logic low level, thereby enabling the oscillator 20. When the oscillator 20 is enabled to output the oscillation signal OSC with the predetermined oscillation frequency, the pump controller 30 receives the oscillation signal OSC to generate the pump control signal PUMP_CTRL and the charge pump 40 performs a negative charge pumping operation in response to the pump control signal PUMP_CTRL. This charge pumping operation continues until the voltage level of the back-bias voltage output terminal reaches the target level determined according to the back-bias reference voltage VREFB.
Conventionally, the back-bias voltage detector 10 of FIG. 1 includes a back-bias voltage normal detector, a back-bias voltage modulation detector, a back-bias voltage high clamping detector, and a back-bias voltage low clamping detector, and a detection signal combination circuit. The back-bias voltage normal detector is configured to detect the voltage level of the back-bias voltage VBB that is constant independent of a temperature change. The back-bias voltage modulation detector is configured to detect the voltage level of the back-bias voltage VBB that is linearly dependent on a temperature change. The back-bias voltage high clamping detector is configured to detect the highest (absolute) clamping level of the back-bias voltage VBB that is constant independent of a temperature change. The back-bias voltage low clamping detector is configured to detect the lowest (absolute) clamping level of the back-bias voltage VBB that is constant independent of a temperature change. The detection signal combination circuit is configured to combine detection signals, which are outputted respectively from the back-bias voltage modulation detector, the back-bias voltage high clamping detector, and the back-bias voltage low clamping detector, to generate a combined detection signal.
FIG. 2 is a circuit diagram of the back-bias voltage detector 10 of FIG. 1, which includes a back-bias voltage normal detector 10A, a back-bias voltage modulation detector 10B, a back-bias voltage high clamping detector 10C, and a back-bias voltage low clamping detector 10D, and a detection signal combining unit 10E.
Referring to FIG. 2, the back-bias voltage normal detector 10A includes a first PMOS transistor P1, a second PMOS transistor P2, and a first inverter INV1. The first PMOS transistor P1 has a gate connected to receive a ground voltage VSS, a source and a bulk connected to receive a back-bias reference voltage VREFB, and a drain connected to a first detection node NODE_1. The second PMOS transistor P2 has a gate connected to receive a back-bias voltage VBB, a drain connected to receive the ground voltage VSS, a bulk connected to receive the back-bias reference voltage VREFB, and a source connected to the first detection node NODE_1. The first inverter INV1 is configured to have an input terminal, which is connected to the first detection node NODE_1, to output a normal detection signal DET_N.
The back-bias voltage modulation detector 10B includes a third PMOS transistor P3, an NMOS transistor N1, and a second inverter INV2. The third PMOS transistor P3 has a gate connected to receive the ground voltage VSS, a source and a bulk connected to receive the back-bias reference voltage VREFB, and a drain connected to a second detection node NODE_2. The NMOS transistor N1 has a gate connected to receive the back-bias reference voltage VREFB, a source and a bulk connected to receive the back-bias voltage VBB, and a drain connected to the second detection node NODE_2. The second inverter INV2 is configured to have an input terminal, which is connected to the second detection node NODE_2, to output a modulation detection signal DET_T.
The back-bias voltage high clamping detector 10C includes a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a third inverter INV3. The fourth PMOS transistor P4 has a gate connected to receive the ground voltage VSS, a source and a bulk connected to receive the back-bias reference voltage VREFB, and a drain connected to a third detection node NODE_3. The fifth PMOS transistor P4 has a gate connected to receive the back-bias voltage VBB, a drain connected to receive the ground voltage VSS, a bulk connected to receive the back-bias reference voltage VREFB, and a source connected to the third detection node NODE_3. The third inverter INV3 is configured to have an input terminal, which is connected to the third detection node NODE_3, to output a high clamping detection signal DET_H.
The back-bias voltage low clamping detector 10D includes a sixth PMOS transistor P6, a seventh PMOS transistor P7, and a fourth inverter INV4. The sixth PMOS transistor P6 has a gate connected to receive the ground voltage VSS, a source and a bulk connected to receive the back-bias reference voltage VREFB, and a drain connected to a fourth detection node NODE_4. The seventh PMOS transistor P7 has a gate connected to receive the back-bias voltage VBB, a drain connected to receive the ground voltage VSS, a bulk connected to receive the back-bias reference voltage VREFB, and a source connected to the fourth detection node NODE_4. The fourth inverter INV4 is configured to have an input terminal, which is connected to the fourth detection node NODE_4, to output a low clamping detection signal DET_L.
Herein, since the back-bias voltage normal detector 10A, the back-bias voltage high clamping detector 10C, and the back-bias voltage low clamping detector 10D always have constant back-bias voltage detection levels regardless of a temperature change, they may be implemented in the same circuit configuration. However, since the back-bias voltage normal detector 10A, the back-bias voltage high clamping detector 10C, and the back-bias voltage low clamping detector 10D must have different target back-bias voltage detection levels, their NMOS or PMOS transistors must be different in size.
That is, the sizes of the NMOS or PMOS transistors of the back-bias voltage normal detector 10A are set to detect a back-bias voltage target level value between the back-bias voltage detection level of the back-bias voltage high clamping detector 10C and the back-bias voltage detection level of the back-bias voltage low clamping detector 10D.
The detection signal combining unit 10E includes a first selecting unit 12E, a signal combining unit 14E, and a second selecting unit 16E.
The first selecting unit 12E is configured to select the normal detection signal DET_N outputted from the back-bias voltage normal detector 10A of the modulation detection signal DET_T outputted from the back-bias voltage modulation detector 10B according to a first test signal TEST1 and a fuse option (not illustrated) and output the selected signal as an uncombined detection signal DET_S. The signal combining unit 14E is configured to combine the high clamping detection signal DET_H outputted from the back-bias voltage high clamping detector 10C, the uncombined detection signal DET_S outputted from the first selecting unit 12E, and the low clamping detection signal DET_L outputted from the back-bias voltage low clamping detector 10D to generate a combined detection signal DET_CLP. Herein, the combined detection signal DET_CLP is used to detect the voltage level of the back-bias voltage VBB, whose back-bias voltage detection level varies linearly, in response to the uncombined detection signal DET_S in an intermediate-temperature range, to detect the lowest (absolute) clamping level of the constant back-bias voltage VBB in response to the low clamping detection signal DET_L in a low-temperature (deep cold) range lower than the intermediate-temperature range, and to detect the highest (absolute) clamping level of the constant back-bias voltage VBB in response to the high clamping detection signal DET_H in a high-temperature (deep hot) range higher than the intermediate-temperature range. The second selecting unit 16E is configured to select the uncombined detection signal DET_S or the combined detection signal DET_CLP according to a second test signal TEST2 and a fuse option (not illustrated) and output the selected signal as an enable signal BBEb.
FIG. 3A is a characteristic diagram illustrating a temperature-dependent back-bias voltage (VBB) detection level change in each of the detectors 10A, 10B, 10C and 10D of FIG. 2. FIG. 3B is a characteristic diagram illustrating a change in the back-bias voltage (VBB) detection level clamped by the back-bias voltage detector 10 of FIG. 2.
Referring to FIG. 3A, it can be seen that the normal detection signal DET_N outputted from the back-bias voltage (VBB) normal detector 10A, the high clamping detection signal DET_H outputted from the back-bias voltage (VBB) high clamping detector 10C, and the low clamping detection signal DET_L outputted from the back-bias voltage (VBB) low clamping detector 10D detect the voltage level of the back-bias voltage VBB on the basis of a specific target level even in a temperature change.
On the other hand, it can be seen that a target level for detection of the voltage level of the back-bias voltage VBB for the modulation detection signal DET_T outputted from the back-bias voltage (VBB) modulation detector 10B varies according to a temperature change. That is, it can be seen that the voltage level of the back-bias voltage VBB is detected on the basis of a relatively low target level (absolute value) at a relatively low temperature whereas the voltage level of the back-bias voltage VBB is detected on the basis of a relatively high target level (absolute value) at a relatively high temperature.
Referring to FIG. 3B, it can be seen that the characteristics of the enable signal BBEb outputted to the oscillator 20 vary according to the temperature ranges due to the operation of the detection signal combining unit 10E.
When the normal detection signal DET_N (among the normal detection signal DET_N and the modulation detection signal DET_T) is selected and outputted as the uncombined detection signal DET_S by the first selecting unit 12E of the detection signal combining unit 10, the enable signal BBEb with characteristics determined according to the normal detection signal DET_N is outputted regardless of the operations of the signal combining unit 14E and the second selecting unit 16E. That is, if the voltage level (absolute value) of the back-bias voltage VBB is higher than the normal target level (absolute value) determined by the back-bias voltage normal detector 10A, both of the logic levels of the normal detection signal DET_N and the enable signal BBEb become high; and if the voltage level (absolute value) of the back-bias voltage VBB is lower than the determined normal target level (absolute value), both of the logic levels of the normal detection signal DET_N and the enable signal BBEb become low. In this case, as illustrated in the drawings, since the normal target level (absolute value) does not change according to a temperature change, the logic level of the enable signal BBEb is not affected by the temperature change.
On the other hand, when the modulation detection signal DET_T (among the normal detection signal DET_N and the modulation detection signal DET_T) is selected and outputted as the uncombined detection signal DET_S by the first selecting unit 12E and the uncombined detection signal DET_S (among the uncombined detection signal DET_S and the combined detection signal DET_DLP) is selected and outputted as the enable signal BBEb by the second combining unit 16E, the enable signal BBEb with characteristics determined according to the modulation detection signal DET_T is outputted. That is, if the voltage level (absolute value) of the back-bias voltage VBB is higher than the modulation target level (absolute value) determined by the back-bias voltage modulation detector 10B, both of the logic levels of the modulation detection signal DET_T and the enable signal BBEb become high; and if the voltage level (absolute value) of the back-bias voltage VBB is lower than the determined modulation target level (absolute value), both of the logic levels of the modulation detection signal DET_T and the enable signal BBEb become low. In this case, as illustrated in the drawings, since the modulation target level (absolute value) changes according to a temperature change, the logic level of the enable signal BBEb is affected by the temperature change.
When the modulation detection signal DET_T (among the normal detection signal DET_N and the modulation detection signal DET_T) is selected and outputted as the uncombined detection signal DET_S by the first selecting unit 12E and the combined detection signal DET_CLP (among the uncombined detection signal DET_S and the combined detection signal DET_DLP) is selected and outputted as the enable signal BBEb by the second combining unit 16E, the enable signal BBEb with characteristics determined according to a combination of the modulation detection signal DET_T, the high clamping detection signal DET_H and the low clamping detection signal DET_L is outputted. That is, if the voltage level (absolute value) of the back-bias voltage VBB becomes lower than the lowest (absolute) clamping level of the back-bias voltage VBB, the logic level of the enable signal BBEb is determined according to the logic level of the low clamping detection signal DET_L regardless of the logic level of the modulation detection signal DET_T; if the voltage level (absolute value) of the back-bias voltage VBB becomes higher than the highest (absolute) clamping level of the back-bias voltage VBB, the logic level of the enable signal BBEb is determined according to the logic level of the high clamping detection signal DET_H regardless of the logic level of the modulation detection signal DET_T; and if the voltage level (absolute value) of the back-bias voltage VBB lies between the lowest (absolute) clamping level of the back-bias voltage VBB and the highest (absolute) clamping level of the back-bias voltage VBB, the logic level of the enable signal BBEb is determined according to the logic level of the modulation detection signal DET_T.
The conventional back-bias voltage generator can control the target level of the back-bias voltage VBB by means of the back-bias voltage detector 10 at the desire of a user even when the internal temperature of the semiconductor device changes.
However, the premise that the voltage level of the back-bias reference voltage VREFB supplied to the back-bias voltage detector 10 must always maintain the predetermined target level regardless of a temperature change or an external power supply voltage (VDD) level change, must be satisfied so that the back-bias voltage detector 10 of the conventional back-bias voltage generator can operate as described above.
If the voltage level of the external power supply voltage VDD supplied to the semiconductor device is sufficiently high, the above premise can be satisfied by the bandgap reference circuit that is used to generate the reference voltage VREF.
However, when the voltage level of the external power supply voltage VDD supplied to the semiconductor device decreases further according to the requirements for a low-power operation of the semiconductor device, the above premise fails to be satisfied, which causes the following problems.
FIG. 4 is a characteristic diagram illustrating a back-bias voltage (VBB) level change depending on an external power supply voltage (VDD) level change in the conventional back-bias voltage generator. Referring to FIG. 4, it can be seen that the voltage level of the back-bias reference voltage VREFB for the reference voltage VREF is determined at a different point as the voltage level of the external power supply voltage VDD increases.
That is, it can be seen that the reference voltage VREF with a relatively low target voltage level of 0.75 V increases along with the external power supply voltage VDD before the voltage level of the external power supply voltage VDD exceeds a voltage level of 0.75 V, but the reference voltage VREF continues to maintain the target voltage level without any more voltage level increase after the voltage level of the external power supply voltage VDD exceeds the voltage level of 0.75 V.
On the other hand, it can be seen that the back-bias reference voltage VREFB with a relatively high target voltage level of 1.5 V must increase along with the external power supply voltage VDD until the voltage level of the external power supply voltage VDD reaches a voltage level of 1.5 V, and the back-bias reference voltage VREFB continues to maintain the target voltage level without any more voltage level increase after the voltage level of the external power supply voltage VDD exceeds the voltage level of 1.5 V.
Herein, as described above, the back-bias voltage detector 10 of the conventional back-bias voltage generator receives the back-bias reference voltage VREFB to perform an operation of detecting the voltage level of the back-bias voltage VBB. Therefore, as illustrated in the drawings, the voltage level of the back-bias voltage VBB detected by the back-bias voltage detector 10 changes as the voltage level of the back-bias reference voltage VREFB changes.
Specifically, it can be seen that the voltage level of the back-bias voltage VBB fails to maintain a predetermined target level and changes with a change in the voltage level of the back-bias reference voltage VREFB in a period A before the voltage level of the back-bias reference voltage VREFB reaches a predetermined target level, and the back-bias voltage VBB maintains the predetermined target level in a period B after the voltage level of the back-bias reference voltage VREFB reaches the predetermined target level.
Herein, it can be seen that the voltage level of a first back-bias voltage VBB@COLD of the back-bias voltage VBB increases with an increase in the voltage level of the back-bias reference voltage VREFB, whereas the voltage level of a second back-bias voltage VBB@HOT of the back-bias voltage VBB decreases with an increase in the voltage level of the back-bias reference voltage VREFB. The reason for this is that the back-bias voltage normal detector 10A and the back-bias voltage modulation detector 10B have different operational characteristics as the voltage level of the back-bias reference voltage VREFB changes.
In general, the MOS transistors of the back-bias voltage normal detector 10A operate in a saturation state when the back-bias reference voltage VREFB increases. Therefore, the back-bias voltage normal detector 10A performs a detecting operation so that the absolute value of the back-bias voltage VBB can increase further. Also, the MOS transistors of the back-bias voltage modulation detector 10B operate in a linear state when the back-bias reference voltage VREFB increases. Therefore, the back-bias voltage modulation detector 10B performs a detecting operation so that the absolute value of the back-bias voltage VBB can decrease further. Of course, the back-bias voltage high clamping detector 10C and the back-bias voltage low clamping detector 10D have the same characteristics as the back-bias voltage normal detector 10A.
Thus, the first back-bias voltage VBB@COLD will be the back-bias voltage VBB generated according to the detecting operation of the back-bias voltage modulation detector 10B, and the second back-bias voltage VBB@HOT will be the back-bias voltage VBB generated according to the detecting operation of the back-bias voltage normal detector 10A.
Due to these characteristics, the back-bias voltage modulation detector 10B and the back-bias voltage normal detector 10A can perform the opposite detecting operations. As illustrated in the drawings, such a feature becomes more apparent as the voltage level of the back-bias reference voltage VREFB increases. It can be seen that the back-bias voltage modulation detector 10B and the back-bias voltage normal detector 10A can stably perform the completely opposite detecting operations after the voltage level of the back-bias reference voltage VREFB reaches the predetermined target level.
However, as the voltage level of the external power supply voltage VDD supplied to the semiconductor device decreases further according to the requirements for a low-power operation of the semiconductor device, the back-bias voltage modulation detector 10B and the back-bias voltage normal detector 10A cannot perform the opposite detecting operations, so that the separate configuration of the back-bias voltage modulation detector 10B and the back-bias voltage normal detector 10A becomes meaningless.
That is, as illustrated in the graph of FIG. 4, if the voltage level of the external power supply voltage VDD becomes 1 V, the back-bias voltage modulation detector 10B and the back-bias voltage normal detector 10A perform the detecting operations with the same characteristics, so that it is unnecessary to provide the back-bias voltage modulation detector 10B and the back-bias voltage normal detector 10A separately.
Actually, an external power supply voltage VDD with a voltage level of 2.5 V is supplied for a DDR DRAM; an external power supply voltage VDD with a voltage level of 1.8 V is supplied for a DDR2 DRAM; an external power supply voltage VDD with a voltage level of 1.5 V is supplied for a DDR3 DRAM; and an external power supply voltage VDD with a voltage level of 1.2 V is supplied for a DDR4 DRAM that is developed recently.
When this trend is analyzed on the basis of the graph of FIG. 4, it can be seen that the DDR DRAM, the DDR1 DRAM, the DDR2 DRAM and the DDR3 DRAM can be stably operated using the conventional back-bias voltage generating circuit, but the DDR4 DRAM cannot be stably operated even using the conventional back-bias voltage generating circuit.
As described above, because the voltage level of the external power supply voltage VDD continues to decrease with the development of new semiconductor devices, there is a possibility that the voltage level of the external power supply voltage VDD may decrease below 1 V. If a new semiconductor device operated by an external power supply voltage VDD with a voltage level of below 1 V is developed, the new semiconductor device cannot operate according to the intention of a designer even when using the conventional back-bias voltage generating circuit, so that it is difficult to expect the normal operation.

Internal voltage generator of semiconductor device


An open-drain output buffer is operative to sustain relatively high voltages applied to an output pad. The open-drain buffer includes a number of floating wells, output switching devices and corresponding well-bias selectors to ensure that no gate oxide sustains voltages greater than a predefined value. PMOS and NMOS well-bias selectors operate to select and provide an available highest or lowest voltage, respectively, to bias corresponding well-regions and ensure no device switching terminals are electrically over stressed. As output related terminals experience switching related voltage excursions, the well-bias selectors select alternate terminals to continue selection of the respective highest or lowest voltages available and provide correct well-biasing conditions. Voltage dividers are incorporated to generate well-biasing control voltages. By electrical coupling across maximal voltages, the voltage dividers generate reference voltages that induce proper selection of well-bias voltages to the floating wells.

The present invention relates to electronic circuits, and more particularly to an open-drain output buffer adapted to operate at relatively high voltages.
To realize manufacturing and economical leverages, topological geometries of semiconductor devices have been continually scaled downward across successive product generations. Supply voltages for semiconductors have correspondingly scaled downward, at least in part, to maintain consistent working voltages across materials, such as gate oxides. Historically a 0.35 micron (μm) technology has incorporated a 3.3 Volt (V) supply voltage and correspondingly, 0.18 μm and 0.13 μm technology generations have used 1.8 V and 1.2 V supplies, respectively. Maintaining consistent maximal operating voltages is necessary to avoid over-voltage conditions across electrical terminals that expose corresponding materials to electric field magnitudes that would cause material breakdown and device failure. The challenge of maintaining operating voltages within electrical limits of material properties comes at the input and output terminals of the semiconductor device. The input and output terminals are where an operating voltage region of a first device interacts with the voltage region of a second device. The device most challenged is the one operating in a lower voltage region. During electrical switching between the two operating voltage regions, the first device, operating at the lower voltage, experiences voltage from the second voltage region that may exceed operational voltage limits of the first device. During voltage excursions to the upper logic levels of the second device, over-voltage conditions in the first device are likely to cause exposed materials to fail.
Output buffers with open-drain pull-down transistors are typically used for attachment to common buses with other transistors (usually in another package). A single voltage supply point, perhaps with a pull-up resistor to a power source, provides the highest logic level required by any switching transistor on the bus. Output buffers with open-drain pull-down transistors are commonly fabricated in complementary metal oxide semiconductor (CMOS) processes. As an output terminal of an open-drain CMOS buffer turns off, pull-down transistors are switched off and buffer terminals remain in electrical connection with the output pad. An open-drain buffer of the first transistor (as above) experiences a high voltage level corresponding to an upper logic level voltage coming from the second transistor. The magnitude of the high logic-level of the second transistor, when applied to terminals of the first transistor may provide voltages that exceed the operating voltages and maximum sustainable voltages for particular materials in the first transistor. To avoid damage, the pull-down transistors have to be maintained in a semiconductor well provided with a voltage equal to the voltage provided by the second transistor and no gate oxide of a switching transistor may be exposed to a voltage causing failure of the gate. To avoid material breakdown, transistors exposed to elevated external voltages have been placed within a well provided with voltage near the switching voltage levels.
Typically, designers have found ways of providing a biasing voltage level to a substrate well encompassing a given switching transistor exposed to a relatively higher voltage region. Presuming that no explicit connection to the higher voltage region exists for the first transistor, a designer has been faced with utilizing some means of providing a path from the external voltage source to provide biasing to a well-region isolated from the well-regions operating at the native voltage-region level. Often the isolated or floating well-region is coupled to the output pad by a coupling transistor having a conductance characteristic provided and triggered by the elevated external voltage level. The coupling transistor provides an electrical path to the floating well providing the external voltage level as a well bias. This technique has been limited to a relative voltage level of about two times the operating voltage (VDD) of the first transistor. In order to provide a broader possible range of interface voltage interactions between semiconductor transistors, a means of allowing a greater range of disparity between voltage regions being switched to-and-from would be desirable. It would also be desirable to have a way of incorporating the voltage level of the external region and yet, still incorporate the floating well principle, and at the same time allow continued use of less expensive process technologies for the implementation of the interface transistor.

Open-drain output buffer for single-voltage-supply CMOS


Composition and methods for enhancing oligonucleotide-directed nucleic acid sequence alteration in vivo, ex vivo and in vitro are presented. These methods and compositions involve cells and cell-free extracts with altered levels or activities of a protein from the RAD52 epistasis group, the mismatch repair group and/or the excision repair group.

A number of different poly- and oligo-nucleotides have been described for use in targeted alteration of nucleic acid sequence including chimeric RNA-DNA oligonucleotides that fold into a double-stranded, double hairpin conformation and single-stranded chemically modified oligonucleotides. These oligonucleotides have been shown to effect targeted alteration of single base pairs as well as frameshift alterations in a variety of host organisms, including bacteria, fungi, plants and animals.
Several cellular pathways and gene groups are believed to be involved in mediating in vivo repair of DNA lesions resulting from radiation or chemical mutagenesis, including the RAD52 epistasis group of proteins, the mismatch repair group of proteins and the nucleotide excision repair group of proteins. The role of these proteins in homologous recombination and maintaining genome integrity has been extensively studied and is reviewed, for example, in Heyer, Experientia 50(3), 223–233 (1994); Thacker, Trends in Genetics 15(5), 166–168 (1999); Paques & Haber, Microbiol. and Molec. Biol. Rev. 63(2), 349–404 (1999); and Thompson & Schild, Mutation Res. 477, 131–153 (2001). The specific function of these proteins in oligonucleotide-directed nucleic acid sequence alteration is not well understood.
The utility of oligonucleotide-directed nucleic acid sequence alteration as a means, for example, to generate agricultural products with enhanced traits or to generate animal models or animals with desired traits is affected by its frequency. The utility of oligonucleotide-directed nucleic acid sequence alteration as a therapeutic method would also be enhanced by increasing its efficiency. A need exists for methods to enhance the efficiency of oligonucleotide-directed nucleic acid sequence alteration.

Compositions and methods for enhancing oligonucleotide-mediated gene alteration


A driveline component with a housing, a pinion mounted in the housing for rotation about a first axis, a ring gear and a pair of output members. The ring gear is meshed with the pinion and is rotatable about a second axis. The ring gear is supported for rotation relative to the housing by a pair of tapered roller bearings that are disposed along the second axis on a common lateral side of the ring gear. The output members are drivingly coupled to the ring gear.

This section provides background information related to the present disclosure which is not necessarily prior art.
Many modern automotive vehicles, such as crossover vehicles, are available with an all-wheel drive (AWD) drivetrain that is based on a front-wheel drive (FWD) architecture. This optional drivetrain arrangement permits drive torque to be selectively and/or automatically transferred from the powertrain to both the primary (i.e., front) driveline and the secondary (i.e., rear) driveline to provide better traction when the vehicle is operated in inclement weather and on off-highway road conditions. Such AWD vehicles necessarily are equipped with a much more complex drivetrain which, in addition to the primary driveline, must include the additional components associated with the secondary driveline such as a power take-off unit and a propshaft.
In an effort to minimize driveline losses (i.e., viscous drag, friction, inertia and oil churning) associated with secondary driveline being back-driven when no drive torque is transmitted thereto, it is known to incorporate a disconnect system that is configured to uncouple components of the secondary driveline such as, for example, the rear wheels or the rear differential from the remainder of the secondary driveline. To this end, there remains a need in the art for development of improved disconnectable drivelines for use in AWD vehicles.

Single speed and two-speed disconnecting axle arrangements


A drum spur extension apparatus having an elongate member having a predetermined length, a longitudinally extending axis and a longitudinally extending inner bore that is sized for receiving a drum spur. The elongate member has a closed end and an opposite open end defining an opening in communication with the longitudinally extending bore. Other embodiments of the spur extension apparatus of the present invention are disclosed herein.

Bass drums are known in the art and are widely used by musicians all over the world. Bass drums are typically used with foot pedal assemblies which comprise a hammer or beater that strikes the drumhead of the bass drum when a user depresses a foot pedal. Typical foot-operated pedals for use with bass drums are disclosed in U.S. Pat. No. 5,565,637, entitled "Foot Pedal for A Drum", issued to Shigenaga, and U.S. Pat. No. 4,567,808, entitled "Foot Operated Bass Drum Pedal", issued to Smith. It is imperative that the bass drum is in the correct or desired position so the hammer strikes the drumhead at the desired location. Lifts devices have been developed to position the bass drum in the desired position. Such devices are described in U.S. Pat. No. 4,829,874 and U.S. Patent Application Publication No. US2006/0005689. Another such device is disclosed in commonly owned and copending U.S. application Ser. No. 11/805,922, entitled "Drum Lift". These devices are located under the rear portion of the bass drum and raise the position of the drum beating spot to a desired height. Bass drums also include a spur which is typically adjustable and located toward the front area of the base drum. Specifically, the spur is slidably disposed within a spur mount attached to the drum and has a first portion within the spur mount and/or the interior of the bass drum, and a second portion that extends from the spur mount and contacts the surface, e.g. floor, upon which the bass drum is positioned. The spur can be pulled outward to increase the length of the portion of the spur that extends from the spur mount so as to raise the front portion of the bass drum. The spur can also be pushed inward so as to reduce the portion of the spur that extends from the mount thereby lowering the height of the front portion of the bass drum. However, early model bass drum spurs and some current bass drum spurs are limited in that they cannot raise the front portion of the bass drum to the appropriate height when certain types of drum lifts are used with the bass drum. Thus, in some instances, the drum will be at an awkward slant while the player is playing the bass drum. Such a slant in the bass drum's position could have a degrading effect on the sound produced by the drum.
What is needed a drum spur extension device that addresses the foregoing problems.


An antenna includes a non-conductive pane, a ground plane disposed on the non-conductive pane, and a radiating strip disposed on the non-conductive pane for operating in a plurality of frequency bands. The radiating strip defines a plurality of loops. A portion of a periphery of one of the loops coincides with at least a portion of a periphery of another of the loops. The radiating strip also includes at least one branch extending away from the periphery of one of the loops to allow tuning and shifting of the resonant frequencies of the antenna.

1. Field of the Invention
The subject invention relates to a multi-band antenna, specifically to a conductive strip loop antenna, disposable on a window for transmitting and receiving RF signals.
2. Description of the Related Art
Conductive strip antennas that are disposable on windows of vehicles are well known to those skilled in the art. These antennas are often used to receive broadcasts from radio stations in the AM and FM broadcast bands and are commonly used in vehicles. The primary advantage of such antennas is the removal of the vertical rod antennas that typically extend from body panels of vehicles. This provides improved vehicle aesthetics as well as less wind resistance for the vehicle.
Development of cellular communications networks, often referred to as mobile communications networks, cellular phone networks, or mobile telephone networks, has progressed at breakneck speeds over the last few decades. As such, RF coverage of these networks is nearly ubiquitous in populated areas of the planet. Manufacturers continue to integrate devices that utilize these networks into vehicles for both voice and data communications. As with AM/FM antennas, these cellular antennas are frequently rods or posts that extend from body panels.
Development of these cellular communication networks have been done in a piecemeal fashion, such that the frequency bands that they utilize are spread throughout the electromagnetic spectrum. Often it is desirable to have an antenna that can operate in several of these frequency bands to accommodate a wide variety of networks.
As stated above, the prior art discloses antennas that are disposable on windows of vehicles. However, these antennas often do not operate on multiple frequency bands. Furthermore, when these antennas do operate on multiple frequency bands, they often define a large surface area that may either obstruct the view of a driver of a vehicle and/or are not aesthetically pleasing.


The present disclosure provides micro-array devices for capturing cells in blood and methods of their use. In some aspects, a method for counting cells in a blood sample is provided, the method comprising applying a blood sample onto a CNT device; allowing cells in the blood sample to differentially settle on the CNT device, and identifying and counting cells of preselected type in the blood sample.

Circulating tumor cells (CTC) detection in blood can help study various cancers. The field of isolation and study of circulating tumor cells has been growing with many types of devices reported in the recent past based on immunomagnetic methods, microfluidic chips, laser scanning cytometry, high-throughput optical-imaging systems fiber optic array scanning technology and nano-Velcro arrays. While each method has advantages, there also many disadvantages associated with each method. However, there is still a need for devices and methods for isolation of CTCs from blood.

Micro-array devices for capturing cells in blood and methods of their use

University of Louisville Research Foundation, Inc.