The invention provides an inorganic reaction system for the preparation of electroconductive paste. Particularly, an inorganic reaction system comprises conductive glass. The inorganic reaction system may comprise a silver containing matrix forming composition. The silver containing matrix composition may comprise at least one of silver oxide or silver halide, or both. The invention also provides solar cells manufactured utilizing an electroconductive paste comprising an inorganic reaction system comprising conductive glass, and methods of manufacturing solar cells utilizing an electroconductive paste comprising an inorganic reaction system comprising conductive glass.

Solar cells are devices that convert the energy of light into electricity using the photovoltaic effect. Solar power is an attractive green energy source because it is sustainable and produces only non-polluting by-products. Accordingly, a great deal of research is currently being devoted to developing solar cells with enhanced efficiency while continuously lowering material and manufacturing costs.
When light hits a solar cell, a fraction of the incident light is reflected by the surface and the remainder transmitted into the solar cell. The transmitted light/photons are absorbed by the solar cell, which is usually made of a semiconducting material, such as silicon. The absorbed photon energy excites electrons from the atoms of the semiconducting material, generating electron-hole pairs. These electron-hole pairs are then separated by p-n junctions and collected by conductive electrodes that are applied on the solar cell surface. These conductive electrodes typically comprise an electroconductive paste composition.
Traditional electroconductive pastes contain metallic particles, glass frit, and an organic vehicle. These components are usually selected to take full advantage of the theoretical potential of the resulting solar cell. The metallic particles act as the conductive component of the surface electrode. The organic vehicle provides the medium through which all of the components are combined. The glass frit component has a number of purposes, one of which is to improve contact between the electrode and the underlying silicon surface. It is desirable to maximize the contact between the electroconductive paste and silicon surface, as well as with the metallic particles themselves, so that the charge carriers can flow through the interface and then through the surface electrodes. The glass particles in the electroconductive paste provide the media by which the paste builds contact between the metal and the underlying silicon substrate. The glass component must have specific properties in order to achieve optimal contact. Thus, the goal is to minimize contact resistance while improving solar cell efficiency. Known glass compositions have high contact resistance due to the insulating effect of the glass in the interface of the electrode and silicon wafer. Further, glass frit is known to have wide melting temperature ranges, making their behavior strongly dependent on the processing parameters. Accordingly, electroconductive paste compositions with improved electrical properties are desirable. Specifically, electroconductive paste compositions with improved glass frit components are needed.

Inorganic reaction system for electroconductive paste composition

Heraeus Precious Metals North America Conshohocken LLC


There is provided a circuit including a capacitor, a current source configured to supply a current to the capacitor, a comparator configured to output a result of comparison between a voltage stored in the capacitor and a predetermined voltage, and a switch section configured to intermittently which is caused to flow to the capacitor by the current source.

The present technology relates to a circuit, particularly, to a circuit that generates timing by utilizing charging and discharging to and from a capacitor using a current source.
Various types of soft start-up circuits according to the related art are known (see, for example, Hirokazu Tsujimoto and Tetsuo Tateishi, "SOFT STARTING REFERENCE VOLTAGE CIRCUIT", U.S. Pat. No. 6,348,833, Kabushiki Kaisya Toyoda Jidoshokki Seisakusyo, 2002 (Patent Literature 1), Chun-Yu Hsieh, Yung-Chun Chuang, and Ke-Horng Chen, "A Novel Precise Step-Shaped Soft-Start Technique for Integrated DC-DC Converter", 14th IEEE International Conference on Electronics, Circuits and Systems, pp 771-774, 2007 (Non-Patent Literature 1), and Ke-Horng Chen, Chia-Jung Chang and Te-Hsien Liu, "Bidirectional Current-Mode Capacitor Multipliers for On-Chip Compensation", IEEE Transactions on Power Electronics, Vol. 23, 2008, pp 180-188 (Non-Patent Literature 2)). FIG. 15 is a diagram illustrating an example power supply circuit including a soft start-up circuit, and FIG. 16 is a timing chart for explaining the operation of the power supply circuit illustrated in FIG. 15. The power supply circuit 1 illustrated in FIG. 15 is a step-down DC-DC converter in voltage control mode, and includes a DC power supply voltage B, switching elements M1, M2, an inductor L, an output capacitor C, a feedback control circuit FB, and a soft start-up circuit SS.
One end of the inductor L is connected to the positive terminal of the power supply voltage B via the switching element M1 as well as to the ground via the switching element M2. The other end of the inductor L is connected to a load as well as to the ground via the output capacitor C.
The switching element M1 is a P-channel electric field effect transistor (hereinafter referred to as a PFET), and when the switching element M1 is switched from off to on, magnetic energy is stored in the inductor L, and a current, which is smoothed by the inductor L and the capacitor C, is supplied to the load.
The switching element M2 is an N-channel electric field effect transistor (hereinafter referred to as a NFET), and when the switching element M2 is switched from off to on, the magnetic energy stored in the inductor L flows as a current through the load via the switching element M2 and is discharged, the current being smoothed by the inductor L and the capacitor C. It should be noted that the switching element M2 may be configured with a commutation diode.
The switching elements M1, M2 receive inputs of PWM control signals at their control terminals from the driver circuit Dry described later, the PWM control signals having on/off states inverted to each other. That is, when the switching element M1 is on, the switching element M2 is off, and when the switching element M1 is off, the switching element M2 is on. In this manner, constant voltage control can be performed according to a duty ratio of the PWM control signals.
The feedback control circuit FB includes an error amplifier EA, a comparator Comp, a flip-flop FF, and the driver circuit Drv, and is configured to control on/off of the switching elements M1, M2 so that an output voltage V0 converges to a target voltage.
The error amplifier EA detects an error between the output voltage and the target voltage, and outputs an error voltage Ve. Specifically, the error amplifier EA receives inputs of a voltage bV0 and a reference voltage Vref, and outputs a voltage as the error voltage Ve according to the difference between the voltage bV0 and the reference voltage Vref, the voltage bV0 being obtained by dividing the output voltage V0 of the power supply circuit 1 into a predetermined ratio, the reference voltage Vref indicating the target voltage of the voltage Vb0.
The comparator Comp generates a switching signal to be outputted to the driver circuit Drv. Specifically, the comparator Comp receives inputs of the error voltage Ve and a ramp wave Vramp which is a saw-tooth triangular wave inputted from a triangular wave generation circuit, and outputs a signal of positive logic (high level) when the error voltage Ve is higher than the lamp signal Vramp, or outputs a signal of negative logic (low level) when the error voltage Ve is lower than or equal to the ramp signal Vramp. That is, a PWM signal Spwm having a frequency according to the period of the ramp wave Vramp is outputted.
The flip-flop FF receives inputs of the PWM signal Spwm and a clock signal CK at reset terminal R and set terminal S, respectively, and outputs a PWM signal equivalent to the PWM signal Spwm to the driver circuit Dry only when the clock signal CK is being inputted.
When positive logic (high level) is inputted, the driver circuit Dry turns on the switching element M1 and turns off the switching element M2, whereas when negative logic (low level) is inputted, the driver circuit Dry turns off the switching element M1 and turns on the switching element M2.
Thus, the on/off ratio of the switching element M1 and the switching element M2 is controlled as follows: when the output voltage V0 is lower than the target voltage, the on-proportion of the switching element M1 and the off-proportion of the switching element M2 are increased, whereas when the output voltage V0 is higher than the target voltage, the off-proportion of the switching element M1 and the on-proportion of the switching element M2 are increased. As a consequence, on/off of the switching elements M1, M2 is controlled so that the output voltage V0 converges to the target voltage.
In the case where a desired reference voltage Vref is directly inputted to the error amplifier without providing the soft start-up circuit SS, when the power supply is activated, a rush current flows due to an abrupt rise of the output voltage. The rush current that occurs at the time of activation of the power supply is caused by a current that is for supplying charging current to the output capacitor
Specifically, when voltage bV0 corresponding to the output voltage V0 and the reference voltage Vref are inputted to the error amplifier at the time of activation of the power supply 1, the error voltage Ve outputted by the error amplifier EA is increased to nearly power supply voltage Vg.
At this point, the output of the comparator Comp is in a low level state, and thus the switching element M1 is turned on, and this state continues until all capacitors connected to the power source line are charged to a set voltage.
An increasing amount of current is continued to be supplied from a power supply circuit and/or a battery in a previous stage that supply power to the power supply circuit 1, which eventually causes an over current state, and a problem such as breakdown of a power transistor (such as the transistor elements M1, M2) and/or the inductor L may occur.
The capacitance of the output capacitor is decreasing every year due to an increase in switching frequency, and so effect of large capacitance is decreasing. However, many power supply circuits still need large-capacitance output capacitors, and in some cases, not only output capacitors but also huge capacitors are installed in a power line as a measure against momentary power failure. Therefore, at the time of activation of such a power supply circuit, it is necessary to charge all capacitors connected to the power line from 0V to the set voltage.
In order to avoid such a problem, it is preferable to reduce the charging current to the output capacitors. To cope with this, the power supply circuit 1 including a DC-DC converter is provided with a soft start-up circuit SS (see, for example, Patent Literature 1 and Non-Patent Literature 1, 2) that controls charging current to a capacitor to be lower than a certain level by delaying the increasing rate of the output voltage, thereby reducing rush current and/or overshoot which occurs due to an input at the time of activation of the power supply circuit 1.

Circuit and power supply circuit with output that transitions between capacitor stored voltage and predetermined voltage


Different stem sections, made by injection plastic molding or other manufacturing processes are assembled to produce an artificial plant. Some of the sections resemble sections of natural plant stems from which artificial leaves or flowers extend. Other sections are spacers. Each section is formed with a bore, dimensioned to receive a common wire. The upper end of the wire receives a flower head molded or otherwise adhered thereon. One end of each section is formed with a reduced external diameter plug and the opposite end with an enlarged internal diameter bore or socket. Hence adjacent sections are threaded on the wire from the bottom up and detachably, and preferably rotatably, joined together by inserting the plug of one section into the socket of the next. The structure at the upper end of the plant varies depending on what, if any, natural plant is being imitated. In a typical embodiment, the upper end section receives the upper end of the wire and has a style and stigma. The lower end forms a reduced diameter plug. A ring slips over the lower end of the upper end section, fitting against a stop on the upper end section. From the ring extend filaments, to which are connected anthers. The lower end of the ring is formed with a reduced diameter plug. An extended length bottommost section may be injection molded onto the wire after assembly of the other sections.

1. Field of the Invention
This invention relates to a new and improved sectionalized artificial plant having a central wire, a stamen molded onto the top end of the wire, and a plurality of preferably injection-molded plastic stem sections which are slipped over the wire from the bottom and are formed to interfit so as to simulate a natural plant stem. Branches extend from at least some of the stem sections and are integrally formed with leaves or other foliage. The lower end of the wire is closed off with a bottom stem section of extended length so that the wire may be cut to length when arranging the plant or flower for display.
2. Description of the Related Art
One type of artificial plants and flowers, as presently commercially available, are formed with plastic, injection-molded stems. Unitized leaves and flowers are attached to such stems by co-operating snap-on means molded onto the stem and into the leaves and flowers. Unfortunately, such snap-on means are ineffective and pieces of the plant frequently fall off.
Injection molding of leaves, including the filaments to which they are attached, and flowers is commonly practiced. Such leaves, flowers and filaments are then "double injected" onto the main stem. In order to close the mold, about one inch on either side of the stem must be without leaves. Wires must be implanted in the leaf stems. Once molded, the branches may not be twisted relative to each other. The present invention eliminates the double injection operation.
Flower heads are frequently assembled on the upper end of the stem and are secured either by a snap-on arrangement or by adhesive.
The present invention eliminates many of the problems of prior constructions as hereinafter appears.

Sectionalized artificial plant and flower construction


A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

1. Field of the Invention
The present invention relates to stacked integrated circuit memory.
2. State of the Art
Manufacturing methods for increasing the performance and decreasing the cost of electronic circuits, nearly without exception, are methods that increase the integration of the circuit and decrease its physical size per equivalent number of circuit devices such as transistors or capacitors. These methods have produced as of 1996 microprocessors capable of over 100 million operations per second that cost less than $1,000 and 64 Mbit DRAM circuits that access data in less than 50 ns and cost less than $50. The physical size of such circuits is less than 2 cm2. Such manufacturing methods support to a large degree the economic standard of living in the major industrialized countries and will most certainly continue to have significant consequences in the daily lives of people all over the world.
Circuit manufacturing methods take two primary forms: process integration and assembly integration. Historically the line between these two manufacturing disciplines has been clear, but recently with the rise in the use of MCMs (Multi-Chip Modules) and flip-chip die attach, this clear separation may soon disappear. (The predominate use of the term Integrated Circuit (IC) herein is in reference to an Integrated Circuit in singulated die form as sawed from a circuit substrate such as s semiconductor wafer versus, for example, an Integrated Circuit in packaged form.) The majority of ICs when in initial die form are presently individually packaged, however, there is an increasing use of MCMs. Die in an MCM are normally attached to a circuit substrate in a planar fashion with conventional IC die I/O interconnect bonding methods such as wire bonding, DCA (Direct Chip Attach) or FCA (Flip-Chip Attach).
Integrated circuit memory such as DRAM, SRAM, flash EPROM, EEPROM, Ferroelectric, GMR (Giant MagnetoResistance), etc. have the common architectural or structural characteristic of being monolithic with the control circuitry integrated on the same die with the memory array circuitry. This established (standard or conventional) architecture or circuit layout structure creates a design trade-off constraint between control circuitry and memory array circuitry for large memory circuits. Reductions in the fabrication geometries of memory cell circuitry has resulted in denser and denser memory ICs, however, these higher memory densities have resulted in more sophisticated control circuitry at the expense of increased area of the IC. Increased IC area means at least higher fabrication costs per IC (fewer ICs per wafer) and lower IC yields (fewer working ICs per wafer), and in the worst case, an IC design that cannot be manufactured due to its non-competitive cost or unreliable operation.
As memory density increases and the individual memory cell size decreases more control circuitry is required. The control circuitry of a memory IC as a percentage of IC area in some cases such as DRAMs approaches or exceeds 40%. One portion of the control circuitry is the sense amp which senses the state, potential or charge of a memory cell in the memory array circuitry during a read operation. The sense amp circuitry is a significant portion of the control circuitry and it is a constant challenge to the IC memory designer to improve sense amp sensitivity in order to sense ever smaller memory cells while preventing the area used by the sense amp from becoming too large.
If this design constraint or trade-off between control and memory circuits did not exist, the control circuitry could be made to perform numerous additional functions, such as sensing multiple storage states per memory cell, faster memory access through larger more sensitive sense amps, caching, refresh, address translation, etc. But this trade-off is the physical and economic reality for memory ICs as they are presently made by all manufacturers.
The capacity of DRAM circuits increase by a factor of four from one generation to the next; e.g. 1 Mbit, 4 Mbit, 16 Mbit and 64 Mbit DRAMs. This four times increase in circuit memory capacity per generation has resulted in larger and larger DRAM circuit areas. Upon introduction of a new DRAM generation the circuit yields are too low and, therefore, not cost effective for high volume manufacture. It is normally several years between the date prototype samples of a new DRAM generation are shown and the date such circuits are in volume production.
Assembling die in a stacked or three dimensional (3D) manner is disclosed in U.S. Pat. No. 5,354,695 of the present inventor, incorporated herein by reference. Furthermore, assembling die in a 3D manner has been attempted with regard to memory. Texas Instruments of Dallas, Tex., Irvine Sensors of Costa Mesa, Calif. and Cubic Memory Corporation of Scotts Valley, Calif., have all attempted to produce stacked or 3D DRAM products. In all three cases, conventional DRAM circuits in die form were stacked and the interconnect between each DRAM in the stack was formed along the outside surface of the circuit stack. These products have been available for the past several years and have proved to be too expensive for commercial applications, but have found some use in space and military applications due to their small physical size or footprint.
The DRAM circuit type is referred to and often used as an example in this specification, however, this invention is clearly not limited to the DRAM type of circuit Undoubtedly memory cell types such as EEPROMs (Electrically Erasable Programmable Read Only Memories), flash EPROM, Ferroelectric, or combinations (intra or inter) of such memory cells can also be used with the present Three Dimensional Structure (3DS) methods to form 3DS memory devices.
The present invention furthers, among others, the following objectives:
1. Several-fold lower fabrication cost per megabyte of memory than circuits conventionally made solely with monolithic circuit integration methods.
2. Several-fold higher performance than conventionally made memory circuits.
3. Many-fold higher memory density per IC than conventionally made memory circuits.
4. Greater designer control of circuit area size, and therefore, cost
5. Circuit dynamic and static self-test of memory cells by an internal controller.
6. Dynamic error recovery and reconfiguration.
7. Multi-level storage per memory cell.
8. Virtual address translation, address windowing, various address functions such as indirect addressing or content addressing, analog circuit functions and various graphics acceleration and microprocessor functions.

Adjacent substantially flexible substrates having integrated circuits that are bonded together by non-polymeric layer


A communication switch apparatus and a method for use in a geographically extensive serial, parallel or hybrid communication network linking a multi-processor or parallel processing system has a very low software processing overhead in order to accommodate random burst of high density data. Associated with each processor is a communication switch. A data source and a data destination, a sensor suite or robot for example, may also be associated with a switch. The configuration of the switches in the network are coordinated through a master processor node and depends on the operational phase of the multi-processor network: data acquisition, data processing, and data exchange. The master processor node passes information on the state to be assumed by each switch to the processor node associated with the switch. The processor node then operates a series of multi-state switches internal to each communication switch. The communication switch does not parse and interpret communication protocol and message routing information. During a data acquisition phase, the communication switch couples sensors producing data to the processor node associated with the switch, to a downlink destination on the communications network, or to both. It also may couple an uplink data source to its processor node. During the data exchange phase, the switch couples its processor node or an uplink data source to a downlink destination (which may include a processor node or a robot), or couples an uplink source to its processor node and its processor node to a downlink destination.

Large data processing applications are often partitioned such that they may be carried out by concurrently operating (parallel) processors, each of which handles a different portion of the problem. Independent of the complexity of the processing application, some data communication networks are challenging due to extensive geographic distribution of the elements supported by that communication network and the density of the data transmitted. In either of these two situations or their combination, efficient communication depends on the ability of the communication network to quickly route data from or to elements supported by the communication network. Speed must be maximized, especially in multi-processing systems having heavy traffic due to data acquisition and exchange, while data integrity and simplicity of transmission to any node, from the user's point of view, are maintained.
Prior art solutions called for a large software processing overhead to parse and interpret communication protocol and message routing at each node of the communication network. These prior art solutions have tended to trade speed in favor of flexibility. Examples of such prior art include the Scalable Coherent Interface (SCI), High Performance Parallel Interface (HIPPI), and Fiber Distributed Data Interface (FDDI).
The SCI approach transfers communication control words, destination addresses and source address, in addition to data in each 80 word communication packet. This imposes a burden of approximately 25% of the available packet space to communication protocol overhead (16 words), and time is spent parsing and interpreting every transmission.
The HIPPI is a simplex high performance communication interface which can transmit 800-1600 Megabits per second over a distance of 25 meters using copper cables. In the HIPPI approach, control lines are combined with data lines limiting the network topography to a static communication network configuration, making the HIPPI approach suitable only for parallel and distributed processing systems which have a static distribution of tasks.
The FDDI is a local area network based on token ring protocol. Information is transferred at the rate of 100 Megabits per second on the FDDI ring in frames that are variable in length. The FDDI provides a bridge between conventional high speed ethernet and high speed fiber optic link. It works such that a backbone FDDI ring connects a local island of ethernet work-group to a similar island located in another part of the network. The FDDI approach requires that control lines, source address, destination addresses, and data travel on the same physical line, thereby imposing burdens similar to the message space and processing time dedicated to communication protocol by the SCI approach and the limitation of a fixed communication network configuration as in the HIPPI approach.
Crossbar switches have also been commercially available for interconnecting general purpose processing nodes. Crossbar switches have a fixed number of input/output ports. A crossbar switch may be programmed such that a message transmitted through the crossbar switch may be coupled from any input port to any specified output port. The limited number of nodes attachable to a single crossbar switch results in a high cost per channel when crossbar switches are applied to a geographically extensive multi-processor system consisting of a large number of parallel processors.
These approaches are unsatisfactory for providing efficient data communication in a geographically extensive multi-processor system. It is preferable for such a system to have the following features. It is preferable that the communication network provide simple node access, from the user's perspective, in a reconfigurable multi-processor system. The communication network should also preferably provide intrinsic flexibility to use any combination of the following: (a) multi drop, flat ribbon cable type communication link for short distances, (b) conventional copper (or similar) cable links with intermediary signal filter/amplifiers between start and end points of data transmission as required to prevent signal degradation and distortion if operating over long distances or in a high electromagnetic noise environment, (c) fiber optic links, (d) segmented point to point communication with the capability to concurrently transfer different data in different communication segments within the system, (e) serial data links, (f) parallel data links, or (g) a combination of any of the above approaches applied to individual communication network subsets within the multi-processor system communication network.
It is also preferable that the communication network provide the highest possible ratio of data transferred to transmission protocol overhead. It is preferred that the communication network facilitate SCI, HIPPI and FDDI interfaces, to other systems. The communication network should also preferably facilitate designer selection of the best type of connection and length for each segment within the communication network and interface(s) with other processing systems in accordance with the requirements of the specific application.
In sum, prior art communication schemes do not satisfactory provide for a high speed, minimal protocol overhead means for efficiently communicating a random burst of high density data within a geographically extensive multi-processor system during data acquisition/exchange modes of operation. A communication system design is needed which maximizes data routing speed while maintaining data integrity.

Switch for serial or parallel communication networks


A radome that defines an axis and has an open end. The radome includes a plurality of plies including a first ply and a second ply. At least one of the plies includes a first sheet that defines a first edge and a second sheet that defines a second edge. The first edge abuts against the second edge to define a seam. A core portion is disposed between the first ply and the second ply.

The present invention relates generally to a cover for a radar antenna (radome). More particularly, the present invention relates to a seam arrangement for a composite radome.
Radomes are used to cover a radar antenna to protect the antenna from wind or foreign objects. In aircraft applications, the radome also provides aerodynamic improvements that allow the aircraft to fly with the radar antenna.
Radomes are often manufactured as composites. However, the materials used are not completely transparent to the electromagnetic energy emitted or received by the radar antenna. As such, the radome may reduce the overall performance of the radar system. In addition, the formation of the radome can affect the performance of the radome. Thus, the use of some radomes may result in operational limitations of the radar system due to the manufacturing techniques, materials, or processes used to build the radome. For example, it is often necessary to assembly multiple sheets of material to define a ply or layer of the radome. Adjacent sheets meet and define a seam that can interfere with or attenuate a radar signal, thereby degrading the performance of the radar system. Furthermore, excess thickness may be used to provide strength for the radome but may unnecessarily degrade the performance of the radar system.

This patent is subject to a terminal disclaimer.


A method for fabricating a semiconductor device includes forming a device isolation layer pattern on a substrate to form an active region, the active region including a first contact forming region at a center p of the active region and second and third contact forming regions at edges of the active region, forming an insulating layer and a first conductive layer on the substrate, forming a mask pattern having an isolated shape on the first conductive layer, etching the first conductive layer and the insulating layer to expose the active region of the first contact forming region by using the mask pattern, to form an opening portion between pillar structures, forming a second conductive layer in the opening, and patterning the second conductive layer and the first preliminary conductive layer pattern to form a wiring structure contacting the first contact forming region and having an extended line shape.

1. Field
Example embodiments relate to methods for fabricating a semiconductor device. More particularly, example embodiments relate to methods for fabricating a highly integrated DRAM device.
2. Description of the Related Art
Recently, semiconductor devices including DRAM devices are highly integrated. According to the increase of an integration degree, the contacting area of a contact may be decreased and a contact resistance may be increased. In addition, bridge defects between the contact and an adjacent pattern or bridge defects between the contact and an adjacent active region are increasing.

Methods for fabricating a semiconductor device


A forceps includes a pair of grip pieces which are pivotally supported about a first fulcrum to be mutually openable and closable. A pair of tip-end forceps pieces are pivotally supported about a second fulcrum to be mutually openable and closable. The second fulcrum is separated from the first fulcrum. An operation transferring member transfers opening and closing operation of the grip pieces about the first fulcrum to opening and closing operations of the tip-end forceps pieces about the second fulcrum.

1. Field of the Invention
The invention relates to a forceps for an endoscopic operation which is passed through a trocar to be used for performing an endoscopic operation in the body cavity.
2. Description of the Related Art
Recently, in various kinds of operations such as cholecystectomy, an endoscopic operation is widely performed. Such an endoscopic operation is performed without making a large incision and with thrusting plural trocar sheaths (hereinafter, referred to merely as "trocars") which are thin tubular members, into the somatic layer, and passing a surgical instrument and an endoscope through the trocars.
In an endoscopic operation, forceps such as a grasping forceps which grasps organs, and a cutting forceps which cuts organs are necessary. Generally, such forceps are configured so that a pair of members in each of which a grip piece on the side of the basal end and a forceps piece on the side of the tip end are integrally formed are rotatably coupled to each other at a fulcrum in an X-shape.
A forceps is passed through a trocar under a state where forceps pieces at the tip end are closed so as to reduce the size in section. In the body cavity, preferably, the tip end forceps pieces are widely opened.
As shown in FIG. 9, however, the open angle .theta. of tip end forceps pieces 91 is restricted by the inner diameter of a trocar 100. In a related art forceps for an endoscopic operation which is configured as described above, therefore, the open angle .theta. is restricted by the both end openings of the trocar 100.
The open angle .theta. is maximum when the fulcrum 92 is at to the middle of the trocar 100 in the longitudinal direction as shown in FIG. 9, and hence Tan(.theta./2) cannot be made large. Unless the trocar 100 is made unrealistically thick and short, consequently, a large open angle .theta. cannot be attained.
Even when a diseased part is slightly large, therefore, the part cannot be surely grasped or cut. As a result, an endoscopic operation cannot be adequately performed.


Various kinds of broadcast TV signals can be watched on display devices at desirable places (rooms). High-frequency signals of CS broadcast, BS broadcast and terrestrial broadcast are received and inputted via a lead wire to a retransmission device. A high-frequency signal of a cable television broadcast is directly inputted to the retransmission device. The retransmission device subsequently converts high-frequency signals of incoming different broadcasts into common high-frequency signals and transmits them in time-series. Then, the common high-frequency signals are transmitted by wired or wireless means to a plurality of display devices that may be installed in different rooms or are portable.

The present invention relates to a home network system capable of collectively receiving various broadcasts, converting received data into common digital data and transmitting the same content broadcast or different content broadcasts to a plurality of display devices.
Recently, there has been available a variety of broadcasting services which are terrestrial analog broadcasting, BS analog broadcasting, CS broadcasting, CATV and so on. Generally, subscribers-viewers selectively receive broadcasts at home terminals according to preferences, local conditions and service contents.
With this, each member in each home may always want to watch preferred programs in a desired way at a particular place.
In addition, the development of the digital technology accelerates the digitalization of the broadcasting services including BS and terrestrial digital broadcasting services.
FIG. 1 is a view for explaining conventional broadcast receiving means for receiving various broadcasting services.
The indoor connection system for receiving, for example, CS (Communication Satellite) broadcasting services in a home is as follows:
The CS broadcast 1 is received by a CS receiving antenna 5 and input to a CS receiver (or a set top box) 9 whereby the received television broadcast signal is converted into a signal to be displayed on a CS display 13.
The connection systems for receiving BS broadcasting and terrestrial broadcasting are analogous to that of the CS broadcasting and comprise respectively antennas 6, 7, receivers 10, 11, and displays 14, 15 in the described order.
Terrestrial broadcasts (VHF, UHF) are received by a so-called television set 17 in which a receiver 11 and a display 15 are combined.
Cable television (CATV) broadcasts transmitted over a cable network are received by a receiver (or a set top box) 12 and converted into a television signal to be displayed on a display unit for CATV 16.
As described above, each viewer (user) has to prepare in his or her home separate receivers and display units for viewing respective broadcasts (CS, BS, Terrestrial and CATV broadcasting services) (except display units usable common to receive the BS broadcasting and the terrestrial broadcasting).
The problems of the prior techniques are as follows:    (1) To enjoy various broadcasting services, the user selects in advance a place (room) for enjoying the broadcasting services, extends thereto respective coaxial cables from respective antenna receivers coupled to respective antennas (aerials), connects the cables to respective specific receivers and finally connects with connecting cables the respective specific receivers to a television receiver(s) (display unit(s)).    (2) In order to enjoy the various kinds of broadcasts in another place (other than the selected place as the above (1)), the user must extend to a newly selected place a coaxial cable from a distributor connected to respective antenna portions.    (3) To change the receiving place (room) for a particular broadcast service to another place (room), the user must extend to a newly selected place (another place) a coaxial cable from a distributor connected to a corresponding antenna portion, disconnect the corresponding receiver, replace it to the new place and then reconnect the receiver to the receiver to the display unit at the new place.    (4) The user cannot receive all kinds of broadcasts on a single television receiver and can enjoy only a limited number of the broadcasting services, each of which is received by a specific receiver connected to a corresponding receiving means of the television receiver.


A method and apparatus for transmitting/receiving an ACKnowledgement/Negative ACKnowledgement (ACK/NACK) signal to support packet data retransmission in an Frequency Division Multiple Access (FDMA) wireless communication system are provided, in which a User Element (UE) generates an ACK/NACK signal for received packet data, determines whether the UE is set to support ACK/NACK repetition, transmits the ACK/NACK signal on a basic response channel mapped to one of a DCH on which the packet data was received and a Shared Control Channel (SCCH) carrying scheduling information about the packet data, if the UE is not set to support ACK/NACK repetition, and selects one of supplementary response channels for each ACK/NACK repetition, the supplementary response channels being allocated for ACK/NACK repetition and repeatedly transmits the ACK/NACK signal on the selected supplementary response channel according to a predetermined repetition factor, if the UE is set to support ACK/NACK repetition.

1. Field of the Invention
The present invention relates to an apparatus and method for transmitting/receiving an ACKnowledgement/Negative ACKnowledgement (ACK/NACK) signal for received packet data in order to support Hybrid Automatic Repeat reQuest (HARQ) in a Frequency Division Multiple Access (FDMA) wireless communication system.
2. Description of the Related Art
With reference to FIG. 1, FDMA will first be described below. FIG. 1 illustrates FDMA.
Referring to FIG. 1, FDMA is a technology for distinguishing physical channels in frequency. In general, all available resources are divided in time and frequency as indicated by reference numeral 101. A minimum block is composed of one symbol in time and one subcarrier in frequency. This is called a Time-Frequency (TF) bin. A TF bin is an actual transmission unit carrying a modulation symbol on a physical channel. The total number of TF-bins depends on a total frequency bandwidth and the number of symbols transmittable in a Transmission Time interval (TTI).
In FDMA, different TF bins are allocated to different channels and different User Equipments (UEs). Basically, it is impossible to share one TF bin between different channels or different UEs. However, to achieve time diversity, frequency diversity, or spatial diversity for a low-rate channel, a TF bin can be shared by covering or spreading the TF bin with a code as with Code Division Multiplexing (CDM). For transmission of high-rate packet data, TF bins are purely allocated. Mapping between data symbols and TF bins is equivalent to subcarrier mapping 102. The mapping relationship between a channel and TF bins is signaled beforehand or determined according to a predefined rule.
Since a channel carrying packet data or a channel carrying signaling data is allocated on a UE basis, TF bins are allocated to the channel and then the channel with TF bins is allocated to an intended UE. Although TF bins can be allocated on a UE basis, TF bins allocated to a specific channel form a logical channel as indicated by reference numeral 103, which is preferable in terms of signaling. One logical channel (hereinafter, "channel") is composed of a plurality of TF bins and the number of TF bins is determined, taking into account the characteristics of the channel. In determining the number of TF bins for a channel, the lowest data rate of packet data is considered if the channel is a packet data channel, and signaling overhead of information about a scheduled channel is considered if scheduling is carried out. For a control channel, the number of TF bins is determined according to the number of bits transmitted per TTI.
A channel to be allocated to a UE is scheduled every TTI or set by higher signaling. In the illustrated case of FIG. 1, if a Data CHannel (DCH) 103 is allocated to a UE, packet data symbols 105 for the UE are mapped to the DCH 103 by channel mapping 104 and then mapped to actual TF bins by subcarrier mapping 102. During the subcarrier mapping 102, the channel may be mapped to scattered TF bins (e.g. a DCH 106) or successive TF bins (e.g. the DCH 103), depending on whether frequency diversity is to be achieved or according to a TF bin 4 allocation algorithm. Since the channel is a logical channel, when only an allocated channel is transmitted as with a UE, there may not be a need for channel mapping because transmission symbols are simply mapped to predefined TF bins of the allocated channel.
HARQ is a technique for increasing a reception success rate by soft-combining initial transmission data with retransmission data without discarding the initial transmission data. A HARQ receiver determines whether a received packet has errors and transmits a HARQ ACK signal or a HARQ NACK signal to a HARQ transmitter according to the determination result. Accordingly, the HARQ transmitter retransmits the HARQ packet or transmits a new HARQ packet according to the received HARQ ACK/NACK signal.
HARQ is categorized into synchronous HARQ and asynchronous HARQ according to the timing of retransmission. In synchronous HARQ, a retransmission occurs a predetermined time after completion of a previous transmission, whereas a retransmission occurs irrespective of the time of a previous transmission in asynchronous HARQ.
With reference to FIG. 2, a synchronous HARQ operation will be described in more detail. FIG. 2 illustrates a basic HARQ operation.
Referring to FIG. 2, a HARQ transmitter transmits an initial HARQ packet on a DCH 202 by a predetermined process in step 203. A HARQ receiver decodes the initial HARQ packet and determines whether the initial HARQ packet has errors by a Cyclic Redundancy Check (CRC) check. In the presence of errors, the HARQ receiver stores the HARQ packet in a buffer and transmits an HARQ NACK to the HARQ transmitter on an ACK CHannel (ACKCH) 202 in step 205. In step 206, the HARQ transmitter retransmits the HARQ packet. The HARQ receiver soft-combines the stored HARQ packet with the retransmission HARQ packet and performs a CRC check in step 207. If the combined HARQ packet still has errors, the HARQ receiver stores the HARQ packet in the buffer and transmits an HARQ NACK to the HARQ transmitter. However, if decoding of the combined HARQ packet is successful, the HARQ receiver transmits an HARQ ACK to the HARQ transmitter in step 208.
The HARQ transmitter repeats the above operation until it receives an HARQ ACK from the HARQ receiver or the number of retransmissions for the HARQ packet reaches a predetermined retransmission number.
Now an ACK/NACK transmission method will be described.
Conventionally, a dedicated channel is allocated for a UE so that the UE can transmit an ACK/NACK signal. Under an environment where channels are non-orthogonal as with Code Division Multiple Access (CDMA), the total amount of available resources is limited by transmit power or reception interference level rather than it is directly related to the number of codes. Therefore, allocation of a code to each UE is not a significant problem in terms of resource utilization even if the UE does not use the dedicated channel. However, T-F resources are orthogonal and the amount of T-F resources directly affects that of available resources in FDM. Hence, when T-F resources allocated to an ACKCH are not used, it is a waste of resources. In other words, dedicated allocation of resources for ACK/NACK transmission on a UE-by-UE basis is inefficient in terms of resource utilization in an FDMA system.
In this context, one-to-one mapping between ACKCHs and DCHs or Shared Control CHannels (SCCHs) has been proposed and is under discussion in order to support HARQ efficiently in the FDMA system.
FIG. 3 illustrates one-to-one mapping between DCHs and ACKCHs.
Referring to FIG. 3, reference numerals 302 to 305 are DCHs and reference numerals 307 to 310 denote ACKCHs. The DCHs 302 to 305 are mapped to the ACKCHs 307 to 310 in a one-to-one correspondence and an ACK/NACK signal for a received DCH is transmitted on a predetermined ACKCH mapped to the DCH. If packet data is received on a first DCH 302 (DCH #1), an ACK/NACK signal for the packet data is transmitted on a first ACKCH 307 (ACKCH #1). If packet data is received on a second DCH 303 (DCH #2), an ACK/NACK signal for the packet data is transmitted on a second ACKCH 308 (ACKCH #2). The mapping between the ACKCHs and the DCHs enables ACK/NACK transmission without allocating dedicated frequent resources to UEs.
FIG. 18 illustrates one-to-one mapping between SCCHs and ACKCHs.
Referring to FIG. 18, reference numerals 1802 to 1805 are SCCHs and reference numerals 1807 to 1810 denote ACKCHs. The SCCHs 1802 to 1805 are mapped to the ACKCHs 1807 to 1810 in a one-to-one correspondence and an ACK/NACK signal for a received DCH is transmitted on a predetermined ACKCH mapped to an SCCH by which the DCH has been scheduled. If scheduling information about packet data is received on a first SCCH 1802 (SCCH #1), an ACK/NACK signal for the packet data is transmitted on a first ACKCH 1807 (ACKCH #1). If scheduling information about packet data is received on a second SCCH 1803 (SCCH #2), an ACK/NACK signal for the packet data is transmitted on a second ACKCH 1808 (ACKCH #2).
ACK/NACK repetition will be described below.
Typically, an ACK/NACK TTI is equal in length to a TTI of a general downlink frame or an uplink frame. When a Mobile Station (MS) at a cell boundary needs a transmit power exceeding a maximum allowed power, for ACK/NACK transmission, it transmits an ACK/NACK signal with the maximum allowed power. The resulting decreased received signal level renders the ACK/NACK transmission unreliable. To avert this problem, a High Speed Downlink Packet Access (HSDPA) system repeats the same ACK/NACK signal, so that instantaneous power level requirements are decreased as much as a repetition number and thus the ACK/NACK signal can be transmitted within a maximum allowed power level. Information about whether an ACK/NACK signal is repeated (hereinafter, referred to as ACK/NACK repetition setting information) is set in an upper-layer signaling message or a Medium Access Control (MAC) message by a network.
For ACK/NACK repetition, a repetition factor should be set in order to indicate whether an ACK/NACK signal is repeated and how many times the repetition occurs. For example, if the repetition factor is a non-zero number, the ACK/NACK signal is repeated as many times as the repetition factor. If the repetition factor is 0, the ACK/NACK signal is transmitted only once.
When a system with ACKCHs mapped to DCHs or SCCHs supports ACK/NACK repetition, it faces some problems, which will be addressed with reference to FIG. 4. In the illustrated case of FIG. 4, one cell has two UEs, UE #1 and UE #2. UE #1 is located at a cell boundary and UE #2 is near to a Node B at the center of the cell.
First, one-to-one mapping between DCHs and ACKCHs will be described.
Referring to FIG. 4, three ACK/NACK repetitions are set for UE #1 so that it can transmit an ACK/NACK signal reliably. Since UE #2 has sufficient transmit power, UE #2 is supposed to transmit an ACK/NACK signal only once.
Upon receipt of packet data on a first DCH 402 (DCH #1) in step 405, UE #1 transmits an ACK/NACK signal on a first ACKCH 402 (ACKCH #1) at time k=4 in step 407 and then repeats the ACK/NACK signals on ACKCH #1 at time k=5 and k=6 in steps 408 and 409. Meanwhile, a Node B may transmit packet data to UE #2 on DCH #1 during the next TTI through scheduling in step 406. Then UE #2 transmits an ACK/NACK signal for the received packet data on ACKCH #1 at time k=5 in step 410. Thus, the ACK/NACK signals from UE #1 and UE #2 collide on ACKCH #1 at time k=5. This data collision occurs because UEs share the ACKCHs and the DCHs are mapped to the ACKCHs in a one-to-one correspondence.
ACK/NACK repetition is viable on the premise that an ACKCH can be allocated to a UE for a plurality of TTIs. However, data is transmitted on a DCH only during one TTI and the one-to-one mapping between ACKCHs and DCHs does not allow for allocation of an ACKCH mapped to the DCH long enough for ACK/NACK transmission. As SCCHs are also transmitted on a TTI basis, the one-to-one mapping between SCCHs and ACKCHs illustrated in FIG. 18 leads to the same problem.

Method and apparatus for transmitting/receiving ACK/NACK in a frequency division multiple access system


A multiband reception antenna enables the combined reception of circularly polarized satellite radio signals from at least one satellite radio service which emits with circular polarization and of terrestrially emitted radio signals. The multiband reception antenna comprises at least one satellite reception antenna with a ring line emitter and a plurality of vertical emitters are connected to the ring line emitter over the circumference of the ring line emitter. Furthermore, a monopole is provided, with a monopole connection point formed at the lower end thereof.

Terrestrially transmitted radio broadcast signals of radio broadcasts are transmitted in the frequency ranges of the radio broadcasting bands AM and FM by means of electromagnetic waves whose wavelengths are not shorter than approximately 2 m. New developments with rod-shaped active antennas attached perpendicular to the vehicle body acting as a conducting base surface for the two said broadcasting bands have led to smaller antenna lengths of approximately 20 cm. However, in the construction of vehicles frequently a further reduction in length of such antennas is required.
Due to the narrow construction spaces, the substantial requirement exists with regard to vehicle antennas to minimize their smallness and, in particular to thereafter minimize the outline of the antenna. In particular for satellite radio services as a first radio service the combination of satellite antennas and antennas for other radio services in a narrow space is problematic due to the coupling of radiation between the antennas and the deformation of the directional pattern of the satellite antenna associated therewith. This is, in particular founded on the tightly dimensioned link budget which can lead to a failure of the radio connection due to a drastic deformation of the directional pattern. For example, for satellite antennas in accordance with the standard of satellite radio transmission SDARS in the elevation angular range, e.g. between 25 and/or 30 degrees and 60 and/or 90 degrees an antenna gain of constantly e.g. 2 dBi and/or 3 dBi for circular polarization is strongly required, in dependence on the operator. This requirement exists for an antenna assembled in a center of a planar conductive base plate. This requirement can then only be maintained when the deviation from the ideal radiation characteristic for no spatial angle amounts to more than 0.5 dB. Thus, the directional pattern, in particular in view of the dimension known for antennas of vehicles, has an extremely narrow tolerance. In the DE 101 08 910, e.g. the constructional shape of an antenna is provided which enables the maintenance of the narrowly tolerated directional pattern. With antennas of this type the antenna gain required in the region of the zenith angle can generally be realized without a problem. For this antenna, the reception of terrestrially transmitted signals according to the SDARDS standard are combined with a monopole antenna, whereby a smaller design of the combined antenna advantageous with regard to the use at vehicles results for the first radio service 1. A requirement of narrow tolerance is to be substantially maintained in a corresponding manner for the assembly at a vehicle. Beside this satellite radio broadcast service also further satellite radio services should be possible, such as e.g. the Global Positioning System (GPS).
An antenna according to the state of the art is provided in the DE 101 08 910, it is, however, in no way suitable to receive terrestrially transmitted broadcast signals of radio broadcasts in the frequency ranges of the AM radio bands having free space wavelengths between 600 m and 10 m, as well as the FM radio bands with approximately 3 m free space wavelengths due to its small height.

Multiband reception antenna for the combined reception of satellite signals and terrestrially emitted radio signals


The present invention relates to a fast acting chemical treatment for preventing the generation of hydrogen sulfide odor by the microbial metabolic activities of sulfate reducing bacteria. Specifically, the invention relates to a method for preventing hydrogen sulfide odor generation in a sulfur species-containing aqueous medium, which includes adding to the aqueous medium an effective amount for the purpose of a sulfide scavenger treatment selected from the group consisting of glyoxal, triazine, n-chlorosuccinimide, and mixtures thereof.

The reactivity between various aldehydes and sulfidic compounds (H2S, mercaptans, etc.) has been known in the art for some time. For example, Marks in U.S. Pat. No. 1,991,765 discloses a method of reacting hydrogen sulfide and an aldehyde in an aqueous solution having a pH between 2 and 12 at a temperature between substantially 20° C. and 100° C. After Marks' disclosure in 1935, many patents appeared disclosing the use of aldehydes during acid cleaning of iron sulfide deposits, including U.S. Pat. Nos. 2,606,873; 3,514,410; 3,585,069; 3,669,613; 4,220,550; 4,289,639; and 4,310,435. Consumption of the hydrogen sulfide liberated by acidification of sulfide-containing deposits increased the safety of such operations. Decreased corrosivity of the aldehyde-containing acids is also disclosed in the prior art, sometimes with the addition of ancillary corrosion inhibitors.
Menaul in U.S. Pat. No. 2,426,318 discloses a method of inhibiting the corrosive action of natural gas and oil containing soluble sulfides on metals by utilizing an aldehyde and preferably formaldehyde.
Roehm in U.S. Pat. No. 3,459,852 discloses a process for deodorizing and reducing the biochemical demand of an aqueous solution which contains at least one compound of hydrogen sulfide and compounds containing the —SH group. Roehm's process comprises mixing the solution with a sulfide-active alpha, beta unsaturated aldehyde or ketone in an amount sufficient to form sulfur-containing reaction product of the sulfide active aldehyde or ketone. Two such sulfide-active compounds disclosed by Roehm are acrolein and 3-buten-2-one.
Formaldehyde, formaldehyde with SO3−2, and acrolein are all commercially used hydrogen sulfide (H2S) scavengers. However, formaldehyde produces a solid reaction product and reverts readily to formaldehyde and free H2S. Acrolein is more expensive than formaldehyde as well as extremely toxic and dangerous to handle. The use of SO3−2 with formaldehyde eliminates the re-release of H2S but not solids formation.
Despite the prior art approaches to H2S scavenging, the provision of a product that can prevent the H2S formation microbiologically (rather than removal of H2S after it is formed) is highly desirable since it is a more effective way of controlling H2S odor and preventing corrosion and related problems. Existing H2S prevention methods that include utilizing biocides to kill microbes such as Sulfate Reducing Bacteria (SRBs) are non-selective and will kill other microorganisms, and may be detrimental to the wastewater remediation processes. These concerns are effectively negated by the utilization of the hydrogen sulfide prevention methods of the present invention, often combined with a H2S scavenging component chemical.

Method of preventing hydrogen sulfide odor generation in an aqueous medium


A photopolymerizable and photocleavable (P&P) resin monomer is derived from a reactive photoresponsible moiety via various linkages to form photopolymerizable monomers and/or oligomers.

Highly cross-linked polymers have been studied widely as matrices for composites, foamed structures, structural adhesives, insulators for electronic packaging, etc. The densely cross-linked structures are the basis of superior mechanical properties such as high modulus, high fracture strength, and solvent resistance. However, these materials are irreversibly damaged by high stress due to the formation and propagation of cracks. Polymerization stress is originated from polymerization shrinkage in combination with the limited chain mobility. Which eventually leads to contraction stress concentration and gradually such a trapped stress would be released and cause microscopic damage in the certain weak zone like interfacial areas. Macroscopically it was reflected as debonding, cracking, et al. Similarly, the origin of contraction stress in current adhesive restorations is also attributed to the restrained shrinkage while a resin composite is curing, which is also highly dependent on the configuration of the restoration. Furthermore, non-homogeneous deformations during functional loading can damage the interface as well as the coherence of the material. Various approaches have been explored by limiting the overall stress generation either from the restorative materials, or by minimizing a direct stress concentration at the restored interface. It included, for example, new resin, new resin chemistry, new filler, new curing process, new bonding agent, and even new procedure.
There has been tremendous attention paid to new resin matrix development that could offer low polymerization shrinkage and shrinkage stress. For example, various structure and geometry derivatives of (meth) acrylate-based resin systems; non-(meth) acrylates resin systems, non-radical-based resin system. In addition, for light curable, low shrink dental composites, not only new resin systems and new photinitiators, new filler and filter's surface modification have also been extensively explored, such as filler with various particle size and size distribution, from nanometer to micrometer, different shape, irregular as milled or spherical as-made. It can also be different in composition like inorganic, organic, hybrid. Although an incremental improvement has been achieved with each approach and/or their mutual contribution, polymerization stress is still the biggest challenge in cured network systems.
This invention is related to a new kind of resin composition. However, unlike conventional resin system, a new concept is involved in designing such a new resin composition, which would render the polymerization stress in post-gel stage to a subsequent, selective network cleavage in order to have the stress partially released. As mentioned above, all of previous arts towards low shrink and low stress are based on the limitation on the shrink and stress formation in general. However, the shrinkage and stress development in cured network system should have two different stages: a pre-gel phase and a post-gel phase. Actually, most efforts of current arts are focused on the pre-gel stage and some of them were proved to be effective. Unfortunately, these approaches become ineffective in terms to control the stress development in post-gel stage, where the shrinkage is not as much as in the pre-gel stage but the stress turns to much more sensitive to any polymerization extend. It is the immobility nature of the increasing cross-link density within the curing system that leads to the increasing stress concentration within the curing system, period. Even worse, the problem does not stop here and the trapped stress would eventually get relief from slow relaxation, which can create additional damage on a restored system. Therefore, our approach is based on such a concept that in the post-gel stage if some of "closed net" of any cross-linked system can be selectively broken to promote an extended stress relief period, the total stress concentration would be substantially reduced. To fulfill such a task, a photopolymerizable and photocleavable resin is proposed and a general molecular constitution is designed. It was expected that such a resin monomer can be polymerized like any other resin monomer can be polymerized like any other resin monomer but its mainframe is able to be triggered to break upon additional light source such as near UV is blended. This is a typical photocleavable process, but it is its capability to be photopolymerized and embedded into a cross-linked system that makes it unique. In addition, it also makes possible to avoid regenerating any leachable species through such secondary breakage.
Photocleavage is nothing new in solid synthesis of peptides, from which new peptides was directed on certain template in designed sequence, then it was cleaved from its template via a subsequent light exposure. There is no chemical contamination with such a process. On the other hand, photoacid and photobase could be viewed as extended applications for photocleavage. Acidic or basic component is temporally latent to avoid any unwanted interaction with others in the system and they can be released on demand such as light exposure to trigger the regeneration of the acid or base, which then act as normal acidic or basic catalyst for next step reactions. Recently, thermally removable or photo-chemically reversible materials are developed in order to make polymer or polymeric network depolymerizable or degradable for applications such as easily removing of fill-in polymer in MEMS, thermally labile adhesives, thermaspray coatings and removable encapsulation et al. Most recently, photocleavable dentrimers are explored in order to improve the efficiency for drug delivery. Based on our knowledge, there is no prior art involved photocleavable segment in cured network for contract stress control. However, all of those related arts could be used as a practical base to justify this investigation.

Photopolymerizable and photocleavable resins and low shrink and low stress composite compositions


A variable-gain amplifier circuit and a method of changing gain amplifier paths are provided for receiving and amplifying an image sensing signal. The variable-gain amplifier circuit includes variable path and gain amplifier circuits. According to the amplification factor for the image sensing signal, the gain amplifier paths in the variable path and gain amplifier circuits are changed based on a control signal, so as to achieve the appropriate construction of the variable-gain amplifier circuit. The image sensing signal generates the required image result through appropriate numbers of variable gain amplifiers, thereby decreasing the power consumption of the circuit and reducing the design requirement of the circuit.

1. Field of Invention
The present invention relates to a signal amplifier circuit, in which controllable amplifier gain. More particularly, the present invention relates to a variable-gain amplifier circuit and a method of changing the gain amplifier path suitable for receiving and amplifying an image sensing signal, wherein the path of amplifying the image sensing signal is also controllable.
2. Description of Related Art
Complementary metal oxide semiconductor (CMOS) image sensor is an image sensor widely used at present and can be produced by using a standard semiconductor process. Since CMOS devices have the advantages of low power consumption, low cost and can be well integrated with peripheral circuits, the CMOS image sensors have been widely used in many fields such as digital cameras, camera mobile phones, video recorders, security monitor systems, and medical equipments.
Generally, a CMOS image sensor has a variable-gain amplifier circuit with an amplification factor of 8˜24, wherein the factor is subdivided. Based on the consideration of the circuit layout and the linearity of variable gain amplifiers (VGA), the variable-gain amplifier circuit in the CMOS image sensor usually comprises a plurality of VGAs connected in series. As an operational amplifier in the VGA are not optimal, for example, having a limited DC gain and limited bandwidth, the input sensing signal is distorted after passing through each stage of the amplifying circuit. Therefore, in order to reduce distortion, the DC gain and bandwidth of the operational amplifier must be increased. However, the above two characteristics, impacting each other, cannot be improved simultaneously. In addition, after passing through the variable-gain amplifier circuit, the signal must be converted to be digital data by a high-speed analog-to-digital converter (ADC), so the quality of the signal amplified by the VGAs must exceed the resolution of the subsequent ADC. Therefore, the operational amplifier in the preceding VGA must meet a high requirement. To achieve the requirements of a high DC gain and broadband, the operational amplifier usually consumes a large amount of power and occupies a large area of the chip. In another aspect, since the input sensing signal must pass through every stage of VGA to reach the ADC, the gain error of the whole circuit is increased with the increase of the number of amplifiers and the latency of the whole circuit is increased accordingly.
FIG. 1 is a block view of a variable-gain amplifier circuit 100 for receiving and amplifying the image sensing signal in the conventional CMOS image sensor. As shown in FIG. 1, the variable-gain amplifier circuit 100 comprises a VGA 110 and a VGA 120 connected in series. As such, the input sensing signal must pass through the VGA 110 and the VGA 120 to reach an ADC 130. If a feedback factor β1 of the VGA 110 and a feedback factor β2 of the VGA 120 are both 1, the gain of the VGA 110 and the gain of the VGA 120 are both 1, i.e., the output power levels are 0 db. If the DC gain of the operational amplifier in the VGA 110 is A1 and the DC gain of the operational amplifier in the VGA 120 is A2, the gain error generated by the VGA 110 is calculated to be 1/(1+A1) and the gain error generated by the VGA 120 is 1/(1+A2). Thus, after the input sensing signal passes through the VGA 110 and the VGA 120, the signal distortion caused by the gain errors of the above two amplifiers is approximately 1/(1+A1)+1/(1+A2). If the resolution of the ADC 130 is 10 bits, the distortion of the signal input into the ADC 130 must be smaller than one half of the least significant bit (LSB) of the ADC 130 (i.e., ½11). As such, the values of A1 and A2 must be larger than 4096. Besides, if neither of the output power levels of the VGA 110 and the VGA 120 is 0 db, the values of A1 and A2 must be larger.
In the conventional variable-gain amplifier circuit, the way to reduce the signal distortion is to increase the DC gain of the operational amplifier in the VGA while maintaining the bandwidth of the operational amplifier. However, this design method may cause a great increase in the chip area and power consumption of the circuit.

Variable-gain amplifier circuit and method of changing gain amplifier path


A Doppler frequency calculating apparatus that calculates a Doppler frequency, which is the magnitude of a time-dependent fluctuation of a characteristic of the transmission path through which an orthogonal frequency-division multiplexing (OFDM) signal is transmitted, includes a received signal point memory operable to store a received signal point of a sub-carrier having a reference carrier signal of the OFDM signal, a modulated component eliminating section operable to eliminate a modulated component from the received signal point stored in the received signal point memory, and a Doppler frequency calculating section operable to calculate a Doppler frequency by performing frequency analysis on the received signal point of each sub-carrier from which the modulated component has been eliminated by the modulated component eliminating section.

1. Field of the Invention
The present invention relates to a Doppler frequency calculating apparatus and method that calculates a Doppler frequency, which is the magnitude of a time-dependent fluctuation of the characteristic of a transmission path for receiving an orthogonal frequency division multiplexing (OFDM) signal in motion, for example, and an OFDM demodulating apparatus that performs equalizing processing by using the calculated Doppler frequency.
2. Description of the Related Art
Digital signals may be transmitted by a modulating method called Orthogonal Frequency Division Multiplexing method (called OFDM method hereinafter). In OFDM method, data is assigned and is digitally modulated to the amplitude and phase of each of many orthogonal sub-carriers within a transmission band by PSK (Phase Shift Keying) or a QAM (Quadrature Amplitude Modulation).
In OFDM method, the total transmission speed is the same as that of a modulation method in the past though the modulation speed decreases since the transmission band is divided by the multiple sub-carriers and the band for each sub-carrier is narrow. Furthermore, in OFDM method, the symbol speed decreases since many sub-carriers are transmitted in parallel, and the relative time length of multipath can be shorter than the symbol time length, resulting in the resistance to multipath interference.
Still further, in OFDM method, since data is assigned to multiple sub-carriers, a transmitting/receiving circuit may include an IFFT (Inverse Fast Fourier Transform) calculating circuit that performs inverse Fourier transform upon modulation and an FFT (Fast Fourier Transform) calculating circuit that performs Fourier transform upon demodulation.
For these characteristics, OFDM method may often be applied in terrestrial digital broadcasting, which is susceptible to multipath interference. For example, the standards for the terrestrial digital broadcasting adopting such OFDM method may include DVB-T (Digital Video Broadcasting-Terrestrial) and ISDB-T (Integrated Services Digital Broadcasting-Terrestrial).
The transmission symbol in OFDM method (called OFDM symbol hereinafter) includes, as shown in FIG. 10, a valid symbol and a guard interval. The valid symbol is a signal period when IFFT is performed upon transmission. The guard interval is a copy of the waveform of a part of the second half of the valid symbol. The guard inertial is provided in the first half of the OFDM symbol. The existence of the guard interval in OFDM method allows the inter-symbol interference due to the multipath, which improves the multipath resistance.
For example, in Mode 3 of ISDB-TSB standard (which is a broadcasting standard adopted in Japan for terrestrial digital voice broadcasting. See "Chijo Dejitaru Onsei Hosoyo Jushin Souchi Hyoujun Kikaku (Nozomashii Shiyou) (Standard Specification (Desirable Standard) of Receiving Apparatus for Terrestrial Digital Voice Broadcasting) ARIB STD-B30", Association of Radio Industries and Business, a valid symbol contains 512 sub-carriers, and the sub-carrier interval is 125/126≈0.992 kHz. In Mode 3 of the ISDB-TSB standard, 433 sub-carriers of 512 sub-carriers within a valid symbol are modulated by transmission data. In Mode 3 of ISDB-TSB standard, the time length of a guard interval is one of ¼, ⅛, 1/16 and 1/32 of the time length of the valid symbol.
OFDM method defines that one OFDM frame, which is a transmission unit, includes a collection of multiple OFDM symbols as described above. For example, in ISDB-TSB standard, one OFDM frame includes 204 OFDM symbols. In OFDM method, the position to which a pilot signal is to be inserted may be defined in the OFDM frame units, for example.
In OFDM method adopting QAM modulation as a modulation method for each sub-carrier, the characteristics of the amplitude and phase may differ among sub-carriers when the signals carried and modulated in the sub-carriers are distorted by the influence of the multipath upon transmission. Accordingly, received signals may need to be wave-equalized in a receiver side such that the amplitudes and phases of the sub-carriers can be equal. In OFDM method, a sender side scatters pilot signals with a predetermined amplitude and a predetermined phase within a transmission symbol in a transmitted signal while the receiver side monitors the amplitude and phase of the pilot signals, calculates the frequency characteristic of the transmission path, and equalizes the received signal by using the calculated characteristic of the transmission path. In OFDM method, a scattered pilot (SP) signal and/or a continual pilot (CP) signal, which will be described later, may be used as a pilot signal, which is to be used for calculating the characteristic of a transmission path.
FIG. 11 shows an arrangement pattern of SP signals within an OFDM symbol, which is adopted in ISDB-T standard.
In ISDB-T standard, one BPSK-modulated SP signal is inserted every 12 sub-carriers in the sub-carrier direction (frequency direction). Furthermore, in DVB-T standard or ISDB-T standard, the position where the SP signal is inserted is shifted in the frequency direction by three sub-carriers in each OFDM symbol. As a result, an SP signal is inserted every four OFDM symbols in one sub-carrier in the OFDM symbol direction (time direction)
In this way, in ISDB-T standard, an OFDM symbol is inserted with SP signals spatially scattered, whereby the redundancy of the SP signals is lowered for original information.
By the way, when the transmission path characteristic is calculated by using the SP signal, the characteristic can be specified for the sub-carrier to which SP signals are inserted. However, the characteristics may not be directly calculated for the other sub-carriers, that is, the other sub-carriers including original information. Therefore, the receiver side estimates the transmission path characteristics of the other sub-carriers including original information by filtering SP signals through a two-dimensional interpolation filter.
The processing of estimating a transmission path characteristic through a two-dimensional interpolation filter is generally performed as follows.
That is, in order to perform the processing of estimating a transmission path characteristic, the information component is eliminated from a received OFDM signal, and SP signals inserted at the positions shown in FIG. 11 are only extracted.
Next, the modulated component of each of the extracted SP signals is eliminated by using a reference SP signal. The SP signal from which the modulated component is eliminated exhibits the transmission path characteristic of the sub-carrier to which the SP signal is inserted.
Next, the SP signal from which the modulated component is removed is input to an interpolation filter in the time direction and undergoes time direction interpolation processing therein, whereby the transmission path characteristic of the sub-carrier including the SP signal is estimated for every OFDM symbol. As a result, as shown in FIG. 12, the transmission path characteristic of every three sub-carriers can be estimated in the frequency direction for all OFDM symbols.
Next, as shown in FIG. 13, the SP signal interpolated in the time direction is input to an interpolation filter in the frequency direction and undergoes frequency direction interpolation processing through three-times oversampling, whereby the transmission path characteristic of all sub-carriers within the OFDM symbol is estimated. As a result, the transmission path characteristic of all sub-carriers of the received OFDM signal can be estimated.
Since the transmission path characteristic fluctuates depending on time when an OFDM signal is received in motion, the estimation of the transmission path characteristic with an SP signal is difficult. For example, time-direction interpolation processing may be performed on an SP signal when the Doppler frequency, which is the magnitude of the time-dependent fluctuation of the transmission path characteristic, is large. In this case, since the Nyquist condition is not satisfied, a wrong estimation result is obtained for the transmission path characteristic. Then, it is proposed in the past that a Doppler frequency is calculated based on speed information from a speedometer, and the transmission path characteristic is corrected in accordance with the magnitude of the calculated Doppler frequency (see JP-A-10-75226).
However, with the Doppler frequency calculating method by using a speedometer in the past, a Doppler frequency may not be calculated if speed information is not available from the speedometer.
Accordingly, it is desirable to propose a Doppler frequency calculating apparatus and method, which allows the calculation of a Doppler frequency without a speedometer and an OFDM demodulating apparatus that performs equalizing processing by using the calculated Doppler frequency.

Doppler frequency calculating apparatus and method and OFDM demodulating apparatus


A method is presented for performing authentication operations. When a client requests a resource from a server, a non-certificate-based authentication operation is performed through an SSL (Secure Sockets Layer) session between the server and the client. When the client requests another resource, the server determines to step up to a more restrictive level of authentication, and a certificate-based authentication operation is performed through the SSL session without exiting or renegotiating the SSL session prior to completion of the certificate-based authentication operation. During the certificate-based authentication procedure, an executable module is downloaded to the client from the server through the SSL session, after which the server receives through the SSL session a digital signature that has been generated by the executable module using a digital certificate at the client. In response to successfully verifying the digital signature at the server, the server provides access to a requested resource.

1. Field of the Invention
The present invention relates to an improved data processing system and, in particular, to a method and apparatus for multicomputer data transferring. Still more particularly, the present invention provides a method and apparatus for multicomputer communication using cryptography.
2. Description of Related Art
E-commerce web sites and web applications perform transactions over computer networks on behalf of users. A user must often pass through an authentication procedure in order to prove the user's identity to an appropriate level of certainty for security purposes.
Many computer systems have different types of authentication for different levels of security. For example, after a successful completion of a first level of authentication in which a correct username and password combination is provided by a user, a system may provide access to a particular set of resources on a web site. A second level of authentication might require a user to present a hardware token, e.g., a smartcard, after which the user is provided access to more tightly controlled resources on the web site. A third level of authentication might require the user to provide some form of biometric data, e.g., through a fingerprint scan or a retina scan, after which the system provides access to very sensitive or confidential resources on a web site.
The process of moving up from one authentication level to the next level is termed "step-up authentication". In other words, the user steps from one level of authentication up to a higher level as required by a system in order to gain access to more sensitive resources.
In an e-commerce web-based environment, computer systems often implement authentication services as a form of front door or sentry gate for accessing a web site. These authentication services sit in front of applications, i.e. between the user and the applications, to ensure that the user is authenticated before obtaining access to any resources. These authentication services may be implemented as a web server plug-in, a reverse proxy, or other similar technology. A potential problem with these authentication services is that they often use username/password authentication and cannot step up to authentication methods that use client-based certificates. A certificate-based authentication procedure is generally considered to achieve a higher level of security than a username/password-based authentication procedure.
Certificate-based authentication involves the use of public/private asymmetric cryptographic key pairs; a digital certificate binds a certified user's identity with a public cryptographic key. During a certificate-based authentication procedure, the user provides his or her digital certificate to an authentication service, and the user is required to prove that the user has access to a private cryptographic key that corresponds to the public key. For example, the authentication service provides some form of challenge data to the user's client computer, which then signs the challenge data with the user's private cryptographic key, and the authentication service can verify the digital signature with the user's public key. If the authentication service determines that the challenge data was properly signed with the user's private key, then the authentication service has verified the identity of the user to a high degree because the private key should always be kept secret by the user whose identity is stored in the certificate.
The operation of stepping up to a certificate-based authentication procedure is often not possible. A problem typically arises because a mutually authenticated SSL session has already been established between the client and the server for a lower-level of non-certificate-based authentication, such as a username/password combination. If the authentication service that requires the certificate-based authentication procedure does not have control over the SSL stack, which is the case with most commercially available products, e.g., it may be embedded within the operating system in some manner, then the authentication service cannot force the establishment of a new SSL session. Hence, the authentication service cannot step up from a username/password-based authentication procedure that has already occurred over an active SSL session to a certificate-based authentication procedure while maintaining the active SSL session.
Therefore, it would be advantageous to have a method and a system that can step up from a non-certificate-based authentication procedure to a certificate-based authentication procedure without exiting or renegotiating a previously established SSL session in order to obtain a higher level of security that is required by an authentication service for some purpose.

Method and system for stepping up to certificate-based authentication without breaking an existing SSL session

International Business Machines Corporation


An exemplary foldable electronic device includes a first cover, a second cover coupled to the first cover and a latch mechanism. The latch mechanism includes a hooking portion disposed on the first cover and a latching portion formed on the second cover. The hooking portion has a hook, the latching portion has a latching slot, an unlatching slot, and a sliding slot connecting the latching slot and the unlatching slot. The hook is deformable to capable of latching the latching slot or unlatching from the latching portion when sliding to the unlatching slot along the sliding slot.

1. Field of the Invention
The present invention generally relates to foldable electronic devices and, particularly, to a foldable electronic device having a top cover and a main body.
2. Discussion of the Related Art
Referring to FIGS. 4 and 5, a typical housing 80 of a foldable electronic device is shown. The housing 80 includes a main body 81, a top cover 82, a sliding member 83, a hook 84, and a spring 85. The main body 81 defines a latching groove 811 adjacent to a side of the main body 81. The top cover 82 defines a rectangular mounting groove 821 in a side of the top cover 82 and forms a resisting member 823 that is adjacent to the mounting groove 821. The sliding member 83 is disposed in the mounting groove 821 and is capable of sliding, left or right, along the mounting groove 821. The hook 84 is configured to be latched in the latching groove 811. The hook 84 includes an end that is fixed to the sliding member 83 so that the hook 84 is movable together with the sliding member 83. One end of the spring 85 abuts the resisting member 823 and the other end of the spring 85 abuts the hook 84 so that the hook 84 and the sliding member 83 are normally forced to remain on the left side of the mounting groove 821.
To open the top cover 82, a user has to slide the sliding member 83 towards the right side of the mounting groove 821. However, the sliding member 83 is generally designed to be inconspicuous, thereby having a small outer surface area and the outer surface of the sliding member 83 may line up with the surface of the edge (side) of the cover. Thus when sliding the sliding member 83 with a finger to open the top cover 82, the finger may slip. As a result, opening the top cover 82 maybe bothersome.
Therefore, a new foldable electronic device is desired in order to overcome the above-described shortcomings.

Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd.


A conveyor system for a working machines such as a cold planer is disclosed. The working machine that can optionally have a frame, a rotor moveable relative to the frame to remove material from a surface of a working area and the conveyor system. The conveyor system can optionally include a first belt and a second belt. The conveyor system can be positioned to receive loose material from the rotor and transport the loose material relative to the frame away from the rotor. Optionally, the second belt can be positioned adjacent to and extending along the first belt and moveable relative to the frame.

Asphalt-surfaced roadways are built to facilitate vehicular travel. Depending upon usage density, base conditions, temperature variation, moisture levels, and/or physical age, the surfaces of the roadways eventually become misshapen and unable to support wheel loads. In order to rehabilitate the roadways for continued vehicular use, spent asphalt is removed in preparation for resurfacing.
Cold planers, sometimes also called road mills or scarifiers, are used to break up and remove layers of an asphalt roadway. A cold planer typically includes a frame propelled by tracked or wheeled drive units. The frame supports an engine, an operator's station, a milling drum or rotor, and conveyors. The milling drum, fitted with cutting tools, is rotated through a suitable interface with the engine to break up the surface of the roadway. The broken up roadway material is deposited by the milling drum onto a conveyor, which transfer the broken up material into haul trucks for removal from the worksite. As haul trucks are filled, they are replaced with empty haul trucks. The filled trucks transport the broken up material to a different location to be reused as aggregate in new asphalt or otherwise recycled. This transport process repeats until the milling process is finished.
With conventional conveyors a continuous belt is positioned over a series of rollers, one or more of which is powered. Flashings can be provided at the lateral edges of the belt to create a seal and prevent material from being dislodged and falling from the belt before reaching the extreme end. These flashings are fixed in place while the belt moves. Examples of such flashings are provided in Great Britain Patent Application Publication 912,985A and U.S. Patent Application Publication No. US20080121495A1. These disclosed flashings are either fixed or can configured to be repositioned (e.g., deflected or tilted) relative to the belt if desired.
While the flashings of these publications are effective in containing material, they have drawbacks. In particular, the moving nature of the main belt along with the fixed nature of the flashings creates wear of the flashing over time. Eventually this can impact the effectiveness of the seal created by the flashings with the main belt.
The conveyor system of the present disclosure solves one or more of the problems set forth above and/or other problems in the art.

Conveyor system for material transport on cold planer


Embodiments related to outputting spatial audio via a portable computing device are presented. For example, one disclosed embodiment provides a portable computing device for wirelessly detecting a presence of a remote speaker external to the portable computing device, determining a location of the remote speaker, and establishing a wireless connection with the remote speaker. The embodiment further includes presenting visual content via a display of the portable computing device, the visual content comprising an object positionally associated with a location in a real-world environment around the portable computing device, generating an audio signal corresponding to the object, and sending the audio signal to the remote speaker.

An entertainment environment may include various different sound sources and audio output devices. For example, a home entertainment environment may include a television, a stereo, a desktop computer, a video game console, one or more mobile devices (e.g. smartphone, tablet, laptop, etc.), and each of these devices may output sound through one or more associated speakers.


A power supply module package suitable for both high packaged power density and cost effective manufacture. In an exemplary embodiment, the power supply module includes: (1) at least one printed circuit board containing conductors for interconnecting components of the power supply, (2) a thermally conductive baseplate or case operable for transferring heat generated inside the module to the outside environment, wherein the external package dimensions are of a sufficiently small size to allow the user the greatest flexibility in the design of the overall circuit assembly, (3) at least one power magnetic device operable for providing electrical isolation between the input and the output of the power module, and (4) a set of electrical leads to facilitate communication and power flow between the module and circuitry being powered. The present invention provides a highly compact, thermally conductive package for a power supply module (perhaps a DC/DC converter) that is cost effective, readily manufacturable, durable, and easily mounted to a circuit card, allowing the power module to, for example, form a portion of a distributed power architecture.

The trend in the design of power systems for electronic assemblies has been toward the use distributed power architectures. In a distributed power system, many small, individual board mounted power supply modules are used in place of a few larger, centralized power supplies. Such a distributed power architecture could be used to power a diverse variety of electronic assemblies, including, for example, a computer work station, a file server, or a telecommunications switching system. Each of the board mounted power modules is conveniently located close to the circuitry being powered, often with one or more power modules located on each circuit card in the electronic assembly. It is advantageous to minimize the size of the individual power modules, as the circuit card space used by the power module could be used, for example, for additional circuitry to increase the processing throughput of a computer card, or to increase the switching capacity of a telecommunications card. Therefore, a power module which has a relatively large footprint area is generally considered undesirable. Additionally, many electronic assemblies employ circuit card to circuit card spacing of less than one inch. Minimizing the card to card spacing allows for a denser assembly, which advantageously increases throughput or capacity. It is therefore desirable to provide a power module with the additional attribute of a low height profile.
Consequently, the trend in the design of power supply modules has been toward achieving increased output power along with a lower height profile and a smaller footprint area, thereby increasing power density. However, any improvements in power level, power density or profile cannot be at the expense of the thermal and electrical characteristics of the overall power module and its constituent internal devices.
A power supply module is conventionally constructed as a unitary, encapsulated package, with one or more rows of leads to connect the module to a circuit card, and a metallic case containing attachment mounts for an external heatsink. The internal construction of the power module often comprises one or more power devices (e.g., transistors and diodes) in thermal communication with the metal case, one or more magnetic devices (e.g., transformers and inductors) providing electrical isolation and energy storage, and one or more circuit boards containing electronic components to, among other things, provide control and monitoring functions.
Using a DC/DC power converter as an example, a simplified internal structure of a conventional power module package will hereinafter be described. The packaged power devices and magnetic devices that must be thermally managed due to high power dissipation are mounted onto a metal circuit board employing an insulated metal substrate technology, such as a THERMAL CLAD substrate manufactured by the Bergquist Corporation of Minneapolis, Minn. The metal circuit board also contains components for filtering and control. The remainder of the filtering and control components are mounted to a conventional FR4 printed circuit board, which is mechanically and electrically connected to the metal circuit board to facilitate communication and power flow between various parts of the power supply module. Leads allowing for communication and power flow between the power module and the external circuit card are mechanically and electrically fastened to one or both of the circuit boards in the power module. The power module is cased in a plastic or metallic enclosure which receives an encapsulant operable for protecting the internal components from contaminants and perhaps to improve heat flow between the internal components and the enclosure. The enclosure also contains means for attaching an external heatsink.
While the aforementioned internal structure provides a viable alternative for packaging a power supply module, it endures several limitations. First, it requires two printed wire boards to accommodate components and interconnection traces, e.g., the metal circuit board and the FR4 circuit board. Such a two board design increases the cost of the module and increases complexity of assembly. Second, the module employed discrete magnetic devices and did not incorporate planar magnetics into the printed circuit board. The use of planar magnetics can reduce the size of the design by allowing components to be placed directly on top of transformer and inductor windings, thus effectively making double use of the available internal space. Planar magnetics can also reduce the cost of the module. Third, the packaged power density is low. Finally, the design requires several iterative manual steps that are not consistent with a mass producible and cost effective design for a power supply module.
Accordingly, what is needed in the art is a power supply module which simultaneously achieves the requirements of high packaged power density and cost effectiveness, without sacrificing the thermal and electrical characteristics of the device. Preferably, the aforementioned power supply module should present a user with the minimum number of features and functions required to provide tight tolerance remote voltage regulation, protection during a fault or trouble condition, and external control of the power supply module.