A template operable to reestablish the center of rotation of a native femoral head at the head of an implanted prosthesis. The template includes a first member with a marking passage and optional cutting guide and a second member with a target. The first member of the template can be placed on a femur and the second member can be moved in the proximal-distal, medial-lateral and anterior-posterior directions to fix the center of the target at the center of rotation of a femoral head. The head of a prosthesis can be manipulated to come in contact with the target to reestablish the center of rotation of the native femoral head.

This section provides background information related to the present disclosure which is not necessarily prior art.
During reconstruction of a hip, it is often desirable to reestablish a native head center of a femur with an implanted prosthesis. During a medical procedure, the native head of a femur is often resected early in the procedure, which makes it difficult to position a head center of the prosthesis at the same location and orientation as the native head center of the femur. Generally, a trial prosthesis can be used to approximate or test establishment of a head center during a procedure.

Method and apparatus for determining a location


Integrated circuit arrangement having first and second signal input pads, to which a differential input signal is applied, and first and second signal outputs, at which a differential output signal is provided. The first signal output is coupled to the first signal input pad and the second signal output is coupled to the second signal input pad. A first capacitance is between the first and second signal input pads. First and second inductances are connected in series, are between the first and second signal input pads, and are connected in parallel with the first capacitance. A first terminal is at a first supply potential and a second terminal is at a second supply potential. A first electrostatic discharge element is between the first and second terminals. A second electrostatic discharge element is between the first terminal, on the one hand, and the first and second inductances, on the other hand.

"Electrostatic Discharge" (ESD) describes the processes and effects when electrical charges are equalized between two differently charged components. If the latter come into contact with one another, positive and negative charges are exchanged, and this may give rise to damage in an electrical circuit.
In an integrated circuit, an upper operating potential VDD and lower operating potential VSS are provided, between which provision is made of protection mechanisms for avoiding damage on account of ESD.
ESD, that is to say electrostatic discharges, are often the cause of damage to or destruction of an integrated circuit and thus cause high financial damage. The development of MOS technology (metal oxide semiconductor) in microelectronics has been accompanied by a miniaturization of the semiconductor components at increasingly high clock rates. This results in a rising sensitivity towards ESD pulses, that is to say high voltage and current spikes of such clock signals. Semiconductor components under ESD stress can cause errors in an integrated circuit. ESD can lead to a total failure of or damage to the component. Therefore, protection against electrostatic discharges (ESD protection) is important nowadays in all areas of microelectronics.
ESD protection in radiofrequency circuitry applications is a difficult technical problem, since the high parasitic capacitance of ESD protection elements inherently greatly restricts the maximum operating frequency that can be achieved for the circuit. Such ESD protection elements are, for example, a diode, a thyristor or a grounded n-MOS component (that is to say an n-MOS field effect transistor with a gate terminal at the electrical ground potential). Smaller ESD protection elements would enable higher frequencies, but do not sufficiently satisfy the functionality as ESD protection, that is to say are not sufficiently able to dissipate ESD currents.
A description is given below, referring to FIG. 1, of a circuit arrangement 100 with ESD protection in accordance with the prior art.
In the case of the circuit arrangement 100, an input signal can be provided at a signal input pad 101 and be fed to an input/output circuit 102. In order to supply the circuit arrangement 100 with electrical energy, a supply potential 103 VDD is provided, and an electrical ground potential 104 GND. A first ESD protection element 105 is provided between the signal input pad 101 and the supply potential 103 VDD. Furthermore, a second ESD protection element 106 is provided between the signal input pad 101 and the electrical ground potential 104.
Furthermore, FIG. 1 shows a circuit arrangement 110, which has, in addition to the components of the circuit arrangement 100, a nonreactive resistor 111 between the signal input pad 101 and the input/output circuit 102.
FIG. 1 clearly shows circuit arrangements 100, 110 having protection against high voltages through the provision of the ESD protection elements 105, 106, since the latter electrically decouple the supply potential 103 VDD from the ground potential 104 GND.
In the case of a large electric current intensity, the ESD elements 105, 106 have to be sufficiently large. In radiofrequency applications, however, large ESD elements lead to an undesirable large parasitic capacitance.
Approaches for ESD protection circuit arrangements for radiofrequency circuits are disclosed in (1) Ming-Dou Ker at al., EOS/ESD-Symp. Proceedings 2003, pages 204-213, (2) Vassilev, V et al., EOS/ESD-Symp. Proceedings 2003, pages 195-203, (3) Hyvonen et al., EOS/ESD-Symp. Proceedings 2003, pages 188-194, (4) Galai, S, Razavi, B "Broadband ESD Protection Circuits in CMOS-Technology", Proceedings ISSCC 2003, Paper 10.5, (5) Leroux, P, Steyaert, M "A high performance 5.2 GHz LNA with an on-chip inductor to provide EDS-protection", IEE Electronics Letters, Volume 37, No. 1, pages 467-469, March 2001, (6) Leroux, P, Janssens, J, Steyaert, M "A 0.8 dB NF ESD-protected 9 mW CMOS LNA", ISSCC Dig. Tech. Papers, Volume 26, pages 410-411, 2001, (7) Mahdavi, S, Abidi, A "Fully integrated 2.2-mW CMOS Front End for a 900-MHz Wireless Receiver", IEEE JSSC, 05/2002, and (8) Liebermann, T, Tiebout, M "A Low Phasenoise, Differentially Tuned, 1.8 GHz Power VCO with an ESD-compatible 14 dBm Output Stage in Standard Digital CMOS", ESSCIRC Proceedings, Villach, 09/2001.
The approach disclosed in Leroux, P, Steyaert, M "A high performance 5.2 GHz LNA with an on-chip inductor to provide EDS-protection", IEE Electronics Letters, Volume 37, No. 1, pages 467-469, March 2001, Leroux, P, Janssens, J, Steyaert, M "A 0.8 dB NF ESD-protected 9 mW CMOS LNA", ISSCC Dig. Tech. Papers, Volume 26, pages 410-411, 2001, and Mahdavi, S, Abidi, A "Fully integrated 2.2-mW CMOS Front End for a 900-MHz Wireless Receiver", IEEE JSSC, 05/2002, essentially consists in using smaller ESD protection elements.
FIG. 2 shows an ESD protection circuit 200 such as is disclosed in Mahdavi, S, Abidi, A "Fully integrated 2.2-mW CMOS Front End for a 900-MHz Wireless Receiver", IEEE JSSC, 05/2002.
FIG. 3 shows an ESD protection circuit arrangement 300 disclosed in Leroux, P, Janssens, J, Steyaert, M "A 0.8 dB NF ESD-protected 9 mW CMOS LNA", ISSCC Dig. Tech. Papers, Volume 26, pages 410-411, 2001, in the case of which arrangement the ESD protection is realized by means of a first ESD protection diode 201 and by means of a second ESD protection diode 302.
The approaches in accordance with Leroux, P, Steyaert, M "A high performance 5.2 GHz LNA with an on-chip inductor to provide EDS-protection", IEE Electronics Letters, Volume 37, No. 1, pages 467-469, March 2001, Leroux, P, Janssens, J, Steyaert, M "A 0.8 dB NF ESD-protected 9 mW CMOS LNA", ISSCC Dig. Tech. Papers, Volume 26, pages 410-411, 2001, and Mahdavi, S, Abidi, A "Fully integrated 2.2-mW CMOS Front End for a 900-MHz Wireless Receiver", IEEE JSSC, 05/2002, have the disadvantage, however, that they usually have only low ESD strength, and that the range of processable radio frequencies with which the circuit arrangements can be operated is restricted. At higher frequencies such as 5 GHz or 17 GHz such as are used for WLAN systems ("wireless local area network") these approaches are thus only poorly suitable or no longer suitable at all.
An alternative approach in accordance with Ming-Dou Ker at al., EOS/ESD-Symp. Proceedings 2003, pages 204-213, Vassilev, V et al., EOS/ESD-Symp. Proceedings 2003, pages 195-203, Hyvonen et al., EOS/ESD-Symp. Proceedings 2003, pages 188-194, and Galai, S, Razavi, B "Broadband ESD Protection Circuits in CMOS-Technology", Proceedings ISSCC 2003, Paper 10.5essentially consists in decoupling the ESD protection elements using LC resonant circuits realized on-chip, or in tuning the capacitance of each ESD element in an LC resonant circuit.
The ESD protection circuit arrangement 400 shown in FIG. 4 represents a solution such as is disclosed in Galai, S, Razavi, B "Broadband ESD Protection Circuits in CMOS-Technology", Proceedings ISSCC 2003, Paper 10.5. The ESD protection circuit arrangement 400 is provided with a first ESD protection subcircuit 401 and a second ESD protection subcircuit 402, an ESD capacitance 403 representing a (parasitic) capacitance of the ESD protection elements 401, 402.
What is disadvantageous about the approach in accordance with Ming-Dou Ker at al., EOS/ESD-Symp. Proceedings 2003, pages 204-213, Vassilev, V et al., EOS/ESD-Symp. Proceedings 2003, pages 195-203, Hyvonen et al., EOS/ESD-Symp. Proceedings 2003, pages 188-194, and Galai, S, Razavi, B "Broadband ESD Protection Circuits in CMOS-Technologyis the high area requirement of the integrated inductances.
In the case of the ESD protection circuit arrangement 500 disclosed in Liebermann, T, Tiebout, M "A Low Phasenoise, Differentially Tuned, 1.8 GHz Power VCO with an ESD-compatible 14 dBm Output Stage in Standard Digital CMOS", ESSCIRC Proceedings, Villach, 09/2001, which is shown in FIG. 5, an inductance is used instead of traditional ESD protection elements. ESD protection is clearly achieved by means of the standard ESD protection elements coupled to the supply voltage.
Consequently, the ESD protection circuit arrangement 500 is provided with a first inductance 501 and a second inductance 502, but also a capacitance 503. Furthermore, a plurality of signal inputs 101 and a plurality of signal outputs 102 are provided.
The problem of effective ESD protection is particularly pronounced in the context of a differential circuit in the case of an ESD discharge between two differential radiofrequency input/output pins (RF I/O pins). Conventional ESD protection of the radiofrequency input/output pins against local supply potentials leads to particularly high voltage drops across an ESD protection path.
A description is given below, referring to FIG. 6, of a circuit arrangement 600 in accordance with the prior art, which reveals the particular jeopardization of a differential RF input circuit in the case of one ESD discharge between two differential RF pins (IN and IP).
The circuit arrangement 600 contains a first signal input pad 601 (IN) and a second signal input pad 602 (IP) between which a differential input signal can be provided. A differential output signal can be provided between a first signal output 603 (ON) and a second signal output signal 604 (OP). The first signal input pad 601 is coupled to the gate region of a first n-MOS field effect transistor 605, the first source/drain region of which is coupled to a current source 607 and the second source/drain region of which is coupled to the first signal output 603. The second signal input pad 602 is coupled to the gate region of a second n-MOS field effect transistor 606, the first source/drain region of which is coupled to the current source 607 and the second source/drain region of which is coupled to the second signal output 604. A second terminal of the current source 607 is brought to the ground potential 104 VSS. Three ESD protection paths are formed between the supply potential 103 VDD and the ground potential 104 VSS. A first ESD protection path comprises a first ESD protection diode 608 and a second ESD protection diode 609. A second ESD protection path comprises a third ESD protection diode 610 and a fourth ESD protection diode 611. A third ESD protection path comprises an ESD protection element 612, which may be a thyristor for example. As shown by way of example in FIG. 6, in the event of a positive discharge from the RF input pin IN 601 with respect to the second RF input pin IP 602, the ESD current is passed via three protection elements in series (protection diodes 608, 609 at IN, protection element 612 between VDD and VSS, protection diodes 610, 611 at IP). The high voltage drop arising in this case may lead to the breakdown of the two gate insulating layers of the input transistors 605, 606, that is to say to an undesirable current flow between the gate regions of the transistors 605, 606, and may thus destroy the circuit arrangement 600. Conventionally, this problem can only be combated by inserting additional protection elements, which would degrade the performance of the circuit on account of the additional capacitance per unit length.
DE 102 39 230 A1 discloses a radiofrequency semiconductor device in which an ESD protection circuit is connected to a node forming a branch junction of a radiofrequency signal input/output line, one end of the radiofrequency signal input/output line being connected to a radiofrequency input/output pad, the other end of the radiofrequency input/output line being connected to an internal circuit, and a DC blocking capacitor being connected in series between the node and the internal circuit.


Disclosed are methods of increasing exogenous protein expression in a cell or a transgenic plant. Constructs, i.e., vectors, DNA fusions and polynucleotides, for use in conjunction with the methods to cause increased exogenous protein expression are also disclosed. These constructs generally include intron 1 and/or intron 2 of the PAT1 gene. Additionally disclosed are cells, including recombinant cells, and plant lines transformed with the described constructs. In particular, a cultivated, transgenic food plant, the genome of which has been augmented through the genomic introduction of a preselected exogenous protein gene not found in the genome of non-transformed parentage of the plant is described. Also described are seed, progeny and cells of the described transgenic food plant.

I. Field of the Invention
The present invention relates to the expression of exogenous proteins in plants. In particular, this invention relates to the use of downstream elements, specifically introns, to enhance expression of certain desired exogenous proteins in plants. Additionally, this invention relates to the use of methods to enhance expression of proteins of pharmacological interest in food plants. Methods and compositions for the enhancement of protein expression in plants and plant cells are disclosed.
II. Description of Related Art
The amount of protein that is synthesized from a gene is a function of several complex and interacting processes. Transcription, RNA maturation, and translation are each comprised of a large number of events, all of which are potentially regulated either independently or in concert. It is widely recognized that the upstream elements that control transcription and translation have very significant roles in determining the quantity, timing, and tissue specificity of gene expression. However, the sequences that are required for other aspects of expression (such as RNA processing) could be of equal or greater importance, and might be located in virtually any part of a gene.
While an enormous amount of research has demonstrated the importance of 5'elements in controlling gene expression, evidence shows that sequences downstream of the start of transcription can also have a major influence on the level or pattern of expression of plant genes. These elements include protein coding sequences (De Almeida et al., 1989; Douglas et al., 1991), introns (Callis et al., 1987; Clancy et al., 1994), and 5' or 3' transcribed but untranslated sequences (Dean et al., 1989; Larkin et al., 1993; Ulsamov and Folk, 1995). Despite the documented importance of downstream elements on gene expression, these regions are included in only a minority of reporter gene fusions designed to investigate the expression pattern of a gene.
The use of intronic portions of genes to aid in gene expression has also been reported for certain genes. For example, Callis et al. reported that at least the first intron of the maize (Zea mays L.) alcohol dehydrogenase -1 (Adh1) gene was probably required for significant levels of expression. (Callis et al., 1987). Further, Callis et al. reported that the position of the first intron with respect to the chimeric chloramphenicol acetyl transferase (cat) gene to be expressed was important to the level of expression observed. Illustrative of this point are the pACI.sub.1 I.sub.8,9 A and pAI.sub.1 CI.sub.8,9 A constructs wherein A represents Adh1, I.sub.X represents intron number x and C represents the cat gene. The construct wherein intron 1 was located upstream from the CAT gene showed a 110-fold increase in transient gene expression relative to pACI.sub.8,9 A, but a 21-fold increase relative to pACI.sub.1 I.sub.8,9 A (i.e., 110-fold relative to a construct lacking the first intron, but 21-fold relative to one in which the first intron is downstream of the cat gene).
It has also been shown that compositions comprising the Zea mays L. (maize) Sh1 first intron fused to short sections of the flanking exons increases transient reporter gene expression in protoplasts of several grass species (Vasil et al., 1989). Further, Clancy et al. (1994) showed that in some instance, variations can be made in the intron structure and length without affecting the rate of enhancement of protein expression. Nevertheless, it is also known that not all genes containing introns require the presence of introns for efficient expression. For example, Chee et al., (1986) showed that removal of introns from bean phaseolin genes transferred to tobacco did not affect the expression of phaseolin protein in callus tissue.
The histochemical staining patterns previously reported for intronless GUS fusions to the tryptophan pathway genes TSB1, TSB2, ASA1, and ASA2 are similar to the patterns seen in lines containing an intronless GUS fusion to the tryptophan pathway gene PAT1 (Niyogi, 1993; Pruitt and Last, 1993). In light of the poor expression of PAT1-GUS in the absence of an intron detailed below, it seems plausible that these fusions might under-represent the expression of the genes under study. Consistent with this hypothesis, results analogous to those reported for PAT1-GUS fusions with and without introns were obtained for all three of the Arabidopsis genes encoding the next tryptophan pathway enzyme, phosphoribosylanthranilate isomerase (J. Li and R. L. Last, unpublished data). In each case, GUS fusions containing introns and the transit peptide give much more intense and widespread histochemical staining in transgenic plants than fusions lacking introns and the transit peptide.

Methods and compositions for enhancing the expression of genes in plants

Boyce Thompson Institute for Plant Research, Inc.


Compounds of formula (I):

Hepatitis C virus (HCV) is the major etiological agent of post-transfusion and community-acquired non-A non-B hepatitis worldwide. It is estimated that over 200 million people worldwide are infected by the virus. A high percentage of carriers become chronically infected and many progress to chronic liver disease, so-called chronic hepatitis C. This group is in turn at high risk for serious liver disease such as liver cirrhosis, hepatocellular carcinoma and terminal liver disease leading to death.
The mechanism by which HCV establishes viral persistence and causes a high rate of chronic liver disease has not been thoroughly elucidated. It is not known how HCV interacts with and evades the host immune system. In addition, the roles of cellular and humoral immune responses in protection against HCV infection and disease have yet to be established. Immunoglobulins have been reported for prophylaxis of transfusion-associated viral hepatitis, however, the Center for Disease Control does not presently recommend immunoglobulins treatment for this purpose. The lack of an effective protective immune response is hampering the development of a vaccine or adequate post-exposure prophylaxis measures, so in the near-term, hopes are firmly pinned on antiviral interventions.
Various clinical studies have been conducted with the goal of identifying pharmaceutical agents capable of effectively treating HCV infection in patients afflicted with chronic hepatitis C. These studies have involved the use of interferon-alpha, alone and in combination with other antiviral agents. Such studies have shown that a substantial number of the participants do not respond to these therapies, and of those that do respond favorably, a large proportion were found to relapse after termination of treatment.
Until recently, interferon (IFN) was the only available therapy of proven benefit approved in the clinic for patients with chronic hepatitis C. However the sustained response rate is low, and interferon treatment also induces severe side-effects (i.e. retinopathy, thyroiditis, acute pancreatitis, depression) that diminish the quality of life of treated patients. Recently, interferon in combination with ribavirin has been approved for patients non-responsive to IFN alone. However, the side effects caused by IFN are not alleviated with this combination therapy. Pegylated forms of interferons such as PEG-Intron® and Pegasys® can apparently partially address these deleterious side-effects but antiviral drugs still remain the avenue of choice for oral treatment of HCV.
Therefore, a need exists for the development of effective antiviral agents for treatment of HCV infection that overcome the limitations of existing pharmaceutical therapies.
HCV is an enveloped positive strand RNA virus in the Flaviviridae family. The single strand HCV RNA genome is approximately 9500 nucleotides in length and has a single open reading frame (ORF) encoding a single large polyprotein of about 3000 amino acids. In infected cells, this polyprotein is cleaved at multiple sites by cellular and viral proteases to produce the structural and non-structural (NS) proteins. In the case of HCV, the generation of mature nonstructural proteins (NS2, NS3, NS4A, NS4B, NS5A, and NS5B) is effected by two viral proteases. The first one, as yet poorly characterized, cleaves at the NS2-NS3 junction (henceforth referred to as NS2/3 protease); the second one is a serine protease contained within the N-terminal region of NS3 (NS3 protease) and mediates all the subsequent cleavages downstream of NS3, both in cis, at the NS3-NS4A cleavage site, and in trans, for the remaining NS4A-NS4B, NS4B-NS5A, NS5A-NSSB sites. The NS4A protein appears to serve multiple functions, acting as a cofactor for the NS3 protease and possibly assisting in the membrane localization of NS3 and other viral replicase components. The complex formation of the NS3 protease with NS4A seems necessary to the processing events, enhancing the proteolytic efficiency at all of the sites. The NS3 protein also exhibits nucleoside triphosphatase and RNA helicase activities. NS5B is a RNA-dependent RNA polymerase that is involved in the replication of HCV.
A general strategy for the development of antiviral agents is to inactivate virally encoded enzymes that are essential for the replication of the virus.
The following is a list of patent applications published in the last few years that disclose HCV NS3 protease inhibitor peptide analogs that are structurally different from the compounds of the present invention:    GB 2,337,262; JP10298151; JP 11126861; JP 11292840; JP 2001-103993; U.S. Pat Nos. 6,159,938; 6,187,905; WO 97/43310; WO 98/17679; WO 98/22496; WO 98/46597; WO 98/46630; WO 99/38888; WO 99/50230; WO 99/64442; WO 99/07733; WO 99/07734; WO 00/09543; WO 00/09558; WO 00/20400; WO 00/59929; WO 00/31129; WO 01/02424; WO 01/07407; WO 01/16357; WO 01/32691; WO 01/40262; WO 01/58929; WO 01/64678; WO 01/74768; WO 01/77113; WO 01/81325; WO 02/08187; WO 02/08198; WO 02/08244; WO 02/08251; WO 02/08256; WO 02/18369; WO 02/60926 and WO 02/79234.
One advantage of the present invention is that it provides tripeptide compounds that are inhibitory to the NS3 protease, an enzyme essential for the replication of the hepatitis C virus.
A further advantage of one aspect of the present invention resides in the fact that the compounds specifically inhibit the NS3 protease and do not show significant inhibitory activity against other serine proteases such as human leukocyte elastase (HLE), porcine pancreatic elastase (PPE), or bovine pancreatic chymotrypsin, or cysteine proteases such as human liver cathepsin B (Cat B). Furthermore, the compounds are active in cell culture and have good pharmacokinetic profile in vivo.
A further advantage of the present invention is that it provides compounds that are orally bioavailable in mammals.

Abstract: Compounds of formula (I):

Abstract: wherein R1 is hydroxyl or sulfonamide derivative; R2 is t-butyl or —CH2—C(CH3)3 or —CH2-cyclopentyl; R3 is t-butyl or cyclohexyl and R4 is cyclobutyl, cyclopentyl or cyclohexyl; or a pharmaceutically acceptable salt thereof, are described as useful as inhibitor of the HCV NS3 protease.


A lamination molding apparatus includes an irradiator, a processing unit, and a cooling device. The irradiator irradiates a material layer with a beam to form a solidified layer. The processing unit includes a processing head having a tool that performs processing on the solidified layer, and a processing head driver moving the processing head at least in a horizontal direction. The cooling device is provided in the processing head and cools at least a part of a solidified body including an upper surface to a predetermined cooling temperature, and the solidified body is formed by laminating the solidified layer. The cooling device includes a cooling plate having a cooling surface being cooled to the cooling temperature, and the cooling surface is in close contact with the upper surface of the solidified body in a recumbent state with the cooling surface along the horizontal direction.

There is a plurality of methods for metal lamination molding. For example, in powder bed fusion, a material layer made of material powder is formed on a molding table capable of vertical movement in a sealed chamber filled with inert gas. Then, a predetermined portion of the material layer is irradiated with a laser beam or an electron beam to melt or sinter the material layer at the irradiated position to form a solidified layer. In this way, the formation of the material layer and the solidified layer are repeated, and a plurality of solidified layers are laminated to produce a desired three-dimensional molded object. Here, the solidified layer includes a molten layer and a sintered layer. Further, the laminated solidified layer is called a solidified body.
In such metal lamination molding, temperature adjustment may be performed on a three-dimensional molded object after molding or a solidified layer in the middle of molding. For example, Japanese Patent No. 6295001 discloses a lamination molding method in which martensitic transformation is intentionally advanced each time one or more solidified layers are formed. In this method, tensile stress due to the contraction of the solidified layer(s) is reduced by compressive stress due to the martensitic transformation, and deformation due to residual stress of the molded object is suppressed. In this molding method, in order to advance the martensitic transformation intentionally, predetermined temperature control is performed on the solidified layer(s) each time one or more solidified layers are formed.


A silver halide photographic emulsion, wherein 70% or more of the total projected area of silver halide grains is occupied by silver halide grains satisfying the following requirements (a) to (d).

1. Field of the Invention
The present invention relates to a silver halide photographic emulsion having high sensitivity and excellent latent image keeping characteristics and a silver halide photosensitive material using thereof.
2. Description of the Related Art
It is well known generally to use tabular silver halide grains (hereinafter, called as "tabular grains") for obtaining a silver halide photosensitive material having high sensitivity. As the sensitization process of these tabular grains, a sensitization process using epitaxial splice is disclosed (for example, Jpn. Pat. Appln. KOKAI Publication No. (hereinafter referred to as JP-A-)8-69069 and JP-A-2002-278007).
The epitaxial sensitization process disclosed in these patents is a process by which silver halide having comparatively high silver halide content rate is epitaxially spliced with host tabular grains mainly having silver iodobromide.
However, although high sensitivity can be obtained by the epitaxial flat plate, performance is not always stable and it cannot be said that it is suitable for stably obtain performance as a photosensitive material. It is caused by that since the solubility product of silver chloride is larger than the solubility product of silver iodide, halogen conversion between the epitaxial protrusion portions of host grains occurs easily. Consequently, a photosensitive material using the epitaxial flat plate has a problem that the lowering of sensitivity and fog increase at storage occur easily.
In order to improve the stability of the epitaxial flat plate, there is disclosed an epitaxial flat plate having silver halide in which the main compositional component of host grains and the epitaxial flat plate is silver bromide (JP-A-2003-15245).

Silver halide photographic emulsion and silver halide photosensitive material using thereof

Abstract: (a) It is composed of a tabular silver halide host grain with an aspect ratio of 12 or more having two mutually parallel principal planes and a silver halide protrusion portion bonded by epitaxial junction on the surface of the host grain.

Abstract: (b) The silver bromide content rates of the host grain and the protrusion portion both are 70 mol % or more.

Abstract: (c) When the average silver iodide content rate of all grains is I mol %, the average silver iodide content rate of the region of 8%, based on the silver amount of the host grain, of the outer shell of the host grain is (I+12) mol % or less.


The present invention provides a rear cover of a flat panel electronic device and a flat panel electronic device having the rear cover. A outer surface of the rear cover is provided with a recess and a supporting leg, the supporting leg is pivotably connected in the recess through a pivot means so as to enable the supporting leg to pivot between a retracting position and an unfolding position, the supporting leg is configured to be contained in the recess when being in the retracting position, and to make an angle with the rear cover when being in the unfolding position, a speaker is disposed in the supporting leg, sound holes are disposed at a position on a side wall of the supporting leg which is corresponding to the speaker, a through-hole is formed at a position of the rear cover which is corresponding to the pivot means, and an electric wire of the speaker passes through the through-hole to extend into the rear cover. The angle of the screen of the flat panel electronic device relative to the user can be adjusted through the supporting leg of the rear cover to improve the user's comfort level in watching, and the surface to be placed (such as the table surface) has no influence on the sound effect.

1. Field of the Invention
The present invention relates generally to a flat panel electronic device, in particular, to a rear cover of a flat panel electronic device and a flat panel electronic device having the rear cover.
2. Description of the Related Art
The present flat panel electronic device (including a tablet PC, a flat panel mobile phone such as iphone, etc.) is usually held by a user or placed on a table. However, the user would feel tired after prolonged handhold, if the flat panel electronic device is heavy because of its big screen. However, if the flat panel electronic device is placed on the table, the screen is parallel to the horizontal plane, and it brings about the inconvenience in watching and operating. In addition, the speaker of the flat panel electronic device and the sound holes corresponding to the speaker are disposed on the back by some designers to improve aesthetics. When the flat panel electronic device is placed on the table, a part of the sound holes may be covered by the table, and thus, the sound effect may be influenced. Moreover, the sound effect is further influenced, since the sound may be transmitted to the ears of the user after the reflection of the table.
Therefore, there is a need of providing a rear cover of a flat panel electronic device and a flat panel electronic device having the rear cover to solve the above problem in the prior art.

Rear cover of flat panel electronic device and flat panel electronic device having the rear cover


A mother board includes a CPU, a suction fan mounted on the CPU for dissipating heat resulting from operation of the CPU, a north bridge chip disposed downstream to the suction fan, a power-consumption component disposed at one side of the CPU, and a ventilation-enhancing member disposed above the chip and capable of diverting an air flow of the suction fan toward the power-consumption component.

A central processing unit, and a chip set assembly (such as a north bridge chip set, a south bridge chip set) of the new version are provided with precise and complicated structure in such a manner to result in high performance and fast computing power thereof. As the computing capability of the PC increases, the temperature of the central processing unit and the chip set assembly subsequently gets higher when under operation. It is the trench and object of the manufacturers of the mother board to lower the temperature of these components around the central processing unit so as to prevent from malfunction due to the rise in the temperature of electronic components around the central processing unit.
A heat dissipating device is provided on the mother board, and includes a first suction fan disposed on the central processing unit via a heat sink and a second suction fan mounted on the computer housing. The heat sink on the first suction fan has a fin configuration so as to be adapted to guide the airflow toward the chip assembly in order to lower the actual temperature of the chip assembly. The second suction fan on the computer housing draws the air outwardly so as to cause an air circulation, which, in turn, results in an increase of the air density within the computer housing so as to enhance the heat dissipating effect of the CPU and the chip assembly.
FIG. 1 is a fragmentary view of a conventional mother board 1 which includes a CPU 2, a suction fan 12 mounted on the CPU 2 via a first heat sink 11, and a plurality of electronic components. The electronic components may includes a RAM (random access memory) module disposed at a left side of the CPU 2, and a row of capacitors 14 and a row of power-consumption components 15 disposed at a right side of the CPU 2. A north bridge chip set 3 (not visible) is mounted on the mother board 1 at a rear side of the CPU 2. A second heat sink 16 is mounted above the north bridge chip set 3, and is formed with a plurality of fins 16a for heat dissipation. An expansion card 17 is disposed adjacent to the second heat sink 16 away from the CPU 2. The first heat sink 11 is formed with a plurality of fins (not visible since covered by the suction fan 12) so as to guide the air flow from the suction fan 12 toward the second heat sink 16, thereby lowering the temperature of outer surface of the north bridge chip set 3.
It is noted that in addition to the north bridge chip set 13, the power transistors (mostly made up of MOSFET) disposed at the right side of the CPU generates a relatively high temperature under operation. Under the predetermined output rate, the temperature of the power transistors 15 may exceed 100° C. Though these power transistors 15 can operate under a temperature that is higher than that of the CPU or the chip assembly, the constant operation of the power transistors above 100° C. can result in melting of the tin, which is used for mounting the power transistors on the mother board. Since the mother board 1 is mounted uprightly in the computer housing, displacement and disengagement of these power transistors on or from the mother board 1 can adversely affect the functions of the mother board 1.

Mother board with a ventilation-enhancing member


A substrate having a plurality of light emitting diodes united therewith lies on a plane containing the longitudinal axis of an insertion unit of an endoscope. Likewise, part of a first objective surface lies on the plane containing the longitudinal axis of the insertion unit of the endoscope. As long as the diameter of the insertion unit remains unchanged, the plane containing the longitudinal axis of the insertion unit of the endoscope provides the largest area for the light emitting diodes. The light emitting diode sub-assembly is therefore placed on this plane, so that the outer diameter of a distal endoscope part can be made as small as possible.

1. Field of the Invention
The present invention relates to a distal endoscope part, or more particularly, a distal endoscope part characterized by a portion thereof in which light emitting diodes serving as an illuminating means are placed.
2. Description of the Related Art
Structures having a light emitting source such as light emitting diodes incorporated as an illuminating means in a distal endoscope part have been proposed in the past.
For example, Japanese Unexamined Patent Publication No. 63-260526 describes a distal endoscope part for side viewing in which a plurality of light emitting diodes is placed circumferentially with an objective optical system as a center in order to improve the light emitting characteristic of the distal part.
However, according to the prior art (Japanese Unexamined Patent Publication No. 63-260526), the light emitting diodes are placed on a spherical surface on the outer circumference of an endoscope. The plurality of light emitting diodes must be attached one by one to a distal member.
When the light emitting diodes must be attached one by one to the distal endoscope member, there is difficulty in narrowing the spacing between adjoining light emitting diodes. Therefore, a side viewing endoscope having a plurality of light emitting diodes placed on the outer circumference of an objective optical system has a drawback in that the distal part thereof is large in size.
Japanese Unexamined Patent Publication No. 8-117184 proposes a structure having a light emitting source as an illuminating means incorporated in a distal endoscope part. Japanese Utility Model Registration No. 3007137 proposes a structure having light emitting diodes as an illuminating means placed around a camera in a distal part of a tubular examination camera system. In these structures, the light emitting unit is protected with a cover glass or acrylic plate placed on the front surface thereof.
Especially in Japanese Utility Model Registration No. 3007137, the cover glass over the front surfaces of the light emitting diodes also works to render the light emitting diodes watertight.
However, when a watertight structure is realized using a transparent member such as the cover glass described in the prior art, the cover glass must have a thickness large enough to position the perimeter thereof relative to a metallic member to support itself therein. In the structure having the cover glass, therefore, mechanical members must be made larger to a dimension corresponding to the perimeter used for positioning the cover glass.
As described in Japanese Utility Model Registration No. 3007137, a structure has the light emitting diodes, which serve as an illuminating means, placed on the outer circumference of an imaging unit and a transparent member placed on the front surfaces of the light emitting diodes. This poses a problem in that the outer diameter of the distal part must be made larger to a dimension corresponding to the perimeter of the transparent member.
An object of the present invention is to provide a distal endoscope part which makes it possible to realize a side viewing endoscope having a plurality of light emitting diodes placed on the outer circumference of an objective optical system without an increase in the outer diameter of the distal part.
Another object of the present invention is to provide a distal endoscope part which makes it possible to realize a watertight structure without the necessities of placing a transparent member over the front surfaces of the light emitting diodes and of increasing the outer diameter of the distal part.
A distal endoscope part in accordance with the present invention has a plurality of light emitting diodes for supplying illumination light placed as an illuminating means on the outer circumference of an objective optical system. The plurality of light emitting diodes is mounted on a substrate and united therewith. A sub-assembly of the plurality of united light emitting diodes is placed on a plane containing the longitudinal axis of an insertion unit of the endoscope. Consequently, although the side viewing endoscope has the plurality of light emitting diodes placed on the outer circumference of the objective optical system, the outer diameter of the distal part thereof is not large in size.
Other features of the present invention and advantages thereof will be fully apparent from the description below.

Distal endoscope part having light emitting source such as light emitting diodes as illuminating means


According to one embodiment, an ultrasonic diagnostic apparatus includes an ultrasonic probe, position detector detecting a probe position, ultrasonic image generation circuitry generating an ultrasonic image, storage circuitry storing volume data and a designation position in association with each other, slice image generation circuitry generating a slice image to the designation position based on the data and the designation position, a display displaying at least one of first display displaying the slice image and the ultrasonic image and second display displaying contents different from contents in the first display, control circuitry controlling switching from the first display to the second display in response to movement of the probe position into a range to the designation position.

In recent years, an ultrasonic diagnostic apparatus has a function of performing display (to be referred to as dual display hereinafter) of a tomographic image corresponding to a scanning slice by ultrasonic waves together with a B-mode image by using an output from a position sensor such as a magnetic sensor and three-dimensional image data collected by modalities such as an X-ray CT (Computed Tomography) apparatus and MRI (Magnetic Resonance Imaging) apparatus. FIG. 21 is a view showing an example of dual display. With dual display, differential diagnosis of a benign/malignant tumor by dynamic tumor observation using ultrasonically guided puncture and a contrast medium is efficiently and accurately performed. An ultrasonic diagnostic apparatus having a dual display function designates a specific position via an operation by an operator using position information of a position sensor. The ultrasonic diagnostic apparatus has a guide function of performing guide from a slice during scanning to the specific position in accordance with the distance between the slice during scanning and the specific position, and a direction perpendicular to the scanning slice.
The ultrasonic diagnostic apparatus having the guide function allows guide to a position with respect to the scanning slice including the specific position. However, there are an infinite number of scanning slices including the specific position. Therefore, the operator needs to confirm, in advance, a plurality of scanning slice candidates associated with puncture treatment among the plurality of scanning slices including the specific position. The plurality of scanning slice candidates include, for example, a slice where it is possible to grasp the running position of a lumen such as a blood vessel or bile duct positioned near a treatment target region, and a slice where it is possible to grasp the position of another tissue region adjacent to a tissue region when the treatment target region is close to the boundary of treatment target tissue. In addition, an advanced technique for reproducing the same scanning slice among the plurality of confirmed scanning slices is required for the operator.
To support recognition of the position of an ultrasonic scanning slice in a three-dimensional space, the ultrasonic diagnostic apparatus having the dual display function has an image processing function such as surface rendering using three-dimensional image data by a number of modalities, and a function of displaying a three-dimensional body mark indicating the current scanning slice by processing position information in real time. FIG. 22 is a view showing an example of a conventional three-dimensional body mark.
A three-dimensional body mark can indicate, to the operator, the relative position of an ultrasonic probe with respect to an object. However, it is impossible to efficiently guide a position, at which the ultrasonic probe is brought into contact with the object, to the position of the ultrasonic probe with respect to a scanning slice desired by the operator by only displaying the three-dimensional body mark. That is, displaying again the slice desired by the operator depends on the memory and skill of the operator. Thus, it takes time to reproduce the slice desired by the operator.
The conventional ultrasonic diagnostic apparatus can display, by ultrasonic scanning, a B-mode image which is almost the same as that stored in the past. When, however, the almost same B-mode image is displayed (to be referred to as almost same image display hereinafter), it is necessary to perform an input operation for displaying a plurality of screens by other modalities while holding the probe position in order to display a plurality of slice images by the other modalities, each of which includes a specific position, with respect to the displayed B-mode image. Consequently, in addition to the cumbersome operation, a display slice may deviate. In the conventional ultrasonic diagnosis apparatus, when almost same image display is executed, if another B-mode image such as a vertical slice including the specific position is generated, if various software programs associated with ultrasonic diagnosis are activated, or if a B-mode image in which an annotation about a slice image is displayed is displayed, it is necessary to perform an input operation such as an addition operation or scan condition change operation by an input device, and thus it may be impossible to display a desired slice while holding the probe position, as described above. That is, the operator needs to execute an input operation while maintaining a slice, resulting in cumbersomeness.
As described above, in the conventional ultrasonic diagnostic apparatus, when almost same image display is executed, the operator needs to execute again an input operation by the input device, thereby degrading the diagnosis efficiency.


Circuits and methods for precisely self-timed SRAM memory are disclosed to track the wordline and/or bitline/bitline bar (BL/BLB) propagation delays. At least one reference cell can be placed near the far end of a driver to drive a selected wordline or a reference wordline. When a wordline and/or a reference wordline is turned on, the reference cell can be selected not earlier than any selected SRAM cells and can activate a reference bitline (RBL) not later than any selected SRAM cells activating the BL or BLB. The activation of the RBL can be used to trigger at least one sense amplifier. The RBL can also be used to de-select wordline or reference wordline after the sense amplifier operation is complete to save power.

1. Field of the Invention
The present invention relates to effective circuit, system designs, and methods of a self-timed SRAM for high speed and low power applications.
2. Description of the Related Art
Today's SRAM is commonly used as caches in ultra-high clock-rate CPU. A clock rate of 1 GHz CPU can be achieved easily in today's nanometer devices, such as 65 nm CMOS and beyond. For an SRAM to match such high clock rate, the access time needs to be less than 1 ns. In such short period of time, it would be very hard to generate control signals to keep propagation delay short while keeping inactive block idle to meet both high speed and low power. It is the objective of this invention to achieve high speed, low power, and small area to meet the very demanding SRAM requirements in today's applications.
A conventional SRAM memory cell is shown in FIG. 1. The cell 10 consists of a cross-coupled latch constructed from inverters 11 and 12, two pass transistors 13 and 14. The input of the inverter 11 NB is coupled to the output of the inverter 12, and the input of the invert 12 N is coupled to the output of the inverter 11. The sources of MOS 13 and 14 are coupled to the two nodes N and NB, respectively. The MOS 13 and 14 have their sources coupled to nodes N and NB, their gates coupled to a wordline (WL), their drains coupled to bitline (BL) and bitline bar (BLB), respectively. The SRAM cell can be organized as a two-dimensional array with all BLs and BLBs of the cells in the same columns coupled together in vertical direction and all wordlines of the cells in the same row coupled together in horizontal direction. The SRAM cell can be read by pre-charging the BL and BLB to a high voltage (i.e. VDD) and then let floating. The BL or BLB voltage can be pulled low by the inverter 11 or 12 in the cell, depending if the data stored is 0 or 1, when the WL is turned on. Similarly, the SRAM cell can be written with data 0 or 1, by pulling BL or BLB low, respectively, when the WL is turned on.
A conventional sense amplifier (SA) of an SRAM is shown in FIG. 2. The latch-type SA 20 has a structure very similar to the SRAM cell shown in FIG. 1. The SA is based on the positive feedback of a latch to amplifier the input signals so that the gain can be high and the power consumption can be low. The SA can be activated when the input signals reach sufficient differential voltages; otherwise incorrect data may be sensed instead. The SA 20 has PMOS 21-1 and NMOS 21-2 constructed as an inverter with their gates coupled to QB, their sources coupled to VDD and ground through a NMOS 25, respectively. The drain of PMOS 21-1 is coupled to the drain of NMOS 21-2 and to a node Q. The SA 20 also has PMOS 22-1 and NMOS 22-2 constructed as an inverter with their gates coupled to Q, their sources coupled to VDD and ground through the NMOS 25, respectively. The drain of PMOS 22-1 is coupled to the drain of NMOS 22-2 and to a node QB. The sources of NMOS 21-2 and 22-2 are coupled to the drain of the same NMOS 25, whose gate is coupled to an SA enable (SE) and whose source is coupled to ground. The nodes Q and QB are coupled to the sources of PMOS 23 and 24, respectively. The drains of PMOS 23 and 24 are coupled to DI and DIB, respectively. The gates of PMOS 23 and 24 are coupled to an SA input enable (SIB). Two PMOS 26-1 and 26-2 are pullup devices for nodes QB and Q, respectively, with the gates coupled to SE.
The SA shown in FIG. 2 works as follows. Before sensing, SE is low and the nodes Q and QB are pulled high to VDD by a pair of PMOS pull-ups 26-2 and 26-1, respectively. When the signals at DI and DIB reach sufficient voltage difference (i.e. 100 mV split), SIB can be pulled low to allow signals coming into the nodes Q and QB, respectively. After the differential voltages are passed from DI/DIB to Q/QB, SE can be turned on to pull the drain of MOS 25 low while disabling PMOS 26-1 and 26-2. At the mean time, the SIB can be set to low to turned off the PMOS 23 and 24 to isolate the input signals from the internal nodes Q and QB in the SA. Subsequently, the cross-coupled latch consisting of PMOS 21-1 and 22-1 can be activated to make Q and QB split wider and reach rail-to-rail levels eventually. The cross-coupled latch consists of NMOS 21-2 and 22-2 can also be activated when the NMOS 25 is more heavily turned on. The timing of turning on SE is very crucial only after substantial signal splits are developed at nodes Q and QB, otherwise wrong data can be sensed and latched instead.
FIG. 3(a) shows a block diagram 30 of a portion of a self-timed circuit in a prior art. A memory cell array 31 has a reference column 32 that consists of 3 reference cells 33-1, 33-2, and 33-3, and some dummy cells 35 to fill up a column. The reference cells can be modified slightly from the normal cells to make reference BL pulled low earlier and then used as a control signal to trigger at least one SA.
FIG. 3(b) shows a schematic of a reference cell 40, corresponding to the reference cells 33-1 through 33-3 in FIG. 3(a), in a prior art. The reference cell 40 has a pair of cross-coupled inverters 41 and 42 constructed as a latch, and two pass transistors 43 and 44, similar to a normal SRAM cell. However, the gates of the pass transistor 43 and 44 are coupled to BLin (equivalent to BL in the normal cell), and the drain of the NMOS 43 is coupled to high (i.e. VDD). When BLin is set high, RBL can be pulled low. If the three reference cell 33-1, 33-2, and 33-3 in FIG. 3(a) have their BLin coupled together and have one shared RBL, RBL can be pulled down faster than any normal cells pulling down BL/BLB. As a result, RBL can be used to trigger an SA. BLin signal can be generated from a control signal, such as a clock CLK, through a multi-tap delay chain 45. Turning on BLin with respect to CLK can be adjusted by setting a plurality of delay control signals or a plurality of registers.
To achieve a reliable SRAM function with low power consumption, it is desirable to turn on the selected WL while turning off BL pullups only during the memory cells are ready for access. FIG. 4(a) shows a portion of a schematic 50 of a self-timed circuit in a prior art. The schematic 50 has a plurality of address buffers 57, pre-decoders 58, and decoders 59. The address buffer 57 consists of inverters 51-1, 51-2 and 51-3 to generate true and complement addresses, respectively. The pre-decoder 58 has a multi-input NAND 52-1 and followed by a buffer 52-2. The decoder 59 has a multi-input NAND 53-1 and followed by a wordline driver 53-2 to drive a WL. The addresses generated from the address buffers 57 are then input to a plurality of pre-decoders 58 to generate more pre-decoded signals, which are then input to a plurality of decoders 59 to fully decode the available address space. A WL can be turned on by using a wordline enable (WLEN) in one of the input in one of the pre-decoders. WLEN can be generated from a control signal, such as a clock CLK, through a multi-tap delay line 54. The delay line 54 can be controlled by a plurality of delay control signals or a plurality of registers.
The relative timing between CLK and WLEN is shown in FIG. 4(b). There is a parameter Twld to specify the turning on of WLEN after CLK transitions to deliver a new address. If a WL is turned on too early, excess power may be wasted. If a WL is turned on too late, the speed may be penalized. Another parameter Twlp is related to the WL pulse width. If Twlp is too narrow, sufficient BL/BLB split may not be developed before the WL is turned off again. If Twlp is too wide, excess power may be wasted. These two parameters can be used to illustrate the concept of tradeoff between speed and power.
The self-timed circuit as shown in FIGS. 3(a), 3(b), 4(a), and 4(b) are not self-timed precisely. The turning on of RBL is not tracking with WL turn-on time. The turning off of a WL is not tracking with SA enabling or disabling either. As a result, RBL may turn on an SA when the input signals are not split wide enough, or even before the selected WL is turned on at the worse. The selected WL may be turned off prematurely before sufficient signal splits reaching the inputs of an SA and sensed. Consequently, wide timing margins are needed to build a robust SRAM; otherwise yield and reliable operations may suffer. Therefore, it is still very desirable to invent some precise self-timed circuits to reduce timing margins to meet today's very demanding SRAM requirements.

Circuits and methods of a self-timed high speed SRAM


A methodology 40 for producing a laminated tool 10 having desired dimensional accuracy. The tool 10 is produced by the use of several sectional members, such as sectional members 14, 16 which are selectively coupled and which are measured. The measurement is used to determine whether to selectively press these previously coupled sectional members 14, 16 to ensure that their coupled arrangement has a desired dimensional accuracy. Additional measurements and needed pressing operations are accomplished each time a new sectional member is added to the previously coupled sectional member combination.

A tool has traditionally been created or formed from a substantially solid object. Particularly, the substantially solid object is burned, cut, or otherwise configured to form the tool. It should be appreciated, at the outset, that the term "tool" is meant to broadly refer to any object or tangible entity which is used to selectively create another tangible entity or item. Further, the term "tool", as used in this description, should not be narrowly construed to refer to any particular type of tool, but should remain broadly defined.
While the foregoing traditional approach does allow a tool to be selectively created, it suffers from some drawbacks. By way of example and without limitation, the foregoing strategy requires a relatively large amount of time and effort and is relatively costly. Further, the created tool is not easily modified.
To overcome these and other drawbacks associated with this traditional tool building technique and strategy, an approach has been developed in which a soft design (e.g., a design based upon or created within software) of the tool is initially created. The soft design is then used to create various intangible or "soft" sections and these sections are respectively, typically, and sequentially manifested into respective physical sections which are sequentially coupled to build the tool. Such an approach is often referred to as a "lamination" approach and is described within U.S. Pat. No. 6,587,742 ("The '742 Patent"), which was issued on Jul. 1, 2003, which was assigned to Applicant's assignee, and which is fully and completely incorporated herein by reference, word for word and paragraph for paragraph.
While this "lamination" strategy does reliably produce a tool which overcomes the foregoing drawbacks of prior tool forming strategies, sometimes the produced tool fails to have a desired overall dimensional accuracy. That is, various spatial dimensions of the produced tool may not always be as close to the spatial dimensions of the softly designed tool as is desired, and such differences may arise from spatial variations associated with the structure and/or surface contours or the individual sectional members. That is, a produced sectional member may have surface features, contours, or other spatial dimensions which are not quite equal to or similar to the surface features, contours, and spatial dimensions of the corresponding "soft" or intangible sectional member. Such differences may arise from the technique used to produce the sectional member or just from seemingly minor surface or other structural imperfections associated with the physical sectional member. Accordingly, as the number of selectively coupled sectional members increases, these individual variations accumulate and may cause a rather undesirable overall variation between the actually produced physical tool and the corresponding "soft" design.
One approach to address this issue involves the measurement of the spatial dimensions of each produced sectional member and the use of these measurements, in feedback fashion, to "fix" or set the location within the "soft" design which specifies the characteristics of the next produced sectional member. This "feedback" approach is described with The '742 Patent.
While the foregoing approach does increase the overall dimensional accuracy of the produced tool, yet another approach to overcoming the foregoing difficulties may be utilized and this competing approach is described within this Application. Further, it should be appreciated that the following described approach may be used in combination with the "feedback" approach which is described with The '742 Patent to produce a tool having even greater overall dimensional accuracy.


A testing apparatus having testing module slots onto which different types of testing modules are selectively mounted includes controlling modules for supplying control signals to the testing modules mounted on the testing module slots. The control signals are used for controlling the testing module. The apparatus also includes a setting information supplying unit for supplying hardware setting information to a specific testing module, an enable signal controlling unit for instructing the specific testing module to generate and supply an enable signal to the controlling module corresponding to the specific testing module, and a setting unit for setting the controlling module received said enable signal from the specific testing module so as to supply the control signal corresponding to the specific testing module based on the hardware setting information.

1. Field of the Invention
The present invention relates to a testing apparatus. More particularly, the present invention relates to a testing apparatus including a plurality of testing module slots onto which different types of testing modules are selectively mounted.
2. Description of the Related Art
A testing apparatus for performing an analog test of a device under test performs the test by instructing one testing module to generate and supply a test signal to the device under test and another testing module to measure the output signal from the device under test. In order to properly operate each of a plurality of testing modules, each of a plurality of controlling modules selects and supplies both a trigger signal and a clock signal corresponding to the type of each of the testing modules among a plurality of trigger signals and clock signals to the testing module based on a testing program. In order to realize the operations of such controlling modules, one who prepares the testing program prepares a management table for managing the connections of the inputs and outputs of the controlling modules so as to arbitrarily select the trigger signals and the clock signals inputted to the controlling modules, and the trigger signals and the clock signals outputted from the controlling modules to the testing modules, and prepares a testing program for testing the device under test in consideration of the connections of inputs and outputs of the controlling modules.
Recently, a testing apparatus including a plurality of testing module slots onto which different types of testing modules for generating different types of test signals for the test of the device under test respectively are selectively mounted has been developed. In such testing apparatus, since the connection relation of the controlling modules and the testing modules are arbitrarily changed, and the times required for the test operations for the test modules are different from each other, it is inevitable to prepare a management program whenever the testing modules are changed, and a testing program corresponding to the mounting positions the testing modules whenever the testing modules are changed, and a preparation process is needed for a extremely difficult test.


A cableless power lift assembly for raising and lowering the roof structure or camper top of a pop-up camper includes an elongated drive housing mounted to the base of a pop-up camper and a pair of aligned left and right threaded screw drives mounted in the drive housing for rotatable movement therein. A motor is attached to the left and right screw drives for rotatably driving the screw drives to raise the camper top upon actuation of said motor in a first direction and lower the camper top upon actuation of the motor in an opposite second direction. In addition, collapsible lifting apparatus is also provided for moving the camper top between a generally horizontal lowered or collapsed position and a generally horizontal raised or extended position. In a preferred embodiment, an air conditioning unit is mounted in the camper top.

A review of the prior art found in a search for subject matter related to the present invention revealed no cableless power lift assemblies or other cableless powered apparatus for raising and lowering the roof structure of a pop-up camper of the type having a collapsible soft or flexible wall. The search included a review of the following patents; U.S. Pat. Nos. 3,884,520; 4,969,793; 5,769,485; 6,086,134 and 6,325,447. In addition, the search revealed no pop-up campers having an air conditioner mounted in the pop-up camper's roof or powered lift systems for a pop-up camper having the capability of raising and lowering the camper's pop-up roof with any type of a significant load mounted or stored on the roof.


Rolled plate products up to 6 inches thick or more and other products in an aluminum alloy consisting essentially of about 5.2 to 6.8% zinc, 1.7 to 2.4% copper, 1.6 to 2% magnesium, 0.03 to 0.3% zirconium, balance substantially aluminum and incidental elements and impurities, are useful in making structural members for commercial airplanes especially by machining or shaping such members from the plate. Such members include lower wing skins and wing spars and other members. The plate is made by operations comprising homogenization, hot rolling, solution heat treatment, stretching and artificial aging. Alternatively, the plate is shaped after stretching, which may include machining, and is then artificially aged.

There are numerous commercial jet aircraft of various sizes including the large "jumbo jet" aircraft, such as the Boeing 747 and the McDonnell Douglas MD11 and the Lockheed L1011. In going to a still larger aircraft, such as a 600-passenger aircraft envisioned for the future, the loads on the wing member needed to hold the airplane aloft are heightened some. These large aircraft will carry in the neighborhood of 600 passengers and may include two passenger decks. Whereas a Boeing 747 (one of the largest commercial jet aircraft in use) has an empty weight in the neighborhood of about 399,000 pounds, it is estimated that the high capacity aircraft envisioned will weigh in the neighborhood of 532,000 pounds empty and somewhere around 1,200,000 pounds loaded. High capacity aircraft as used herein refers to an aircraft weighing more than 450,000 pounds empty. To heighten efficiency in such an airplane, it would be important to have materials in the wing structures that can support the load of the airplane without themselves becoming too heavy. Aluminum alloys have seen wide use in airplane structural members, including airplane wing structural members, and have an enviable record for dependability and performance. More exotic, composite or other materials can be used for airplane wing structural members, but are much more costly and can be somewhat less dependable than aluminum alloys.
In general, the structural core of a large airplane wing can include a box-like structure made up of an upper wing skin, a lower wing skin, and end pieces to close the box-like beam structure. While the upper and lower members are labeled "skin", it is important to appreciate that these are not thin skins such as on the airplane fuselage, but rather, somewhat thick, for instance a half inch or more in thickness. In most of the current commercial jet aircraft, the upper wing skin is made of a 7000 Series alloy, currently a 7X50 alloy (7X50 is intended to refer to 7050 and 7150), or more recent alloy 7055. U.S. Pat. No. 3,881,966 describes 7X50 alloys and U.S. Reissue Pat. No. 34,008 describes 7150 alloy used as an upper wing skin on a commercial jet aircraft, and U.S. Pat. No. 5,221,377 describes alloy 7055 and refers to its use in airplane structural members. The upper wing skins were normally in artificially aged tempers such as T6-type or possibly T7-type tempers. U.S. Pat. Nos. 4,863,528, 4,832,758 and 4,477,292, along with U.S. Pat. No. 5,108,520, all describe tempers for 7000 type aluminum alloys, which said temper can be applied to the 7000 Series alloys just mentioned to improve performance. All the aforesaid patents (U.S. Pat. Nos. 3,881,966, Re. 34,008, 5,221,377, 4,863,528, 4,832,758, 4,477,292 and 5,108,520) are fully incorporated herein by reference.
In commercial jet aircraft, the lower wing skins have generally been made of aluminum alloy 2024 or similar products such as alloy 2324 which is included in U.S. Pat. No. 4,294,625, the entire content of which is incorporated herein by reference. The temper was normally T3-type such as T351 or T39. Temper and alloy designations used herein are generally those used in accordance with the Aluminum Association and are generally recognized in the art and described in the Aluminum Association Standards and Data book.
Both the upper and lower wing skins are often reinforced by stringer members which can have a channel or J-type shape or other shape which are riveted to the inside surfaces to stiffen the wing skins and thereby stiffen the wing box structure. In general, when a commercial jet aircraft is in flight, the upper wing skin is in compression, whereas the lower wing skin is in tension. An exception occurs when the airplane is on the ground where these stresses are reversed but at a much lower level since at that point the wing outboard of the landing gear pretty much just holds up its own weight. Thus, the more important applications are when the airplane is in flight which places the upper wing skin in compression and the lower wing skin in tension. An exception occurs in certain military airplanes which are designed to utilize their enormous power to weight ratio and are intended to fly upside down, right side up, or any condition between at enormous speeds.
Because of the particular loading differences encountered in commercial jet airplanes, the alloy selections were, for the most part, as just described. There have been some exceptions in that airplanes such as the Lockheed L1011 included 7075-T76 lower wing skins and stringers and the military KC135 fueler airplane included 7178-T6 lower wing skins and stringers. Another military airplane, the C5A, used 7075-T6 lower wing skins that were integrally stiffened by machining out metal. Military fighter planes such as the F4, F5E, F8, F16 and F18 have included lower wing materials of 7075 alloy or related 7475 alloy (F16 and F18). Nonetheless, over the years the airplane wing box structure has, for the most part, in commercial jet aircraft included a 7000 Series alloy upper wing skin and a lower wing skin of 2000 Series alloy, namely, 2024 or a member of the 2X24 alloy family.
The important desired properties for a lower wing skin in a high capacity and new commercial passenger jet aircraft include a higher strength than 2X24 alloys, a better fatigue life and improved fracture toughness over 2X24 materials. Because the airplane flies at high altitude where it is cold, fracture toughness at minus 65.degree. F. has become a concern in new designs. Additional desirable features include age formability whereby the material can be shaped during artificial aging, together with good corrosion performance in the areas of stress corrosion cracking resistance and exfoliation corrosion resistance. Alloys used to date for lower wing skin members in commercial jet aircraft are all lacking in satisfying the needed levels for high capacity aircraft in one or more of these properties.
In the past, the wing box-like structure was often made from several pieces, as shown in FIG. 3, left side, wherein the end member or spar comprised a plate fastened to the upper and lower wing skins by riveting to angle or tee-like members, in turn riveted to the wing skins. Some builders prefer to make the entire end piece or spar as shown on the right side of FIG. 3 thus eliminating several rivets and considerable weight by reducing the amount of metal structure. This end piece or spar is made by machining from a thick plate but the plate needs good properties in the transverse directions as well as longitudinal direction.

Aluminum alloy products suited for commercial jet aircraft wing members


A method for reducing the number of operations performed on a recording disk during Mt. Rainier defect processing is disclosed. According to this method, data is written from a host to a recording disk. If there are defects in the section where data is to be written, a replacement block for the currently-processed defective block is searched for. If there is previous replaced data currently stored in the replacement packet buffer (RPB), and if the packet in the RPB is the same as the packet for the replacement block, then the method only copies the data in the currently-processed defective block into the corresponding replacement block in the RPB without any reading operations. In addition, after completion of the read and copy operations, no immediate write to the recording disk is performed, thereby saving time.

1. Field of the Invention
The present invention relates to a method for reducing the number of read and write operations performed on a recording disk during Mt. Rainier defect processing.
2. Description of the Prior Art
Mt. Rainier is an industry standard, proposed by Microsoft, Compaq, Philips, Sony and others, that regulates the data storage format of new recording disks. Hereafter the new recording disks are called CD-MRW for short. First, it is well-known that a optical disk drive can only write complete packets. Each packet includes one link block, four "run-in" blocks (Rin), 32 user data blocks, and two "run-out" blocks (Rout). The link block indicates whether the laser in the optical disk drive (which is used for the writing operation) is on or off. Typically, the start and the end of each packet contain a half block, for a total of one block. The Rin blocks can be considered to be "waiting" blocks, to address the situation where the servo system is not completely ready even when the laser is turned on (i.e., starting the write operation). The Rout blocks are similar in function to the Rin blocks.
FIG. 3 illustrates how the storage space on a conventional recording disk is organized. Each data block DA is intended to store data (i.e., data is to be written to each data area), and each data block DA is followed by an adjacent spare block SA that is used to store the data intended for its adjacent data block DA if that data block DA contains a defect. If the adjacent spare block SA is full, the defective block data will be written to other spare blocks SA.
In addition, each CD-MRW has a main table area (MTA). Defect tables are contained in a maximum of eight packets in the main table area. FIG. 4 illustrates a typical layout of a defect table block (DTB). The "Reallocation Entries" identify a defective block to which a replacement block has been assigned. The "Free Entries" identify a replacement block that has not yet been assigned to a defective block. The "Unusable Entries" identify a replacement block that cannot be used (e.g., the replacement block itself is defective). When a recording disk is formatted, defect table entries are recorded on to the disk. Each defect table entry consists of six bytes. The first three bytes indicate a defective block and the last three bytes indicate the corresponding replacement block that has been assigned for the defective block.
FIG. 1 is a flow chart illustrating a conventional Mt. Rainier method of writing data to a recording disk which has defects. Before the write operation begins, the defect tables on the disk are checked. When writing data to a defective block, the optical disk drive will write to the replacement block instead based on the physical block numbers contained in the defect tables.
In Step 10a, the write operation begins. In Step 11a, a write command is issued by the host; that is, the host issues the write command to the CD-RW unit, directing the optical disk drive to receive data that comes from the host and to write the received data to the recording disk.
In Step 12a, it is determined whether all the data from the host has been written. If all the data has been written, processing then proceeds to Step 13a where the write operation concludes. If all the data has not been completely written, then processing proceeds to Step 14a.
In Step 14a, it is determined whether any defects are detected in a given section where data is to be written. If there is a defect in this section, then read, modify and write operations are performed for each of the defects. In other words, for the first defect, the block that is to be replaced is searched for in Step 141a, and then in Step 142a the entire packet where the replacement block is located is read from the recording disk into the replacement packet buffer (RPB), which is in the RAM of the optical disk drive. The RPB usually has a size of one packet. Next, in Step 143a, the data in the defective block is copied from the main buffer (which is also in the RAM of the optical disk drive) into the corresponding replacement block in the RPB. Then, in Step 144a, the modified data in the RPB is written to the corresponding spare block SA in the recording disk, after which processing proceeds to Step 15a.
In Step 15a, it is determined whether there are more defects in the section where data is to be written. If there are other defects, then processing returns to Step 141a and the read, modify and write operations are repeated in Steps 141a–144a, until all the defects for the section have been processed. If there are no other defects in the section, processing then returns to Step 12a.
Returning to Step 14a, if there are no defects in the section where data is to be written into, processing then proceeds to Step 145a where the contents of the main buffer are written directly to the recording disk. Processing then proceeds to Step 16a.
In Step 16a, it is again determined whether there are new defects detected during the write operation. In this step, if no new defects are detected, processing then returns to Step 12a. However, new defects may occur on a recording disk even after it has been formatted (such as from scratches during use by the user). If any such new defects are detected, then processing proceeds to steps 161a–165a where free replacement blocks are searched for in the defect table for use as new replacement blocks. Here, "free replacement blocks" mean those blocks that have not been written into, and which are available to receive data.
At this point, the writing operation is terminated in step 161a so that free replacement blocks can be searched for. Then, in step 162a, free defect table entries (i.e., free replacement blocks) are searched for use as replacement data. After the search of the defect table is completed, processing proceeds to Step 163a.
In step 163a, the entire packet where the replacement block is located is read from the RAM of the optical disk drive into the replacement packet buffer (RPB), which is in the RAM of the optical disk drive. Next, in Step 164a, the data of the defective block is copied from the main buffer into the corresponding replacement block in the RPB. Then, in Step 165a, the modified data in the RPB is written to the corresponding spare block SA in the recording disk, after which processing proceeds to Step 17a.
In Step 17a, it is determined whether there are more defects. If new defects are detected, processing then returns to Step 162a and the read, modify and write operations are repeated in Steps 162a–165a, until processing of all the defects has been completed. If no new defects are detected, processing then returns directly to Step 12a. Thus, the read, modify and write operations in Steps 142a–144a are similar to those in Steps 163a–165a.
As can be seen from the above, in this conventional method, replacement packets are read from the recording disk, the defective block data are copied, and then all the packet data are written to the recording disk. Thus, regardless of whether the defect encountered by the optical disk drive already exists in the defect table block (DTB) or is a new defect detected during the process of writing to the recording disk, the optical disk drive must still perform the read-modify-write operation for each and every defect. As a result, if N defects are detected in the recording disk, then the optical disk drive must perform N read and N write operations, resulting in a low efficiency in the buffer control. This will also seriously affect the read and write speed of the optical disk drive.

Method for reducing the number of read and write operations during Mt. Rainier defect processing


A suspension assembly of an actuator for a disk drive to support a slider, on which a read/write head is mounted, elastically biased toward a surface of a disk. The suspension assembly includes: a load beam coupled to an end of a swing arm of the actuator; a flexure supporting the slider and having a fixed end fixed to a surface of the load beam facing the disk and a free end disposed close to a leading end of the load beam; an extender extending from the free end of the flexure; and a limiter limiting a range of up and down vibrations of the extender.

1. Field of the Invention
The present invention relates to a disk drive, and more particularly, to a suspension assembly of an actuator for a disk drive supporting a slider on which a rear/write head is mounted.
2. Description of Related Art
Hard disk drives (HDDs), which are data storage devices used for computers, use read/write heads to reproduce or record data with respect to a disk. In the HDD, the head performs its functions while being moved by an actuator to a desired position in a state of being lifted to a specified height from a recording surface of a rotating disk.
FIG. 1 is a plan view illustrating the configuration of a conventional hard disk drive. Referring to FIG. 1, the hard disk drive includes a spindle motor 12 installed on a base member 10, a disk 20 which is one or more disks and installed on the spindle motor 12, and an actuator 30 to move a read/write head (not shown) for reproducing and recording data to a specified position on the disk 20. The actuator 30 includes a swing arm 32 rotatably coupled to a pivot bearing 31 installed on the base member 10, a suspension assembly 40 installed at one end portion of the swing arm 32 and supporting a slider 44, on which the head is mounted, toward a surface of the disk 20 to be elastically biased, and a voice coil motor (VCM) to rotate the swing arm 32. The voice coil motor includes a VCM coil 36 coupled to the other end portion of the swing arm 32, a lower yoke 37 installed under the VCM coil 36, and a magnet 38 attached to an upper surface of the lower yoke 37. Although not shown in the drawing, the voice coil motor may further include an upper yoke installed above the VCM coil 36 and a magnet attached to a lower surface of the upper yoke.
The voice coil motor having the above configuration is controlled by a servo control system to rotate the swing arm 32 in a direction following the Fleming's left hand rule by the interaction between current applied to the VCM coil 36 and a magnetic field formed by the magnet 38. That is, when the power of the hard disk drive is turned on and the disk 20 starts to rotate in a direction D, the voice coil motor rotates the swing arm 32 counterclockwise, that is, in a direction A, to move the slider 44 on which the read/write head is mounted toward a position above the recording surface of the disk 20. The slider 44 is lifted to a specified height from the surface of the disk 20 by a lift force generated by the rotating disk 20. In this state, the head mounted on the slider 44 reproduces or records data with respect to the recording surface of the disk 20.
When the hard disk drive is not in operation, that is, the rotation of the disk 20 is stopped, the head is parked at a position out of the recording surface of the disk 20 so that the head does not collide against the recording surface of the disk 20. The head parking system can be classified into a contact start stop (CSS) method and a ramp loading method. In the CSS method, a parking zone where data is not recorded is provided at an inner circumferential side of the disk 20 and the head is parked in the parking zone in a contact manner. However, in a head parking system adopting the CSS method, since the parking zone needs to be provided at the inner circumferential side of the disk 20, a data storage is lessened. Thus, to meet the recent trend toward a higher data recording density, a head parking system adopting the ramp loading method which can secure a larger data storage space is wildly adopted.
In the ramp loading method, a ramp 50 is installed outside the disk 20 and the head is parked on the ramp 50. To this end, the suspension assembly 40 has an end-tab 45 supported by the ramp 50. When the power of the hard disk drive is turned off and the disk 20 stops rotating, the voice coil motor rotates the swing arm 32 clockwise, that is, in a direction B, and accordingly, the end-tab 45 is moved from the disk 20 to the ramp 50 to be supported by the ramp 50.
In a state in which the read/write head is parked on the ramp 50, when an external impact or vibrations are applied to the disk drive, the actuator 30 is rotated and moved toward the recording surface of the disk 20 from the ramp 50. In this case, the recording surface of the disk 20 may be damaged by the head which contacts the same. Thus, in a state in which the disk 20 stops rotating and the head is parked on the ramp 50, the actuator 30 needs to be locked at a specified position so as not to rotate. For this purpose, an actuator latch 60 is provided.
FIGS. 2 and 3 are a perspective view and a side view, respectively, illustrating the suspension assembly of an actuator shown in FIG. 1.
Referring to FIGS. 2 and 3, the suspension assembly 40 includes a load beam 41 coupled to an end portion of the swing arm 32, the end-tab 45 extending from an end portion of the load beam 41, and a flexure 43 supporting the slider 44 on which the head is mounted. The load beam 41 and the flexure 43 are typically formed of a thin stainless steel plate. The load beam 41 has a thickness of about 0.5 mm to have a certain rigidity while the flexure 43 has a thickness of about 0.2 mm, which is relatively thinner than the load beam 41, so that a free movement is possible as described later. A rear end portion of the flexure 43 is fixed by welding to a surface of the load beam 41, that is, a surface facing the disk 20 while a leading end portion thereof is freely moved up and down. A dimple 42 protruding toward the flexure 43 is formed on the load beam 41. The dimple 42 provides a specified elastic force to the flexure 43 so that the flexure 43 can freely move. Accordingly, smooth pitching and rolling of the slider 44 attached to the flexure 43 are possible.
A protrusion 46 protruding toward a support surface 51 is generally formed on the end-tab 45 to reduce a contact area between the end-tab 45 and the support surface 51 of the ramp 50.
However, in the conventional suspension assembly 40 having the above configuration, when an external impact is applied, the leading end portion of the flexure 43, that is, a free end, vibrates up and down. If the external impact is large enough to cause severe vibrations, the flexure 43 may be bent and deformed or the sliders 44 facing each other bump against each other so that the heads mounted on the sliders 44 may be damaged.

Suspension assembly of actuator for disk drive with portion of load beam inclined lengthwise between limiter and leading end


A pneumatic tire using an inner liner layer comprising a film of a thermoplastic resin, or a blend of a thermoplastic resin and an elastomer, having an air permeation coefficient of not more than 25×10−12 cc·cm/cm2·sec·cmHg and a Young's modulus of 1 to 1000 MPa, wherein a buffer rubber layer containing short fibers is arranged between the inner liner layer and a carcass layer in bead directions from two ends of a widest width belt layer in ranges of at least 20 mm, whereby a problem of trouble during production is solved and the durability of the inner liner layer is improved, without causing a problem of an increase in tire weight.

Pneumatic tires have the problem at the time of tire production that the cord of the carcass layer projects out to the side of the inner liner layer, particularly at the shoulder and breaks the inner liner layer (i.e., spread cord). To deal with such breakage of the inner liner layer, the known method is to provide a tie rubber layer between the inner liner layer and the carcass layer, but this method causes the problem of an increase in the tire weight. As a prior art related to the present invention, for example, Japanese Unexamined Patent Publication (Kokai) No. 59-120501 describes an example of a tie rubber formulation.


A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a wafer substrate having a top surface and a bottom surface, and a conductive pillar in the wafer substrate defined by a deep trench insulator through the top surface and the bottom surface of the wafer substrate. The method for fabricating the semiconductor structure includes following steps. A deep trench is formed from a top surface of a wafer substrate to define a conductive region in the wafer substrate. The conductive region is doped with a dopant. The deep trench is filled with an insulation material to form a deep trench insulator. And the wafer substrate is thinned from a bottom surface of the wafer substrate to expose the deep trench insulator and isolate the conductive region to form a conductive pillar.

The semiconductor industry has experienced rapid growth. The improvements in the density of various electronic components, such as transistors, diodes, resistors, capacitors, allows more components to be integrated into a given area. The number and lengths of interconnections also increase with the increasing density of the electronic components, so are circuit RC delay and power consumption. However, the volume of the integrated components is two dimensional (2D) in nature which is essentially on the surface of the semiconductor wafer. The density of the components on the wafer surface has physical limitation. To solve such limitations, three-dimensional integrated circuit (3D IC) with stacked dies may be introduced which promises the higher speed and density, smaller size, and multifunctional electronic devices.
By integrating multiple dies in a vertical direction, through-silicon vias (TSVs) may be used in such as the stacked dies to connect the dies with different functions and devices TSVs are vias that extend completely through the semiconductor wafer substrate to allow chip-to-chip interconnect schemes or wafer-to-wafer interconnect schemes compatible with 3D wafer-level packaging. The TSVs are filled with conductive material, and connective pads are formed on top and bottom of the conductive material. TSVs are also used to route signals from one surface of a die to the opposite surface, which provides a shorter interconnection distance in contrast with a 2D structure. TSVs are much larger than other standard cells in a design, and thus impact IC performance in a greater degree. Accordingly, improvements in TSVs continue to be sought.

Semiconductor structure and fabricating method thereof

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.


Angular rate sensor and method in which the parameters of a circuit which provides drive signals and processes signals from a sensing element are configured electronically by a programmable memory. Being configured in this manner, the circuit is extremely versatile and can be used with different types of sensing elements.

1. Field of Invention
This invention pertains generally to angular rate sensors and, more particularly, to an electronically configurable circuit for actuating and processing signals in a vibratory rate sensor.
2. Related Art
In a vibratory rate sensor or gyroscope, a mass is driven to vibrate or oscillate along a drive axis. Rotation of the sensor about an axis perpendicular to the drive axis causes a Coriolis force to be applied to the mass along a response axis which is perpendicular to the drive and sensing axes. The force is proportional to the product of the rate of rotation and the velocity of vibration, and the rate of rotation is determined by monitoring the force or the movement of the mass along the response axis.
Different types of sensing elements are used in such devices. Some are fabricated from silicon wafers, and others are fabricated of crystalline quartz and other piezoelectric materials.
With silicon sensing elements, the masses are commonly driven electrostatically, and the Coriolis induced forces are monitored capacitively. Such structures are generally planar, which tends to maximize the capacitance of the sensing elements.
Piezoelectric rate sensors are commonly in the form of tuning forks having at least one pair of tines which are positioned side-by-side and driven out of phase with each other in the plane of the tines. When the tuning fork is rotated about an axis parallel to the tines, the Coriolis force produces a second (pickup) mode of oscillation in which the tines vibrate in an antiphase manner perpendicular to the plane of the tines. Examples of such rate sensors are found in U.S. Pat. Nos. 4,654,663, 4,899,587, 5,396,144, 5,408,876, 5,585,561 and 6,262,520.
The tuning forks in such rate sensors often have more than one pair of tines, e.g. two pairs of tines arranged in an H-shaped configuration, with one pair being driven in the plane of the fork. The out-of-plane vibration produced by the Coriolis force is torsionally coupled to the other pair of tines, and the two pairs vibrate out-of-plane in opposite directions in the pickup mode. With a central mounting point, the out-of-phase motion of the two sets of tines cancels pickup mode forces at the mounting point, minimizing the effect of boundary conditions at the mount on the pickup mode oscillation.
Regardless of the type of sensing element employed, all rate sensors require certain common elements of electronic circuitry in order to function. Vibratory sensors require an oscillator circuit to produce the primary mode of vibration, and the output of the sensor must be detected, amplified, filtered and/or otherwise processed.
In addition to these common features, the electronic circuitry must also meet the individual requirements of a particular sensing element or type of sensing element. The resonance frequency of different types of vibratory rate sensors can, for example, vary widely even within a given class. Drive mode resonant frequencies can range from about 6 KHz to 40 KHz, and the strength of the output signal derived from the various devices can vary over a wide range, depending upon their size and efficiency. Output noise and bandwidth requirements also vary considerably.
In safety-critical applications such as automobile stability controls, built-in fault detection is also highly desirable. However, variations among sensors can make fault detection difficult since it depends, inter alia, upon the range and sensitivity of the sensor.
Heretofore, the variation among sensors has required specially adapted circuitry for driving and processing the signals produced by different types and sub-types of sensing elements. This has generally required either a unique integrated circuit for each type or sub-type of sensing elements or a multitude of external components which must be modified to configure an integrated circuit for use with a particular sensing element.

Electronically configurable rate sensor circuit and method