In a method for magnetic resonance imaging using a partial parallel acquisition technique with a non-Cartesian occupation of k-space, a number of antennas disposed around an imaging volume for reception of magnetic resonance signals and the magnetic resonance signals in the imaging volume are spatially coded by magnetic gradient fields, such that k-space for each antenna is only incompletely occupied with magnetic resonance signals with at least one trajectory proceeding around the origin of k-space. From the reception signals of each antenna, missing sample values of the trajectory that lie on a straight-line segment extending from the origin are determined in k-space according to a weighting with weighting factors from sample values of the trajectory that likewise lie on the straight lines, such that each k-space is completely occupied. A partial image of the imaging area is generated from each completely occupied k-space by means of a Fourier transformation. An image of the imaging volume is generated from the partial images.

1. Field of the Invention
The present invention concerns a method for magnetic resonance imaging using a partial parallel acquisition technique with non-Cartesian occupation of k-space, with a number of antennas disposed around an imaging volume for reception of magnetic resonance signals, and with spatial coding of the magnetic resonance signals in the imaging volume by means of magnetic gradient fields such that k-space is only incompletely occupied with magnetic resonance signals, with at least one trajectory proceeding around the origin of k-space.
2. Description of the Prior Art
A method of the above-described type is known from the article by Pruessmanet al. "Advances in Sensitivity Encoding with Arbitrary k-Space Trajectories", in Magnetic Resonance in Medicine, Vol. 46, pages 638-651, 2001. For magnetic resonance imaging using a partial parallel acquisition technique, the reception signals from a number of antennas disposed around an examination volume are further processed into a image of the imaging volume that is free of aliasing artifacts. In the SENSE method, an aliasing-free reconstruction ensues from individual images of the reception antennas, even though the individual images themselves exhibit aliasing foldings. This is accomplished by k-space not being occupied by the reception signals of the individual antennas, i.e., it is under-scanned. The method specified in the artifacts for reconstruction that is free of aliasing artifacts allows k-space to be occupied with the reception signals along arbitrary trajectories, in particular along spiral trajectories. Spiral trajectories are used in neuro-imaging and cardio-imaging. The k-space trajectories are determined by the magnetic gradient fields used for spatial coding. The reconstruction effort, however, is computationally intensive in this known method.
Because of the non-Cartesian k-space occupation, the artifact behavior is reduced. For example, artifacts known as "blurring" artifacts and fluctuations of physiological parameters (physiological noise) are thereby reduced. This method is additionally less susceptible to deficiencies of the apparatus (such as, for example, inhomogeneities).
A method involving a different partial parallel imaging technique is know from German OS 101 26 078. In that method (as in the SENSE technique) reception signals are acquired by a number of antennas and are sorted into respective k-space associated with the antennas. The k-spaces are again incompletely occupied. In contrast to the SENSE method, however, missing sample points in each scanned k-space are determined from existing sample values with usage of a previously-determined weighting matrix. Such methods belong to the SMASH family and are known under the designations SMASH, AUTO-SMASH, VD-AUTO-SMASH and GRAPPA. Partial images that are then processed into an overall image of the imaging volume are then generated from completed k-spaces of the individual antenna signals by means of respective Fourier transformations. The method is described for a Cartesian occupation of k-space.

Magnetic resonance imaging method using a partial parallel acquisition technique with non-Cartesian occupation of k-space


An arthroscopic method for reattaching a rotator cuff tendon to a humeral head may include creating a trough in the top of the humeral head, creating a cavity in the lateral portion of the humeral head, creating one or more tunnels between the cavity and the trough, retrieving sutures affixed to a loose end of the tendon through the trough, at least one tunnel, and the cavity; and passing the sutures through a tensioning and securing device, which is then implanted in the cavity, and the sutures are variously pulled or released to pull, tension, or release the sutures until the tendon is secured in the trough. The trough is preferably created using a unique extendable, angled surgical burr.

The present method and apparatus for rotator cuff repair generally relates to methods and devices for surgical repair of soft tissue damage. More specifically, the present method and apparatus-for rotator cuff repair relates to methods and devices for reattaching tendons to bone.
It has been estimated that over 15 million people in the United States alone are at risk from disability related to rotator cuff injuries. The rotator cuff is a group of four muscles in the shoulder: the supraspinatus; the infraspinatus; the teres minor; and the subscapularis. The supraspinatus extends over the top of the humerus, and is attached to the top of the humeral head by a tendon. This tendon can tear, and often tears away from the humeral head. These tears cause pain and limited mobility. Surgical repair of rotator cuff tears is common, but the surgical technique used to accomplish these repairs has changed significantly over time.
Historically, rotator cuff repairs have been performed in an open fashion. The traditional open approach involved a relatively large incision, e.g. 5 cm, and splitting of the deltoid to "open" the affected area for repair. Once open, the humeral head was exposed, and a burr and rongeur were typically used to create a trough in the top of the humeral head, exposing bone marrow on all sides and the bottom of the trough. A transosseous bone tunnel or tunnels were also created between the trough and the lateral cortex. The tendon was sutured, and the sutures passed through transosseous tunnel(s). The tendon was then pulled into the trough, and the sutures were typically tied over the lateral cortex for fixation.
The open approach is still described as the "gold standard" of rotator cuff repair because of the excellent functional results that rarely deteriorate over time. The trough provides excellent biological fixation between the tendon and the bone. Yet, a major disadvantage of the open technique is the required traumatic splitting of the deltoid. This often causes a long recovery time for patients, and can result in deltoid dehiscence and deltoid atrophy.
Over time, rotator cuff repair has evolved to include less invasive and traumatic approaches. A "mini-open" approach was developed that still involved an open incision and splitting of the deltoid to fix the tendon to the humeral head, but took an arthroscopic approach to other aspects of the repair. For example, in the mini-open approach, an arthroscope can be used to inspect the tear and surrounding anatomy. The tendon can also be released arthroscopically, and a subacromial bursectomy and decortication of the greater tuberosity performed. The tendon is typically fixed, however, using anchors or transosseous tunnels through a traditional open incision. Decortication of the humeral head is intended to promote a biological healing response, but is inferior to the creation of a trough.
Most recently, various techniques for purely arthroscopic rotator cuff repair have been developed. In these approaches, tendon fixation is also accomplished arthroscopically. These purely arthroscopic approaches rely on suture anchors implanted arthoscopically into the humeral head for fixation of the tendon. One disadvantage of the purely arthroscopic approaches is the technical complexity of such an operation. The most significant disadvantage of this approach, however, is that it lacks the biological healing associated with the tendon-to-trough healing of the open repair. Today's arthroscopic repair failures are commonly associated with bone, anchor, suture, or suture to tendon failure. Numerous refinements in suture techniques and anchor designs have been made in response, yet these refinements do not promote biological healing that may be crucial to obtaining lasting rotator cuff repairs.

Arthroscopic method and apparatus for rotator cuff repair


An optical transmitting unit comprises an integrated optical transmitter module including an LD, a TEC configured to heat or cool the LD, a thermal sensor configured to sense a temperature of the LD, and a package configured to house the LD, the thermal sensor, and the TEC, an MCU, and a temperature detection circuit configured to detect a temperature outside the package. The thermal sensor is thermally coupled with the TEC and is also thermally coupled with the outside of the package, and the MCU defines data output from the temperature detection circuit as an internal temperature when the LD is being energized, and estimates the data of internal temperature on the basis of the temperature detected with the thermal sensor and the data when the LD is not being energized.

Field of the Invention
The present invention relates to an optical transmitter.
Related Background of the Invention
Recently, for speed-up and capacity increase of a communication network, miniaturization and power consumption reduction of an optical transceiver (including both optical transmitter and optical receiver) have been continuously demanded from an optical communication system market. For example, as a 100-gigabit optical transceiver, CFP (100G Form-factor Pluggable) products have started to spread in the market. Also, lately, study of industrial standards called MSA (Multi Source Agreement) such as CFP2 and CFP4 of the next generation is underway for further miniaturization by a factor of one half and one quarter from the CFP.
When miniaturizing (highly integrating) an optical transceiver, it is preferable that internal components and an IC can be connected through a serial communication bus with a small number of signal lines. For example, in Patent Literature 1, plurality of internal components like a PHY (Physical Layer Chip) to communicate in a physical layer by electric signals, a CPU (Central Processing Unit) to monitor and control inside of the optical transceiver, a memory and so on, are interconnected through an internal serial communication bus. For the optical transceivers such as the CFP products, for example, two optical transceivers are connected to each other through a duplex optical fiber for bidirectional communication by optical signals. Therefore, an optical transmitter (optical transmitting unit) to convert an electric signals to an optical signal and transmit the converted optical signal outward and an optical receiver (optical reception unit) to receive an optical signal and convert the received optical signal to an electric signal are included in an optical transceiver.
Patent Literature 1: Japanese Patent Application Laid-Open Publication No. 2008-113207
The optical transmitter described above has two modes, one of which is a power saving mode for suppressing the entire power consumption as much as possible, practically less than a value specified in the MSA standard, and another of which is an operating mode for normally transmitting an optical signal. For example, for the CFP products, the power consumption should be smaller than 1 W for the power saving mode, but may be larger than 8 W for the operating mode. In the power saving mode, it is needed to run only the minimum parts such as an MCU (Micro Controller Unit) including a communication circuit with an external device (host system) of an upper layer and an arithmetic processing circuit, and to shut off an internal power supply to the other components such as a signal processing circuit for transmission and reception of optical signals. At the time, when the internal power supply for the other components is stopped and one of terminals of a component connected to the serial communication bus is pulled down to Low level of logic signal levels, the communication among all the components connected through the serial communication bus becomes unavailable because the serial communication bus is stuck
An optical transmitter is required to monitor a temperature inside the optical transceiver and answer the monitored temperature to the host system for monitoring and control in the upper layer. Hereinafter, the temperature inside the optical transceiver is called "internal temperature". The internal temperature corresponds to an environmental temperature common for a plurality of internal components, and is different from a temperature inside a specific component (for example, an optical transmitter module). As a method of monitoring the internal temperature, an analog circuit to monitor resistance of a thermistor, which changes with the temperature, is used. Also, as another method, a prescribed component with a temperature detection circuit, which detects the temperature and outputs data of the detected temperature through the serial communication bus is used.
However, the analog circuit needs a large mounting area because a lot of electrical parts are included. Therefore, from a viewpoint of the miniaturization of the optical transceiver, the method of using the prescribed component and communicating with it through the serial communication bus is preferable because the prescribed component is available as an IC with a small package. However, as described above, since the serial communication bus is stuck in the power saving mode, it becomes difficult to monitor the internal temperature through the serial communication bus.


Improved storage systems which use write off-loading are described. When a request to store some data in a particular storage location is received, if the particular storage location is unavailable, the data is stored in an alternative location. In an embodiment, the particular storage location may be unavailable because it is powered down or because it is overloaded. The data stored in the alternative location may be subsequently recovered and written to the particular storage location once it becomes available.

Enterprise data centers have a high power consumption which limits the density of servers and increases the total cost of ownership. Power management features have been introduced for server CPUs (central processing units) which provide low power states and dynamic clock and voltage scaling and reduce power consumption significantly during periods when the CPU is idle. There is no such advanced power management, however, for the storage sub-system of a data center and as a result storage uses a significant fraction of the power budget. In an example, a typical enterprise grade disk consumes 12 W even when idle, compared to 24 W for a dual-core processor. As servers typically have many disks, the power consumption due to storage exceeds that of the processors.
The embodiments described below are not limited to implementations which solve any or all of the disadvantages of known data centers and their storage sub-systems.


Roughly described, a floating gate memory cell is fabricated by forming an oxide-nitride dielectric layer above a floating gate of the memory cell and in an oxide growth region not above a floating gate. The nitride layer is removed in the oxide growth region using a mask that protects the nitride layer above the floating gate, and then the bottom oxide layer is removed in the oxide growth region using a wet etch that does not affect the nitride remaining above the floating gate. First and second oxide layers are then formed both above the floating gate and in the oxide growth region, to act as the top layer of ONO above the floating gate and as the gate oxide in the oxide growth region. One of the first and second oxide layers is formed using in-situ steam generation.

1. Field of the Invention
The invention relates to the formation of interpoly dielectric in flash and other floating-gate-based memory, and more particularly to the use of an in-situ steam generation (ISSG) procedure in the formation of a first oxide layer.
2. Description of Related Art
Read only memory (ROM) is a memory device that contains fixed data patterns determined at the time of fabrication. In the fabrication of a ROM, it is necessary to make a storage cell that maintains data after the applied power is turned off. Because data to be stored in a ROM is predetermined prior to fabrication, the change of a single bit in the stored data would require an alteration of the entire circuit and the manufacturing process.
To avoid having to custom design each ROM from scratch, ROMs are often manufactured using a process known as mask programming, by which data is stored in the ROM at one of the final process steps. A ROM made this way is called a mask ROM because the programming in the device is carried out by means of the mask at one of the final process steps, typically a metal layer.
Although mask ROM is more flexible than conventional ROMs, data must still be stored in the device during fabrication. In this regard, programmable read only memory (PROM) is a further improvement to the mask ROM. Data can be electrically programmed in a PROM device by the user. However, a PROM cell can be programmed only once.
A still further improvement to mask ROM and PROM is an EPROM, or erasable programmable ROM. A typical EPROM is shown in FIG. 1A, where a floating gate 12 is located between a control gate 14 and a substrate 10. An isolation region 16 surrounds both the floating gate 12 and the control gate 14. The isolation region includes a bottom oxide layer 110 between the floating gate 12 and the substrate 10, and a gate oxide layer 112 between the floating gate 12 and the control gate 14. Note that an EPROM cell is structurally similar to an NMOS device, except that the former has two gate conductors and no LDD (lightly doped drain) region.
The contacts of the source 13 and the substrate 10 of an EPROM are both coupled to ground, whereas the control gate 14 and the contact of the drain 15 are connected to high potentials VG and VD, respectively. The control gate 14 is reverse-biased with respect to the drain 15. Because the drain 15 is not protected by an LDD structure, the PN junction of an n-doped drain 15 and a p-doped substrate 10 will foster the well-known carrier multiplication effect. Some of the hot electrons produced as a result of this effect will be collected by the drain 15, while the rest of them will transverse through the isolation region 16 and be trapped in the floating gate 12. The voltage supplied to the control gate 14 and the drain 15 are switched off as soon as these hot electrons are trapped in the floating gate 12. The electrons trapped in the floating gate do not have enough energy to escape because of the potential barrier in the isolation region 16 surrounding the floating gate 12. As a consequence, the data may be stored in the floating gate 12 for years.
The electric charges in the floating gate 12 determine the value stored in the memory cell. If no electric charge is stored at the floating gate 12, the floating gate 12 will have no influence on the electrical field that control gate 14 generates in the channel region between the source 13 and drain 15. However, if the floating gate 12 is charged with electrons, the electric charges in the floating gate 12 will shield the field of the control gate 14 and generate an electrical field in the channel region; this second electrical field is opposite in sign to the field of the active control gate 14. Thus, a small active signal at the control gate 14 cannot generate a sufficiently strong field to turn on the transistor. Only with a much higher control gate potential can the storage transistor be turned on; i.e., the field of the control gate 14 must be strong enough to compensate the field of the floating gate 12 and to make the channel between source 13 and drain 15 conductive.
Referring again to FIG. 1A, an EPROM can be programmed by loading the floating gate 12 with electrons. The stored data may be erased by exposure to ultraviolet (UV) radiation for a certain period of time. Essentially, the electrons trapped in the floating gate 12 absorb sufficient energy from the UV light and escape from the floating gate 12 in the same way as they were previously trapped. An EPROM with an empty floating gate 12 may be reprogrammed again in accordance with the above-described programming process.
Because the electric charges in the EPROM can only be erased with ultraviolet radiation, it is necessary for the packaging of an EPROM to have a window made of, e.g., quartz glass, to allow the die to be exposed to ultraviolet radiation. This results in an increase in the manufacturing cost. Furthermore, all the electric charges (and hence any data or program) in the device are erased all at once, dictating a time-consuming reprogramming process. These concerns can be overcome by using an electrically erasable programmable read-only memory (EEPROM), where the electric charges in the floating gate 12 can be electrically erased. As shown in FIG. 1B, EEPROM is programmed in the same way as the EPROM, i.e., through hot electron ejection generated by a relatively long voltage pulse between the control gate 14 and the drain 15. In this process, electrons generated in the drain 15 traverse through an oxide layer 18 into the floating gate 12. This is the well-known Fowler-Nordheim tunneling mechanism, and the bottom oxide layer 18 is known as tunneling oxide layer. In the case where both the floating gate 12 and the control gate 14 are made of polysilicon, the gate oxide layer 112 is sometimes called an interpoly dielectric. The interpoly dielectric need not be strictly an oxide; often it is made of an oxide-nitride-oxide (ONO) composite.
To erase an EEPROM, an inverse voltage is applied between the control gate 14 and the drain 15. As a result, electrons in the floating gate 12 travel to the drain 15 again through the tunneling oxide layer 18. The stored data is erased accordingly; new data can be programmed into the memory cell again. Because the inverse voltage is applied to each pair of the control gate 14 and the drain 15, each gate can be erased independent of other gates. This allows bit-by-bit erasure and reprogramming of the EEPROM cell, a significant improvement over the aforementioned EPROM cell.
A more recent type of memory cell is the flash EPROM cell, which is often used as a substitute for floppy disk or hard disk drives. This is because flash memory may be programmed as flexibly as a random access memory (RAM). The structure of flash memory cells is similar to that of EEPROMs, except that the tunneling oxide layer 18 is often made thinner than that in an EEPROM memory cell, allowing lower programming and erasure voltages applied between the control gate 14 and the drain 15; see FIG. 1A. Flash memories also typically have simplified array structures, improving speed and density but permitting erasure only in a block-by-block manner.
Many varieties of floating gate memories have been developed in addition to those described above, including twin bit or split cell memories, memories which use conductive material (e.g. polysilicon) as the floating gate, and memories which use dielectric material (e.g. silicon nitride within an ONO composite) as the floating gate.
Data storage in all these variations is accomplished by trapping hot electrons or Fowler-Nordheim tunneling electrons in a floating gate. Therefore, it is vitally important to control the thickness of the gate dielectric layer and the tunneling oxide layer between the floating gate and the semiconductor substrate.
Typical conventional methods for controlling the thickness of the gate oxide or tunneling oxide layer are depicted as follows. As shown in FIG. 2A, after a floating gate 12 is fabricated, an interpoly dielectric layer is formed on the floating gate 12. This interpoly dielectric layer is a composite of oxide-nitride-oxide (ONO) dielectric materials, including a bottom silicon oxide layer 22, a silicon nitride layer 24, and a top silicon oxide layer 26; all three layers are deposited typically via a chemical vapor deposition (CVD) process. The conventional bottom oxide layer 22 is usually grown to a thickness between 20 to 40 nm; the nitride layer 24 may be anywhere between 10 to 25 nm; and the top oxide layer 26 is usually limited to approximately 3 to 4 nm.
Because a gate oxide layer must be grown in the peripheral area after forming the oxide-nitride-oxide composite structure, the interpoly dielectric layer in the peripheral area must be removed before the oxidizing process. Since it is difficult to grow a gate oxide layer on the silicon nitride layer 24, the conventional process dictates that certain portions of the silicon nitride layer 24 of the ONO interpoly dielectric in the peripheral area be completely removed before growing the gate oxide. Several conventional methods may be used to accomplish this goal.
One method for removing selected portions of the ONO dielectric is shown in FIG. 2B, where the top oxide layer 26 and the silicon nitride layer 24 over a gate oxide growth region 28 are removed via a dry etch process using CF4 as the etchant. Because the etch rate in the bottom oxide is relatively low, the dry etch process stops within the bottom oxide layer 22. Next, a gate oxide layer 30 is formed on the bottom oxide layer 22 through a thermal oxidation process; see FIG. 2C. The thickness of the remaining bottom oxide layer 22 is an important factor in this method. If the thickness of the remaining bottom oxide layer 22 cannot be ascertained, it will be difficult to control the thickness of the gate oxide layer that is subsequently grown. On the other hand, it is not advisable to etch away all of the remaining bottom oxide 22 with hydrofluoric acid, because the photoresist film 32 (shown in FIG. 2B) cannot be used as a shield to the hydrofluoric acid; the ONO structure on top of the floating gate 21 will also be etched. Using the buffered oxide etch (BOE) process does not solve this problem, either, because the field oxide region 34 will be etched at a greater etch rate, causing deterioration of the isolation region between the gates.
A second method for removing selected portions of the ONO dielectric is depicted in FIG. 2D, in which a dry etch process (using CF4 as the etchant) is used to remove the entire ONO structure from the gate oxide growth region 28. This etch process stops at the substrate 10. Next, as is illustrated in FIG. 2E, a gate oxide layer 36 is formed on the gate oxide growing region 28 via a thermal oxidation process. This method requires that the dry etchants be able to etch silicon dioxide but not silicon; otherwise, the silicon substrate would also be etched, resulting in adverse effects such as gate oxide quality degradation.
In U.S. Pat. No. 6,136,647, ONO was used as the interpoly dielectric layer in a floating gate memory structure. But in order to facilitate removal of the nitride sub-layer before growing the gate oxide, the interpoly dielectric was formed initially to include only an oxide-nitride (ON) composite layer instead of the full ONO layer. The portion of the ON layer over the gate oxide growth region was then removed. The removal of such an ON film was said to cause much less damage to the substrate compared to the conventional case of the ONO film. After the removal process, a thermal oxidation process and an oxide CVD process were used to grow the gate oxide and the top oxide of the ONO layer simultaneously. This process was said to provide better assurance of the quality of the gate oxide and the ONO interpoly dielectric layers.
However, thermal oxidation processes and oxide CVD processes can sometimes create significant stresses within the oxide layer. The large stresses often create defects in nearby active regions, which can result in leakage current and degrade reliability. The insulation between the two gates can degrade, and word-line to word-line shorts can occur.
Accordingly, it is an object of the present invention to provide a method for fabricating a memory device that avoids the drawbacks of the conventional methods.

Method for manufacturing interpoly dielectric


The drain breakdown voltage walk-in of a dual-source, dual-gate PMOS transistor is significantly reduced by utilizing source regions which have a width that is equal to or less than a width of the drain region. By utilizing source regions with widths that are equal to or less than the width of the drain region, the current density in the drain region is significantly reduced which reduces the number of hot charge carriers that are trapped at the silicon-to-silicon dioxide interface which, turn in, reduces the drain breakdown voltage walk-in rate.

1. Field of the Invention
The present invention relates to MOS transistors and, more particularly, to a multi-source, multi-gate MOS transistor with a drain region that is wider than the source regions.
2. Description of the Related Art
A MOS transistor is a well-known semiconductor device that can be fabricated in many well known ways. MOS transistors can be formed as n-channel (NMOS) devices or as p-channel (PMOS) devices. In addition, MOS transistors can be formed as low-voltage devices or as high-voltage devices.
FIGS. 1A and 1B show views that illustrate a prior-art, single-source, single-gate, high-voltage PMOS transistor 100. FIG. 1A shows a schematic layout that represents a plan view of transistor 100, while FIG. 1B shows a cross-sectional view of transistor 100 taken along line 1B—1B of FIG. 1A.
As shown in FIGS. 1A and 1B, PMOS transistor 100 includes an n-type semiconductor material 110, and spaced-apart p-type source and drain regions 112 and 114 that are formed in semiconductor material 110. Source region 112 includes a heavily-doped (p+) region, while drain region 114 includes an extended lightly-doped (p−) region 114A and a heavily-doped (p+) region 114B.
PMOS transistor 100 also includes a channel region 116 of semiconductor material 110 that lies between the source and drain regions 112 and 114, and a layer of insulation material 120, such as gate oxide, that lies over channel region 116. Further, transistor 100 includes a gate 122, such as polysilicon, that lies on insulation material 120 over channel region 116.
In addition, PMOS transistor 100 includes an isolation material ISO that surrounds transistor 100. Isolation material ISO lies adjacent to the two short sides, and the long side of p+ drain region 114B. P+ drain region 114B must be formed a distance WC from the nearest edge of isolation material ISO. On the other hand, isolation material ISO contacts source region 112, extended p− region 114A, and channel region 116.
In operation, when a negative drain-to-source voltage VDS is present, and the gate-to-source voltage VGS is more negative than the threshold voltage, PMOS transistor 100 turns on and holes flow from source region 112 to drain region 114. When the gate-to-source voltage VGS is more positive than the threshold voltage, PMOS transistor 100 turns off and no holes (other than a very small leakage current) flow from source region 112 to drain region 114.
FIGS. 2A and 2B show views that illustrate a prior-art, dual-source, dual-gate, high-voltage PMOS transistor 200. FIG. 2A shows a schematic layout that represents a plan view of transistor 200, while FIG. 2B shows a cross-sectional view of transistor 200 taken along line 2B—2B of FIG. 2A.
As shown in FIGS. 2A and 2B, PMOS transistor 200 includes an n-type semiconductor material 210, spaced-apart p-type source regions 212A and 212B that are formed in semiconductor material 210, and a drain region 214 that is formed in semiconductor material 210 between, and spaced apart from, the source regions 212A and 212B.
Source regions 212A and 212B have heavily-doped (p+) regions. On the other hand, drain region 214 includes an extended lightly-doped (p−) region 214A, and a heavily-doped (p+) region 214B that is surrounded at the surface by p− region 214A. Drain region 214 always receives holes when transistor 200 is turned on, while source regions 212A and 212B always provide holes when transistor 200 is turned on. In addition, source regions 212A and 212B have a width W1 that is greater than a width W2 of p+ drain region 214B.
PMOS transistor 200 also includes a first channel region 216A of semiconductor material 210 that lies between the source and drain regions 212A and 214A, and a second channel region 216B of semiconductor material 210 that lies between the source and drain regions 212B and 214A.
In addition, PMOS transistor 200 includes an isolation material ISO that surrounds transistor 200. Isolation material ISO contacts the source regions 212A and 212B, the extended p− region 214A, and the first and second channel regions 216A and 216B. Further, both the top and bottom sides of p+ drain region 214B must be formed a width WC from the nearest edge of isolation material ISO. As a result, the width W2 of p+ drain region 214B is 2 WC less than the width W1 of p+ source and drain regions 212A and 212B.
PMOS transistor 200 additionally includes a first insulation layer 220A, such as gate oxide, that lies over channel region 216A, and a second insulation layer 220B, such as gate oxide, that lies over channel region 216B. PMOS transistor 200 further includes a first gate 222A, such as polysilicon, that lies on insulation layer 220A over channel region 216A, and a second gate 222B, such as polysilicon, that lies on insulation layer 220B over channel region 216B.
In operation, when source regions 212A and 212B are electrically connected together, gates 222A and 222B are electrically connected together, a negative drain-to-source voltage VDS is present, and the gate-to-source voltage VGS is more negative than the threshold voltage, PMOS transistor 200 turns on and holes flow from both of the source regions 212A and 212B to drain region 214.
When the gate-to-source voltage VGS is more positive than the threshold voltage, PMOS transistor 200 turns off and no holes (other than a very small leakage current) flow from the source regions 212A and 212B to drain region 214. Due to the multi-fingered structure, PMOS transistor 200 sources more current than PMOS transistor 100.
PMOS transistors 100 and 200 are both in common use, with transistor 200 often being preferred over transistor 100 because of the greater current capacity and reduced effective area of transistor 200. One problem with transistor 200, however, is that transistor 200 has an accelerated drain breakdown voltage walk-in.
When PMOS transistor 200 is initially fabricated, transistor 200 has a drain-to-semiconductor material breakdown voltage. Over time, however, positive hot charge carriers become trapped at the silicon—silicon dioxide interface (between semiconductor material 210 and insulation layers 220A and 220B) near drain region 214 which, in turn, causes the drain breakdown voltage to change.
When the trapped charge carriers cause the drain breakdown voltage of a PMOS transistor to decrease over time, the process is known as drain breakdown voltage walk-in. (Walk-out can also occur.) Continued drain breakdown voltage walk-in eventually leads to the failure of the device. As a result, a device that has an accelerated drain breakdown voltage walk-in is a device that can fail prematurely due to changes in the drain breakdown voltage.
FIG. 3 shows a graph that illustrates the drain breakdown voltage walk-ins of five prior-art, high-voltage PMOS transistors when stressed for varying periods of time. In this example, the stress times and temperature are VGS=−14V, VDS=−100V, and Temp=110° C. When the drain breakdown voltage has walked-in by 30V, the device is considered to have failed.
The five high-voltage PMOS transistors include a (100/3.5) double gate (combined) transistor 310, a (100/3.5) double gate (separated) transistor 312 (which represents transistor 200), a (50/3.5) double gate (combined) transistor 314, a (100/3.5) single gate transistor 316 (which represents transistor 100), and a (50/3.5) single gate transistor 318.
As shown in FIG. 3, the drain breakdown voltage of PMOS transistor 316 (which represents PMOS transistor 100) remains unchanged when stressed up to 100 kS. After this, however, the drain breakdown voltage walks in quickly and exceeds the 30V failure point. On the other hand, the drain breakdown voltage of PMOS transistor 312 (which represents PMOS transistor 200) remains unchanged for only 100 s. After 300 s, the drain breakdown voltage also walks in quickly and exceeds the 30V failure point.
Thus, as shown in FIG. 3, dual-source, dual-gate, high-voltage PMOS transistor 312 (which represents transistor 200) has a drain breakdown voltage that walks-in approximately 500× faster than the drain breakdown voltage of single-source, single-gate, high-voltage PMOS transistor 318 (which represents transistor 100). As a result, there is a need for a high-voltage, multi-gate PMOS transistor that has a reduced drain breakdown voltage walk-in rate.

Multi-source, multi-gate MOS transistor with a drain region that is wider than the source regions


A display device which displays an image having a size corresponding to a display area exposed outside a housing is disclosed. In one aspect, the display device includes a flexible display panel having a recognition pattern, a housing, and a light-receiving sensor. The recognition pattern includes a plurality of self-luminous indicators arranged according to a first direction, and having different colors or different light-emitting intensities. The housing is coupled to the flexible display panel for entering/discharging of the flexible display panel according to the first direction such that a display area of the flexible display panel is variously exposed. The light-receiving sensor is positioned corresponding to the recognition pattern in the housing and respectively recognizes a plurality of indicators to sense the exposed display area of the flexible display panel.

1. Field
The described technology relates generally to a display device. More particularly, the described technology relates generally to a display device having a flexible display panel, and a driving method thereof.
2. Description of the Related Technology
A flexible display panel may be rolled onto a roller installed inside a housing. In this case, the flexible display panel may be drawn out of the housing by rotation in one direction of the roller and may be returned to the housing by rotation of the roller in an opposite direction.
The flexible display panel has a display area that is exposed and changed as it is moved into or out of the housing, and thus it is necessary to display an image with a size corresponding to the exposed display area. For this, the display device must correctly recognize the size of the display area that outside the housing.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the described technology and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

Flexible display device and driving method thereof


A shelf management system is disclosed having a tray defining a first mating structure and a second mating structure, a shelf management component having a spring biased pusher connected thereto and movable between a first position wherein the pusher is extended to a rear of the shelf management component and a second position wherein the pusher is retracted to a front of the shelf management component, and an interstitial member positioned between the shelf management component and the tray to secure the shelf management component to the tray and hinder lateral movement of the shelf management component with respect to the tray. Improved components of the shelf management system are also disclosed as are methods relating to same.

Shelving systems have been used for decades to organize shelves and the presentation of products on shelves. For example, U.S. Pat. No. 2,516,122 issued to Hughes on Jul. 25, 1950, U.S. Pat. No. 2,688,409 issued to Echlin on Sep. 7, 1954, U.S. Pat. No. 2,884,139 issued to Dunham on Apr. 28, 1959, U.S. Pat. No. 3,285,429 issued to Propst on Nov. 15, 1966, U.S. Pat. No. 3,339,746 issued to McCabe on Sep. 5, 1967, U.S. Pat. No. 3,780,876 issued to Elkins on Dec. 25, 1973, U.S. Pat. No. 3,868,021 issued to Heinrich on Feb. 25, 1975, and U.S. Pat. No. 4,615,276 issued to Garabedian on Oct. 7, 1986, all disclose shelving systems that use dividers that are laterally moveable about front and/or rear rails associated with the shelves to neatly present items on the shelves in an organized manner and in such a way as to maximize the use of available shelving space.
In addition to the problems of neatly displaying items on shelving and organizing items in a way to maximize the use of available shelving space, retailers were also faced with the problem of keeping product at the front of shelves to maintain neat appearance, give off the impression of a well-stocked store and to ensure older product is sold before newer product. Many gravity feed systems were devised to solve this problem, such as U.S. Pat. No. 2,769,551 issued to Just on Nov. 6, 1956. Additional push and/or pull systems were then devised to accommodate shelving systems or product where gravity feed systems were not an option or at least did not work as well as desired. U.S. Pat. No. 3,008,583 issued to Lindell on Nov. 14, 1961, U.S. Pat. No. 3,161,295 issued to Chesley on Dec. 15, 1964, Japanese Patent No. JPS56-33414 issued Nov. 27, 1979 and Japanese Patent No. JPS63-61007 issued Dec. 8, 1984 disclose examples of such systems which automatically advance stored product toward the front of the shelving unit as items are removed from the shelf. These automatic advancement merchandisers are typically referred to as "front-facing", "auto-facing" or "self-facing" merchandisers and are desired because they greatly reduce the amount of time retailers or suppliers to retailers have to spend straightening or organizing their shelves to achieve the objectives discussed above (e.g., neatly presenting product in an organized manner, maximizing use of available shelving space, keeping product at the front of shelves to give the impression of a well-stocked store, to ensure older product is sold before newer product, etc.).
One problem associated with such front-facing merchandisers, however, is that they require advance knowledge of the product size before positioning the system on a shelf in order to maximize the use of available shelving space or the retailer has to be willing to give-up some shelf space by using a merchandiser that is not sized for the specific product or good being displayed. For example, in the 1950s, 1960s and 1970s, many of the products displayed via such merchandising systems were cigarette boxes and cartons of cigarette boxes which did not all come in the same size or shape. Thus, if a generic merchandiser was used that would fit all products, there would certainly be wasted space due to some packages being smaller than others. In order to solve this problem, systems were devised that would accommodate for products of varying size, and allow the merchandiser or merchandising system to be adjusted to varying product sizes so as to accommodate product of different size and shape and maximize the available shelving space (also known as maximizing "pack-out" or "packout"). U.S. Pat. No. 3,308,961 issued to Chesley on Mar. 14, 1967, Swiss Patent No. CH412251 issued to Gemperle/ETH Zurich on Apr. 1, 1968 and U.S. Pat. No. 3,452,899 issued to Libberton on Jul. 1, 1969, all disclose merchandisers that adjust to fit the specific size of the product being displayed and, thereby allowing retailers to maximize use of available shelving space or pack-out.
Over the years, a variety of different front-facing merchandisers that account for product size have been provided. Some comprise self-contained systems that simply rest on top of shelving like U.S. Pat. No. 4,730,741 issued to Jackie on Mar. 15, 1988, U.S. Pat. No. 5,110,192 issued to Lauterbach on May 5, 1992, U.S. Pat. No. 5,673,801 issued to Markson on Oct. 7, 1997 and Japanese Patent Application Publication No. JPH11-155701 published to Kawajun on Jun. 15, 1999. Other front-facing merchandisers utilize the front and/or rear rail systems discussed above such as British Patent No. GB2027339 issued to Corjon on Feb. 20, 1980, French Published Patent Application No. FR2667229 published to Corjon on Apr. 3, 1992, U.S. Pat. No. 5,390,802 issued to Pappagallo on Feb. 21, 1995, International Patent Application No. WO95/13003 published to PPE Ltd. on May 18, 1995, European Patent Application Publication No. EP0956794 published to HMG Worldwide on Nov. 17, 1999, Japanese Published Patent Application No. JPH11-342054 published to Kawajun on Dec. 14, 1999, Japanese Published Patent Application No. JPH11-346879 published to Kawajun on Dec. 21, 1999, Japanese Published Patent Application No. JP2000-004996 published to Kawajun on Jan. 11, 2000. Many of the latter references further improve the merchandisers by reducing the number of merchandiser components and making more of the system parts out of plastic, such as by integrating the pusher track and divider and making the combined divider and track structure, the corresponding pushers, and front and rear rails out of plastic. These merchandisers not only allow for quick and easy adjustment to the specific size of the product being displayed in order to maximize usage of available shelving space, but also allow for easy adjustment to accommodate changes in displayed product size, the addition of new product and/or the reorganization of a shelf or product category on the shelf (typically referred to as "cut-ins" and "resets") without requiring removal of product inventory.
In addition, several systems have been designed with features to improve the performance of such front-facing merchandisers. For example, systems have been designed with pusher locks for locking the pusher in a rear stocking or re-stocking position such as U.S. Pat. No. 3,161,295 issued to Chesley on Dec. 15, 1964, U.S. Pat. No. 4,730,741 issued to Jackie on Mar. 15, 1988, U.S. Pat. No. 5,634,564 issued to Spamer on Jun. 3, 1997, U.S. Pat. No. 5,673,801 issued to Markson on Oct. 7, 1997 and British Patent GB2392667 issued to Gamble on Mar. 10, 2004. In some systems, pushers have been designed with dampers to slow the progression of the pusher as product is removed from the merchandiser so that the pusher does not exert too much force against the displayed product (which could damage the product and/or force it out of the merchandiser unintentionally). Such systems are disclosed in Japanese Published Patent Application No. JPH06-38735 published to Sunco Spring on May 24, 1994 and British Published Patent Application No. GB2392667 published to Gamble on Mar. 10, 2004. Other improvements include systems having pushers that can be adjusted in width (e.g., such as by having pivoting members to widen the reach of a pusher) or adjusted in height (e.g., such as by attaching a pusher attachment that extends the upper bounds of the pusher). Such systems are disclosed in U.S. Pat. No. 5,390,802 issued to Pappagallo on Feb. 21, 1995, U.S. Pat. No. 5,634,564 issued to Spamer on Jun. 3, 1997, Japanese Published Patent Application No. JPH11-342054 published to Kawajun on Dec. 14, 1999 and U.S. Pat. No. 6,142,317 issued to Merl on Nov. 7, 2000. Some systems also provide for adjusting the height of the system to accommodate taller types of product or stacked product such as U.S. Pat. No. 4,901,869 issued to Hawkinson on Feb. 20, 1990 and U.S. Pat. No. 6,598,754 issued to Weller on Jul. 29, 2003.
Other areas where significant efforts have been expended in this field relate to the desire to make the shelf organizers easy to adjust to accommodate re-planograms (e.g., changes to the planogram or store shelf layout), which may be due to a desire to change how products are displayed on a shelf or for other reasons (e.g., due to changes in a particular product's container or shape, etc.). For decades, it has been desirable to have the shelf organization components movable horizontally along a front or rear rail or channel to allow the system to be adjustable to accommodate product of different sizes and easily adjust for re-planograms. See, e.g., U.S. Pat. No. 2,516,122 issued to Hughes on Jul. 25, 1950, 2688409 issued to Echlin on Sep. 7, 1954, 2884139 issued to Dunham on Apr. 28, 1959, 3285429 issued to Chesley on Mar. 14, 1967, U.S. Pat. No. 3,339,746 issued to McCabe on Sep. 5, 1967, U.S. Pat. No. 3,780,876 issued to Elkins on Dec. 25, 1973, U.S. Pat. No. 3,868,021 issued to Heinrich on Feb. 25, 1975, U.S. Pat. No. 4,615,276 issued to Garabedian on Oct. 7, 1986, U.S. Pat. No. 4,712,694 issued to Breslow on Dec. 15, 1987 and U.S. Pat. No. 4,830,201 issued to Breslow on May 16, 1989. One shortcoming with such systems, however, was that the easier they were to adjust horizontally, the more likely they were to shift during use which often was undesirable. Thus, further improvements came by creating systems that required movement of the shelf components out of their normal resting position during use to a separate position to allow for horizontal adjustment and prevent such movement when in their normal resting position for usage. See, e.g., U.S. Pat. No. 5,110,192 issued to Lauterbach on May 5, 1992, U.S. Pat. No. 5,673,801 issued to Markson on Oct. 7, 1997, U.S. Pat. No. 6,041,720 issued to Hardy on Mar. 28, 2000, and U.S. Pat. No. 7,971,735 issued to Mueller Jul. 5, 2011. These too, however, have had problems and/or increased expense of the units due to their complex make-up/configuration.
Even with all of these improvements, there are still other areas in which merchandisers can be improved, such as by further reducing the number of merchandiser components and further simplifying and/or perfecting the operation of the merchandiser including some of the very areas of operation discussed above. Accordingly, it has been determined that a need exists for an improved front-facing merchandiser and components for same which overcome the aforementioned limitations and which further provide capabilities, features and functions not available in current merchandisers and for improved methods relating to same.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions and/or relative positioning of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments. It will further be appreciated that certain actions and/or steps may be described or depicted in a particular order of occurrence while those skilled in the art will understand that such specificity with respect to sequence is not actually required. It will also be understood that the terms and expressions used herein have the ordinary technical meaning as is accorded to such terms and expressions by persons skilled in the technical field as set forth above except where different specific meanings have otherwise been set forth herein.

Shelf management system, components thereof, and related methods


Methods are provided for amplification and monitoring of oligonucleotide amplification in which a primer has an overlap with one or more bases of a detection probe.

Efficient PCR amplification is particularly required in biological applications in which highly sensitive and accurate detection is required. In most primer and probe design programs it is recommended that probes should be designed first and then primers should be designed close to the probes without overlapping sequences (e.g. Primer Express Software Version 2.0, Applied Biosystems, Foster City, Calif.). PCR amplification methods are widely used in the diagnostic industry. Unexpectedly, we discovered that overlapping primer and probe still give efficient PCR, expanding probe and primer design opportunities particularly in challenging sequence environments. The PCR method and its clinical applications have been disclosed (U.S. Pat. No. 4,683,202; Lynch J R, Brown J M. J Med. Genet., 27:2-7 (1990); Yang S, Rothman R E. Lancet Infect Dis., 4:337-48 (2004))
The schematic representation of the overlapping probe and primer in a novel amplification method of the invention is shown in FIG. 1. FIG. 1a) and b) show a schematic representation of primer and probe location on the target, with a primer sequence overlapping with a probe sequence. FIG. 1c) shows a schematic representation of two overlapping primer sequences. FIG. 1d) shows a schematic representation of a probe sequence overlapping with both primers.
5′-Minor groove binder (MB)-Quencher (O)-oligonucleotide-Fluorophore (Fl)-3′ or 5′-MB-Fl-oligonucleotide-Q-3′ or 5′-Fl-oligonucleotide-Q-MB-3′ probes have not been overlapped with primers. It is suggested in the PCR amplification literature that "one should avoid complementarity at 3′-ends of primer pairs as this promotes the formation of primer-dimer artifacts and reduces the yield of the desired products (Innis, M. and Gelfand, D. Optimization of PCR in Innis, M., Gelfand, D., Sninsky, J. and White, T., Editors. PCR PROTOCOLS A GUIDE TO METHODS AND APPLICATIONS. Academic Press, San Diego, Calif. pages 3-12, 1989.) Since the probe and primer have overlapping complementary sequences and available 3′ sequences, it was expected the 5′-MB-Q-oligonucleotide-Fl-3′ or 5′-MB-Fl-oligonucleotide-Q-3′ or 5′-Fl-oligonucleotide-Q-MB-3′ probes overlapping with a primer would give poor amplification. However, unexpectedly it was observed that efficient amplification occurs in the case of FIG. 1b. Without being bound to a theory, we suspect that the probe containing a MB ligand, Q and a Fl has a tight conformation in solution where these components are in close proximity. We have shown that such a probe in solution is quenched from temperatures ranging from 25 to 95° C., suggesting that overlaps from 1 to about 7 bases are not enough to overcome the in solution stable conformation of the probe to allow hydrogen bond formation. In FIG. 1a the Primer-Probe dimer should not give rise to any artifacts. The 3′-end is not available for priming. Surprisingly, this type of design can provide good amplification.


A computer implemented method for calculating a charge density q1 of a first gate of a double gate transistor comprising a thin body with a first and a second gate interface, the method including determining, using a physical processor, an initial estimate q1,init of the charge density of the first gate; performing, using the physical processor, at least two basic corrections of the initial estimate based on a Taylor development of a function fzero(q1) able to be nullified by a correct value of the charge density q1 of the first gate.

Ultra-thin body transistors such as FinFETs or Ultra-Thin Body and Box (UTBB) MOSFETs are required for sub-20 nm nodes because of their excellent electrostatic integrity and reduced variability. Compared to FinFET, UTBB technology on thin buried oxide presents two decisive benefits: a much simpler process than FinFET and the possibility to use the backplane bias to optimize the power consumption and speed trade-off at circuit level. To take full advantage of this latter benefit, circuit designers need compact models that describe properly the transistor behavior for a wide range of back bias.
S. Khandelwal, Y. S. Chauhan, D. D. Lu, S. Venugopalan, M. U. A. Karim, A. B. Sachid et al, "BSIM-IMG:A compact model for ultrathin-body SOI MOSFETs with back-gate control", IEEE Transactions on Electron Devices, vol. 59, pp.2019-2026, 2012 and O. Rozeau, M. A. Jaud, T. Poiroux, M. Benosman, "Surface potential based model of ultra-thin fully depleted SOI MOSFET for IC simulations", IEEE International SOI conference, 2011, have disclosed such compact models describing the transistor behavior. However, in such models, the interface between the body and the buried oxide is assumed always depleted, which provides correct results in reverse and low forward back bias (FBB) range. However, when a strong FBB is applied, inversion occurs first at the back interface, which has a significant impact on device characteristics. Consequently, the previous models are not realistic when a strong FBB is applied.

Computer implemented method for calculating a charge density at a gate interface of a double gate transistor

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES


In a configuration where systems C and D having different reception quality requirements are present, a peak suppressor generates a replica of a signal from system C combined together with a signal from system D before peak suppression. Based on the replica, system specific peak suppressing units respectively perform peak suppression on signals of each system according to the respective reception quality requirements of each system. A combining unit combines the peak-suppressed signals of each system. Hence, peak suppression on signals from systems requiring different reception qualities is performed at an appropriate degree according to each system.

1. Field of the Invention
The present invention relates to a peak suppressor and more particularly to a peak suppressor built in a wireless transmitter.
2. Description of the Related Art
In the field of wireless digital communication, a technology to improve transmission amplifier efficiency involving peak suppression of a transmission target signal prior to amplification by a transmission amplifier is conventionally known. When a peak-to-average power ratio (PAPR) of an input signal to the transmission amplifier is reduced by peak suppression, output back-off of the transmission amplifier decreases, and amplifier efficiency improves.
FIG. 15 is a graph illustrating the relationship between input/output characteristics of the transmission amplifier and the peak of each signal. As shown in FIG. 15, the signal in the lower portion of the figure having an operating point A as an average power has a large back-off, and hence efficiency of the transmission amplifier is reduced. On the other hand, the signal in the upper portion of the figure is obtained by clipping a signal that has an operating point B as an average power, a waveform similar to that of the signal in the lower portion of the figure and a power larger than a given power, i.e., it is a signal subjected to peak suppression. Since the PAPR of the signal is reduced by peak suppression in this manner, the back-off is restrained, thereby enhancing the efficiency of the transmission amplifier. Various peak suppression modes have been proposed.
FIG. 16 is a block diagram of a wireless transmitter having a conventional clipping mode peak suppressor. As shown in FIG. 16, a conventional clipping mode peak suppressor 1 has an amplitude calculator 2, a comparator 3, a suppression coefficient calculator 4, a selector 5, a delay unit 6, and a multiplier 7. The amplitude calculator 2 calculates an amplitude of a transmission target signal generated by a digital signal generator 8. If i and q respectively represent amplitudes of a signal i and a signal q of the transmission target signal, then an amplitude of the transmission target signal is obtained based on [√{square root over ((i2+q2))}]. The comparator 3 compares the amplitude obtained by the amplitude calculator 2 with a preset threshold value Vth.
The suppression coefficient calculator 4 calculates [Vth/√{square root over (i2+q2))}] as a value required to suppress a peak of the transmission target signal. The selector 5 selects a suppression coefficient based on a result of the comparison by the comparator 3. The selector 5 selects the value obtained by the suppression coefficient calculator 4 if the amplitude obtained by the amplitude calculator 2 is larger than the threshold value Vth [Vth/√{square root over ((i2+q2))}>Vth], and selects 1 if not. The delay unit 6 delays the transmission target signal for a period equivalent to the time required from amplitude calculation of the transmission target signal generated by the digital signal generator 8 to selection of the suppression coefficient.
The multiplier 7 multiplies the transmission target signal output from the delay unit 6 by the suppression coefficient selected by the selector 5. Therefore, the peak suppressor 1 outputs a peak suppressed transmission target signal when the amplitude obtained by the amplitude calculator 2 is larger than the threshold value Vth, and outputs the transmission target signal as it is when not. A digital/analog (D/A) converter 9 converts the transmission target signal output from the peak suppressor 1 into an analog signal, a mixer 10 multiplies the analog signal by a local carrier wave from a local oscillator 11, and a resulting signal is input to a transmission amplifier 12. The signal amplified by the transmission amplifier 12 is transmitted via an antenna 13.
FIG. 17 is a block diagram of a wireless transmitter having a conventional windowing function mode peak suppressor. As shown in FIG. 17, a windowing function mode peak suppressor 16 has a windowing function generator 17 between the suppression coefficient calculator 4 and the selector 5 in the peak suppressor 1 depicted in FIG. 16. That is, the peak suppressor 16 is configured to apply a windowing function generated by the windowing function generator 17 to a value obtained by the suppression coefficient calculator 4. Peak suppression distorts a signal in both the clipping mode and the windowing function mode, thereby leading to deterioration in reception quality. That is, a reduction in the PAPR due to peak suppression and the reception quality have a trade-off relationship. Therefore, the degree of peak suppression must be determined so as to satisfy the reception quality set for each system.
A transmitter that controls for signal level adjustment of a multi-carrier signal obtained by combining multiple carriers is known. This transmitter includes a peak suppressing unit that detects the presence/absence of a peak based on a sum of the power levels of respective input carriers and outputs carriers obtained by suppressing power levels of respective carriers so as to reduce the total power level below a predetermined peak threshold value when a peak is detected. The transmitter further includes an input power calculator that calculates an average power level with respect to the respective carriers before input to the peak suppressing unit and an output power calculator that calculates an average power level with respect to the respective carriers after output from the peak suppressing unit; a monitoring unit that outputs level control information required to control signal levels of respective carriers output from the peak suppressor based on the average power level calculated by the input power calculator and the average power level calculated by the output power calculator; and a level adjusting unit that adjusts the levels of respective carriers based on corresponding level control information. For an example of such a transmitter, refer to Japanese Patent Application Laid-open No. 2004-166245, claim 3, paragraph 0025.
However, the aforementioned conventional peak suppression technologies are all technologies for suppressing signal peak in a single system, and do not perform system specific signal peak suppression for multiple systems where each system has a different required reception quality. The Japanese Patent Application Laid-open No. 2004-166245 does not clearly explain or suggest that peak suppression is performed for multiple systems specific to the different reception quality requirements of each system.
Therefore, a problem arises with the conventional technologies when the same frequency band is used to perform services in systems. For example, under the Third Generation Partnership Project (3GPP), standardization of a 3GPP long-term evolution system (LTE system) is currently in progress.
The LTE system uses the same frequency band as that in widely prevalent third-generation (3G) systems. Therefore, both the LTE system and the 3G system coexist in the same frequency band at the start of a service of the LTE system. In such a case, provision of separate transmission amplifiers for each of the systems, the LTE system and the 3G system, in a transmitter is inefficient. Accordingly, a configuration where a common transmission amplifier is provided for both of the systems and signals of both of the systems are input to the transmission amplifier in a multi-carrier combined state is desirable.
However, the LTE system and the 3G system have defined reception qualities that are different from each other. Therefore, similar to the conventional technologies, by a configuration in which peak suppression is performed on a combined multi-carrier signal obtained by combining the signals of both systems and the resulting signal is input to the transmission amplifier, peak suppression is performed in compliance with the system having a higher required reception quality, i.e., the LTE system. Accordingly, weak peak suppression is effected with respect to the system having a lower required reception quality, i.e., the 3G system, resulting in a problem that PAPR cannot be sufficiently reduced.
To at least solve the above problems in the conventional technologies, it is an object of the present invention to provide a peak suppressor that can perform an appropriate degree of peak suppression on signals of multiple systems according to differing reception quality requirements of each system.


An optical sheet is moved by a conveyor belt, and at least one beam is configured above the conveyor belt. When the beam is intersected by the moving optical sheet, the optical sheet is determined to be curled. The present invention achieves automatic in-line measuring of optical sheet curls by precise optical measurement and thus enhances measuring accuracy and raises measuring speed.

1. Field of Invention
The present invention relates to a manufacturing and quality controlling method of optical sheets. More particularly, the present invention relates to an apparatus and method for automatically measuring a curl of an optical sheet in real time.
2. Description of Related Art
A liquid crystal display (LCD) has many advantages over conventional types of displays having high display quality, small volume, low driving voltage and low power consumption and being lightweight. Hence, LCDs are widely used in small portable televisions, mobile telephones, video recording units, notebook computers, desktop monitors, projector televisions and so on, and have gradually replaced the conventional cathode ray tube (CRT) as a mainstream display unit.
Polarizers are main components of a liquid crystal panel in a liquid crystal display. A polarizer can be composed of one or more optical sheets, and in addition to the polarizing function can have other functions, such as anti-peeping or optical compensation. An optical sheet may have a curl due to bad manufacturing. The curled optical sheet cannot be adhered smoothly onto the liquid crystal panel and therefore causes the liquid crystal display to have bad quality.
The prior art usually manually measures curls of optical sheets after manufacturing the optical sheets to select good optical sheets, which meet the quality control level regarding curls. However, the conventional method of manual measurement is not convenient and is also inaccurate, and thus easily causes poor quality control due to measurement errors. Moreover, manual measurement takes a long time, slows the manufacturing rate, wastes manpower and thus increases manufacturing costs.

Apparatus and methods for automatically measuring a curl of an optical sheet


The subject matter described herein includes a method for enhanced signaling gateway status detection and selection for emergency calls. The method includes, in a mobility management entity (MME) including at least one processor, detecting that a signaling gateway is in a risky state using a combination of echo request and call setup signaling timeouts. The method further includes marking the signaling gateway as risky in a signaling gateway status database maintained by the MME. The method further includes performing signaling gateway selection for an emergency call in a manner that excludes signaling gateways marked as risky. The method further includes routing the emergency call to a signaling gateway selected by the signaling gateway selection.

The signaling gateway is the node in the telecommunications network that communicates call setup signaling messages to a remote signaling gateway to set up voice calls between users. In some instances, the signaling gateway may go out of service, because of a hardware or software failure. In other instances, call setup may be delayed because there are multiple legs of the call between the end users. It may be desirable to avoid a failed or failing SGW for call setup procedures. In the event of multi-leg call setup traversal, it is desirable to wait for the SGW to respond to a call setup request. It may be difficult to distinguish between SGW failure and multi-leg traversal.
The mobility management entity (MME) is the node in the 3GPP mobile communications network that communicates with a signaling gateway to setup a call. While there are existing mechanisms for the MME to detect failure of a signaling gateway, the mechanisms can result in unacceptable delays in detecting the failure. In addition, as stated above, it is difficult to determine whether the signaling gateway has failed or whether the delay in establishing the call is due to communications between multiple legs of the call.
For some types of calls, such as regular priority calls, the existing signaling gateway failure detection mechanisms are sufficient, as a delay in call setup is not critical for normal priority calls. However, for emergency calls, such as E911 calls, delayed call setup is unacceptable.
Accordingly, there exists a need for improved methods, systems, and computer readable media for signaling gateway status detection and selection for emergency calls.

Methods, systems, and computer readable media for enhanced signaling gateway (SGW) status detection and selection for emergency calls


Rolling element bearings and particularly design features which reduce peak stresses acting on the bearing elements which affect bearing service life and rated load caring capacity. To reduce maximum stresses imposed by applied loads acting on the bearings, one or more of the bearing elements features an asymmetric configuration in which circumferential segments of the bearing element have increased flexibility. Such flexibility reduces maximum loads on the bearing and spreads out the load over a larger circumferential region. In addition to applied load components, nonuniform loads can act on rolling bearing elements at their lines of contact with the bearing raceways. In some embodiments of this invention segments of the bearing feature greater flexibility in order to adjust the load distribution acting on the rolling elements lines of contact.

This invention relates to rolling element bearings and particularly to such bearings having design features for providing a more favorable sharing of loading on the bearing elements thus providing increased service life and/or load carrying capacities.
Rolling element bearings such as ball, tapered, needle, and cylindrical bearings are used in widespread applications. When rolling element bearings are used to support pure radial loads, or a combination of radial and thrust loads (as opposed to pure axial or thrust loads) they have an inner race surrounded by an outer race with rolling elements interposed between them. The operating life of rolling element bearings is related to the maximum stresses experienced by the bearing components. Cyclical application of such stresses produce fatigue damage to the bearing, leading to ultimate bearing failure. By providing a more even sharing of rolling element loading around the circumference of the races and forcing a more favorable distribution of stress at each rolling element raceway contact, bearing life and load carrying capacity can be increased. This invention is related to design features for providing such loading conditions.
In their operating environments, bearings may be exposed to applied loads which create contact stresses which are not uniform around the circumference of one of the races and act repeatedly on the same area. Consequently, the contact stress developed between the rolling elements and the bearing races vary as a function of the angular position on one or both of the races. Various design approaches are available for reducing peak contact stresses, such as enlarging the overall bearing size so that larger and more numerous rolling elements combine to restrain the applied loads. Such design approaches, however, possess tradeoffs and disadvantages of their own.
One facet of this invention involves design approaches which enable bearings to be designed in a way that peak contact stresses are reduced by causing the loading around the circumference of a bearing race to be spread out over a larger angular range. By reducing peak contact stresses, the life of the bearing can be extended, or in the alternative, the bearing can be rated to have a higher maximum external load carrying capability.
Conventional rolling element bearings have inner and outer races which are rotationally symmetrical. In other words, a radial cross-section taken at any circumferential position has the same cross-sectional shape and area. In accordance with this invention, the bearing inner and/or outer race is provided with circumferential segments which are more flexible in response to rolling element contact loads as compared with other segments. Such "structural asymmetry" can be provided by modification to the bearing mounting structure or to the bearing races themselves. In a preferred embodiment of this invention, one or both of the races have a variation in cross-sectional shape which renders certain circumferential segments less stiff than other segments. By placing the more flexible circumferential segments in the region where peak applied loads are expected, a reduction in peak contact stress occurs. This reduction provides a bearing having a longer service life characteristic and also enables the bearing to be used with higher applied loads. Various embodiments of this invention describe techniques for providing asymmetrical flexibility characteristics for the bearing.
In addition to the circumferential distribution of applied load, rolling element bearings may be subjected to misalignment between the inner and outer bearing races. Such misalignment as well as other factors can cause the force distribution along the lines of contact between the rolling elements and the races to be nonuniform. Significantly higher forces and resulting stresses can be encountered at one axial end of the rolling elements as compared to the other. In addition to conditions where one axial end of a rolling element is disproportionately loaded, transient loading conditions along the bearing element lines of contact can occur. In such conditions, the peak stress alternates between ends of the bearing elements, or one rolling element repeatedly has a higher average normal load than another element. As in the case of applied load induced stresses, a reduction in peak stress and elimination of transients along the rolling element lines of contact also tend to increase the bearing service life.
In view of the foregoing, this invention further involves techniques for producing greater uniformity in stress distribution along the bearing element contact lines by selectively providing portions of the axial length of one of the bearing races with increased flexibility. Such increased flexibility can be provided either by modification to the bearing housing or the races themselves. Additional benefits and advantages of the present invention will become apparent to those skilled in the art to which this invention relates from the subsequent description of the preferred embodiments and the appended claims, taken in conjunction with the accompanying drawings.

Bearing with asymmetrical flexible section


An alcohol fermentation process and composition that includes production of alcohol esters by esterification of product alcohol in a fermentation medium with a carboxylic acid (e.g., fatty acid) and a catalyst (e.g., lipase) capable of esterifying the product alcohol, such as butanol, with the carboxylic acid to form the alcohol esters. The alcohol esters can be extracted from the fermentation medium, and the product alcohol recovered from the alcohol esters. The carboxylic acid can also serve as an extractant for removal of the alcohol esters from the fermentation medium.

Alcohols have a variety of applications in industry and science such as a beverage (i.e., ethanol), fuel, reagents, solvents, and antiseptics. For example, butanol is an alcohol that is an important industrial chemical and drop-in fuel component with a variety of applications including use as a renewable fuel additive, as a feedstock chemical in the plastics industry, and as a food-grade extractant in the food and flavor industry. Accordingly, there is a high demand for alcohols such as butanol, as well as for efficient and environmentally-friendly production methods.
Production of alcohol utilizing fermentation by microorganisms is one such environmentally-friendly production method. In the production of butanol, in particular, some microorganisms that produce butanol in high yields also have low butanol toxicity thresholds. Removal of butanol from the fermentation vessel as it is being produced is a means to manage these low butanol toxicity thresholds. Thus, there is a continuing need to develop efficient methods and systems for producing butanol in high yields despite low butanol toxicity thresholds of the butanol-producing microorganisms in the fermentation medium.
In situ product removal (ISPR) (also referred to as extractive fermentation) can be used to remove butanol (or other fermentative alcohol) from the fermentation vessel as it is produced, thereby allowing the microorganism to produce butanol at high yields. One ISPR method for removing fermentative alcohol that has been described in the art is liquid-liquid extraction (U.S. Patent Application Publication No. 2009/0305370). In general, with regard to butanol fermentation, the fermentation medium which includes the microorganism is contacted with an organic extractant at a time before the butanol concentration reaches a toxic level. The organic extractant and the fermentation medium form a biphasic mixture. The butanol partitions into the organic extractant phase decreasing the concentration of butanol in the aqueous phase containing the microorganism, thereby limiting the exposure of the microorganism to the inhibitory butanol. In order to be technically and economically viable, liquid-liquid extraction requires contact between the extractant and the fermentation broth for efficient mass transfer of the product alcohol into the extractant; phase separation of the extractant from the fermentation broth (during an/or after fermentation); efficient recovery and recycle of the extractant; and minimal decrease of the partition coefficient of the extractant over a long-term operation.
The extractant can become contaminated over time with each recycle, for example, by the build-up of lipids present in the biomass that is fed to the fermentation vessel as feedstock of hydrolyzable starch. As an example, during the conversion of glucose to butanol, a liquified corn mash loaded to a fermentation vessel at 30 wt % dry corn solids can result in a fermentation broth that contains about 1.2 wt % corn oil generated by simultaneous saccharification and fermentation (with saccharification of the liquified mash occurring during fermentation by the addition of glucoamylase to produce glucose). The dissolution of the corn oil lipids into oleyl alcohol (OA) serving as an extractant during ISPR can result in build-up of lipid concentration with each OA recycle decreasing the partition coefficient for the product alcohol in OA as the lipid concentration in OA increases with each recycle of OA.
In addition, the presence of the undissolved solids during extractive fermentation can negatively affect the efficiency of the alcohol production. For example, the presence of the undissolved solids may lower the mass transfer coefficient inside the fermentation vessel, impede phase separation in the fermentation vessel, result in the accumulation of corn oil from the undissolved solids in the extractant leading to reduced extraction efficiency over time, increase the loss of solvent because it becomes trapped in solids and ultimately removed as Dried Distillers' Grains with Solubles (DDGS), slow the disengagement of extractant drops from the fermentation broth, and/or result in a lower fermentation vessel volume efficiency.
Several approaches for reducing the degradation of the partition coefficient of the extractant used in extractive fermentation have included wet milling, fractionation, and removal of solids. Wet milling is an expensive, multi-step process that separates a biomass (e.g., corn) into its key components (germ, pericarp fiber, starch, and gluten) in order to capture value from each co-product separately. This process gives a purified starch stream; however, it is costly and includes the separation of the biomass into its non-starch components which is unnecessary for fermentative alcohol production. Fractionation removes fiber and germ, which contains a majority of the lipids present in ground whole corn resulting in a fractionated corn that has a higher starch (endosperm) content. Dry fractionation does not separate the germ from fiber and therefore, it is less expensive than wet milling. However, fractionation does not remove the entirety of the fiber or germ, and does not result in total elimination of solids. Furthermore, there is some loss of starch in fractionation. Wet milling of corn is more expensive than dry fractionation, but dry fractionation is more expensive than dry grinding of unfractionated corn. Removal of solids including germ containing lipids, from liquefied mash prior to use in fermentation can substantially eliminate undissolved solids as described, for example, in co-pending, commonly owned U.S. Provisional Application Ser. No. 61/356,290, filed Jun. 18, 2010. However, it would be advantageous if the degradation of the partition coefficient of the extractant caused by contamination by lipid can be reduced even without fractionation or removal of substantially all undissolved solids. Converting the lipids present in a liquefied mash into an extractant that can be used in ISPR is another method of decreasing the amount of lipids that are fed to the fermentation vessel as described, for example, in co-pending, commonly owned U.S. Provisional Application Ser. No. 61/368,436 and U.S. Provisional Application Ser. No. 61/368,444, both filed on Jul. 28, 2010.
There is a continuing need for alternative extractive fermentation methods which do not necessitate the partitioning of the product alcohol between the fermentation medium and the ISPR extractant as a means to reduce the toxic effect of the product alcohol such as butanol on the microorganism, and which can also reduce the degradation of the partition coefficient of a fermentation product extractant.

Production of alcohol esters and in situ product removal during alcohol fermentation


Provided is an improved catalyst for treating exhaust gas, particularly for selectively reducing NOx, and methods for using the same, wherein the catalyst includes a blend of a transition metal promoted zeolite and an un-promoted zeolite, wherein both zeolites have the same framework type.

1. Field of Invention:
The present invention relates to catalysts, articles, and methods for treating combustion exhaust gas.
2. Description of Related Art:
Combustion of hydrocarbon fuel produces exhaust gas that contains, in large part, relatively benign nitrogen (N2), water vapor (H2O), and carbon dioxide (CO2). But the exhaust gas also contains, in relatively small part, noxious and/or toxic substances, such as carbon monoxide (CO) from incomplete combustion, hydrocarbons (HC) from un-burnt fuel, nitrogen oxides (NOx) from excessive combustion temperatures, and particulate matter (mostly soot). To mitigate the environmental impact of exhaust gas released into the atmosphere, it is desirable to eliminate or reduce the amount of undesirable components, preferably by a process that, in turn, does not generate other noxious or toxic substances.
NOx, which includes nitric oxide (NO), nitrogen dioxide (NO2), and nitrous oxide (N2O), is a burdensome component to remove from exhaust gas generated by lean burn engines (e.g., diesel engines and gas turbines). The reduction of NOx to N2 is particularly problematic in lean burn exhaust gas because the exhaust gas contains enough oxygen to favor oxidative reactions instead of reduction. Notwithstanding, NOx can be reduced by a process commonly known as Selective Catalytic Reduction (SCR).
An SCR process involves the conversion of NOx, in the presence of a catalyst and with the aid of a nitrogenous reducing agent, such as ammonia, into elemental nitrogen (N2) and water. In an SCR process, ammonia is added to an exhaust gas stream prior to contacting the exhaust gas with the SCR catalyst. The reductant is absorbed onto the catalyst and the NOx reduction reaction takes place as the gases pass through or over the catalyzed substrate. Chemical pathways for stoichiometric SCR reactions using ammonia include:2NO+4NH3+2O2→3N2+6H2O2NO2+4NH3+O2→3N2+6H2O
N2O is produced in limited quantities by combustion. However, undesirable processes occurring in SCR systems also include several competitive, nonselective reactions with oxygen, which is abundant in the system. These reactions can either produce secondary emissions including the production of N2O. Commercial SCR catalysts, including vanadia, iron-zeolites, and copper-zeolites, all produce N2O. Exhaust gas treatment systems, particularly in which the NO2 content has been increased to exceed the NO level in the feed gas, allow N2O formation via pathways such as:8 NO2+6 NH3→7 N2O+9 H2O4 NO2+4 NH3+O2→4 N2O+6 H2O2NH3+2O2→N2O+3H2OAccordingly, there remains a need for improved SCR catalysts that provide improved NOx conversion and reduced N2O make. The present invention satisfies these needs amongst others.

Zeolite blend catalysts for treating exhaust gas


An emergency exit arrangement for a vehicle and or a building comprising of a plurality of spring pressured stud assembly having a plurality of locking pin in the upper region connected correspondingly to a plurality of rope which is connected to a first pulling device; a plurality of locking pin in the lower region connected correspondingly to a plurality of rope which is connected to a second pulling device. Sequential pulling of the first and the second pulling device ejects out the aperture cover. The pulling devices are electrical, operated by pressing a button; or through temperature sensor, impact sensor, pressure sensor, smoke sensor and or a combination thereof. The pulling devices are alternatively rotatable knobs. The aperture cover is easily mountable.

Emergency exit windows are a safety requirement so that persons entrapped in an enclosure, whether a vehicle or a building, can free themselves by removing the covering matter, usually glass. In a way, any and every window, which is open-able in some easy way, can also serve the purpose of emergency exit. However, it is important that the opening is clear enough to facilitate quick and unhindered evacuation.
Patent GB1248307 discloses one of the early emergency windows for passenger vehicles. The ejection arrangement is compressed air based and is fairly complex in construction as well as functioning. Patent application number DE102006057288A1 discloses another emergency exit window which opens from inside as well as outside, though the opening remains partial, as also disclosed in CN103818220 as well as CN103847471. CN202879413 discloses a kind of belt alarming device for fast opening escape window, which opens partially. CN201428362Y disclose pressure sensitive fire escape.
Patent Publication No: US2011/0289850A1 discloses an emergency egress assembly which provides wider opening to exit than the normal window when the normal opening arrangement fails. The design is robust and needs elaborate linkages and dismantling. Patent Publication No: WO2013/184356 A1 discloses a speedier opening design. Both these disclosures are more suited for armored vehicles.
Patent Publication no. CN201442505U discloses a vehicular sealing window capable of performing quick escape, wherein the entire glass is removable by tearing the seal away.
Patent application No: GB2514673A discloses a concept of removing the window by deploying an unfastening device which could be triggered by heat, pressure, explosive to shatter the window pane; however the construction and operation of the unfastening device is difficult to gauge from this document. Also claimed is an escape chute for evacuation. Patent Application No: WO2006/103305 A1 (also published as EP1710105 B1) discloses an auto or manually ejecting emergency exit window using spring assisted braided wire actuated by actuation device. The document does not elaborate the mechanical arrangement nor actuation device for workability.
Modern transport vehicles as well as buildings have controlled temperature and other comfort parameters. Openings are for fitment of transparent material like glass, polycarbonate and the like, provided for cross visibility, sunshine et cetera. Consequently, the fitment of transparent material is generally of a permanent nature and is made to ensure proper insulation of environment of the transport vehicle or the building from outside. In such a case, using such opening as emergency exit warrants that the insulation of environment in the normal course is not compromised. Such an arrangement is not prior known. It is due to this reason that most vehicles and buildings provide a hammer like object to break the glass, instead of several known designs.
Breaking the glass is obviously not a comfortable option for passengers or occupants, given the trauma of situation warranting emergency evacuation.
Our design effectively addresses this gap.


An object of the present invention is to provide ferrite particles having a high saturation magnetisation, and being excellent in the dispersibility in a resin, a solvent or a resin composition, a resin composition including the ferrite particles, and a resin film composed of the resin composition. The ferrite particles are a single crystalline body having an average particle size of 1 to 2000 nm, and Mn-based ferrite particles having a spherical shape, and have a saturation magnetisation of 45 to 95 Am2/kg. The resin composition includes the ferrite particles as a filler. The resin film is composed of the resin composition.

As flexible printed wiring boards used for wiring to electronic devices, cables and the like, there have been proposed resin films including fillers such as silicon oxide, titanium oxide, and aluminum oxide each having an average particle size of 1 to 10 μm (see, for example, Patent Literature 1).
Such a resin film is formed, for example, as follows: a filler is dispersed in a resin composition including a resin and an aqueous solvent or an organic solvent-based solvent, then the resin composition including the filler is applied to a substrate, subsequently the solvent is evaporated to harden the resin. Then, a metal wiring is formed by laminating a metal layer such as a copper layer on the resin film. In this case, the resin film which function as a base is necessary when the metal layer is laminated. On the other hand, after the lamination of the metal layer, it is necessary to remove the resin film which is now unnecessary depending on the shape of the metal wiring.
Accordingly, in order to simply and efficiently perform the removal of the resin film, it is conceived that ferrite particles are used as a filler in place of silicon oxide or the like, the resin film is adsorbed to remove by applying a magnetic field to the resin film.
It is conceivable to use as the ferrite particles, for example, Mn—Mg ferrite particles disclosed in Patent Literature 2, having an average particle size of 20 to 50 μm and a magnetisation (saturation magnetisation) of approximately 60 Am2/kg.

This patent is subject to a terminal disclaimer.

Ferrite particles, resin composition and resin film


A method for designing a photomask pattern is provided. First, all line ends of object patterns are determined with reference to layout data. Then, object patterns, front edge portions, and joints, which are aligned on the same line extending along the Y-axis, are connected to form first reticle data. Reticle pattern data having data representing binding portions serving as light blocking portions is formed. The front edge portions being adjacent to each other and aligned in the X-axis are connected and adjacent joints being aligned in the same manner as the front edge portions are also connected to form second reticle data. Then, portions are provided at central regions between the binding portions so as to connect the adjacent binding portions including the front edge portions and the joints. Then, reticle data having data representing the binding portions serving as transparent patterns is formed.

1. Field
The embodiments discussed herein are related to a method for manufacturing semiconductor devices which facilitate miniaturization, and a method for designing photomask patterns.
2. Description of the Related Art
In line with the requirement for miniaturization of semiconductor devices, recently the width of gate electrodes and the like has also been required to be smaller than a wavelength of exposure light used in patterning and positive-type resists have been mainly used in such an exposing step. However, for features smaller than the wavelength of the exposure light, proximity effects considerably appear when a resist pattern is formed and may result in differences between a pattern of a reticle and a pattern of a resist transferred from the reticle. Accordingly, a technique for compensating for the differences is applied, in which serifs on line ends of a reticle pattern, which are called hammer-heads, are provided in order to form a desired resist pattern.
To reduce the proximity effects, optical proximity correction (OPC) has been used, and this technique can be used to suppress variation of linewidth of patterns. However, the technique cannot also improve resolution. Therefore, to enhance the resolution, techniques of super-resolution are occasionally applied. Examples of super-resolution techniques include a technique using a phase-shift mask such as a Levenson-type mask and a technique using oblique illumination such as zone plate illumination.
However, in a case in which two conductive line ends face each other or a line end faces the side of another line, there may be difficulties in using such super-resolution techniques to form a resist pattern, which is designed to have fine features as small as the wavelength of exposure light, with a sufficient lithography margin. As a result, short circuits may occur at gate electrodes and the like. For currently manufactured TEGs that include several billion minute transistors, short circuits are a serious problem even if a short circuit occurs in only one transistor among several billion transistors.
Japanese Laid-open Patent Publication No. 2004-103999 discloses a technique in which two exposing steps for patterning gate electrodes to be a desired shape are performed. These two steps are performed with different reticles under different optical conditions. However, if this technique is applied, a lithography margin, which is needed in at least one exposing step, may be undesirably reduced and defects may easily occur in a developing step, which may lead to short circuiting of the pattern.

Method for manufacturing semiconductor device and method for designing photomask pattern