The present application relates to a marine buoy featuring a novel bracing assembly disposed within a marine buoy and featuring a plurality of bracing members extending between and connecting to a first fastening member and a second fastening member.

Marine buoys are manufactured from a broad selection of materials, in sizes and shapes appropriate to the application. Buoys encountering highly active seas tend to be of large and sturdy construction. They are generally configured to provide long range visibility and to survive the tremendous static and dynamic forces impressed upon them in open sea and inclement weather. Large, deep-water buoys of composite or plastic materials will typically have framed constructions designed to house floatable materials, with the frames designed to withstand severe environmental conditions. These frameworks are usually extremely heavy, of metal construction, and can be expensive to produce because of concern for the forces acting upon them in deep water and in a corrosive environment.
On the other hand, in more sheltered locations, buoys tend to be smaller, requiring less visual range, and having somewhat less robust construction. Unlike large buoys, small buoys are commonly constructed of lightweight materials, such as foamed materials encapsulated within a solid, or high-density plastic skin. These smaller buoys will typically have a mooring eye embedded either directly within the plastic skin or attached to a single rod element that passes through the buoy body. The mooring eye is typically attached to one end of the buoy. Use of such lightweight materials and construction methodologies is particularly advantageous because of low costs, low weights, transportability and buoyancy.
Unfortunately, in larger buoy applications, use of the above described designs and lightweight materials can result in premature failure of a buoy. This failure is often due not only to the proportionally larger acting forces placed upon the buoy, but also to the inability of a single rod element configuration to effectively distribute the forces and lateral stresses commonly encountered in more severe marine environments.
Accordingly, there is a need for a large marine buoy that can be made from one or more lightweight materials, as are typically found in smaller buoys, but that can still effectively handle and distribute the forces placed upon the large buoy design in more severe marine environments. Further, there is a need for a comparatively large marine buoy for use in severe marine environment that can be produced efficiently at moderate cost.


A system and method of disambiguating entities in a computerized web search includes identifying a set of potential meanings for an entity; retrieving at least one web page having descriptions referencing the entity; establishing a base web page having a selected context for the entity; attributing dimensions of a vector space attributed to domains in the retrieved web page; and computing a probability of similarity between the referenced entity in the retrieved web page and the entity in the base web page. The method includes corresponding a similarity measure between the dimensions of the vector space attributed to domains in the retrieved web page and a likelihood of the retrieved web page referring to the entity in the base web page. The method further includes ranking web pages based on the computed probability of similarity.

1. Field of the Invention
The embodiments of the invention generally relate to web page searching and indexing and, more particularly, to a streamlined system and process to facilitate efficient web page searching.
2. Description of the Related Art
Generally, a large number of searches on web search engines refer to entities such as people, organizations, and places. However, there may be many different people, organizations, and places that are referred to on web pages, which have the same name, but are, in fact, distinct entities. For example, given the search query "Charles Smith", a typical search engine may retrieve references to 12-15 different people named "Charles Smith" in the first 20 results alone. This is a problem (hereinafter "identified problem") with not just the names of people.
For example, the search query "Asha" retrieves pages relating to an educational charity called Asha, the American Speech and Hearing Association, the singer Asha Bhosle, the American Saddle Horse Association, the American Social Health Association, etc. In any one search, a user is likely searching for information about only one of these entities. To filter the pages referring to only about one particular use of Asha (hereinafter, the term Asha will be used in the generic sense; i.e., to refer to the entity denoted by the query, and the term 'Asha' will refer to the word or phrase), a user may be forced to augment the query with additional terms that are likely to occur on pages referring to that particular use of Asha, which the user is searching for. For example, if a user wants to search for information regarding the singer "Asha Bhosle" but did not know the singer's last name, the user may augment the query with additional terms such as "singer" or "music" or "musician", etc.
Sometimes, one particular entity, which is not the one the user is looking for, dominates the search results. For example, the search "Michael Jordan" mostly retrieves pages about the famous basketball player. This is a problem if the user happens to be searching for information about someone else named Michael Jordan, for example, an individual named "Michael Jordon" who may be a high school teacher in Akron, Ohio. Again, the user is generally forced to contort the query in an attempt to eliminate the unwanted pages. This process not only places an additional burden on the user, but also often results in valid pages being left out of the results.
Taking the example of the search query for Asha, one of the problems of disambiguating different denotations of 'Asha' can be seen as a special case of the conventional word sense disambiguation (WSD) problem which has been previously studied. However, there are some major differences between WSD and the problem identified above, which makes the traditional approaches to WSD inappropriate for the identified problem. WSD has generally dealt with the problem of identifying the word sense of a particular use of a word such as "bank", which might refer to either a financial bank or a river bank. Typically, the problem is that of distinguishing between the two to four possible alternative meanings of a particular word, all of which are a priori known. This is done by using linguistic properties of the word, domain knowledge, or by looking for commonly co-occurring words. Further, from a linguistic and common sense domain knowledge perspective, all of the denotations are equally plausible.
Some conventional approaches look at the problem of the semantically same record (i.e., set of n-tuples), with erroneous syntactic variations (such as an address being written differently) in some of the fields, appearing as different records in the same database (such as the census database). The goal is to correctly link these duplicate records. In this approach, it is determined which field values are actually the same. However, the identified problem is different from this record linkage problem in two important ways. First, in the present context, even if everything two pages say about the Asha on the two pages is the same, it might not follow that the Ashas denoted by the two pages are, in fact, the same. For example, two pages might simply say that the person is called Asha and is a resident of the United States, from which one cannot conclude that they are the same. Second, different pages are likely to have very different kinds of information. One might identify the person based on his/her organizational affiliation and another based on the books he/she has written and, as such, it would be advantageous to still be able to co-identify them, if indeed they are the same.
Conventionally, a number of popular search engines provide a feature for retrieving similar or related pages. These features are aimed at retrieving pages that are overall similar to the page under consideration. Consequently, most of the pages they retrieve might not even refer to the original search query. For example, according to one of the most popular search engines, one of the top search results for the query "Barbara Johnson" is the web page for the Barbara Johnson who previously ran for governor of Massachusetts. Over half of the retrieved pages that are similar to this do not even contain the term "Barbara Johnson". This is to be expected since the similarity is defined just as a function of the page, and not of the user's original query.
This problem is closely related to the much studied Information Retrieval problem of relevance feedback, which typically involves finding documents similar to a given document. As it relates to the identified problem, a precise definition is given of the sense in which two documents are to be considered similar; i.e., they refer to the same Asha. With this definition, one can measure the performance of different methodologies.
However, the conventional approaches have not generally worked well for web page searching and retrieval. Therefore, while the conventional approaches were sufficient for the purpose they were intended for, there remains a need for a novel entity disambiguation technique capable of being used in web page searching and retrieval.

System and method for disambiguating entities in a web page search

International Business Machines Corporation


The present invention provides for improving image clarity through sub-pixel positioning of the image in a grid space based on pixel homogeneity scores. The pixel homogeneity scores indicating the uniformity of state for sub-pixels produced from an over-sampling of the pixels within the grid space. A representation of an image (or at least a portion thereof) is positioned at various sub-pixel locations with in the grid space, and pixel homogeneity scores are calculated for the various locations. Based on a comparison of the pixel homogeneity scores, a position to display the image is chosen such that image rendering is optimized or at least improved.

1. The Field of the Invention
The present invention generally relates to improving the quality of rendering graphical images such as text. More specifically, the present invention relates to improving image rendering through sub-pixel positioning of the image in a grid space based on pixel homogeneity scores.
2. Background and Related Art
Computing technology has transformed the way we work and play. Computing systems now take a wide variety of forms including desktop computers, laptop computers, tablet PC's, personal digital assistance (PDAs), and the like. Even household devices (such as refrigerators, ovens, sewing machines, security systems, and the like) have varying levels of processing capability and thus may be considered computing systems. As time moves forward, processing capabilities maybe incorporated into a number of devices that traditionally did not have such. Accordingly, the diversity of computing systems may likely increase.
Almost all computing systems that interface with human beings use a display to convey information. In many cases, the appeal of the display is considered an important attribute of the computing system. Display of textural information (e.g., Latin-based characters) typically includes processing glyphs that represent characters of a font. A glyph includes control points and instruction for connecting the control points such that an outline of corresponding character can be generated in an arbitrary grid space (e.g., a pixel grid). Often, a character or image will be defined for display at larger size and high resolution. The character can then be mathematically scaled down (or otherwise manipulated) when the character is rendered at smaller sizes and lower resolutions (or as bold, italic, etc.). Thus, a reduced number of descriptions, and potentially one description, for a character (per font) need be stored.
To scale down a character, the location of controlled points can be divided by a scaling factor. For example, to scale a character down by a scaling factor of 10, the coordinates of each control point defining the character (at the higher resolution) can be divided by 10. It may be that control points defining a character for display on a 100×100 grid are to be scaled down for display on a 10×10 grid. Thus, a control point at grid position (50, 30) can be scaled down to a controlled point at grid position (5, 3). Similarly, a control point at grid position (70, 70) can be scaled down to controlled point at grid position (7, 7), etc. According, a smaller outline representing the character may be calculated, and there is a reduced need for storing a number of different sizes of bit-maps for the character.
The small outline can then be analyzed to identify grid locations (e.g., pixels) that are to be turned on and that are to be turned off (a process often referred to as "scan conversion"). One scan conversion algorithm determines if the center of a grid position is in side or outside a resulting scale down outline. When the center of a grid position is inside the scaled down outline the grid position is turned on. On the other hand when the center of a grid position is outside the scaled down outline the grid position in turned off.
Unfortunately, at times, and especially at lower resolution and smaller font sizes, the results of scan conversion produce an unacceptable representation of a character. Unacceptable character representations can result from rounding errors in scaling down process or from the scan conversion process itself. In order to appropriately render smaller images (e.g., letters of small font size often used by handheld devices with limited processing power), an over sampling of the image is preformed. This over-sampling results in sub-pixel positioning of a bit-map image and can be used to greatly improve the appearance of a smaller image. For example, as shown in FIG. 1A the grid space 100 is divided up into a numerous amount of pixels 105 for displaying images such as glyph 115. Each pixel is over-sampled to produce a set of sub-pixels 110 for positioning a representation of the image 105 (in this instance the letter "F"). As shown, the over-sampling allows the lower size font glyph to be more accurately positioned within the grid space 100.
Although the use of sub-pixel positioning on pixel-oriented display devices has made it possible to more appropriately display text of smaller images, there are other problems associated with rendering such smaller objects. For example, diagonal lines, or narrow or curvy linier portions of larger images in can cause jaggies or dropout conditions to occur. As such, in order to more appropriately render smaller images hinting and anti-aliasing techniques have been adapted to improve the smooth appearance of smaller objects. Hinting typically ensures that the letter maintains certain attributes, while anti-aliasing techniques allow the pixels that surround the edges of a line (especially those that do not cover a full pixel) to be changed to varying shades of grey or color in order to blend the sharp edge into the back ground.
FIG. 1A illustrates an example of where anti-aliasing techniques can be used to improve image quality. As shown, the vertical edge 120 of glyph 115 is shown as being partially placed over the column of pixels supporting that vertical edge 120. In such instance, various sub-components of those pixels 105 can be turned on or off, as appropriate in order to more appropriately render the vertical edge 120 of glyph 115. For example, various sub-components of red, green and blue can be used at varying intensities to appropriately render glyph 115. Alternatively, the entire pixel 105 can be partially turned on when such sub-components are not available, or other techniques simply turn the pixel fully on or fully off depending on the percentage or fraction of sub-pixels that would be turned on or off.
Although such anti-aliasing techniques allow for smaller fonts or bit-map images to be more accurately rendered, these techniques typically produce fuzzy or jagged edges. As such, as in the case of FIG. 1A, if a small image or glyph 115 is positioned on the grid space such that several of its edges must rely on anti-aliasing techniques, the smaller images or glyphs 115 can become unacceptable or undeterminable. Accordingly, there exists a need to be able to more appropriately position a glyph in order to ensure a uniformity of sub-pixel state within each pixel.

Using pixel homogeneity to improve the clarity of images


Provided is a destination-prediction apparatus that predicts a destination with increased accuracy than using a conventional technique. The destination-prediction apparatus comprises a candidate-destination selecting unit that selects and orders a plurality of candidate destinations, a drawing processing unit that displays the selected candidate destinations according to the ordering, a rule setting unit that sets a rule that a moving object moves to the candidate destination at a constant frequency during a certain unit period, a unit-period frequency accumulating unit that determines actual frequency at which the moving object has moved to the candidate destination during the unit period, and a actual-frequency judging unit that judges whether or not the actual frequency reaches trip frequency included in the rule. The drawing processing unit displays the candidate destinations, reflecting a result of the judgment that the actual frequency satisfies the rule.

Conventionally, there is a disclosed example of a technique applied to a navigation apparatus to be installed in a vehicle. The navigation apparatus predicts, on the basis of a past trip history of the vehicle, a goal for which the vehicle is heading. The trip history includes start and end points of trips and days and times of the trips (See Patent Reference 1, for example). According to Patent Reference 1, the navigation apparatus searches a past trip history for a record of moving at "20:30, Thursday" when, for example, a driver is traveling in a vehicle at 20:30 on a Thursday. In the case where a search result shows that the vehicle moved to a landmark A three times and a landmark B once at corresponding times and on corresponding days in the past, the landmark A is predicted to be a goal with a high probability of 75%. In the case where there is no record of moving at "20:30, Thursday" in the past, the condition for searching for a history record is eased to, for example, "20:30, weekday" to extract an appropriate record, so that a landmark to be a goal is predicted similarly on the basis of trip frequency. In this example, a "day" of Thursday, is generalized to a larger set (hereinafter referred to as class) of "weekdays". Similarly, the "time" of 20:30 may be categorized into a defined class such as "evening (18:00 to 24:00)" for the purpose of calculating a prediction probability on the basis of frequency using more history records. Using such classes for prediction is effective not only for the case where there is no record to satisfy a condition but also from viewpoint of increasing reliability of a prediction probability, because referring to more data items in a calculation of probability generally increases reliability.
Patent Reference 1: Japanese Unexamined Patent Application Publication No. 2005-156350

Destination-prediction apparatus, destination-prediction method, and navigation apparatus


A facility for facilitating custom radiation treatment planning is described. During a distinguished radiation treatment session for a patient, the facility collects data indicating positioning of a predefined treatment site of the patient relative to a target treatment location throughout the distinguished radiation treatment session. The facility associates the collected positioning data with data describing one or more other aspects of the distinguished radiation treatment session. The facility provides the associated data to a treatment planning facility to determine a treatment plan for future radiation treatment sessions for the patient.

Radiation therapy can be used to treat localized cancer. In a typical application, a radiation delivery system has an ionizing radiation device mounted to a movable gantry. The radiation delivery system controls the motion of the radiation device to direct an ionizing radiation beam to a specific point in space commonly referred to as the "machine isocenter." During radiation therapy, a patient is positioned so that the patient's tumor is located at the machine isocenter throughout treatment.
Radiation is typically delivered to a patient during a radiation therapy session in accordance with a session plan. A session plan typically specifies, for each of one or more "treatment fields," such information as the gantry position, which determines the path that radiation energy will take to the tumor during the treatment field; collimator settings that determine the shape and cross-sectional area of the radiation energy beam; the intensity level of the radiation beam; and a duration that determines for how much time radiation energy will be delivered during the field. Various session plans may include different or additional information, however.
A plan is typically prepared using determinants such as the following: the tumor's mass, volume, shape, orientation, location in the body, and proximity to different organs and other anatomical structures; and information about radiation energy intended to be delivered to the tumor in foregoing radiation therapy sessions, as well as other approaches previously used to treat the tumor. Various plan preparation techniques may use fewer, more, or different determinants, however.
Conventionally, a batch of several session plans are prepared for a number of future sessions in advance of the sessions. In this batch approach to session plan preparation, the individual plans of the batch are often homogeneous, and assume either (1) no relevant changes in the patient's condition during the course of the batch, or (2) projected changes in the patient's condition determined in advance. This approach further typically assumes (1) that radiation has been and will be delivered in accordance with each plan with complete accuracy, or (2) that radiation has been and will be delivered in accordance with each plan at a projected level of accuracy determined in advance.
The batch approach to session plan preparation has the disadvantage that each plan of a batch after the first plan is based upon important assumptions that may in many cases be unwarranted. As a result, individual plans prepared using the batch approach may have various deficiencies, which have the effect of degrading the effectiveness of radiation therapy in treating the tumor.
In view the foregoing, and approach to session plan preparation having a reduced reliance on such important assumptions would have significant utility.

This patent is subject to a terminal disclaimer.

Dynamic/adaptive treatment planning for radiation therapy


A plasmon generator includes a first portion and a second portion that are adjacent in a first direction orthogonal to the direction of travel of light propagating through a core. The second portion includes a front end face located in a medium facing surface of a magnetic head. The core has a concave portion recessed from the top surface of the core. At least part of the first portion is received in the concave portion. The concave portion has a surface including an evanescent light generating portion. The first portion includes a plasmon exciting portion opposed to the evanescent light generating portion. The evanescent light generating portion is inclined relative to a first surface.

1. Field of the Invention
The present invention relates to a near-field light generator for use in thermally-assisted magnetic recording in which a recording medium is irradiated with near-field light to lower the coercivity of the recording medium for data writing, and to a thermally-assisted magnetic recording head including the near-field light generator.
2. Description of the Related Art
Recently, magnetic recording devices such as magnetic disk drives have been improved in recording density, and thin-film magnetic heads and recording media of improved performance have been demanded accordingly. Among the thin-film magnetic heads, a composite thin-film magnetic head has been used widely. The composite thin-film magnetic head has such a structure that a read head unit including a magnetoresistive element (hereinafter, also referred to as MR element) for reading and a write head unit including an induction-type electromagnetic transducer for writing are stacked on a substrate. In a magnetic disk drive, the thin-film magnetic head is mounted on a slider that flies slightly above the surface of a recording medium. The slider has a medium facing surface facing the recording medium.
To increase the recording density of a magnetic recording device, it is effective to make the magnetic fine particles of the recording medium smaller. Making the magnetic fine particles smaller, however, causes the problem that the magnetic fine particles drop in the thermal stability of magnetization. To solve this problem, it is effective to increase the anisotropic energy of the magnetic fine particles. However, increasing the anisotropic energy of the magnetic fine particles leads to an increase in coercivity of the recording medium, and this makes it difficult to perform data writing with existing magnetic heads.
To solve the foregoing problems, there has been proposed a technology so-called thermally-assisted magnetic recording. The technology uses a recording medium having high coercivity. When writing data, a write magnetic field and heat are simultaneously applied to the area of the recording medium where to write data, so that the area rises in temperature and drops in coercivity for data writing. The area where data is written subsequently falls in temperature and rises in coercivity to increase the thermal stability of magnetization. Hereinafter, a magnetic head for use in thermally-assisted magnetic recording will be referred to as a thermally-assisted magnetic recording head.
In thermally-assisted magnetic recording, near-field light is typically used as a means for applying heat to the recording medium. A known method for generating near-field light is to use a plasmon generator, which is a piece of metal that generates near-field light from plasmons excited by irradiation with laser light. The laser light to be used for generating near-field light is typically guided through a waveguide, which is provided in the slider, to the plasmon generator disposed near the medium facing surface of the slider.
The plasmon generator has a front end face located in the medium facing surface. The front end face generates near-field light. Surface plasmons are excited on the plasmon generator and propagate along the surface of the plasmon generator to reach the front end face. As a result, the surface plasmons concentrate at the front end face, and near-field light is generated from the front end face based on the surface plasmons.
U.S. Patent Application Publication No. 2011/0170381 A1 discloses a thermally-assisted magnetic recording head in which a surface of a waveguide and a surface of a metallic structure (plasmon generator) are arranged to face each other with a gap therebetween. In this thermally-assisted magnetic recording head, evanescent light that occurs at the surface of the waveguide based on light propagating through the waveguide is used to excite surface plasmons on the metallic structure, and near-field light is generated based on the excited surface plasmons. Further, U.S. Patent Application Publication No. 2011/0170381 A1 discloses forming a part of the metallic structure from a material different from that of other parts of the metallic structure.
Materials that are typically employed for plasmon generators are metals having high electrical conductivities, such as Au and Ag. However, Au and Ag are relatively soft and have relatively high thermal expansion coefficients. Thus, forming an entire plasmon generator of Au or Ag gives rise to problems as discussed below.
In the process of manufacturing a thermally-assisted magnetic recording head, the medium facing surface is formed by polishing. During polishing, polishing residues of metal materials may grow to cause smears. To remove the smears, the polished surface is slightly etched by, for example, ion beam etching in some cases. If an entire plasmon generator is formed of Au or Ag, which are relatively soft, the polishing and etching mentioned above may cause the front end face of the plasmon generator to be significantly recessed relative to the other parts of the medium facing surface. In such a case, the front end face of the plasmon generator becomes distant from the recording medium, and the heating performance of the plasmon generator is thus degraded.
Part of the energy of light guided to the plasmon generator through the waveguide is transformed into heat in the plasmon generator. Part of the energy of near-field light generated by the plasmon generator is also transformed into heat in the plasmon generator. The plasmon generator thus rises in temperature during the operation of the thermally-assisted magnetic recording head. If the entire plasmon generator is formed of Au or Ag, the rise in temperature of the plasmon generator causes the plasmon generator to expand and significantly protrude toward the recording medium. This in turn may cause a protective film covering the medium facing surface to come into contact with the recording medium and thereby damage the recording medium or be broken. When the protective film is broken, the plasmon generator may be damaged by contact with the recording medium or may be corroded by contact with high temperature air.
Further, if the entire plasmon generator is formed of Au or Ag, the temperature rise of the plasmon generator may result in deformation of the plasmon generator due to aggregation. In addition, such a plasmon generator expands when its temperature rises and then contracts when its temperature drops. When the plasmon generator undergoes such a process, the front end face of the plasmon generator may be significantly recessed relative to the other parts of the medium facing surface. In such a case, the heating performance of the plasmon generator is degraded as mentioned above.
For the various reasons described above, a plasmon generator that is formed entirely of Au or Ag has the drawback of being low in reliability. The drawback becomes more noticeable if the front end face of the plasmon generator is large in area.
U.S. Patent Application Publication No. 2011/0170381 A1 discloses a metallic structure composed of a main body and a layer having a greater hardness than the main body (this layer will hereinafter be referred to as the hard layer). In the metallic structure, the main body is not exposed in the medium facing surface, but the hard layer is exposed in the medium facing surface. In the metallic structure, surface plasmons are generated in the main body. The generated surface plasmons propagate to the hard layer, and near-field light is generated from the vertex of the hard layer.
In the thermally-assisted magnetic recording head disclosed in U.S. Patent Application Publication No. 2011/0170381 A1, the surface of the waveguide that generates evanescent light and the surface of the metallic structure facing the aforementioned surface of the waveguide are both arranged parallel to the direction of travel of the light propagating through the waveguide. This configuration allows only a small amount of the entire light propagating through the waveguide to reach the evanescent light generating surface of the waveguide. It is thus difficult with this configuration to generate much evanescent light and to thereby excite a lot of surface plasmons on the plasmon generator.

Near-field light generator including a waveguide and a plasmon generator


Systems and methods to process packets of information using an on-chip processing system include a memory bank, an interconnect module, a controller, and one or more processing engines. The packets of information include a packet header and a packet payload. The packet header includes one or more operator codes. The transfer of individual packets is guided to a processing engine through the interconnect module and through the controller by operator codes included in the packets.

Information-processing systems that process electronic information commonly use electronic storage to store electronic information, digital processors to process the stored electronic information, and busses, networks, or other logic to connect such electronic storage to such digital processors, for example for the purpose of transferring electronic information. Commonly, the functions of storing electronic information and processing electronic information are performed by different devices and/or systems. Electronic storage may be implemented as an independent device or component, separate from any related but external digital processors. A digital processor may be implemented as an independent device or system, separate from any external electronic storage. The connection between the electronic storage and one or more digital processors may be implemented as an independent module, component, device, or system, separate from related electronic storage and any related digital processors. Information-processing systems commonly distinguish "write" operations from "read" operations, wherein write operations may be used to store information in the electronic storage, and wherein read operations may be used to retrieve the stored information and transfer it to, e.g. the processor. Read and write operations may be associated with a source (which may be referred to as origin) and a destination. For example, for write operations, the electronic storage may be referred to as a destination. For example, for read operations, the electronic storage may be referred to as a source. In information-processing systems having more complicated topologies, hierarchies, and/or architectures, individual read and write operations may selectively be associated with one of multiple sources and/or destinations. In some cases, individual operations may be associated with multiple sources and/or destination. For example, in information-processing systems having one or more busses to connect multiple destinations, one or more appropriate destinations may be distinguished from one or more inappropriate destinations by various means of disambiguation, such as the use of addresses. Based on the address, a read or write operation may be guided to and/or from a particular source and/or destination.


An air bag assembly 10 includes a reaction/coupling structure 12, an air bag subassembly 14 coupled to the reaction coupling structure 12, and an inflator 16 also coupled to the reaction/coupling structure 12. The reaction/coupling structure 12 includes a reaction device 20 and a coupling device 22 which are coupled together in a mated arrangement. The air bag subassembly 14 includes an air bag 24 having a mouth portion 26 which defines a gas inlet opening The inflator 16 is positioned to supply inflation fluid to the air bag 24 through the inlet opening. The mouth portion 26 of the air bag 24 is trapped between the reaction device 20 and the coupling device 22 thereby coupling the air bag subassembly 14 to the reaction/coupling structure 12. The inflator 16 is coupled to the reaction/coupling structure 12 in such a manner that the reaction device 20 and the coupling device 22 are locked in the mated arrangement.

A vehicle air bag assembly commonly includes a reaction device, an air bag coupled to the reaction device, and an inflator also coupled to the reaction device. The air bag includes a mouth portion which defines a gas inlet opening. The inflator is positioned to supply inflation fluid to the gas inlet opening to inflate the air bag. The air bag assembly will usually also include a cover which is coupled to the reaction device and which, together with the reaction device, forms a receptacle for the air bag.
An air bag assembly is generally coupled with a structural part of the vehicle via the reaction device. In the case of a passenger side air bag assembly, for example, the reaction device may be coupled with the support structure for the vehicle instrument panel or dashboard, and the cover may form a part of the instrument panel. When coupled with a vehicle, the air bag assembly operates to deploy the air bag at the onset of a vehicle collision. Specifically, at the onset of a collision, the inflator supplies inflation fluid to the air bag through its gas inlet opening. The cover is designed so that when the air bag begins to inflate, an opening will be created for the expanding air bag. The inflation fluid simultaneously forces the air bag through the opening in the cover and inflates the air bag.
In a typical assembly process, the air bag is coupled to the reaction device with a set of fastening elements (such as bolts or rivets). The inflator is coupled to the reaction device with an additional set of fastening elements. The cover is then coupled to the reaction device using a further set of fastening elements. Generally, the more separate fastening elements incorporated into an air bag assembly, the more complicated will be the assembly technique. For this reason, applicant believes a need remains for an air bag assembly which simplifies assembly techniques, particularly by minimizing the number of separate fastening elements.


The present invention provides a method for erasing floating gate memory devices. Specifically, one embodiment of the present invention discloses a method for erasing an array of non-volatile flash memory cells arranged in a plurality of rows and a plurality of columns. A plurality of word lines are coupled to the plurality of rows. The embodiment of the method begins by applying a positive voltage to odd word lines in the plurality of word lines in a first phase of an erase cycle. The plurality of word lines comprising alternating odd and even word lines. The embodiment continues by applying a negative voltage to even word lines in the plurality of word lines in the first phase of the erase cycle. Then, the embodiment applies the negative voltage to the odd word lines in the plurality of word lines in a second phase of said erase cycle. Thereafter, the embodiment continues by applying the positive voltage to the even word lines in the second phase of the erase cycle.

A flash or block erase memory (flash memory), such as, Electrically Erasable Programmable Read-Only Memory (Flash EEPROM), includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory as a whole are made smaller by eliminating the independent nature of each of the cells. As such, all of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide Semiconductor (MOS) memory cells that are field effect transistors (FETs). Each FET, or flash, memory cell includes a source, drain, and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block. The flash memory cell provides for nonvolatile data storage.
A typical configuration of an array of flash memory cells includes rows and columns of flash memory cells. The array is supported by word lines and bit lines, wherein the word lines are coupled to gates of flash memory cells, and the bit lines are coupled to drains.
In a dual bit flash memory cell, the flash memory cell stores data by holding charge within an oxide-nitride-oxide (ONO) layer. The charge storage element within the ONO layer allows electrons to be stored on either side of the flash memory cell. As a result, the basic memory cell behaves as two independent conventional memory cells. In a typical dual bit flash memory cell, a program operation is done by injecting hot electrons into the ONO layer, and an erase operation is done by injecting hot holes into the ONO layer.
In a floating gate flash memory cell, the flash memory cell stores data by holding charge within the floating gate. In a write operation, charge can be placed on the floating gate through hot electron injection, or Fowler-Nordheim (F-N) tunneling. In addition, F-N tunneling can be typically used for erasing the flash memory cell through the removal of charge on the floating gate.
A common failure in flash memory is a programming failure due to an over-erasure of the flash memory. Prior Art FIG. 1A illustrates the over-erasure in a flash memory array 100A consisting of dual bit floating gate memory cells. For purposes of illustration only, in one case, the cross sectional view of the flash memory array 100A as presented in Prior Art FIG. 1A can be taken along line B–B′ of FIG. 3 in a dual bit case.
During multiple erase and program cycles, overerasure under the sidewall region 110 between a plurality of word lines 130 occurs. That is, over-erasure occurs due to hot hole injection of electrons into the sidewall region 110. For example, in an erase cycle of the conventional art, a negative voltage (e.g., −6 volts) is applied to an entire block of the array, a positive voltage (e.g., +6 volts) is applied to the drains of memory cells in the array, and the corresponding sources are left floating. As shown in Prior Art FIG. 1, the ONO layer 120 is erased during the erase process, as indicated by the darkened layer. This is because the potential of the sidewall region 110 reaches the applied potential on the plurality of word lines 130. As such, even the ONO layer 120 between each of the plurality of word lines 130 beneath the sidewall region 110 is erased.
During a program cycle, an isolated flash memory cell 130A in the array 100 is subjected to voltage to program the floating gate layer under the gate. Typically, a high positive voltage (e.g., +9.5 volts) is applied to the gate through an associated word line, the source is grounded, and a positive voltage (e.g., +5 volts) is applied to the drain through an associated bit line. Because the applied voltage is isolated to each of the gate, source, and drain regions of the programmed flash memory cell 130A, the programmed region, as shown in Prior Art FIG. 1 is isolated to the ONO layer under the gate.
After multiple erase and program cycles, because the programmed portion and erased portion do not overlap between the word lines 130, certain areas under the sidewall region 110 between the plurality of word lines 130 are subjected to multiple erase cycles without any correction from a program cycle. As a result this develops an accumulation of holes between the word lines 130 and under those sidewall regions subjected to multiple erase cycles. This reduces the threshold voltage of the associated flash memory cell and results in overerasure of those flash memory cells.
Correspondingly, prior Art FIG. 1B illustrates the over-erasure in a floating gate flash memory array 100B that consists of floating gate flash memory cells 140, to include flash memory cell 140A. For purposes of illustration only, in one case, the cross sectional view of the flash memory array 100B as presented in Prior Art FIG. 1B can be taken along line B–B′ of FIG. 3 in a floating gate case. Construction of each of the floating gate flash memory cells 140 in the floating gate flash memory array 100B includes, in part, a control gate 190, an ONO layer 180, a floating gate 170, and a tunnel oxide layer 160.
During multiple erase and program cycles, overerasure under the sidewall region 150 between a plurality of word lines that are coupled to the control gates 190 of each of the floating gate flash memory cells 140 occurs. That is, over-erasure occurs due to hole injection into the sidewall region 150.
Unfortunately, having an over-erased cell (floating gate or dual bit flash memory) on the same column line with a programmed cell can cause a failure when the programmed cell is read. The over-erased cell produces a leakage current and causes the entire column to malfunction. In particular, the current that is read from the column should be below a reference current (IRef) that corresponds to a properly configured threshold voltage, when reading a programmed cell. IRef is the erased cell reference current used for comparison.
However, if an over-erased cell is in the same column as that of the programmed cell, the over-erased cell has a threshold voltage that is less than 0 producing a leakage current (ILeak). As such, the total current read from the column will include the current from the programmed memory cell (IProgram) and the leakage current. If the sum of IProgram+ILeakage>IRef, then the total current being read from the column is greater than the reference current, and the programmed cell appears to be erased.
What is needed is a method for erasing flash memory cells that does not induce overerasure in an array of flash memory cells.

Method for pulse erase in dual bit memory devices


A sheet of glass (rear glass) is provided with a radiation conductor and a ground conductor. An electronic circuit unit includes a base plate fixed on the sheet of glass; a frame body which houses a circuit substrate and is screwed on the base plate; and a cover for covering the frame body. The circuit substrate has a component-holding surface and a radio-wave reflective surface at opposite surfaces of the circuit substrate, the radio-wave reflective surface facing the radiation conductor. A section of the frame body proximate the sheet of glass is provided with an engagement portion that fits in an opening of the base plate; and stoppers placed on sections of the base plate that are adjacent to the opening. An amount of insertion of the engagement portion with respect to the opening is set within a thickness of the base plate.

1. Field of the Invention
The present invention relates to an in-vehicle antenna apparatus mounted on a windowpane of a vehicle, such as an automobile, and particularly, to an in-vehicle antenna apparatus in which a conductor layer provided on one surface of a circuit substrate of an electronic circuit unit is opposed to a radiation conductor in order to achieve a higher gain.
2. Description of the Related Art
A conventional in-vehicle antenna apparatus is provided with a radiation conductor disposed on an inner surface of rear glass or front glass of a vehicle, and an electronic circuit unit that includes a pre-amplifying circuit and that is attached to the inner surface, such that the in-vehicle antenna apparatus is capable of, for example, receiving a circularly-polarized wave or a linearly-polarized wave sent from a satellite or a ground-based station. In comparison with other types of antenna apparatuses that are set on the exterior of a vehicle, such as a roof, this type of antenna apparatus is advantageous in having a longer lifespan and a lower possibility of being stolen. Furthermore, in comparison with antenna apparatuses that are set in the vicinity of the inner surface of a windowpane of a vehicle, this type of antenna apparatus is advantageous in providing a good space factor and a wide angle of view.
In an in-vehicle antenna apparatus of this type, the electronic circuit unit attached to the inner surface of a sheet of glass, such as rear glass or front glass, facing the inside of the vehicle includes a housing that houses a circuit substrate provided with, for example, a pre-amplifying circuit. In the electronic circuit unit, a radiation conductor having a predetermined shape and disposed on the sheet of glass is electrically connected with the circuit substrate via appropriate means so that the radiation conductor can receive electricity and load a received signal.
Japanese Unexamined Patent Application Publication No. 6-53722 (p. 2 to p. 3, FIG. 1) discloses an example of such a conventional in-vehicle antenna apparatus in which a conductor segment protrudes from an insulating housing that houses a circuit substrate such that the conductor segment is soldered on an electric feeding point of a radiation conductor. Since one end of the conductor segment is connected to an input section of a pre-amplifying circuit inside the housing, the radiation conductor and the pre-amplifying circuit are electrically connected to each other via the conductor segment, and the electronic circuit unit is fixed on the sheet of glass.
In such a conventional in-vehicle antenna apparatus, however, a radiation pattern is generated not only on one side of the sheet of glass having the radiation conductor but also on the other side of the sheet of glass. This may easily lead to an insufficient gain in the desired direction. In order to solve such a problem, a conductor layer functioning as a radio-wave reflective surface may be disposed in the interior of the vehicle at a position facing the radiation conductor. In that case, however, a high gain cannot be achieved unless the distance between the radiation conductor and the conductor layer is set in a highly accurate manner.
Furthermore, in this example of a conventional in-vehicle antenna apparatus, the electronic circuit unit, which is an integrated unit, is fixed to the sheet of glass by, for example, soldering. This is problematic in view of the fact that when the circuit substrate is to be inspected or replaced with a new one, it is necessary to perform complicated processes, such as demounting the electronic circuit unit from the sheet of glass and remounting the electronic circuit unit back to the sheet of glass, and thus makes the maintenance difficult.


Systems and methods for an identity management router to allow application clients/servers to communicate via an identity management protocol to facilitate communication of identity management artifacts with a simplified topology. Specifically, embodiments of an IM router may adhere to various data protection requirements, including, but not limited to, local data protection regulations, when routing identity management information. The identity management router is location aware and applies data compliance policies for areas of data compliance to selectively route or not route identity management data based on location.

Many enterprises are turning to cloud-based applications to provide geographically distributed users using a variety of devices with access to the applications and data of the enterprise. While cloud-based applications provide the convenience of wide accessibility, this accessibility leads to a number of security concerns, not the least of which is compliance with data protection compliance. Large enterprises are often made up of geographically dispersed organizations and sub-organizations and the data of an enterprise may be subject to various data protection regulations and other data protection requirements based on where the data is maintained, where the data is used, and/or the content of the data. For example, identity management data about citizens of the European Union (EU) is subject to the General Data Protection Regulations (GDPR) of the EU and may also be subject to additional regulation when the data is stored or used outside of the EU. Whereas identity management data about non-EU citizens used and stored outside of the EU may be free from the GDPR.
Identity Management (IM), also known as Identity and Access Management (IAM) or Identity Governance (IG), is the field of computer security concerned with the enablement and enforcement of policies and measures which allow and ensure that the right individuals access the right resources at the right times and for the right reasons. It addresses the need to ensure appropriate access to resources across increasingly heterogeneous technology environments and to meet increasingly rigorous compliance requirements. Escalating security and privacy concerns are driving governance, access risk management, and compliance to the forefront of identity management.
A number of IM protocols (also referred to IAM protocols) designed specifically for the transfer of identity management data have been developed. The SCIM (System for Cross-Domain Identity Management) protocol specified by Internet Engineering Task Force (IETF), for example, is an HTTP-based protocol that makes managing identities in multi-domain scenarios easier to support via a standardized service application-level protocol. The SCIM specification provides an open API for managing identity management data.
In current SCIM technologies, SCIM providers and SCIM consumers communicate point-to-point. The SCIM protocol does not encapsulate filtering of identity management data based on a per user basis or per the user's current location. This combined with the point-to-point nature of SCIM makes it challenging to manage and filter personal information (PI) data to satisfy local data protection requirements and ensure compliance with data protection regulations, such as the GDPR. Moreover, the point-to-point nature of current SCIM technologies results in complicated topologies when more than two SCIM endpoints are used to share information. These topologies can be difficult to manage. For example, because security is based on access rights to the SCIM endpoint (if available), the point-to-point nature of SCIM leads to complicated access rights which have to be re-engineered for each endpoint added to the topology.
Other aspects of a network environment may also limit the scalability of SCIM technologies. For example, if an endpoint is behind a firewall and needs access to other endpoints outside of the firewall, the firewall must be configured to allow the endpoint to connect with the other endpoints. In a point-to-point topology, this may require individual rules for each endpoint. As new endpoints are added, the firewall (and possibly other aspect's an enterprise network environment) may have to be reconfigured to allow connection to those endpoints.


A high frequency signal generator using a superconducting quantum interference device is disclosed including: a magnetic signal generator for supplying a low frequency magnetic signal to a superconducting quantum interference device; a first filter for selectively supplying only the magnetic signal to the superconducting quantum interference device, and preventing a high frequency signal generated from the superconducting quantum interference device from flowing to the magnetic signal generator; the superconducting quantum interference device for frequency-multiplying the magnetic signal generated from the first filter to the high frequency signal of a sinusoidal wave according to the frequency, waveform and amplitude of the magnetic signal; a second filter for preventing the magnetic signal generated from the magnetic signal generator from flowing to a high frequency guide and antenna, and selectively supplying only the high frequency signal generated from the superconducting quantum interference device to the high frequency guide and antenna; and the high frequency guide and antenna for transmitting the high frequency signal supplied through the second filter to the exterior.

1. Field of the Invention
The present invention relates to high frequency signal generators and, more particularly, to a high frequency signal generator for frequency-multiplying a low frequency signal to a high frequency signal by using a magnetic-to-voltage multiplex characteristic of a superconducting quantum interference device.
2. Discussion of Related Art
Generally, as an apparatus for generating a high frequency wave such as a millimeter wave, a resonator having a variety of forms is connected to an active element such as a Gunn diode or a GaAs FET (field effect transistor) to generate a desired resonant frequency signal. The configuration and operation of such a high frequency signal generator will be described with reference to FIGS. 1, 2, 3A and 3B.
Referring now to FIG. 1, a resonant frequency is generated using a resonator 12 and an amplifier 11 consisting of FETs. Among signals of various frequency components generated from the amplifier 11, only a signal of a predetermined band passing the resonator 12 is continuously generated as a high frequency signal from an output terminal OUT through positive feedback.
Referring to FIG. 2, a Gunn diode 21 is used to generate the high frequency signal. Only a corresponding resonant frequency component generated from a resonator 22 among signals generated from the Gunn diode 21 is supplied to the exterior through an output terminal OUT.
FIG. 3A shows the operating principle of a high frequency signal generator using a superconducting junction. An AC effect is used indicating that if a constant voltage V is applied to a Josephson junction 30, a signal of a frequency component proportional thereto is generated. This can be. expressed by the following equation: ##EQU1## where Ic: superconducting critical current
.PHI.o: magnetic quantum=h/2e=2.0679.times.10.sup.-15 T-m.sup.2 PA1 e: electron charge=1.6.times.10.sup.-19 C PA1 h: Planck's constant=6.6262.times.10.sup.-34 Js PA1 V: DC voltage across Josephson junction, PA1 I: AC current flowing into Josephson junction, PA1 .phi.(o): constant phase, and PA1 f.sub.j : Josephson oscillation frequency by DC voltage.
FIG. 3B shows one example of a Josephson junction array using the above principle. If constant currents flow through a first high frequency choke coil 31A, bias lines 32, Josephson junctions 33 and a second high frequency chock coil 31B, a high frequency signal which varies linearly according to a voltage across the Josephson junction 33 is generated. If only one of the Josephson junctions 33 is used, since a power is weak, the above array structure is utilized to raise the output power.
However, the high frequency signal generator using the FET or the Gunn diode is difficult in actuality to generate a very high frequency such as a millimeter wave. Moreover, the high frequency signal generator using the AC effect of the superconducting Josephson junction also has difficulty in forming the Josephson junction under the conditions of high temperature superconductivity operated at a nitrogen temperature.

High frequency signal generator using superconducting quantum interference device


An active probe card having integral test circuitry directly attached to the probe card. The probe card includes a circuit board wherein the test circuitry is mounted on the circuit board. In an alternate embodiment, the probe card also includes an on-board signal selection device. The test circuitry applies test signals through probe pins to integrated circuit input pads and samples the test signal responses at integrated circuit output pads. The orientation of the test circuitry attached to the each pin, i.e., input or output, is field programmable. The test circuitry may use boundary scan testing methodology. The active probe card's test circuitry may implement the test methodology of IEEE standard 1149.1 or analog test circuitry to determine the ac and dc parametric characteristics of the integrated circuit. The active probe card may include terminals to which Automatic Test Equipment (ATE) can be attached.

Current testing of high density integrated circuits is accomplished by large, very expensive test apparatus. As is currently well known in the art, integrated circuits are evaluated by connecting the peripherally arranged input and output pads or traces of the integrated circuit to the test set via a probe card.
Typically, probe cards consist essentially of a circular or rectangular printed circuit board having a centrally located circular opening which provides access to the integrated circuit to be tested, one or more concentric rings of spaced conductive pads on the bottom side of the board surrounding the opening, and connector terminals connected to the conductive pads via conductive traces. A radial array of conductive probes, which are positioned to engage the traces of the integrated circuit under test, are attached at one end to the conductive pads and the distal end extends into the opening.
Generally, the probe pins are pressed against the pads to establish electrical contact. In some instances, the pins may be constructed to include mechanical switches, commonly referred to as edge sensors, which become open when probe pin contact of sufficient force to ensure conduction is established The open state informs the test system that the probe card is ready to test the integrated circuit.
Typically, the probe card is attached to the test instrumentation via a long cable. For high speed systems, the impedances within the test arrangement must be accurately matched and the signal time delays accounted for in order to perform accurate testing. A time domain reflectometer (TDR) is typically used to characterize the test system prior to testing The measured system anomalies can be removed from the recorded test data by extensive signal processing once the data has been recorded or compensation and adjustment can be applied while the data is being collected. In either case, having the test apparatus, i.e., the test signal drive circuits and the test signal response sampling circuits, located a distance from the device under test is undesirable.
Additionally, test circuitry used to evaluate integrated circuits must be easily configurable at the user's firm to meet the specific needs of the device under test. Thus, the test signal drive circuits and the test signal response sampling circuits which are connected to the probes via the long cable must be oriented to match the specific nature of integrated circuit terminal under tested. In other words, the integrated circuits input circuits must be aligned with a test probe which is connected to a test signal drive circuit and the output circuits must be aligned with the test signal sampling circuits.
In an effort to standardize test procedures concerning on-board testing of integrated circuits, the Institute of Electrical and Electronic Engineers (IEEE) promulgated the IEEE Standard Test Access Port and Boundary-Scan Architecture, as described in the document IEEE Std. 1149.1, and incorporated herein by reference. The standard was developed by the Joint Test Action Group (JTAG) and has become known in the integrated circuit industry as the JTAG standard. This standard is adaptable to provide versatile test apparatus which can be configured by the user. An integrated circuit adapter as disclosed in U.S. patent application Ser. No. 07/650,692, entitled "Integrated Circuit Test Adapter" now U.S. Pat. No. 5,096,266 teaches apparatus which configures the JTAG boundary-scan test circuitry to fulfill the current needs of the device under test. This application in herein incorporated by reference.
The specified technique enables integrated circuits to be tested using boundary-scan methodology after the integrated circuits have been permanently installed on a circuit board. However, the JTAG standard circuitry can be adapted to be incorporated into a probe card, creating an active probe card.
The present invention is an active probe card having boundary-scan test circuitry attached directly to the probe pins. In this arrangement, the test circuitry is not separated from the device under test. Therefore, costly time delay and impedance mismatch compensation circuitry is eliminated from the test arrangement.
An objective of the present invention is to enable the testing to be controlled by a workstation or personal computer. Boundary-scan test techniques are especially amenable to control by workstations and personal computers.
Another objective of the present invention is to provide a versatile probe card which can have the test pin orientations, i.e., input or output, programmed in the field to match a specific device under test.
Another object of the present invention is to provide a probe card which includes boundary-scan test circuitry, but also can be operated in conjunction with Automatic Test Equipment (ATE). Thus, a probe card mode of operation which makes the boundary scan circuitry invisible to other test circuitry is necessary.


The augments, systems and methods for supporting acetabular implants described herein can include an augment (100) for supporting an acetabular shell (90) having a first portion (136) of a locking mechanism. The system can also include a shell having a second portion of a locking mechanism (96). The first portion of the locking mechanism and the second portion of the locking mechanism can be adapted to move relative to one another from an unlocked state to a locked state to fixedly couple the augment to the shell. In some examples, the augment can be contourable to match the shape of a bone.

A total hip arthroplasty (THA) procedure can be performed to repair a diseased or damaged hip joint and replace it with a hip prosthesis. Sometimes, as with any other mechanical device, a total hip replacement can be subject to various forms of mechanical or biological issues. When issues occur, a reoperation of the hip prosthesis can be necessary to resolve the issues. Such a reoperation of a THA is called a revision THA. This is usually done several years after the original implantation and is more common in patients who had the initial THA performed at a young age and the patient chose to have a very active physical lifestyle.
One of the challenges of a THA, including a revision THA is how to securely implant the hip prosthesis. In particular, it can be challenging to securely implant and support an acetabular shell of the prosthesis into the remaining bone of the patient, especially in the presence of poor bone quality or bone loss. In addition, it can be challenging when using an augment to support an acetabular shell, to have a secure coupling of the augment to the acetabular shell.

Augments, systems and methods for acetabular implants


A contact connection adapter for producing an intermittent electrical contact between two plugs has a main body and two socket-like receptacles placed thereon for the plugs. The cross-sections of the receptacle receiving the plugs to be connected intersect peripherally in this case in such a way that the plugs press against one another at their lateral contact faces and produce an electrical contact.

1. Field of the Invention
The present invention relates to a contact connection adapter for producing an intermittent electrical contact between a first plug, particularly a standard terminal plug of a cardiac pacemaker electrode, and at least one second plug, particularly a typical laboratory plug for intermittent connection of the electrode to a stimulus threshold analyzer.
2. Background Art
The background of the present invention is the procedure during implantation of a cardiac pacemaker, defibrillator, or similar cardiological device, whose electrophysiological stimulation pulses are delivered by appropriate electrodes positioned in or on the heart. During the implantation procedure, the electrodes are typically advanced in a controlled way via the vascular system of the patient with the aid of a mandrel inserted into the electrode. This mandrel runs coaxially through the proximal terminal plug of the electrode. This plug is typically a plug standardized for medical application, designated IS-1/IS-4/DF-1, etc., for example, which may be implemented as unipolar or bipolar.
After an electrode is seated, its seat and stimulation pulse delivery behavior must be analyzed, for which a stimulus threshold analyzer is responsible. This device simulates the cardiac pacemaker otherwise coupled via the electrode terminal plug and must be electrically connected to the electrode plug for this purpose. However, this may not be performed by simply plugging the plug into the device, since the electrode plug must be kept sterile, and, in addition, the mandrel is not to be pulled out of the electrode yet for the present test, since repositioning of the electrode with the aid of the control mandrel may possibly be necessary. Since the mandrel end is guided through the plug, the plug may not be inserted into a device socket in any case.
DE 198 10 262 A1 (=U.S. Pat. No. 6,708,067 B1) discloses a test cable assembly, in which, on a cardboard-like support, a terminal pole of the electrode plug may be fixed on a clamp terminal attached to the support. The second pole, typically an electrode terminal ring, is contacted via an alligator clip, which simultaneously produces a further mechanical connection between the paperboard-like support and the electrode plug. Clamp terminal and alligator clip are electrically connected via thin litz wires, which may be plugged into a fitting socket of the test unit via a corresponding plug device.
This previously known achievement of the object has a provisional character, and, in addition, multiple steps are necessary for the production of the adapter, namely cutting the paperboard support to length and wiring and attaching the terminal clamp and alligator clip. Handling this test adapter is cumbersome and the contact provided, particularly to the alligator clip, is in need of improvement in its reliability.

Contact connection adapter for producing an intermittent electrical contact between two plugs


A method of fabricating a semiconductor device includes the steps of forming a plurality of gate electrodes on a first region and a second region of a substrate, the plurality of gate electrodes having cap insulating layers thereon; forming source and drain regions in the first region and the second region, the source and drain regions of the second region having an LDD structure; forming an insulating layer on the substrate including the plurality of gate electrodes; forming contact holes in the insulating layer to simultaneously expose the source and the drain regions of the first region and the cap insulating layer on the gate electrodes in the second region; selectively removing the cap insulating layer on the gate electrodes in the second region; and forming a metal line in the contact holes and on the insulating layer.

1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of fabricating a highly integrated semiconductor device with improved reliability.
2. Discussion of the Related Art
Generally, as the packing density of an integrated circuit increases, the device size decreases and its metal line becomes finer and multilevel. Accordingly, the step coverage on a contact hole, a via hole or an uneven surface of the device becomes more important. To solve this problem in a dynamic random access memory (DRAM), a self aligned contact hole was proposed. This contact hole is formed in such a manner that double insulating layers are formed, and its lower insulating layer is not etched when a hole is formed in its upper insulating layer.
The conventional method of fabricating a semiconductor device employing the self aligned contact hole is disclosed in U.S. Pat. No. 5,384,287 and will be explained below with reference to FIGS. 1A to 1G. As shown in FIG. 1A, on a semiconductor substrate 1 including a cell region and a periphery region, a field oxide layer 2 for isolating devices from each other is formed on a field region of the semiconductor substrate 1. An active region is defined by the field oxide layer 2, i.e., where the field oxide layer 2 is not formed. Thereafter, a first insulating layer 3, a polysilicon layer 4 and a second insulating layer 5 are sequentially formed on the overall surface of the substrate 1.
Referring to FIG. 1B, a first photoresist layer (not shown) is formed on the second insulating layer 5, and selectively exposed and developed to form a first photoresist pattern (not shown). Then, the second insulating layer 5, the polysilicon layer 4 and the first insulating layer 3 are selectively removed using the first photoresist pattern as a mask, to thereby form gate electrodes. Here, the first insulating layer 3 is used as a gate insulating layer, and the second insulating layer is used as a cap gate insulating layer. The second insulating layer may be formed of nitride. Thereafter, impurity ions are implanted in a lower concentration into the substrate 1 using the gate electrodes as a mask, to thereby form a lightly doped impurity region. A third insulating layer is formed on the substrate 1 including the gate electrodes and etched back, to thereby form gate sidewalls 6 on both sides of the gate electrodes. Then, impurity ions are implanted in a higher concentration into the substrate 1 using the gate electrodes, the sidewalls 6 and a second photoresist pattern (not shown) which selectively masks the cell region as a mask, to thereby form source and drain impurity regions 7 having a lightly doped drain (LDD) structure only on the periphery region. The second and third insulating layers are to serve as a lower insulating layer when a self aligned contact hole is formed in the following process.
Referring to FIG. 1C, a fourth insulating layer 9 is formed on the overall surface of the substrate, and a third photoresist layer is formed thereon. Here, the fourth insulating layer 9 serving as an interlevel insulating layer may be formed of an oxide.
Referring to FIG. 1D, the third photoresist layer is selectively exposed and developed to thereby form a third photoresist pattern 10 defining a contact hole region. This contact hole region is defined only in the periphery region.
Referring to FIG. 1E, the fourth insulating layer 9 and the second insulating layer 5 are selectively etched using the third photoresist pattern 10 as a mask. By doing so, contact holes 11 and 11a are formed to respectively expose a predetermined portion of the substrate 1, and the surface of the gate electrodes.
Here, the actual areas of the contact holes formed through the etching of the fourth insulating layer 9 are smaller than the areas defined by the third photoresist pattern 10. This is because the sidewall 6 formed on the side of the gate electrode reduces the area of the contact hole.
Referring to FIG. 1F, a fourth photoresist layer 10a is formed on the overall surface of the substrate 1 including the fourth insulating layer 9, and only a portion of the fourth photoresist layer 10a placed on the cell region is selectively exposed and developed, thereby forming a fourth photoresist pattern 10a.
Referring to FIG. 1G, the fourth insulating layer 9 is selectively etched using the fourth photoresist pattern 10a as a mask, to thereby expose a predetermined portion of the substrate. By doing so, contact holes are formed. Thereafter, a metal layer is formed on the overall surface of the substrate including the contact holes and selectively etched through photolithography, to thereby form a metal line 12.
The aforementioned conventional method of fabricating a semiconductor device has the following problems. First, the surface of the substrate in the periphery region is overetched when the cap gate insulating layer, i.e., the second insulating layer, is etched because the cap gate insulating layer and the interlevel insulating layer (i.e., the fourth insulating layer) have etch selectivity to each other. This leads to poor quality of the contact hole pattern on the source and drain regions. As a result, the characteristic of the device is deteriorated. In addition, since the contact holes in the periphery region and the cell region are patterned using separate photoresist patterns, it is difficult to have accurate alignment.

Method of fabricating semiconductor device


In an image reader, an original is irradiated with a light source. A reading of the original in a main scan direction is performed for each line by a line sensor. An optical system is movable relative to the original in a subsidiary scan direction of the original. The relative movement of the original and the optical system in the subsidiary scan direction is caused by a driving section. A line clamp of a DC level of an output signal of the line sensor is performed by a line clamp section. The timing at which the line clamp is to be performed and the presence/absence of the line clamp are controlled by a control section.

1. Field of the Invention
The present invention relates to an image reader for a scanner, copier or the like provided with a reading position alignment function.
2. Description of the Related Art
In recent years, a flat bed type image scanner device capable of inputting an image in a simple manner has come into wide use. The coordination of the image scanner device and a host device during transfer exists as a problem associated with the improvement in the precision of image reading and the improvement in the image reading speed. Especially, in the case where the image reading speed of the image scanner device is higher than the data transfer speed of the host device, it is necessary to coordinate these devices by use of any means.
In such a case, storing image data of the image scanner device into a buffer memory, stopping an image reading operation in progress, and so forth are measures that are generally taken. The former measure of storing the image data into the buffer memory and then making the transmission corresponding to the processing speed of the host device is effective and easy. However, the amount of image data to be handled has been increased in association with the improvement in resolution and the treatment of a color image and hence the provision of a buffer memory corresponding to one image results in a high cost. As a result, it cannot be said that this measure is expedient.
The latter measure is a more simple and economical measure and involves of temporarily stopping the reading operation. In a device having such a temporary stop function, in order to avoid a deviation in the reading position in the case where a rereading operation is performed after the temporary stop of a reading operation, a horizontal synchronizing signal is resynchronized so as to always keep the storage time of a line sensor (mentioned just below) constant. Thereby, double reading of an image or a miss in reading is prevented.
The line sensor is composed of a light receiving portion including a multiplicity of aligned light receiving elements for photoelectric conversion, a transfer portion including shift registers provided corresponding to the respective light receiving elements, and a gate portion provided between the light receiving portion and the transfer portion. Each light receiving element of the light receiving portion generates electric charges corresponding to a received light amount and the generated charges are stored thereinto in accordance with the lapse of time. At a point of time when the gate is opened by a shift pulse signal after the lapse of a predetermined charge storage time, the stored charges are all transported to the corresponding shift register. The charges transported to each shift register of the transfer portion are transferred in accordance with transfer clocks successively applied to the shift registers and are outputted as a serial signal from an output terminal.
FIG. 9A is a timing chart showing a shift pulse signal, FIG. 9B as a timing chart showing a transfer clock for each pixel, FIG. 9C is a timing chart showing a line sensor output signal, FIG. 9D is a timing chart showing a sample pulse, and FIG. 9E is a timing chart showing an output signal (or sample hold output signal) c of the line sensor. The line sensor output signal shown in FIG. 9C includes a reset pulse signal a, a field through signal b and the output signal c. Also, the line sensor has a sample and hold circuit and a line clamp circuit for performing a line clamp by the field through signal b. As shown in FIG. 9E, the output signal c of the line sensor has a light-shielded output signal and an effective pixel signal for each line. The light-shielded output signal is a signal indicative of a dark output level of the line sensor and is used as an offset voltage in the case where a line clamp is performed for each line. In general, the signal processing of the output signal c of the line sensor as an analog signal is such that the output signal c of the line sensor after amplified in its AC level is DC-clamped with the level of the light-shielded output signal taken as an offset level (that is, the level of the light-shielded output signal is clamped to a fixed DC level), and then A/D conversion is performed.
Next, FIGS. 10A to 10C will be used to explain a line clamp pulse defining timing at which the above-mentioned DC clamp is performed. FIG. 10A is a timing chart showing a horizontal synchronizing signal, FIG. 10B is a timing chart showing an inverted version of the output signal c of the line sensor, and FIG. 10C is a timing chart showing a line clamp pulse. As shown in FIGS. 10A to 10C, the line clamp pulse is generated at the same period as the horizontal synchronizing signal (equivalent to the shift pulse signal shown in FIG. 9A) and at a timing at which the light-shielded output signal of the line sensor is outputted.
As a responsibility at the time of charging and discharging of an offset voltage for a coupling condenser in the above-mentioned DC clamp, it is preferable that the charging and discharging are completed within the duration of one line clamp pulse. As a storage time and a transfer clock period are shortened due to the improvement of the reading speed, the completion of the response within a light-shielded output signal generation time requires a high-speed clamp buffer. However, even if the response is not completed within the light-shielded output signal generation time of the line sensor corresponding to one line, the completion of the response in a warm-up period after the turn-on of a power supply suffices to provide a function as the offset control since the potential of the coupling condenser after that is little.
This will now be explained using FIGS. 11A to 11F. FIG. 11A is a timing chart showing a horizontal synchronizing signal, FIG. 11B is a timing chart showing an output signal c of the line sensor, FIG. 11C is a timing chart showing an inverted version of the output signal c of the line sensor, FIG. 11D is a timing chart showing a line clamp pulse, FIG. 11E is a timing chart showing a response waveform of the output signal c of the line sensor in a warm-up period, and FIG. 11F is a timing chart showing the warm-up period. Even if about seven lines are taken to obtain a target DC level in the line clamp, as shown in FIG. 11E, the response in the case of a storage time of 3 msec per one line can be completed if there is a standby time of about 3.times.7=21 msec. If the response is once completed, there is little a change after that and hence a convergence into the tolerance of the target DC level is possible by the line clamp for every line.
However, when a buffer over-run is generated in the course of the reading of an image, a different situation may be encountered. This will be explained using FIGS. 12A to 12E. FIG. 12A is a timing chart showing a horizontal synchronizing signal, FIG. 12B is a timing chart showing a line clamp pulse, FIG. 12C is a timing chart showing an inversely amplified output signal of the line sensor, FIG. 12D is a timing chart showing an ideal response waveform in the line clamp, and FIG. 12E is a timing chart showing an actual response waveform in the line clamp. When the horizontal synchronizing signal is resynchronized due to the generation of a buffer over-run in the course of the reading of an image (see a resynchronizing point T1 in FIG. 12A associated with the restart of reading), the line sensor encounters the case where the period of the shift pulse is shorter than the time in which image data corresponding to one line is transferred, that is, a time equal to (the transfer time per one pixel).times.(the number of pixels). In this case, image data in the preceding time remaining untransferred is outputted in a form added to image data of the next line newly stored, as shown in FIG. 12C. As a result, there may be the case where the DC level changes greatly at the timing of DC clamping, thereby making it impossible to make a response to a normal offset not later than an effective line for rereading shown in FIG. 12E (or effective image data for rereading). For example, when the light-shielded output signal generation time is 10 .mu.sec for a clamp charging/discharging time constant of 10 .mu.sec, a response (in the case where it is regarded as a transient response of a primary system) is on the order of about 63% (=1-exp(-10 .mu.sec/10 .mu.sec)) and hence an offset level at the time of buffer over-run becomes larger than a normal level (or the coupling condenser for clamp is excessively charged) so that the level of the line sensor output signal is apparently lowered. This means that each time an image rereading operation is performed, the rendering of gradation corresponding to several lines is deteriorated so that lateral stripes are generated.
In the conventional approach for solving such a problem, the speed-up of a clamp buffer is contemplated so that the response to the DC offset level is completed within the duration of one line clamp pulse. For example, as the speed of the system is increased, in order to obtain a response equal to or higher than 99% in the case of a light-shielded output signal generation time of 10 .mu.sec, such a clamp buffer needs to have a charging/discharging time constant of 2 .mu.sec which is equal to one fifth of 10 .mu.sec. In order to ensure the charging/discharging time constant of 2 .mu.sec, the ON resistance of an analog switching is 20 .OMEGA. in the case where a 0.1 .mu.F coupling condenser is used. In the case where an ideal response as shown in FIG. 12D is not attained, the conventional approach includes a method which uses the fact that the response is nearly completed after, for example, five lines, that is, a method in which the timing of resynchronization of the horizontal synchronizing signal is set to five lines before the effective line for rereading and image data is made effective from image data read after the reading of image data corresponding to the five lines.
However, in the case where the speed of the line clamp response is increased by use of the high-speed clamp buffer, as mentioned above, there is a problem that in order to increase the speed of the line clamp charging/discharging response of the DC level, a clamp buffer involving a large amount of current flowing therethrough is needed, thereby increasing power consumption. Also, there is a problem in that the increase of noise components attendant upon variations in the power supply voltage caused the large amount of current deteriorates the S/N ratio of a read image.
In the above-mentioned method in which the horizontal synchronizing signal is resynchronized several lines before the point of time of reading restart, the adaptation of the moving speed of a carriage to a reading speed and the resynchronization of the horizontal synchronizing signal are made prior to the reading restart point of time and image data is made effective from image data read after reaching the actual reading restart point of time after several lines. Therefore, this method has a problem in that the moving amount of the carriage attendant upon the rereading operation becomes large.
Under the above circumstances, one of the requirements on the image reader associated with the resynchronization of a horizontal synchronizing signal is that even if the storage time of a line sensor output signal becomes shorter than the transfer time so that the level of the light-shielded output signal becomes abnormal, a disturbance of the image is not generated. Also, it is required that there be no need to cause a high-speed response of the clamp buffer. Further, it is required that even in the case where a rereading operation is performed, the positional deviation of the joint of images is not generated. Furthermore, it is required that the operation of a carriage until the restart of reading is minimized.

Matsushita Electric Industrial Co., Ltd.


A system for detecting if a refrigerant in an HVACR system is contaminated. The system includes a detector that detectes a property of a refrigerant gas in a vapor space and compares the detected property with a reference property for uncontaminated refrigerant gas. The detector determines that a contaminant is present in the refrigerant gas if the detected property is different from the reference property. The property detected by the dectector can be either a speed of sound through the refrigerant gas or a thermal conductivity of the refrigerant gas. Also disclosed is a method for detecting contamination of refrigerant gas in a HVACR system that includes detecting, by a detector, a property of refrigerant gas in a vapor space of the HVACR system.

HVACR systems generally use a refrigerant for cooling, heating or dehumidifying a heat transfer medium. A refrigerant for an HVACR system includes, but are not limited to, HCFC, HFC, HCFO or HFO refrigerants or blends of these refrigerants. When the refrigerant is contaminated or counterfeited with material other than the refrigerant to be used for the HVACR system, the HVACR system will fail to operate adequately. Even worse, the HVACR system could be susceptible to damage or explosion if the contaminant or counterfeiting refrigerant, for example, methyl chloride (R-40), has a high toxicity or flammability potential.

System and method for detecting refrigerant contamination in an HVACR system


An application-specific rf optoelectronic integrated circuit having a generic chip member and a defining substrate in communication with at least one generic chip member. The generic chip member contains passive building block components that are independent from each other and being connected by paths external to the generic chip member. The external connection paths are defined by a defining substrate member having passive components for providing optical and electrical interconnection between selected building block components on the generic chip member to define the specific function of the integrated circuit. It is possible to use the same design of the generic chip for several applications merely by altering the interconnect paths on a defining substrate.

The present invention relates generally to integrated optoelectronic circuit devices and integrated microwave devices and more particularly to a two-part optoelectronic circuit.
Optoelectronics pertains to the interaction of electronic processes with optical processes. This interaction is typically associated with energy conversion between electrical signals and optical signals. Optoelectronic devices, such as lasers, photodetectors, optical modulators, and optical switches, are examples of devices within which this interaction takes place.
Integration of optoelectronic/microwave modules has typically followed two paths, hybrid and monolithic. The hybrid integration connects discrete devices with electrical interconnects. Many individual devices are mounted separately on a carrier. Interconnections between the devices are typically accomplished through bond wires or metal paths formed on the carrier substrate. This approach has high flexibility since the devices are selected and interconnected according to the needs of a given application. However, this approach generally results in large circuit size and high parasitics relative to monolithic circuits. The advantage is that semiconductor materials and fabrication processes can be independently selected to enhance the performance of each device.
The hybrid approach is well suited for constructing prototypes. Production can be costly if the circuit contains many devices and interconnections. Additionally, the many separate devices must be tested and mounted individually.
Monolithic integration places all active and passive components on the same substrate. In addition to reducing the overall circuit size, this process reduces parasitic inductances and capacitances because it shortens the length of circuit interconnect structures. Monolithic circuits are typically formed with compound semiconductor families, for example, gallium aluminum arsenide (GaAlAs) and indium phosphide (InP), that inherently facilitate the realization of high resistivity substrates which reduce microwave losses and crosstalk in electrical interconnects.
The monolithic integration approach is particularly suited for high volume applications. Since many circuit chips can be obtained from a single wafer and several wafers can be processed in a given fabrication run, the cost of a fabrication run is shared among the many units produced. However, each integrated circuit is designed for a specific purpose. Therefore, different applications must be served by designing and fabricating entirely new chips. The tooling cost associated with each new application is high and may not be justifiable when small volumes are needed.
The present invention facilitates an application-specific rf-optoelectronic circuit by combining at least one generic chip, having common building-block components, with a defining substrate, having application-specific circuit parts and patterns. Thus, the same generic chip can be used in many different applications, and the defining substrate is specific to each application.
The generic chip contains building block components that perform functions such as, but not limited to, optical detection and generation, optical modulation, electrical switching and latching, and electrical amplification. The generic chip can be used in any application due to the fact that paths external to the generic chip connect the building block circuit parts on the generic chip.
The defining substrate consists of passive electronic and microwave components such as, but not limited to, capacitors, inductors, resistors and transmission line elements. These passive components provide electrical and optical interconnection between selected building block components on the generic chip and define the specific function of the combined chip/substrate circuit.
As an example, the components on the defining substrate can determine the gain, frequency response, input/output impedances, logic function, and optical interference according to the needs of a specific application. The defining substrate determines the overall function, so the same generic chip can be used in combination with different versions of defining substrates to perform a variety of application-specific functions.
It is an advantage of the present invention that prototype and production optoelectronic and rf circuits can be rapidly designed and fabricated. Another advantage is the reduced cost associated with using the same generic chip in many different applications. Yet another advantage is the flexibility to meet application specific needs simply by fabricating a defining substrate. Because the defining substrate contains only passive components, its fabrication is fairly quick and easy.
It is an object of the present invention to provide an application specific rf-optoelectronic circuit. It is another object of the present invention to maintain flexibility in the design and fabrication of the application specific rf-optoelectronic circuit. Yet another object of the present invention is to provide a two-part rf-optoelectronic circuit.
A further object of the present invention to use at least one generic chip in combination with a defining substrate, wherein the defining substrate determines the overall function of the circuit. Still a further object of the present invention is to maintain inexpensive and relatively fast fabrication of the application specific defining substrate.
Other advantages, objects and features of the present invention will become apparent when viewed in light of the detailed description of the preferred embodiment when taken in conjunction with the attached drawings and appended claims.

Application-specific optoelectronic integrated circuit