A sprung gangway that is counterbalanced to remain in a given degree of extension or retraction includes a lifting resistance device that includes a linear index rail that slides selectively into and out of a hollow sheath unless engaged by a locking paw that is pivotally mounted to the sheath via a pivot bar, which when pivoted by tugging on a release cord effects disengagement of the locking paw and thereby permits raising of the gangway from the lowered working orientation to a storage orientation.

In accessing the tops of rolling stock (tank trucks, tank railroad cars, etc.), a gangway or bridge is used to allow workers to move from an elevated loading platform to the top of the rolling stock. Such a gangway often includes self-leveling steps and is pivotally mounted to a platform that is disposed above the top of the rolling stock. In one type of these gangways such as disclosed in U.S. Pat. No. 7,140,467, which is hereby incorporated herein in its entirety by this reference for all purposes, the gangway is a retractable stairway 26 that has a retracted disposition in which the free end, i. e., the distal end, of the stairway is stored in a position that resides above the walking surface of the floor 22 to which the gangway is pivotally mounted. This retractable stairway 26 can include an adjustable chain stop 27 that is configured and disposed so as to limit downward swinging movement of the stairway 26.
In gangways that are disclosed in U.S. Pat. Nos. 4,679,657 and 7,216,741, which patents are hereby incorporated herein in their entirety by this reference for all purposes, the gangway can be moved pivotally like a drawbridge between a relatively elevated stowed orientation with respect to the top of rolling stock and a relatively lowered operative orientation with respect to the top of rolling stock. These gangways can include expansion springs or hydraulic actuators that are interconnected so as to bias or counterbalance the gangway to remain in any given orientation, for example the relatively elevated stowed orientation, and the user can push against this biasing or counterbalancing force to dispose the gangway in a different orientation, for example the relatively lowered operative orientation that leads to the top of the rolling stock. In such embodiments, the expansion springs and/or hydraulic actuators serve to counterbalance the weight of the gangway and so enable an individual user to move the gangway between the lowered operative orientation and the elevated stowed orientation by the exertion of a reasonable level of manual force by a typical individual user.
In gangways that are disclosed in U.S. Pat. Nos. 8,015,647 and 8,403,109, which patents are hereby incorporated herein in their entirety by this reference for all purposes, the gangway can be held in the lowered operative orientation by extending the piston rods from within actuating cylinders that force the gangway downward by overcoming the biasing force of expansion springs. However, such actuating cylinders are an added expense in themselves as well as introducing the further complexity and expense of providing the pressurized fluid and associated motors, compressor, valves and controls and that are necessary to the actuate the cylinders in order to operate them. This patent also discloses a foot-activated lock that can be engaged so as to restrain the gangway in the lowered orientation. This foot-activated lock is disposed near the walking surface of the platform from which the gangway is pivotally attached. Unfortunately, the heavy foot traffic of workers between the platform and the gangway can result in an inadvertent deactivation of the lock, and once the lock is deactivated the gangway 30 can be moved away from the top of the rolling stock and expose workers remaining on the rolling stock to a risk of falling if they are unaware of the removal of the gangway.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate at least one presently preferred embodiment of the invention as well as some alternative embodiments. These drawings, together with the written description, serve to explain the principles of the invention but by no means are intended to be exhaustive of all of the possible manifestations of the invention.

Device for resisting lifting of a gangway and gangway fitted with such device


A database management system has a query interface for receiving a query and a query executor for executing the received query. The query executor dynamically generates a task, and executes a plurality of tasks in parallel. In execution of each task, each time data is required to be read from a database, the query executor generates a task for acquiring the data, and in execution of the generated task, issues a data read request for reading the data from the database, to thereby shorten a time taken to execute each task.

1. Field of the Invention
The present invention relates to database management technologies.
2. Description of the Related Art
US20040117398 discloses a management server in a system which configures a database (DB) under a virtualization environment. The management server acquires DB processing information such as an execution plan and a processing priority of DB, from a database management system (DBMS), predicts data to be accessed and the order of accesses based on the information, instructs the reading of the data to be accessed in the near future on the cache of a storage device based on the prediction result, and reads the data to be accessed in the nearest future in the cache memory of its own server.

Database management system and method capable of dynamically generating new tasks that can be processed in parallel


A pick-up device for picking up a tubular knitted article from a circular knitting machine for hosiery and for transferring the article to a unit adapted to perform additional work thereon. The device comprises an annular pick-up body that supports pick-up members that can slide with respect to the pick-up body along radial directions. The pick-up body can be arranged coaxially around the needle cylinder of a circular knitting machine for hosiery so that each one of the pick-up members faces laterally a needle of the machine. The end of each one of the pick-up members that is directed toward the axis of the pick-up body has a seat that can engage a region of the stem of the needle that is arranged proximate to the latch of the needle on the opposite side with respect to the head of the needle. The device comprises actuation elements formed by elastic elements that act on the pick-up members for their sliding toward the axis of the pick-up body and radial pushers that act on the pick-up members for their sliding away from the axis of the pick-up body in contrast with the action of the elastic elements.

In the field of the production of knitted tubular articles with circular knitting machines for hosiery or the like, in some cases it is necessary to transfer the article from the machine used to produce it to another production unit in order to perform on the article additional work that cannot be performed on said machine or that it is not economically convenient to perform on said machine.
In particular, in the field of the production of hosiery, in recent years techniques have been developed for automated toe closing by sewing or looping. Some of these techniques are based on picking up the article from the machine used to produce it and on transferring it to a station for further work, which is distinct with respect to the production machine, so as to close the toe of the hosiery item in the station for further work, while the machine is used to produce another hosiery item. These techniques have the advantage, with respect to other techniques based on closing the toe of the hosiery item directly on the machine used to produce it, of not penalizing excessively the productivity of the machine.
The transfer of the hosiery item, or more generally of the tubular article, from the machine used for its production to the station in which the closure of an axial end of the article, or more generally additional work, must be carried out, is generally performed by means of a pick-up device, which by means of pick-up members individually grips the loops of knitting of the article from the needles of the machine and retains them during the transfer of the article.
In some toe closing techniques, the pick-up device is also used to support the article during the execution of the additional work, while in other techniques the pick-up device is used exclusively to transfer the article, since once it has reached the station where the additional work is to be done it releases, usually again in an individual manner, the loops of knitting picked up previously from the needles to another device that is designed to support the article during execution of the additional work, such as for example a handling device. Such handling device arranges the loops that belong to one half of the row of knitting received from the pick-up device so that they face the loops that belong to the other half of said row of knitting and supports the two half-rows of knitting in a mutually facing position during the intervention of a sewing or looping head that joins the pairs of mutually facing loops of knitting.
In known types of pick-up devices used to simply transfer the article from the machine that produces it to a handling device, the coupling between the pick-up members and the needles, in order to transfer the loops of knitting from the needles to the pick-up members, usually occurs by inserting the head of the needle in a seat formed in the end of the pick-up member. For that reason, the pick-up device usually has an annular pick-up body, designed to face coaxially the end of the needle cylinder from which the heads of the needles protrude and which supports a plurality of pick-up members oriented parallel to the axis of the pick-up body.
A pick-up device of this type is disclosed for example in EP0942086.
In devices of this type, the coupling between one end of the pick-up members and the head of the corresponding needle requires high precision both in the provision of the pick-up device as a whole and in the positioning of the pick-up body with respect to the needle cylinder of the machine and of the pick-up members with respect to the needles.
Moreover, the arrangement of the pick-up members, as well as the presence of any members for actuating them, entails a relatively large space occupation of the pick-up body along a direction that is parallel to the axis thereof. This relatively large space occupation can cause problems in positioning the pick-up body with respect to the machine in order to pick up the article. In order to be able to arrange the pick-up body so that it faces the needle cylinder of the machine, in the case of single-cylinder circular machines, it is in fact necessary to lift the dial and the yarn guides that are used to provide the needles with the yarns required to manufacture the article. This lifting can cause tangling of the yarns and accordingly cause problems when knitting on the machine resumes.
If the pick-up device is used with double-cylinder circular machines, the problems generated by the axial space occupation of the pick-up body are even greater, since in this case the pick-up body must be arranged between the two needle cylinders by first lifting the entire upper needle cylinder and the members connected thereto.

Pick-up device for picking up a tubular knitted article from a circular knitting machine for hosiery or the like and for transferring it to a unit adapted to perform additional work on the article


A group feed is displayed for a selected group by a private social network service. The group feed displays only threads with unviewed content along with a user actuatable display element that allows the user to switch to a feed that displays all content for the group.

Computer systems are currently in wide use. Some computer systems are used to provide social networking services.
As one example, a social networking service may be provided for private communications within an organization. Access to such a network may, for instance, be determined by a user's Internet domain so that only individuals with approved e-mail addresses may join their respective networks. In such networks, a user may subscribe to, or otherwise obtain membership in, a group. A group may correspond to a certain subject matter, a product group, a team, or a wide variety of other entities within an organization. The private social network service provides a platform for authoring and posting messages to a group message feed, and for other collaboration activities.
When a user belongs to a group, the private social network service allows the user to receive the message feed from the group. The feed illustratively displays messages that have been posted to that group.
In some such systems, a user can interact with messages in a feed. For instance, the user can reply, like, expand or otherwise interact with a message. A message, and its corresponding replies, comprise a thread. Therefore, a group feed within such a social network system can be comprised of a plurality of different threads, each thread including a plurality of different messages or other posts.
It is not uncommon for users of such systems to belong to a relatively large number of groups. Therefore, it can be difficult for a user to ensure that he or she is up to date on the content posted to the feeds for the various groups to which the user belongs.
The discussion above is merely provided for general background information and is not intended to be used as an aid in determining the scope of the claimed subject matter.


Monoclonal antibodies directed against coagulation factors and their use in inhibiting thrombosis are disclosed.

Under normal circumstances, an injury, be it minor or major, to vascular endothelial cells lining a blood vessel triggers a hemostatic response through a sequence of events commonly referred to as the coagulation "cascade." The cascade culminates in the conversion of soluble fibrinogen to insoluble fibrin which, together with platelets, forms a localized clot or thrombus which prevents extravasation of blood components. Wound healing can then occur followed by clot dissolution and restoration of blood vessel integrity and flow.
The events which occur between injury and clot formation are a carefully regulated and linked series of reactions. In brief, a number of plasma coagulation proteins in inactive proenzyme forms and cofactors circulate in the blood. Active enzyme complexes are assembled at an injury site and are sequentially activated to serine proteases, with each successive serine protease catalyzing the subsequent proenzyme to protease activation. This enzymatic cascade results in each step magnifying the effect of the succeeding step. For an overview of the coagulation cascade see the first chapter of "Thombosis and Hemorrhage", J. Loscalzo and A. Schafer, eds., Blackwell Scientific Publications, Oxford, England (1994).
While efficient clotting limits the loss of blood at an injury site, inappropriate formation of thrombi in veins or arteries is a common cause of disability and death. Abnormal clotting activity can result in and/or from pathologies or treatments such as myocardial infarction, unstable angina, atrial fibrillation, stroke, renal damage, percutaneous translumenal coronary angioplasty, disseminated intravascular coagulation, sepsis, pulmonary embolism and deep vein thrombosis. The formation of clots on foreign surfaces of artificial organs, shunts and prostheses such as artificial heart valves is also problematic.
Approved anticoagulant agents currently used in treatment of these pathologies and other thrombotic and embolic disorders include the sulfated heteropolysaccharides heparin and low molecular weight (LMW) heparin. These agents are administered parenterally and can cause rapid and complete inhibition of clotting by activation of the thrombin inhibitor, antithrombin III and inactivation of all of the clotting factors.
However, due to their potency, heparin and LMW heparin suffer drawbacks. Uncontrolled bleeding as a result of the simple stresses of motion and accompanying contacts with physical objects or at surgical sites is the major complication and is observed in 1 to 7% of patients receiving continuous infusion and in 8 to 14% of patients given intermittent bolus doses. To minimize this risk, samples are continuously drawn to enable ex vivo clotting times to be continuously monitored, which contributes substantially to the cost of therapy and the patient's inconvenience.
Further, the therapeutic target range to achieve the desired level of efficacy without placing the patient at risk for bleeding is narrow. The therapeutic range is approximately 1 to less than 3 ug heparin/ml plasma which results in activated partial thromboplastin time (aPTT) assay times of about 35 to about 100 seconds. Increasing the heparin concentration to 3 ug/ml exceeds the target range and at concentrations greater than 4 ug/ml, clotting activity is not detectable. Thus, great care must be taken to keep the patient's plasma concentrations within the therapeutic range.
Another approved anticoagulant with slower and longer lasting effect is warfarin, a coumarin derivative. Warfarin acts by competing with Vitamin K dependent post-translational modification of prothrombin and other Vitamin K-dependent clotting factors.
The general pattern of anticoagulant action,in which blood is rendered non-clottable at concentrations only slightly higher than the therapeutic range is seen for warfarin as well as for heparin and LMW heparin. Clearly, a need exists for an anticoagulant agent which is efficacious in controlling thrombotic and embolic disorders yet does not cause uncontrolled bleeding or its possibility.

Nucleic acids encoding immunoglobulin domains

University of Vermont and State Agricultural College


A method for operating a router which combines virtual channels is disclosed, where both forward and reverse directed resource management cells are used to control transmission rate of a source computer. The merging router receives forward directed resource management cells from a plurality of upstream routers, where each forward directed resource management cell represents a virtual channel. The router: (1) replies to each upstream router with a reverse directed resource management cell; and (2) forwards to a downstream router a combined forward directed resource management cell, the combined forward directed resource management cell combining a plurality of virtual channels established between the router and the plurality of upstream routers.

The present invention is directed to communications networks. It particularly concerns congestion avoidance.
Internetwork communications are based on operations of routers, which are network devices that determine, on the basis of destination information in packets that they receive, where to forward the packets so that they are likely to reach the intended destinations.
Router configurations vary widely, but that of FIG. 1 is typical. Router 10 includes a plurality of communications interfaces 12, 14, and 16, which send and receive communications packets to and from remote locations. When one of the interface modules receives an incoming packet from a remote location, it places header information from that packet onto an internal communications bus 18 by which it communicates with a forwarding engine 20 that determines where the packet should be sent. The interfaces and forwarding engine can be implemented in respective high-performance processors 21 and storage circuitry 22 that contains program instructions that configure the processors to act together as a router. The programming for such implementations is typically provided in some type of persistent medium, such as a magnetic disk or semiconductor read-only memory. That type of implementation most often executes that programming after it has been transferred to a volatile medium, such as dynamic or static random-access memory. The drawing shows the storage circuitry 22 as separate media for each interface or forwarding engine, but some configurations may additionally, or instead, employ common storage. In some cases the router's programming may be updated remotely by sending it electrical or other signals that represent the instructions.
To maximize speed capacity, other routers are implemented wholly or largely in "random logic" instead of general-purpose processors. The "programming" in such implementations is ordinarily hard-coded in the circuitry's structure, but read-only or read/write storage media may be employed in such implementations, too, to affect the router's behavior. Once the decision has been made, an output packet is formed from the input packet by packet-assembly circuitry that may reside in one or more of the interface modules and/or the forwarding engine, and the forwarding engine causes another interface to send the output packet to a further remote location.
Some routers may actually be implemented in switches that employ the Asynchronous Transfer Mode (ATM) protocol. Such switches operate in the manner that FIG. 2 depicts. Suppose that one of router 10's ATM interfaces provides communication with another router 24, while a different ATM interface provides communication with a further router 26. Suppose further that router 10 is an "edge router" of an internet-service provider: although it is part of a network that is maintained by the service provider, it has direct links to client routers such as router 26, which are outside the service-provider network.
Router 26 sends information in packets to router 10, and we will assume for present purposes that the packets sent by router 26 conform to the Internet Protocol (IP). In accordance with that protocol, each packet begins with a header that includes, among other information, an address that indicates the host system to which the packet should ultimately be routed. Router 10 includes storage circuitry containing a routing table that tells the router the direction in which to send the packet so that it will reach the destination set forth in the IP header.
Now, the service provider must of necessity base its initial routing decision on the incoming packet's destination address. But IP addressing makes doing so in the conventional manner a relatively time-consuming process. An IP address is typically 32 bits long: it could theoretically distinguish over four billion host systems. Although the number of host systems that have globally unique IP addresses is much smaller than this, the actual number of such systems is considerably greater than the number of entries it is practical for an individual router's forwarding table to include.
Many of the forwarding table's entries therefore are directed not to a single host address but rather to a "prefix" of fewer than the thirty-two bits. Such an entry indicates that the forwarding information contained in it can be used to reach any destination address that begins with the prefix to which the entry is directed. Prefixes vary in length, the longest being the most specific and thus presumably representing the best routes to the included host addresses. So a router that receives an IP packet searches through its forwarding table to find the longest prefix that matches the incoming packet's destination address, and it forwards the packet in accordance with the information thus found.
Such longest-match searches are time-consuming. But an Internet-service provider's "transit" routers, i.e., those that are not edge routers, can avoid such an expensive longest-match search if they forward the packets in ATM "cells." An ATM cell includes a "virtual-channel identifier," which identifies the receiving router's forwarding-table entry that contains the forwarding information for the "virtual channel" along which the cell is to be forwarded. For this purpose, an edge router such as router 10 works with other routers to set up a virtual channel within the service-provider network before it forwards the first packet to a particular destination. That is, successive routers determine the path through the network that such packets should take, and they tell each other where in their respective forwarding tables they keep forwarding information for that virtual circuit.
FIG. 3 depicts the format that ATM switches use to send information over the resultant virtual channel. From the point of view of an ATM client, the frame that FIG. 3's third row depicts is the basic transmission unit. (Those skilled in the art will recognize that there are also other possible ATM frame formats, but FIG. 6's third row depicts one, known as "AAL5," that would typically be employed for user data.) Since the service-provider network is being used to forward IP datagrams from router 26, that drawing's fourth row depicts the frame's payload as an IP datagram having the usual IP header and IP data.
From the point of view of such an ATM switch, though, the (variable-length) third-row frame is not the basic transmission unit. Specifically, the edge router divides that frame into pieces that it forwards in a plurality of equal-sized cells. As FIG. 3's second row shows, an ATM cell consists of a cell payload and header. FIG. 3's first row depicts the cell's header format and shows that it includes a PTI field. One purpose of the PTI field is to indicate whether the cell containing it is the last one in a frame. If it is, then the cell's last eight bytes form the frame trailer field depicted in FIG. 3's third row. Among other things, the trailer indicates how much of the preceding cell's contents is not actual frame payload but instead is fill used to pad the cell to the predetermined ATM cell size.
The header field of particular interest here is the VPI/VCI field. Each switch associates a virtual path or virtual channel with a virtual-path or virtual-channel identifier of local significance to that switch: it indicates the forwarding-table entry from which the switch is to fetch forwarding information for the cell being forwarded. Part of that entry's information is a replacement for the incoming cell's virtual-path or virtual-channel identifier. The replacement specifies the virtual path or virtual channel's correct entry in the forwarding table of the "next-hop" switch, to which the current switch's forwarding-table entry directs that the cell be sent.
Suppose that the client router 26 of FIG. 2 sends edge router 10 a packet whose IP destination address is D1. Also suppose that a further client router 28 provides access to that destination. The service-provider router having a direct link to client router 28 is router 30. To forward the packet properly, the provider network sets up an ATM virtual path from router 10 through routers 24 and 32 to router 30. Router 10 then divides packets specifying destination D1 into ATM cells, and it places into each such cell's header the virtual-path identifier V1 that router 10 learned during the virtual-channel-establishment process was the location in router 24's forwarding table where router 24 stored the proper forwarding information for the virtual channel to router 30. So router 24 does not need to perform a longest-match search when it receives such cells: it goes directly to the table entry that virtual-path identifier V1 specifies, and that entry tells it both the interface over which to forward the cell and the virtual-channel identifier V2 with which it should replace the incoming cell's virtual-channel identifier V1.
Similarly, router 32 employs virtual-channel identifier V2 to find its forwarding-table entry for that virtual channel. That entry tells router 32 to forward the cell over its interface with the link to router 30 and to place the value V3 into that cell's VPI/VCI field. Since router 30 is an edge router and must forward the packet to a non-ATM router 28, it assembles the IP-packet-containing frame from its constituent cells and forwards that IP packet, which still contains its destination address D1 to client router 28.
A similar sequence of events occurs when another customer router 34 sends an IP datagram containing destination address D1 to another edge router 36. As before, each of the routers along the service provider's path toward destination D1 allocates a virtual-channel identifier to that virtual channel. Edge router 36 encapsulates the datagram in an ATM frame and divides the frame into fixed-length cells whose virtual-channel identifier is, say, V4. Subsequent routers 40 and 32 forward such cells, replacing their virtual-channel identifiers with values V5 and V6, respectively. And, as before, the egress edge router 30 re-assembles the IP datagram and sends it to the customer router 28 that can forward it on to its ultimate destination.
Note that routers 30 and 32 in this scenario allocate two different virtual-channel identifiers to a common-destination path; they do not "merge" the channels by assigning a common virtual-channel identifier. This scenario is typical, even though virtual-channel identifiers are a relatively scarce resource in ATM switches.

This patent is subject to a terminal disclaimer.


The present disclosure provides for predictively allocating computing resources based on movement of a simulation agent through a simulation environment, such as in a video game. In order to support the movement of the simulation agent, computing resources may be allocated in various ways. For example, one option may be to transfer data assets associated with the simulation agent from the first computing resource to the second computing resource. Another option may be leave the data assets at the first computing resource and transfer authority over at least a portion of the second region from the second computing resource to the first computing resource. In various embodiments, the way in which the computing resources are allocated may be determined based on various factors, such as resource costs, so that the movement of the simulation agent can be supported with optimal system efficiency.

Software applications such as video games have become increasingly sophisticated, with intricate graphics, networked gameplay, and other advanced features. However, such applications require large amounts of data and computing resources. Game data or control of various aspects of a game may be distributed across a number of game servers and/or player devices. At certain points during gameplay, certain data may be transferred between game servers, between game servers and player devices, or even between player devices in order to render or enable certain aspects of the game. However, it may take an amount of time to transfer and load data, known as latency. Latency can cause delays in gameplay, incomplete rendering of game elements, communication lag, and other such disruptions, all of which contribute to a suboptimal gaming experience.

Resource allocation based on agent behavior in a simulation environment


In an oil separator for separating oil from a fluid flow with a labyrinth-like flow guide which is formed essentially by baffle walls, at least one of the baffle walls in at least one partial area can be deformed in a manner similar to rubber.

DE 101 19 892 C2 discloses one example of a cylinder head cover of an internal combustion engine which includes an elastomer part connected to a cover-like part of plastic. Also, DE 198 20 384 A1 discloses an oil separator with a labyrinth-like flow guide for crankcase ventilation, preferably for cylinder head covers of internal combustion engines.


Disclosed herein are MEMS resonator device designs and fabrication techniques that provide protection against electrostatic charge imbalances. In one aspect, a MEMS resonator device includes a substrate, an electrode including a first microstructure supported by the substrate, a resonant element including a second microstructure spaced from the first microstructure by a gap for resonant displacement of the second microstructure within the gap during operation, and a disabled shunt coupled to the electrode or the resonant element. The disabled shunt is disabled to enable the resonant displacement but otherwise configured to protect against damage from an electrostatic charge imbalance before the operation of the MEMS resonator device.

1. Field of the Disclosure
The disclosure relates generally to microelectromechanical systems (MEMS) and, more particularly, to MEMS resonator devices.
2. Brief Description of Related Technology
Many types of MEMS resonators are electrostatically actuated. A resonant element of the MEMS device is spaced from stationary electrodes such that the MEMS device is coupled across one or more air gaps. In some designs, the size of the gap between the resonant element and a stationary electrode is significantly less than 1 micron. Vibration of the resonant element varies the spacing between the resonant element and stationary electrodes. To maximize the coupling, the opposing surfaces of the resonant element and stationary electrodes are often large in comparison with the size of the air gap. For example, the surface area in some designs exceeds 1000 μm2.
The large opposing surfaces and small air gap have complicated the fabrication of MEMS resonators. For instance, releasing the resonant element has required a wet etch or other steps in which capillary forces can undesirably pull the resonant element into a collapsed, inoperative condition often referred to as stiction. Stiction has long been recognized as a source of yield loss in MEMS device fabrication.
A number of design solutions and fabrication techniques have been proposed and implemented to minimize stiction-based yield losses. Nonetheless, MEMS device yields often remain unsatisfactorily low due to collapsed resonant elements.

ESD protection for MEMS resonator devices


A handheld gesture recognition control apparatus and its method are provided for a mobile phone. The input method of the present invention includes collecting a plurality of images; storing the images as control images; mapping the control images to corresponding control commands; capturing an image taken by a camera as a current image; comparing the current image to the control images; selecting one of the control images as a target control image according to a comparison result; extracting a control command mapped to the target control image; and executing the control command.

1. Field of the Invention
The present invention relates to a mobile phone and, in particular, to a handheld gesture recognition input system and its method for a mobile phone.
2. Description of the Related Art
As mobile phones integrate various multimedia modules and functions, different input technologies have been developed for enhancing the convenience of a user's manipulation. Among them keypad, touchscreen, and speech recognition based input technologies that are currently available.
A keypad input system is a well known solution, in which a plurality of keys is arranged on a keypad such that pressing a series of keys generates a mobile phone-recognizable instruction.
A touchscreen input system has been offered as an alternative manual input method and collects coordinates generated by touch events on a touchscreen, then recognizes an input signal by comparing the coordinates of the images on the screen.
A speech recognition input system is another alternative input system. The speech recognition input system analyzes a voice input and generates a mobile phone-recognizable instruction corresponding to the voice input through a microphone. Although the keypad, touchscreen, and speech recognition input systems are useful, they have implementation limits in mobile phones. That is, the keypad input system has a limit of securing enough space for arranging a plurality of keys, and also the touchscreen input system has a key event generation portion limited by the touchscreen. In the speech recognition system, recognition reliability is very dependent on the noise environment, and a high accuracy is required for matching input speech against a stored representation.
For these reasons, there is a need for developing a novel input technology for a space-limited mobile phone that is capable of facilitating information conveyance as well as mobile phone control.

Hand gesture recognition input system and method for a mobile phone

Maetan-dong, Yeongtong-gu, Suwon-si, Gyeonggi-do, Korea


The invention relates to a microelectromechanical structure, and more particularly, to systems, devices and methods of compensating the effect of the thermo-mechanical stress by incorporating and adjusting elastic elements that are used to couple a moveable proof mass to anchors. The proof mass responds to acceleration by displacing and tilting with respect to a moveable mass rotational axis. The thermo-mechanical stress is accumulated in the structure during the courses of manufacturing, packaging and assembly or over the structure's lifetime. The stress causes a displacement on the proof mass. A plurality of elastic elements is coupled to support the proof mass. Geometry and configuration of these elastic elements are adjusted to reduce the displacement caused by the thermo-mechanical stress.

A. Technical Field
The present invention relates to a microelectromechanical structure, and more particularly, to systems, devices and methods of compensating effect of thermo-mechanical stress by incorporating and adjusting elastic elements that are used to couple a moveable proof mass and anchors included in the microelectromechanical structure.
B. Background of the Invention
A microelectromechanical structure is widely applied as a sensor to measure acceleration, rotation, pressure, temperature and many other physical parameters. The microelectromechanical structure is normally formed on a silicon substrate using a micromachining process that results in characteristic feature sizes of several micrometers. Such miniaturized devices may transduce mechanical movement to electrical properties. One typical microelectromechanical structure is a micromachined capacitive accelerometer that comprises a proof mass that is suspended above a silicon substrate.
FIG. 1A illustrates a z-axis capacitive accelerometer 100, and FIG. 1B illustrates its response 150 to an out-of-plane acceleration. The z-axis capacitive accelerometer 100 has its moveable proof mass 102 anchored to a substrate 104 via an anchor 106. Electrodes are formed on both the proof mass 102 and the stationary substrate, such that two capacitors 108A and 108B are formed and arranged on two sides of the anchor 106. In response to an out-of-plane acceleration along the z-axis, the proof mass 102 tilts with respect to its rotation axis 106. The gaps between the proof mass 102 and the corresponding electrodes, 110A and 110B, vary differently, and lead to a mismatch between capacitors 108A and 108B. Such a capacitance mismatch is processed by an interface circuit to output a signal that indicates the magnitude of the out-of-plane acceleration.
Thermo-mechanical stress may introduce an intrinsic offset or drift to the output even though no out-of-plane acceleration is applied. In an ideal situation, the capacitance mismatch between capacitors 108A and 108B should only be associated with the out-of-plane acceleration, and does not exist when no out-of-plane acceleration is involved. However, thermo-mechanical stress may be accumulated in the substrate 104 during the course of soldering and packaging, unavoidably causing the substrate to warp. When such warping is symmetric with respect to the anchor 106, the capacitor gap variations happen to cancel out and result in no capacitance mismatch between capacitors 108A and 108B. In most cases, substrate warping is asymmetric. Regardless of how close they could be, gap variations of capacitors 108A and 108B are always different. Such asymmetric gap variations are incorporated into the final output from the interface circuit, and lead to an offset in the sensed acceleration and a sensitivity drift for the accelerometer 100.
Apparently, device performance of the capacitive accelerometer 100 is compromised due to the thermo-mechanical stress in the substrate 104. Such performance degradation is commonly shared by microelectromechanical structures that rely on suspended proof masses for sensing and transducing mechanical movement. A need exists to compensate the thermo-mechanical stress that is built up in the substrate 104 during the course of manufacturing, packaging, assembly and lifetime operation.

Micro-electromechanical structure with low sensitivity to thermo-mechanical stress


The present invention relates to compounds of general formula I

The intake of food and its conversion in the body is an essential part of life for all living creatures. Therefore, deviations in the intake and conversion of food generally lead to problems and also illness. The changes in the lifestyle and nutrition of humans, particularly in industrialised countries, have promoted morbid overweight (also known as corpulence or obesity) in recent decades. In affected people, obesity leads directly to restricted mobility and a reduction in the quality of life. There is the additional factor that obesity often leads to other diseases such as, for example, diabetes, dyslipidaemia, high blood pressure, arteriosclerosis and coronary heart disease. Moreover, high body weight alone puts an increased strain on the support and mobility apparatus, which can lead to chronic pain and diseases such as arthritis or osteoarthritis. Thus, obesity is a serious health problem for society.
The term obesity means an excess of adipose tissue in the body. In this connection, obesity is fundamentally to be seen as the increased level of fatness which leads to a health risk. There is no sharp distinction between normal individuals and those suffering from obesity, but the health risk accompanying obesity is presumed to rise continuously as the level of fatness increases. For simplicity's sake, in the present invention, individuals with a Body Mass Index (BMI), which is defined as the body weight measured in kilograms divided by the height (in metres) squared, above a value of 25 and more particularly above 30, are preferably regarded as suffering from obesity.
Apart from physical activity and a change in nutrition, there is currently no convincing treatment option for effectively reducing body weight. However, as obesity is a major risk factor in the development of serious and even life-threatening diseases, it is all the more important to have access to pharmaceutical active substances for the prevention and/or treatment of obesity. One approach which has been proposed very recently is the therapeutic use of MCH antagonists (cf. inter alia WO 01/21577, WO 01/82925).
Melanin-concentrating hormone (MCH) is a cyclic neuropeptide consisting of 19 amino acids. It is synthesised predominantly in the hypothalamus in mammals and from there travels to other parts of the brain by the projections of hypothalamic neurones. Its biological activity is mediated in humans through two different G-protein-coupled receptors (GPCRs) from the family of rhodopsin-related GPCRs, namely the MCH receptors 1 and 2 (MCH-1R, MCH-2R).
Investigations into the function of MCH in animal models have provided good indications for a role of the peptide in regulating the energy balance, i.e. changing metabolic activity and food intake [1,2]. For example, after intraventricular administration of MCH in rats, food intake was increased compared with control animals. Additionally, transgenic rats which produce more MCH than control animals, when given a high-fat diet, responded by gaining significantly more weight than animals without an experimentally altered MCH level. It was also found that there is a positive correlation between phases of increased desire for food and the quantity of MCH mRNA in the hypothalamus of rats. However, experiments with MCH knock-out mice are particularly important in showing the function of MCH. Loss of the neuropeptide results in lean animals with a reduced fat mass, which take in significantly less food than control animals.
The anorectic effects of MCH are presumably mediated in rodents through the Gαs-coupled MCH-1R [3-6], as, unlike primates, ferrets and dogs, no second MCH receptor subtype has hitherto been found in rodents. After losing the MCH-1R, knock-out mice have a lower fat mass, an increased energy conversion and, when fed on a high fat diet, do not put on weight, compared with control animals. Another indication of the importance of the MCH system in regulating the energy balance results from experiments with a receptor antagonist (SNAP-7941) [3]. In long term trials the animals treated with the antagonist lose significant amounts of weight.
In addition to its anorectic effect, the MCH-1R antagonist SNAP-7941 also achieves additional anxiolytic and antidepressant effects in behavioural experiments on rats [3]. Thus, there are clear indications that the MCH-MCH-1R system is involved not only in regulating the energy balance but also in affectivity.

Pyridone derivates with MCH antagonistic activity and medicaments comprising these compounds

Abstract: wherein the groups and radicals B, k, L, U, V, W, X, Y, Z, R1, R2, have the meanings given in claim 1. Moreover the invention relates to pharmaceutical compositions containing at least one compound according to the invention. By virtue of their MCH-receptor antagonistic activity the pharmaceutical compositions according to the invention are suitable for the treatment of metabolic disorders and/or eating disorders, particularly obesity, bulimia, anorexia, hyperphagia and diabetes.


An etching method of etching a multilayered film includes etching a multilayered film by generating plasma within a processing vessel of a plasma processing apparatus. In the etching of the multilayered film, a first processing gas containing a hydrogen gas, a hydrogen bromide gas, a fluorine-containing gas, a hydrocarbon gas, a hydrofluorocarbon gas and a fluorocarbon gas is supplied from a first supply unit configured to supply a gas toward a central region of the processing target object and a second supply unit configured to supply a gas toward outer region than the central region; a second processing gas containing a hydrocarbon gas and a fluorocarbon gas is supplied from either one of the first supply unit and the second supply unit; and the first processing gas and the second processing gas are excited.

As a kind of semiconductor device, there is known a NAND type flash memory device having a three-dimensional structure. In the manufacture of this NAND type flash memory device having the three-dimensional structure, a deep hole is formed in a multilayered film, which is composed of alternately stacked two layers having different permittivities, by performing an etching process. This etching process is described in Patent Document 1.
To elaborate, in Patent Document 1, there is described a method of etching a multilayered film by exposing a processing target object, which has a mask made of silicon nitride on the multilayered film, to plasma of a processing gas containing a CH2F2 gas and a NF3 gas.
Patent Document 1: U.S. Patent Application Publication No. 2013/0059450
In the above-described etching of the multilayered film, a space such as a hole is required to be formed on the entire region of the processing target object with straightness, i.e., high verticality, in a stacking direction of the multilayered film. In the method set forth in Patent Document 1, however, the verticality of the space may be degraded on a partial region of the processing target object in a diametrical direction thereof.
Thus, it is required to suppress deterioration of the verticality of the space on the partial region of the processing target object.


A semiconductor device testing apparatus is provided which includes an output voltage corrective circuit wherein a test voltage to be applied to a semiconductor under test (DUT) 14 is corrected through digital processing. An offset memory 1, a gain memory 2, an output level register 3, a tester processor 5, a selection register 15, a selector 16, a data register 17, an all-pin data setting sequencer 19, a load controller 20, a digital multiplier 21, and a digital adder 22 are provided in the main frame of the testing apparatus. A multi-channel D/A converter 23 for converting digital serial data from the main frame to analog parallel data for each channel and drivers 13 each for applying the test voltage to one of the pins of the DUT 14 are provided in the test head of the testing apparatus. The offset memory 1 prestores therein offset data contained in correction data and the gain memory gain data also contained in the correction data. The output level register 3 stores therein the test voltage to be applied to the pin of the DUT for each channel.

1. Field of the Invention
The present invention relates to a semiconductor device testing apparatus suitable for testing semiconductor devices such as semiconductor integrated circuits, and more particularly, to a semiconductor device testing apparatus having an output voltage corrective circuit of the type that corrects, by digital processing, a voltage of a test signal to be applied to a semiconductor device under test (semiconductor device under test, commonly called DUT) and outputs the corrected voltage.
2. Description of the Related Art
A semiconductor device testing apparatus (commonly called an IC tester) for testing a semiconductor device, specifically, a semiconductor integrated circuit (hereinafter referred to as IC) which is a typical example of semiconductor devices, has in its body (commonly called main frame) a various kinds of circuits of the testing apparatus that generate a test signal of a predetermined pattern to be applied to an IC to be tested (IC under test), an address signal, a control signal and so forth for application to the IC under test, and receive and process response signals from the IC under test to measure their electric characteristics. A test head (commonly called pin electronics) of the testing apparatus, which applies the test signal of a predetermined pattern, the address signal, the control signal and so forth to the IC under test, and receives response signals therefrom, is placed at a distance from the main frame (for example, at a test section of a semiconductor device transporting and handling apparatus commonly called handler which transports a semiconductor device for testing, and handles or processes the tested semiconductor device on the basis of the test results). The test head has a socket mounted thereto, with which the IC is brought into electrical contact when a predetermined test is performed.
While the semiconductor device testing apparatus will hereinbelow be described as being applied to testing of ICs which are a typical example of semiconductor devices for brevity of description, it is needless to say that the semiconductor device testing apparatus of this kind can be used to test other semiconductor devices than IC as well.
As is well known in the art, an IC to be tested has a number of terminals (leads) or pins and the semiconductor device testing apparatus (hereinafter referred to as IC tester) carries out testing of the IC by applying a test signal of a predetermined pattern to each of the pins of the IC under test (DUT). To this end, the IC tester and each pin of the DUT (in practice, each terminal of the socket to which the DUT is mounted) are electrically connected to each other via an independent or separate electrical path (including a circuit or circuits). Usually, the path between the IC tester and each pin of the DUT is called a channel.
The voltage of a test signal, which is applied to each of the pins of a DUT, often differs from the voltage value set in the IC tester due to variations in the characteristics, values, or the like of individual elements forming respective paths, or owing to various other causes. Hence, it is necessary that voltages of test signals to be applied to the pins of a DUT be corrected in compensation for variations or the like in respective paths.
An example of this kind of prior IC tester is illustrated in FIGS. 9 and 10. FIG. 9 shows the configuration of the pertinent part of the circuits of the IC tester housed in its main frame, and FIG. 10 shows a test head of the IC tester and an IC under test (DUT).
As shown in FIG. 9, the IC tester of this example has in its main frame an offset memory 1, a gain memory 2, a plurality of RON output level registers 3, an output level selection register 4, a tester processor 5, a first, a second and a third digital-to-analog (D/A) converters 6, 7 and 8, a selector 9, an analog selector 10, a refresh capacitor 11, a plurality of RON/ROF selection register 15, an RON/ROF selector 16, an ROF data register 17, and a refresh sequencer 18.
As depicted in FIG. 10, there is provided in the test head a driver 13 for applying a test signal to each of the pins of a DUT 14. Although only one driver 13 is shown in FIG. 10, the number of such drivers is equal to the number of pins of the DUT 14, and accordingly, the number of channels. The main frame and the test head are electrically connected via cables 12 (only one cable 12 is shown in FIG. 10, but the number of such cables is equal to the number of channels), and the output voltage from each driver 13 is applied to the corresponding pin of the DUT 14 via a cable and an IC socket not shown.
In the offset memory 1 there is prestored (previously stored) offset data contained in data that is used to compensate for variations of the channels to the respective pins of the DUT. In the gain memory 2 there is prestored gain data also contained in the immediately mentioned data. These offset and gain data will be described later on.
The number of RON output level registers 3 used is set to the same number as that of several kinds of independent voltage values of test signals to be applied to DUTs, and the voltages of different values are stored in the corresponding RON output level registers, respectively. When only one kind of voltage value, for example, 3 V is applied to the DUTs, one RON output level register may suffice to test them. In general, however, a plurality of RON output level registers are provided so that a required kinds of set voltage values can be stored in selected ones among them, respectively. Thus, the voltage values corresponding in number to the RON output level registers 3 can be set. Since the illustrated example is provided with eight RON output level registers 3, it is possible to set up to eight independent voltage values to be applied to the DUTs. These voltage values are set by a test program.
The output level selection register 4 stores therein select information for determining which voltage value among the voltage values stored in the RON output level registers 3 is to be allocated to the corresponding one of the pins of each DUT, and accordingly the channels thereto. The RON/ROF selection registers 15 each store therein select information for determining whether to output the set voltage stored in the corresponding RON output level register 3 (an RON state) or to output the set voltage stored in the ROF data register 17 (an ROF state). Accordingly, the number of RON/ROF selection registers 15 is the same as that of the RON output level registers 3. Since in this example eight RON output level registers 3 are provided, the number of RON/ROF selection registers 15 used is also eight. These select information stored in the selection registers 4 and 15 are set by the test program.
What is meant by the term "RON state" is to turn on (ON) the voltage set in the RON output level register 3, that is, refers to an operation by which the voltage set in the RON output level register 3 is outputted therefrom. The term "ROF state" is intended to refer to an operation by which the voltage set in the RON output register 3 is turned off (OFF) and 0 V of the initial voltage value is outputted from the ROF data register 17.
The tester processor 5 is a central processing unit (CPU) which exerts centralized control over the whole IC tester including peripheral equipment, and it responds to instructions of the test program to provide predetermined data, voltages and select information to the offset memory 1, the gain memory 2, the RON output level registers 3, the output level selection register 4, and the RON/ROF selection registers 15.
The ROF data register 17 stores therein 0 V as a fixed value that is a set voltage outputted in the ROF state.
The refresh sequencer 18 generates a sequence of serial data generation and processing, and sequentially controls the offset memory 1, the gain memory 2, and the output level selection register 4.
The refresh sequencer 18 is always in operation since the voltage corrected for each channel to be applied to the corresponding one of the pins of the DUT 14 needs to be charged in the refresh capacitor 11 in each channel at all times. The offset memory 1, the gain memory 2 and the output level selection register 4 operate in accordance with the sequence generated by the refresh sequencer 18 and sequentially output respective signal data for each channel. The offset data prestored in the offset memory 1 and the gain data prestored in the gain memory 2 are inputted into the first D/A converter 6 and the second D/A converter 7 where they are converted into analog data, respectively. The output from the second D/A converter 7 is inputted via an amplifier amp2 into a terminal vref (reference voltage terminal) of the third D/A converter 8 to correct its reference voltage vref, namely, its gain.
Either the output data of each RON output level register 3 which is the test signal to be fed to the DUT 14 or the output data of the ROF data register 17 with the fixed voltage of 0 V stored therein is selected by the RON/ROF selector 16 in response to a select signal that is provided thereto from the corresponding RON/ROF selection register 15. The voltage data selected by the RON/ROF selector 16 is fed to the selector 9. Responding to a select signal fed thereto from the output level selection register 4, the selector 9 selects the channel over which the received voltage data is to be sent. In this way, the RON/ROF voltage data for each channel specified by the test program is outputted from the selector 9. This voltage data is inputted into the third D/A converter 8 where it is converted into analog data.
The analog voltage data outputted from the first D/A converter 6 is provided via an amplifier amp1 to an inverting input terminal of another amplifier amp3 subsequent thereto and the analog voltage data outputted from the third D/A converter 8 is provided to a non-inverting input terminal of the amplifier amp3, wherein they are added to each other or subtracted one from the other in analog form. The output from the amplifier amp3 is inputted as corrected analog voltage data into the analog selector 10 which converts the inputted serial data to parallel data corresponding to the individual channels and outputs a corrected analog voltage to each channel.
It is arranged that the analog voltage outputted from the analog selector 10 charges the refresh capacitor 11 in each channel, which holds it while a different channel is being selected.
Since the main frame and the test head are electrically connected via the cables 12 as mentioned previously, the voltage charged in the refresh capacitor 11 of each channel is amplified by an amplifier amp4 and then applied via the associated cable 12 to the corresponding driver 13 provided in the test head. The output of each driver 13 is connected to the corresponding terminal of an IC socket (not shown) mounted on the test head. Therefore, when the DUT 14 is brought into electrical contact with the IC socket, the output voltage is applied as a test voltage to each pin of the DUT 14 from the driver 13 corresponding thereto.
It is most desirable that the above-described voltage generator circuit (including the driver 13) of each channel, which generates the voltage for test to be applied to the DUT, be configured so that its output voltage characteristic with respect to the voltage value set in the corresponding RON output level register 3 (the output voltage characteristic of the driver 13) offers or exhibits a linear equation of the coefficient 1. Though linear circuit elements are used as circuit elements forming the respective voltage generator circuits of respective channels, in practice, there are many cases that each voltage generator circuit (driver 13) does not necessarily exhibits its output voltage characteristic which is represented by a linear equation of the coefficient 1 with respect to the set voltage due to variations in circuit elements, or owing to various other causes. Therefore, by merely setting the applied voltage to the DUT or the driver output voltage, the output voltage of each voltage generator circuit can seldom come to the set value. For this reason, it is customary in the art to always correct the set voltage outputted from the RON output level register 3 so that the output voltage characteristic of the voltage generator circuit of each channel exhibits a linear equation of the coefficient 1 and thereafter a test for DUTs is performed by applying the corrected voltage for test to the DUTS.
This will be described below in more detail. If the relationship between the output voltage of the voltage generator circuit of each channel, that is, the output voltage Y of the driver 13 at the last stage and the set voltage X of, the RON output level register 3 exhibits the following linear equation EQU X=Y
then the output voltage characteristic of the voltage generator circuit of each channel will come to the linear equation of the coefficient 1 as indicated by the solid line in FIG. 8. As a result, the proper output voltage can be obtained from the driver by merely setting the driver output voltage. Practically, in most instances, however, the relationship between the output voltage Y of the driver 13 at the last stage and the set voltage X exhibits the following linear equation EQU Y=BX+C
as indicated by the broken line in FIG. 8 owing to variations in the circuit elements used or various other causes. In the above, B is a coefficient and C is a constant. For example, when the set voltage is 3 V, the output voltage of 3 V will be obtained with respect to the set voltage of 3 V if the driver 13 has such an output voltage characteristic as indicated by the solid line in FIG. 8. Since the actual driver output voltage characteristic will become Y=BX+C due to the differences in characteristic, value or the like between the circuit elements or for some other reasons, an output voltage of only 2.5 V or so, for instance, can be obtained. It is therefore necessary to make corrections in which the coefficient B becomes 1 and the constant C becomes 0 so as to obtain the output voltage of 3 V.
Even if the voltage generator circuits of respective channels have exactly the same circuit configuration, the values of the coefficient B and the constant C often differ between channels due to the variation in the circuit elements used or owing to various other causes. Therefore, corrections of the values of the coefficient B and the constant C must be made for each channel so that an output voltage of each channel becomes the set voltage. The offset data prestored in the offset memory 1, which is contained in the data for compensating for the variations of the circuit elements of each channel, corresponds to the above-mentioned constant C, and the gain data prestored in the gain memory 2 corresponds to the above-mentioned coefficient B.
Next, a description will be given of a method for correcting the driver output voltage in a conventional IC tester of the above configuration.
First, the RON output level registers 3 are put in the ROF state and the zero volt set in the ROF data register 17 is selected and provided via the analog selector 10 to the corresponding channel. The output voltage from the driver 13 of the test head at this time is measured. This measured value is used as offset data (C in the equation of the broken line in FIG. 8), and hence it is stored in the offset memory 1. Next, the RON output level registers 3 are put in the RON state and an arbitrary set voltage is selected and provided via the analog selector 10 to the same channel. The output voltage from the driver 13 of the test head at this time is also measured. Based on the ideal value in this case (an arbitrary set voltage) and the measured value, gain data is calculated by the test processor 5 so that the set voltage is obtained from the driver 13. The gain data thus obtained is stored in the gain memory 2.
Since the gain and offset data are unique or inherent values of each pin of the DUT, the above operation is repeated for each channel and the offset data of each channel is stored in the offset memory 1 and the gain data in the gain memory 2, respectively.
During testing the offset memory 1, the gain memory 2 and the output level selection register 4 are sequentially controlled by the refresh sequencer 18. The gain memory 2 is thus accessed, from which the corrected gain data is fed via the second D/A converter 7 and the amplifier amp2 to the terminal vref of the third D/A converter 8 to set its reference voltage Vref based on the corrected gain data. By this, the reference voltage Vref of the third D/A converter 8 (and consequently the slope of the output voltage characteristic in FIG. 8) is altered in an analog quantity. The corrected offset data is read out of the offset memory 1 and fed via the first D/A converter 6 and the amplifier amp1 to the amplifier amp3 for analog addition to or subtraction from the corrected set analog voltage that is provided from the third D/A converter 8.
Output voltages thus corrected by analog processing for all channels CH1 to CHn are sequentially outputted from the analog selector 10, then the refresh capacitors 11 of all the channels are charged one after another, and the charged voltages are supplied to the drivers 13 of the test head for application to the respective pins of the DUT.
FIG. 11 is a timing chart showing the operation sequence described above. In this example, three kinds of voltages of 3 V (HIN1), 2 V (HIN2) and 1 V (HIN3) are set in three of the output level registers 3, respectively, and the set voltages are selected by a test program in the order of 3 V.fwdarw.1 V.fwdarw.2 V.fwdarw.3 V .fwdarw.. . . 3 V.fwdarw.1 V.fwdarw.2 V.fwdarw.3 V for the channels CH1 through CHn. Further, this example shows the case that select information is inputted into the RON/ROF selection registers 15 from the test program so as to select the set voltages of 3 V (HlN1) and 2 V (HIN2) and so as not to select the set voltage of 1 V (HIN3) and hence so as to select ROF (0 V). Thus, the set voltages are outputted from the analog selector 10 to the channels CH1 through CHn in the order of 3 V.fwdarw.0 V.fwdarw.2 V.fwdarw.3 V.fwdarw. . . . 3 V.fwdarw.0 V.fwdarw.2 V.fwdarw.3 V.
Since the conventional IC tester has a construction which charges and holds the corrected output voltage in the refresh capacitor 11, a refresh circuit is naturally needed to hold the voltage. The refresh circuit is always in operation during testing the operation of the DUT, and hence there is a drawback that the refresh circuit interferes with other circuits of the IC tester, which results in deterioration of the accuracy of the test for the operation of the DUT.
Another problem of the prior art lies in that charging the refresh capacitor 11 is time-consuming since it has a time constant. On this account, as indicated by the waveform in the prior art shown in FIG. 12(A), the refresh capacitor 11 is not charged up to the set voltage level on only a single charge over one refresh cycle period during the RON/ROF state, and hence it has a drawback that its settling time is long. That is, it requires much time for the charged voltage of the refresh capacitor 11 to reach the set voltage level and become stable, and hence there is a disadvantage that the time duration of the test is lengthy.
Further, since the refresh circuit charges the capacitors 11 of the respective channels in a sequential order (i.e. serially), charged voltages in all the channels do not rise up at the same timing and a time delay occurs for each channel. The time delay from the time point that the capacitor of the first channel is fully charged to the time point that the capacitor of the last channel is fully charged increasing more and more as the number of channels is increased. When the time delay is increased, it is difficult to simultaneously apply test signals (voltages for test) to all the pins of the DUT with a predetermined delay after the application of the power supply voltage to the DUT. As will be understood from the waveform in the prior art shown in FIG. 7(A), after the application of the power supply voltage to the DUT, the channel CH1 rises up after a time interval tb has passed, but a time interval tc is required until the channel CHn rises up after the channel CH1 has risen. For this reason, it is difficult to simultaneously apply voltage signals for test to all the pins of the DUT unless the time delay of tc is given. As stated above, the time delay tc is increasing more and more as the number of channels is increased. Accordingly, since every IC is supplied with voltages its all terminal pins at the same time in its actual use, there is a disadvantage that the test corresponding to the actual use of an IC cannot be performed.
Another disadvantage of the conventional IC tester is that a large-scale corrective circuit must be used for correcting the set voltages because the set voltages are corrected through analog processing. Since it is hard to place such a large-scale circuit in the test head of a multi-channel configuration, it is general practice in the prior art to connect the main frame and the test head via a large number of cables for the transmission of voltage signals. This requires a cable for each channel, and hence the large amount of cables must be used.
Besides, if it is wanted to test a DUT with a different set voltage applied to a particular one or more of the pins of the DUT from the remaining pins thereof, it is necessary in the prior art to alter or modify the test program since a distinct independent setting cannot be made. Accordingly, this is time-consuming and troublesome.


A wheel mounting assembly for installing a transmission-based anti-lock braking system sensor thereon has a stub axle. An anti-lock braking system sensor is mounted relative to the stub axle. A hub is rotatably mounted on the stub axle. A disc is mounted for rotation with the hub. The disc has a plurality of apertures circumferentially spaced on a face thereof for passing the anti-lock braking system sensor as the disc rotates.

Trucks such as pickup trucks and the like are often used to transport small cargo loads and/or to make deliveries and pickups. One of the difficulties of using such trucks is that of loading and unloading heavy or awkward cargo when a loading dock of proper height is not available. For example, the cargo box of a pickup truck can be three or more feet off of the ground, making it difficult to load or unload cargo to and from the cargo box.
Various attempts have been made in the past to make it easier to load and unload cargo. For example, Canadian patent application no. 2,145,259, published Sep. 23, 1995, illustrates a vehicle having a U-shaped chassis with a drop tray decking. The tray is powered by hydraulics at each corner of the decking to raise and lower the tray. However, such a system requires a sophisticated control system for activating the hydraulics to ensure that each of the hydraulic cylinders operate simultaneously.
U.S. Pat. Nos. 4,902,188 to Page and 5,288,197 to Harris show systems wherein the cargo platform of a vehicle and a trailer, respectively, is lowered by pivoting the platform rearward and downward to facilitate easier loading and unloading of cargo. These systems suffer from the fact that they require a clear space behind the vehicle or trailer to allow the cargo platform to move rearward as it is pivoted downward.
Vehicles according to U.S. Pat. No. 4,902,188 to Page were briefly offered for sale in the United States under the trademark KELPIE KARGO. However, such vehicles were not commercially successful.
On some vehicles, the antilock braking system sensors are mounted on the rear differential of the drivetrain. On removing the rear axle to convert such vehicles to have an elevating cargo box, it was discovered that the antilock braking system brakes would not function properly without the sensor. Further, certain manufacturers use the antilock braking system sensor as a digital input for the speedometer and without a sensor, the speedometer would not operate.

Wheel mounting assembly for installing a transmission-based anti-lock braking system sensor thereon


A reprogrammable metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. A lower barrier layer is formed from Ti. A lower adhesion-promoting layer is disposed over the lower Ti barrier layer. An antifuse material layer selected from a group comprising at least one of amorphous carbon and amorphous carbon doped with at least one of hydrogen and fluorine is disposed over the lower adhesion-promoting layer. An upper adhesion-promoting layer is disposed over the antifuse material layer. An upper Ti barrier layer is disposed over the upper adhesion-promoting layer.

1. Field of the Invention
The present invention relates to amorphous carbon metal-to-metal antifuse structures. More particularly, the present invention relates to reprogrammable amorphous carbon metal-to-metal antifuse structures employing adhesion layers and titanium (Ti) barrier layers.
2. The Background Art
Integrated electronic circuits are typically fabricated with all internal connections set during the manufacturing process. However, because of high development costs and high manufacturing tooling costs of such circuits, it is advantageous for integrated circuits to be configured or programmed by the user to implement a desired application. Such circuits are called programmable circuits, and antifuses are known in the art for providing the programmability of these circuits. Antifuses are devices that generally comprise a pair of conductive electrodes sandwiched about an insulating antifuse material layer.
A programming process disrupts the antifuse material and forms a filament between the two electrodes. Prior to programming, antifuses exhibit a resistance as high as a few gigaohms between the two electrodes and may be considered to be open circuits. The programming process creates a low-impedance connection of a few ohms to a few thousand ohms between the two electrodes. Programming voltages range from a few volts to about 20 volts.
It is known in the art that antifuses have been fabricated where the electrodes have been selected from a number of different electrically conductive layer materials, and the antifuse material layer has been fabricated from a number of different insulating materials. It is also known that many different antifuse structures have been proposed, including, "via" type, half-stacks, full stacks, conductive plugs and numerous other variations.
Antifuses are generally classified into two categories. A first type of antifuse, referred to as a substrate antifuse, has a doped region in a semiconductor substrate as its lower electrode and a layer of metal or doped polysilicon as its upper electrode. The antifuse material typically comprises one or more layers of silicon nitride or silicon dioxide. An example of such an antifuse is made of an oxide-nitride-oxide (ONO) antifuse material layer sandwiched between an N+ diffusion layer and a polysilicon ("Poly") layer (N+/ONO/Poly). Such a device is described in detail in U.S. Pat. Nos. 4,823,181 and 4,881,114. For this category of antifuse, contacts have to be made to the N+ diffusion layer and the upper electrode from two corresponding conductive metal lines.
There are known problems with substrate-level antifuses. Some of the suggested dielectric materials require complex manufacturing techniques and have low reliability during programming. Some programmed antifuses may have a finite resistance on the order of several hundred to several thousand ohms which may render them relatively unsuitable for use in high speed circuits, and also result in high power consumption when a large number of circuits are switching simultaneously. Further, to maintain reliable operation at commercially acceptable voltages, proposed antifuse material layers are typically thin enough to produce a relatively high capacitance. This can place a limit on device operating speed because antifuses on a single line act as capacitors linked in parallel, such that the sum of the individual capacitances of the unprogrammed antifuses can slow data signals undesirably. Finally, substrate antifuses consume a lot of chip area.
A second type of antifuse, referred to as a metal-to-metal antifuse has a first metal layer disposed above and insulated from a semiconductor substrate as its lower electrode, a second metal layer as its upper electrode, and an antifuse material layer sandwiched between the first and second layers of metal. The antifuse material layer may be accompanied by one or more barrier metal layers separating it from lower and upper metal interconnect layers. Numerous structures for metal-to-metal antifuses are known in the art. Illustrative and non-exhaustive examples of metal-to-metal antifuses are shown in U.S. Pat. No. 5,272,101 to Forouhi et al.
The resistance of a programmed metal-to-metal antifuse is typically much lower than a programmed substrate level antifuse. During programming of a metal-to-metal antifuse, the metallization layers in the vicinity of the antifuse, the antifuse material layer and a portion of the adjacent metallization layers will disrupt and/or melt, and a conductive link will form through the antifuse material layer due to metal from the adjacent metallization layer being drawn in and intermixed through mass transport and thermal driven material diffusion and chemical reaction which is specific for an a-Silicon metal-to-metal antifuse.
Metal-to-metal antifuses usually employ a layer of amorphous silicon as the antifuse material, however, they may also employ oxide and nitride layers either alone or in multilayer combinations, or in combinations with amorphous silicon. Examples of antifuses that have been suggested using one or more oxide or nitride layers as antifuse material layers include U.S. Pat. No. 4,543,594 to Mohsen et al., U.S. Pat. No. 4,823,181 to Mohsen et al., U.S. Pat. No. 4,899,205 to Hamdy et al. Examples of antifuses that have been suggested using amorphous silicon as an antifuse material layer, either by itself, or in combination with one or more oxide or nitride layers include U.S. Pat. No. 5,070,384 to McCollum et al., U.S. Pat. No. 5,171,715 to Husher et al., and U.S. Pat. No. 5,181,096 to Forouhi et al., U.S. Pat. No. 5,272,101 to Forouhi et al., and U.S. Pat. No. 5,196,724 to Gordon.
Antifuse capacitance, as described above, is also a problem for metal-to-metal antifuses. Amorphous silicon antifuses alleviate this problem by providing a relatively thick antifuse layer, however, amorphous silicon antifuses exhibit relatively high leakage currents. Another approach has been to form a leakage barrier between the electrodes and the amorphous silicon antifuse material. A thin layer of deposited silicon dioxide or silicon nitride has been used. If this layer is too thin, it will not be an effective barrier, and if it is too thick, it will appreciably raise the programming voltage of the antifuse.
It is known that a-Silicon metal-to-metal antifuses will exhibit, under specific conditions where excessive current is placed across a programmed antifuse, a phenomenon wherein the conductive links will open up or become non-conductive. This failure mode is commonly known as "read disturb" because an excessive parasitic current occurs during the read state of the antifuse.
One factor that contributes to read disturb is the presence of any significant quantity of aluminum in the antifuse conductive links due to electromigration of the aluminum. Metal Barrier layers which serve to block aluminum flow into the antifuse material layer of various materials and various thicknesses have been proposed. The barrier materials, between the aluminum and the amorphous silicon, provide essentially all of the conductive material forming the conductive filament in the programmed antifuse. An antifuse formed with such a barrier metal link material can tolerate more current and have a higher reliability than an antifuse formed without the barrier metal link material.
Another way to overcome this problem is to change the composition of the antifuse material. For example, an amorphous silicon antifuse layer may be replaced with another low-temperature dielectric, such as oxide, nitride, or combinations of oxide and nitride have lower leakage current and higher breakdown voltage. Therefore, to maintain the same breakdown voltage requirements, the thickness of the antifuse dielectric has to be reduced. However, reducing the thickness of the antifuse material layer results in an increase in the capacitance of the antifuse in its unprogrammed state. This increased capacitance has a negative impact on the product speed.
Other materials which are harder and denser than amorphous silicon, such as silicon carbide (SiC) and amorphous carbon have been proposed to replace amorphous silicon to reduce the read disturb phenomenon and other problems associated with amorphous silicon metal-to-metal antifuses. It is important to employ these materials at desired programming voltages, and with a minimum of capacitance.
Amorphous carbon has been shown to significantly address the read disturb phenomenon. One problem in employing amorphous carbon as the antifuse material layer has been that it can fail to adhere to a metal electrode. Adhesion of the layers in a thin film device typically occurs because there is either ionic bonding at the interface of the films, metallurgical bonding where a chemical reaction between the materials results in a new material, or mechanical adhesion where the adhesion is due to the deposited film hooking onto surface nooks and projections.
When materials in a thin film device do not adhere to one another, a "glue" layer must be employed. In an amorphous-carbon based antifuse device, the problem of finding a glue layer material is difficult because a suitable glue layer material must adhere to both the metal electrode and the amorphous-carbon antifuse material layer. Concurrently, the adhesion material of the glue layer employed should have minimal impact on the programming and capacitance characteristics of the antifuse.
One other characteristic that is common to prior-art antifuses is that they have typically been only one-time programmable, that is that the programming mechanism that creates the low-resistance connection between the two antifuse electrodes has been irreversible. Once the antifuse has been programmed it becomes a permanent low-resistance connection. Controllable reprogramming of antifuses has been an elusive goal.

Reprogrammable metal-to-metal antifuse employing carbon-containing antifuse material


A voltage multiplier includes input and output differential multiplying stages, first and second operational amplifiers, and first and second linear devices. An input voltage is received by an inverting input of the first operational amplifier via the first linear device. An output of the voltage multiplier is provided at an output of the second operational amplifier. When the voltage multiplier is disabled, the second linear device provides the input voltage a linear path to an inverting input of the second operational amplifier and, when the voltage multiplier is operational, the second linear device has negligible effect on the voltage multiplier.

Analog multipliers are known to provide multiplication of an input AC voltage or current. Multipliers generally include a pair of differential amplifier stages which receive their respective DC bias currents from a DC power supply via matched current mirrors and are controlled by independent DC current sources located between the common node of each respective differential amplifier stage and a return of the DC power supply. An operational amplifier is typically employed to provide simultaneous control of the pair of differential amplifier stages which subsequently results in multiplication of the input current with the DC currents provided by the current sources. To produce voltage multiplication, an input voltage is provided to the input of a current multiplier via a resistor that converts the input voltage to an input current. The input current is multiplied by the current multiplier and delivered to the output of the multiplier. The output current is subsequently re-converted back to a voltage via an output operational amplifier to effectively produce voltage multiplication of the input voltage.
Multipliers are commonly used in transmitter compressors and receiver expandors to enable companding of a communication signal transmitted over a radio frequency (RF) channel with limited dynamic range. The companding operation allows wide dynamic range communication signals to be transmitted over limited dynamic range RF channels without significant reduction in the communication signals' signal-to-noise ratios. Compressors reduce, or compress, the dynamic range of the communication signal by a fractional amount dependent upon the dynamic range of the RF channel. In a complementary manner, expandors expand the dynamic range of the received communication signal such that the dynamic range of the original, pre-compressed signal is restored. For example, suppose a communication signal with 100 dB of dynamic range is to be transmitted over an RF channel with a dynamic range of 30 dB. The communication signal would require a 4:1 compression to reduce its dynamic range to 25 dB prior to transmission over the 30 dB dynamic range channel. Upon reception, a 1:4 expansion of the received communication signal would be necessary to restore the original 100 dB of dynamic range.
In most modern medium and high tier wireless and wireline communication systems, companding is a standard system function; however, in low tier, lower cost systems, companding may be an optional system addition. To reduce equipment and service costs, companding may be excluded by system proprietors that are constructing a low tier system. Accordingly, in radios or radiotelephones to be utilized in these low tier systems, compressors and expandors must be removed or bypassed. Typically, to maintain synergy and commonality with the medium and high tier radios and radiotelephones, compressors and expandors are disabled and bypassed in their respective transmitters and receivers by removing the DC power from the multiplier and using analog switching circuitry to reroute the communication signal around the compressor or expandor. However, this switching circuitry requires a significant number of additional circuit components when implemented to bypass a discrete multiplier or a significant amount of additional silicon area when implemented to bypass a multiplier within an integrated circuit. The additional circuit components and silicon area often reduce reliability and limit functionality of the voltage multiplier with which they are associated.
Therefore, a need exists for a method and apparatus that provides a disabled voltage multiplier's input signal a path to the voltage multiplier's output without impacting functionality of the operational voltage multiplier and without introducing a significant number of circuit components or requiring a significant amount of silicon area in an integrated circuit.

Method and apparatus for providing a representation of an input voltage at a disabled voltage multiplier's output


According to an embodiment, an image forming apparatus includes an image forming unit that forms an image on a sheet. A heat source heats the sheet at a control temperature according to a job type. A storage unit includes a job queue that registers jobs in a received order. When a plurality of jobs that differ in the control temperature are registered in the job queue, a controller groups the jobs registered in the job queue into job groups according to the control temperature. The controller also changes an execution order of the job groups in the job queue into the ascending order of the control temperature of the heat source, and executes the jobs registered in the job queue according to the changed order.

In the past, there is an image forming apparatus capable of performing an image forming job by a decolorable toner, a non-decolorable image forming job by a non-decolorable toner, and an image decoloring job by a decolorable toner. The image forming job by the decolorable toner is a job of forming an image using a decolorable toner and thermally fixing the image onto a recording medium such as a sheet. The non-decolorable image forming job by the non-decolorable toner is a job of forming an image using a non-decolorable toner and thermally fixing the image onto a recording medium such as a sheet. The image decoloring job by the decolorable toner is a job of thermally decoloring an image fixed onto a recording medium such as a sheet using the decolorable toner. The image forming apparatus performs the image forming job by the decolorable toner, the non-decolorable image forming job by the non-decolorable toner, and the image decoloring job by the decolorable toner using the same heat source.
However, in the image forming apparatus, the respective jobs are performed at different control temperatures of the heat source. Thus, in the image forming apparatus, when a plurality of jobs to be executed are received, it is necessary to frequently change the temperature of the heat source when the respective jobs are executed. Thus, there is a problem in that a time to complete the jobs by the image forming apparatus gets longer.


A hydroelectric jack system, which is mounted on the underside of the vehicle. It comprises of two conventional double direction hydraulic jacks. The jack has a round flat plate which rests on the ground when jack is operated to lift the vehicle. It can be remotely operated using push button controls installed in the dashboard of the vehicle. It utilizes the existing hydraulic cylinder provided currently in the vehicle for their operation(s) e.g. the hydraulic systems to operate steering unit or any other devices. The jack system has safety checks—the electrical circuit of the hydroelectric jack does not operate till the emergency brake is applied. An auto lock system ensures the jack will not open accidentally. In case of a car, jack can be installed on to the floor beam inside the body. Jack is firmly placed in the specially designed hole of required diameter. Jack on both driver's and adjoining seat duly balances the weight of the car. The jack when fitted on to the floor beam works efficiently and without any hindrance to normal vehicle operation. It takes less time to raise the vehicle and to lower it after the work is accomplished. It is very safe and easy to use.

Presently, there are a number of different types of jacks being used to lift a vehicle.
A mechanical type of jack comprises of a power screw rotatably mounted in a housing, screw being fixed to a worm gear at one end, which is meshed with another screw coupled to a handle. A nut is screwed on to the power screw. A load support plate is integral with the nut. When handle is turned, it rotates the screw meshed with worm gear, thereby, rotating the worm gear. The worm gear, in turn, rotates the power screw, which is pivoted at two ends inside the housing. The nut screwed on the power screw moves vertically upward or downward, the load support plate integral with the nut moves with it. The support plate is positioned under the floor beam of the car to lift the car.
A manually operated hydraulic frame type jack system known to the industry comprised of a base, a pressure release valve, a lever, a hydraulic oil cylinder, a piston, a pair of pulling bars, a pair of links, a pair of pushing bars, a load-engaging head and a locking rod. The locking rod is inserted into and extended through the holes on the pushing bars to prevent unintentional lowering of the car jack and the car.
However, to date no hydraulic or hydroelectric jack system is known which can be mounted on the underside of the vehicle and can be operated remotely from the dashboard of a vehicle.
One of the drawbacks of the widely used manual jacks is that the jack has to be physically positioned, by hand, under the vehicle and the handle/lever is operated manually to lift the jack, thereby, lifting the vehicle. Other drawback of the presently used jacks is that it takes a long time, up to 15 to 30 minutes, to lift the vehicle and another 15–20 minutes to bring jack to original position, unbundled and finally store it.
Yet another drawback of the known jacks is that in inclement weather conditions like rain, scorching heat, muddy road conditions or in snow operating a jack causes discomfort to the operator.
The present invention could be comfortably fitted beneath the driver and the adjoining seat. It is provided with the mechanical lock system.

Vehicle-mounted hydro-electric jack system