The disclosure relates to antimicrobial peptides, pharmaceutical compositions comprising the peptides and to uses thereof for treatment or prevention of microbial, bacterial, fungal, viral and parasitic infection.

Antimicrobial Peptides (AMPs) are an essential component of the defense system of organisms throughout nature and offer protection against invading pathogens. AMPs do not target single defined molecular structures (epitopes), but act on the cell membrane, thus killing bacteria and fungi rapidly. Therefore, as opposed to conventional antibiotics, they are effective regardless of the metabolic activity of bacteria. In addition to their direct microbicidal activities, antimicrobial peptides are particularly attractive as certain peptides show multiple activities such as the regulation of the innate and adaptive immune systems, inflammation and wound healing, and additional antifungal, antiviral, antiparasitic and anticancerous activities. AMPs are quite diverse in sequence and secondary structure, but share some common properties. They are usually short (about 15 to 40 amino acids), cationic, amphipathic and exert their microbicidal effect mostly by compromising the bacterial membrane integrity. Interaction of AMPs with the anionic membrane surface of the target microbes leads to membrane permeabilization, cell lysis and death. It is generally accepted that the cytoplasmic membrane is the main target of most antimicrobial peptides, whereby accumulation of peptide in the membrane causes increased permeability and loss of barrier function, resulting in leakage of cytoplasmic components and cell death. Various molecular mechanisms for membrane permeabilization, some phenomenological and others more quantitative, have been proposed to explain the action of AMPs.
Experimental observations in model systems were mainly rationalized by the carpet or pore model (FIG. 1). In the carpet model, AMPs accumulate on the membrane surface oriented in a parallel fashion to the membrane, resulting in local membrane thinning and destabilization of the cell membrane leading to the release of intracellular content. However, there is compelling evidence that many AMPs also function in a detergent-like manner, by disrupting the packing and organization of the lipids in a nonspecific way (e.g., lipid clustering or segregation of polar and nonpolar groups of the lipids) or by inducing non-bilayer lipid aggregates. Moreover, some AMPs pass the cell membrane and interact with an intracellular target (FIG. 1), leading to loss of bacterial/fungal viability.
Clearly, the mode(s) of action of AMPs differ from those of conventional antibiotics, which often have simple targets, such as a unique epitope on the cell wall, or in the protein and RNA synthesis processes, allowing the pathogenic bacteria to develop resistance more rapidly. A major advantage of antimicrobial peptides over conventional antibiotics is that microbial resistance against these AMPs does not readily develop, most likely because these peptides—in contrast to conventional antibiotics—do not target single defined molecular structures (epitopes), but act on the cell membrane, thus killing bacteria and fungi within minutes. Thus, owing to the fast killing rate, being faster than the growth rate of bacteria, and nature of the target (substantial modification of the lipid composition would affect bacterial cell viability), resistance development is less likely. The emergence of mutants being resistant to AMPs has been determined by monitoring bacterial susceptibility after repeated sub-culturing in the presence of sub-inhibitory concentrations of the peptides, showing that the mutation rate was lower than other clinical antibiotics tested (e.g., ciprofloxacin and erythromycin). While the Minimal Inhibiting Concentration (MIC) of those antibiotics increased through all the subcultures (up to 64 times), the pressure of the peptides did not increase the MIC of the strain. Thus, in contrast to conventional antibiotics, resistance development in the presence of AMPs is less unlikely to occur. Furthermore, AMPs are fast-acting and biodegradable, which alleviates the current concern about residual antibiotics in the environment.
A wide variety of microbial infections are associated with biofilm formation, where microorganisms aggregate in a structured community in a self-produced polymeric matrix and adhere to a surface. An additional disadvantage of conventional antibiotics is that they do not ensure eradication of biofilm infections for the following reasons:
1) Insufficient penetration of conventional antibiotics into biofilms: The matrix in which bacteria are embedded protects them from external influences, such as antimicrobial substances. Most antibiotics are able to penetrate the biofilm, but their diffusion into the biofilm is slow so that they are inactivated before they can elicit their desired effect.
2) Low metabolic activity of bacteria: Biofilm-associated infections (BAI) are usually treated with vancomycin, often in combination with rifampicin. Although vancomycin is known to penetrate biofilms rather well—albeit at a significantly reduced transport rate—it poorly reduces the number of bacteria residing within the biofilm. Treatment with this antibiotic still has, therefore, a relatively high rate of failure, which can be explained by the low metabolic activity of bacteria in the biofilm, rendering the antibiotic ineffective.
3) Inactivation or degradation of the antibiotics: In BAI, antibiotics are mostly administered systemically. Therefore, they are prone to be removed from the bloodstream by renal clearance and degraded enzymatically in the blood and surrounding tissues. Enzymes (produced by bacteria) can directly destruct or modify the compound. These mechanisms actively reduce the concentration of drugs in the local environment. In biofilms, the low penetration poses an additional problem. Increasing the systemically administered concentration is not feasible due to the toxicity of high blood concentrations of antibiotics.
4) Bacteria have developed resistance: On top of the general increase of bacterial resistance to antibiotics, due to the decreased concentrations of antibiotics in the deeper layers, the risk that bacteria escape from antibiotic pressure is higher, which may lead to the survival of mutants that have increased resistance to these antibiotics. It has even been reported that suboptimal concentrations of antibiotics, including vancomycin, enhance biofilm formation. Moreover, repetitive administration of conventional antibiotics that have an insufficient effect promotes the development of antibiotic resistance.
5) Conventional antibiotics cause the release of pro-inflammatory microbial compounds: It has been shown that in BAI, peri-implant tissue is colonized by bacteria. To a large extent, this is due to the deregulation of the local immune response. This is the reason why, in many cases, the infection persists, even after replacement of the implant. Implantation of a biomaterial provokes an inflammatory response known as the "foreign body response," characterized by sequential influx of neutrophils, macrophages/monocytes and lymphocytes, followed by fusion of macrophages to multinucleated foreign body giant cells lining the biomaterial, novel fibroblast foiination and deposition of fibrin, leading to fibrosis/encapsulation of the foreign body. This sequence of events is highly regulated by molecular signals such as cytokines produced by the cell types involved. In case of infection, the host immune system is additionally triggered by molecules of the bacteria designated as "Pathogen-Associated Molecular Patterns" (PAMPs) recognized by specific receptors on the host cells, such as Toll-Like Receptors (TLRs). For example, bacterial peptidoglycan or lipopolysaccharide are recognized by TLR2 and TLR4, and are potent inducers of inflammatory responses. The activation of the immune system, both by the foreign body response and the bacterial infection, leads to an "over-the-top" reaction of the host immune system, leading to inflamed and disrupted tissue; in fact, providing the ideal environment for infection. Thus, the simultaneous activation by biomaterial and PAMPs can have deleterious effects on immune function and strongly increase susceptibility to infection.
At present, over 2,000 different antimicrobial peptide sequences are known (see, for instance, the World Wide Web at bbcm.univ.trieste.itttossi/search.htm), including cecropins, defensins, magainins and cathelicidins. Antimicrobial peptides and proteins are, for instance, described in:
U.S. Pat. No. 6,503,881, which discloses cationic peptides being an indolicidin analogue to be used as an antimicrobial peptide. The cationic peptides are derived from different species, including animals and plants.
U.S. Pat. No. 5,912,230, which discloses anti-fungal and anti-bacterial histatin-based peptides and methods for treatment of fungal and bacterial infections. The peptides are based on defined portions of the amino acid sequences of naturally occurring human histatins.
U.S. Pat. No. 5,717,064, which discloses methylated lysine-rich lytic peptides. The lytic peptides are tryptic digestion resistant and non-natural. The lytic peptides are suitable for in vivo administration.
U.S. Pat. No. 5,646,014, which discloses an antimicrobial peptide isolated from an antimicrobial fraction from silkworm hemolymph. The peptide exhibits antimicrobial activity against several bacterial strains, such as Escherichia coli, Staphylococcus aureus and Bacillus cereus.
WO 2004/016653, which discloses a peptide based on the 20 to 44 sequence of azurocidin. This peptide contains a loop structure linked by disulfide bridges.
U.S. Pat. No. 6,495,516, which discloses peptides based on the bactericidal 55 kDa protein bactericidal/permeability-increasing protein (BPI). The peptides exert antimicrobial effects as well as having LPS-neutralizing capacity.
WO 01/81578, which discloses numerous sequences encoding G-coupled protein receptor-related polypeptides, which may be used for numerous diseases.
WO 2004/067563 and WO 2005/040192, that disclose antimicrobial peptides based on peptide LL-37, the 37 C-terminal amino acid of the human cathelicidin.
Several AMPs, daptomycin and DPK-060, are currently in clinical use and/or development, e.g., polymyxin B, nisin, pexiganan, omiganan, iseganan. Further, up to phase 2 clinical trials have been performed for OP-145, a 24-amino acid peptide derived from the endogenous human cathelicidin antimicrobial peptide LL-37. OP-145 has been developed as an endotoxin-neutralizing antimicrobial peptide for the topical treatment of chronic otitis media. The currently known AMPs still have a few drawbacks. Although proteolytic degradation is beneficial for the environment (no residual AMPs), it prevents dynamic circulation. This is also caused by efficient peptide clearance. Also, the exact working mechanisms of AMPs remain largely unknown, so it is difficult to foresee their true applications and full potential. For example, it is often not known how AMPs interact with host cells to induce their effects. Therefore, the use of AMPs in clinical indications has been limited to topical applications.
Various bacteria, such as P. aeruginosa, E. faecalis, Proteus mirabilis, Streptococcus pyogenes and S. aureus all secrete proteases that degrade several antimicrobial peptides, such as the cathelicidin LL-37. Thus, protease-resistant antimicrobial peptides are advantageous from a therapeutical standpoint. Additionally, many of the antimicrobial peptides are not very efficient in challenging microorganisms such as bacteria, e.g., S. aureus and P. aeruginosa, frequently playing key roles in problematic pathogeneses, and need to be optimized to show an increased effect. Furthermore, due to potential lytic as well as other properties of AMPs against bacterial as well as mammalian membranes, one of the challenges in designing new peptides relies on developing AMPs with high specificity against microorganisms such as bacterial or fungal cells as compared to cellular membranes of the infected patient, i.e., a high therapeutic index (minimal hemolytic concentration/minimal antimicrobial activity; MHC/MEC).
Therefore, even though there are a relatively large number of antimicrobial peptides available today, there is still an increased need of new improved antimicrobial peptides, which can be used to counteract microbes, in particular, those that are resistant or tolerant against antibiotic agents and/or other antimicrobial agents. More importantly, there is a need for new antimicrobial peptides, which are non-allergenic when introduced into mammals such as human beings and that have high specificity against pathogenic microorganisms.

Academisch Ziekenhuis Leiden H.O.D.N. LUMC


Apparatus and method wherein body fluid to be treated flows proximate the surface of hepatocytes, the hepatocyte treatment of said body fluid substantially being made to occur across a layer of albumin concentration substantially greater than the concentration in said body fluid, the albumin layer being less than 3 microns.

Standard hemodialysis readily removes molecules (e.g., urea, raffinose, and potassium) in the body fluids which are free and not bound to other molecules like proteins. However, molecules such as jaundice-causing bilirubin and tranquilizer diazepam can not be removed from body fluids by standard hemodialysis because such molecules, though small, are bound to larger molecules like albumin (MW 69,000) and other proteins present in the body fluids: standard hemodialysis membranes are not permeable to albumin or large proteins because their pores are too tiny to admit them (FIG. 1); consequently molecules bound to large proteins remain stuck to the proteins and do not cross the membrane.
Some years ago, I invented a hybrid bio-artificial liver (U.S. patent Ser. No. 3,734,851) which works on the principle of flowing body fluid across one side of a semi-permeable membrane while keeping living liver cells (hepatocytes) proximate opposite side of said membrane. The membrane was physiologically semi-permeable in that the porosity allowed cross-over of molecules such as nutrients, toxins, proteins, and hepatocyte-secretory products, but prevented the cross-over of cells such as lymphocytes in the body fluid which can immunologically reject and kill the hepatocytes. Protein-bound toxins that are normally removed by the liver are also removed by my bio-artificial liver.
However, it became advantageous to use animal hepatocytes to treat human beings because animal hepatocytes are more readily available in quantity and are generally cheaper than human hepatocytes. Because it can be disadvantageous to allow contamination of human body fluid with animal proteins, it was felt best to use a semi-permeable membrane that would not allow the cross-over of proteins like albumin. It was discovered, however, that just any randomly selected membrane impervious to proteins would not work well in my bio-artificial liver because protein-bound toxins and substances in the body fluid remained unremoved. Work was done to figure out how to remove protein-bound substances while still using semi-permeable membrane that would not allow the cross-over of proteins.
While conducting extensive studies over many years on the removal of protein-bound substances by hepatocytes, some other interesting observations were made which became the bases of the invention described herein.
If one flows body fluid containing bilirubin molecules that are bound to albumin simply across the surface of hepatocytes extracted from liver tissue, one is surprised to find that the hepatocytes do not remove the bilirubin molecules as well as would be commonly expected. Those skilled in the art had always believed that one can create a bio-hybrid artificial liver by simply passing body fluid across the surfaces of hepatocytes which are isolated from liver and which are attached to a solid surface such as a membrane or beads. As the inventor of the first practical bio-artificial liver (cited above), I also believed the same, that the only ingredients needed for a fully functional bio-artificial liver were 1) live hepatocytes and 2) flowing body fluid that can feed nutrients and oxygen to the liver cells. While my bio-artificial liver of the aforementioned patent employed a semi-permeable membrane interposed between the flowing body fluid and the hepatocytes proximate the membrane, I had intended that the purpose of the membrane was purely to prevent the flowing body fluid from washing away the hepatocytes and to prevent immunologic cells in the body fluid from attacking and destroying the hepatocytes which may be invariably immunologically incompatible with the patient from which the body fluid flowed. For this reason, this semi-permeable membrane was exactly that: semi-permeable. I specified that the membrane be permeable to molecules but that it allows no immunologic cells to cross the pores of the membrane even over time slowly.
As other technologies developed so that 1) hepatocytes can be attached so securely to a solid surface so as to make their washing away no longer a problem, and 2) immunologic rejection of hepatocytes can be prevented without a semi-permeable membrane, I began to envision a bio-artificial liver using no semi-permeable membrane where hepatocytes would be bathed directly in the flowing body fluid. As we began to have success in growing human hepatocytes in culture, it became possible to consider a bio-artificial liver using no semi-permeable membrane which would be no longer necessary to block contamination of the treated body fluid with animal proteins from animal hepatocytes. It was expected that such a bio-artificial liver would be more efficient since molecules to be treated in the body fluid did not have the obstacle of having to cross the membrane to be taken up by the hepatocytes. In fact, others (B. Eiseman, L. Norton, N. C. Kralios, Surg. Gyn. Obst. 142:21-28, Jan. 1976; J. Uchino, et al. Proc. Am. Soc. Artif. Intern. Organs 34:972-977, 1988; K. Yanagi, et al. Proc. Am. Soc. Artif. Intern. Organs 36:M727-M729, 1990; T. Soyer et al. Annals of Surg. 177:393-401, 1973) proposed bio-artificial livers in which hepatocytes were directly bathed by flowing body fluids such as plasma from a continuous plasmapheresis device. Although it has not been publicly reported, nothing has yet come of bio-artificial livers not using an interposing semi-permeable membrane between hepatocytes and body fluid.
In light of the the discoveries I have been making over the past twenty years pertaining to the removal of protein-bound substances from plasma by hepatocytes, it is now not surprising that a bio-artificial liver does not efficiently remove protein-bound bilirubin if one simply flows body fluid across the surfaces of hepatocytes.
What I have learned mostly through experimentation is that it is necessary to interpose a layer of substantially increased albumin concentration between the flowing body fluid and the hepatocytes.

Methods and apparati for removing protein-bound molecules from body fluids


A network controller to allocate route targets for communication services provided on one or more corresponding virtual private networks, the route targets identifying service providers associated with the virtual private networks and the communication services provided by the corresponding virtual private networks.

Many service providers use layer 3 Multi-Protocol Label Switching (MPLS) Virtual Private Networks (VPNs) for customer-based communication. Since service providers often utilize many VPNs to support their networks, management and troubleshooting of these VPNs become increasingly critical.
According to MPLS VPN protocol, service providers assign or allocate route targets to corresponding VPNs. These route targets typically are formatted according to a 6-bit Autonomous System Number (ASN) that expresses a distinct inter-domain routing policy and a 32-bit decimal number representing a range of available values to be associated with route targets for any ASN. Another, less utilized, route target format includes a 32-bit Internet Protocol (IP) address associated with the service provider and a 16-bit decimal number representing a range of available values to be associated with route targets for any IP address.
Most of these service providers manage VPNs with a centralized management system, which, for example, allows for the provisioning and display the route targets on a console. This management technique allows network administrators the ability to receive and view a list of route targets corresponding to a service provider, however, it is often difficult, if not impossible, to manage VPNs or troubleshoot problems associated with one or more VPNs from the list of route targets without intensive computation and holistic knowledge of the centralized management system.

Allocation of route targets based on service offered


The object of the present invention is to provide a light-emitting device that emits phosphorescence with high efficiency. The light-emitting device of the present invention includes a host containing two kinds of dopants, wherein a dopant having a longer maximum-emission wavelength is doped in a low concentration and has a substituent.

1. Field of the Invention
The present invention relates to a light-emitting device containing a phosphorescent metal complex having an organic ligand, and a display apparatus including the light-emitting device.
2. Related Background Art
There has been known an organic electroluminescence device (hereinafter, also referred to as "organic EL device") as a light-emitting device.
The organic EL device has at least one organic layer provided between electrodes. An organic layer may have a multi-layer structure, for example, a three-layer structure including a hole transporting layer, a light-emitting layer, and an electron transporting layer, or a four-layer structure including a hole transporting layer, a light-emitting layer, an exciton diffusion blocking layer, and an electron transporting layer.
The hole transporting layer may be composed of α-NPD. The light-emitting layer may be composed of Alq3, CBP as a host doped with Ir(ppy)3 or CBP as a host doped with PtOEP. The exciton diffusion blocking layer may be composed of BCP. The respective compounds are listed below in full.    Alq3: aluminum-quinolinol complex    α-NPD: N4,N4′-Di-naphthalen-1-yl-N4,N4′-diphenyl-biphenyl-4,4′-diamine    CBP: 4,4′-N,N′-dicarbazole-biphenyl    BCP: 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline    PtOEP: platinum octaethylporphyrin complex    Ir(ppy)3: iridium-phenylpyridine complexThe structures of the above compounds except PtOEP are shown in FIG. 3.
Also, an electron transporting material includes oxadiazole derivatives.
Examples of an organic EL device making use of phosphorescence are reported in, for example, "Improved Energy Transfer in Electrophosphorescent Device" (D. F. O'Brien et al., Applied Physics Letters Vol. 74, No. 3, p. 422 (1999)) and "Very High-efficiency Green Organic Light-emitting Devices based on Electrophosphorescence" (M. A. Baldo et al., Applied Physics Letters Vol. 75, No. 1, p. 4 (1999)).
The technique of converting an excitation energy from triplet excitation to singlet excitation is disclosed by U.S. Pat. No. 6,310,361, Applied Physics Letters: 79, 7, 1045 (2001), and Nature: Vol. 403, 750 (2000).
Besides, Japanese Patent Application Laid-Open No. 2003-077674 discloses that an energy is converted from a triplet exciton to triplet excitation and light is emitted from the triplet excitation.
However, none of the above techniques offer a satisfactory device in terms of phosphorescence efficiency, device lifetime, and power consumption.

Light-emitting device and display apparatus


A single pass ROS system provides a plurality of latent images which may subsequently be developed in different colors. The ROS units are initially aligned so that each color image is precisely registered at the same relative position along the exposed area of a photoreceptor belt. The alignment is accomplished by forming a pair of opposed alignment apertures in the surface of the belt and detecting coincidence or lack of coincidence of signals generated by the beginning and end of each scan line. The skew correction is enabled by rotating an optical component in the ROS system to create the required rotation of the projected scan line so as to correct for the detected skew error caused primarily by belt conicity. Once the initial X and Y-axis alignments are complete, subsequent alignment is maintained through subsequent passes by checking the positions of the previously identified pixels as they advance past additional lead edge apertures formed in the process direction along the belt surface.

The present invention relates to registration of plural image exposures formed on a photoreceptor belt by a plurality of Raster Output Scanning (ROS) systems and, more particularly, to a method and apparatus for registering the image exposures in the process direction of the belt to form registered color images in a single pass.
In a single pass, color xerographic system, a plurality of ROS stations are positioned adjacent to a photoreceptor surface and selectively energized to create successive image exposures, one for each of the three basic colors. A fourth ROS station may be added if black images are to be created as well. Thus, each image area on the photoreceptor surface must make at least three passes relative to the transverse scan line formed by a modulated laser beam generated by the ROS system. Each image must be measured to within a 0.1 mm circle or within a tolerance of .+-.0.05 mm. Each color image must be registered in both the photoreceptor process direction (skew registration) and in the direction parallel to the process direction (referred to as the fast scan or transverse registration). Registration in the transverse direction of a single pass ROS system is known in the prior art and a preferred registration technique is disclosed in copending U.S. application Ser. No. 07/635,835 filed on Jan. 8, 1991, and assigned to the same assignee as the present invention. Contents of this application are hereby incorporated by reference.
The present invention is directed towards a method and apparatus for registering the color images in the process direction only by detecting deviations in the skew of the color images being formed with respect to one another and by controlling registration errors at the lead edge of the images.
FIG. 1 shows a prior art, single pass, ROS color printing system 8 having four ROS systems, 10, 12, 14, and 16. The system 8 includes a photoreceptor belt 18, driven in the process direction, indicated by the arrow 19. The length of the belt 18 is designed to accept an integral number of spaced image areas I.sub.1 -I.sub.n represented by dashed line rectangles in FIG. 1. Upstream of each image area is a charging station (not shown) which places a predetermined electrical charge on the surface of belt 18. As each of the image areas I.sub.1 -I.sub.n reaches a transverse line of scan, represented by lines 20a-20d, the area is progressively exposed on closely spaced transverse raster lines 22, shown with exaggerated longitudinal spacing on the image area I.sub.4 in FIG. 1. Each image area I.sub.1 -I.sub.n is exposed successively by ROS systems 10, 12, 14, 16. Downstream from each exposure station, a development station (not shown) develops the latent image formed in the preceding image area. A fully developed color image is then transferred to an output sheet. Details of charge and development xerographic stations in a multiple exposure single pass system are disclosed, for example, in U.S. Pat. No. 4,660,059, whose contents are hereby incorporated by reference. The charge, development, and transfer stations are conventional in the art. Each ROS system contains its own conventional scanning components, of which only two, the laser light source and the rotating polygon, are shown. The particular system 10 has a gas, or preferably, laser diode 10a, whose output is modulated by signals from control circuit 30 and optically processed to impinge on the facets of rotating polygon 10b. Each facet reflects the modulated incident laser beam as a scan line, which is focused at the photoreceptor surface. Control circuit 30 contains the circuit and logic modules which respond to input video data signals and other control and timing signals to operate the photoreceptor drive synchronously with the image exposure and to control the rotation of the polygon 10b by a motor (not shown). The other ROS systems 12, 14, 16, have their own associated laser diodes 12a, 14a, 16a, and polygons 12b, 14 b, 16b, respectively. In the system of FIG. 1, transverse alignment of each successive image exposure is obtained by providing horseshoe shaped sensors 36a, 36b, 36c, 36d, which cooperate with optical targets T1, T2, T3, T4, respectively, formed in the belt surface. Further details regarding transverse alignment registration are described in the aforementioned application Ser. No. 07/635,835. However, for this prior art system, a skew or process alignment must also be accomplished to ensure complete registration of the multiple image exposures.
One of the main causes of skew error is due to belt conicity in the photoreceptor belt. Belt conicity is created when the two ends of the photoreceptor sheet are welded together to form the belt, causing the two belt edges to be of slightly different lengths. Another factor is the "set" that the belt takes over the life of the belt due to lateral deviation in tension roll or steering roll forces. A third source of potential belt conicity is the machine warm-up difference in temperature gradients from machine front-to-back causing lateral distortion. A still further potential source of conicity is movement of the photoreceptor module during, for example, a jam clearance. Any of these might create a situation, referring to FIG. 1, wherein the leading edges of images I.sub.1, I.sub.2, I.sub.3, I.sub.4 would rotate as they translate from one position to the next. If images I.sub.2, I.sub.3, I.sub.4 are to be perfectly registered with image I.sub.1, the leading edges must not be parallel to each other but must accommodate the rotation induced by the conicity of the belt. Since the degree and direction of the conicity of the belt varies from belt to belt, each ROS system must be individually aligned to correct for the initial misregistration.
According to the present invention, a method and apparatus is provided for aligning ROS units in a single pass printing system, so that each ROS is aligned along the process or X-axis, so as to compensate for belt conicity and other registration errors. After this alignment, the images formed by each ROS will be in proper registration within the prescribed tolerances. The rotational alignment in the X-direction, also referred to as a skew alignment, is made by sensing exposure lines formed by each ROS through apertures which extend transversely and are at opposite ends of the photoreceptor belt.
The ends of each scan line of each ROS are sensed simultaneously, and, if the detected signals are not coincident in time, an error signal is generated and applied to a precision, linear actuator, such as a stepper motor, which, in turn, transfers the linear motion to one of the optical components of the ROS system. In a preferred embodiment, a folding mirror is selected to be movable by the actuator, so as to change the angle of the projected scan line to correct for a detected skew error. This skew registration is accomplished for the first ROS system and then is repeated for each of the ROS systems until all four leading edge exposures, 20a, 20b, 20c, 20d, are sensed through the two skew apertures in coincidence, ensuring process registration of the associated color images. More particularly, the present invention relates to an imaging system for forming multiple image exposure frames on a photoconductive member during a single pass including:
a photoreceptor belt adapted to accommodate the formation of an integral number of image exposure frames, said belt having a first and second alignment aperture on opposite sides of the belt width and outside of the exposure frame,
a plurality of Raster Output Scanners (ROS) units, each ROS unit associated with the formation of one of said image exposure frames, each ROS unit forming a plurality of projected scan lines in a fast scan (traverse) direction across the belt width, said scan lines beginning and ending at points outside of the image exposure frame,
first and second detecting means associated with each of said ROS units, said detecting means adapted to sense the projected scan lines when they become visible through said alignment apertures and to generate position signals indicative thereof, and
means for rotating said scan line to correct for process registration errors until the detected position signals from said first and second detecting means are concurrent.

Method and apparatus for image registration in a single pass ROS system


A data driver includes a first signal generating circuit for externally producing a start signal; a second signal generating circuit for externally producing a first clock signal; a third signal generating circuit for externally producing a load signal; a generator externally generating a source video signal having a frequency; and a single integrated circuit including: an m-bit register circuit for receiving the start signal corresponding to the first clock signal and outputting a latch clock signal, where m is an integer; a data latch circuit for latching and outputting at least two sets of three video signals corresponding to the source video signal, the data latch circuit receiving all of the video signals simultaneously, each of the video signals having n-bits of data, where n is an integer; a line latch circuit for latching the video signals from the data latch circuit corresponding to the latch clock signal from the shift register, the line latch circuit storing and outputting the video signal according to the load signal of the third signal generation circuit; a digital to analog converter circuit for converting the video signal from the line latch to an analog signal; and a data output circuit for outputting the analog signal from the digital to analog converter, where a frequency of the first clock signal is reduced by the number of sets of the three video signals as compared to a frequency of the source video signal.

1. Field of the Invention
The present invention relates to a driver, and more particularity, to a data driver for a liquid crystal display.
2. Discussion of the Related Art
Referring to FIG. 1, a general active matrix liquid crystal display includes a lower substrate on which gate lines G1-Gn, data lines D1-Dn, a thin film transistor for switching pixels, and a pixel electrode are arranged. An upper substrate has a color filter for displaying colors and a common electrode. A liquid crystal panel 1 has a liquid crystal filled between the two upper and lower substrates, and a gate driver 2 sequentially applies driving signals to respective gate lines G1-Gn of liquid crystal panel 1. A data driver 3 applies video data to respective data lines D1-Dn of liquid crystal panel 1.
In such a liquid crystal display, liquid crystal panel 1 is becoming larger and with higher resolution. In order to drive larger and higher-resolution liquid crystal displays, the driving frequency of respective drivers 2 and 3 becomes higher. However, it is difficult to develop a driver IC capable of directly driving such a high frequency. Even though the driver IC capable of directly driving the high frequency may be developed, direct driving is not feasible due to high-frequency EMI. For this reason, as shown in FIG. 2, a data driver is provided on both sides of liquid crystal panel 1 according to two separate even and odd lines so that the driving frequency is reduced by half.
In the liquid crystal display of FIG. 2, however, because the driver is formed on both sides, the area of the liquid crystal panel for displaying actual images becomes smaller in the overall liquid crystal display. This limits the obtaining of a large-sized screen. The data driver of the conventional liquid crystal display of FIG. 1 will be discussed with reference to FIG. 3.
The data driver of the conventional liquid crystal display includes an m-bit shift register 11 for shifting a source start pulse SSP by a source pulse clock SCL and outputting a latch clock. A data latch 12 latches and outputs three signals DA(n), DB(n), and DC(n) of display data by source clock SCL. A line conversion logic 14 converts the polarity for every horizontal period by an external POL signal for the purpose of inversion. A 3m-by-n-bit two-line latch 13 latches, by lines, all display data of one horizontal line output from data latch 12 by the latch clock output from shift register 11 according to an external load signal and the output of line conversion logic 14. A D/A converter 15 selects and outputs one voltage of 2.sup.n levels formed by an external reference voltage so as to convert the data output from line latch 13 into an analog signal to be applied to the liquid crystal. A data output circuit 16 amplifies the signal output from D/A converter 15 to a stable voltage having a sufficient driving capability and a less-deviation output voltage. The amplified signal is output to the liquid crystal.
The operation of the conventional data driver will be described below with reference to FIG. 4. First, shift register 11 receives source clock SCL and source start pulse SSP, and outputs m latch clocks SR01, SR02, SR03, . . . , and SR0m (m=64) sequentially to line latch 13. Source clock SCL is a clock signal of about 65 MHz in XGA. The R/L input is a shift right/left input that informs the mBIT shift register 11 to shift right or left.
Data latch 12 latches signals DA(n), DB(n), and DC(n) of the n-bit display data corresponding to the falling edge of source clock SCL, and outputs the latched result to line latch 13. Line latch 13 latches the n-bit display data latched to the falling edge of the source clock to 3m-by-n bit first line latch portion 13a by latch clocks SR01, SR02, SR03, . . . , and SR0m output from shift register 11. After one horizontal line of display data is stored, one line data is stored in second line latch portion 13b at one time by an external load signal LOAD. Simultaneously, the next line data is latched to first line latch portion 13a by latch clocks SR01, SR02, SR03, . . . , and SR0m output from shift register 11 in the same method as above. This operation is performed repeatedly.
The line data stored by line latch 13 is output to D/A converter 15. D/A converter 15 selects and outputs, from the 2.sup.n levels formed by an external reference voltage v.sub.REP in an internal decoder, one voltage corresponding to the line data input from line latch 13. Here, line conversion logic 14 converts the polarity for every line by the external POL signal to facilitate the inversion.
The analog signal selected and output from D/A converter 15 is applied and displayed to the liquid crystal as a stable voltage having a sufficient driving capability and less-deviation output voltage. The conventional data driver, however, has the following drawbacks.
With the trend of larger screens and higher resolution, the hardest obstacle in the application of liquid crystal displays to liquid crystal laptop computers and their monitors is the operation frequency (65 MHz for XGA and 107 MHz for EWS) in accordance with resolution. The operation frequency of the conventional IC data driver is 55 MHz at 5 V driving (40 MHz at 3.3 V). Hence, the driver cannot be driven directly. Even when a directly drivable driver IC is developed, high frequency EMI is involved, making the direct driving impossible.
An external line memory may be provided in the conventional data driver in order to reduce frequency into half through bisected driving or driving by ICS. In this case, however, the cost as well as the weight of the product increase due to the line memory. Accordingly, power consumption and volume are also increased.


A hidden pathway to a host is provided in an internetwork having an egress router coupled to the host. A selected port of the egress router is connected to the host as a hidden access port. A label table in the egress router is configured to associate the selected port with a predetermined label. Distribution of the predetermined label is restricted to one or more controlled access points so that access to the hidden pathway is restricted to the controlled access points. The controlled access points may reside at the users themselves, but are preferably contained within proxy devices coupled to the internetwork using secure connections.

The present invention relates in general to data network communication using routers to provide a secure access channel to authorized users, and, more specifically, to maintaining availability of a host computer to high priority users during times that excessive traffic or a malfunction would otherwise disrupt access.
Communications within TCP/IP-based data networks is of the connectionless type. In order to send computer data signals from one computer to another, the data signals are fragmented into packets. Each network packet is tagged with routing information such as a source address (of the originating computer) and a destination address (of the recipient computer). In the event that the destination address is not in the local network, it must typically be passed through one or more routers in order to reach the local network of the recipient. At the receiving end, the packets are reassembled into the intended communication signals.
A router typically includes a plurality of ports or interfaces, with each port or interface being connected to a respective local network or to another router. When a router receives a particular packet at one port, the packet is examined in order to determine which of the other ports it should be sent out from (if any). The most basic method, one which is currently used to handle most network traffic within the Internet, depends on routing tables maintained in each router. The destination IP address is compared to information in a routing table which maps IP addresses in various remote networks to respective ports of the router. Since any particular destination is potentially reachable by many different paths through the interconnected routers making up the internetwork, least-cost algorithms are employed in each router to determine the next hop to an adjoining router that a packet should take toward its final destination. Routers exchange status information that is maintained in each router for use in determining the best routes.
A more recent type of routing employs label switching wherein a routing path is determined prior to any particular packet reaching the beginning of the path (i.e., the ingress router). Instead of using an IP address, a label for the label switched path (LSP) is added to the packets according to the predetermined series of routers in the path. The label is examined at each hop in the path and compared to information from a label table maintained in each router to determine the destination port. At the last router in the LSP (i.e., the egress router), routing typically reverts to use of a routing table based on IP addressing.
Label switching is typically used in creating virtual private networks (VPN's) and to create channels for providing class of service (CoS). A primary example of conventional label switching is multi-protocol label switching (MPLS). Due to the administrative requirements to create and maintain a label switched path, LSP's are typically limited to operation within a particular network domain which is administered by a single entity. Routing of packets between network domains is normally handled using standard IP routing. Routing of traffic between most users and publicly-oriented web sites (e.g., search engines, news and weather sites, and merchant sites) also depends almost entirely upon standard IP routing.
Network-originated traffic routed to a particular host computer within a respective local network (using either label switching or standard IP addressing) must pass through a router directly connected to that local network (i.e., a border router). There is typically only one or a small number of border routers through which the host can be reached from a remote network. Overloading (i.e., flooding) of the border router(s) or other malfunctions can prevent or greatly slow down attempted connections to the host. Such flooding can result from a distributed denial of service (DDoS) attack, for example, wherein an attacker breaks into a large number of individual computers connected to the internetwork and places an attack program on them. The attack programs simultaneously transmit bogus data traffic to the host victim, resulting in a flood of network traffic at the border router, or other shared network resource (sometimes the access link, or traffic shaper, or other shared resource), which overwhelms the processing capacity of the router and denies access of legitimate users to the host.


An image forming apparatus which enables easy management of proofs in a printing process. An image forming apparatus 299 is provided with a reader unit 50, a transfer charger 220, color sensors 274-1 to 274-4, a printer controlling unit 21. The reader unit 50 inputs image data for forming an image on a sheet having an RFID tag 701. The transfer charger 220 generates a transfer image for forming the image on the sheet based on the inputted image data. The color sensors 274-1 to 274-4 measure image formation conditions of the transfer image. The printer controlling unit 21 writes the measured image formation conditions into the RFID tag 701.

1. Field of the Invention
The present invention relates to an image forming apparatus which enables easy management of proofs in a printing process, a control method therefor, a control program and an image forming system.
2. Description of the Related Art
In a conventional printing process such as a process by an offset printing machine, a picture of a printed matter is reproduced in desired gradation by printing a plurality of sample outputs for proofing (proofs) for which adjustment parameters have been variously adjusted by a sample-for-proofing printing machine called a proofer, for one image data received from a requester, such as PostScript data (a PS file), and adjusting the ink coating thickness based on color information about a proof selected from among the proofs (see Japanese Laid-Open Patent Publication (Kokai) No. 2002-326343).
In general, a color mark called a profiling target, which is created with a specified density parameter, is printed on a proof, and a computer calculates the value read from the color mark by a calorimeter or the like and creates a device profile to be a color adjustment basis for a printing machine. The color information described above corresponds to this device profile.
The adjustment parameters related to image formation by a proofer at the time when the proof is outputted are required in the case where the proof is reprinted or in the case where fine adjustment of proof output is performed again and again. The adjustment parameters are printed on a margin part of the proof or described on a printed matter physically different from the proof. The above-described profiling target is commonly written on a proof itself. In some cases, a multitude of profiling targets are written on margins of a proof. In other cases, a proof for confirming the profiling target is printed separately from a proof for confirming the reproductivity of image data.
In the above proofer, a considerable number of combinations of proofs for which color balance, basic color density and the like have been finely adjusted based on image data received from a requester are outputted at a time. A proof to be adopted is determined by comparing and reviewing them. Currently, a so-called ink jet printer or an electrophotographic printer is used as a proofer. Such a printer makes it possible to easily perform fine adjustment of parameters such as density, color balance and a gradation correction table, and therefore, a device profile to be adopted for printing is determined by outputting a multitude of proofs for which these parameters have been finely adjusted variously and comparing output results.
However, in the method in which printing is managed by printing adjustment parameters of a proofer on a sheet different from a proof, an input mistake of an adjustment parameter by a person easily occurs, and it is not easy to certainly associate a multitude of outputted proofs and a multitude of adjustment parameters with one another.
In the method in which adjustment parameters of a proofer are written on a margin, it cannot be strictly said that a proof and a final output matter are the same data if a setting information image, such as characters, put on the margin is considered, and there is therefore a problem that it is difficult to grasp the image of a final output matter.
Furthermore, when the adjustment parameters of a proofer are reset, it is necessary to input a multitude of adjustment parameters. Therefore, it is conceivable that an input mistake by a person similar to the above frequently occurs.
Furthermore, the method in which a profiling target for creation of a device profile is created on a margin of a proof has a problem that it is difficult to grasp the image of a final output matter because the appearance of the proof is not the same as the final printed matter.
In the method in which a proof for confirming a profiling target is printed separately from a proof for confirming the reproductivity of image data, the association relation between the proof for confirming the reproductivity of image data and the proof for confirming a profiling target tends to unclear, and there is therefore a problem that no means for ensuring that a profiling target corresponding to a desired proof has been certainly converted to a device profile for a printing machine exists.
Since there are a multitude of adjustment parameters of a proofer, and it requires skilled work and much work time to output a multitude of proofs by efficiently changing the settings. Further, since the adjustment parameters of a proofer or the device profile for printing machine described above include a multitude of parameters, the amount of data of a setting table or the like increases to collectively manage the parameters. Hereinafter, as more fine printing quality is required, it is required to efficiently manage the increasing data.

Image forming apparatus, control method therefor, control program and image forming system


A single crystal semiconductor separated from a single crystal semiconductor substrate is formed partly over a supporting substrate with a buffer layer provided therebetween. The single crystal semiconductor is separated from the single crystal semiconductor substrate by irradiation with accelerated ions, formation of a fragile layer by the ion irradiation, and heat treatment. A non-single crystal semiconductor layer is formed over the single crystal semiconductor and irradiated with a laser beam to be crystallized, whereby an SOI substrate is manufactured.

1. Field of the Invention
The present invention relates to a method for manufacturing a silicon on insulator (SOI) substrate in which a crystalline semiconductor layer is provided on an insulating surface and a method for manufacturing a semiconductor device.
Note that the semiconductor device in this specification indicates all the devices that operate by utilizing semiconductor characteristics. For example, electro-optic devices (including liquid crystal display devices and EL display devices), semiconductor circuits, and electronic devices are all included in the category of the semiconductor device.
2. Description of the Related Art
Flat-panel television sets to which thin display devices such as liquid crystal display devices and plasma display devices are applied have been widely used. In recent years, EL television sets to which electroluminescence (hereinafter also referred to as EL) display devices are applied have been developed. One of the main technologies thereof is a thin film transistor. By improving performance of a thin film transistor and reducing manufacturing cost thereof, thin display devices having excellent display performance can be provided inexpensively. In the market of the thin display device (a flat-panel display) where various companies are competing with each other, improvement in performance and cost reduction are essential to gain the ascendancy.
It is necessity that thin film transistors used for a flat-panel display is formed over an inexpensive and large-size substrate such as a glass substrate. In general, thin film transistors using amorphous silicon layers or polycrystalline silicon layers are formed. In terms of performance of a transistor, single crystal silicon is preferable; however, restrictions on a process, particularly restrictions on heat treatment temperature are severe in the case of employing a glass substrate.
On the basis of the above situation, methods for increasing the crystallinity of a semiconductor layer have been researched and developed in order to improve performance of a thin film transistor. As an example, there is a technique where amorphous silicon is irradiated with a laser beam to be polycrystallized. For example, in Patent Document 1, a technique is disclosed in which a high performance thin film transistor having a high quality polycrystal is obtained by scanning a laser beam aligned at an angle of crystal faces of a semiconductor layer.

Semiconductor Energy Laboratory Co., Ltd.


An enhanced ball grid array substrate package and method for manufacturing the same, where the substrate package includes a metal core having a first surface and a second surface opposite the first surface. The metal core further includes at least one cavity in which at least one integrated circuit is positioned. A dielectric layer is secured to the first surface of the metal core and includes at least one die cavity formed therein. Thereafter, a conductive seed layer is chemically deposited to exposed portions of the dielectric layer and the first surface of the metal core. Adjacent to the conductive seed layer, a circuit is electrolytically and selectively formed within a first circuit pattern.

The present invention relates to an integrated circuit package and, more particularly, to a ball grid array substrate package that is sequentially built and accommodates at least one integrated circuit.
There have been several generations of integrated circuit packages used to mount an integrated circuit. Recently, development of one such generation known as a ball grid array substrate package has exhibited several advantages over earlier generations of integrated circuit packages. Earlier generations of integrated circuit packages include ceramic and metal packaging, each of which are expensive and difficult to manufacture. The advantages associated with the ball grid array substrate package generally include: (1) eliminating the need to route package leads to the outer edges of the integrated circuit package; (2) permitting smaller packages and closer spacing of packages mounted to the same printed circuit board; and (3) shortening interconnect lengths to improve electrical performance.
Ball grid array substrate packages have been further classified into either enhanced ball grid arrays or micro ball grid arrays. The micro ball grid arrays are typically used with integrated circuits having a relatively low number of inputs and outputs. Such integrated chips include various memory chips. Typically the micro ball grid array is constructed as a single layer of tape having dimensions similar to that of the integrated chip.
The enhanced ball grid arrays are used with integrated circuits that generate more than 3 watts or have a relatively large number of inputs and outputs. A relatively large number of inputs and outputs is in the range 300 through 1000. The integrated circuits used in conjunction with enhanced ball grid arrays are generally application specific integrated circuits, digital signal processors or microprocessors.
An example of an enhanced ball grid array package is briefly discussed below and disclosed in U.S. Pat. No. 5,583,378. The ""378 patent issued to Marrs et al. on Dec. 10, 1996, and is assigned to Amkor Electronics, Inc.
Referring to FIG. 1, there is illustrated a cross-sectional view of an enhanced ball grid array package 100, an integrated circuit 102 and a thermal conductor 104 all of which are described in the ""378 patent. The thermal conductor 104 is typically a thin layer (i.e. 0.127 to 0.254 millimeters thick) of copper that covers the entire outer surface of the enhanced ball grid array package 100.
The thermal conductor 104 is attached to an interconnection substrate 106 by an adhesive layer 108. The interconnection substrate 106 is a multi-layered printed circuit board laminate having a well region 110 in which the integrated circuit 102 is positioned. The integrated circuit 102 may be directly attached to a surface of the thermal conductor 104 or have an optional adhesive layer 112 located therebetween.
The interconnection substrate 106 is alternately composed of at least one insulating layer 114 and at least one conductive trace layer 116 manufactured by well known methods. The number of insulating layers 114 and conductive trace layers 116 depends on the type of integrated circuit 102, the electrical design requirements, and the number of circuit interconnections required. Insulating layers 114 and conductive trace layers 116 are laminated together with epoxy resin. Conductive vias or plated through-holes 118 are then drilled or laser ablated, and plated to form conductors for electrical connections between multiple conductive trace layers 116.
A soldermask layer 120 is applied over the outermost conductive trace layer 116 and functions as an insulator. The soldermask layer 120 further includes a plurality of electrical contacts 122 that are formed by creating selective openings in the soldermask layer 120. The electrical contacts 122 are typically plated with nickel and gold and are electrically connected to the integrated circuit 102. The connections between the electrical contacts 122 and the integrated circuit 102 start with the electrical contacts that are connected by the conductive vias 118 to various conductive trace layers 116, thereafter, a plurality of bond wires 124 connect the conductive trace layers to the integrated circuit.
A plurality of solder balls 126 are attached to the electrical contacts 122 such that the enhanced ball grid array package 100 can electrically communicate with a larger electronic system such as a printed circuit mother board (not shown).
As described earlier, the integrated circuit 102 is positioned in the well region 110 which may be filled to a predetermined level with an insulating encapsulant material 128. The insulating encapsulant material 128 is typically an epoxy based plastic resin that functions to protect the integrated circuit 102 and the plurality of bond wires 124 from the outside environment.
Low yield and high manufacturing costs are disadvantages associated with the current enhanced ball grid array package 100, because glass reinforced epoxy laminate is used in the interconnection substrate 106. In addition, the current enhanced ball grid array package 100 is highly susceptible to problems during the manufacturing process such as warpage, cosmetic defects, and unreliable application of nickel and gold onto the electrical contacts 122.
Furthermore, the application of nickel and gold to the electrical contacts 122 requires a bussing network that utilizes valuable space located externally of the interconnection substrate 106. The bussing network also requires that the solder balls 126 be coated with gold, where a problem may occur when using dissimilar metals in connecting the enhanced ball grid array 100 to the printed circuit mother board that has connections typically manufactured from copper.
Accordingly there is a need for a new generation of ball grid array substrate packages that are constructed by a manufacturing process using sequential build technology. There is also a requirement to position at least one integrated circuit within a corresponding cavity formed within a metal core of the ball grid array substrate packages. These and other needs are satisfied by the ball grid array substrate package of the present invention.
The present invention is an enhanced substrate package suitable for use with a ball grid array and a method for manufacturing the same, wherein the substrate package includes a metal core having a first surface and a second surface opposite the first surface. The metal core further includes at least one cavity in which at least one integrated circuit is positioned. A dielectric layer is secured to the first surface of the metal core and includes a die cavity formed therein. Thereafter, a conductive seed layer is chemically deposited to exposed portions of the dielectric layer and the first surface of the metal core. Adjacent to the conductive seed layer, a circuit is electrolytically and selectively formed within a first circuit pattern. An electrically resistive soldermask layer may be disposed on the dielectric layer and the circuit.
According to one aspect of the invention, the first surface has an adhesion promoting electrically conductive surface layer which permits the dielectric layer to be directly attached to the core without the need for an adhesive.
According to another aspect of the invention, the dielectric layer has a outer recessed edge located along at least a portion of an outer perimeter of the metal core and/or an inner recessed edge located along at least a portion of an outer perimeter of said cavity. In each instance, the recessed edge can be covered by the soldermask layer and thereby protected from moisture ingress.
In addition, the substrate package of the invention may further include a via or through-hole extending through the thickness of the dielectric layer and the soldermask layer, and an electrical conductor extending through the via from an outer surface of the soldermask layer to an upper surface of the adhesion promoting layer, whereby the metal core can be grounded through the land.
According to the present invention there is provided a ball grid array substrate package manufactured using sequential build technology. Also in accordance with the present invention there is provided a ball grid array substrate package having a bonding area that is electrolytically and selectively formed over a portion of the circuit. In accordance with the present invention there is further provided a ball grid array substrate package the uses a differential etch process to remove a conductive seed layer. Further in accordance with the present invention there is provided a ball grid array substrate package having a bonding area selectively formed with an inner layer of nickel and an outer layer of gold in a predetermined location.
A process for manufacturing a ball grid array substrate according to the invention includes the steps of oxidizing a first surface of a metal core with an adhesion promoter, applying a dielectric to the first surface of the metal core, creating at least one die cavity within the dielectric to expose a portion of the first surface of the metal core, metallizing a conductive seed layer to an exposed portion of the dielectric layer and to at least an exposed portion of the first surface of the metal core, and electrolytically forming a circuit. Manufacturing improvements provided by the invention further include forming successive layers electrolytically without use of an adhesive, and a semi-additive metallization technique which applies a seed layer in a thickness sufficient to form a circuit thereon, then later removes the seed layer after the circuit has been formed. These and other aspects of the invention are discussed in the detailed description that follows.

Substrate for an integrated circuit package


An antimicrobial hydroalcoholic composition comprising hydroalcoholic solvent system comprising a lower alcohol and water in a weight ratio of at least about 50:50; a thickener system comprising at least one cationic or nonionic polymeric thickener that is solid at ambient temperature; and a secondary antimicrobial agent.

Control of nosocomial infection and exposure to infectious disease is of paramount concern to doctors, nurses, and clinicians who work in hospitals and surgery centers. One of the most effective methods for controlling infection is regimented hand disinfection before and possibly after each patient contact and particularly before and after each surgical procedure. Hand disinfection is generally accomplished using antimicrobial soaps with water. These soaps are usually formulated to include either povidone-iodine (usually 7.5% by weight) or chlorhexidine digluconate (CHG) (usually 2% or 4% by weight) as the active antimicrobial agent. In addition, these formulated soaps may contain surfactants and possibly low levels of humectants such as glycerin.
Hand disinfection is also accomplished using presurgical scrub replacements. These are used instead of the soap and water scrub. Presurgical scrub replacements ideally achieve bacterial kill equal to or better than a traditional soap and water scrub and in a shorter period of time. Additionally, they maintain or improve the skin's natural barrier to microbial and chemical contamination while providing acceptable tactile properties. Examples of presurgical scrub replacements include hydroalcoholic gels which generally include high levels of either ethanol or isopropanol as the disinfecting agent and also include a thickener and optionally a humectant (e.g., glycerin).
To date, thickeners used in hydroalcoholic gels have been based primarily on anionic polymers such as polyacrylic acid (sold under the tradename "CARBOPOL" by B F Goodrich Specialty Polymers and Chemicals Division of Cleveland, Ohio). See, for example, U.S. Pat. Nos. 4,956,170 (Lee) and 5,167,950 (Lins). These compositions are generally incompatible with cationic compounds such as chlorhexidine gluconate. There are a few reports of nonionic and cationic-polymeric thickeners being used as well. See, for example, U.S. Pat. No. 4,478,853 (Chausee) and International Publication No. WO 93/007903 (Deckner). These hydroalcoholic compositions have relatively low levels of alcohol, generally too low to provide rapid and effective antimicrobial activity.
U.S. Pat. No. 5,512,199 (Khan) discloses a hydroalcoholic wipe composition, incorporating nonionic and cationic polymeric emollients or humectants. These compositions have very low viscosities, too low to be used as a lotion. U.S. Pat. Nos. 4,915,934 (Tomlinson) and 4,981,698 (Tomlinson) provide hydroalcoholic biocidal compositions incorporating low molecular weight polymeric emollients such as polyglycerol and polyvinyl pyrrolidone. These polymers do not provide adequate thickening in hydroalcoholic lotions.
In other hydroalcoholic systems, such as those described in U.S. patent application Ser. Nos. 08/493,714 and 08/493,695 (both of which were filed on Jun. 22, 1995 and assigned to 3M Company), nonionic, anionic, cationic, or zwitterionic emulsifiers are used as thickeners for a wide range of concentrations of alcohol, without the need for a polymeric thickener such as polyacrylic acid. Although these systems are highly desirable, other high viscosity hydroalcoholic compositions useful as an antimicrobial lotion, for example, are still needed.

This patent is subject to a terminal disclaimer.

Hydroalcoholic compositions thickened using polymers


Methods and devices for removing entrapped bubbles or air in photovoltaic solar cells during a manufacturing process including an encapsulation process include, for example, wiggling the photovoltaic solar cells or pushing out air bubbles by applying vibrations and/or light pressures. Optional additional steps include liquid wetting or dispensing to or around the photovoltaic solar cell matrix for air releasing before the placement of the matrix into a liquid for encapsulation.

During a typical PV cell encapsulation process, air bubbles are formed in gaps between the glass, liquid, and cells. These bubbles result in voids in the finished PV cells, which, among other things, increase the probability of delamination in the PV cells, decrease the structural strength of the cells, and reduce the energy conversion capabilities of the cells. Prior art systems use vacuum devices to remove entrapped air bubbles between the encapsulating liquid film and the substrate. This requires high capital investments in vacuum chambers and other equipment, while also increasing the manufacturing time.

PV module cell matrix placement station and methods for removing air or bubbles during the manufacturing process


A method, apparatus, and computer program product for performing density biased buffer insertion in an integrated circuit design are provided. A tiled Steiner tree topology map is used in which density values are associated with each tile in the map. A directed acyclic graph (DAG) is created over an initial set of potential candidate points. A subset of the candidate points is selected by associating costs with each tile, and with each path or edge, to each tile. The total costs associated with placement of a buffer at a position within each tile are calculated. The lowest cost tile is then selected as a candidate position for buffer insertion. This process is then repeated to obtain an asymmetrically distributed set of candidate buffer insertion points between a source and a sink.

1. Technical Field
The present invention is directed to an improved method and apparatus for performing buffer insertion into an integrated circuit design. More specifically, the present invention is directed to a buffer insertion technique for efficiently locating candidate buffer insertion locations and managing logic design density within an integrated circuit, wherein the candidate buffer insertion locations are biased based on the relative density of one candidate location to other candidate locations.
2. Description of Related Art
It is now widely accepted that interconnect performance is becoming increasingly dominant over transistor and logic performance in the deep submicron regime. Buffer insertion is now a fundamental technology used in modern integrated circuit design methodologies. As gate delays decrease with increasing chip dimensions, however, the number of buffers required quickly rises. It is expected that close to 800,000 buffers will be required for 50 nanometer technologies. Thus, it is critical to automate the entire interconnect optimization process to efficiently achieve timing closure.
In addition to timing issues, managing the density of an integrated circuit design is becoming more problematic. The performance of a design highly depends on how packed the logic is geographically in the physical integrated circuit. If the logic is completely spread out, the design is routable but the performance suffers significantly. On the other hand, if the logic is packed, the design is not routable but would yield the best timing characteristics. A packed design is unsuitable for later design changes, such as the insertion of additional logic, such as a synthesized clock tree, since there is no room for the new logic.
Physical synthesis is now prominent in the automated design of blocks for use in high performance processors and Application Specific Integrated Circuits (ASICs). Physical synthesis is the process of concurrently optimizing placement, timing, power consumption, crosstalk effects, and the like, in an integrated circuit design. Physical synthesis helps to eliminate iterations between synthesis and place-and-route. Physical synthesis has the ability to repower gates, insert buffers, clone gates, and the like. Hence, the area of logic in the design remains fluid.
During physical synthesis, buffer insertion is called for to either optimize nets for delay or to fix nets due to electrical violations. One mechanism for performing buffer insertion on a fixed Steiner integrated circuit topology is the van Ginneken algorithm. Van Ginneken's dynamic programming algorithm, described in "Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay," Int'l Symposium on Circuits and Systems, 1990, pp. 865–868, which is hereby incorporated by reference, has become a classic in the field. Given a fixed Steiner tree topology, the van Ginneken algorithm finds the optimal buffer placement on the topology under an Elmore delay model for a single buffer type and simple gate delay model. The primary idea of van Ginneken is to choose a set of buffer candidate locations that lie on the Steiner topology at some uniformly fixed distance apart. Buffer insertion then proceeds for that particular set of candidates from sink to source.
One problem with the van Ginneken approach to buffer insertion is that buffers are inserted at uniformly placed points along a net. That is, there is no consideration for the density of the logic in the vicinity of the candidate point. Thus, buffers may be inserted into regions that are very densely packed with logic or into regions that are sparsely populated with logic, depending on the particular uniform spacing of the candidate points.
Thus, it would be beneficial to have a method and apparatus for performing density-biased buffer insertion in the design of an integrated circuit.

Method and apparatus for performing density-biased buffer insertion in an integrated circuit design

International Business Machines Corporation


A system and method for retrieval of similar images related to query images is provided. The query images are pre-processed for noise removal by selecting filtering technique based on noise variance estimation in each query image with respect to pre-set noise variance threshold value. The pre-processed query images are pre-classified for determining class one image identifier. Image types are generated from pre-processed query images for determining class two image identifier. Features are extracted from pre-classified query images based on class one image identifier and from generated images based on class two image identifier. The images similar to query images are retrieved which have features similar to extracted features of pre-classified query images and generated images. The retrieved similar images are ranked for determining most similar images with respect to query images. Similarity between query images and retrieved similar images is analyzed for re-ranking retrieved similar images.

Image retrieval is a process of searching or extracting relevant or similar images from large databases based on certain features of a query image. Automation of image retrieval solutions have reduced the otherwise time-consuming procedure. Conventionally, the image retrieval systems employ metadata based image retrieval (MBIR) or content based image retrieval (CBIR). These methods have constraints such as, but are not limited to, less precision, insufficient image processing, involves large amount of manual labor and time, lacks in capturing vital image features, irrelevant results, etc. Further, present image retrieval systems and methods do not provide a human level performance. Humans in general understand semantic meaning when looking at an image. Situations like a football match, a queue at the counter or a festival procession have a meaning which can be easily understood by humans.
Typically, existing image retrieval systems do not depict such capabilities which focus on human's visual interest and therefore do not provide results with precision. Further, image retrieval techniques retrieves images that are only specific to certain applications. The applications may include, but are not limited to, medical imaging, face matching (identification), brand name (Trademark) identification etc. Further, existing systems and methods cannot be utilized for image retrieval, if image, which is to be retrieved, relates to another application or domain type other than the application or domain type for which the image retrieval system is utilized. Further, existing systems does not perform well where entirely different entities in an image need to be identified for similar image retrieval. For example, situations wherein images containing several objects from various categories need to be identified.
Furthermore, it has been observed that if large scale variations, noise distortions, illumination changes, photometric changes, complex backgrounds, viewpoint changes, user interest and application requirements, occlusions occurs in a query image, therefore efficient image retrieval on such a large scale requires extensive training of network models for every possible application and present systems are not able to adapt quickly to such changes and therefore, provides inaccurate results.
In light of the aforementioned drawbacks, there is a need for a system and a method for automated semantic level image retrieval. There is a need for a system and a method for efficient automated search of similar images of different image type with increased accuracy and precision. There is a need for a system and method which is capable of being utilized for image retrieval of multiple applications and domains types. There is a need for a system and method for prioritizing object or category of interest and for automated identification of types and features of applications associated with an image. Furthermore, there is a need for a system and method that retrieves images which are noise distortion less, not blurry, robust to geometric variations, resistant to changes in illuminations and occlusion invariant.

System and a method for semantic level image retrieval

COGNIZANT TECHNOLOGY SOLUTIONS INDIA PVT. LTD.


A voltage regulator includes a regulation MOS transistor and an amplifier providing an output for driving a gate of the regulation MOS transistor. The amplifier drives the gate based upon a difference between a reference voltage and a feedback voltage. The voltage regulator may further include a circuit for making the amplifier switch to a standby mode with low current consumption when the difference between the supply voltage and the output voltage of the regulator is below a first threshold. This is done while maintaining, at the gate of the regulation transistor, a voltage that keeps the regulation transistor on. The present invention is particularly applicable to the management of power supplies in portable telephones.

The present invention relates to the field of electronic circuits, and, more particularly, to low drop-out (LDO) type linear voltage regulators, namely low serial voltage drop-out regulators.
Low drop-out (LDO) linear voltage regulators, such as low serial voltage drop-out regulators, may be used in several applications. In particular, such regulators may be used in mobile telephones to deliver a regulated voltage to radio transmission/reception circuits from a battery.
By way of example, a standard linear regulator 10 according to the prior art whose output delivers a regulated voltage Vout to a load Z is shown in FIG. 1. The load Z represents, for example, several radio circuits in a mobile telephone. The regulator 10 is electrically powered by a voltage Vbat delivered by a battery 1 and includes a differential amplifier 2 whose output drives a gate G of a P-channel metal oxide semiconductor (PMOS) regulation transistor 3. The transistor 3 is generally a transistor with low serial resistance in the conductive or on state (drain-source resistance RdsON), and it receives the voltage Vbat at its source S. A drain D of the transistor 3 is connected to the output of the regulator 10 and to the anode of a capacitor Cst for filtering and stabilizing the voltage Vout. This capacitor Cst is parallel-connected with the load Z.
The amplifier 2 receives a reference voltage Vref at its negative input and a feedback voltage Vfb at its positive output. The voltage Vfb is a fraction of the voltage Vout provided to the input of the amplifier 2 by a divider bridge including two resistors R1, R2.
Operation of a regulator of this kind, which is well known to those skilled in the art, includes modulation of the gate voltage Vg of the transistor 3 using the amplifier 2. This is done based upon a difference between the voltage Vfb and the reference voltage Vref, which the amplifier maintains at about 0 V. When the voltage Vg is smaller than the value Vbatxe2x88x92Vtp, the transistor 3 is on because its gate-source voltage Vgs is higher than the threshold voltage Vtp. When the voltage Vg is higher than Vbatxe2x88x92Vtp, the transistor is off. In a stabilized mode, the voltage Vout is regulated in the neighborhood of its nominal value Voutnom, which is equal to (R1+R2) Vref/R2.
A typical embodiment of the amplifier 2 according to the prior art is shown in FIG. 2. The amplifier 2 includes a differential stage 5 which receives the voltages Vref and Vfb as inputs and is biased by a current generator 6. The output of the differential stage 5 drives the gate of an N-channel MOS (NMOS) transistor 7 connected between the output node of the amplifier 2 and ground. The transistor 7 is biased at its drain D by a current generator 8. The output node of the amplifier is connected to the power supply voltage Vbat by a gate resistor Rg, which determines the gain of the amplifier and the maximum current that can be delivered at the output. Thus, according to the value of the signal delivered by the differential stage 5, the transistor 7 draws the output of the amplifier 2 to ground or the resistor Rg draws the output upwards, namely toward the voltage Vbat.
In an application such as supplying power in a mobile telephone, it is important that the regulation amplifier consume as little electricity as possible to maintain the charge of the battery. To this end, the gate resistance Rg is chosen such that it has a high value (e.g., 100 Kxcexa9) to limit the current flowing in the output stage. At the same time, the currents delivered by the generator 6, 8 are calibrated appropriately. Generally, the choice of the resistance Rg and of the bias currents is the result of a compromise between the need to efficiently drive the transistor 3, which generally has a high parasitic gate capacitance, and the need for low consumption.
Such consumption is typically in the range of 50 to 200 microamperes, i.e., it is acceptable per se when the battery is properly charged, and allows the regulator to work in a stabilized mode. Yet, the present invention is based on the assumption that this consumption is too high when the battery voltages Vbat become low and are below the nominal value Voutnom of the output voltage. Such a drop in the voltage Vbat below the nominal voltage Voutnom may be temporary and due to high current consumption, or it may be due to the fact that the battery has become discharged.
Turning now to FIGS. 3A, 3B, and 3C, according to observations and conclusions that form an integral part of the present invention, the passage of the voltage Vbat below the value Voutnom at an instant tA (FIG. 3A) results in the feedback voltage Vfb being lower than Vref at the input of the amplifier 2. This voltage is unbalanced and makes the gate voltage Vg drop to ground to compensate for the imbalance (FIG. 3B). The regulation transistor 3 is continually on, the voltage Vout becomes substantially equal to the voltage Vbat (FIG. 3), and the regulator 10 works in the follower mode. Since the output node of the amplifier 2 is grounded, it can be seen in FIG. 2 that the consumption in the gate resistor Rg is at the maximum.
Thus, the amplifier consumes current unnecessarily when the regulator works in the follower mode. This is because the regulation transistor is continually on and the output voltage Vout can no longer be regulated.
An object of the present invention is to provide a voltage regulator which overcomes the above drawback, for example, by switching the regulation amplifier into a low consumption standby mode while keeping the regulation transistor in the on state.
This and other objects, features, and advantages according to the present invention are provided by a, voltage regulator including a regulation MOS transistor and an amplifier whose output drives a gate of the regulation MOS transistor based upon a difference between a reference voltage and a feedback voltage. The voltage regulator may also include a circuit or means to make the amplifier change over into a standby mode with low current consumption when the difference between the supply voltage and the output voltage of the regulator is below a first threshold. This is done while keeping an electrical potential at the gate of the regulation MOS transistor at a value that keeps the regulation MOS transistor in the on state.
More specifically, the voltage regulator may include a comparator for comparing the supply voltage and the output voltage of the regulator and delivering a standby signal to the amplifier when the difference between the supply voltage and the output voltage of the regulator is below the first threshold. Also, the comparator provides a switch-over hysteresis and cancels the signal for putting the amplifier on standby when the difference between the supply voltage and the output voltage of the voltage regulator is higher than a second threshold, where the second threshold is higher than the first threshold.
Additionally, the amplifier may include a resistor connecting the output of the amplifier to the supply voltage. Further, a switch may be series-connected with the resistor and may be open when the amplifier is put on standby. Otherwise, this switch is closed. The amplifier may also include current sources that switch to low current mode when the amplifier is put on standby.
In addition, the amplifier may include a switch driven by a standby-setting signal to connect the gate of the regulation MOS transistor to an electrical potential making the regulation MOS transistor conductive when the amplifier is put on standby. The amplifier may also include a stage for biasing the gate of the regulation MOS transistor when the amplifier is on standby. The stage biases the gate with a voltage that is set so that the gate-source voltage of the regulation MOS transistor is close to the threshold voltage of the regulation MOS transistor. The electrical supply of the amplifier may be eliminated in the standby mode by a switch.
A mobile telephone according to the invention includes at least one radio circuit, a battery, and a voltage regulator as described above for powering the at least one radio circuit from the battery.
A method aspect of the invention is for managing the power available in a battery powering a load using a voltage regulator. The voltage regulator includes a regulation MOS transistor and an amplifier whose output drives a gate of the regulation transistor based upon a difference between the reference voltage and a feedback voltage. The method includes monitoring the difference between the supply voltage and the output voltage of the regulator and switching the amplifier to a standby mode providing low current consumption when the difference between the supply voltage and the output voltage of the regulator is below a first threshold. This is done while keeping the gate of the regulation MOS transistor at a potential that keeps the regulation MOS transistor in the on state.
More specifically, the amplifier may be reactivated when the difference between the supply voltage and the output voltage of the regulator is higher than a second threshold, where the second threshold is higher than the first threshold. The consumption of the amplifier may be reduced in standby mode by disconnecting the output node of the amplifier from the supply voltage, diminishing the current delivered by current sources internal to the amplifier, or disconnecting the supply voltage. Further, when the amplifier is put on standby, it is advantageous to apply a gate voltage to the gate of the regulation MOS transistor where the gate voltage is set so that the gate-source voltage of the regulation transistor is close to its threshold voltage.

Low electrical consumption voltage regulator


A food press includes upper and lower portions each having first and second ends, a plunger, a chamber, and a grate. The upper and lower portions are pivotally connected at their respective first ends. The plunger is disposed between the upper and lower portions. The chamber is disposed on the lower portion and includes an inlet and an outlet and is adapted to receive the plunger. The grate is pivotally connected to the lower portion and is disposed in the chamber in a user position and is disposed between the second ends of the upper and lower portions in a cleaning position.

1. Field of the Disclosure
The present disclosure is generally directed to a food press and, more particularly, to a garlic press that includes easy-to-operate and easy-to-clean features.
2. Description of Related Art
Garlic presses are known in the art. For example, U.S. Pat. No. 5,165,335 discloses a cross-ribbed garlic press. The cross-ribbed garlic press includes a grate in which perforations are created by inside and outside grooves running at angles to each other. A ram wall is provided with ridges which mate with the inside grooves of the grate. These grooves and ridges can be cleaned by scraping or wiping comb teeth along them. The comb teeth protrude from the far ends of the two levers, wherein one is attached to the ram, and the other is attached to the cup. The two parts are joined by a detachable hinge that allows the comb of one part to be engaged with the corrugations of the other.
In another example, U.S. Pat. No. 5,463,941 discloses a garlic press that does not require the clove to be separated and peeled, effecting the pressing operation without orienting the clove in the press. The garlic press permits a mechanism to automatically open when pressure is released for removal of the remains. Cleaning the parts is simple because of the open construction and ease of washing the parts when in an open position.
In yet another example, U.S. Pat. No. 6,505,548 discloses a garlic press having a pivotally-joined base and handle with an intermediate press plate pivoted therebetween and cooperating with the base in defining a receiving chamber selectively receiving an enlarged pressure block formed on the handle. The press plate includes a bladed cutter assembly engageable with the upper surface of the base for the severing of a base supported item. The base has an elongate hand-receiving opening formed therein to define an upper hand grip functioning in conjunction with the handle to manipulate the press, and a lower base support, below the opening, for a direct supporting engagement of the base on a support surface. This allows operation of the press by a direct downward pressure on the handle against a surface-supported base.
These and other garlic presses known in the art do, however, have inherent limitations and drawbacks that make the garlic presses difficult to use and clean.
While the method and device described herein are susceptible to various modifications and alternative constructions, certain illustrative embodiments thereof have been shown in the drawings and will be described below in detail. It should be understood, however, that there is no intention to limit the invention to the specific forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the disclosure as defined by the appended claims.


A storage device 1 includes: a case member 2; a lid member 3 configured to change between a closed position, an opened position, and a half-opened position; a fin member 4 configured to be pivotally supported on the second end portion 32 of the lid member 3; a cover member 5 configured to be positioned so as to be fixed relative to the case member 2, and to be disposed backward of the lid member 3 on the back side; and an urging member 80. When the lid member 3 changes between the half-opened position and the opened position, the projecting tooth portions 46 of the fin member 4 are in sliding contact with the recessed groove portions 55 of the cover member 5 by urging force of the urging member 80.

As a storage device, a storage device that includes a case member having an article storage portion that is opened upward, and a lid member that opens and closes the opening of the article storage portion, has been known. Ina standard storage device, the lid member changes, by, for example, sliding, rotating, or oscillating, between a closed position at which the opening of the article storage portion is closed and an opened position at which the opening thereof is opened. In recent years, a storage device in which a part of a lid member is disposed rearward of an article storage portion at the opened position in order to make the storage device compact, has also been suggested (for example, see JP2006290012(A)). Hereinafter, this type of storage device may be referred to as an inward-opening storage device, as appropriate.
JP2006290012(A) discloses an inward-opening storage device in which a door changes its state between an opened position and a closed position by rotating relative to a main body of a storage unit. Furthermore, the inward-opening storage device disclosed in JP2006290012(A) has a cover member disposed adjacent to the main body of the storage unit. The main body of the storage unit has a storage portion, and the door is disposed rearward of the storage portion at the opened position. More specifically, at this time, the door is disposed between the storage portion and the cover member. The door, the main body of the storage unit, and the storage portion in JP2006290012(A) correspond to a lid member, a case member, and an article storage portion, respectively, according to the present invention.


An arrangement for protecting data saved in a memory, in which arrangement at least one memory element and at least one data processing element are combined by means of required interfaces into a data processing entity. The arrangement comprises at least one scrambler (300, 410, 600) connected to the data processing entity, which scrambler (300, 410, 600) scrambles the form in which the data to be saved in the memory element is represented and/or descrambles data saved in the memory element into plain text when data is taken from the memory element for the use of the data processing elements.

1. Field of the Invention
The invention relates to a method and an arrangement for protecting information in a memory element.
2. Description of the Related Art
Many modern electronic devices, such as mobile telephones and microcomputers, contain integrated circuits that are also called microcircuits. These integrated circuits have enabled a significant increase in the performance of electronic devices during the recent years and decades. More and more components are compressed in integrated circuits, which enables an increase in the memory and data processing capacity. The continuous increase in the integration degree is mainly due to the diminished size of the components used in the microcircuits brought about by the advancement in manufacturing technology. Further, when the size of the electronic devices diminish, the integration degree of the microcircuits must be increased, in other words the number of components to be positioned in the same package must be increased. The intention can even be to integrate a whole functioning data processing system, for instance the central functions of a mobile phone, on the same chip. For the reasons of cost-effictiveness, the intention is to use as many prefabricated components as possible and to avoid client-specific components.
Electronic devices frequently have at least one, but usually more memory elements, in which data relevant for the function has been saved. This data is essential from the point of view of illegal copying, i.e. piracy, so that its protection for instance by encrypting is very important for the legal manufacturer of the device.
Further, if several ASIC (Application Specific Integrated Circuit) components are to be positioned in one microcircuit package along with memory elements, the central processing unit, i.e. the CPU, and other data processing elements, the protection of the data is problematic, because the protection must not disturb the internal functioning of the microcircuit, but it must provide sufficient protection against illegal copying of data.

Method and arrangement for protecting information