A method for forming dual damascene is provided. First, a first inter-metal dielectric layer and a stop layer is formed on a substrate, and then a first photoresist pattern including a via hole and a dummy metal line is patterned and the stop layer is etched for forming via hole. Next, a second inter-metal dielectric layer is deposited and then a second photoresist pattern is patterned for forming metal line trench by etching. Afterwards, a glue layer and a metal layer are blanketed and the dual damascene structure is formed by chemical mechanical polishing.

1. Field of the Invention
This invention relates in general to a method for forming dual damascene, and more specifically relates to a method for forming dual damascene by means of shallow dummy metal-line pattern.
2. Description of Related Art
In many high-integration semiconductor devices, there are more than two layers of interconnect metal layer, which are called multilevel interconnects for the purposes of forming wiring line structures. The process of multilevel interconnects usually provides a first or a lower layer structure of metal wiring and interconnect, then forms a second layer of metal wiring for connecting the first layer of metal wiring and interconnect. The first layer of metal wiring is polysilicon or metal layer and electrically connects to the drain/source of the device within the substrate.
As the sizes of the devices become smaller and smaller, the numbers of devices per unit area increase. As a result, the manufacture of low resist and high reliable interconnects to connect the devices is a significant problem for developing high quality integrated circuits in modern era.
At present, a method for forming metal interconnects, named dual damascene, provides a more stable and more progressive process to manufacture integrated circuits. Therefore, the dual damascene method has been widely applied to the VLSI process under 0.25 .mu.m, which can form high efficient and high stable structure of metal interconnects.
Referring to FIGS. 1A through 1E, they show a conventional process for forming dual damascene. First, as shown in FIG. 1A, a first inter-metal dielectrics 104 is formed on a semiconductor substrate 100 containing a first metal line 102, and the material of the first inter-metal dielectric layer 104 is silicon oxide (SiO.sub.2). Next, a stop layer 106, which is used to be an etch stop layer of a metal trench while etching the first inter-metal dielectric layer 104 thereafter, is formed on the first inter-metal dielectric layer 104 by means of chemical vapor deposition (CVD), and the material of the stop layer 106 is silicon nitride (SiNx) or similar matter. Next, a first photoresist pattern 108 of via hole is patterned on the stop layer 106, and then the stop layer 106 that is not protected by the first photoresist pattern 108 and the first inter-metal dielectric layer 104 are etched by anisotropic etching until a first opening 110 which is above the corresponding first metal line 102 is formed and the depth of the first opening is shallow.
Referring to FIG. 1B, after removing the first photoresist pattern 108, a second inter-metal dielectric layer 112 is formed on the whole stop layer 106 and filled inside the first opening 110. The material of the second inter-metal dielectric layer is the same as the first inter-metal dielectric layer 104, such as silicon oxide. Referring to FIG. 1C, a second photoresist pattern 114 is patterned on the second inter-metal dielectric layer 112, then the second inter-metal dielectric layer 112 that is not protected by the second photoresist pattern 114, the stop layer 106, and the first inter-metal dielectric layer 104 are etched by anisotropic etching. Therefore, a second metal-line trench 116 is formed through the first opening 110 so that the surface of the first metal-line 102 is exposed and a via hole 118 is formed. Besides, a number of third metal-line trench 120 are formed at one side of the second metal-line trench 116, and the area where these third metal-line trench 120 is so-called high integration region of metal-line trench 121. It should be noticed that the bottom of the second metal-line trench 116 and the top of the via hole 118 are communicated, and the stop layer 106 is exposed to the bottoms of the third metal-line trenches 120.
Referring to FIG. 1D, after removing the second photoresist pattern 114, a glue layer 122 is blanketed on the surface of the second inter-metal dielectric layer 112 and along the side walls and bottoms of the second metal-line trench 116, via hole 118 and the third metal-line trenches 120. The material of the glue layer 122 is titanium, titanium nitride, tantalum or tantalum nitride for providing a better glue ability between materials of adjacent layers, and also has the function of barrier to prevent spiking between the silicon surface of the semiconductor substrate 100 and conductor deposited thereafter. Next, a metal layer 124 is formed on the glue layer 122 and filled inside the second metal-line trench 116, the via hole 118 and the third metal-line trenches 120. With the help of chemical mechanical polishing (CMP), the surface of the metal layer 124 and the glue layer 122 where are higher than the second inter-metal dielectric layer 112 is plannarized as shown in FIG. 1E, and then the metal filled inside the second metal-line trench 116, the via hole 118, the third metal-line trench 120 forms the second metal line 116a, the via hole 118a for connecting the first metal line 102 and the second metal line 106a, and the third metal lines 120a.
After polishing the metal layer 124 higher than the second dielectric layer 112, the glue layer 122 is then polished. However, the material of glue layer 122 is different the metal layer 124 so that it is hard to remove. If the area of the glue layer exposed to be polished is large, it needs much time to remove the glue layer, which causes over polishing effect so that the erosion of the metal line or dielectric layer occurs, and therefore the thickness of the metal line is reduced. For a wider metal lines spacing, the erosion problem is not serious. When the line spacing become smaller, especially under 0.18 .mu.m of modem technology, the erosion of the metal line causing by the over polishing becomes more serious. In addition to the thickness of the metal line being reduced, it also increases the resistance of the metal line and reduces the conductivity of the metal line.
As the forgoing description, another conventional method that uses dummy metal-line pattern is provided to prevent reducing the thickness and increasing the resistance of the metal line due to over polishing. FIGS. 2A to 2E show cross-sectional views for forming dual damascene by means of dummy metal-line pattern. Referring to FIG. 2A, a first inter-metal dielectric layer 204 and a stop layer are formed on a semiconductor substrate 200 containing a first metal line 202, wherein the first inter-metal dielectric layer 204 whose material is silicon oxide is formed on the substrate 200, and the stop layer 206 whose material is silicon nitride is formed on the first inter-metal dielectric layer 204. Next, a first photoresist pattern 208 of via hole is patterned on the stop layer 206, and then portion of the stop layer 206 and the first inter-metal dielectric layer 204 that are not protected by the first photoresist pattern 208 are etched with anisotropic etching.
Subsequently, as shown in FIG. 2B, after removing the first photoresist pattern 208, a second inter-metal dielectric layer 212 whose material is the same as the dielectric layer 204 such as silicon oxide is formed on the stop layer 206 and is filled inside the first opening 210. Afterwards, as shown in FIG. 2C, a second photoresist pattern 214 which includes a intensive metal-line region 221 and a dummy metal-line region 223 is patterned on the second inter-metal dielectric layer 212. Then, the second inter-metal dielectric layer 212 and the stop layer 206 that are not protected by the photoresist pattern 214 are etched until the stop layer 206 is etched slightly whereby a second metal-line trench 216 and via hole opening 218 above the first metal line 202, a number of third metal-line trenches 220 defined by the intensive metal-line region 221, and dummy metal-line trench 226 defined by the dummy metal-line region 223 are formed. Therefore, the bottom of the second metal-line trench 216 and the top of the via hole opening 218 are communicated and the surface of the first metal-line 202 is exposed to the bottom of the via hole opening 218. Besides, the third metal-line trenches 220 whose bottom are slightly below the surface of the stop layer 206 are located at one side of the second metal-line trench 216, and the dummy metal-line trenches 226 whose bottom are also slightly below the surface of the stop layer 206 are located at the other side of the second metal-line trench 216.
Referring to FIG. 2D, after removing the second photoresist pattern 214, a glue layer 222 whose material is titanium, titanium nitride, tantalum, or tantalum nitride for increasing the glue ability between different layers is blanketed on the surface of the second inter-metal dielectric layer 212 and along side walls of the second metal-line trench 216 and along the side walls and bottoms of the via hole 218, the third metal-line trenches 220 and the dummy metal-line trenches 226. In addition, the glue layer 222 also has the function serving as a barrier that prevents the spiking between the silicon surface of the substrate 200 and conductor deposited thereafter. Afterwards, a metal layer 224 is blanketed on the glue layer 222 and is filled inside the second metal-line trench 216, the via hole 218, the third metal-line trenches 220 and dummy metal-line trenches 226. Finally, as shown in FIG. 2E, with the help of chemical mechanical polishing (CMP), a portion of the glue layer 222 and metal layer 224 higher than the second inter-metal dielectric layer 212 is polished, and then a second metal line 216a, a via hole 218a, and a number of third metal lines 220a and dummy metal lines 226a are formed.
According to the forgoing description, because the dummy metal-line region 223a composing of number of dummy metal lines 226a decreases the area of the glue layer which has to be removed, the polishing time can be reduced. Therefore, the thickness of the metal line does not have to be reduced which increases the resistance of the metal line as compared with conventional method. However, the dummy metal lines 226a cause parasitic capacitances between conducting lines and reduce the operation speed of devices when current flows through the devices.
Conclusively, there are number of disadvantages of the conventional methods, which are described as following:
(1) Without the help of the dummy metal-line pattern to form a structure of dual damascene, the over polishing for metal line due to CMP causes the erosion of the metal line. Especially, if the width between metal lines is too narrow, the thickness of metal lines PA1 (2) With the help of the dummy metal-line pattern to form a structure of dual damascene, the thickness of the metal lines. However, if the device turns on, it will increase the parasitic capacitor between conducting lines, which decreases the operation speed of the device.

Method of forming a dual damascene with dummy metal lines


Embodiments of the present disclosure provide a method, a device and a computer program product of storage management. According to example implementations of the present disclosure, in response to data to be replicated from a first storage zone to a second storage zone, a utilization rate of resources associated with the replication is determined; the utilization rate of the resources is compared with a predetermined threshold utilization rate; and in response to the utilization rate of the resources being less than the threshold utilization rate, the replication of the data is initiated from the first storage zone to the second storage zone. Therefore, the present disclosure can automatically adjust replication behaviors for various scenarios, thereby realizing a more flexible data replication policy, and enabling more efficient use of various resources.

A data storage system, such as Elastic Cloud Storage (ECS), typically provides additional protection for user data by backing up the same in one or more storage zones. The backup of user data involves multiple types of data replication across a plurality of storage zones. At a higher level (i.e., macroscopically), each type of data replication has its own business logic. In contrast, at a lower level, in the current replication solution, when data are replicated from a source storage zone to a target storage zone, resource utilization (for example, processing resources of the source storage zone, storage resources of the target storage zone or communication resources between storage zones) associated with the replication is not taken into account. This reduces the data replication efficiency, affects user experience, for example, restricts the upload rate of the local data due to shortage of processing resources of the source storage zone, and wastes resources, such as bandwidth or the like, in some cases. Furthermore, the conventional data replication solution includes developing different logic architectures for different replication requirements (for example, types of replication), which is inefficient for a new replication requirement.

Data storage management devices using utilization rates and methods for data storage management using utilization rates


In a standard cell synthesizing step 101, a net list is synthesized from an RTL description, and an instance name list is formed which contrasts a register description portion with an instance name contained in the net list; in a simulation step 103, an operation simulation written by the RTL description is carried out; the toggle information among registers which is extracted in the simulation step 103 is recorded in a toggle storing step 104, a flip-flop-to-flip-flop toggle information database is constructed in which the recorded toggle information corresponds to a flip-flop-to-flip-flop instance name obtained from the instance name list in a mapping step 105; and in an electric power optimizing step 102, a physical designing operation for reducing power consumption is optimized by employing the net list, the flip-flop-to-flip-flop toggle information database, and a timing restriction.

1. Field of the Invention
The present invention is related to a lower power consumption designing method of a semiconductor integrated circuit.
2. Description of the Related Art
In connection with increases of circuit scales in semiconductor integrated circuits, increases of electric power consumed in these semiconductor integrated circuits may cause a problem. Therefore, low power consumption designing methods have been conventionally developed and carried out in order to reduce the power consumption. More specifically, since portable appliances have been recently popularized, it is a very important aspect that power consumption of semiconductor integrated circuits mounted on these portable appliances may be reduced as much as possible.
As low power consumption designing methods for semiconductor integrated circuits, such a conventional low power consumption designing method requires a repetition of layout designing operation, and therefore, may induce an increase in developing cost. In the conventional designing method, after a layout designing operation has been accomplished, magnitudes of currents flowing through respective circuit portions within the semiconductor integrated circuit are confirmed, and then, the layout is corrected in order to reduce power consumption.
In contrast to the above-described designing method, another conventional designing method has been conventionally carried out in which power consumption is estimated before a layout designing operation, and the estimated power consumption is reflected to the layout designing operation. Concretely speaking, a designing method disclosed in JP-A-9-246389 is carried out in order to reduce power consumption as follows: That is, a logic simulation of a semiconductor integrated circuit is carried out which should be designed; power consumption is estimated by totalizing toggle operation times of each of circuit portions; and a restriction condition in a layout designing operation is determined based upon the estimated power consumption.
Also, a designing method disclosed in JP-A-2002-318826 is performed as follows: That is, while an attention is paid to such a fact that power consumption as to two sorts of flip-flops having different operating characteristics is changed, depending upon data operating rates and input waveform transition times, such flip-flops are individually selected, the power consumption of which becomes low in response to a data operating rate and an input waveform transition time every logic path.
FIG. 9 is a flow chart for describing a conventional low power consumption designing method of a semiconductor integrated circuit. In FIG. 9, a semiconductor integrated circuit designing method is constituted by a logic synthesizing step 201, an arrangement synthesizing step 204, a clock tree synthesis step 207, and a wiring line optimizing step 208. In the respective stages of this conventional low power consumption designing method, the above-described electric power optimizing method is employed, and in order to perform this electric power optimizing method, uniform toggle information is applied to the respective circuit portions.
However, in the above-explained conventional low power consumption designing method, both the structural elements and the wiring line systems have been determined after the logic synthesizing operation, and thereafter, the logic simulation is carried out. As a consequence, there is such a problem that lengthy time is necessarily required until the toggle information is acquired.
Also, in order to shorten the time, such a designing method for applying the uniform toggle information has been employed. However, with respect to such uniform toggle information, an information amount is small and precision is low. As a result, there is another problem that such a low power consumption capable of achieving a maximum effect cannot be realized.

Low power consumption designing method of semiconductor integrated circuit

Matsushita Electric Industrial Co., Ltd.


In a disk array of the RAID constitution, a likelihood of occurrence of a failure is predicted from the number of times of error occurrence for each of disk drives #0 to #3 in a certain parity group. Two storage areas #0_UH and #2_LH of a half size, which are different in data stripes from each other, are selected from two disk drives #0 and #2 having a relatively high likelihood of occurrence of a failure, respectively, and the data thereof is copied to a spare disk #A (divided data copy). When the likelihood of occurrence of a failure of one disk drive #0 further increases, the remaining half storage area #OLH of the disk drive #0 is copied to the spare disk #A (dynamic sparing). Dynamic sparing time is reduced and a likelihood of data lost due to a multiple disk failure by employing the divided data copy processing.

The present invention relates to a disk array device having plural disk drives and spare disk drives provided with the RAID (Residential Array of Independent Disks) function, in which data is copied from plural disk drives to one or plural spare disk drives in parallel, and a control method for the same.
Conventionally, a disk array device is provided with spare disk drives, in addition to employment of the RAID function, to improve the reliability thereof. In such a disk array device, when trouble has occurred in one of the disk drives constituting the RAID configuration, data is recovered from the other disk drives constituting the RAID configuration and is copied to the spare disk drives (correction copy), whereby the disk array device is recovered from a degenerate operation of the RAID function to a normal access state. However, since the disk array device sometimes enters the degenerate operation at the time of data recovery, there are problems in the reliability and performance thereof. Thus, the reliability is improved by analyzing an error history of the disk drives to predict the likelihood of a failure and by copying data in disk drives having a high likelihood of a failure to spare disk drives before a failure occurs (an operation called dynamic sparing).
However, recently, disk drives tend to have a larger capacity and are often used in a high load environment. Thus, the time required for the above-mentioned correction copy and dynamic sparing operations is increased.
Therefore, there is higher likelihood of occurrence of a multiple disk failure for the following reason. For example, it is likely that a trouble frequently occurs in a copy source disk drive and a READ operation cannot be continued during a copying operation for carrying out dynamic sparing. In this case, the disk drive is blocked, and a data recovery operation (correction copy) is carried out for a parity group (i.e., ECC (error correcting code) group) to which the disk drive belongs. However, it is likely that a problem, such as a partial sector fault or hard disk blocking, will occur in another disk drive in the identical parity group during this correction copy operation. If such a multiple disk failure occurs, data will be lost.

Disk array device having spare disk drive and data sparing method


Contrast in an image is enhanced by mapping an input intensity value to an output intensity value in accordance with a mapping function. A mean intensity value of the image is determined. Co-ordinates of the mapping function are calculated in accordance with the mean intensity value and a plurality of predefined parameters. The mapping function is applied to the input intensity value for determining the output intensity, wherein the mapping function is generated dynamically for each image.

Image contrast is usually achieved by rearranging the distribution of gray levels in an image scene. Increasing the contrast of an image is accomplished by making the dark portions of the image darker and the light portions of the image lighter. The effect of redistributing the gray levels is often visually beneficial because redistribution of gray levels uses more of an available dynamic range of a black to white intensity spectrum. Often the redistribution of energy is performed with the aid of a non-linear function.
Many approaches have been devised to improve the contrast of an image. Histogram equalization is a method that has been used to alter the contrast of an image by attempting to redistribute the gray level energy in the image such that the output distribution is uniform. However, histogram equalization suffers from a serious drawback because the effects of full equalization are usually too severe to be visually pleasing. This method has some preferred uses such as in medical imaging, where colour balance is not always as important as accentuating gray level detail. In video and film processing, however, histogram equalization is not used because maintaining a proper proportion of gray level through the image spectrum is important.
More recently, adaptive histogram equalization has received much attention. The basic idea behind adaptive histogram equalization is to generate a histogram of pixel intensities in an image and normalize them to produce a cumulative density function (CDF). Then, an altered version of the CDF is used to map the intensity, or gray level, data in an image to change the contrast. Even more sophisticated methods use local histogram information and local image statistics on a region of the image in order to achieve the desired context-dependent level of contrast enhancement.
However, all of the state of the art solutions to the problem of contrast enhancement still have results that have room for improvement. Therefore, it desirable that to develop a system and a method for providing an image that is more visually pleasing than the original and can be readily implemented on a microprocessor.

System and method for dynamically enhanced color space


The present invention provides a therapeutic agent for acute liver failure containing a hepatocyte growth factor (HGF), particularly an agent for treating fulminant hepatitis or late onset hepatic failure or suppression of progression of acute liver failure without hepatic coma to fulminant hepatitis or late onset hepatic failure. The present invention also provides a method for evaluating the efficacy of HGF including measuring the amount of α-fetoprotein (liver regeneration biomarker) and/or soluble Fas (anti-apoptotic biomarker) in a sample obtained from a liver injury patient administered with HGF.

Acute liver failure (ALF) is a fatal clinical syndrome characterized by an abrupt loss of hepatocellular function, which causes coagulopathy, jaundice and encephalopathy. In our country, acute liver failure with a histological appearance of hepatitis is classified as fulminant hepatitis (FH) or late-onset hepatic failure (LOHF). Fulminant hepatitis is a disease with extremely poor prognosis, for which liver transplantation has solely been established as a treatment method that improves the lifesaving rate thereof. Due to the donor shortage and the like, however, the executing rate thereof is only just over 20%, and the lifesaving rate by a medical treatment is as low as 20-50%. Therefore, it is an urgent task to develop a new treatment method with verified effectiveness.
Hepatocyte growth factor (HGF) is a growth factor having a potent promoting effect on liver regeneration, which is isolated from the plasma of patients with fulminant hepatitis (e.g., see patent document 1). Since HGF has been found to have, in addition to a hepatocyte proliferative or regenerative action (e.g., see non-patent documents 1 and 2), a wide variety of physiological activities such as a hepatocyte-protective action (e.g., see non-patent documents 3-5) by anti-apoptosis, an anti-fibrotic action and the like, a treatment of hepatic failure by HGF is expected. Although the effectiveness has been confirmed in vitro and in animal models, the efficacy, safety and the like of HGF in the human body are still unclear. Particularly, the lifesaving effect in acute liver failure with extremely poor prognosis such as fulminant hepatitis and late onset hepatic failure, and whether HGF administration is effective for the prevention of acute liver failure associated with encephalopathy without coma from becoming fulminant cannot be predicted at all. In addition, a possibility of HGF administration causing side effects such as decreased blood pressures, renal toxicity and the like was suggested in preclinical safety tests. However, an administration protocol that avoids those side effects in clinical situations has not been established.
Moreover, a technique and an index for monitoring the efficacy of HGF, i.e., liver regeneration promoting action and anti-apoptotic action, in the human body have not been developed heretofore. In the animal experiment level, the liver regeneration promoting action of the recombinant human HGF has been appreciated in view of the increased liver weight and increased serum albumin value thereby (non-patent document 6). However, the evaluation based on an increase in the liver weight (liver volume) cannot provide a real-time evaluation of liver regeneration induction, since the time necessary for increasing the weight (volume) after the induction of liver regeneration is long. Moreover, the serum albumin value reflects improved liver synthesizability as the result of liver regeneration, and is not suitable as an index for liver regeneration per se.
α-Fetoprotein (AFP) is a glycoprotein with a molecular weight of 67 kDa, which is found in the human fetal serum, and is practically used as a serum immunological diagnosis marker for hepatocellular carcinoma. In animal disease models, AFP is expressed in immature hepatocytes such as liver progenitor cell, hepatoblast and the like, and clinically, it has been reported that the serum AFP value reflects liver regeneration and mildly increases in fulminant hepatitis and chronic hepatitis (non-patent document 7).
On the other hand, soluble Fas is a Fas present on a cell surface, which is cleaved and released into the blood, and binds to Fas ligand to antagonize the binding of Fas and Fas ligand on the cell surface, thus suppressing apoptosis.
In fulminant hepatitis, the blood HGF value important for the prediction of prognosis remarkably increases. However, since a correlation is not found between blood HGF value, and serum AFP value and soluble Fas value, there was no prediction on the utilizability of AFP and soluble Fas as an index (efficacy biomarker) for the treatment effect of exogenous HGF administration.

Acute hepatic insufficiency depressant and method for evaluating drug efficacy thereof


The invention concerns a closing device (1) for the removal of solid and/or liquid substances from housings, containers, bottles, or the like, which can be filled with a liquid or solid material, consisting of an air intake element (7), which in a manner allowing detachment closes an auxiliary opening of the housing, container, bottle, or the like, and a suction pipe connection (2) and/or a suction pipe (6), which traverse(s) this air intake element (7), whereby the air intake element (7) includes a pressure equalizing device having at least one membrane (5) made of a material which is impervious to liquids and/or solids but permeable by gases, and that the suction pipe connection (2) or suction pipe (6) is joined at its exterior wall to the air intake element (7) as a tight seal against gas and/or liquid.

In the case of containers from which substances are removed, such as for example, by a spray gun, the problem arises that the decrease in volume inside the container must be equalized by a stream of incoming air. To that end, the container must be opened at another place or must be equipped with an air intake valve. It is also possible for the closing device or spray gun to be equipped, for example, with an additional air intake pipe.
Considerable drawbacks are associated with these devices. Thus, in the case of containers bearing an additional opening, steps must be taken to seal it off during or after use. Air intake valves have the drawback that an additional and costly construction component must be used. It is possible for air intake pipes to clog during use, especially when utilization is interrupted, and thereafter they cannot be employed any more for further use.
The task of the present invention is, therefore, to create a closing device which overcomes the drawbacks inherent in the state of the art. In particular, the object is to create a closing device simple in design which consists of only a few components and can be easily assembled.
This and other purposes of the present invention will become apparent based on the teachings herein.

Combination ventilation unit and seal for spray heads of spray bottles


A method, system, application programming interface, computer system and computer program product to provide locks for controlling access to data by nodes in a multi-node system while minimizing the number of messages sent between nodes. Locks can be grouped into blocks of locks, and exclusive access to data protected by locks in a block of locks can be granted together to a block agent for a particular node. The block agent handles requests for access to the data on behalf of clients running on the respective node. The block agent sends a message to a block master running on another node only when a request is made for access to data to which the block agent has not already obtained access. Access can be granted to a block agent for an entire block or for a portion of a block of locks.

Information drives business. A hardware or software failure affecting a data center can cause days or even weeks of unplanned downtime and data loss that could threaten an organization's productivity. For businesses that increasingly depend on data and information for their day-to-day operations, this unplanned downtime can also hurt their reputations and bottom lines. Businesses are becoming increasingly aware of these costs and are taking measures to plan for and recover from hardware and software failures.
Most complex business applications are run not on a single computer system, but in a distributed system in which multiple computer systems, referred to as nodes, each contribute processing resources and perform different tasks. In such an environment, disruption due to hardware and software failures can be lessened or prevented using a strategy known as clustering. In a clustered environment, computer systems and storage devices are interconnected, typically at high speeds within a local data center, for the purpose of improving reliability, availability, serviceability, and/or performance via load balancing. Redundant interconnections between the computer systems are typically included as well, and the collection of computer systems, storage devices, and redundant interconnections is referred to herein as a cluster. In some implementations, the cluster appears to users as a single highly available system. Different types of clusters may be established to perform independent tasks, to manage diverse hardware architectures performing similar tasks, or when local and backup computer systems are far apart physically.
In some clustering environments, only one of the computer systems in the cluster provides processing resources with respect to a particular software application. In other clustering environments, processing for a single software application is distributed among nodes in the cluster to balance the processing load.
Within a single computer system, multiple threads executing a given software application may access and/or update the same data. The term 'thread' is used to describe the context in which a computer program is being executed. This context includes the program code, the data for execution of the program code, a stack, a program counter indicating a memory location from which the next instruction will come, and state information. Coordination is necessary to ensure that one thread does not read shared data at the same time that another thread is updating that data, thereby possibly resulting in data inconsistency depending upon the timing of the two operations. In clustering environments where processing for a given software application is "load balanced," threads that share data can be running on different nodes within a cluster.
Coordination between threads accessing shared data is often implemented using locks. Typically, a lock is software that protects a piece of shared data; for example, in a file system, a lock can protect a file or a disk block. In a distributed system, a lock can also protect shared "state" information distributed in memories of each node in the system, such as the online or offline status of a given software application. All shared data is protected by a lock, and locks are typically managed by a lock manager, which often provides an interface to be used by other application programs.
A lock is requested before the calling application program can access data protected by the lock. A calling application program can typically request an "exclusive" lock to write or update data protected by the lock or a "shared" lock to read data protected by the lock. If the calling application program is granted an exclusive lock, then the lock manager guarantees that the calling program is the only thread holding the lock. If the calling program is granted a shared lock, then other threads may also be holding shared locks on the data, but no other thread can hold an exclusive lock on that data.
The lock manager cannot always grant a lock request right away. Consider an example where one thread has an exclusive lock L on a given set of data, and a second thread requests shared access to the given set of data. The second thread's request cannot be granted until the first thread has released the exclusive lock on the given set of data.
A lock can be placed on data that are stored on a shared disk. Locks can also be placed on shared data stored in memory for each node, where the data must be consistent for all nodes in a cluster. For example, nodes in a cluster can share information indicating that a file system is mounted. A lock can be placed on the shared state information when the state of the file system changes from mounted to not mounted, or vice versa.
FIGS. 1 through 4 provide examples of prior art messaging used to implement locks for data sharing. FIG. 1 is a block diagram illustrating prior art initialization of a lock. Two nodes, node 110A and node 110B, share data 152 protected by a lock 150. Lock 150 is managed by lock manager 160, which includes a module on each of nodes 110A and 110B, respectively, lock agent 130 and lock master 140. In many environments, a single lock master exists for each lock, and the lock master resides on one of the nodes. In the example shown, lock master 140 resides on node 110B. Lock master 140 tracks the access levels for a given lock in use on all nodes. Lock master 140 also maintains a queue of unsatisfied locking requests, which lock master 140 grants as threads unlock the corresponding lock. Different locks may have lock masters on different nodes, and all nodes agree on which node masters a given lock.
Each node can have a program that handles access to data protected by each lock. In this example, lock agent 130, a module of lock manager 160, runs on node 110A to provide access to data 152 protected by lock 150. Node 110B may also include another lock agent (not shown) to handle locks for clients on node 110B. If lock agent 130 itself does not have the access level requested by a client, such as client 120, running on node 110A, lock agent 130 calls lock master 140 to request the desired access level for node 110A. Lock master 140 keeps track of the access levels, also referred to as lock levels, held by all of the lock agents, such as lock agent 130, on each node.
Initialization of a lock, such as lock 150, is initiated by a client, or thread, such as client 120 of node 110A. A client calls a lock agent, such as lock agent 130, for the lock protecting the data of interest, such as lock 150. In the embodiment shown in FIG. 1, initialization is performed before the client is ready to use the data and allows a lock agent to prepare for that client's use of the lock. For example, the lock agent may allocate data structures or perform other functions to prepare for the client's use of the lock.
In action 1.1, client 120 running on node 110A requests lock agent 130 to initialize lock 150 on data 152. In action 1.2, lock agent 130 sets up data structures necessary for client 120 to use data 152 protected by lock 150. No communication with lock master 140 is needed to set up the data structures, which are discussed further below with reference to FIG. 3. In action 1.3, lock agent 130 informs client 120 that lock 150 is initialized.
Subsequent requests to initialize locks from client 120 or other clients (not shown) on node 110A can be granted by lock agent 130 by performing actions such as actions 1.1, 1.2, and 1.3. In other embodiments, initializing a lock may include communication with a lock master, such as lock master 140.
FIG. 2 is a block diagram illustrating a prior art first request for access to data protected by a lock that has been initialized and grant of the first request in the environment of FIG. 1. In action 2.1, client 120 requests shared access to data 152 protected by lock 150, which was initialized as described with reference to FIG. 1 above. In action 2.2, lock agent 130 determines that access to lock 150 has not yet been granted to lock agent 130. In action 2.3, lock agent 130 requests shared access to data 152 protected by lock 150 from lock master 140 running on node 110B. Lock master 140 determines in action 2.4 that no other client is currently holding lock 150, and therefore that no contention exists for data 152 protected by lock 150. Contention indicates that other nodes already hold conflicting access levels for this lock. For example, if a node holds shared access to a lock, then no node can be granted exclusive access to data protected by the lock until the shared access is relinquished.
In action 2.5, lock master 140 grants shared access to data 152 protected by lock 150 to lock agent 130. Now that lock agent 130 has been granted shared access to data 152, lock agent can grant shared access to any client running on node 110A that wishes to read data 152. A grant of access to a lock agent, such as lock agent 130, can be viewed as a grant of access to data protected by the lock, here lock 150, corresponding to the lock agent, for the entire node on which the lock agent is running. Lock agent 130 handles requests for access by client processes running on its respective node, in this case, node 110A. In action 2.6, lock agent 130 grants shared access to data 152 protected by lock 150 to client 120.
As shown in FIG. 2, each time lock agent 130 does not have the level of access requested by a client, such as client 120, lock agent 130 sends a message to lock master 140. When a lock agent must communicate with a lock master in order to obtain access to data protected by a lock on behalf of a client, locking is referred to herein as being performed in accordance with a "normal" lock protocol, and the lock itself is referred to as a "normal" lock.
Messaging between nodes is very expensive when compared to normal instruction execution; for example, on a typical computer system, a program can execute 250,000 instructions in the time it takes to send, receive, and process a message. Communicating with other processes on the same node is much less expensive, and therefore it is desirable, when possible, to minimize messages between nodes in favor of communications between processes on the same node. Using lock agents, such as lock agent 130, helps to minimize messaging because the lock agent can grant the access level that the lock agent itself has been granted. However, when the lock agent has not been granted access, the lock agent/lock master scheme still requires significant messaging whenever the lock agent has not already been granted the access level desired and the lock master is running on a different node.
FIG. 3 is a block diagram illustrating a prior art first request for access to data protected by a lock with contention between nodes and a grant of the first request. FIG. 3 is shown in the environment of FIGS. 1 and 2. In action 3.1, client 120 requests exclusive access to data 152 protected by lock 150. In action 3.2, lock agent 130 determines that exclusive access to data 152 protected by lock 150 has not yet been granted to lock agent 130. In action 3.3, lock agent 130 requests exclusive access to data 152 protected by lock 150 from lock master 140 running on node 110B, in accordance with the normal lock protocol.
Lock master 140 determines in action 3.4 that data protected by lock 150 are currently held at a shared access level by lock agent 330 running on node 110C, in contrast to the finding in FIG. 2 that no contention was present. Because the data protected by lock 150 is currently held at a shared access level, exclusive access cannot be granted to lock agent 130. Lock master 140 has three options at this point: (1) wait until the client of lock agent 130 holding lock 150 releases lock 150; (2) grant shared access rather than exclusive access to lock agent 130; or (3) request lock agent 330 to release lock 150.
In this example, lock master 140 takes the third option, and in action 3.5, lock master 140 requests lock agent 330 to lower the access level with which lock agent 330 holds data 152 protected by lock 150. Lowering the access level with which a lock agent holds data protected by a lock is also referred to herein as "lowering the access level for the lock," and locks can be referred to as having an access level. Lowering the access level is also referred to herein as "releasing the access level" or releasing the lock. A request to lower the access level can also be referred to as a revocation request.
In response to the revocation request to lower the lock access level for lock 150, in action 3.6, lock agen 330 waits on clients on node 110C to finish using data 152 so that it can lower the access level of lock 150. In action 3.7, lock agent 330 sends a message indicating that the access level of lock 150 is lowered to a "no lock" access level. Lock master 140 records the fact that lock agent 330 no longer holds lock 150 in a data structure, which is described with reference to FIG. 4 below. No contention exists, which allows exclusive access to be available to lock agent 130.
In action 3.8, lock master 140 grants exclusive access to data 152 protected by lock 150 to lock agent 130. Now that lock agent 130 has exclusive access to data 152, lock agent can grant exclusive access to data 152 protected by lock 150 to client 120.
In this example, an additional message was sent by lock master 140 in action 3.5 between nodes to handle contention for data 152 between nodes 110A and 110B. The other two options described above, waiting until the client of the lock agent holding the lock has released the lock, and granting shared access rather than exclusive access, do not require lock master 140 to send additional messages to lock agent 330. Waiting until lock 150 is released would eliminate action 3.5, where lock master 140 requests lock agent 330 to revoke access to data 152 protected by lock 150. However, access to data 152 by client 120 would be delayed until lock agent 330 voluntarily releases lock 150 on data 152. Granting shared access instead of exclusive access would change actions 3.8 and 3.9 to grant shared rather than exclusive access, and would eliminate action 3.5. However, a grant of shared rather than exclusive access would not satisfy the need of client 120, possibly resulting in additional messaging for client 120 to obtain the access level needed.
FIG. 4 is an example of prior art data structures maintained by the lock agent and lock master of FIGS. 1 through 3. Lock agent 130 of FIG. 1 (not shown) maintains lock agent data structure 432 to track access levels granted to the node on which lock agent 130 resides, node 110A of FIG. 1 (not shown). For each lock, lock agent data structure 432 includes lock identifier 434, the current access level for this node 436, and state information 438. State information 438 enables lock agent 130 to manage multiple requests for the lock identified by lock identifier 434.
Lock master 140 of FIG. 1 (not shown) maintains lock master data structure 442 to track access levels granted to each node. In some embodiments, lock master 140 may track each lock request from each thread on every node, and the data structure in such an embodiment would track lock- and thread-level information. In this example, lock master data structure 442 includes lock identifier 444, access level for node X 446X, access level for node Y 446Y, and access level for node Z 446Z, and state information 448.
As illustrated in this example, communication to request and grant locks in a multi-node environment has heretofore been very expensive and significantly reduces time available for processing instructions. What is needed is a system that minimizes messaging between nodes, while allowing locks to be used to enable data sharing among multiple threads running on the nodes.

Block locking in a multi-node environment


Zinc oxide (ZnO) varistors containing vanadium oxide as the principal additive and one or more cobalt oxides and/or manganese oxides additives exhibit excellent nonlinear current-voltage characteristics. Preferably the varistor compositions are capable of being sintered at a temperature of from 900.degree. C. to 950.degree. C. The low-firing capability of the newly developed materials is attractive for the application in the multilayer chip varistor, because it can cofire with the silver (Ag) or palladium/silver (Pd/Ag) internal electrode instead of using the expensive palladium (Pd) or platinum (Pt) metal. With an appropriate combination of ZnO, vanadium oxide (V.sub.2 O.sub.5) and other oxide additives, a varistor sintered at 900.degree. C. for 2 hours is obtained with a nonlinear coefficient>50 and a leakage current<20 .mu.A/cm.sup.2.

1. Field of the Invention
The present invention relates to a zinc oxide (ZnO)--vanadium oxide varistors comprising a blend of metal oxide additives and having improved nonlinear current-voltage characteristics, more particularly to a ZnO--vanadium oxide varistor able to be sintered at a relatively low temperature and having a lower breakdown voltage and leakage current and a higher value of the nonlinear coefficient.
2. Description of the Prior Art
Varistors are resistors with resistance varying in voltage in a nonlinear relation. Varistors have high resistance and are good resistors when loaded with voltage below the critical voltage. The resistance of the varistor abruptly decreases and the electric current through the varistor will greatly increase when voltages are higher than the critical voltage. In other words, varistors possess the ability to absorb surges, reduce overload voltage to a safe level and prevent electric components from being damaged by surges.
As to the electric characteristic of varistors, the value of voltage (V) selected to give a 1 mA current through the varistor is called the breakdown voltage (V.sub.B). The leakage current (I.sub.L) means the electric current at the voltage of 0.8 V.sub.B. The breakdown characteristics of varistors are very important in application. The relationship between voltage and electric current is expressed by the equation of EQU I=k V.sup..alpha.
wherein I represents the electric current through the varistor, k is a constant, V represents the voltage applied across the varistor, and .alpha. is a nonlinear coefficient. Based on the above simple equation, the a value of the nonlinear coefficient can be determined by the values of the voltage and the electrical current.
The technique of producing zinc oxide varistor has been in development for several years. Bi.sub.2 O.sub.3 has been used as an elementary additive up to now. When ZnO and Bi.sub.2 O.sub.3 powders are sintered, Bi.sub.2 O.sub.3 will segregate at the ZnO boundaries as an intergranular phase and form an electronic conduction barrier between ZnO grains, so that the ZnO ceramics exhibit nonohmic behavior. Several other oxides are added into general commercial varistor products to enhance the nonohmic effect, such as to improve intergranular barriers and microstructure. The zinc oxide varistors produced by conventional methods of bulk ceramics have excellent nonlinear voltage (V)--current (I) characteristics. That is, based on the above equation of I=k V.sup..alpha., the nonlinear coefficient .alpha. is more than 50. The varistors are widely applied since the electrical stability and the ability to absorb surges are good.
Recently, electrical appliances gradually have become smaller and integrated circuits are frequently used. General bulk varistor cannot be directly applied because of high working voltages. In order to protect the integrated circuit elements from being damaged by surges, varistors with low working voltages are necessary, the multilayer chip varistors with low working voltages are particularly important. The advantages of the multilayer technique for producing varistors are for instance: (1) the volume of varistors is reduced for subsequent surface mount technology; and (2) the breakdown voltage ranges from several voltages to dozens of voltages simply by controlling the thickness of the ceramic layer. In addition, the design of the multilayer can achieve the purpose of increasing electrode area. As compared with other methods of producing low voltage varistor, such as thin foil method, thick film method, and seed grain method, multilayer method can produce in a large scale, have good reproducibility and higher surge absorption per volume.
Traditional ZnO--Bi.sub.2 O.sub.3 system varistors are obtained by sintering at a temperature above 1100.degree. C. The internal electrodes within the multilayer varistor should be the expensive palladium (Pd) or platinum (Pt) material due to their high melting point. However, it is noted that when the ZnO--Bi.sub.2 O.sub.3 system and the palladium internal electrode are sintered at high temperatures, Bi.sub.2 O.sub.3 and the palladium internal electrode produce a solid solution reaction and result in damage. In U.S. Pat. No. 4,290,041, Utsumi et al. uses borosilicate-lead-zinc (i.e. Pb--B--Zn--Si) glass as the principal additive to replace the original Bi.sub.2 O.sub.3 additive. But a high sintering temperature, for instance more than 1100.degree. C. is still necessary in Utsumi's method. Therefore, it is inevitable to use the expensive palladium or platinum material as internal electrodes which will keep the manufacturing cost high.
Based on the above description, the principal additives used in commercial varistors are classified into three series: bismuth based additives (Bi.sub.2 O.sub.3), praseodymium based additives (Pr.sub.6 O.sub.11) and borosilicate-lead-zinc (Pb--B--Zn--Si) glass. In order to solve the problems of the above mentioned three series, the present invention provides a vanadium based additive (V.sub.2 O.sub.5) used in ZnO varistors. The varistors of the present invention not only can be sintered at a lower temperature of 900.degree. C. due to the addition of V.sub.2 O.sub.5, but also have excellent nonlinear current-voltage characteristics by the incorporation of several metal oxides. Sintering at a relatively low temperature is important for applications because the ZnO--V.sub.2 O.sub.5 system can be cofired with a silver inner-electrode (m.p. 961.degree. C.) rather than using the expensive palladium or platinum material.

Zno varistor of low-temperature sintering ability


Porous ceramic catalyst supports or filters to be provided with catalyst coatings via oxide washcoating processes are pre-coated with polymer barrier layers to prevent washcoat nanoparticle intrusion into the microcracked and/or microporous surfaces of the ceramics, the barrier coatings being formed of hydrocarbon polymers that are soluble or dispersible in polar media, capable of forming neutral or hydrophilic surfaces on porous ceramic supports, and completely vaporizable at moderate washcoat stabilization or catalyst activation temperatures.

The present invention relates to processes for applying catalyst or catalyst support coatings onto ceramic supports. More particularly, the invention relates to methods for coating ceramic substrates with catalyst coatings wherein a pre-coating or passivation step is used to improve the properties of the catalyzed substrates, by reducing catalyst and/or support coating diffusion into the fine pore and microcrack structure the substrates.
To address tightening diesel engine emissions regulations being adopted in the United States and Europe, recent attention has focused on basic improvements in the design and performance of ceramic wall-flow honeycomb filters for treating diesel exhaust gases. Among other improvements, design changes allowing for the use of catalyst coatings to control hydrocarbon and/or nitrogen oxide emissions are being implemented. The goal is to develop an improved high-temperature-resistant, high-thermal-shock-resistant, low cost honeycomb soot filter compatible with advanced emissions control catalyst technologies that can replace current high-cost and/or uncatalyzed particulate filters.
Among the filter designs being developed for this application are refractory ceramic oxide filters offering improved resistance to high exhaust temperatures encountered during decarbonizing filter regeneration cycles, as well as to the thermal shock conditions arising during rapid filter heat-up and cool-down in the course of startup and regeneration. Examples of advanced cordierite and aluminum titanate compositions and honeycomb filter designs being developed for these applications are disclosed in U.S. Pat. No. 6,541,407 and in co-pending, commonly assigned U.S. patent applications Ser. No. 60/400,248 filed Jul. 31, 2002, 10/209,684 filed Jul. 31, 2002, and Ser. No. 10/098,711 filed Mar. 14, 2002. Among other materials that are candidates for refractory, catalyst-compatible ceramic particulate filters are the refractory alkali zirconium phosphates as well as low-expansion alkali aluminosilicates such as beta-eucryptite and pollucite. Many of these same compositions, and other microcracked ceramic materials such as the calcium aluminates, are being considered for use as flow-through catalyst supports for the control of nitrogen oxide (NOx) emissions from automotive and diesel engines
Advanced aluminum titanate ceramics are among the most promising candidates for use in diesel exhaust filter applications, meeting or exceeding most specifications for high melting point, high thermal capacity, and low thermal expansion. However, one difficulty with these and other porous ceramics intended to function as particulate filters is the need to maintain both high gas permeability and a low coefficient of thermal expansion throughout the processes involved in depositing catalysts on the filter walls. A general requirement is that a low average linear coefficient of thermal expansion (CTE) for these filters should be maintained. Desirably, Increases in CTE resulting from the application of washcoats and catalyst should not exceed 10×10−7/° C. averaged over the range from 25–1000° C., and CTE values for the washcoated filters should not exceed 20×10−7/° C. over that temperature range, in order to preserve the thermal shock resistance of the filter. Further, gas permeabilities through the catalyzed filter should be sufficient to maintain pressure drops below 8 kPa at exhaust gas space velocities up to 150,000 hr−1 after filter regeneration to remove trapped particulates.
Problematically, significant increases in CTE and reductions in filter permeability frequently result from the application to these filters of the alumina or other washcoating materials customarily employed to support the required emissions control catalysts. Present understanding is that during the washcoating or catalyzing process, both wall porosity of the filter and the structural micro-cracks (crack widths of 0.1–3 microns) that are present in most of these ceramic materials are frequently filled with the washcoating material. The problem is most severe in the case of highly microcracked ceramics such as the aluminum titanates, particularly when the washcoating formulations contain materials of very fine particle size (e.g., particle diameters in the 0.02–0.1 μm range).
Microcracking is a significant contributor to the low CTEs exhibited by many of these materials, with crack closure during heating considerably moderating the dimensional increases that would otherwise occur. Thus the filling of these microcracks with washcoating constituents can result in some cases in much higher expansion coefficients, e.g., in the range of 40–50×10−7/° C., in the washcoated structures. At these CTE levels the risk of structural damage to the filters under the normal conditions of exhaust filter use is unacceptable.
One approach to the problem of washcoat microcrack filling that has been employed during the catalyzation of conventional flow-through catalyst substrates for gasoline engine emissions control has been the use of so-called passivating coatings. These are pre-coatings applied to the walls of the ceramic substrates prior to washcoating that can block the washcoating materials from intruding into the microcrack structure of the ceramic. U.S. Pat. No. 4,532,228 provides some examples of coating materials that can be carbonized or otherwise solidified to provide a washcoat barrier, and then removed after the washcoat has been laid down.
Unfortunately, these conventional coating approaches have so far not been effective to provide suitable passivating coatings for ceramic wall flow filters or advanced flow-through catalyst supports. One recurrent problem is that the known passivating coatings do not provide adequate protection against CTE increases in highly microcracked ceramics such as the aluminum titanates. Another problem is that such coatings are not very effective to guard against unacceptable reductions in ceramic wall gas permeability. The high gas permeability provided by the highly interconnecting wall porosity of advanced ceramic wall flow filters is of critical importance for engine exhaust filtration applications. Thus some means of simultaneously preserving the low thermal expansion coefficients and high gas permeability of advanced ceramic support or filter materials such as the aluminum titanates, even at high catalyst washcoat loadings, is required. Further the means selected cannot adversely affect the important catalyst support functions of the washcoat.

Porous ceramic filters with catalyst coatings


An auto-repairing photoresist composition comprises 1 to 10 wt % of microcapsule having a capsule wall and a capsule core based on the total weight of the photoresist composition, wherein the capsule wall includes an alkali-insoluble resin, and the capsule core includes: 10 to 60 wt % of a photo-curable unsaturated resin oligomer; 10 to 50 wt % of a photo-curable monomers; 10 to 70 wt % of a first black pigment paste; 0.1 to 10 wt % of a first photo-initiator; and 0.1 to 5 wt % of a coupling agent, based on the total weight of the capsule core. The photoresist composition of embodiments of the present invention can be used for preparation of Black Matrix, and has an auto-repairing property to improve substantially the pass yield of product. A method of preparing the photoresist composition, a color filter substrate, and a display apparatus are also disclosed.

In flat panel display apparatuses, Thin Film Transistor Liquid Crystal Display (TFT-LCD) are characterized in small volume, low power consumption, relatively low production cost, no radiation, and the like, and thus predominates in the current market of flat panel displays.
Currently, the primary structure of TFT-LCD comprises an array substrate and a color filter (CF) substrate assembled together. Among others, the color filter substrate comprises primarily a glass substrate, a Black Matrix (BM), a color photoresist, and a protective film. In general, the Black Matrix is arranged in a manner of grating, stripe, or speckle among the color patterns formed from the color photoresist. The primary function of Black Matrix is to improve the contrast by inhibiting the mixing of colors, as well as to provide a shield against stray light so as to prevent the malfunction of TFT caused by light leakage among pixels.
A photoresist composition for Black Matrix undergoes coating, exposure, and development to form Black Matrix. The current photoresist composition for Black Matrix comprises a black pigment paste, photo-polymerizable monomers, photoinitiators, and an organic solvent, wherein the black pigment paste serves primarily to form a black color for preventing light leakage; and the photoinitiators induce a polymerization reaction of the photo-polymerizable monomers under UV radiation to form a polymeric film. The Black Matrix layer is required to possess a high light shielding property. However, BM is commonly prepared in an earlier procedure, which is followed by procedures of preparing the color photoresist, the protective layer, etc. Thus, the process technology of production line, as well as other factors including particles, impurities and the like will affect the BM layer and cause scratching damages leading to light leakage of damages and formation of white defects, thereby affecting the quality of TFT-LCD products. For avoiding such defects, the current process has to comprise a repair procedure after completing the preparation of Black Matrix, as shown in FIGS. 1a to 1c, that is, a schematic flowchart of the current process of preparing Black Matrix. Among others, FIG. 1a indicates that damages appear in some sites after a photoresist composition for Black Photoresist is applied; FIG. 1b indicates that white defects are formed at the damaged sites of the Black Matrix after the photoresist composition for Black Matrix undergoes laser radiation; and FIG. 1c indicates that the formed white defects are repaired by means of a repair procedure which can repair the defects by adding the photoresist composition for Black Matrix onto the damaged sites and allowed the added photoresist composition to be cured.
The current technology has a disadvantage that when white defects appear in the Black Matrix, a specific repair procedure and additional devices are required to add the photoresist composition for Black Matrix, thereby increasing the cost.

Photoresist composition and method of preparing the same, color film substrate, and display apparatus

BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.


Methods, systems, and articles of manufacture for entity-level technology recommendation are provided herein. A method includes searching a first query against a first corpus of documents to determine a set of documents matching an entity of interest identified in the first query, generating a list of technologies that (i) appear within the content of the set of documents and (ii) are associated to the entity of interest, searching a second query against a second corpus of documents to determine a set of documents representing a technology recommendation for the entity of interest, wherein said second query is based on one or more selected technologies from the list of technologies, and outputting the set of documents representing a technology recommendation to a user and/or a display.

Licensing technological information such as intellectual property (IP) includes selling certain rights to third-party individuals and/or business. Traditionally, entities and/or individuals have needed to manually identify and select potentially appropriate technological information for licensing purposes from large amounts of data. Such searching for appropriate technologies from large data sources is a labor-intensive task. Accordingly, a need exists for leveraging knowledge bases in the selection of unlabeled data in furtherance of named entity classification.

Techniques for entity-level technology recommendation

International Business Machines Corporation


An .alpha.-D-hlycosyl kasugamycin having the formula (III): ##STR1## wherein n is an integer of not less than 1. According to the present invention, the novel substance which is highly safe and easily hydrolyzed with .alpha.-glucosidase to exhibit physiological activities inherent to kasugamycin is obtained.

The present invention relates to an .alpha.-D-glycosyl kasugamycin and its preparation, and an antibacterial agent containing the same; more particularly, to a novel substance, an .alpha.-D-glycosyl kasugamycin exhibiting an antibacterial activity, to a process which comprises allowing a saccharide-transferring enzyme to act on an amylaceous substance and kasugamycin to form .alpha.-D-glycosyl kasugamycin and recovering said .alpha.-D-glycosyl kasugamycin, and to an antibacterial agent which contains .alpha.-D-glycosyl kasugamycin.
Kasugamycin is an antibiotic that is produced by a microorganism of the species, Streptomyces kasugaensis as disclosed in Japanese Examined Patent Publication No. 6818/1967, and has the chemical structure shown by the following formula (I): ##STR2## Because of its activity of inhibiting the growth of pathogenic microorganisms proliferating in plants, fishes, domestic animals and poultries, kasugamycin is utilizable as an antibacterial agent applicable to agriculture and gardening or fishery and farming, for example, as disclosed in Japanese Examined Patent Publications No. 56202/1988 and No. 33447/1989.
In general, antibiotics cause a trouble of the emergence of resistant bacterium and there has been a great demand to establish a highly safe derivative of kasugamycin.
An object of the present invention is to provide a novel highly safe derivative of kasugamycin which exhibits an antibacterial activity inherent to kasugamycin.
Another object of the present invention is to provide a process for preparing the derivative.
Further object of the present invention is to provide an antibacterial agent containing the derivative.
These and other objects will become apparent from the description hereinafter.

Alpha-D-glycosyl kasugamycin, its preparation, and antibacterial agent containing the same

Hayashibara Biochemical Laboratories, Inc.


The present invention provides methods and compositions for producing a neurosalutary effect in a subject useful in treatment of neurological disorders, including retinal and optic nerve damage, in a subject in need thereof. The method includes administering to a subject a therapeutically effective amount of a hexose, such as mannose.

Nerves in mature mammals, such as the optic nerve, do not normally regenerate after injury. Retinal ganglion cells (RGCs) initiate a sprouting reaction at their damaged nerve endings, but this growth is abortive and the cells soon begin to die (Ramon y Cajal, 1991). Nonetheless, RGCs can regenerate lengthy axons through a peripheral nerve graft (Aguayo et al., 1991) and even through the optic nerve itself if the lens is injured (Fischer et al., 2000; Leon et al., 2000), or if a fragment of peripheral nerve is implanted into the vitreous (Berry et al., 1996). These latter manipulations lead to the appearance of activated macrophages in the eye, and it has been recently shown that intravitreal macrophage activation is sufficient to allow RGCs to regenerate their axons through the optic nerve (Leon et al., 2000; Yin et al., 2003). In culture, a macrophage-derived protein, acting in concert with a small molecule that is constitutively present in the vitreous, stimulates mature rat RGCs to regenerate their axons in a cAMP-dependent fashion (Yin et al., 2003).
In contrast to mammals, fish and amphibia can regenerate their optic nerves throughout life (Jacobson, 1991). In culture, the most potent axon-promoting factor for goldfish RGCs is a small hydrophilic molecule (<500 Daltons) that is secreted by non-neuronal cells of the optic nerve. This molecule is referred to as AF-1 (Schwalb et al., 1995; Schwalb et al., 1996).
Understanding the factors involved in mammalian and non-mammalian neuron regeneration will aid in the development of potential therapeutics for treatment of neuronal disorders. Disorders of the peripheral and central nervous system are widespread, and for many of these conditions effective therapeutic interventions are lacking. Neurological disorders may be caused by an injury to a neuron, such as a mechanical injury or an injury due to a toxic compound, by the abnormal growth or development of a neuron, or by the misregulation (such as downregulation or upregulation) of an activity of a neuron. There is a need in the art for methods and compositions that can improve the ability of a neuron, or portion of the nervous system, to resist insult, to regenerate, and to maintain desirable function, which can be used for treatment of neurological disorders.

This patent is subject to a terminal disclaimer.

Methods and compositions for treatment of neurological disorder


The cavity in the mirror arm of a conventional interleaver is replaced by a wedge integral with the beamsplitter structure of the interleaver. Thus, the light reflected from the AR-coated surface of the wedge is dispersed away from the optics of the device. The beam emerging from the wedge surface is directed toward a tilted mirror that reflects it totally on-axis. As a result of the diversion of the light reflected from the wedge surface and the non-parallel disposition of the wedge surface with respect to the mirror, phase errors are virtually eliminated. In another embodiment, a second wedge is used with a second antireflective surface disposed in parallel to the first wedge's antireflective surface, and with a mirror normal to the optical axis of the device.

1. Field of the Invention
This invention pertains to the general field of optical communications and, in particular, to a step-phase interferometric optical interleaver.
2. Description of the Prior Art
Interferometric optical interleavers are commonly utilized in dense wavelength division multiplexing (DWDM) optical communication, where various frequencies (1/λ) of laser light are used as carrier signals (channels) and are coupled into the same optical fiber, which acts as a waveguide. Data signals are superimposed over the carrier signals and are transported in the waveguide. Thus, the information capacity is directly proportional to the number of channels in the fiber. Since the total usable wavelength range is limited (about a few tens of nanometers), as channel spacing decreases, more channels can fit into the same optical fiber and greater communication capacity is achieved.
Channel spacing is limited by the capability of the multiplexer (MUX) and the de-multiplexer (de-MUX). Currently, the standard channel spacing is 100 GHz (0.8 nm) and manufacturing costs increase dramatically to implement a channel spacing smaller than 100 GHz. Therefore, a cost-effective method for interleaving channels and enabling the use of higher bandwidth filters with lower channel spacing in an optical communication system would be very desirable. For example, a one-stage interleaver can be used with 100-GHz filters and a 50-GHz channel spacing. Similarly, a two-stage interleaver enables the use of 100-GHz filters in a 25-GHz channel-spacing communication system.
Interferometric interleaver devices used to separate communications channels into distinct optical signals are well known in the art. See, for example, U.S. Pat. Nos. 6,169,626, 6,268,951 and U.S. Pat. No. 6,275,322. These interleavers combine a beamsplitter with an etalon cavity (also known as a Gires-Tournois resonator or GTR) in a non-linear phase-shifter arm (the GTR arm) of the interleaver and a mirror in a reference arm (the mirror arm) to produce the necessary phase shift and interference effects. FIG. 1 illustrates schematically such a conventional step-phase interferometric interleaver. A multi-channel optical input W0 is passed through a beam splitter 10 which splits the beam into a first wavefront W1 transmitted toward a GTR device Mc and a second wavefront W2 reflected toward a mirror M2. The GTR includes a front surface 12 and a parallel back surface 14 with very low and very high reflectance, respectively (which define a cavity also known in the art as an "etalon"). The GTR Mc and the mirror M2 are positioned at distances L1 and L2, respectively, from the interface 16 of the splitter 10. The GTR causes a phase shift in the wavefront W1 which is returned to and partially reflected by the beamsplitter 10 to produce a beam ETCR. in a first output arm of the step-phase interferometer and is partially transmitted to produce a beam ETCT, in a second output arm of the interleaver. Similarly, the wavefront W2 is reflected from the mirror M2, is partially transmitted by the beamsplitter 10 to produce a beam ERMT in the first output arm, and is partially reflected to produce a beam ERMR in the second output arm of the interleaver. The notation used in this disclosure, wherein T, R, M and C refer to transmission, reflection, mirror and cavity (resonator), respectively, and the prime symbol (′) refers to the internal optical path, is conventional in the art.
Several complicating factors limit the degree to which these interferometric interleavers can be utilized to increase communication capacity. For instance, the non-linear dependence of the optical phase on carrier frequency of the interleaver intrinsically introduces undesirable chromatic dispersion that reduces their usefulness. A solution to this problem is disclosed in commonly owned U.S. Ser. No. 10/267,216, hereby incorporated by reference, wherein a GTR is used to cancel chromatic dispersion in the passband of the device.
The proper functioning of optical interleavers is predicated upon the precise control of the optical-path lengths of the wavefronts traversing the device (L1 and L2 in FIG. 1), which are susceptible to variation as a result of manufacturing tolerances and thermal effects. U.S. Ser. No. 10/287,340, also incorporated by reference, provides a solution to this problem based on the use of a parallel glass plate mounted on a rotating fixture in the cavity of the interferometric interleaver. The glass plate refracts the incident optical signal to increase the length of its optical path as a function of the angle of incidence. Thus, the device can easily achieve a precision in the order of nanometers.
Another problem arises from the way interleavers are in fact manufactured in order to simplify the challenge of controlling precisely the optical-path length of each arm of the device. Rather than using a mirror as illustrated in FIG. 1 or a totally reflective surface on a solid block, each of which provides no flexibility in establishing the length of the optical path L2, a cavity with spacers is used. As illustrated in FIG. 2, the structure of such a conventional interleaver device 20 consists of two air spaces between a transparent body incorporating the beamsplitter interface 16 and the reflective mirrors M2 and 14 (see FIG. 1 also). These air spaces are varied to set the cavity length Lc and the distance of the mirror M2 from the beamsplitter interface 16 such that the mirror's distance L, from the interface is equal to the distance from the interface to the middle of the GTR's cavity; that is, L2=L1−1/2Lc. Accordingly, a first set of spacers 22 determines the distance between the two etalon surfaces 12 and 14. A second set of spacers 24 establishes the distance L2 between the beam splitter interface 16 and the mirror M2, thereby also setting the optical-path difference L2-L1. Thus, in practice the mirror arm of the interleaver is also implemented with a cavity structure and the reflectivity of the front surface 26 is critical to the proper functioning of the interleaver. Ideally, the surface 26 should be totally transmissive, which would produce the same effect as the mirror of FIG. 1. In practice, a reflectivity of less than 10 percent is tolerated because of limits in the effectiveness of antireflective coatings, but a corresponding phase error is introduced that severely limits the use of interleavers to improve the capacity of optical communication systems.
As those skilled in the art would readily recognize, in the pass band of optical frequency processed by an interferometric interleaver, the two beams are in phase, causing constructive interference. In the stop band of the optical frequency, the two beams are out of phase and, therefore, interfere destructively. Channel isolation depends on how well destructive interference is achieved. If the interfering beams are exactly out of phase within the stop band (i.e., with a phase difference of 180 degrees), the resulting isolation is perfect. However, any variation from 180-degree in the phase difference between the two interfering beams (herein defined as "phase error") significantly degrades the performance of the interleaver. The dependence of channel isolation on phase error is given by the relation
                              Channel                                                              Isolation                =                  10          *                                    log              10                                                  [                                                sin                  2                                                                  (                                                            ϕ                      error                                        2                                    )                                            ]                                                          (        1        )            where φerror is phase error in radians; and Channel Isolation is defined as the ratio of the residual power to the input power in the stop band, measured in dB. This relation is illustrated graphically in FIG. 3.
In current communication systems, the typical acceptable channel isolation is about 27 dB. Accordingly, the graph of FIG. 3 shows that a maximum phase error of 5 degrees is acceptable, which is very difficult to achieve with traditional interleaver construction. It is well known that a GTR or any etalon cavity structure introduces a nonlinear phase. For an interleaver of the type shown in FIG. 1 (see also B. Dingel et al., "Multifunction optical filter with a Michelson-Gires-Tournois interferometer for wavelength-division-multiplexed network system applications," Optics Letters, Vol. 23, No. 14, 1998), the phase difference between the beams reflected by the GTR and the Mirror M2 is nearly 180 degrees in the stop band and, therefore, the two beams interfere destructively. The phase difference in the pass band is nearly in phase; thus, they interfere constructively. Any deviation from 180 degrees produces a residual power in the stop band, as illustrated by the intensity plots of FIG. 3A. The local peaks in the stop band determine the channel isolation of the device. The phase error corresponding to the local peak is a local extreme and is given by the relation
                                                                                ϕ                  NP                                =                                                      2                                                                                tan                                                  -                          1                                                                                [                                                                                α                                                                                (                                                                  1                                  -                                                                      2                                                                        α                                                                                )                                                                                (                                                              2                                -                                α                                                            )                                                                                ]                                                                              -                                                            tan                                              -                        1                                                                                [                                                                                (                                                          1                              -                                                              2                                                                α                                                                                )                                                                                α                                                                                (                                                              2                                -                                α                                                            )                                                                                ]                                                                                α                  =                                                            1                      -                                                                        R                          NP                                                                                1                      +                                                                        R                          NP                                                                                ,                                                    ,        where                            (        2        )            and ′RNP is the reflectivity of the front surface 12 of the cavity in the GTR. Usually, to obtain wide enough pass-bandwidth, the reflectivity RNP must be in 0.15 to 0.2 range. FIG. 4 shows the phase error introduced by the non-linear phase shifter as a function of the front-surface reflectivity. The illustrated by the graph, a reflectivity RNP of 0.2 produces the maximum allowable phase error of 5 degrees.
In interleavers constructed with an etalon cavity in the mirror arm, as illustrated in FIG. 2, an additional phase error is introduced by the etalon as a result of multiple-reflection effects, in addition to the intrinsic phase error φNP. This phase error at the extreme (because its extreme values affect channel isolation) is given by the relation
                                          ϕ            etalon                    =                      2                                                                                tan                                  -                  1                                                                          [                                                      1                    2                                                                          (                                                                                (                                                                                1                              +                                                              R                                                                                1                              -                                                              R                                                                                )                                                                    -                                                                        (                                                                                1                              -                                                              R                                                                                1                              +                                                              R                                                                                )                                                                                )                                                  ]                                                    ,                            (        3        )            where R is the reflectivity of the etalon's front surface 26. It should be noted that both cavities in the interleaver of FIG. 2 experience the effect of multiple reflections. Each phase error is measured with respect to the same mirror M2. Due to the location of this mirror, and the corresponding difference in optical paths, the phase-error equations are correspondingly different for each cavity. FIG. 5 is a plot of this phase error as a function of front-surface reflectivity. It is noted that a reflectivity of 0.25% produces a phase error of about 6 degrees, which degrades channel-isolation performance to an unacceptable degree.
Thus, the total phase error of a conventional interleaver (FIG. 2) within its stop band is given by the sum of the respective contributions from both arms of the device, as followsφerror=|φNP|+|φetalon|.  (4)FIG. 6 illustrates the dependence of channel isolation on the reflectivity of the etalon's front surface 26 when the GTR has a front surface 12 with a reflectivity RNP of 20% The graph shows that channel isolation is degraded by about 7 dB by a change in AR coating from zero to about 0.25% reflectivity. At 0.25% reflectivity, the isolation is only −20.5 dB, which is well below the typical requirement of 27 db in today's telecommunication system. In order to achieve the desired performance from a conventional interleaver, the etalon's front surface 26 has to exhibit a reflectivity better than 0.01% (−25.2 dB). This is almost impossible to implement with existing AR coatings.
To the extent that the resonator cavity Mc (see FIG. 1) is necessary to the function of an interferometric interleaver, the corresponding phase error is unavoidable. On the other hand, to the extent that a cavity structure is used for practical reasons only to precisely place the mirror M2, its contribution of ghost reflections from the front surface 26 of the etalon diminishes the usefulness of interferometric interleavers for channel isolation. Unfortunately, antireflective (AR) coatings are not sufficiently effective to control the reflectivity of a surface to the degree necessary to precisely control phase error. Therefore, there is still a need for an interferometric interleaver that minimizes the introduction of phase error as a result of its configuration, rather than through the use of AR coatings. The present invention provides simple solutions to that end.

Step-phase interferometric optical interleaver


A method, system, and apparatus are provided for capturing a video image and speed of a target vehicle. A ranging device detects a distance to a target vehicle. The focal distance or zoom of a video camera is set and adjusted based on the distance. The speed of travel of the vehicle is detected, displayed, and/or stored in association with a video image captured of the vehicle by the video camera. A range of distances within which to capture the video image and speed of the vehicle may be set by detecting distances between a pair of landmarks or using GPS and compass heading data. An inclinometer is provided to aid initiation of a power-conservation mode. A target tracking time may be determined and compared to a minimum tracking time period. A device certification period can be stored and displayed and the device deactivated upon expiration thereof.

The use of radar and lasers to determine the speed of travel of objects, such as motor vehicles has been employed for quite some time. Law enforcement officials often use handheld or vehicle mounted traffic enforcement systems (TES) that emit and receive such types of radiation to identify motor vehicles that are being operated in excess of posted speed limits and to aid enforcement of those limits.
Devices have also been developed that capture an image of a vehicle as a TES unit determines the speed thereof. These images may be combined with or have superimposed thereon, the determined speed of the vehicle as well as other information associated with the vehicle, the law enforcement official, and the TES unit, among other information. For example, U.S. Pat. No. 6,985,827 to Williams et al discloses a laser-based speed measurement system that transmits image capture signals to a digital camera and produces a digital still image that includes speed data.
The emitted electromagnetic radiation, e.g., radio waves, microwaves, or light waves, may also be employed to determine the range or distance of a targeted object from the emitter or TES unit. This range data may be employed to inform a focal distance or zoom distance of a camera associated with the TES unit. For example, U.S. Pat. No. 5,939,717 to Dunne et al. discloses a speed detection and image capture system for moving vehicles that uses a laser to determine the range to the vehicle and then focuses a video camera based on the range for capture of a still image. Similarly, U.S. Pat. No. 7,920,251 to Chung discloses a speed measurement system in which a laser rangefinder is employed to trigger capture of a still image of a vehicle when the vehicle enters a predetermined range.
Traffic enforcement system (TES) units utilizing radar and laser technologies have been in use for a number of years. It is typical for the law enforcement agencies utilizing these systems to require their officers to practice established tracking history procedures. In addition to the tracking history procedures, some agencies require the officers to track the target speed for a set minimum time before taking any enforcement action. Knowing the minimum tracking time period and ensuring that the minimum tracking time was observed is the responsibility of the law enforcement officer operating the TES unit.
It is also typical for the law enforcement agencies utilizing these systems to require periodic testing and certifications as to the accuracy of the devices. The initial certification of the devices is typically performed by the system manufacturer prior to shipping to the end law enforcement agency. The periodic recertification testing is the responsibility of the law enforcement agency intending to use the equipment. The testing laboratories perform what is known as critical-performance testing (CPT) on these systems and provides the agency with the Certificates of Calibration. These certificates can be used in court to help establish the legal justification for issuing a particular traffic citation. Certification periods may vary from one jurisdiction to another and it is the responsibility of the law enforcement agency to track when each device is due for recertification.
It would be advantageous in the design of the TES devices to allow for a method of warning the operator when the date for recertification is near. This warning, for example, could be accomplished by displaying the recertification date on the device during TES device power up sequence.

Traffic enforcement system with time tracking and integrated video capture