It is an object of the present invention to provide a technique capable of suppressing power consumption when printing an image with high density in a thermal printer. the recording paper contains a reversible thermochromic recording material which is in a color-developed state in an initial state, starts color reduction at T1 or higher after the start of rising temperature, and turns into an achromatized state at T2 or higher which is higher than T1. A thermal printer includes the input unit that receives image data, the image processing unit that converts the density for each pixel of the image data into heating data based on the density and temperature characteristics of the reversible thermochromic recording material, and the print processing unit that makes the thermal head heat the recording paper for each pixel based on the heating data to form an image on the recording paper.

A thermal printer using a thermal head adopts a thermosensitive system in which recording paper containing an irreversible thermochromic recording material that develops color when heated is used, and the color develops gradually from white to black with the heat applied by the thermal head (for example, see Patent Document 1).
The thermal printer of the thermosensitive system is incorporated into a medical diagnostic device such as an ultrasonic diagnostic device, for example, and almost all the image data to be printed is black, and an image of an organ or the like is formed in white or gray on the black background. Therefore, when printing, even higher heat is necessary to be applied in order to generate a deeper color.


The disclosed technology provides systems and methods for identifying potential error locations, patterns, and likelihood metrics in connection with trellis-based detection/decoding. In one aspect of the invention, the disclosed technology computes soft reliability information for each detected/decoded bit or codeword syndrome value.

This invention relates to identifying most likely errors in a communication signal and, more particularly, to identifying potential error locations, patterns, and likelihood metrics in connection with trellis-based detection and/or decoding. This invention also relates to computing soft reliability information for each detected/decoded bit or codeword syndrome value.
Consider a system that can be represented by a finite state machine. For example, a finite state machine can be used to model an inter-symbol-interference (ISI) channel or a convolutional code encoder. A trellis diagram can be used to represent the sequence of all possible paths (i.e., sequences of states) that the system can visit over time. If the system can transition from state A at time t to state B at time t+1, then these states are connected by a branch. Each branch may be labeled by X/Y pair, where X denotes the input that causes the system to transition from state A to B and Y represents an output corresponding to this transition. For example, an ISI channel with a two-bit channel response can be represented by a four-state trellis diagram. The states of this trellis can be labeled as 00, 01, 10, 11 and may be associated with the latest two bits transmitted through the ISI channel. For example, if the system is at state 01 at time t, and 0 is transmitted, then the next state at time t+1 would be 10. Similarly, the system would transition to state 11 if 1 were transmitted. Channel output Y that results from these transitions is a real number m, that may be different for each branch.
In the convolutional encoding situation, an encoder receives input bits and generates output bits that are weighted sums of the input bits.
In the case of an ISI channel, the number of output signals will be usually the same as the number of input signals. In contrast, a convolutional encoder generally does introduce additional output bits, such that there may be two bits at the output of a convolutional encoder for each input bit, for example.
In the ISI channel situation, the signals at the output of the ISI channel are detected by a trellis-based detector, such as a Viterbi (maximum-likelihood) detector. In the convolutional encoder situation, the bits at the output of the encoder (also called "parity bits") are communicated to a receiver and are decoded using a Viterbi decoder. In either situation, the detector/decoder is based on the trellis representing the ISI channel or the convolutional encoder. However, a Viterbi detector/decoder does not know the particular path that occurred in the trellis of the ISI channel/convolutional encoder. Rather, the Viterbi detector/decoder must use the signals/bits it receives and find the trellis path that most-likely occurred based on the received signals/bits. This detection/decoding is often complicated by the presence of noise or errors in the received signals/bits. In some situations, the trellis path that most-likely occurred based on the received signals/bits may not be the same as the trellis path that actually occurred in the ISI channel/convolutional encoder. In such situations, another layer of error-correction may be applied before the ISI channel/convolutional encoding, so that any errors that may remain after Viterbi detection/decoding can be addressed. In this case, it may be helpful to determine the potential location and nature of these errors and to provide this information to the additional layer of error-correction for its consideration.

Reliability metric generation for trellis-based detection and/or decoding


To provide a highly heat resistant flame retardant.

Flame retardants are well known as an additive to impart flame retardancy to a resin when blended with the resin. Among such flame retardants, compounds containing bromine in a large amount have been added in various resins and used as a halogenated flame retardant. For example, tetrabromobisphenol A which is one of representative brominated flame retardants, is known as a halogenated flame retardant the most produced in the world.
As brominated flame retardants, higher molecular weight type flame retardants tend to be used considering environmental consciousness. For example, ethylene-bridged oligomers of tetrabromobisphenol A have been proposed (Patent Documents 1 to 4).
Such oligomers are defined to have a molecular weight of from 1,000 to 5,000 and a melting point of from 120 (or 150)° C. to 250° C., and are considered to be useful to impart flame retardancy to polystyrene or reinforced polyester.

Halogen-containing polymer and production method for same

Abstract: A polymer having repeating units represented by the following formula (1), which has a weight average molecular weight as calculated as standard polystyrene of at least 6,000:

Abstract: wherein R is a C1-6 alkylene group, —S— or —SO2—.


An interior window seal includes an interior window seal having a pair of substantially parallel trim panel fingers adapted to receive a trim panel therebetween and a pair of substantially parallel flange fingers adapted to receive an inner door panel flange therebetween, the flange fingers adapted to rotate between a flange non-contacting position and a flange contacting position, thereby allowing for longitudinal movement of the seal relative to the flange when in the non-contacting position and preventing movement of the seal relative to the flange when in the contacting position.

Door seals, and in particular door interior window seals for attaching to a door window opening in an automotive vehicle, must perform many functions. Primarily this includes prevention of various contaminants such as moisture, dirt and debris from getting into the door interior. The seal must also prevent noise such as road, engine, and wind noise from penetrating into the passenger compartment. Additionally, the seal determines the quality of the fit between a vehicle door interior trim panel, inner door panel and side window. A good fit affects window opening and closing characteristics, as well as window rattle and seal appearance, important elements in customer perception of vehicle quality.
To accomplish these functions effectively, a seal must not only be designed to properly interact with the vehicle door interior trim panel, the inner door panel and side window, but must also be easily attached to the flange of the inner door panel while being difficult to remove. Low seal attachment effort is necessary to expedite vehicle assembly, while seal extraction effort must be high to provide seal retention and to prevent seal disengagement during window usage. Low seal attachment effort is particularly important when attaching door interior window seals because of the importance of proper alignment of the seal with respect to the inner door panel. More specifically, during vehicle assembly the seal is first attached to the interior trim panel and then both the interior trim panel and seal are attached to the inner door panel via the seal. The seal must be manipulated longitudinally of the vehicle to insure proper alignment of the interior trim panel with respect to the inner door panel. High attachment effort of the seal on to the inner door panel flange would hinder such manipulation.
In addition to meeting attachment and manipulation effort requirements, a door interior window seal must also be capable of fitting on the inner door panel flange securely. Variable thickness inner door panel flanges may cause a seal to fit improperly, thus decreasing the debris barrier and noise attenuation functions. Previous window seal designs had to trade off low insertion efforts, and more specifically the ability to properly align the interior trim panel with respect to the inner door panel, in order to have a seal that would securely hold the interior trim panel to the inner door panel flange.
What is desired than is a door interior window seal that facilitates attachment of the interior trim panel to the inner door panel flange via the seal, allows for low effort longitudinal adjustment of the interior trim panel relative to the inner door panel, and provides secure attachment of the interior trim panel to the inner door panel at the seal interface.

Automotive vehicle door interior window seal


A recording apparatus for selectively recording, on a recording medium, a plurality of kinds of digital main information signals having different data rates is arranged to generate a digital additional information signal related to the recorded digital main information signal, to record the additional information signal on the recording medium along with the digital main information signal, and to obtain a clock signal for the operation of an additional information generating circuit by frequency-dividing one of different clock signals used for main information generating circuits. The arrangement requires only one additional information generating circuit to minimize the scale of circuit arrangement for reduction in size and weight of the recording apparatus. A reproducing apparatus for reproducing digital main information signals from a recording medium on which the digital main information signals of different data rates are selectively recorded together with the digital additional information signal related thereto is arranged to generate a clock signal for an additional information processing circuit for reproducing the digital additional information signal by frequency-dividing one of clock signals applied to main information processing circuits for processing digital main information signals reproduced. The size and weight of the apparatus can be reduced as the circuit arrangement requires only one additional information processing circuit.

1. Field of the Invention
This invention relates to a digital signal recording/reproducing apparatus and more particularly to a digital signal recording/reproducing apparatus capable of recording and/or reproducing, along with additional information, a plurality of kinds of digital main information having different data rates from each other.
2. Description of the Related Art
The apparatuses of the kind reproducing records from tape-shaped recording media by means of rotary heads have recently come to include a digital audio tape recorder (abbreviated to DAT), a digital data recorder (DDR), etc., in addition to the video tape recorder (VTR) which is well known. As a result, it has become necessary to arrange the VTR to have some function that is compatible with such various apparatuses.
Such being the background situation, a device for recording, in addition to the conventional analog audio signal, a digital audio signal on an extended part of a video recording track in a time-base compressed state has been developed for the VTR and is now being marketed.
The recording format of the digital audio signal varies with necessary specifications for recording. In other words, since the data rate of the data to be recorded varies according to the necessary specifications, the recording format also varies accordingly. It is, therefore, desirable that the digital audio signal is arranged to be recordable in accordance with any of the audio signal recording formats of varied kinds by the same apparatus (or VTR) while the video signal recording format is arranged to be unvaried.
Generally, in designing a VTR to be capable of recording audio signals in any of various audio signal recording formats, the VTR must be provided with different digital audio signal processing circuits for different data rates respectively. Further, in cases where it is necessary to permit retrieval of the digital audio signal or to have the like function, the VTR must be provided with processing circuits arranged to generate a retrieval signal as additional information and to extract and reproduce the retrieval signal for each of the various recording formats. It is conceivable to process this additional information (or retrieval signal) by the same processing circuit provided for processing the digital audio signal. Generally, however, the additional information to be added for retrieval is preferably recorded and reproduced at a low bit rate for the purpose of facilitating the extracting action thereon.
Therefore, for arranging the VTR to be capable of complying with the audio signal recording formats of varied kinds, the VTR must be provided with processing circuits for processing the audio signals for the various formats and also with processing circuits for processing the retrieval additional information for the various formats. Such arrangement would result in a great increase in the circuit scale of the VTR.

Digital signal recording/reproducing apparatus for recording and/or reproducing main information along with additional information


A video graphics system in which an effect can be produced in selected portions of a image held in a first store. Image data in the first store relating to a user defined area of interest in the image is copied to a second store and processed in accordance with a user selected function. The area of interest is selected by the user by magnifying and shifting a displayed representation of the image so that the area of interest is displayed and then selecting a locking function which retains parameters associated with the shifting and magnifying of the displayed image. Once the image data relating to the area of interest has been processed it can be painted onto the image held in the first store to produce the desired effect. By processing only the selected area of interest the speed of processing is increased.

An example of a video graphics system of the aforesaid type is described in British Patent No. 2,089,625 and corresponding U.S. Pat. No. 4,514,818 assigned to the present assignee. This system includes a touch tablet and stylus combination for generating position signals designating the position of the stylus relative to the touch tablet. The user paints or draws (hereinafter referred to as "painting") by selecting a desired color and implement from a range of predefined colors and implements and manipulating the stylus on the touch tablet. This manipulation causes the touch tablet to generate a series of position signals which define the path or positioning of the stylus. An image is held in a store and when a position signal is produced a new patch of pixels are derived by a processing circuit for every picture point of the image covered by the selected implement. The image data in the store is read repeatedly and is applied to a TV-type color monitor so that the build up of the picture can be observed. Video graphics systems of this type are manufactured by the present assignee and sold under the trade marks "PAINTBOX" and "GRAPHIC PAINTBOX".
In addition to painting and picture composition as described in the aforesaid patents, systems of this type can also provide for automatic processing of stored images to produce special effects. Some of these effects may be applied to the whole picture, such as a color wash or tint, but others are used much more selectively. Thus parts of an image may be required to be blurred or the reverse process (that is to say a sharpening or crisping of the image) may instead be required and such effects may be achieved by any suitable known blur or crisp algorithm. One known procedure for generating such effects involves an automatic manipulation of data for the whole image, usually involving spatial filtering algorithms or adjustment of color parameters, and results in a manipulated version of the whole of the original image being produced. The final processed data is obtained by processing the manipulated data selectively in combination with the original data by painting selected portions of the manipulated image into the original image, and thus manipulated data is only incorporated into the final image in selected regions. The painting of selected portions can be achieved by deriving pixels by combining the original image pixels with manipulated image pixels and writing the resulting modified pixels back into the framestore as described in British Patent No. 2,113,950 and U.S. Pat. No. 4,602,286 assigned to the present assignee. In this system first and second images are stored in respective first and second storing means and are combined on a picture point by picture point basis by a interpolator under the control of control image data stored in a third storing means. The control image can be created by the operator when the system is in a painting mode as described in the abovementioned British Patent No. 2,089,625 and corresponding U.S. Pat. No. 4,514,818. The control image can be used as a mask or stencil to blank off areas in the first, i.e the original, image to prevent the creation of effects in those blanked off areas of the image. Image data in the blanked off areas of the first image can be prevented from being combined with corresponding image data in the second, i.e modified, image and in this way areas in the first image in which effects are not required can be defined.
The original graphics system of this type operated with a definition suitable for standard (NTSC or PAL) television broadcasting. The abovementioned "GRAPHIC PAINTBOX" is a second generation machine arranged to operate at higher definitions than that of the original system, but recently there has been a demand for machines capable of operating at even higher definitions.
The definition of a picture is increased by increasing the number of picture elements used in defining the picture and increasing the definition of a picture also increases the time taken to copy and manipulate these elements. Thus a machine capable of operating at higher definitions would be correspondingly slower in use than a machine operating at say broadcast definition to such a degree to be irritating to the operator.

Video graphics systems separately processing an area of the picture before blending the processed area into the original picture


Embodiments of the present disclosure provide methods, systems, apparatuses, and computer program products for selecting a test suite for an API. In one embodiment, a computing entity or apparatus is configured to receive test patterns and heuristics, receive an input API, the input API comprising API specifications, parse the input API to extract the API specifications, and based at least in part on the extracted API specifications and the test patterns and heuristics, select a test suite, wherein the test suite is programmatically generated using a machine learning model and comprises one or more test routines, one or more data values, and one or more expected results.

An application programming interface (API) is a set of subroutine definitions, protocols, and tools for building application software. Put another way, an API is a set of clearly defined methods of communication between various software components. An API may be for a web-based system, operating system, database system, computer hardware or software library. An API specification can include specifications for routines, data structures, object classes, variables or remote calls. Testing and validating representational state transfer (RESTful) application program interfaces (APIs) can be time consuming due to delays generated by test design, execution, and planning. Through applied effort, ingenuity, and innovation, many of these identified problems have been solved by developing solutions that are included in embodiments of the present disclosure, many examples of which are described in detail herein.

Method, apparatus, and computer program product for predictive API test suite selection


An information handling system, such as a disc drive, including a base, a disc stack rotatably attached to the base, and an actuator assembly movably attached to the base. The actuator assembly also includes a load spring and a slider attached to said load spring. The slider has an air-bearing surface. The air-bearing surface includes a first rail, a second rail and a depression positioned between the first rail and the second rail of the air-bearing surface. The depression further includes a first level surface and a second level surface. The first level surface of the slider is at a different distance from a surface of the first rail of the slider than the second level surface of the slider. The air-bearing surface may also include a divider located between the first level surface of the slider and the second level surface of the slider.

One of the key components of any computer system is a place to store data. One common place for storing data in a computer system is on a disc drive. The most basic parts of a disc drive are a disc that is rotated, an actuator that moves a transducer to various locations over the disc, and electrical circuitry that is used to write and read data to and from the disc. The disc drive also includes circuitry for encoding data so that it can be successfully retrieved and written to the disc surface. A microprocessor controls most of the operations of the disc drive as well as passing the data back to the requesting computer and taking data from a requesting computer for storing to the disc. The magnetic transducer translates electrical signals into magnetic field signals that actually record the data "bits."
The transducer is typically housed within a small ceramic block called a slider. The slider is passed over the rotating disc in close proximity to the disc. The transducer can be used to read information representing data from the disc or write information representing data to the disc. When the disc is operating, the disc is usually spinning at relatively high revolutions per minute ("RPM"). A current common rotational speed is 7200 RPM. Rotational speeds in high-performance disc drives are as high as 15,000 RPM. Higher rotational speeds are contemplated for the future.
The slider is usually aerodynamically designed so that it flies on the cushion of air that is dragged by the disc. The slider has an air-bearing surface ("ABS") which includes rails and a cavity or depression between the rails. The air-bearing surface is that surface of the slider nearest the disc as the disc drive is operating. Air is dragged between the rails and the disc surface causing an increase in pressure which tends to force the head away from the disc. Simultaneously, air rushing past the cavity or depression in the air-bearing surface produces a lower than ambient pressure area within the cavity or depression. This sub-ambient pressure counteracts the pressure produced at the rails. The opposing forces equilibrate so the slider flies over the surface of the disc at a particular fly height. The fly height is the thickness of the air lubrication film or the distance between the disc surface and the transducing head. This film minimizes the friction and resulting wear that would occur if the transducing head and disc were in mechanical contact during disc rotation.
Information representative of data is stored on the surface of the memory disc. Disc drive systems read and write information stored on tracks on memory discs. Transducers, in the form of read/write heads attached to the sliders, located on both sides of the memory disc, read and write information on the memory discs when the transducers are accurately positioned over one of the designated tracks on the surface of the memory disc. The transducer is also said to be moved to a target track. As the memory disc spins and the read/write head is accurately positioned above a target track, the read/write head can store data onto a track by writing information representative of data onto the memory disc. Similarly, reading data on a memory disc is accomplished by positioning the read/write head above a target track and reading the stored material on the memory disc. To write on or read from different tracks, the read/write head is moved radially across the tracks to a selected target track. The data is divided or grouped together on the tracks. In some disc drives, the tracks are a multiplicity of concentric circular tracks. In other disc drives, a continuous spiral is one track on one side of a disc drive. Servo feedback information is used to accurately locate the transducer. The actuator assembly is moved to the required position and held accurately during a read or write operation using the servo information.
The best performance of the disc drive results when the slider is flown as closely to the surface of the disc as possible. In operation, the distance between the slider and the disc is very small; currently "fly" heights or head media spacing is about 0.5-1 micro inches. The constant demand for increasing hard drive recording density has resulted in a drastic decrease in head media spacing (HMS) over the years. Variation in the HMS of fly height due to altitude or manufacturing variation-induced fly loss, is now an increasing source of problems due to head/media intermittent contact, especially at sub half-micro inch fly height. Intermittent contact induces vibrations detrimental to the reading/writing quality at such low fly height. Intermittent contacts may also eventually result in a head crash and total loss of data, which, of course, is very undesirable.
Slider air bearings possess three degrees of freedom; namely vertical motion, pitch rotation and roll rotation. Associated with the three degrees of freedom are three applied forces, a pre-load force imposed by the gimbal, an air-bearing suction force, and an air-bearing lift force. Steady state fly altitude of the entire slider is achieved when these three forces balance each other. Previous studies have shown a strong relationship between suction force center position and altitude sensitivity. On the one hand, lower ambient pressure will generate both loss from lift force and suction force but by different amounts, thereby having the slider reaching equilibrium with the pre-load force at lower or higher overall fly height. On the other hand, the component that will dictate the actual PTFH (pole tip fly height) loss or gain, is rotation of the slider around the pivot point (Xcg) (See FIG. 5 which is a free body diagram of slider with forces). It is generally acknowledged that the closer the suction force center is towards the leading edge (Xn<Xcg, FIG. 1), the more pitch variation that occurs when the suction force is lost or varies. Simply put, the loss of suction rotates the slider counter clockwise in the pitch direction and makes the fly loss worse. On the other hand, rotating the slider clockwise and compensation of the global fly loss can be achieved with Xn>Xcg, even to a point where PTFH can increase with altitude.
What is needed is a slider air-bearing design for low altitude sensitivity. What is also needed is a design for controlling suction force center location. However, this has to be achieved without decreasing lift and suction magnitude, which could degrade other performance characteristics such as bearing stiffness and manufacturing sensitivity.

Bi-level cavity for a slider air-bearing surface


In a double-layered vessel wall construction, which has two transversally spaced longitudinal wall layers, and wall layer-connecting plates, each of which has one longitudinal edge weldingly joined in a plate edge-to-plate edge joint in one of the longitudinal wall layers, and an opposite longitudinal edge weldingly joined in a plate edge-to-plate edge joint in the other of the longitudinal wall layers, so as to divide space enclosed by the wall construction into a plurality of cells that are typically closed at opposite ends by transverse bulkheads, cell-to-cell access openings are longitudinally staggered and located near cell ends. Accordingly, forced air ventilation can sweep through virtually all of the space enclosed within the wall construction, and a worker who falls while climbing from one cell to another via an access hole can fall no further than the vertical extent of the two cells which are interconnected by that access opening.

The following U.S. patents:
______________________________________ Patentee U.S. Pat. No. Issue Date ______________________________________ Cuneo et al. 5,085,161 February 4, 1992 Goldbach et al. 5,086,723 February 11, 1992 Goldbach et al. 5,090,351 February 25, 1992 Goldbach et al. 5,269,246 December 14, 1993 ______________________________________
disclose modular, double-walled vessel hull constructions in which one or more longitudinal walls of at least a portion of the vessel hull is fabricated of two transversally spaced longitudinal extending wall layers each made of plates weldingly joined at edges, and a series of wall layer-connecting plates, each of which has one longitudinal edge weldingly joined in a respective plate joint in one of those longitudinal wall layers, and an opposite longitudinal edge weldingly joined in the transversally corresponding plate joint in the other of those longitudinal wall layers.
A typical use of the vessel wall construction is for fabrication of modules for longitudinal midbodies of vessels for transporting flowable cargo stored in tanks each of which is defined at least in part by a layer of at least one such double walls. Some of the double walls may have a layer which forms an external boundary of the vessel, i.e., it forms part of a bottom wall or side wall of a hull. In such instances, one of the wall layers forms part of an outer hull, and the other forms part of an inner hull. In other instances, a double wall may provide a longitudinal bulkhead internally of a vessel hull, e.g., extending vertically between a bottom wall and a deck so as to divide the internal space enclosed by the hull, into a greater number of mutually isolated cargo tanks, arranged on transversally opposite sides of the longitudinal bulkhead.
Typically, in such vessel longitudinal midbody constructions, each module is a longitudinal segment of the whole, each is fabricated so as to have, not only a hull portion (including a deck portion) and possibly one or more longitudinal bulkheads, but also a transverse bulkhead, preferably provided at one end of the respective module. The modules are serially welded together end-to-end to provide a vessel longitudinal midbody. A vessel bow member is welded to one end of the longitudinal midbody, and a vessel stern member is welded to the opposite end of the longitudinal midbody, in order to constitute a complete vessel. The longitudinal bulkheads (if provided) and transverse bulkheads internally divide the space enclosed by the vessel hull into a plurality of cargo tanks. Other equipment normally provided on the particular type of vessel can be installed, as will be appreciated by those skilled in the art.
In each double wall of the vessel hull, and longitudinal bulkhead(s) (if provided), the wall layer-interconnecting plates which join the two wall layers at the plate-to-plate edge joints divide the space within each such double wall into a plurality of compartments or cells each delimited by two wall layers, two wall layer-interconnecting plates, and two transverse bulkheads.
Some of these cells can be intended to remain empty in use, or to act as pipe chaces, keel ducts, ventilation ducts or have other uses than carrying cargo. Not unusually, some can be intended for carrying (typically) sea water or river or lake water as ballast, for helping maintain a sufficiently low center of gravity and high density as to permit safe vessel operation when the cargo tanks are partly or completely empty.
In conventional double-hulled vessels, the plates which interconnect the inner and outer hulls are often provided with openings. These permit the vessel operations to fill and empty the compartments with ballast without providing piping to each compartment. They also permit the vessel operators to inspect the compartments (when the compartments are emptied of ballast), e.g., looking for corrosion damage and leaks from or to the compartments, indicating a need for repairs and maintenance. In such conventional double-hulled vessels, the openings from one compartment to the next are all aligned from plate to plate, girthwise.
This conventional layout can be the source of several problems which have safety implications.
If all the openings are provided near one end of each module, ventilation efforts will tend to be more effective at the module end that is near the openings; fumes due to leaks from the cargo tanks into the cells will tend to build towards unsafe levels at cell ends furthest from the openings while ventilation is being conducted.
Inspectors and repairers, who are climbing through the cell array, from cell to cell on ladders conventionally provided, should they slip, could fall, drop through an opening, continue to fall through the next compartment and next opening, and so on, striking ladder rings and the edges of openings, and thereby becoming seriously injured. If the ventilator or respirator that the worker is wearing is not operating properly, or has been removed by the worker, fumes that have built up at a poorly ventilated far end of a compartment could cause the worker to become dizzy, disoriented or subject to blacking out while, after walking the length of the compartment to its ventilated end, they had stepped onto the ladder to climb up or down to a neighboring compartment.
The wall layer-connecting plates in a conventional double-hulled tanker may be simple flat plates having such access openings, or they may be stiffened by stiffening ribs or plates welded or otherwise secured thereto (typically to one face, and running crosswise of the plate). A typical wall layer-connecting plate is about seven feet wide, fifty feet long, spaced about eight feet from its closest neighbors, and its access openings are two feet in diameter. The access openings may be provided with sealable hatches for selectively closing them, or they may be simple openings that are intended to remain always open. Such access openings can also be called manholes.

Double-layered vessel wall construction with longitudinally staggered cell-to-cell access openings through wall layer-connecting plates


A combination of circuits is responsive to a respective one of a definite number of operation patterns of a plurality of PTCs, the operation patterns being different therebetween and including a plurality of first patterns each respectively representative of an operating state of a corresponding PTC thermally operated, for providing a signal with a corresponding one of a definite number of signal states representing the operation patterns, respectively, and a common LED is operable by the signal with a respective signal state to provide an identifiable indication relative to an indication by the signal with any other signal state.

1. Field of the Invention
The present invention generally relates to a thermistor (thermally sensitive resistor) monitor system, and particularly, it relates to a monitor system a light emitting diode (hereafter "LED") for monitoring a thermistor network composed of a plurality of thermistors of a kind, such as a positive temperature coefficient thermistor (hereafter "PTC"), a critical temperature resistor (hereafter "CTR") or a negative temperature coefficient thermister (hereafter "NTC"), to display an operating state of the thermistor network, indicating, if any, a thermistor having a significantly changed resistance relative to a normal state in an identifiable manner.
2. Description of Relevant Art
The thermistor is a collective nomenclature of electronic components each respectively comprising a semiconductor extremely sensitive to its temperature so that its electric resistance greatly changes in dependence on the temperature relative to a state in a temperature range under a normal working condition, and has a non-linear temperature coefficient that is positive in PTC or negative in NTC or suddenly drops in CTR at a critical temperature.
The thermistor has a wide range of applications, where it is frequently employed in the form of a network to be monitored with one or more LEDs. Such a thermistor network comprises a plurality of identical thermistors with or without interconnections therebetween.
For example, a PTC network is employed for protection of loads in an electrical system, and occasionally some PTCs conduct large currents due such as to faulty loads that may be short-circuited, having their temperatures increased, entering their apparent open states to interrupt current conduction therethrough. Such a PTC network needs monitoring in a manner identifiable of a respective PTC automatically operated to be apparently open.
FIG. 1 shows a conventional PTC monitor system in a simplified form, and FIG. 2, another conventional PTC monitor system.
The conventional system of FIG. 1 comprises a pair of monitor circuits 2a+3a, 2b+3b each comprised of an LED 2a or 2b and a resistor 3a or 3b connected in series. The monitor circuits 2a+3a, 2b+3b are each connected across a corresponding one of two PTCs 1a, 1b that are installed in a pair of electric circuits connected in parallel between a power supply and a ground. The electric circuits are each constituted with an electric load 4a or 4b, and one PTC 1a or 1b is connected thereto in series.
If the PTC 1a or 1b is operated with e.g. a short-circuit in associated load, a corresponding one 2a or 2b of the two LEDs has a changed brightness with a varied current conducted therethrough, thereby indicating an operating state of the PTC 1a or 1b.
The conventional system of FIG. 2 also monitors two PTCs 1a, 1b that are installed in a pair of electric circuits connected in parallel between a power supply and a ground, which electric circuits are each constituted with an electric load 4a or 4b. This system however comprises a single monitor circuit comprised of an LED 2 and a resistor 3 connected thereto in series. The monitor circuit is connected at its positive pole end to a power supply end of each PTC 1a, 1b and at its negative pole end via a forward diode 5a, 5b to a load end of the PTC 1a, 1b
If either PTC 1a or 1b is operated, the LED 2 has a changed brightness, indicating an operating state of a combination of the PTCs 1a and 1b.
In the former system, two PTCs are individually monitored by two LEDs, which means any increase in number of PTCs requires an identical increase in number of LEDs, causing an undesirable increase in number of circuit components accompanying a dear cost.
In the latter system, two PCTs are monitored with a common single LED failing to identify which PTC is operated to be apparently open.
Similar circumstances appear with respect to other thermistors.


There is provided a HVAC system comprising: a fluid circuit for conveying a refrigerant; a compressor for compressing the refrigerant; three heat exchangers defining an evaporator, an outdoor exchanger and a heat recovery exchanger provided along the fluid circuit; an expansion valve provided along the fluid circuit; and a receiver connected in parallel to the expansion valve, wherein a fill valve is located between the receiver and a connection upstream of the expansion valve and a drain valve is located between the receiver and a connection downstream of the expansion valve; wherein the fluid circuit comprises a plurality of valves which are configured to be controlled based on a selected operating mode such that at least one of the outdoor exchanger and the heat recovery exchanger is connected to a discharge line of the compressor and in series with one of the other heat exchangers which is connected to a suction line of the compressor, with the expansion valve disposed between the heat exchangers; wherein the fill and drain valves are configured to be controlled to store a volume of refrigerant in the receiver so as to provide an effective refrigerant charge in the fluid circuit that corresponds to the selected operating mode.

Four-pipe HVAC systems comprise separate heating and cooling portions, each having its own heat exchanger coil with supply and return pipes. The heating and cooling portions can be operated independently such that four-pipe systems are able to provide simultaneous heating and cooling.
Four-pipe systems have a number of modes based on the desired operation. The effective volume of the system varies depending on the mode of operation being used (e.g. based on the volume of the heat exchanger(s) utilised in the mode of operation). Consequently, the volume of refrigerant (i.e. the refrigerant charge) in the system is typically a compromise to provide the best overall performance.
However, it is desirable to provide a four-pipe system which has improved performance.


A system and method for displaying the status of a patient on ventilation is disclosed including a ventilator system configured to provide mechanical ventilation to a patient and a display device operatively associated with the ventilator system. The display device is configured to display a user interface including a pictogram having patient status information related to the ventilator system. The pictogram includes a central section configured to display patient status information relating to an overall status of the patient and at least one group section configured to display patient status information relating to a particular category of ventilatory status parameters.

Mechanical ventilation is often an essential, life-saving therapy for critically ill patients and patients experiencing respiratory failure. Critical care ventilators provide ventilator support and display patient data to assist caregivers with determining the ventilatory status of a patient. Current generation critical care ventilators provide caregivers with a large quantity of information from which to make critical determinations about the patient's status. For example, ventilatory data is typically provided in the form of graphs, numbers, and other similar elements shown on one or more status screens.


A low voltage dimmer for LED lamps incorporates an AC-DC power supply along with a Pulse Width Modulator (PWM) to modify the power delivered to an LED load is configured to fit inside the form factor of a standard single gang electrical to control the intensity of the light emitted by the LED. The PWM portion of the dimmer circuit incorporates a microprocessor configured to produce a train of output pulses and controlled by a variable input voltage to modulate the output duty cycle of these pulses to drive one or more LED lamps to switch between “on” and “off” conditions. Variation of the duty cycle of the pulses regulates the total amount of time in each cycle that the lamp is illuminated, with the aggregate “on” time determining the apparent brightness of the lamp.

1. Field of the Invention
The present invention relates, in general, to control circuits for Light Emitting Diode (LED) illumination devices, and more particularly to an economical, low-voltage dimmer control configured for use in a standard electrical box of the type typically used, for example, in residential lighting installations, for controlling the brightness of LED lamps.
2. Discussion of the Prior Art
Traditionally, LED illumination devices have been used as low power indication devices and for low power electronic displays, principally because they were small and long-lasting, and because they used very small amounts of power as compared to incandescent bulbs, neon tubes or other light sources. As materials science and semiconductor fabricating technologies progressed, it became feasible to manufacture LEDs that would generate an increased amount of light per device (i.e., having greater luminous intensity, or brightness) in a wider variety of colors, with the result that LED lighting has recently found applications in a variety of new areas. Since LEDs more efficiently convert electrical energy into visible light and because the energy usually wasted as heat is much lower for LEDs than for most other sources of light, LED lights are between 5 and 10 times more efficient than incandescent lights, and about 2 to 3 times more efficient than fluorescent lights.
Recently, it has become economically feasible to make relatively high output LEDs which render a pleasing white light, and these newer LEDs have been incorporated into automotive and traffic signaling lamps, handheld flashlights and a variety of other products. In addition, LED lamps have become viable for use in residential and other illumination fixtures, and they can now be obtained in a configuration having a standard Edison-style base for use, for example, in an ordinary lamp socket configured for standard incandescent bulbs.
The particular characteristic of the LED which remains unchanged by these recent developments, however, is that, being a solid-state Diode, it typically has only two states; namely, "on" or "off." Therefore, users seeking to adjust the illumination from an LED lamp were confounded by this characteristic, and those who wanted a light that could be controlled with a standard "dimmer" were frustrated, because the common technique for dimming incandescent bulbs by lowering the supply voltage, when applied to an LED lamp typically would only turn the lamp from "on" to "off".
Standard dimmers are readily available to consumers for use in "single-gang" electrical boxes, where they are often installed instead of a standard single-throw light switch in residential and commercial lighting applications. The space in that single gang box is limited, however, since it is about 1.50″ wide, 2.25″ long and 1.25″ high, and there is no way, at present, to provide a dimming control at suitable power levels for driving LED lamps, where the dimming control circuitry will fit in such a tight spot, for prior approaches were cumbersome and expensive.
Some of the newer LEDs can be powered directly from a 120V supply line, but these tend to be expensive and many of them cannot be dimmed, and when used in ambiance lighting, they have the tendency to be too bright. LEDs using lower voltage levels are more economical, but the circuitry used to switch or modulate a voltage signal has typically required too much power, generated too much heat and taken up too much space to be useful for anyone but a technician who has the space and budget to assemble the power supply and pulse width modulating or switching components needed to generate a useable dimming signal. There is a need, therefore, for an economical and easy to use low voltage LED dimmer controller for overcoming these problems, and providing an economical and convenient-to-install structure which can work in typical residential lighting installations.

Low voltage LED dimmer with integrated universal switch mode power supply


A single ended line sense amplifier having an input coupled to a single ended line having a near end and a far end device comprises a plurality of nFET stacks coupled between the near end of the single ended line and the far end of the single ended line, a single ended line comparator coupled to the near end of the single ended line configured to compare a voltage at the near end of the single ended line to provide a logic state output, and a charge transistor coupled to the single ended line at a point that is between the near end of the single ended line and the far end of the single ended line to shift occurrence of snap back from strong charging of the single ended line.

Content addressable memories ("CAMs") are commonly used in cache and other address translation systems of high speed computing systems. Ternary content addressable memories ("TCAMs") are ternary state CAM cells and are commonly used for parallel search in high performance computing systems. The unit of data stored in a TCAM bitcell is ternary, i.e., having three possible states: logic one, logic zero, and don't care state (referred to as an "X" state). To store these three states, TCAM bitcells include a pair of memory elements.
CAMs permit its memory cells to be referenced by their contents. Thus, CAMs have found use in lookup table implementations such as cache memory subsystems and are now rapidly finding use in networking system applications such as network address translation, and other applications such as pattern recognition and data compression. CAMs' most valuable feature is its ability to perform a fast search operation in which search data is compared with stored data. Typically, a searched data word is loaded onto search lines and compared with stored data words in the CAMs. The stored data words are compared bit-by-bit with the searched data word. During a search-and-compare operation, the CAMs perform a parallel search and generates match or mismatch signal associated with each stored data word, indicating whether the search word matches any of the stored data words.
FIG. 1 illustrates a prior art block diagram for TCAM unit cells connected to a match line sense amplifier. TCAM bitcells 10 that form a data entry can be connected along the same row and connected to a match line ML, word lines WLY and WLX, and search lines ST and SC. A match line sense amplifier 20 is connected to an end of the match line. Each of the TCAM bitcells 10 comprise two static random-access memory ("SRAM") cells (or dynamic random access memory ("DRAM") cells, depending on the implementation) and a compare circuit 12 (e.g., an XOR circuit) to compare the data within the respective TCAM bitcell with bits of the searched data word.
An indication of a match or mismatch is indicated on the match line. The compare circuits 12 of the TCAM cells 10 of a stored data word can have their respective outputs logically dotted together in a dot-XOR structure via the match line. If any of the compare circuits 12 are on (i.e., driving the match line to a low state to indicate a mismatch), a mismatch can be identified for that respective stored data word. If the match line goes to a high state, then the stored data word can be identified as a match and the location of that data entry is outputted.
FIG. 2 illustrates a prior art block diagram for compare circuits of TCAM bitcells connected to a match line sense amplifier. As indicated above, the compare circuits 12 of the TCAM data entry are connected together via the match line. Due to the large number of compare circuits 12, the match line can be highly capacitive. The match line is further coupled to a match line sense amplifier 20 at one end of the match line to charge the match line and to detect a voltage on the match line. Due to their inherent parallel structure and charging required for operation, the match line can consume large amounts of power. For this reason, TCAMs require relatively high power and large current pulses to operate the compare function circuitry (e.g., match and search line pulsing) and for match line sensing. In order to produce fast compare circuits, large amounts of power are consumed to quickly recharge the match line to its high state in preparation for another data match comparison. Because the match line is highly capacitive and the match line sense amplifier is high powered to quickly charge the match line, a phenomena known as snap back occurs.
FIG. 3A illustrates a prior art block diagram of an equivalent circuit for a match line sense amplifier 20. The match line sense amplifier 20 is coupled to match line 23 and includes a match line charger 21 controlled by signal CM_B, and a sense inverter 22. The equivalent circuit of match line 23 includes a plurality of nFET stacks 24 and a resistor between the nFET stacks 24 which represent an equivalent resistance of a section of the metal match line 23. Match line 23 is a single line with a match line far end, ML_FAR, and a match line near end, ML_NEAR. The ML_NEAR end is coupled to the input of match line sense amplifier 20. For ease of understanding and not to obscure the invention with detailed signals, match line charger 21 charges the match line 23 to a high state when signal charge match, CM_B goes to a low state, the signal CM_B denotes an active low. Stated differently, as signal CM_B become active, the match line 23 is charged until a voltage at the input of sense inverter 22 of the sense amplifier 20 becomes a high state and turns off the signal CM_B. The match line has a given length and there is a metal resistance associated with the length. As the match line charger 21 quickly charges the match line 23, voltage throughout the match line 23 cannot change instantaneously and there is noticeable delay before the voltage reaches a steady state throughout the length of the match line 23. For example, a voltage measurement at match line near end, ML_NEAR is different from a voltage measurement at match line far end, ML_FAR because metal resistance and capacitance of the match line 23 introduces an RC time constant delay as the match line is robustly charged.
FIG. 3B illustrates a voltage vs time graph showing a snap back phenomena of a prior art match line. Graph 32 represents the output of sense inverter 22. As the voltage on the match line is quickly charged at the match line near end, voltage at ML_NEAR of the match line as shown by graph 34 increases in excess of the match line trip voltage at which point the match line charger 21 is turned off. A snap back phenomenon occurs as the voltage shown by graph 34 falls back to the match line far end, ML_FAR of the match line as shown by dotted graph 36. The voltage at the far end of the match line ML_FAR lags behind the voltage at the near end due to capacitance and resistance of the match line. Given enough time, the voltage at the match line near end, ML_NEAR and the match line far end, ML_FAR of the match line will eventually merge. However, since the sense inverter 22 senses voltage at the match line near end, ML_NEAR, and the overshoot is at the match line near end, ML_NEAR, the overshoot can reach the trip point of the sense inverter 22 thereby stopping the charge to the match line. Problem arises when the difference from the snap back voltage causes the sense inverter 22 to trip prematurely. Referring to graph 34, the trip point of the sense inverter 22 is set at approximately 400 millivolts. Because of the snap back phenomenon, the sense inverter 22 can be tripped when the voltage from graph 34 reaches the highest point. As the match line charger 21 is turned off, the voltage at the ML_NEAR and the voltage at the ML_FAR charge equalize, which cause the voltage at the ML_NEAR to snap back. The snap back phenomenon can cause the match line sense amplifier 20 to begin charging again. The snap back phenomenon causes havoc to match line sense amplifiers for single ended line sensing. As devices become smaller and voltage margins become tighter, the snap back phenomenon becomes even more of a problem for circuit designers.
For the foregoing reasons, there is a need for new methods and apparatuses for a sense amplifier the overcome the problem associated with quickly charging a single match line for single ended line sensing.

Sense amplifier for single-ended sensing


This invention relates to a lighting or indicator device, in particular for motor vehicles, comprising at least one light source and at least one output optical system in order to form a lighting or indicator lamp beam consistent with regulations. In accordance with this invention the device comprises at least one input optical system comprising a collimating element receiving light rays emitted by the source and transmitting a beam of parallel rays towards an output optical system which forms a lighting or indicator lamp beam.

I. Field of the Invention
This invention relates to lighting or indicator devices intended for motor vehicles in particular. Lighting devices mainly comprise the lamps for dipped, main, fog or running lamps, and the indicator lamps mainly comprise position lamps, direction change indicator lamps, braking indicator lamps, reversing lamps, and rear fog lamps.
In order to simplify location of these various devices on a vehicle it is normal practice to group several together in a single housing, which in particular makes it easier to install them on the vehicle, and to connect them to the vehicle's electrical loom using a single connector provided with an appropriate number of terminals.
Each function generally incorporates a light source, a reflector reflecting the light rays emitted by the source in a general direction of emission, and possibly an enclosing glass, also called an indicator, which may or may not contribute to formation of the light beam, these various components being designed to provide a lighting or indicator beam whose geometrical and photometric characteristics must comply with various regulations. The glass enclosing the housing or indicator is generally common to all the devices present in the same housing.
Each function thus requires a minimum space for location within the individual lighting or indicator device. However the volume available for locating lighting or indicator devices both at the front and rear of a modern motor vehicle is increasingly smaller. In fact the constraints of aerodynamics and stylistic design lead to shapes which are often very different from those which would result from technical considerations alone.
It follows that in many cases three constraints apply simultaneously to the designers of lighting or indicator devices:
i) the light beams must be emitted parallel to the longitudinal axis of the vehicle,
ii) the glass enclosing the housing must have a shape which may at the same time be highly curved and highly inclined in relation to the vertical, and
iii) the volume available within the housing for locating the various optical systems is relatively small.
It is possible to provide lighting or indicator devices in which the light sources, such as electroluminescent diodes, are positioned on a flat surface, with or without a reflector, and with or without diffusing screens, regardless of the external shape of the lighting or indicator device or its enclosing glass. Although such a design is of low cost, it is unable to provide lighting or indicator devices whose styling is suitable for modern vehicles.
Furthermore, if it is desired for example to provide an indicator lamp which is curved in at least one direction, it is generally provided that the light sources are arranged in such a way that the electroluminescent diodes are located in a regular arrangement, i.e. in a matrix of lines and columns when seen from the front. Such design is relatively constricting. Furthermore, if the lighting or indicator device has a curvature in two directions it is in most cases necessary to bend the surface supporting the light sources in two directions, which is relatively complicated.
II. Description of the Related Art
Various solutions have already been suggested in order to overcome these problems. For example a collimating optical component for an indicator lamp which is designed to be associated with a supporting member having electroluminescent diodes incorporating a dorsal surface which acts together with these electroluminescent diodes, the dorsal surface being shaped in steps onto which transverse openings associated with the electroluminescent diodes open, is known from document FR-A-2 680 859.
Such design makes it possible to design a robust optical element, the diodes being located in the appropriate places. They are supported on strips belonging to the supporting member which usually comprises such an indicator lamp. The diodes may also be located as a sandwich between the strips and the steps so that the diodes can be located in the appropriate position, in particular at the focus or optical centre of the openings in the collimating element, despite the awkward shape of the indicator lamp.
It has already been suggested in document EP-A-1 110 817 that an electroluminescent diode power circuit which may have a curved shape, possibly in two different planes, might be constructed instead of a matrix arrangement based on a flat plane. Such a process for the manufacture of an electroluminescent diode power circuit located on planar supports which are parallel to each other comprises the stages of:                determining the relative positions of the supports,        determining whether there is a set of planes perpendicular to the supports, which are parallel to each other, each of which passes through at least one support and such that in each plane the supports have corresponding coordinates relating to a first axis perpendicular to the support which vary uniformly with their abscissas along a second axis parallel to the supports and the planes,        determining a reference plane parallel to the supports,        determining the image of each support by a projection following the same projection axis on the reference plane followed by translation in relation to the second axis by a length equal to the distance of the support along the projection axis, and        linking the images by connecting branches located within the reference plane.
This document also discloses a base for a power circuit for electronic components such that electroluminescent diodes, which are for example constructed using the process which has just been mentioned, and comprising supports for components, the base being of flat shape, the supports being located in such a way that it is possible to make cut-outs in the base so that by forming folds which are parallel to each other the base can be given a shape such that the supports are planar and parallel with each other, and at least some supports are intercepted by a single plane parallel to the folds and perpendicular to the supports, are not coplanar.
Such a process is relatively complex to implement, and requires thorough investigation of the location of the lamp to determine the lines for folding the base for its electrical power circuit. It follows that the lighting or indicator devices so obtained offer greater development possibilities for the stylists, but have relatively high costs which restrict their use to top-of-the-range vehicles.

Lighting or indicator device, in particular for motor vehicles


A wrist includes a wrist housing including a wrist driving structural portion to which rotation is transmitted from a wrist driving pulley, a cylindrical portion arranged coaxially with a rotational axis of the wrist driving structural portion and penetrated by a first hand driving shaft to which rotation is transmitted from a hand driving pulley, a cable introducing portion forming an annular gap with the cylindrical portion, and a hand-driving-shaft penetrating portion penetrated by a second hand driving shaft rotating a hand interface by rotation of the first hand driving shaft being transmitted thereto, and a cable, which comes out of a second arm from a wrist supporting portion, is drawn into the wrist housing from the annular gap and is routed to a hand interface supporting portion in a slackened state.

There are vertically articulated robots in which the wrist drive mechanism (a 5-axis drive mechanism in the case of a 6-axis multi-joint), which supports the wrist (a 5-axis portion in the case of a 6-axis multi-joint) from both sides by the wrist supporting portions provided at the end of the arm and vertically rotates the wrist, and the hand drive mechanism (a 6-axis drive mechanism in the case of a 6-axis multi-joint), which inwardly and outwardly rotates the end effector (a 6-axis portion in the case of a 6-axis multi-joint) arranged on the wrist, are coaxially arranged.
When the wrist drive mechanism and the hand-portion drive mechanism are arranged in the wrist supporting portion on the same side, the distance from the center of the arm becomes significantly different between the right and left sides. Therefore, in order to prevent interference when the robot is driven, it is necessary to set the interference prevention area with reference to the wrist supporting portion having a greater distance from the center of the arm. Consequently, the interference prevention area increases.
Patent Literature 1 discloses a robot that incorporates the hand drive mechanism in the wrist without the wrist drive mechanism and the hand drive mechanism being coaxially located. With this structure, the difference in thickness between the right and left wrist supporting portions supporting the wrist can be reduced compared with the case where the wrist drive mechanism and the hand drive mechanism are arranged on the same side.


A method, apparatus, computer-readable media and user interface for annunciating problems in a system. The method involves producing signals for concurrently indicating a plurality of system problems and problem priority information associated with the system problems based on data representing system conditions. Such signals may be used to drive a display device. Operator input signals may be received to permit selection of a particular problem for which details are provided. The indication of priority information assists a system manager or operator to quickly prioritize system problems according to different perspectives provided by different priority information. Optionally, the operator can also view any of the detailed information related to the particular system problem, which may include alarm information, performance degradation information, service violation information, or penalties or lost income, for example.

1. Field of Invention
This invention relates to the management of systems and more particularly to methods, apparatus, computer-readable media and a user interface for annunciating problems in a system.
2. Description of Related Art
Tools exist for the management of system problems, such as those encountered in telecommunications networks. These system management tools typically operate on a PC or UNIX workstation and enable the maintenance, surveillance and administration of multiple telecommunications network elements making up the system. Such tools provide for management of the network, that is, monitoring alarms, monitoring performance, managing connections and testing for faults.
An objective of existing system management tools is to provide a centralized view of a system so as to enable the operator to identify system problems from multiple events or conditions, such as alarms and performance degradations. For example, an initial root cause, such as an alarm, can often cause a cascade or flood of subsequent events through the system. Many events, such as alarms and performance degradations, can therefore be symptomatic of a single system problem. When there are many such events, it becomes difficult to determine which ones are correlated to a root cause system problem.
Some existing system management tools provide a GUI (graphical user interface) to assist the operator. One example is HP Open View Network Node Manager, provided by Hewlett-Packard Corporation of California, U.S.A. Such tools commonly represent a number of telecommunications network elements on a display in a topological configuration, but the display may be cluttered with iconic representations of a state for each network element. While such a display helps the operator to locate individual alarms or performance degradations in a system, it may not help the operator identify the relationships among these events and system problems, or root causes of problems.
Root-cause analysis tools have been developed for telecommunications networks and may correlate alarm events into problem sets, each set consisting of a direct detected alarm event and a correlated set of symptomatic alarm events. This automated correlation greatly reduces the amount of time the operator would have to spend in manually filtering the alarm events. Furthermore, such tools direct the operator's attention from dealing with individual events to dealing with overall problem sets. Some tools are capable of providing a brief probable cause description of the problem set and of providing a reference that can be used to help correct the problem set.
Most root-cause analysis tools are limited to use with certain types of alarm events. From a flood of different types of alarm events, they select one type of alarm and perform an exhaustive search for alarms of that type only. This allows many different types of alarm events to be treated as symptomatic of a single system problem.
Other tools allow an operator to examine service violations associated with an event. Often, an operator is responsible for maintaining intended service levels across the telecommunications network. These intended service levels could relate to agreements with customers, for example. There may also be penalties or costs associated with failure of the system to comply with the intended service levels described by clauses in a service level agreement (SLA), for example. Compliance of a particular telecommunications network element with a plurality of intended service levels may be crucial. Tools which provide this type of information allow the operator to examine intended service levels and observe service violations associated with a particular event or a particular telecommunications network element.
Generally existing system management tools help the operator to diagnose system problems and synthesize a great deal of information through a centralized view of the system, such as the telecommunications network described above. However, they leave a large amount of information to be synthesized by the operator, unaided. The operator may have to examine details of performance degradations to determine the system problems to which they relate. The operator may have to separately examine details of service violations to determine the system problems to which they relate, and to determine the relative importance of the system problems. The operator may use these determinations to prioritize the system problems and to schedule and plan maintenance and repair of the system. However, little is done by existing tools to summarize such details into problem priority information that could assist the operator in quickly identifying and prioritizing system problems. Consequently, there is a need for system management tools which provide a better description of system problems to permit an operator to better identify and prioritize system problems.

Method, apparatus, computer-readable media and user interface for annunciating problems in a system


A sub-block redundancy replacement memory configuration for repairing a plurality of faulty memory arrays, each consisting of a plurality of memory cells arranged in a first matrix formation, supported by first row decoders and first sense amplifiers, by combining at least two with at most n-1 out n sub-block redundancy arrays, each consisting of a plurality of redundancy memory arrays arranged in a second matrix, and supported by second row decoders and second sense amplifiers. Since additional sub-block redundancy arrays are available, it is possible to repair a defective memory array even if one or more block faults are present in the memory. The number of cells in the redundancy arrays is less than the number of cells in the memory arrays, substantially reducing the silicon overhead. Optionally, the sub-block redundancy memory arrays are distributed within at least two units, each consisting of a plurality of memory arrays, at least one sub-block redundancy array and corresponding columns decoders. The columns decoders are activated as a result of a redundancy match detection which determines whether a memory array or a sub-block redundancy memory array in any unit is activated.

CMOS technology has evolved such that the computer market has rapidly opened to a wide range of consumers. Today multi-media requires at least a 16 MB and preferably even a 32 MB memory, which increases the relative cost of the memory system within a computer. In the near future, it is likely that 64 MB and 128 MB computers will become commonplace, which suggests a potential demand for 256 Mb DRAMs (Dynamic Random Access Memory) and beyond. Still in the development stage, DRAMs in the Gigabit range are already under way, which necessitate the introduction of new techniques that guarantee the repairability of the product notwithstanding the added complexity of the design and manufacture of such memory devices. Despite the huge array size and lithographic difficulties that ensue, it is more important than ever to increase the chip yield. Process engineers are continuously attempting to reduce and, ultimately, eliminate mask defects. Faults that inevitably remain in the chip are generally overcome using special circuit designs, and, more specifically, redundancy replacement.
Conventional redundancy configurations typically employ a Fixed Domain Redundancy Replacement (FDRR) architecture, wherein redundancy elements are used to replace defective elements within a fixed size domain for each row and column redundancy.
A typical redundancy architecture commonly used for low density DRAMs is shown in FIG. 1a. Therein are depicted a plurality of spares that are used for replacing defective elements within the domain, and which are appended to each sub-array comprising the memory. Each redundancy unit (RU) includes a small number of redundancy elements (RE), (e.g., two REs per RU are illustrated herein), which are used to repair existing faults (labeled X) within the corresponding sub-array. This arrangement, labeled intra-block replacement, expands the redundancy area overhead as the number of sub-arrays increases for high density memories, since each sub-array encompasses a domain for replacement purposes, and the domains in different sub-arrays are mutually exclusive of each other. This requires at least one or, preferably, two RUs in each sub-array. Thus, the efficiency of the RUs is rather poor in view of its inflexibility. This reduces the chip yield substantially when faults are clustered in a given sub-array. The above-mentioned concept is embodied in a configuration described in an article by T. Kirihata et al., entitled "A 14 ns 4 Mb DRAM with 300 mW Active Power", published in the IEEE Journal of Solid State Circuits, Vol. 27, No. 9, pp. 1222-1228, September 1992.
A second redundancy architecture, known as flexible redundancy replacement configuration is shown in FIG. 1b, wherein a memory is depicted having a single array as a large domain of RUs to selectively replace failing elements anywhere in the memory. In this configuration, REs within the RU repair faults (labeled X) located in any sub-array within the memory. The advantage of this arrangement over the previously described intra-block replacement is that one section, namely, a redundancy array, having a certain number of RUs may advantageously be used to service any number of sub-arrays forming the memory. This translates into a significant saving of real estate over the previous scheme, although it requires a substantial amount of added control circuitry to properly service all the sub-arrays forming the memory.
More details regarding the above configurations and the various trade-off may be found in an article by T. Kirihata et al., "Fault-Tolerant Designs for 256 Mb DRAMs", published in the IEEE Journal of Solid-state Circuits, Vol. 31, No. 4, pp. 588-566, April 1996; in an article by T. Sugibayashi et al., "A 30 ns 256 Mb DRAM with Multi-divided Array Structure", published in the IEEE Journal of Solid State Circuits, Vol. 28, No. 11, pp. 1092-1098, November 1993; and in an article by H. L. Kalter et al., "A 50 ns 16 Mb DRAM with a 10 ns Data Rate and On-Chip ECC", published in the IEEE Journal of Solid State Circuits, Vol. 25, No. 5, pp. 1118-1128, October 1990.
Regardless of the intra-block replacement arrangement shown in FIG. 1a and the flexible redundancy replacement configuration illustrated in FIG. 1b, they all use wordlines or bitlines as line redundancy. Therefore, the repairability is limited to relatively small faults, such as single bit faults, wordline faults or bitline faults. Although the flexible redundancy replacement can repair somewhat larger faults, a line redundancy replacement, even with its added flexibility, finds it difficult to repair block faults when a memory block contains in excess of 1 Mb cells, as for instance, in a 256 Mb DRAM, that renders the memory device totally inoperative.
Accordingly, a third redundancy architecture has been advanced, known as a block redundancy replacement configuration and shown in FIG. 1c, wherein a block redundancy completely replaces a defective memory block. A memory block is defined as an entire memory region supported by wordline drivers and sense amplifiers. By way of example, and with reference to FIG. 1d, a 256 Mb DRAM chip (100) is shown containing sixteen 16 Mb units (105). Each unit (105) consists of sixteen 1 Mb block (110), each with a 1 Mb array (120), a sense amplifier block SA (130), and a row decoder block RDEC (140). Each 16 Mb unit (105) is also provided with one 1 Mb block redundancy (115). The advantage of this arrangement over previously described ones related to line redundancy replacement is that a block fault (i.e., 110-i, i being an integer larger or equal to 0), typically caused by the wordline driver or by a sense amplifier, can be repaired by replacing it with a block redundancy (115). A power-bus fault can also be repaired by isolating the defective block from the power-bus by replacing it with a redundancy block. As the DRAM density increases, the probability of block faults also occurring increases, an obvious yield detractor for 256 Mb DRAMs and beyond. A fuller description of a block redundancy replacement is described in an article by G. Kitsukawa et al., entitled "256-Mb DRAM Circuit Technologies for File Applications", published in the IEEE Journal of Solid State Circuits, Vol. 28, pp. 1105-1113, November 1993.
In spite of its advantages, Kitsukawa's block redundancy replacement suffers in at least one aspect, namely, it imposes a substantial penalty for its implementation. The size of a redundancy block must be equal or larger than the array block, otherwise its repairability is poor since the majority of block faults are caused by a defective wordline driver, sense amplifier, or power bus. The area penalty of the block redundancy is over 6% for the 256 Mb DRAM, assuming a conventional implementation having one 1 Mb block redundancy for each 16 Mb unit (intra-unit block redundancy). Designing redundancy blocks in a peripheral region (shared block redundancy) allows a redundancy block to be shared among others. However, added column circuitry for the redundancy block is required, which is oftentimes difficult to implement. It also increases the complexity of the wiring for the flexible block replacement, resulting in lower speeds. A detailed embodiment of shared block redundancy is discussed in an article by J. H. Yoo et al., entitled "A 32-Bank 1 Gb DRAM with 1 Gb/s Bandwidth", and published in the IEEE Journal of Solid State Circuits, Vol. 31, pp. 1635-1644, November 1996. Using column circuitry in both the normal block and the redundancy block significantly reduces the design overhead, as was the case for Kitsukawa's block redundancy replacement. Regardless, in Kitsukawa's intra-unit block redundancy and Yoo's shared block redundancy, the defective redundancy block (110-2) cannot be used even if it only contains a single fault (160). The probability of having a fault within a redundancy block is significant, reducing the effectiveness of the block redundancy. Introducing line redundancy repair means for the block redundancy element can overcome the problem; however, it requires a two-step redundancy programming, in which a redundancy block is first repaired and then having the block redundancy repair the defective block. The detailed embodiment of a two step block redundancy with variable size redundancy architecture is discussed in the article by T. Kirihata et. al., entitled "Variable Size Redundancy Replacement Architecture to Make a Memory Fault-Tolerant", filed in an U.S. patent application, Ser. No. 08/825,949 (Attorney docket FI9-97-002), in April 1997.
Other redundancy replacement configurations, including some related to the categories listed above, are described in the following references:
U.S. Pat. No. 5,491,664 to Phelan, issued Feb. 13, 1996, describes the implementation of a flexible redundancy memory block elements in a divided array architecture scheme. This configuration has both, the memory and redundancy memory blocks, coupled to a read bus to allow the redundancy memory in one memory sub-array to be shared by a second sub-array.
U.S. Pat. No. 5,475,648 to Fujiwara, issued Dec. 12, 1995, in which a memory having a redundancy configuration is described such that when an appropriate address signal agrees with the address of a defective cell, a spare cell provided by the redundant configuration is activated to replace the failing one.
U.S. Pat. No. 5,461,587 to Seung-Cheol Oh, issued Oct. 24, 1995, in which a row redundancy circuit is used in conjunction with two other spare row decoders, wherein by a judicious use of fuse boxes, signals generated by a row redundancy control circuit, make it possible to replace failing rows with spare ones.
U.S. Pat. No. 5,459,690 to Rieger at al., issued Oct. 17, 1995, describes a memory with a redundant arrangement that, in the presence of normal wordlines servicing defective memory cells, enables faulty memory cells to be replaced with redundant cells.
U.S. Pat. No. 5,430,679 to Hiltebeitel et al., issued Jul. 4, 1995, describes a fuse download system for programming decoders for redundancy purposes. The fuse sets can be dynamically assigned to the redundant decoders, allowing a multi-dimensional assignment of faulty rows/columns within the memory.
U.S. Pat. No. 5,295,101 to Stephens, Jr. et al., issued Mar. 15, 1994, describes a two level redundancy arrangement for replacing faulty sub-arrays with appropriate redundancy elements.
Whereas the prior art and previous discussions have been described mainly in terms of DRAMs, practitioners of the art will fully appreciate that the above configurations and/or architectures are equally applicable to other types of memories, such as SRAMs, ROMs, EPROMs, EEPROMs, Flash RAMs, CAMs, and the like.

Sub-block redundancy replacement for a giga-bit scale DRAM

International Business Machines Corporation


Systems and methods for map-based lottery games are disclosed. According to one particular embodiment, a method for a map-based lottery game may comprise: establishing a game having a gameboard based on a map that includes a plurality of units; receiving from each of a plurality of players a selection of at least one available unit on the gameboard; uniquely associating each said player with the selected at least one unit such that each unit on the gameboard is associated with no more than one of the plurality of players; and conducting a lottery drawing to select at least one first unit from some or all of the plurality of units such that any player associated with said at least one first unit becomes a first winner of a prize.

Lottery is a popular game of chance in which a number of players contribute to form a jackpot that is later awarded, wholly or partially, to one or more winners. The participating players pay money or contribute other things of value in exchange for lottery tickets. Typically, each lottery ticket bears a combination of numbers or other symbols, and a winning ticket has to at least partially match a randomly generated set of numbers or symbols. In a properly operated lottery game, any one of the outstanding lottery tickets could be selected in a random drawing as a winning ticket, entitling its holder to some or all of the jackpot prize.
Sweepstakes in United States may be considered one special type of lottery games which are free to enter and are typically sponsored by merchants for promotional marketing purposes. In United Kingdom, a sweepstake is technically a lottery game in which the prize is financed through the tickets sold. Small-scale sweepstakes among private parties (e.g., colleagues and classmates) may also be considered lottery games which are often related to ongoing sports events.
Lottery games come in different formats. For example, the jackpot of a lottery game may be either a fixed cash amount or a certain percentage of ticket revenue. The combination of numbers on each lottery ticket could be a unique one, or each player may be allowed to select his or her own lucky numbers, making it possible for multiple tickets to share a same combination. Lottery games can be played either online or offline. The most popular lottery games, such as Powerball™, Mega Millions™, and Euro Millions™, are mostly paper-based, requiring the purchase of actual tickets, although some are now starting to open to online participants. A few lottery games can be played completely online. That is, instead of purchasing a paper ticket and filling in desired numbers with a pencil, an online player can purchase an electronic (or virtual) lottery ticket and select a desired combination via a web interface such as an Internet browser.
In all traditional lottery games, lottery tickets are sold in predetermined, fixed denominations, for example, one dollar per ticket. Accordingly, one winning ticket will entitle its holder to an entire unit of a corresponding winning prize. Proportional value lottery games have been proposed, for example, in U.S. Pat. Nos. 6,296,569 and 7,351,142, but none appears to have been commercially implemented. Both of those patents describe the issuance of proportional denomination lottery tickets, online or at a point of sale (POS). For example, in any transaction involving change under a dollar, the change can be converted to a proportional denomination share of a full-unit (one-dollar) lottery ticket. If the full-unit lottery ticket is qualified for a prize, the holder of the proportional denomination ticket will be entitled to a fraction of the prize. For instance, if a one-dollar ticket matching all the winning numbers would entitle its holder to a jackpot amount, then a 25-cent proportional ticket entitles its holder to 25% of the jackpot.
All the existing types of lottery games appear to share a few common characteristics. First, they all have to issue some kind of lottery tickets, whether paper or electronic, full-denomination or proportional. The purposes for issuing lottery tickets are two-fold. The tickets bear numerical combinations or patterns to be compared to the randomly generated winning combination or pattern. The tickets also serve as proof of participation in the lottery games. However, the entire mechanism of generating, drawing, and matching tickets could impose significant overhead costs on the operation of lottery games.
Second, participation in traditional lottery games depends heavily on player impulse or enthusiasm, which causes ticket revenue to fluctuate. Except for a handful of gambling fanatics, most people only purchase lottery tickets occasionally. A loss in one game might cause an ordinary player to stop playing for a while. Also, public sentiment towards a lottery game often varies with the amount of jackpot prize available at the time. There seems to be a general belief that a one-dollar ticket somehow has a better chance of winning when the jackpot reaches several million dollars or more. At the very least, the nature of the game is such that the economic utility to the player of participating is not determined solely by the probability of winning the jackpot nor the expected return on playing; rather the higher the jackpot the greater the excitement of playing—i.e. this is a motivator to play. Similarly, the greater the chance of winning a small prize, the higher likelihood that players will repeatedly play. This is in part because winning even a small prize reinforces in the player's mind the possibility of winning the jackpot and in part because a game most players never won any prize at all would be perceived as unfair or boring. Therefore, when the total jackpot snowballs into an unusually large amount, the public often become increasingly interested in the game. Once the jackpot is won, a period of stagnation typically follows the news-generating big win. For all these reasons, ticket revenues from traditional lottery games tend to swing with time and seldom generate a steady cash flow.
Third, players in a traditional lottery game have no direct or perceivable incentive for bringing more players into the game. Theoretically, an existing player may be indirectly benefited if more players join the lottery game, because the increased participation will increase the size of jackpot the existing player could potentially win. However, other than in very small games, that potential benefit may not be tangible enough to encourage referrals of additional players. In addition, the existing player's chance of winning does not increase with the number of new players.
Furthermore, traditional lottery games including sweepstakes are pure games of chance and typically do not require any player skill or strategy. Every player's chance of winning is only affected by the number of lottery tickets he or she buys. One player's chance of winning is independent of another player's chance of winning. As a result, there tends to be very little interaction among lottery participants.
In view of the foregoing, it may be understood that there are significant problems and shortcomings associated with traditional lottery games.


The present invention relates generally to plasma processing chambers and electrode assemblies used therein. According to one embodiment, an electrode assembly comprises a thermal control plate, a silicon-based showerhead electrode, and a probe assembly comprising an electrically conductive probe body and a silicon-based cap. The electrode assembly is configured such that the handedness of a threaded engagement of the silicon-based cap and a head section of the probe body and the handedness of the threaded engagement of the thermal control plate and a mid-section of the probe body have a common direction of rotation. Thereby, an application of torque to the silicon-based cap in a tightening direction of rotation tightens both threaded engagements. Further, the electrode assembly is configured such that the threaded engagement of the silicon-based cap and a head section of the probe body permits repetitive non-destructive engagement and disengagement of the silicon-based cap and the probe body.

The present invention relates generally to plasma processing and, more particularly, to plasma processing chambers and electrode assemblies used therein. Plasma processing apparatuses can be used to process substrates by a variety of techniques including, but not limited to, etching, physical vapor deposition, chemical vapor deposition, ion implantation, resist removal, etc. For example, and not by way of limitation, one type of plasma processing chamber contains an upper electrode, commonly referred to as a showerhead electrode, and a bottom electrode. An electric field is established between the electrodes to excite a process gas into the plasma state to process substrates in the reaction chamber. Embodiments of plasma processing chambers and showerhead electrode assemblies used therein are described in U.S. patent application Ser. No. 11/871,586, filed Oct. 12, 2007, the entire disclosure of which is hereby incorporated by reference.

Electrode/probe assemblies and plasma processing chambers incorporating the same


Article, such as sports bras, and methods of making the same are described. A sports bra may comprise a front panel comprising a bust panel, a first shoulder strap, and a second shoulder strap. The sports bra may comprise a rear panel comprising a first back strap and a second back strap. The first back strap may coupled to the first shoulder strap at a first shoulder seam and the second back strap may coupled to the second shoulder strap at a second shoulder seam. The first back strap may be coupled to the bust panel at a first side seam and the second back strap may be coupled to the bust panel at a second side seam. One or both of the back straps may have the second a curve-linear shape exhibiting a tapered width.

In the state of the art, various sports bras have been proposed to provide support for a wearer by including an elastic band disposed at or near the ribs of a wearer to supplement any inherent elasticity in the other portions of the sports bra. Such elastic bands may be less elastic than a material of panels forming the body of the sports bra to secure the sports bra to the torso of the wearer.
As an example, U.S. Pat. Nos. 4,174,717 and 4,311,150 to Schreiber et al. each discloses an athletic brassiere which is designed to hold the breasts snugly to the body. A wide elastic rib band and elastic strips which cross in the back hold the brassiere firmly in place.
U.S. Pat. No. 4,583,544 to Flanagan et al. describes a sports bra having an elastic band attached to the bottom of said front and rear panels and extending continuously around said brassiere.
U.S. Pat. No. 4,816,005 to Braaten describes a sports bra having a continuous bottom edge with an elastic band secured to the bottom edge and coextensive with front and rear panel sections.
U.S. Pat. No. 7,381,113 to Hori describes a sports bra having an elastic band disposed about the lower edges of an inner fabric layer and an outer fabric layer to limit the transverse movement of breast cups of the bra.
In many instances, the sports bras of the prior art including a circumferential elastic band may cause irritation or discomfort to a wearer at a region where the elastic band secures the sports bra to the wearer. As such, improvements in sports bras and other articles of clothing are needed.

This patent is subject to a terminal disclaimer.