An opening arrangement for packaging containers designed so as to prevent splashing or spraying of liquid contents on reclosure of the opening arrangement. The opening arrangement (1) has a closure device (4) with a front end depressable into the pouring opening (5) of the opening arrangement, and a rear compression portion (10) of greater cross sectional area than the pouring opening (5). The compression portion (10) includes arrest heels (14) facing towards the pouring opening (5), the arrest heels, on reclosure of the opening arrangement, coming into contact with the wall surface (3) located around the pouring opening (5) and preventing any possible residual contents (9) thereon from causing splashing in connection with the reclosure operation.

Packaging containers for certain consumer products, for example liquid foods such as milk, juice or the like are often manufactured from a flexible material which is folded and sealed for the formation of a packaging container possessing the desired size and configuration. Known types of packaging materials of this nature comprise laminates with layers of, for example, plastic, paper and aluminium foil. It is also known in the art to produce packaging containers for liquid consumer goods entirely of plastic material, and combinations of laminates and plastic materials are also known in the art, for example in a package of the Tetra Top.RTM. type. This packaging type includes a tubular casing of laminated paper/plastic material whose one end, by folding and sealing, forms a substantially planar bottom. The upper end of the packaging container consists of injection moulded plastic material, for example polyethylene, which makes it possible to design an upper portion with an opening arrangement of optional type. The opening arrangement must be easy to open, an object which is attained in that an openable portion is demarcated and defined from the upper wall surface of the packaging container by means of a weakening line of the desired configuration. The opening arrangement must, moreover, be reclosable and consequently displays a closure device which is capable of being pressed down into the pouring so that it substantially seals against the edges of the pouring opening. The closure device is provided with a rear compression portion which displays a projecting flange which, on reclosure of the packaging container, comes into abutment against the upper wall surface of the packaging container. This type of closure device is common and occurs in a plurality of different, per se known packaging types where the closure device displays a projecting edge or flange which, by abutment against the edge surrounding the pouring opening, prevents the closure device from being forced down completely into the pouring opening and possibly falling down into the interior of the packaging container. A disadvantage inherent in this type of closure device is, however, that possible residues of the contents which have been poured out through the pouring opening and, in such instance, have remained along the edge of the pouring opening are pressed aside by the flange of the closure device when this, on reclosure of the packaging container, is brought into contact at a certain speed with the edge located around the pouring opening and with residual contents located on this edge. This results in residual contents being pressed out over the upper wall surface of the package and, on rapid closing of the closure device, may even make the contents splash outside the circumference of the packaging container which, in unfortunate cases, may dirty the clothes of the consumer or other nearby objects. This problem is particularly accentuated in the type of closure device which is reclosed with a snap action, i.e. closure devices which, for example, have a sealing lip which must pass over a portion of the pouring opening for the closure device to come into a completely reclosed position. When the sealing lip passes the edge of the pouring opening or the narrowest region, a certain compression force is required which, when the sealing lip has passed, results in the flange of the closure device coming into contact at relatively high speed with the wall surface of the packaging container extending around the pouring opening so that droplets of contents located thereon are forcibly flung out from the packaging container. While the problem in the present patent application is principally described in connection with the above-mentioned packaging container type, it occurs, of course, in all types of reclosable packages when similar opening/closure devices are employed. There is, therefore, a general need in the art to realise an opening arrangement which obviates, or in any event greatly reduces the above-outlined problems and makes it possible to reclose a partly emptied packaging container without any possible residual contents causing splashing from the opening region of the packaging container.

Opening arrangement for packaging containers


A millimeter wave link provides a means for easily transporting multiple high speed data channels, in excess of 100 Mb/s, a distance of up to 10 km, without requiring elaborate modulators and demodulators. This invention also provides fast setup, versatility, and is portable, which makes it desirable for field use. In addition, it can be set up for long term high speed data collection in a virtually permanent environment. The unidirectional link of the present invention is intended for use in experimental data collection systems, where portability, ease of setup and high speed data transfer are required. University environments as well as independent research and development institutions can benefit significantly from its use.

The present invention relates generally to digital communication systems and more particularly to a wireless digital communication system.
The use of low cost, portable, short haul high speed data transmission equipment has significant data collection advantages when observing and evaluating scientific data in real time from remote locations. This is especially desirable when processing analog inputs, which are digitally transformed in real time, such as digital signal processing (DSP) signals. This type of data collection often requires fast computational analysis, and immediate conversion back to real time for proper evaluation. Often data is taken at remote locations, such as antenna ranges or mobile sites, where the computing or DSP equipment cannot be co-located with the data collection equipment and thereby a portable data relay must be incorporated to satisfy the data collection requirements.
High speed data transfer has traditionally been achieved via fiber optic land lines or elaborate microwave relay links. Fiber optic systems require a substantial investment in equipment and cable routing and are not portable. Fiber optic systems also require alteration to the landscape in order to bury a cable, which is often forbidden in certain areas. At a minimum burying a cable presents a major inconvenience.
Traditional microwave links are relatively expensive and require bulky antennas and transceivers, which do not easily adapt to a mobile environment. RF data transfer above 50 Mb/s require a substantially higher carrier frequency than the data rate itself, which almost always requires the use of microwave and millimeter wave frequencies. In addition, most microwave links require the data to be pre-processed by elaborate modulators prior to transmission. A similar elaborate demodulation process must also take place at the receiver. Consequently, most applications cannot afford the complexity of a microwave link.
The present invention is therefore directed to the problem of developing a wireless digital communications system that is portable, easily installed in the field, relatively inexpensive and transfers a high data rate.

Dual channel high speed wireless data transfer device


Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.

The present invention relates to thin film transistors, and more particularly to the formation of silicon based thin film transistors on inexpensive, low-temperature plastic substrates. The present invention relates to a method of fabricating thin film transistors wherein heat sensitive substrates, such as inexpensive and flexible plastic substrates, may be used in place of standard glass, quartz, and silicon wafer-based substrates. A reflective coating for radiation protection of the plastic substrates is utilized during processing. The reflective coating layer is deposited above the plastic substrate to protect it from high intensity irradiation during processing by a laser or other high intensity radiation source.
Traditional techniques used in manufacturing high-performance polycrystalline silicon (poly-si) thin film transistors require processing temperatures of at least 600° C. This minimum temperature requirement is imposed by silicon crystallization and dopant activation anneals. Processes have recently been developed for crystallizing and doping amorphous silicon on a low cost, so-called low-temperature plastic substrates using a short pulsed high energy source in a selected environment, without heat propagation and build-up in the substrate so as to enable use of plastic substrates incapable of withstanding sustained processing temperatures higher than about 120° C. Such processes are described and claimed in U.S. Pat. No. 5,346,850 issued Sep. 13, 1994, to J. L. Kaschmitter et al. and U.S. Pat. No. 5,817,550 issued Oct. 6, 1998, to P. G. Carey et al., both assigned to the Assignee of the instant application.
As exemplified by the above-referenced U.S. Pat. No. 5,346,850, high performance polycrystalline silicon devices have been produced at low temperatures (<250° C.). This is accomplished by crystallizing the amorphous silicon layer (and activating dopants) with a short-pulse ultra-violet laser, such as an ArF excimer laser having a wavelength of 308 nm. The extremely short pulse duration (20–50 ns) allows the silicon thin film to melt and recrystallize without damaging the substrate or other layers in the device. Polycrystalline layers produced in this manner provide high carrier mobilities and enhanced dopant concentrations, resulting in better performance.
The present invention extends the capability of the above-mentioned method and processes for fabricating amorphous and polycrystalline channel silicon thin film transistors at temperatures sufficiently low to prevent damage to low cost, so-called low-temperature plastic substrates. The present invention utilizes a reflective coating for radiation protection of the plastic substrates during processing. A reflective coating layer is deposited above the plastic substrate to protect it from high intensity irradiation during processing by a laser or other high intensity radiation source. The process for fabrication of silicon thin film transistors on low-temperature plastic substrates, the thin film transistor, and the set of thin film transistor substrates for use in manufacturing thin film transistors of the present have different characteristics than existing thin film transistors. They have many and varied uses. For example, plastic displays and microelectronic circuits on flexible, rugged plastic substrates constructed in accordance with the present invention may be used for portable consumer electronics (video cameras, personal digital assistants, cell phones, etc.) or on large-area flat panel displays. Large area plastic displays are in need for high resolution large area flight simulators. Flexible detector arrays have use in radiation (X-ray, gamma-ray) detection. Silicon-on-insulator films may be used in radiation-hardened IC circuits. Many other uses exist and the development of the invention will produce additional uses.

Thin film transistors on plastic substrates with reflective coatings for radiation protection

The Regents of the University of California


In handsfree communications devices including a linear echo or noise canceler, both analog and digital gain factors are adjusted in response to user volume control inputs, the analog gain factor being frozen during active communications (e.g., during telephone calls). By providing dual user controls, one of which is disabled when a call is in progress, embodiments of the invention provide the wide dynamic range required in most handsfree applications without degrading performance of the linear echo canceler.

The present invention relates to communications systems, and more particularly, to volume control in communications systems including one or more linear cancelation devices.
Many bi-directional communications systems of today utilize some form of echo and/or noise suppression. For example, many handsfree telephones now include a linear echo canceler to prevent loudspeaker output from being fed back to a proximate microphone, as such feedback can be annoying or even intolerable to a far-end telephone user. U.S. patent application Ser. No. 09/005,145, filed Jan. 9, 1998 and entitled Methods and Apparatus for Providing Comfort Noise in Communications Systems, includes a detailed description of the implementation and advantages of such echo cancelation.
In addition to echo and noise suppression, loudspeaker volume control is also an important design consideration in the context of handsfree telephony. For typical applications, the loudspeaker volume control signal must compensate for a variety of factors, including component gain tolerances on both the transmitting and receiving sides of a communications link (typically in the range of +/xe2x88x9210 dB), voice power differences between human users (from xe2x88x9213 dB for a soft female to +8 dB for a loud male relative to a nominal male voice), varying loudspeaker distances across different installations (typically +/xe2x88x9212 dB for a 10-160 cm range in an automobile), and changes in background noise (typically 0-12 dB compensation for an automobile). When all such gain variations are considered, a volume control range of 77 dB is conceivable.
In conventional handsfree equipment, volume control is performed exclusively in the analog domain. In other words, a single adjustable-gain analog multiplier, or programmable gain amplifier (PGA), is used to adjust the amplitude of an analog loudspeaker feed signal. However, typical programmable gain amplifiers have nowhere near 77 dB of dynamic range. More often, programmable gain amplifiers include a dynamic range on the order of 20-25 dB.
While such range is perhaps sufficient for handheld applications (where the loudspeaker is at a fixed location relative to the user""s ear, and where the telephone body blocks out most background noise from the user""s ear), it is usually quite insufficient for handsfree applications, especially in automobiles. As a result, the telephone user experiences the product as not loud enough for a soft female voice in a noisy car with the loudspeaker at the farthest supported distance, or as too loud for a strong male voice in a quiet car with the loudspeaker at the closest supported distance, or both.
To compensate for this problem, some digital handsfree telephones of today include both analog and digital volume control. Such phones not only provide an adjustable-gain analog multiplier for the analog loudspeaker feed signal, but also include an adjustable-gain digital multiplier for adjusting the corresponding digital audio signal prior to digital-to-analog conversion. Consequently, these phones could provide an overall dynamic range more on the order of the above described 77 dB requirement.
Irrespective of whether the telephone employs analog-only volume control or dual analog and digital volume control, however, conventional volume control techniques can have a deleterious effect on telephone operation. For example, conventional techniques can lead to analog and/or digital signal clipping which can in turn significantly degrade the performance of a linear echo canceler. Moreover, analog gain changes made during a telephone call cause a linear echo canceler to retrain and therefore also result in periods of reduced echo cancelation.
Consequently, there is a need for improved techniques for providing volume control in communications devices incorporating a linear canceler.
The present invention fulfills the above-described and other needs by providing volume control techniques, wherein both analog and digital multipliers are used to adjust a loudspeaker input signal, and wherein analog volume adjustments are disabled during telephone calls. According to the invention, user adjustments to both the digital and analog gains are permitted when no call is in progress (e.g., during standby mode or at telephone installation), but only adjustments to the digital gain are permitted during a call. By providing dual (digital and analog) user controls, one of which is disabled when a call is in progress, embodiments of the invention provide the wide dynamic range required in handsfree applications while avoiding the pitfalls associated with conventional techniques. For example, volume adjustments made in accordance with the invention do not degrade linear echo canceler performance.
In an exemplary embodiment, a bi-directional communications device according to the invention includes a near-end signal processing path and a far-end signal processing path, the far-end signal processing path including a digital-domain multiplier and an analog-domain multiplier, and an echo canceler receiving a far-end digital reference signal from the far-end signal processing path and providing an echo estimate to the near-end signal processing path. According to the embodiment, both an analog gain factor of the analog-domain multiplier and a digital gain factor of the digital-domain multiplier are adjustable in dependence upon user input when users of the device are not communicating with one another via the device. However, when users of the device are communicating with one another via the device, the analog gain factor of the analog-domain multiplier is fixed while the digital gain factor of the digital-domain multiplier remains adjustable in dependence upon user input.
An exemplary method of processing signals in a telephone, the telephone including near-end and far-end signal processing paths and an echo canceler, and the far-end signal processing path including a digital domain multiplier and an analog domain multiplier, includes the steps of determining whether a telephone call is in progress, permitting adjustments of both a digital gain of the digital domain multiplier and an analog gain of the analog domain multiplier when the determination is negative, and permitting adjustments of the digital gain while blocking adjustments of the analog gain when the determination is affirmative.
The above-described and other features and advantages of the invention are explained in detail hereinafter with reference to the illustrative examples shown in the accompanying drawings. Those of skill in the art will appreciate that the described embodiments are provided for purposes of illustration and understanding and that numerous equivalent embodiments are contemplated herein.

Methods and apparatus for providing volume control in communicating systems including a linear echo canceler


Organic electrolytic solutions and lithium batteries using the organic electrolytic solutions are provided. One organic electrolytic solution includes a lithium salt, a mixed organic solvent consisting of a high-dielectric constant solvent and a low-boiling point solvent, and a compound represented by Formula 1 or 2 as an additive. The organic electrolytic solution and the lithium battery using the organic electrolytic solution may inhibit the reductive cleavage reaction of a polar solvent, thereby increasing capacity retention of the battery, and improving charge-discharge efficiency and battery lifetime.

1. Field of the Invention
The present invention relates to organic electrolytic solutions and to lithium batteries.
2. Description of the Related Art
As portable electronic devices such as camcorders, cellular phones, notebook PCs, etc. become lighter and more functional, considerable research is being conducted into batteries used as driving sources for the devices. Rechargeable lithium secondary batteries have energy densities per unit weight about three times greater than conventional lead batteries, nickel-cadmium batteries, nickel-hydrogen batteries, nickel-zinc batteries, etc. In addition, lithium rechargeable batteries can be rapidly charged. Accordingly, much research is directed at lithium rechargeable batteries.
Conventional aqueous electrolytic solutions are not usually suitable for lithium batteries because lithium anodes react vigorously with aqueous electrolytic solutions at high operation voltages. For this reason, organic electrolytic solutions prepared by dissolving lithium salts in organic solvents are used in lithium batteries. A good organic solvent has high ion conductivity, a high dielectric constant and low viscosity. However, it is very difficult to obtain a single solvent having all of these characteristics. As a result, mixed solvent systems have been used in lithium batteries. One such system includes an organic solvent having a high dielectric constant and an organic solvent having a low dielectric constant. Another system includes an organic solvent having a high dielectric constant and an organic solvent having low viscosity.
When polar, non-aqueous carbonate solvents are used in lithium secondary batteries, the carbon in the anodes reacts with the electrolytic solutions at initial charging and excess charge is used. Due to this irreversible reaction, passivation layers, such as solid electrolyte interface (SEI) films, are formed on anode surfaces. The SEI film prevents further decomposition of the electrolytic solution and stabilizes charging/discharging. Further, the SEI film acts as an ion channel, allowing only lithium ions to pass, and prevents organic solvents (which solvate lithium ions) flowing with the lithium ions from being cointercalated into the carbon anode. This prevents a collapse of the anode structure.
However, since high voltages of 4 V or greater are repeatedly applied over the SEI film consisting of only polar solvents and the lithium salt, it is difficult for the SEI film to retain the above functions. Cracks generate in the SEI film and the solvent continues to undergo the reduction reaction. As a result, insoluble salts precipitate on the inner and outer portions of the anode, and gas generates to form cracks in the anode structure, thereby reducing electronic connections. Thus, the internal resistance of the anode increases, thereby reducing the capacity of the battery. Further, due to the decomposition of the solvent, the amount of electrolytes decreases and the electrolytes are exhausted in the battery. Thus, a sufficient amount of the ions cannot be easily transferred. To address these problems, various compounds have been suggested for making the SEI film denser and stronger.

Organic electrolytic solution and lithium battery using the same


An electrostatic ink jet recording apparatus has a head body having an ink chamber in which ink charged to a specified polarity is stored, a plurality of ink ejection ports and a plurality of ejection electrodes. An ejection electrode drive circuit generates an ejection voltage to drive the plurality of ejection electrodes according to a time division method so that the ejection voltage is not simultaneously supplied to the adjacent ejection electrodes. A plurality of opposite electrodes are opposed to the plurality of ejection electrodes via recording paper. They are separated into first opposite electrodes corresponding to those ejection electrodes which are selectively being driven according to the time division method and second opposite electrodes corresponding to those ejection electrodes which are not being driven according to the time division method. An opposite potential setting circuit sets a first potential for the first opposite electrodes and a second potential for the second opposite electrodes. The first potential is set at such a value as to cause ink ejected from the ink ejection ports to be electrically attracted to the first opposite electrodes more strongly than to the second opposite electrodes.

1. Field of the Invention
The present invention relates to an ink jet recording apparatus, and in particular, to an electrostatic ink jet recording apparatus that carries out recording using the effects of electric fields to deposit charged toner in ink on a recording medium.
2. Description of the Prior Art
As described in the PCT International Publication Number WO 93/11866, conventional electrostatic ink jet apparatuses have a recording head body with ejection electrodes for ejecting ink and an opposite electrode disposed opposite to the recording head body.
As shown in FIG. 1, a plurality of ejection electrodes 52 are provided at the end of a recording head body 50 so as to protrude therefrom. An opposite electrode 53 is disposed on the extension of the ejection electrodes 52 via a recording medium 58. The plurality of ejection electrodes 52 are arranged in parallel at an interval depending on the recording resolution are immersed in ink. The ink comprises an ink liquid containing charged particulate material (charged toner) and can reach the end of the ejection electrodes due to surface tension. Compared to the plurality of ejection electrodes 52, the opposite electrode 53 comprises a common integral electrode and is grounded.
When a high voltage pulse is applied to any ejection electrode 52, there will be an electric potential difference between the end of the ejection electrode 52 and the opposite electrode 53. Electric fields (electric force lines 63) formed depending on the potential difference cause the ink to be ejected from the end of the ejection electrode 52 toward the opposite electrode 53. The ejected ink deposits on the recording medium 58 disposed in front of the opposite electrode 53 for recording. Compared to the ejection electrode 52, to which the high voltage pulse has been applied, the potential around the ink deposition location on the opposite electrode 53 is uniform. The ink thus flies in the direction in which the distance between the ejection electrode 52 and the opposite electrode 53 is shortest due to the strength of the corresponding electric field, that is, a direction A, and the ink deposits at a location B.
According to this conventional example, however, there is only a small difference in magnitude between the electric field indicated at A and peripheral electric fields (for example, the one indicated at C), so the magnitude of the electric field C may become larger than that of the electric field A if, for example, the surface of the recording paper is rough or dust sticks to the paper. In such a case, the ink, flying along the electric field C, may deposit at a location D, and this deviation of the recording location may cause image quality to be degraded.

Electrostatic ink jet recording apparatus ejecting ink using different electric potentials applied to different electrodes


A method for forming a chromium nitride coating over a substrate to provide a chromium nitride coated article, and the resulting chromium nitride coated article, each use a bilayer chromium nitride containing material layer. The bilayer chromium nitride containing material layer includes: (1) a first chromium nitride material layer having a first thickness, a first uniform chromium concentration and a first uniform nitrogen concentration located and formed closer to a substrate which provides the article; and (2) a second chromium nitride material layer having a second thickness, a second increasingly graded chromium concentration and a second decreasingly graded nitrogen concentration located and formed upon the first chromium nitride material layer. This particular bilayer chromium nitride containing material layer provides the article with superior reflectivity and crack resistance.

Field of the Invention
Embodiments relate to chromium nitride containing coatings. More particularly, embodiments relate to high performance chromium nitride containing coatings.
Description of the Related Art
Chromium containing coatings are common coatings that have various decorative and functional applications within the context of a plurality of industrial and consumer products. Given this broad applicability of chromium containing coatings in such a plurality of industrial and consumer products, desirable are additional chromium containing coatings and additional chromium containing coated articles that possess enhanced performance characteristics.

Bilayer chromium nitride coated articles and related methods


An encapsulated refrigerator shelf is assembled by interconnecting a platform, such as a glass panel, within a peripheral frame. More specifically, a peripheral shelf frame is formed with a split side portion defining upper and lower frame portions which are spaced by an elongated slot. The encapsulated glass refrigerator shelf is made by slidably inserting the platform onto peripheral frame support structure through the slot formed between the upper and lower frame portions. The frame is also formed with retaining structure to maintain the platform in place once the platform is inserted a requisite amount within the peripheral frame.

1. Field of the Invention
The present invention pertains to the art of refrigerators and, more specifically, to a shelving assembly, including a peripheral frame provided with a slot which slidably receives a glass panel, for a refrigerator.
2. Description of the Related Art
It is common to provide vertically adjustable shelves in refrigerator cabinets in order to increase the versatility of storing a wide range of food items. To this end, mainly fresh food compartments of refrigerators have elongated, vertically extending and laterally spaced rails mounted on rear walls thereof, with the rails enabling shelves to be supported in selected vertically adjustable positions in a cantilevered manner. In other arrangements, pegs or rails are attached to or integrally formed with compartment side walls of a refrigerator in order to support shelves thereon. Providing various sets of the pegs or rails at vertically spaced locations along the side walls permits a consumer to vertically reposition a given shelf as desired.
Many refrigerator shelves are mounted in fixed positions in a refrigerator compartment. It has also been proposed in the art to enable shelves to be selectively slid partially out of a refrigerator compartment in order to enhance access to food items stored on rear portions of the shelves. Typically, with the case of cantilevered shelves, an overall shelf support frame must be provided to support a shelf both at the rear of the refrigerator compartment and for sliding movement relative to the support frame. In the case of shelves supported on liner side wall rails of a refrigerator compartment, the shelves can made to slide directly upon the side rails, while including structure preventing tipping of the slidable shelves. Shelves which are directly supported at the compartment side walls typically exhibit an advantage in that the shelves can extend substantially the full width of the refrigerator compartment.
In making a refrigerator shelf, it has become quite common to employ a glass panel as the shelf platform and to encapsulate the glass with a peripheral rim. Glass panels are seen to be aesthetically pleasing, easy to clean and structurally advantageous. In some known arrangements, the peripheral rim is actually molded directly about the glass panel. Other manufacturers will assemble a glass panel to a plastic frame when the frame is still at a high temperature from a molding process. Each of these arrangements generally provides for an inherent seal between the glass panel and the rim to prevent any spilled liquids or the like from running off the shelf. Unfortunately, these types of shelves require somewhat complicated and expensive molding techniques, while the established degree of sealing is not really required. Also known is ultrasonically weld frame parts around a glass panel, which creates an aesthetic shelf but requires more precision manufacturing and assembly. In still other known arrangements, the peripheral rim or frame will be separately made, with the glass panel being attached to the frame. Many of these types of known shelves have generally required either rather elaborate brackets and fasteners, or were simply cumbersome and difficult to assemble.
Even though various arrangements have been proposed to interconnect a glass panel to a separately formed peripheral rim or frame in forming a refrigerator shelf, there is still seen to exist a need in the art for an improved arrangement wherein a glass panel can be easily positioned in a separately formed peripheral frame to create a refrigerator shelf which is economical to manufacture, sturdy in construction and aesthetically appealing, while also being easily made as either a fixed or sliding shelving assembly.

Refrigerator shelf with glass receiving slot


A system and method for decreasing the route convergence time in a wireless communication network, such as a wireless ad-hoc peer-to-peer network, by finding an alternate route if the nodes anticipate weakening or breakage of a route currently in use. The system and method which enables reactive routing protocols to find optimal routes between nodes in these types of networks when those routes cannot otherwise be found in certain conditions. The system and method thus decrease the route convergence time, provide an effective and efficient way to find optimal routes, and improve overall performance of the network with regard to throughput, delay, packet completion rate and other factors.

1. Field of the Invention
The present invention relates to a system and method for decreasing the route convergence time in a wireless communication network, such as a wireless ad-hoc peer-to-peer network, by finding an alternate route if the nodes anticipate weakening or breakage of a route currently in use. More particularly, the present invention relates to a system and method which enables reactive routing protocols to find optimal routes between nodes in these types of networks when those routes cannot otherwise be found in certain conditions.
2. Description of the Related Art
Wireless communication networks, such as mobile wireless telephone networks, have become increasingly prevalent over the past decade. These wireless communications networks are commonly referred to as "cellular networks", because the network infrastructure is arranged to divide the service area into a plurality of regions called "cells". A terrestrial cellular network includes a plurality of interconnected base stations, or base nodes, that are distributed geographically at designated locations throughout the service area. Each base node includes one or more transceivers that are capable of transmitting and receiving electromagnetic signals, such as radio frequency (RF) communications signals, to and from mobile user nodes, such as wireless telephones, located within the coverage area. The communications signals include, for example, voice data that has been modulated according to a desired modulation technique and transmitted as data packets. As can be appreciated by one skilled in the art, network nodes transmit and receive data packet communications in a multiplexed format, such as time-division multiple access (TDMA) format, code-division multiple access (CDMA) format, or frequency-division multiple access (FDMA) format, which enables a single transceiver at a first node to communicate simultaneously with several other nodes in its coverage area.
In recent years, a type of mobile communications network known as an "ad-hoc" network has been developed. In this type of network, each mobile node is capable of operating as a base station or router for the other mobile nodes, thus eliminating the need for a fixed infrastructure of base stations. More sophisticated ad-hoc networks are also being developed which, in addition to enabling mobile nodes to communicate with each other as in a conventional ad-hoc network, further enable the mobile nodes to access a fixed network and thus communicate with other mobile nodes, such as those on the public switched telephone network (PSTN), and on other networks such as the Internet. Details of these advanced types of ad-hoc networks are described in U.S. Pat. No. 7,072,650 entitled "Ad Hoc Peer-to-Peer Mobile Radio Access System Interfaced to the PSTN and Cellular Networks", granted on Jul. 4, 2006 ,in U.S. Pat. No. 6,807,165 entitled "Time Division Protocol for an Ad-Hoc, Peer-to-Peer Radio Network Having Coordinating Channel Access to Shared Parallel Data Channels with Separate Reservation Channel", granted on Oct. 19, 2004, and in U.S. Pat. No. 6,873,839 entitled "Prioritized-Routing for an Ad-Hoc, Peer-to-Peer, Mobile Radio Access System", granted on Mar. 29, 2005, the entire content of each being incorporated herein by reference.
Two of the routing protocols being considered by IETF for mobile ad-hoc networks (MANET) are Ad-Hoc On-Demand Distance Vector (AODV) Routing Protocol as described, for example, in a publication by Charles E. Perkins, Elizabeth M. Belding-Royer, and Samir Das entitled "Ad Hoc On Demand Distance Vector (AODV) Routing." IETF Experimental RFC, July 2003, and Dynamic Source Routing (DSR) protocol as described in a publication by David B. Johnson, David A. Maltz and Yih-Chun Hu entitled "The Dynamic Source Routing Protocol for Mobile Ad Hoc Networks (DSR)" IETF Internet draft, July 2004 , the entire content of both documents being incorporated herein by reference.
As can be appreciated by one skilled in the art, On-Demand routing protocols create routes only when desired by the source node, that is, the node that is attempting to transmit a data packet. When a node requires a route to a destination, it initiates a route discovery process within the network. This process is completed once a route is found or all possible route permutations have been examined. Once a route has been established, the route is maintained by some form of route maintenance procedure until either the destination becomes inaccessible along every path from the source or until the route is no longer desired.
As described in the publication by Perkins et al. cited above, a node following these On-Demand routing protocols initiates processing for a special message called as Route Error (RERR) in the following situations: if the node detects a link break for the next hop of an active route in its routing table while transmitting data (and route repair, if attempted, was unsuccessful), of if the node gets a data packet destined to a node for which it does not have an active route and is not repairing (if using local repair), or if the node receives a RERR from a neighbor for one or more active routes. In summary, the Route Error message is sent only when a node is absolutely sure that the link towards the next hop is unavailable.
As further described in the Perkins et al. publication, to detect link connectivity (or breakage), a node can use one of the following techniques. Any suitable link layer notification, such as those provided by IEEE 802.11, can be used to determine connectivity, each time a packet is transmitted to an active next hop. For example, absence of a link layer ACK or failure to get a CTS after sending RTS, even after the maximum number of retransmission attempts, indicates loss of the link to this active next hop. If layer-2 notification is not available, passive acknowledgment should be used when the next hop is expected to forward the packet, by listening to the channel for a transmission attempt made by the next hop. If transmission is not detected within NEXT_HOP_WAIT milliseconds or the next hop is the destination (and thus is not supposed to forward the packet), one of the following methods should be used to determine connectivity: receiving any packet (including a Hello message) from the next hop; a route request (RREQ) unicast to the next hop, asking for a route to the next hop; or an Internet Control Message Protocol (ICMP) Echo Request message unicast to the next hop.
Although these techniques are somewhat suitable, certain problems exist which impede their ability to detect link connectivity. For example, these techniques can erroneously indicate breakage of link because of a fail in packet transmission while a packet transmission can fail due to congestion rather than movement of node or breakage of link. Sending a route error message will delete the route maintained by several nodes to the node in question, thus forcing the nodes interested in sending packets to the node in question to restart the bandwidth-expensive route discovery process. Secondly, link layer will only inform the upper layers of failure after it has failed to transmit the packet after several retrials, which may be separated by considerable time and hence, significant delay will be accrued before triggering upper layers to respond.
Certain problems also exist with the passive acknowledgement techniques discussed above. That is, although passive acknowledgement has a very low probability of producing a false alarm, it has very long delay associated with the alarm process. For example, the number of hellos that need to be missed before a link break is declared needs to be of the order of n or more because of the low broadcast reliability of the wireless channel, where n can be as high as 5 or 10, or possibly more. Also, in both the link layer notification and passive acknowledgment techniques, any attempt to repair the route or find another route will be initiated only after the node attempting to send the data packet has determined that a break in the link exists. Hence, there is no "make before break" mechanism that is performed for either of these techniques.
Another problem with the On-Demand protocols discussed above is the optimization technique that they typically use to reduce the overhead in finding routes. This optimization technique is typically known as an "expanding ring search" in which the number of hops that a broadcast RREQ can travel is controlled as described the Perkins et al. publication cited above. Specifically, to prevent unnecessary network-wide dissemination of RREQs, the originating node should use an expanding ring search technique. In an expanding ring search, the originating node initially uses a Time to Live (TTL) value of TTL=TTL_START in the RREQ packet IP header and sets the timeout for receiving a route reply (RREP) to RING_TRAVERSAL_TIME milliseconds. The TTL_VALUE used in calculating RING_TRAVERSAL_TIME is set equal to the value of the TTL field in the IP header. If the RREQ times out without a corresponding RREP, the originator broadcasts the RREQ again with the TTL incremented by TTL_INCREMENT. This continues until the TTL set in the RREQ reaches TTL_THRESHOLD, beyond which a TTL=NET_DIAMETER is used for each attempt. Each time, the timeout for receiving a RREP is RING_TRAVERSAL_TIME. When it is desired to have all retries traverse the entire ad-hoc network, this can be achieved by configuring TTL_START and TTL_INCREMENT both to be the same value as NET_DIAMETER. Accordingly, this optimization (expanding ring search technique) may result in the problem illustrated by the following example network shown in FIG. 1.
Specifically, as shown in FIG. 1, a circle represents a node and lines (dashed or straight) represent the wireless link between the nodes. As indicated, all the links (if they exist) are good except the one between the nodes B and E. It is also assumed that the nodes do not have routes with each other. In this example, if node A wants to communicate with node E and uses the expanding ring search as described above, it will start with TTL=1. Hence, initially the RREQ will be received by nodes B and C. Assuming that these nodes do not know a route to node E, they will simply drop the RREQ after performing the processing as required as per the protocol. Since the TTL used is 1 initially, the RREQ packet will not be forwarded. After the timeout period, node A will resend RREQ with increased TTL which in this case will be 2 (new TTL=2 times old TTL). This time again the RREQ will be first received by nodes B and C. Since this time the value of TTL is 2, the RREQ will be forwarded by them. The RREQ forwarded by node C is received at nodes A and D. Node A ignores the message as it is the source of RREQ and node D drops it after updating the routing table as specified by protocol. Node D drops the RREQ because it can neither reply to it (as it doesn't have a route to E) nor can it forward it (as the TTL was set to 2 and has already traveled two hops). The RREQ forwarded by node B is received by nodes A and E. Node A ignores the message as it is the source of RREQ.
It should be noted that although the link between the nodes B and E is "bad", a small packet can still be sent due to the characteristic of a wireless channel and repeated retrial by the MAC layer. When node E receives the RREQ, it immediately replies with a RREP since it is the destination identified in the RREQ packet. This time, node A should receive the RREP before the expiration of its timer and hence it will not generate any new RREQ with a higher TTL value. Thus, node A chooses route via B to E, and the route through nodes C and D is not computed. In this particular case, the route through nodes C and D may be optimal because of better links. However, the link between nodes B and E can be so bad that it does not allow larger data packets to go through and hence may not even be a useful route. If this is the case and node B is not able to send data packets successfully, it will generate a route error for node E to A. Node A will therefore restart the Route Discovery process and may get the same route because of the reasons explained above. Hence, the optimal route is never found and network bandwidth is wasted by repeated route discoveries.
Another problem with the On-Demand routing protocols is their instantaneous nature of finding routes. On-Demand routing protocols find routes as needed and do not attempt to find any alternate route unless the current route is broken. The route found initially may be the optimal route (based on the metrics used) at that particular instant of time, but as time progresses, it may not be the best route due to node mobility, congestion and so on. Hence, this behavior can lead to inefficient routes and under utilization of network resources.
Accordingly, a need exists for a system and method that is capable of finding optimal routes in a wireless communication network without the drawbacks associated with the existing techniques as described above.

System and method to decrease the route convergence time and find optimal routes in a wireless communication network


A conveyor for buffering products comprises at least first and second drivable curved conveyor parts, which are spaced from each other in horizontal direction. At least, the first conveyor part has at least an inner track and an outer track, wherein the outer track is adjacent to the inner track and disposed at the outside bend side of the inner track. The second conveyor part has at least a second conveyor part track, wherein one end of the outer track of the first conveyor part is coupled to one end of the second conveyor part track. An other end of the second conveyor part track is coupled to one end of the inner track of the first conveyor part. The first and second conveyor parts are at least partly helically-shaped.

The discussion below is merely provided for general background information and is not intended to be used as an aid in determining the scope of the claimed subject matter.
An aspect of the present invention relates to a conveyor for buffering products, comprising at least first and second drivable curved conveyor parts, spaced from each other in horizontal direction, at least the first conveyor part having at least an inner track and an outer track, wherein the outer track is adjacent to the inner track and disposed at the outside bend side of the inner track, the second conveyor part having at least a second conveyor part track, wherein one end of the outer track of the first conveyor part is coupled to one end of the second conveyor part track and wherein an other end of the second conveyor part track is coupled to one end of the inner track of the first conveyor part.
Such a conveyor is known from NL 7101881. In the known conveyor the products are supplied at an upper level of the conveyor and are circulated at that level several times along curved conveyor parts and straight conveyor parts disposed between the curved conveyor parts. The products are first transported along the outer track and subsequently along the inner track. After several circulations at the upper conveyor level the products are transported to a lower level and the products move from an inner track to an outer track at the lower level.


An organic optoelectronic device that includes a substrate and a plurality of structures disposed thereon, the structures include: (a) a first electrode; vertically separated from (b) a second electrode by (c) an electrode gap that includes an organic photoactive layer disposed within the gap, wherein one of the electrodes includes a plurality of plasmonic nanopores or metal nanostructures, wherein the nanostructures project towards the electrode gap and the metal is selected from gold, aluminum, silver, calcium, copper, and nickel is presented.

Light is a wonderful means of transmitting energy and information. More solar light energy reaches our planet every hour than all of humankind consumes in one year. Much progress has been made in the field of photovoltaics in order to try to tap into this vast reservoir of energy, but further improvements in the technology are still necessary in order to expand our ability to harvest solar energy. Regarding the reverse process (of light harvesting)—light emission, an enormous source of wasted energy comes from our lighting and display applications—one of the largest percentage of battery consumption on most smartphones or tablets is attributed to the display. Great strides are necessary to improve optoelectronic devices and integrated devices used for light harvesting and light emission.
Organic-based optoelectronic devices, such as organic light emitting diodes (OLEDs) and organic photovoltaics (OPVs or organic solar cells) are not as efficient as their inorganic counterparts, and they tend to degrade more rapidly when left in air. The potential advantages of organic optoelectronic devices are large enough to motivate researchers across the globe to try to improve the efficiency, lifetime, and cost of these devices.

Organic optoelectronic devices incorporating plasmonic electrodes

RUTGERS, THE STATE UNIVERSITY OF NEW JERSEY


An injection locking oscillator (ILO) circuit includes; an injection circuit that receives input signals having a phase difference and provides injection signals respectively corresponding to the input signals based on a voltage level difference between each input signal and an oscillation signal at an output terminal, and a poly-phase signal output circuit that provides poly-phased signals having a phase difference between signals fixed to a defined phase difference upon receiving the injection signals from the input terminals.

The inventive concept relates generally to injection locking oscillator (ILO) circuits and operating methods for ILOs.
When a memory device including, for example, double data rate synchronous dynamic random access memory (DR SDRAM), receives an external clock and generates an internal clock based on the external clock, the memory device may generate an internal clock using two signals having a quadrature phase difference. In such applications, it is essential that signals having an accurate quadrature phase difference be applied to the memory device.
When the memory device generates an internal clock, the memory device may reduce power consumption and remove a jitter component of an external clock and skew component(s) among various signals associated with an ILO. Thus, an ILO may synchronize oscillation signals of an internal oscillator in relation to signals injected from an external source, and may accurately adjust a phase difference among the injection signals by removing skew components from the injection signals in relation to the synchronized oscillation signals.

Injection locking oscillator circuit and operating method


A solar cell includes a substrate of a first conductive type, a plurality of first electrodes positioned on one surface of the substrate in parallel with one another, and a plurality of back surface field regions which are positioned respectively correspondingly to the plurality of first electrodes, are separated from one another, and are doped with impurities of the first conductive type at a concentration higher than the substrate. Each back surface field region includes discontinuous regions in a longitudinal direction of the first electrodes. An impurity concentration of the discontinuous regions is lower than an impurity concentration of the back surface field region.

Field of the Invention
Embodiments of the invention relate to a solar cell, in which a heavily doped region is locally formed.
Description of the Related Art
A solar cell is a power generating device obtaining photovoltaic power using a photoelectric effect and collects electrons and holes produced in a semiconductor substrate forming a p-n junction through an n-type electrode and a p-type electrode. Further, the solar cell includes a back surface field region forming a potential barrier between the semiconductor substrate and the electrodes, and the back surface field region is formed by heavily doping impurities of the same conductive type as the semiconductor substrate.
The back surface field region is generally formed through a semiconductor process such as a thermal diffusion method and an ion injection method. In recent times, the back surface field region may be more precisely formed through a heavily doped region with the development of an ion implantation method as an example of an ion injection method.


An integrated circuit includes a first and second diode connected in parallel. The first diode has a first breakdown voltage and has first P type region and first N type region adjacent to each other at the surface of the substrate of a substrate to form a lateral diode. The second diode has a second breakdown voltage less than the first breakdown voltage and has a second P type region and second N type region lateral adjacent to each other in the substrate to form a lateral diode below the surface The first and second N type regions overlap and the first and second P type region being electrically connected whereby the first and second diodes are in parallel.

The present disclosure relates generally to integrated circuits and, more specifically, to a pair of parallel diodes in the integrated circuit.
Zener or avalanche diodes are used to limit voltages seen by components in an integrated circuit. These diodes are either discrete components external to the integrated circuit or specially integrated into the integrated circuit with the elements they are to protect. Discrete diodes add to the overall costs at the component and the printed circuit board level. Integrated circuit Zener diodes add to the cost by increasing the die area.
Certain circuits parasitic have intentional inductances that lead to large voltage spikes during fast switching events. Voltage spikes frequently exceed the breakdown of the integrated circuit transistors especially, when the transistors drain to source on-resistance is being minimized. Depending upon the device's architecture, repetitive breakdown events lead to hot carrier charge be trapped. Lateral MOS transistors are particularly susceptible.
An integrated circuit of the present disclosure includes a first and second diode connected in parallel. The first diode has a first breakdown voltage and has first P type region and first N type region adjacent to each other at the surface of the substrate to form a lateral diode. The second diode has a second breakdown voltage less than the first breakdown voltage and has a second P type region and second N type region lateral adjacent to each other in the substrate to form a lateral diode below the surface. The first and second N type regions overlap and the first and second P type region are electrically connected whereby the first and second diodes are in parallel.
The second P type and N type regions have a maximum impurity concentration below the surface of the substrate. The substrate may include a lateral insulation, for example a trench in the surface, and the second diode is below the trench. The first and second P type regions may be spaced in the substrate and are electrically connected by interconnects above the substrate. The first and second P type regions may alternatively overlap to form the electrical connection. The first and second P type regions may be a common P type region abutting the first N type region at the surface and the second N type region below the surface. The common P type region and the N type region have a maximum impurity concentration below the surface of the substrate.
The first P type region may be a body of a lateral field effect transistor and the first N type region is a drain region of the field effect transistor. The field effect transistor may be an insulated gate field effect transistor.
These and other aspects of the present disclosure will become apparent from the following detailed description of the disclosure, when considered in conjunction with accompanying drawings.

Integrated circuit with a subsurface diode


Provided is a method of preventing simultaneous activation of redundancy memory line or spare word lines, the method including: programming a fail address of a memory line determined to be defective; reprogramming the fail address if a first spare line for the memory line is determined to be defective; storing additional information with respect to the reprogrammed fail address; and activating a second spare line and inactivating the first spare line, referring to the additional information.

Apparatuses and methods consistent with exemplary embodiments relate to a semiconductor memory field, and more particularly, relate to techniques of preventing multiple activation of spare word lines and executing post package repairing and a semiconductor memory device including a fuse programming circuit.
If at least one of memory cells of a semiconductor memory device is defective, a function of the semiconductor memory device may not be performed normally. In this case, the semiconductor memory device may become a bad product. To manage a semiconductor memory device including a few defective memory cells as a bad product may be inefficient in terms of product yield.
In general, a semiconductor memory device may have redundancy memory cells. When defective memory cells are generated, they may be replaced with redundancy memory cells. In this case, the semiconductor memory device may be considered as a good product. In particular, a defect repair executed after a package process may be referred to as a post package repair operation. Product yield may be improved through the post package repair operation. However, in the post package repair operation, multiple redundancy line may be simultaneously activated to repair a single defective memory line.

Post package repairing method, method of preventing multiple activation of spare word lines, and semiconductor memory device including fuse programming circuit


A device for mixing paints, varnishes and liquid products in general comprises a support unit for the liquid products, which is intended to support and clamp at least one container. A series of sensors is associated with the device in order to provide signals indicative of a characteristic of the container or of the liquid products, for example, the size of the container. Further sensors provide signals indicative of the position of the support unit during its mixing movement. Further signals coming from units outside the device, together with any data input by an operator, contribute to the selection and the control of the sequence or mode of operation in a mixing method including the steps of starting, regulating and stopping a main motor and an auxiliary motor for clamping and releasing the container and for locking the support unit in a predetermined starting position which corresponds to a final position upon completion of the mixing.

The subject of the present invention is a device for mixing paints, varnishes and liquid products in general.
A further subject of the present invention is a method of controlling a device of the type indicated above.
The invention has been developed particularly, but not exclusively, for a mixing device of the type with gyroscopic action in which a support unit for at least one container for liquid products is rotated simultaneously about two perpendicular axes. For simplicity, the following description will refer to a single container, without thereby excluding the possibility of the principles of the invention being applied to the agitation of several containers simultaneously.
In known mixing devices, a generally cylindrical container containing the liquid or liquids to be mixed or homogenized is supported and clamped in an upright position by the support unit in a configuration thereof which will be referred to below as the starting configuration. The energizing of a main electric motor operatively connected to the support unit causes it to move gyroscopically at a predetermined speed of rotation for a predetermined period of time. After the motor has been de-energized, the motion of the support unit slows down until it stops in a final configuration which generally differs from the starting configuration in which the container is in an upright position. It is therefore the task of the operator to act manually on the support unit to return it to the starting configuration so that the container can be released and removed in an upright position.

Device for mixing paints, varnishes and liquid products in general and a method of controlling the device


A method of identifying or authenticating a product by providing an analog identification indicia including a randomized pattern of identification features on a first part of the product wherein one or more attributes of the randomized pattern of identification features correspond to an item identifier. A digital identification record is provided on a second part of the product including an encoded digital version of the item identifier. The product is viewed from two angles and confirmation of the information from both angles assures product authenticity.

There is an increasing concern over counterfeit products including software, music CDs, and over-the-counter and prescription drugs entering the U.S. market. Counterfeit products not only depress profits of legitimate manufactures, but consumers who unknowingly purchase counterfeit products are being misled. Because of health issues involving counterfeit drugs, this is a paramount concern of drug manufacturers and governmental agencies. The concern is exacerbated because of the ready availability of lower cost prescription drugs from Internet pharmacies and drug stores with undisclosed sources for the product they provide.
Because of governmental regulations and/or to prevent unauthorized tampering, many prescription and over-the-counter drugs are packaged in containers using tamper-resistant seals. The consumer purchasing a drug product must break or destroy the tamper-resistant seal in order to open the container and access the product. While such tamper-resistant seals effectively thwart tampering, sophisticated counterfeit drug manufacturers may manufacture containers that include a tamper-resistant seal. Thus, tamper-resistant seals do not adequately address the issue of counterfeit drugs.
Many other anti-counterfeit measures have been developed for use with other products that been prime targets for counterfeiters such as checks, CDs and DVDs. These anti-counterfeit measures attempt to prevent a counterfeit manufacturer from easily reproducing labels that bear anti-counterfeit indicia. For example, companies such as Microsoft Corporation use holograms on the packages of their software to indicate authenticity. Escher Group of Cambridge, Mass. has developed a FiberFingerprint.™. technology that can identify a piece of paper by its natural and unique fiber patterns. This enables the capability to identify a piece of paper in a way similar to identifying people through fingerprints. Tracer Technologies of Syosset, N.Y. has developed a fluorescent micro-fiber detection technology for security. The micro-fibers are randomly embedded in a plastic material which are only revealed upon illumination by UV light. AMCO of Farmingdale, N.Y. has developed visible as well as fluorescent tags that can be embedded in plastics. Other pigments that can be imbedded in an anti-counterfeit label or in a product have the capability of changing color when viewed at different angles. Such a color-changing pigment is also present in certain denominations of newly printed U.S. currency.
These anti-counterfeiting technologies make it difficult to reproduce the anti-counterfeit label component using copying or scanning techniques. However, more sophisticated counterfeiters have been known to make the investment necessary to duplicate these anti-counterfeit measures. For example, the holographic labels such as those used by Microsoft Corporation are known to have been successfully counterfeited.
U.S. Pat. No. 7,309,011 to He entitled 'Method of Authenticating Products Using Hardware Compatibility Flag' is assigned to the assignee of the present application and is incorporated herein by reference. This patent concerns a method of identifying or authenticating a product by providing an analog identification indicia including a randomized pattern of identification features on a first part of the product wherein one or more attributes of the randomized pattern of identification features correspond to an item identifier. A digital identification record is provided on a second part of the product including an encoded digital version of the item identifier. The randomized pattern of identification features of the analog identification indicia is read and decoded to generate an item identifier and the digital identification record is read and decoded to generate an item identifier. The product is deemed authentic if the item identifier from the analog identification indicia substantially matches the item identifier from the digital identification record.
United States published application 2006/0095778 to He et al, entitled 'Analog and Digital Indicia Authentication' is assigned to the assignee of the present application and is incorporated herein by reference. This published application also concerns an authentication-enabled indicia contains authentication information in a digital recording medium. Characteristics of the reflected light when the features are illuminated is used to generate an analog signature that is encoded in the recording medium. During processing the features are illuminated and a new analog signature is determined for comparison with the signature recorded in the digital recording medium.


Bis(carboalkoxy-substituted m-phenylene)-32-crown-10 compounds, useful as polymerizable monomers, can be formed in one step by reacting a functionalized dihydroxy aromatic compound with a dihalopolyether. In the same reaction, carboalkoxy-substituted m-phenylene-16-crown-5 is formed. Other mono- and di-functionalized bis(phenylene) crown ethers can be made by one step as well as multistep synthesis from similar starting materials.

It has recently been suggested that a family of polymeric analogs to macromolecules, termed "polyrotoxanes", be synthesized using crown ethers (or macrocyclic polyethers) as the cyclic component thereof. See H. W. Gibson et al., Polymer Preprints, 1988, 29(1) 248-249 and P. R. Lecavalier et al., Polymer Preprints, 1989, 30(1) 189-190, Ibid., 1990, 31(2), 659-660.
It is known to form hetero crown ethers (also termed "corands") comprising oxygen atoms separated by (CH.sub.2).sub.n groups and groups of the ortho-phenylene type. See C. J. Pedersen, J. Am. Chem. Soc. 89 (1967) 2495 and 7017. It is well known that such crown ethers can be used as complexation agents.
Chapoteau et al., in J. Org. Chem. 1989, 54, 861-867 mention that crown ethers (corands) based on the 1,3-xylyl subunit have been synthesized with a variety of intraannular or inward facing groups including methoxyl, phenolic, carboxyl, methoxycarbonyl, hydroxyl, nitrile and sulfones.
Moore et al. in J. Amer. Chem. Soc. 99:19, 6398-6410 (1977) show certain monobenzo-crown ethers containing outwardly facing substituents such as --CH.sub.2 C.sub.2 H.sub.5 and --CN.
Allwood et al., in a series of reports in J. Chem. Soc., Chem. Commun., 1987, 1054-1064 illustrate a dinaphtho-crown ether (DN30C10 on pp. 1054-1058), a non-substituted bismetaphenylene-32-crown-10 derivative (BMP32C10) on pp. 1058-1061, and a bisparaphenylene-34-crown-10 derivative (BPP34C10) on pp. 1061-1064. The BMP32C10 derivative was synthesized by partial benzylation of resorcinol to yield 3-benzyloxyphenol which was reacted with tetraethylene glycol bis(toluene-p-sulfonate) (TEGBT) to yield 1,11-bis(3'-benzyloxyphenoxy)-36,9-trioxaundecane. Deprotection of that product followed by reaction of the derived diphenol with TEGBT afforded the BMP32C10 derivative. Allwood et al. discuss the ability of BMP32C10 and BPP34C10 to complex such materials as paraquat and diquat.

Mono- and di(functionally-substituted phenylene) semi-rigid crowns and precursors thereof

Virginia Tech Intellectual Properties, Inc.


A mounting device (10) for mounting a speaker enclosure (12) in an elevated position at an intersection of two walls (14,16) or similar surfaces, wherein the device (10) facilitates easily locating supportive wall studs (18,20) underlying wall sheathings 22,24, and the device (10) is adapted to couple with and support the speaker enclosure (12) in such a manner as to allow for removing and replacing the speaker enclosure (12) from or on the device (10) without removing a corner bracket (26,226) component of the device (10) from the wall (14,16).

1. Field of the Invention
The present invention relates to a mounting device for mounting a speaker enclosure or cabinet in an elevated position at a vertical or horizontal intersection of two walls, a wall and a ceiling, or similar structures, wherein the device facilitates easily locating supportive studs underlying surface sheathings, and is adapted to couple with and support the speaker enclosure in such a manner as to allow for dismounting and remounting the speaker enclosure from or on the device without dismounting the device itself from the structures.
2. Description of the Prior Art
Those with skill in the art of home audio or theater systems and speaker enclosures or cabinets will appreciate that it is often desirable to mount a speaker enclosure in an elevated position at a vertical or horizontal intersection of two walls, a wall and a ceiling, or similar structures. Unfortunately, a number of problems are encountered when attempting to do so, including difficulty locating studs or similar structures capable of supporting the speaker enclosure and a mounting mechanism, and difficulty and inconvenience in dismounting and remounting the speaker enclosure for maintenance or replacement.
The studs are constructed of wood or metal for supporting the walls, and typically spaced between twelve and twenty-four inches apart depending on a number of factors, including use and load bearing requirements. Each wall is framed with corner studs, such that an intersection of the walls results in first and second perpendicularly-oriented closely spaced or abutting studs. The studs are covered with a sheathing such as, for example, sheet rock or wood paneling. The wall sheathing is typically unsuitable for supporting substantial loads, such as the speaker enclosure, so any such load mounted on the surface must be secured to one or more underlying studs for reliable support. Unfortunately, it will be appreciated, locating the studs hidden beneath the sheathing can be very difficult. Furthermore, fasteners driven into the an improperly located stud may split or otherwise damage the stud and fail to provide the desired support.
Additionally, recent developments in home theater systems have resulted in speaker enclosures that are larger and heavier than those previously used, thereby making the mounting thereof even more difficult. The speaker enclosures have become larger in order to house more complex crossover networks and bigger speaker magnets, which provide improved control over speaker cone movement. Furthermore, speaker enclosures have become heavier due to use of heavier materials from which the speaker enclosures are constructed, with the heavier speaker enclosures providing improved bass response and reduced resonance.
Once properly mounted, it may at some point become necessary to dismount the speaker enclosure for maintenance or replacement, after which the same or a different speaker enclosure must be remounted. Unfortunately, many existing mounting schemes do not allow for convenient dismounting and remounting, and some require that the mounting mechanism itself be dismounted and remounted or that the fasteners be withdrawn and reapplied to the studs. It will be appreciated that either action can result in damage to the sheathing or the studs and may ultimately undermine their supportive qualities and cause structural failure.
Due to the above-identified and other problems and disadvantages in the art, a need exists for an improved speaker mounting mechanism.
The present invention overcomes the above-identified and other problems and disadvantages in the art to provide a mounting device for mounting a speaker enclosure or cabinet in an elevated position at a vertical or horizontal intersection of two walls, a wall and a ceiling or similar first and second structures, wherein the device facilitates easily locating supportive studs hidden beneath surface sheathings, and is adapted to couple with and support the speaker enclosure in such a manner as to allow for conveniently dismounting and remounting the enclosure from and on the device without dismounting the device itself from the walls.
The preferred mounting device comprises a corner bracket and an upper and a lower mounting plate. The corner bracket presents a substantially triangular cross-section, is made of aluminum, plastic, or a similarly suitable material, and, in a preferred embodiment, presents five surfaces. The first and second surfaces are corner-facing surfaces and intersect each other at an approximate 150xc2x0 angle. The third and fourth surfaces are wall-facing and intersect the first and second surfaces, respectively, at approximate 150xc2x0 angles. The fifth surface is speaker-facing and intersects the third and fourth surfaces at approximate 45xc2x0 angles, thereby completing and closing the substantially triangular corner bracket. The speaker-facing surface is oriented substantially perpendicular to a plane bisecting the intersection of the walls and provides a coupling mechanism whereby the speaker enclosure may be removably coupled with the mounted corner bracket. In a preferred embodiment, the coupling mechanism comprises an upper and a lower elongated slot or groove in the speaker-facing surface and operable to removably receive upper and lower fasteners associated with the upper and the lower mounting plates.
The mounting plates are secured to a rear portion of the speaker enclosure and incorporate or receive the fasteners. The fasteners may be any suitable coupling mechanism, such as, for example, threaded bolts or fixed mounting posts. Various alternative embodiments of both the corner bracket and the mounting plates are possible, a representative sample of which are presented herein.
In operation, the corner bracket is positioned at the intersection of two walls or a wall and a ceiling. Fasteners driven into holes provided in the corner-facing surfaces automatically align with the underlying corner studs, thereby ensuring proper support. The wall-facing surfaces will abut the walls, and cutouts let into the wall-facing surfaces will correspond to holes in the walls wherethrough speaker wires are able to exit the walls, enter the an interior portion of the corner bracket, and connect to the rear portion of the speaker enclosure. The mounting plates will have been attached to the speaker enclosure using wood screws or an equivalent means. Thereafter, the enclosure may be lowered onto the speaker-facing surface of the bracket such that the upper and lower fasteners are securely received within the elongated grooves. The fasteners are then tightened to complete the mounting process. Dismounting the speaker enclosure is easily accomplished by loosening or removing the fasteners and lifting the enclosure from the mounted bracket.
Thus, it will be appreciated that the present invention offers a number of advantages over the prior art, including a mechanism whereby the corner studs are automatically and reliably located. Furthermore, once mounted, the speaker enclosure may be easily dismounted by loosening the bolts and lifting the enclosure from the corner bracket, without having to dismount the corner bracket itself.
These and other important aspects of the present invention are more fully described in the section entitled DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT, below.


An information processing apparatus for outputting a display signal to a display device includes a memory unit for storing a plurality of display specification setting instructions for specifying display specifications of a plurality of display devices having different specifications form each other, an instruction execution unit for reading one of the display specification setting instructions from the memory unit in response to an identification signal to execute the display specification setting instruction and a display controller for outputting the display signal in accordance with the display specification of the display specification setting instruction. The display signal in accordance with the display specification of the display device is inputted to the display device.

The present invention relates to an information processing apparatus such as a small size information equipment, for example, a notebook computer.
As a display for a notebook computer, a TFT (Thin Film Transistor) type liquid crystal display device (TFT liquid crystal panel) which provides a high display quality but is expensive and an STN (Super Twisted Nematic) type liquid crystal display device (STN liquid crystal panel) which is inexpensive but exhibit high flicker are frequently used. In Japanese Patent Application laid-open No. JP-A-1-277890, an information processing apparatus is constructed by using a dual scan type STN type liquid crystal display device, and in JP-A5-249928, an information processing apparatus is constructed by using the TFT type liquid crystal display device.
FIG. 25 shows a schematic configuration of a conventional personal computer. As shown, a TFT type liquid crystal display device 2 is connected to a personal computer main unit 1 which includes a CPU (central processing unit) 3, a main memory 4, a BIOS (Basic Input/Output System) ROM 5 which stores display specification setting instructions for the TFT type liquid crystal display device 2, a display controller 6, a display memory 7, and a connector device 8 for connecting the personal computer main unit 1 and the TFT type liquid crystal display device 2. The CPU 3, the BIOS ROM 5 and the display controller 6 are arranged on a main board (not shown). The display specification means information on a display system such as a display screen size (the numbers of horizontal and vertical dots), the number of colors and a clock frequency.
FIG. 26 shows a schematic configuration of another prior art personal computer. As shown, an STN type display device 9 is connected to a personal computer main unit 9 which comprises a CPU 3, a main memory 4, a BIOS ROM 10 which stores display specification setting instructions for the STN type liquid crystal display device 9, a display controller 6, a display memory 7 and a connector device 11 for connecting the personal computer main unit 1 and the STN type liquid crystal display device. The CPU 3, the BIOS ROM 10 and the display controller 6 are arranged on a main board (not shown).
In those personal computers, since the display systems of the TFT type liquid crystal display device 2 and the STN type liquid crystal display device 9 are different from each other, the BIOS ROMs 5 and 10 for storing the display specification setting instructions must be provided for each of the display systems. Accordingly, since the main boards for the liquid crystal display device cannot be fully identical, it is not permitted to connect the TFT type liquid crystal display device 2 and the STN type liquid crystal display device to one personal computer main unit 1.
As a result, when a user who has purchased a personal computer which uses the inexpensive STN type liquid crystal display device 9 for economic reasons, desires to change the display device to the high quality TFT type liquid crystal display device 2 because of the flicker problem, he must newly purchase a personal computer which uses the TFT type liquid crystal display device. Further, since a dedicated main board for the liquid crystal device must be prepared for each type of the TFT type liquid crystal display device 2 and the STN type liquid crystal display device 9, it is difficult to promote the sharing of the components used and the manufacturing cost increases. Further, when the personal computers are assembled, the main boards for the two types of liquid crystal display devices must be selected, which takes manpower and time. Recently, application software which handle motion pictures and natural pictures have been becoming popular but since the exchange of only the display device is not permitted, the user must be patient with the STN type liquid crystal display device which exhibits a high flicker and poor image quality or must newly purchase a personal computer which uses the TFT type liquid crystal display device 2. In this case, even if the CPU 3, the main memory 4 and the hard disk do not involve any problems, the user must purchase unnecessary parts.
For an attachment device as shown in FIG. 27 which comprises a bus for exchanging information with the microcomputers 14, and 15 and the personal computer main unit 1 such as a keyboard 12 or a mouse 13, the personal computer main unit 1 can identify the type of the device at the system boot-up, but for the device such as the display device which has no means for conveying information to the personal computer main unit 1, it is not possible to identify the type.


A method of manufacturing a semiconductor device of the present invention includes (a) sequentially forming a gate insulating film 14, a first conductive layer 15 and a first insulating film 16 on a semiconductor layer 13 provided on an insulating film 12; (b) selectively removing the semiconductor layer, the gate insulating film, the first conductive layer and the first insulating film to form a device isolation trench; (c) forming a second insulating film 17 in the device isolation [element separation] trench, wherein a height of an upper surface of the second insulating film is substantially coincident with that of an upper surface of the first insulating film; (d) removing a part of the second insulating film and the first insulating film such that a height of an upper surface of the exposed first conductive layer is substantially coincident with that of the top surface of the second insulating film; and (e) patterning the first conductive layer to form a gate electrode.

The request of a miniaturization and high density fabrication of LSI has become much severer, and a sub 100-nm generation has come. On the other hand, the request of a low power consumption and high speed operation has been increased. It becomes difficult to satisfy those requests by using a conventional bulk substrate.
MISFET (Metal-Insulator-Semiconductor Field Effect Transistor) formed on an SOI substrate is expected as a ULSI element in the sub 100-nm generation, since junction capacitances in source and drain regions are small, a substrate bias effect is low and a sub-threshold characteristic is excellent, as compared with conventional MISFET formed on a bulk substrate.
The SOI-MISFET is grouped into two kinds of operation modes of a fully-depleted SOI-MISFET (hereafter, referred to as an FD-type SOI-MISFET) and a partially-depleted SOI-MISFET (hereafter, referred to as PD-SOI-MISFET). In the FD-type SOI-MISFET, the film thickness of a SOI layer is thinner than a maximum depletion layer (a body region is always in a depleted state), whereas in the PD-type SOI-MISFET, the film thickness of the SOI layer is thicker than a maximum depletion layer. In particular, the FD-type SOI-MISFET could be expected as the ULSI element having a low voltage operation and an excellent ultra high speed operation since a sharp sub-threshold characteristic can be obtained. In the FD-type SOI-MISFET in the sub 100 nm generation, the film thickness of a silicon layer on an SOI substrate is reduced to about 10 nm or less.
A method of manufacturing a conventional SOI-MISFET will be described below.
At first, a case that a shallow trench isolation (hereafter, referred to as STI) is applied to a typical MISFET on a bulk substrate will be described with reference to sectional views of FIGS. 1A to 2B (hereafter, referred to as a first conventional example). An SOI substrate is provided which has a silicon substrate 51, a buried oxide film 52 and a silicon film 53 (FIG. 1A). A pad oxide film 54 having the film thickness of about 5 nm and a stopper nitride film 55 of about 120 nm are sequentially deposited. Then, by using a photo-lithography and a reactive ion etching (hereafter, referred to as RIE) method, the stopper nitride film 55, the pad oxide film 54 and the silicon film 53 are patterned to an island shape, and element isolation trenches are formed (FIG. 1B). Subsequently, an STI embedded insulating film 57 is deposited, and a chemical mechanical polishing (hereafter, referred to as CMP) method is used to flatten the STI embedded insulating film 57 (FIG. 1C).
Next, the stopper nitride film 55 is removed by wet etching of hot phosphoric acid, and the pad oxide film 54 is removed by wet etching of fluoric acid, such that the silicon film 53 is exposed (FIG. 1D). At this time, the buried oxide film 52 in the lower portion of the silicon film 53 is over-etched 59. Then, a gate insulating film 60 is formed, and a polysilicon film 61 is deposited, and then is patterned to form a gate electrode (FIG. 2A). Subsequently, side wall insulating films 63, source and drain regions 64 and a silicide film 65 are formed, and an interlayer insulating film 66 is deposited. Then, contact holes are opened, and metal wirings 67 are formed. Thus, the MISFET is formed (FIG. 2B). FIG. 2C is a plan view showing the MISFET. FIGS. 1A to 2B are sectional views of the MISFET along a line A–A′ of FIG. 2C.
FIGS. 3A to 3D are sectional views showing a method of forming an element insulation region disclosed in Japanese Laid Open Patent Application (JP-A 2001-24202) (hereafter, referred to as a second conventional example). A gate insulating film 68 and a first polysilicon film 70 are deposited in this order on the surface of the silicon film of the SOI substrate in which the buried oxide film 52 and the silicon film 53 are laminated on a silicon substrate 51. Then, the first polysilicon film 70, the gate insulating film 68 and the silicon film 53 are patterned by using a same mask (FIG. 3A). Subsequently, an STI embedded insulating film 69 is deposited on the entire surface, and is flattened by using a CMP method (FIG. 3B).
Next, a second polysilicon film 71 is deposited on the entire surface, and a mask pattern 58 of photo resist is formed (FIG. 3C). By using this mask pattern 58, the second polysilicon film 71, the first polysilicon film 40 and the gate insulating film 68 are patterned by a RIE method. Here, the first polysilicon film 70 functions as a gate electrode 70a, and the second polysilicon film 71 functions as a gate electrode wiring line 71a through which gate electrodes of transistors adjacent to each other are connected. Subsequently, source and drain regions 64 are formed by ion implantation. Thus, the structure of FIG. 3D is obtained.
In the SOI-MISFET, it is known that the exposure of ends 72 of an element region causes a leak current to flow. However, according to this element insulation method, the side of the silicon film 53 on which the element is formed is covered with the STI embedded insulating film 69. Thus, the ends 72 of the element region are not exposed, and the leak current is suppressed (it should be noted that the location where the leak current is generated is the end existing in a direction perpendicular to FIG. 3D, but it is shown in FIG. 3D for the illustrative convenience).
A typical film thickness of a silicon film is about 10 nm in a higher density generation. However, if the STI structure is applied to the SOI-MISFET having such a thin silicon film, there are the following problems in the first conventional example. After the formation of the shape shown in FIG. 1C, the stopper nitride film 55 is removed by the wet etching method of the hot phosphoric acid, and the pad oxide film 54 is further removed by the wet etching method of HF. At this time, the STI embedded insulating film 57 is also etched by HF at the same time. Thus, as shown in FIG. 1D, the buried oxide film 52 under the silicon film 53 is over-etched (numeral 59 of FIG. 1D). In particular, if the silicon film 53 is thin (for example, in a case of 10 nm), when the pad oxide film 54 is etched, the entire STI embedded insulating film 57 on the side of the silicon film 53 is easily lost through the etching. Therefore, the over-etching 59 is extremely easily caused in the lower corner of the end of the silicon film 53.
Moreover, the gate insulating film 60 is formed in the state that the buried oxide film 52 at the lower corner of the end of the silicon film 53 is over-etched. Then, the polysilicon film 61 is deposited. Subsequently, when the polysilicon film 61 is patterned, a residual polysilicon film 62 is left in the over-etched portion 59 (FIG. 2A).
As shown in the plan view of FIG. 2C, the residual polysilicon film 62 is formed to surround an active region (an island region). This results in the connection between the residual polysilicon film 62 and the polysilicon film 61 on a B–B′ section. At this time, if two or more gate electrodes are arranged in parallel to each other, the gate electrodes are short-circuited to each other through the residual polysilicon film 62. In addition, a capacitance generated between the residual polysilicon film 62 and each of the source and drain regions 64 functions as a parasitic capacitance connected in parallel to the gate capacitance. This increases a load on the circuit to decrease the operation speed. Also, if the insulation characteristic of the gate insulating film 60 is deteriorated due to the damage caused by the ion implantation to form the source and drain regions 64, there may be a possibility that an electric short-circuit is caused between the gate electrode and the each of the source and drain regions 64 through the residual polysilicon film 62.
Also, if the formation of the over-etched portion 59 causes the element end to be exposed, a leak current easily flows in the end (numeral 72 of FIG. 3D) of the element region.
Moreover, in the first conventional example, the end of the element region is exposed so that the gate electrode is formed to cover the side of the element region. Therefore, the electric field applied to the silicon film from the gate electrode is increased. Thus, the reverse narrow channel effect becomes severe to decrease the threshold through the miniaturization.
In order to prevent the above-mentioned over-etching, it could be considered to strictly control the wet etching of the pad oxide film 54 by HF, although this control is very difficult actually. At this time, a step will be generated as shown in FIG. 4. This is because the film thickness of the pad oxide film 54 is very thinner than that of the STI embedded insulating film 57. Also, if the wet etching with HF is continued in order to remove this step, the above-mentioned over-etched portion would be generated.
Here, the problem when the step is generated will be described with reference to FIG. 5. In case of the existence of such a step, when the polysilicon film 61 is deposited (FIG. 5A) after the formation of the gate insulating film 60, and the gate electrode is formed by etching this polysilicon film 61 by the RIE method, non-etched polysilicon films 62 is remained in the step portions (FIG. 5B). This residual polysilicon film 62 acts as a cause of short circuit between the polysilicon films or between the gate electrode and each of the source and drain regions. Also, such a step deteriorates the shape of a resist pattern for a gate electrode in a lithography step.
Also, in the second conventional example, if a polishing operation is carried out by the CMP method in order to process as shown in FIG. 3B, the first polysilicon film 70 is polished deeper than the STI embedded insulating film 69, because a polishing rate of the polysilicon film is typically larger than a polishing rate of the oxide film. This results in the formation of a step (FIG. 6A). Moreover, the first polysilicon film 70 can not function as a stopper to the polishing operation in the CMP method. Therefore, if the polysilicon film is a thin film, there may be a possibility that the polysilicon film is perfectly lost (FIG. 6B).
By the way, a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-74538). The semiconductor device of this conventional example has a substrate having an insulating layer. A first conductive type semiconductor layer is formed on the insulating layer such that a part of the semiconductor layer functions as a channel region. A gate insulating film is formed on the channel region of the semiconductor layer, and a gate electrode is formed on the gate insulating layer. A second conductive type source and drain regions are respectively formed on both sides of the channel region within the semiconductor layer. A hole removing region is formed in a region within the semiconductor layer, and the hole removing region is adjacent to the channel region and at least one region of the source region and the drain region, and has a function of preventing the accumulation of a hole of a pair of a hole and an electron generated in the channel region.
Also, a SOI device is disclosed in Japanese Laid Open Patent Application (JP-A 2001-24202). The SOI device of this conventional example contains an SOI substrate constituted of a lamination structure of a base substrate, a buried oxide film and a semiconductor layer. An oxide film is formed so as to be in contact with the buried oxide film in a semiconductor portion of a field region so as to determine an active region. Each of gate electrode patterns has a gate oxide film formed only on the active region, and source and drain regions are formed within the active regions of the semiconductor layer on both sides of the gate electrode pattern. A gate electrode line is formed on the gate electrode pattern and the field region to connect the gate electrode patterns formed on the respective aligned active regions.
Also, a separation structure of a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 11-67895). The separation structure of the semiconductor device includes a semiconductor substrate having an active region and a field region. A buried insulating layer is formed in a predetermined depth within the active region of the semiconductor substrate, and a separation layer is formed in a position deeper than the buried insulating layer within the field region of the semiconductor substrate.

Semiconductor device and method that includes reverse tapering multiple layers