One piece of information used in setting up the optimum location registration area is an area of a peripheral cell. However, in the current system, the area of a cell is set up by the predicted number of subscribers in the area, and therefore, depends on the location. Therefore, when a mobile communication terminal computes the optimum location registration area, it is necessary to obtain the size information about the peripheral cell, which can cause the problem of traffic. The mobile communication terminal in a cell signals a plurality of paging point nodes of mobility and traffic characteristic. Then, the plurality of paging point nodes sets up a location registration area of the mobile communication terminal according to the above mentioned information and network information. Thus, the location management of the mobile communication terminal can be efficiently realized, thereby reducing the traffic.

1. Field of the Invention
The present invention relates to a method of location registration, a location registration system, a mobile communication terminal, an equipment for setting up location registration area, program for setting up location registration area, and more specifically to setting up a location registration area (also referred to as a location area) of a mobile communication terminal in a mobile communication system.
2. Description of the Related Art
In the conventional mobile communication system, the location of a mobile communication terminal not in communications is managed by location registration area formed by a plurality of cells. In the conventional mobile communication system, a location registration area is fixedly set beforehand in a network, and is unified for all terminals.
Generally, a change of a location registration area is triggered by a mobile communication terminal not in communications exiting an old location registration area and entering a new location registration area. When the terminal detects a change of location registration area identification information advertised by a base station, it notifies the network of the change, and the location registration area information about the mobile communication terminal is changed in the network. When a communication request for the terminal not in communications occurs, paging (general call) request signals are transmitted to all cells in the location registration area of the terminal in the network. Then, upon receipt of the paging request, the terminal returns a paging response to the network. Thus, the network can be informed of the cell (base station in the network) in which the terminal is located.
Assume that the optimum location registration area obtains the minimum sum of the location registration traffic of the terminal and the paging traffic. Then, the optimum location registration area depends on the mobility and traffic characteristics of the terminal. Therefore, the optimum location registration area generally different for each terminal. Furthermore, the mobility and traffic characteristics of the terminal change with time, the optimum location registration area for one terminal also changes with time.
Therefore, conventional method of the location management which uses the unified and fixed location registration area is inefficient. That is, in the conventional method, for example, the location management is performed in the same location registration area for a static mobile communication terminal and a mobile communication terminal which frequently changes its location registration area. Therefore, a wasteful traffic can arise when the location registration and paging operation are performed. Namely, the conventional method is insufficient.
The technology for solving the above mentioned problems can be, for example, in Japanese Unexamined Publication No. Heisei 7-322333. As a method of setting up a location registration area for each mobile communication terminal, this publication discloses a method of the mobile communication terminal computing and setting up the optimum location registration area, and a method of the base station computing and setting up the optimum location registration area.
However, the location registration system in the method disclosed in the above mentioned publication pays attention only to the traffic in the radio region, and the traffic in the mobile communication network is not considered.
Furthermore, in the location registration system in the method disclosed by the above mentioned publication, the mobile communication terminal or the base station determines a location area. Thus, there can be a problem with the traffic which the size information about peripheral cells required in setting up a location area is computed.
That is, an area of a peripheral cell is a piece of the information used in setting up the optimum location registration area. However, in the current system, an area of a cell is set up based on the predicted number of subscribers, and therefore depends on the location. For example, the areas of cells are different between a downtown area and a suburban area. Therefore, in the method of the above mentioned publication, it is necessary to obtain the size information about the peripheral cells when the mobile communication terminal computes the optimum location registration area, and there can be a problem with the traffic therewith.
The present invention has been developed to solve the problems with the above mentioned conventional technology. And an object of the present invention is to provide a location registration method, a location registration system, a mobile communication terminal, a location area setting equipment, and a location area setting program which are capable of realizing efficient location management of the mobile communication terminal with reduced traffic.

Method of location registration, location registration system, mobile communication terminal equipment for setting up location registration area, and program for setting up location registration area


According to an embodiment of the present invention, a computer implemented method and system for automatically implementing a fraud strategy may involve identifying transaction data related to a customer transaction based on a payment instrument; automatically identifying a pattern based on one or more factors associated with a customer spending profile; identifying a potential fraud situation based on the identified pattern and the transaction data; executing an action for the potential fraud situation; and adjusting authorized use of the payment instrument.

Currently, fraud pattern detection is a manual process that involves culling through billions of transactions to find fraud patterns. Fraud detection is not an exact science and often transactions from good customers are declined as well as fraudsters, thereby negatively impacting customer relations. The timeliness of fraud detection is also a major concern. In many instances, fraudulent charges are not discovered until the customer receives his or her statement and disputes the charge. By this time, fraudsters have made a major negative impact on their targets.
When fraudulent charges are detected, the customer will be told that his current card will be de-activated and a new card is on the way. During this waiting period, the customer is not able to use his card until he receives his new one.
Other drawbacks may also be present.

Method and system for automating fraud authorization strategies


A system and method for performing a magnetic resonance elastography (MRE) procedure using an MRI system to monitor operation of a medical device performing a medical procedure. The driver system includes a housing, a port located in the housing and connected to a driving power, and an inertial driver moved within the housing by the driving power. A passage is formed in the housing and extends from a first opening in the housing, through the inertial driver, and to a second opening in the housing. The inertial driver receives a medical device extending through the passage and engages the medical device to impart oscillatory motion thereto as the inertial driver is moved by the driving power. The imparted oscillatory motion travels along the medical device as a waveguide to deliver the oscillatory motion to tissue receiving the medical procedure to perform the MRE procedure.

The field of the invention is nuclear magnetic resonance imaging methods and systems. More particularly, the invention relates to devices for implementing magnetic resonance elastography (MRE) in conjunction with the use of insertable or interventional medical devices.
The physician has many diagnostic tools at his or her disposal which enable detection and localization of diseased tissues. These include x-ray systems that measure and produce images indicative of the x-ray attenuation of the tissues and ultrasound systems that detect and produce images indicative of tissue echogenicity and the boundaries between structures of differing acoustic properties. Nuclear medicine produces images indicative of those tissues which absorb tracers injected into the patient, as do PET scanners and SPECT scanners. And finally, magnetic resonance imaging (MRI) systems produce images indicative of the magnetic properties of tissues. It is fortuitous that many diseased tissues are detected by the physical properties measured by these imaging modalities, but it should not be surprising that many diseases go undetected.
Historically, one of the physician's most valuable diagnostic tools is palpation. By palpating the patient, a physician can feel differences in the compliance of tissues and detect the presence of tumors and other tissue abnormalities. Unfortunately, this valuable diagnostic tool is limited to those tissues and organs that the physician can feel, and many diseased internal organs go undiagnosed unless the disease happens to be detectable by one of the above imaging modalities. Tumors that are undetected by existing imaging modalities and cannot be reached for palpation through the patient's skin and musculature, are often detected by surgeons by direct palpation of the exposed organs at the time of surgery. Palpation is a common method for detecting tumors of the prostate gland and the breast, but unfortunately, deeper portions of these structures are not accessible for such evaluation. An imaging system that extends the physician's ability to detect differences in tissue compliance throughout a patient's body would extend this valuable diagnostic tool.
It has been found that MR imaging can be enhanced when an oscillating stress is applied to the object being imaged in a method called MR elastography (MRE). The method requires that the oscillating stress produce shear waves that propagate through the organ, or tissues to be imaged. These shear waves alter the phase of the MR signals, and from this the mechanical properties of the subject can be determined. In many applications, the production of shear waves in the tissues is merely a matter of physically vibrating the surface of the subject with an electromechanical device such as that disclosed in U.S. Pat. No. 5,592,085. For example, shear waves may be produced in the breast by placing the breast in direct contact with the oscillatory device. Also, with organs like the liver that are difficult to directly palpate, shear waves can be produced indirectly within the tissue by applying the oscillatory force to the exterior surface of the body and allowing the waves to propagate into the organ.
A number of driver devices have been developed to produce the oscillatory force needed to practice MRE. As disclosed in U.S. Pat. Nos. 5,977,770, 5,952,828, 6,037,774, and 6,486,669, these typically include a coil of wire through which an alternating current flows. This coil is oriented in the polarizing field of the MRI system such that it interacts with the polarizing field to produce an oscillating force. This force may be conveyed to the subject being imaged by any number of different mechanical arrangements. Such MRE drivers can produce large forces over large displacement, but they are constrained by the need to keep the coil properly aligned with respect to the polarizing magnetic field. In addition, the current flowing in the driver coil produces a magnetic field which can alter the magnetic fields during the magnetic resonance pulse sequence resulting in undesirable image artifacts.
Another approach is to employ piezoelectric drivers as disclosed in U.S. Pat. Nos. 5,606,971 and 5,810,731. Such drivers do not produce troublesome disturbances in the scanner magnetic fields when operated, but they are limited in the forces they can produce, particularly at larger displacements. Piezoelectric drivers can also be oriented in any direction since they are not dependent on the polarizing magnetic field direction for proper operation.
Yet another approach is to employ an acoustic driver system as described in U.S. Pat. Nos. 7,034,534 and 7,307,423. The acoustic driver system includes an active driver located remotely from the MRI system and acoustically coupled by a tube to one or more passive drivers positioned on the subject being imaged. The passive drivers do not disturb the magnetic fields and may be oriented in any direction.
MRE-based tissue stiffness measurements could be important for detecting prostate and rectal cancer, and evaluating the cancer cell death due to thermal ablation. However, these tissues of interest are deep in the body surrounded by normal soft tissues, which makes the conventional external MRE driver not optimal because the waves are not significantly attenuated as they propagate toward these deeper tissues.
On the other hand, some existing MRI-related applications that use insertable catheters, such as endourethral/endorectal MRI and MRI-guided percutaneous thermal ablation, have the benefit of direct access to the tissue in the vicinity of the tip of the catheter where RF coils and heat sources are located, which results in better imaging SNR and better ablation reliability respectively. To measure the MRE-based tissue stiffness in the vicinity of catheter, the above-described conventional external MRE drivers are not suitable because the driver needs to be physically positioned on the surface of the subject's body, and often must be fastened by a supporting belt or frame, which increases the potential for positioning conflicts with the catheter. Furthermore, the above-described conventional, external MRE drivers are not suitable because the wave SNR is degraded because of tissue attenuation along the distance between the external driver and the tissue of interest at the tip of the catheter.
Therefore, it would be desirable to have a system and method for performing MRE studies of organs, such as the prostate, and other areas of the body that are not amenable to MRE imaging using traditional MRE drivers due to particular internal locations in the body, such as near other tissue structures that impede the delivery of the requisite waves to the target tissue. Additionally, it would be desirable to have a system and method for performing MRE studies during insertable or interventional procedures without impeding the clinician's ability to seek positions desirable for the interventional procedure and without degraded wave SNR caused by the insertable or interventional device.

System and method for inertial magnetic resonance elastography driver for use with interventional medical device

MAYO FOUNDATION FOR MEDICAL EDUCATION AND RESEARCH


Calcium-substituted polymeric reagents are provided. These reagents can be prepared via the oxidative addition of a soluble highly reactive calcium species to organic and inorganic polymers containing alkyl, aryl, or alkylaryl pendent groups substituted with halide atoms, cyanide molecules, 1,3-dienes, or any conjugated polyunsaturated system. Preferably, the polymer is a cross-linked p-bromopolystyrene, p-chloropolystyrene, p-fluoropolystyrene, or chloromethylated polystyrene. Preferably, the soluble highly reactive calcium species is prepared from the reduction of Ca(II) salts with an alkali metal arene, such as lithium biphenylide. These calcium-substituted polymeric reagents react with a variety of electrophiles to yield functionalized polymers. Reaction with Cu(I) salts yields calcium-substituted polymeric cuprate reagents, which can react, for example, with acid chlorides to form ketones, alkyl halides containing functionality, and undergo 1,4-conjugate addition with .alpha.,.beta.-unsaturated ketones, aldehydes, esters, and amides. Bifunctionalization of the polymer can be achieved by the addition of highly reactive calcium to a functionalized polymer containing a halogen. Polymers can be cross-coupled with dyes, UV stabilizers, biologically active substrates, molecules that impart specifically desired characteristics, among other desirable functional groups.

Polymers permeate every aspect of today's society. Moreover, advances in our society are keenly tied to advances in new materials, particularly polymers. Unfortunately, however, we are limited in the types of polymers that can be prepared. For example, polymers containing a wide variety of desirable functional groups can not be prepared, or if they can be prepared, it is only with great difficulty. Thus, using presently known techniques it is generally difficult to modify polymers. For example, it is typically difficult to modify the surfaces of polymers to attach dyes, UV stabilizers, or molecules that impart conducting properties, magnetic properties, nonlinear optical properties, etc.
Furthermore, insoluble polymers, such as cross-linked polystyrene resins and functionalized polystyrene resins, are highly desirable reagents in organic synthesis. For example, insoluble polymers are important reagents in organic synthesis as protecting groups and in asymmetric syntheses as chiral auxiliaries. They are also important reagents in solid-phase synthesis, and as supports for chromatography and catalysis.
Methods for chemically modifying polymers, i.e., functionalizing, polymers, such as cross-linked polystyrene resins, typically involve: (1) lithiation of p-bromopolystyrene; (2) lithiation of polystyrene; and (3) nucleophilic substitution on chloromethylated polystyrene. These transformations of insoluble polymers normally occur with a soluble reagent interacting in intimate fashion with an insoluble polymer. This occurs, for example, in the preparation of lithium and potassium derivatives of chloromethylated polystyrene. Furthermore, insoluble Grignard reagents have been prepared in THF from the addition of a soluble magnesium anthracene to lightly cross-linked polymers containing chloromethyl groups and alkyl/aryl bromides. These reagents, however, have limited applicability.
The use of functionalized polymers in organic chemistry, particularly those containing metal atoms, has been slowed by the insoluble form in which most metals are typically found. Thus, there are relatively few effective techniques available to prepare functionalized polymers, particularly containing metal atoms.
An object of this invention is to generate novel functionalized polymers, both soluble and insoluble, that may not be available using standard polymerization techniques. Furthermore, an object of this invention is to develop a method for modifying the surfaces of soluble and insoluble polymers to attach dyes, UV stabilizers, drug systems, biologically active substrates, molecules that impart conducting properties, magnetic properties, nonlinear optical properties, adhesive properties, thermal stability, or increased strength. Another object of this invention is to produce a wide variety of calcium-substituted polymeric reagents that can be used to produce new organic compounds, new functionalized polymers, and new, more direct methods of synthesis. Yet another object of this invention is to produce a wide variety of calcium-substituted polymeric reagents that can be used to produce novel polymers, which upon cleavage can be used to synthesize novel monomers and organic products.

Preparation of functionalized polymers utilizing a soluble highly reactive form of calcium

Board of Regents of the University of Nebraska


The present invention relates to a compact zoom lens system having a long back focus and a zoom ratio of about 1.7, which comprises a first lens unit G1 having a positive focal length, a second lens unit G2 having a positive focal length and a third lens unit G3 having a negative focal length, said first, second and third lens units G1, G2 and G3 being all movable toward the object side during zooming from the wide angle to telephoto side such that the first and second lens units G1 and G2 are spaced away from each other, while the second and third lens units G2 and G3 are moved toward each other, and is characterized by conforming to the following conditional formula: EQU 0.34<f.sub.3 (1-.beta..sub.3W)/f.sub.W <1.00, (1). and EQU 0.30<f.sub.2 /f.sub.W <0.90, (2). where f.sub.W is the focal length of the total system at the wide angle end, .beta..sub.3W is the image-formation magnification of the third lens unit at the wide angle end, and f.sub.2 and f.sub.3 are the focal lengths of the second and third lens units, respectively.

This invention relates to a compact zoom lens system having a zoom ratio of about 1.7 and so lending itself well fit for lens shutter cameras, etc., and more particularly to a zoom lens system comprising three units, say, positive, positive and negative units.
In recent years, zoom lenses smaller in size and lighter in weight have been increasingly demanded to keep pace with lens shutter cameras having a more increased zooming function. A size reduction of zoom lenses for recent lens shutter cameras is tantamount to decreasing mainly the axial length of the lens system (the length from the first surface of the lens system to the film plane). In most cases, this is now achieved by retracting the barrel into the body of a camera when it is kept. However, it is then required to use some barrel-retracting mechanism, which sets limits to the size reduction of a camera body; in other words, the size reduction of a camera should be achieved by reducing the diameters of the lenses or making the optical system short.
So far, some three-unit zoom lenses have been proposed, which comprise a first lens unit having a positive focal length, a second lens unit having a positive focal length and a third lens unit having a negative focal length. Among them, zoom lenses having a zoom ratio of about 1.5 are disclosed in Japanese Provisional Patent Publications Nos. Sho. 60-263113, 61-52620 and 61-109012 and those having a zoom ratio of about 2.0 are set forth in Japanese Provisional Patent Publication No. Hei. 1-93713. These are all made compact in the axial direction while maintaining the power of each unit properly, but they are not in the diametrical direction of the lenses, because the diameter of the image-side lens is increased due to their short back focus. In addition, their short back focus gives rise to a reduction in their distance from the final surface of the lens system to the film plane; flaring is much likely to occur because the light reflected off the image plane is again reflected from the final surface.


A method and system for reducing operational shock sensitivity of a MEMS device includes a closed-loop control circuit for controlling the MEMS device and a shock detector for detecting a shock experienced by the MEMS device. The closed-loop control circuit includes a movable MEMS structure, a detector for sensing a position of the MEMS structure and for providing a first feedback signal related to the sensed position, and a processor for receiving the first feedback signal and for providing a control signal used to control the MEMS device. The shock detector, which according to a preferred embodiment is the MEMS structure itself, is used for detecting the shock experienced by the MEMS device and for generating a second feedback signal, which is used to alter the control signal such that a response of the closed-loop control circuit to the shock is minimized.

Microelectromechanical systems (MEMS) integrate electrical and mechanical components on a single substrate, such as silicon, using microfabrication technologies. Typically, the electrical components are fabricated using integrated circuit processes, while the mechanical components are fabricated using micromachining processes that are compatible with the integrated circuit processes.
MEMS devices are found in an increasing number of applications, from sensor technology, to biomedicine, to telecommunications. Presently, some of the most interesting applications for MEMS devices are optical applications, wherein the tiny mechanical components include mirrors, prisms and/or gratings. For example, in the area of telecommunications, optical MEMS devices form optical switches, modulators, attenuators, and filters.
In most MEMS devices, one or more actuators are provided to position the tiny mechanical components. Some examples of MEMS actuators include electrostatic, thermal, electromagnetic, and/or piezoelectric actuators. In order to limit the actuation power, current, or voltage, and thus minimize the size and cost of the MEMS device, MEMS structures are generally designed to require a relatively low actuation energy. For example, when the mechanical components are coupled to the substrate via a cantilever or one or more springs, it is generally preferred that the spring constant(s) be relatively weak. However, MEMS structures with weak spring constants are susceptible to undesired perturbations. For example, mechanical shock or vibration often results in an impulse that occurs at the natural mechanical vibrational frequency of the MEMS structure.
If the MEMS structure is an integral part of a closed loop control system, which is subject to this impulse error, the control system will apply feedback in an attempt to neutralize the error. Unfortunately, most control systems operate at bandwidths much lower in frequency than the natural mechanical frequency of the MEMS structure in order to avoid difficulties associated with lag due to mechanical inertia. Accordingly, as the mechanical impulse damps out, the control system applies a delayed response to compensate. This compensation is not required, and thus introduces a large additional error due to inappropriate delayed feedback. This additional and delayed error significantly contributes to the operational shock sensitivity of MEMS devices.
It is an object of the instant invention to reduce the operational shock sensitivity of MEMS devices.

Method and system for reducing operational shock sensitivity of MEMS devices


An apparatus and method for extracting a desired portion of an image represented by compressed data. The compressed data is expanded in an expanding circuit and outputted therefrom in accordance with clock pulses. Such clock pulses, or data transfers or addresses associated therewith, are counted so as to determine the position of the data. The determined position of the data is compared to the desired portion so as to determine whether the data is within the desired portion. If the data is determined to be within the desired portion, such data is stored in an image memory. As a result, such extraction may be performed without utilizing an additional memory for temporarily storing the expanded data.

The present invention relates to a video processing apparatus and method and, more particularly, to such apparatus and method for use with an electronic still camera for recording and/or reproducing still image digital video signals in a compressed form onto and/or from a recording medium such as an optical disk, a magneto-optical disk or a semiconductor memory.
In a digital recording and/or reproducing type electronic still camera, an image of an object may be supplied through a photographing or charge coupled device (CCD) so as to obtain a video signal. Such video signal may be converted to digital form and compressed in accordance with an image compression technique of the Joint Photographic Experts Group (JPEG) which may utilize a discrete cosine transform (DCT) and variable-length coding. As a result of such JPEG technique, colored still image data may be compressed with a relatively high compression ratio, such as 1 to 1/100. The digital compressed video signal may thereafter be recorded on a recording medium, such as a magneto-optical disk.
The above-described electronic still camera which records data in a digital form onto a magneto-optical disk has numerous advantages. For example, a relatively large number of still image data may be recorded on one disk, the quality of the recorded images may remain substantially high and may not substantially deteriorate over time, compilation of data is relatively easy, and still image data may be copied into a computer. Furthermore, such use is believed to increase in the future.
A user or operator of the digital type electronic still cameras may wish to extract and display only a part of an original image. Additionally, the user may wish to enlarge or reduce a part of an original image, modify it, move or rotate it and so forth. To perform these latter functions, such part of the original image is extracted. Moreover, a part of an original image may be extracted in numerous other situations. For example, consider the situation wherein an original image is read or introduced through a scanner. In such situation, the image may be larger than a display plane and, as such, a part of the original image is cut so as to display the original image in the display plane. However, to perform such extraction of a part of an original image may necessitate processing of the image data and the use of multiple memories as hereinbelow described.
More specifically, since digital type electronic still cameras may record/reproduce still image data which is compressed in accordance with a JPEG technique, a desired area of an original image to be extracted or cut out may not be designated directly from the JPEG-compressed data. Instead, the desired area is designated or extracted from the original image in a non-compressed form. Accordingly, to extract a desired area from JPEG-compressed data, the original image is reconstructed from the JPEG-compressed data and processing pertaining to the extraction of the designated area is performed. That is, all of the data of a field of the JPEG-compressed data is expanded into the original image data, the expanded data (original image) is stored in a memory, a corresponding area on memory is designated, the desired part of the original image is cut out or extracted, and such part is stored in an image memory.
An example of the above extraction procedure is illustrated in FIGS. 9A-9D. That is, as shown in FIG. 9A, JPEG-compressed data is expanded so as to form an original image which is stored in a memory. A read address corresponding to a region A1 is designated from the original image in the memory, and the image of the region A1 is read out. The data in the region A1 is written in an image memory as shown in FIG. 9B. Upon performing a data interpolation or thinning operation or the like, an enlarged or reduced image may be formed as respectively illustrated in FIGS. 9C and 9D and written into the image memory.
The above-described technique, which expands JPEG-compressed data into original image data, stores it in a memory, cuts out a desired part of the original image in a designated area of the memory, and stores it in an image memory, utilizes an additional memory for temporarily storing the original image data expanded from the JPEG-compressed data. As a result, the number of components in a circuit utilized to perform such technique, and/or the complexity thereof, and/or cost thereof may be relatively high.

Apparatus and method for extracting a portion of an image


In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.

Networks enable computers and other devices to communicate. For example, networks can carry data representing video, audio, e-mail, and so forth. Typically, data sent across a network is carried by smaller messages known as packets. By analogy, a packet is much like an envelope you drop in a mailbox. A packet typically includes "payload" and a "header". The packet's "payload" is analogous to the letter inside the envelope. The packet's "header" is much like the information written on the envelope itself. The header can include information to help network devices handle the packet appropriately.
A number of network protocols (e.g., "a protocol stack") cooperate to handle the complexity of network communication. For example, a transport protocol known as Transmission Control Protocol (TCP) provides applications with simple mechanisms for establishing a flow and transferring data across a network. Behind the scenes, TCP transparently handles a variety of communication issues such as data retransmission, adapting to network traffic congestion, and so forth.
To provide these services, TCP operates on packets known as segments. Generally, a TCP segment travels across a network within ("encapsulated" by) a larger packet such as an Internet Protocol (IP) datagram. Frequently, for example, in Local Area Networks (LAN), an IP datagram is further encapsulated by an even larger packet such as an Ethernet frame. The payload of a TCP segment carries a portion of a stream of data sent across a network by an application. A receiver can restore the original stream of data by reassembling the received segments. To permit reassembly and acknowledgment (ACK) of received data back to the sender, TCP associates a sequence number with each payload byte.

This patent is subject to a terminal disclaimer.


According to this invention, there is provided a semiconductor static data memorizing apparatus including, a first power supply terminal, a second power supply terminal, a first TFT (thin film transistor), the first TFT having a first conductivity type, one terminal connected to the first power supply terminal, and the other terminal connected to a first data storage node for memorizing the second data, a second TFT, the TFT having the first conductivity type, one terminal connected to the first power supply terminal, and the other terminal connected to a second data storage node for memorizing the data, a third TFT, the third TFT having a second conductivity type, one terminal connected to the second power supply terminal, and the other terminal connected to the first data storage node, and a fourth TFT, the fourth TFT having the second conductivity type, one terminal connected to the second power supply terminal, and the other terminal connected to the second data storage node, wherein a gate of the first TFT is connected to the second memory node, and a gate of the second TFT is connected to the first data storage node, such that a flip-flip circuit is formed by the first power supply terminal, the second power supply terminal, the first TFT, the second TFT, the third TFT, and the fourth TFT, and further including data bit lines which are inverted with respect to each other, a first switching device for performing a switching operation between one of the bit lines and the first data storage node, a second switching device for performing a switching operation between the other of the data bit lines and the second data memory, and a word line device, connected to gates of the first and second switching devices, for controlling operations of the first and second switching devices.

1. Field of the Invention
The present invention relates to a static memory cell and, more particularly, to a static random access memory (referred to as an SRAM hereinafter) requiring no data refresh.
2. Description of the Related Art
In general, unlike a dynamic random access memory (DRAM) in which data is updated (refreshed) every predetermined period, a static memory requiring no data refresh can be easily used. In addition, when the static memory is combined with a CMOS technique, a random access memory backed up by a battery having a low standby power can be obtained. However, in this case, since a flip-flop must be formed in a memory cell, the cell area of the static random access memory is larger than that of the DRAM.
In an SRAM to which the present invention is not applied, since a CMOS structure must be independently formed in a memory cell, the cell area is six times or more than that of the DRAM.
According to another method, four transistors must be integrated in a cell, and an NMOSFET has a driving ability of several mA. Therefore, since the resistance of the ground power supply line of the cell must be decreased, a low-resistance wiring material such as polycide must be used, and difficult processing must be performed.

Static semiconductor memory using thin film FET


Particle traps are often used to reduce particulate emissions from internal combustion engines to acceptable levels. In order to maintain the particulate traps, they must be periodically regenerated in order to burn off the trapped particles. Strategies for efficiently regenerating the particle traps have been elusive. The present invention separates the exhaust flow into several flow paths. During regeneration, the flow paths are sequentially partially closed, and the particle traps in each of the flow paths are individually regenerated using electrically conductive filter elements. The present invention can be used to effectively filter particles from any combustion process, especially exhaust from internal combustion engines. The particle trap assembly achieves a relatively low pressure loss and efficient regeneration by supplying an oxidizer via a small cross-flow passage.

In order to meet the very stringent requirements on exhaust particulate emissions being imposed by governmental regulators, modifications to the engine and/or exhaust treatment strategies are necessary. Although particle traps are known in the art, many employ cordierite as the filter medium, and use some separate regenerator, such as injected fuel or an electrically resistive heater, to regenerate the filter. Although several filter mediums are known in the art that can effectively capture particulate matter in a wide range of particle sizes suitable for treatment of an engine's exhaust, efficiently regenerating the particle traps has been much more problematic. For instance, regenerating particle traps by burning fuel in the exhaust section to create the heat necessary to cause regeneration (i.e. burn the particulate matter) can result in an excess usage of fuel, cause uneven regeneration of the filter medium and potentially create even further undesirable emissions. Likewise, particulate trap strategies that employ an electrically resistive heater embedded in, or positioned adjacent, a filter medium can also experience uneven regenerative heating and can consume relatively large amounts of electrical power to perform the regenerative function.
Existing systems often suffer from additional energy consumption due to the fact that regenerative heaters must heat the filter medium well above typical exhaust temperatures. When regeneration is performed with the engine running, the exhaust flow blowing over the filter medium tends to cool the same. Thus, even larger amounts of heat energy must be supplied to overcome this continuous cooling of the filter medium that occurs due to exhaust gas flow. In addition, many prior assemblies attempt to regenerate almost the entire particulate filter assembly in a single operation, which can also place large energy demands on an engine's electrical system.
The present invention is directed to one or more of the problems set forth above.

Efficiently regenerated particle trap for an internal combustion engine and method of operating same


A television information system for distributing television information services, including interactive service, to subscribers divided among a plurality of service areas. A system manager receives requests for service from subscribers and assigns each requesting subscriber to one of a plurality of video provider elements. The video provider element provides a television information service to the requesting subscriber. An rf processing unit associated with the video provider element places the television information service on a carrier frequency assigned to the subscriber by the system manager. An rf switch controlled by the system manager directs each carrier frequency to the service area of the corresponding requesting subscriber.

Television has long been viewed as a one-way information service. Television programming is provided over a number of channels and broadcasts over a wide viewing area. The television signals may be provided through over-air transmission, coaxial cable, a combination of fiber and coaxial cables (known as hybrid fiber/coax), or via satellite. More recently, interest has developed in the ability to provide interactive or two-way communications through television. One method for providing interactive television services is to provide a home with a computer processor with graphical output capability (also known as multimedia processing). Such a processor may be made to modify a television screen to reflect a user's inputs to the system. Thus, an interactive television application can be run on the computer processor with the output of the application viewed on the television while computer server systems at the headend provides the underlying data. Such a system requires that an expensive computer system be placed at each home with further expensive high speed data communications modem technology to link the computer system to the data server computers back at the headend or central office.
Another option for providing interactive television service to homes is to provide the interactive processing ability at the headend of the broadband system with just its output sent to the home for viewing and user inputs from the home are sent to the headend to provide input to the headend system to control its output back to the home. An immediate advantage to locating the processing systems at the headend is that the operator only needs one processor for each active, or simultaneous, user. This contrasts the first method of placing a processor in each subscribers home whether it is used or not. With the processing placed in a central location such as a broadband system headend, an interactive television system could be built much like a telephone switching system. When a user wishes an interactive video service, a call is set-up where a user is assigned a processor card within the central switch and is also assigned a radio frequency (TV) channel between the central switch and that subscriber's home over which to view the interaction. Commands from the user's remote control in the home are relayed back to the headend and directed to the processor card serving that user. The output of the card is viewed by the user over his or her private channel on the user's television set. The systems resources, including the private channel, remain assigned to the individual user for the duration of use and, when the user tunes back to broadcast channels, these resources returned to an allocation pool available for another user.
In one paper, it has been suggested that interactive services be delivered to individual busses on a demand basis only. Large, D., "Tapped Fiber vs. Fiber-Reinforced Coaxial CATV Systems", IEEE LCS Magazine, February, 1990, pp. 12 et seq. A three level distributed switching system was proposed, with one switch at the headend to switch among hubs, one at each hub to switch among distribution lines, and a third level interdiction circuit to select the service for each dwelling. No architecture for such a scheme was proposed.
Van der Star, Jack A. M., "Video on Demand Without Compression: A Review of the Business Model, Regulation and Future Implication", discusses employing frequency re-use to distribute video-on-demand. The conventional cable trunk is split to produce separate feeds for each neighborhood. A video-on-demand block of frequencies is combined with the conventional frequencies. The video-on-demand frequencies are reused in each neighborhood. Each neighborhood trunk appears to be associated with a plurality of agile modulators equal to the number of video-on-demand channels. The article recommends that the number of video-on-demand channels equal 10% of the number of subscribers on the neighborhood trunk. The article further calls for an addressable decoder for each subscriber.

Output switching for load levelling across multiple service areas


A computer device and a method for reading or writing data by a computer device are provided. In the computer device, a central processing unit (CPU) is connected to a cloud controller using a double data rate (DDR) interface. Because the DDR interface has a high data transmission rate, interruption of CPU can be avoided. In addition, the CPU converts a read or write operation request into a control command and writes the control command into a transmission queue in the cloud controller. Because the cloud controller performs a read operation or a write operation on a network device according to operation information in the control command, after writing the control command into the transmission queue, the CPU does not need to wait for an operation performed by the cloud controller and can continue to perform other processes.

With development of data centers and approaching of the era of big data, data center architecture has developed from a tightly coupled silo-like server architecture into a virtualization-technology-centered architecture. To adapt to the coming era of big data, existing data centers are faced with a series of challenges in future big data processing. The challenges include P bits/second real-time data processing, dynamic resource allocation and adjustment on demand, energy efficiency improvement of a large-scale system, etc. In response, high-throughput computer data centers with features such as resource pooling, hardware decoupling, and silicon photonic interconnection come into being.
In an architecture of a high-throughput computer data center, pooling of memory resources, input/output resources, or the like are implemented. A high-throughput computing node is connected to a memory resource pool or an input/output resource pool using a network, so as to dynamically allocate and adjust resources and improve system energy efficiency. Due to the resource pooling, hardware decoupling makes an interconnect technology, for example, silicon photonic interconnection, a most crucial technology. A current data center level interconnect technology relies mainly on Ethernet interconnect technology. However, due to a complex and bloated protocol stack and an extremely high interconnect delay of the Ethernet itself, the interconnect technology becomes less capable of meeting requirements of a data center on quick and high-capacity data exchange. On the other hand, simplified Pooled Resource Access Protocol (PRAP) that can provide high bandwidth and low delay can meet the low delay requirement of high-throughput computer data centers.
In a current method for decoupling a built high-throughput computer, a cloud controller is used as a key module for the interconnection. The PRAP interconnect protocol is used to connect a computing pool, a remote memory resource pool, an input/output (I/O) resource pool, and the like, and a double data rate (DDR) interface is used to connect to a central processing unit (CPU). However, when data in the remote memory resource pool or input/output resource pool needs to be read, due to a network delay, the cloud controller cannot return requested data at the DDR interface within a specified time. Therefore, when a CPU of a high-throughput computer accesses the remote memory resource pool or input/output resource pool using a network, an interrupt of the CPU is caused, leading to a high access delay and a problem that overall performance of a system is affected because the CPU cannot perform another operation during the interrupt.

Computer device and method for reading or writing data by computer device


A method for producing an electro-optical device comprising a first photolithographic step of forming a transparent pixel electrode, a second photolithographic of forming a gate electrode and a gate wiring, a third photolithographic step of forming a contact holes in an insulator film leading to the pixel electrode and the gate wiring, a fourth photolithographic step of forming a source electrode and a drain electrode and a channel portion above the gate electrode, and a fifth photolithographic step of forming a contact hole in a passivation film and isolating the semi-conductor active film below the source electrode, the drain electrode and the source wiring from other adjacent portions.. The number of photolithographic steps can be reduced, to improve the yield and decrease the production cost adjacent thin film transistors.

1. Field of the Invention
The present invention concerns a method of producing an electro-optical device in which thin film transistors are formed and, more in particular, it relates to a technique capable of reducing the number of photolithographic steps as compared with that in the prior art method.
2. Description of the Related Art Statement
FIG. 165 shows an example for a constitution of an equivalent circuit of an active matrix liquid crystal display device using thin film transistors as switching elements.
In FIG. 169, a plurality of gate wirings G1, G2, - - - , Gn and a plurality of source wirings S1, S2, - - - , Sm are wired in a matrix, in which each of the gate wirings G is connected to a scanning circuit 1 and each of the signal wirings S is connected to a signal supply circuit 2 respectively. A thin film transistor (switching element) 3 is disposed to a crossing point between each of the wirings and a capacitance section 4 as a capacitor and a liquid crystal device 5 are connected to a drain electrode of the thin film resistor 3 to constitute a circuit.
FIG. 170 and FIG. 171 illustrate an example for a structure of a thin film transistor array substrate having portions, for example, the gate wirings G and the source wirings F on a substrate in an existent active matrix liquid crystal display device shown by the equivalent circuit in FIG. 169.
In the thin film transistor array substrate shown in FIG. 170 and FIG. 171, the gate wirings G and the source wirings S are wired in a matrix on a transparent substrate 6 such as made of glass. Further, a thin film resistor 3 is disposed near the crossing point between each of the gate wirings G and the source wirings S.
The thin film transistor 3 shown in FIG. 170 and FIG. 171 has a general etch-stopper type constitution formed by disposing an gate insulator film 9 on the gate wiring G and a gate electrode 8 led out of the gate wiring G, disposing a semiconductor film 10 made of amorphous silicon (a-Si) on the gate insulator film 9 and further disposing, on the semiconductor film 10, a drain electrode 11 and a source electrode 12 made of an electroconductive material opposing to each other. An ohmic contact film 10a comprising, for example, amorphous silicon and doped at a high concentration with an impurity as such as phosphorus as a doner is formed to the uppermost layer of the semiconductor film, on which an etching stopper 13 is formed being put between the drain electrode 11 and the source electrode 12. Further, the gate electrode 8 has a double structure comprising a gate insulator film 8a of an upper layer and a gate wiring 8b of a lower layer, and a transparent pixel electrode 15 made of a transparent electrode material is formed from a portion above the drain electrode 11 to lateral sides of the drain electrode 11.
Then a passivation film 16 is disposed covering, for example, the gate insulator film 9, the transparent pixel electrode 15 and the source electrode 12.
A not illustrated orientation film is formed on the passivation film 16, and liquid crystals are disposed above the orientation film to constitute an active matrix liquid crystal display device 15 and the device can control the orientation of liquid crystal molecules when an electric field is applied to the molecules of the liquid crystals by way of the transparent pixel electrode 15.
By the way, the thin film transistor array substrate of the structure described above has been produced so far based on the steps as described in Table 1 shown below.
TABLE 1 __________________________________________________________________________ Step Production method Material Remarks __________________________________________________________________________ Initial cleaning Brush and UV Formation of surface stabilization layer Reactive sputtering TaOx 750 nm Formation of gate wiring metal DC sputtering Al 200 nm Gate wiring metal PL 1 Wet etching Formation of gate electrode DC sputtering Ta 400 nm Gate electrode PL 2 Dry etching Anodization of gate electrode TaOx 300 nm Formation of gate insulation Plasma CVD SiNx 250 nm Formation of a-Si Plasma CVD a-Si 50 nm Formation of ES insulator layer Plasma CVD SiNx 100 nm ES insulator layer PL 3 Wet etching Back exposure method Formation of SD semiconductor Plasma CVD n + Si 25 nm Device area PL 4 Dry etching Formation of SD electrode DC sputtering Ti 400 nm SD electrode PL 5 Dry etching Formation of transparent electrode Reactive sputtering ITO 50 nm Transparent electrode PL 6 Wet etching Formation of protection layer Plasma CVD SiNx 250 nm Protection layer PL 7 Wet etching __________________________________________________________________________ Note: PL: photolithography, ES: etching stopper, SD: source/drain 1-7: Exposure process
At first, a transparent substrate, for example, made of glass is prepared, and then put to initial cleaning by a brush cleaning device and an UV-irradiation device, and a surface stabilization film, for example, made of TiO.sub.x is formed by using a film-forming method such as reactive sputtering on the transparent substrate after cleaning.
A metal film for gate wirings made of an electroconductive material such as Al is deposited on the substrate formed with a surface stabilization film by using a film forming-method such as DC sputtering, and the metal film is etched in a first photolithographic step (1) using a method such as wet etching, to form gate wirings.
Then, a metal film for forming a gate electrode made, for example, of Ta is deposited on the gate wirings by a film forming method such as DC sputtering and then the metal film is etched in a second photolithographic step (2) using a method such as dry etching, to form the gate electrode.
Then, the gate electrode is anodized to form the surface portion into TaO.sub.x to apply a treatment for improving the insulation performance of the gate electrode.
Successively, a gate insulator film made of SiN.sub.x, a semiconductor film made of a-Si (amorphous silicon) or the like and an insulator film for etching stopper made of SiN.sub.x are formed on them by a film-forming method such as plasma CVD.
Then, etching is applied in a third photolithographic step (3) using a method, for example, of wet etching to form an etching stopper on the gate electrode.
Then, an ohmic contact film such as made of a-Si(n.sup.+) is formed on the surface of the substrate after the third photolithographic step by using a method such as plasma CVD.
Then, the semiconductor film and the ohmic contact film are patterned in a fourth photolithographic step (4) using a method such as DC sputtering to form a semiconductor portion above the gate electrode in a state isolated from other portions.
Then, a metal film made, for example, of Ti is formed on the surface of the substrate after the fourth photolithographic step by using a film-forming method such as DC sputtering.
Then, the metal film is patterned in a fifth photolithographic step (5) using a method such as dry etching to form a source electrode and a drain electrode.
Then, a transparent conductive film, for example, made of ITO (Indium Tin Oxide) is formed on the surface of the substrate after the fifth photolithographic step by a film-forming method such as reactive sputtering.
Then, the transparent conductive film is fabricated in a sixth photolithographic step (6) using a method such as wet etching to form a transparent pixel electrode, and then
a protection film, for example, made of SiN.sub.x is formed on the surface of the substrate after the sixth photolithographic step by a method such as plasma CVD. PA1 a step A1 for forming a transparent conductive film on the surface of the substrate, PA1 a first photolithographic step A2 of patterning the transparent conductive film to form a transparent pixel electrode, PA1 a step A3 of forming a first metal film on the surface of the substrate after the first photolithographic step, PA1 a third photolithographic A4 of patterning the first metal film to form a gate electrode and a gate wiring, PA1 a step A5 of forming a first insulator film, a semiconductor active film and an ohmic contact film on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step A6 of patterning the first insulator film, the semiconductor active film and the ohmic contact film to form a contact hole reaching the transparent pixel electrode and a contact hole reaching the gate wiring, PA1 a step A7 of forming a second metal film on the surface of the substrate after the third photolithographic step, PA1 a fourth photolithographic step A8 of patterning the second metal film, to form a source electrode, a source wiring, a drain electrode connected with the transparent pixel electrode by way of the contact hole reaching the transparent pixel electrode and a gate terminal wiring connected with the gate wiring by way of the contact hole reaching the gate electrode, and fabricating the ohmic contact film by using the second metal film as a mask to form a channel portion above the gate electrode, PA1 a step A9 of forming a passivation film on the surface of the substrate after forming the channel portion, and PA1 a fifth photolithographic step A10 of forming, to the passivation film, a contact hole reaching the gate terminal wiring and the source wiring, and fabricating the semiconductor active film below the source electrode, the drain electrode and the source wiring using the passivation film as a mask to isolate the same from the semiconductor active film of adjacent thin film transistors having the gate wiring in common and make a portion above the pixel electrode light permeable. PA1 the step A3 of forming the first metal film on the surface of the substrate and PA1 the second photolithographic step A4 of patterning the first metal film to form the gate electrode and the gate wiring are conducted and, subsequently, PA1 the step Al of forming the transparent conductive film on the surface of the substrate and PA1 the first photolithographic step A2 of patterning the transparent conductive film to form the transparent pixel electrode are applied. PA1 a step B1 of forming a first metal film on the surface of the substrate, PA1 a first photolithographic step B2 of patterning the first metal film to form a gate electrode and a gate wiring, a step B3 of forming a first insulator film, a semiconductor active film and an ohmic contact film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step B4 of patterning the semiconductor active film and the ohmic contact film to form a semiconductor portion above the gate electrode in a state isolated from other portions, PA1 a third photolithographic step B5 of patterning the first insulator film to form a contact hole reaching the gate wiring, PA1 a step B6 of forming a transparent conductive film for a transparent pixel electrode, a second metal film for a source electrode and a drain electrode on the surface of the substrate after the third photolithographic step, PA1 a fourth photolithographic step B7 of patterning the second metal film, the transparent conductive film and the semiconductor active film and the ohmic contact film to form a source electrode, a source wiring and a drain electrode and, further, forming a channel portion above the gate electrode and forming a transparent pixel electrode, PA1 a step B8 of forming the passivation film on the surface of the substrate after the fourth photolithographic step, and PA1 a fifth photolithographic step B9 of patterning the passivation film and the second metal film to make a portion above the transparent pixel electrode light permeable and forming a contact hole for source wiring and gate wiring connection terminals. PA1 a step C1 of forming a first metal film on the surface of the substrate, PA1 a first photolithographic step C2 of patterning the first metal film to form a gate electrode and a gate wiring, PA1 a step C3 of forming a first insulator film, a semiconductor active film, an ohmic contact film and a metal film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step C4 of patterning the semiconductor active film, the ohmic contact and the metal film to form a semiconductor portion above the gate electrode in a state isolated from other portions, PA1 a third photolithographic step C5 of patterning the first insulator film to form a contact hole reaching the gate wiring, PA1 a step C6 of forming a transparent conductive film for a transparent pixel electrode, a source electrode and a drain electrode on the surface of the substrate after the third photolithographic step, PA1 a fourth photolithographic step C7 of patterning the transparent conductive film to form a source electrode, a source wiring, a drain electrode and a transparent pixel electrode, and patterning the transparent conductive film, the buffer film and the ohmic contact film above the gate electrode to form a channel portion above the gate electrode, PA1 a step C8 of forming a passivation film on the surface of the substrate after the fourth photolithographic step, and PA1 a fifth photolithographic step C9 of patterning the passivation film to remove a portion of the passivation film above the transparent pixel electrode and make a portion above the transparent pixel electrode light permeable and forming a contact hole for source wiring and gate wiring connection terminals. PA1 a step D1 of forming a transparent conductive film for a transparent pixel electrode and a first film for a gate electrode and a gate wiring on the transparent conductive film on the surface of the substrate, PA1 a first photolithographic step D2 of patterning the transparent conductive film and the first metal film to form a gate electrode, a gate wiring and a transparent pixel electrode, PA1 a step D3 of forming a first insulator film, a semiconductor active film and an ohmic contact film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step D4 of patterning the ohmic contact film, the semiconductor active film and the first insulator film to form a contact hole reaching the gate wiring, PA1 a step D5 of forming a second metal film for the source electrode and the drain electrode on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step D6 of patterning the second metal film to form the source electrode and the drain electrode and patterning the second metal film and the ohmic contact film on the gate electrode to form a channel portion above the gate electrode, PA1 a step D7 of forming a passivation film on the surface of the substrate after the third photolithographic step, and PA1 a fourth photolithographic step D8 of patterning the passivation film to remove a portion of the passivation film, the second metal film, the ohmic contact film, the semiconductor active film and the first insulator film above the transparent pixel electrode and make a portion above the transparent pixel electrode light permeable, isolating the semiconductor active film below the source electrode, the drain electrode and the source wiring from the semiconductor active film of adjacent thin film transistor having the gate wiring in common and forming a contact hole for source wiring and gate wiring connection terminals. PA1 a step E1 of forming a transparent conductive film for a transparent pixel electrode and a first film for a gate electrode and a gate wiring on the transparent conductive film on the surface of the substrate, PA1 a first photolithographic step E2 of patterning the transparent conductive film and the first metal film to form a gate electrode, a gate wiring and a transparent pixel electrode, PA1 a step E3 of forming a first insulator film, a semiconductor active film and an ohmic contact film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step E4 of patterning the semiconductor active film and the ohmic contact film to form a semiconductor portion above the gate electrode in a state isolated from other portions, PA1 a third photolithographic step E5 of patterning the first insulator film to form a contact hole reaching the gate wiring, PA1 a step E6 forming a second metal film for a source electrode and a drain electrode on the surface of the substrate after the third lithographic step, PA1 a fourth photolithographic step E7 of patterning the second metal film to form a source electrode and a drain electrode, and patterning the second metal film and the ohmic contact film above the gate electrode to form a channel portion above the gate electrode, PA1 a step E8 of forming a passivation film on the surface of the substrate after the fourth photolithographic step, and PA1 a fifth photolithographic step E9 of patterning the passivation film to remove a portion of the passivation film, the second metal film and the first insulator film above the transparent pixel electrode and make a portion above the transparent pixel electrode light permeable, and forming a contact hole for source wiring and gate wiring connection terminal. PA1 a step F1 of forming a first metal film on the surface of the substrate, PA1 a first photolithographic step F2 of patterning the first metal film to form a gate electrode and a gate wiring, PA1 a step F3 of forming a first insulator film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step F4 of patterning the first insulator film to form a contact hole reaching the gate wiring, PA1 a step F5 of forming a transparent conductive film, a second metal film and an ohmic contact film in this order on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step F6 of patterning the ohmic contact film, the second metal film and the transparent conductive film to form a source electrode, a drain electrode, a channel portion and a transparent pixel electrode, PA1 a step F7 of forming a semiconductor active film and a passivation film on the surface of the substrate after the third photolithographic step, and PA1 a fourth photolithographic step F8 of patterning the passivation film, the semiconductor active film, the ohmic contact film and the second metal film to make a portion above the transparent pixel electrode light permeable and isolate the semiconductor film above the source electrode, the drain electrode and the source wiring from the semiconductor active film of adjacent thin film transistors having the gate wiring in common and forming a contact hole for source wiring and gate wiring connection terminals. PA1 a step G1 of forming a first metal film on the surface of the substrate, PA1 a first photolithographic step G2 of patterning the first metal film to form a gate electrode and a gate wiring, PA1 a step G3 of forming a first insulator film, a semiconductor film and an ohmic contact film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step G4 of patterning the semiconductor active film and the ohmic contact film to form a semiconductor portion above the gate electrode in a state isolated from other portions, PA1 a step G5 of forming a second metal film on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step G6 of patterning the second metal film and the ohmic contact film to form a source electrode, a drain electrode and a channel portion, PA1 a step G7 of forming a passivation film on the surface of the substrate after the third photolithographic step, and PA1 a fourth photolithographic step G8 of patterning the passivation film to form a contact hole reaching the gate wiring, a contact hole reaching the drain electrode and a contact hole for source wiring and gate wiring connection terminals, PA1 a step G9 forming a transparent conductive film on the surface of the substrate after the fourth photolithographic step, and PA1 a fifth photolithographic step G10 of patterning the transparent conductive film to form a transparent pixel electrode. PA1 a step H1 of forming a first metal film on the surface of the substrate, PA1 a first photolithographic step H2 of patterning the first metal film to form a gate electrode and a gate wiring, PA1 a step H3 of forming a first insulator film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step H4 of patterning the first insulator film to form a contact hole reaching the gate wiring, PA1 a step H5 of forming a second metal film and an ohmic contact film on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step H6 of patterning the ohmic contact film and the second metal film to form a source electrode, a drain electrode, a source wiring and a channel portion, PA1 a step H7 of forming a semiconductor active film and a passivation film on the surface of the substrate after the third photolithographic step, PA1 a fourth photolithographic step H8 of patterning the passivation film, the semiconductor active film and the ohmic contact film to make a transparent pixel electrode area light permeable, isolating the semiconductor active film above the source electrode, the drain electrode and the source wiring from the semiconductor active film of adjacent thin film transistors having the gate wiring in common and forming a contact hole reaching the source wiring, PA1 a step H9 forming a transparent conductive film on the surface of the substrate after the fourth photolithographic step and PA1 a step H10 of patterning the transparent conductive film to form a transparent pixel electrode. PA1 a step J1 of forming a first metal film on the surface of the substrate, PA1 a first photolithographic step J2 of patterning the first metal film to form a gate electrode and a gate wiring, PA1 a step J3 of forming a first insulator film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step J4 of patterning the first insulator film to form a contact hole reaching the gate wiring, PA1 a step J5 of forming a transparent conductive film on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step J6 of patterning the transparent electrode to form a source electrode, a drain electrode, a source wiring and a channel portion, PA1 a step J7 of forming a second metal film and an ohmic contact film in this order on the surface of the substrate after the third photolithographic step, PA1 a fourth photolithographic step J8 of patterning the ohmic contact film, the second metal film and the ohmic contact film to form a source electrode, a drain electrode and a channel portion, PA1 a step J9 of forming a semiconductor film and a passivation film on the surface of the substrate after the fourth photolithographic step, and PA1 a fifth photolithographic step J10 of patterning the passivation film, the semiconductor active film, the ohmic contact film and the second metal film to make a portion above the transparent pixel electrode light permeable, isolating the semiconductor active film above the source electrode, the drain electrode and the source wiring from the semiconductor active film of adjacent thin film transistors having the gate wiring in common and forming a contact hole reaching the source wiring. PA1 a step L1 of forming a light screening thin film on the surface of the substrate, PA1 a first photolithographic step L2 of patterning the light screening thin film to form a light screening film, PA1 a step L3 of forming a first insulator film and a semiconductor active film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step L4 of patterning the semiconductor active film to form a semiconductor portion on the light screening film, PA1 a step L5 of forming a second insulator film and a first metal film on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step L6 of patterning the first metal film to form a gate electrode and a gate wiring, PA1 a step L7 of forming a third insulator film on the surface of the substrate after the third photolithographic step, PA1 a fourth photolithographic step L8 of patterning the second insulator film and the third insulator film to form a contact hole reaching one end of the semiconductor portion and a contact hole reaching the other end of the semiconductor portion, and patterning the third insulator film to form a contact hole reaching the gate wiring, PA1 a step L9 of forming a transparent conductive film on the surface of the substrate after the fourth photolithographic step, and PA1 a fifth photolithographic step L10 of patterning the transparent conductive film to form a source electrode, a source wiring and a drain electrode on both sides of the gate electrode and forming a pixel electrode. PA1 a step M1 of forming a light screening thin film on the surface of the substrate, PA1 a first photolithographic step M2 of patterning the light screening thin film to form a light screening film, PA1 a step M3 of forming a first insulator film, a semiconductor active film and an ohmic contact film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step M4 of patterning the ohmic contact film and the semiconductor active film to form a semiconductor portion above the light screening film, PA1 a step M5 of forming a first metal film on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step M6 of patterning the first metal film to form a source electrode, a drain electrode and a source wiring, PA1 a step M7 of forming a second insulator film on the surface of the substrate after the third photolithographic step, PA1 a fourth photolithographic step M8 of patterning the second insulator film to form a contact hole reaching gate wiring, a contact hole reaching the source wiring and a contact hole reaching the drain electrode, PA1 a step M9 of forming a transparent conductive film on the surface of the substrate after the fourth photolithographic step, and PA1 a fifth photolithographic step M10 of patterning the transparent conductive film to form a gate electrode above a portion between the source electrode and the drain electrode and forming a gate wiring in connection with the gate electrode. PA1 a step N1 of forming a light screening thin film on the surface of the substrate, PA1 a first photolithographic step N2 of patterning the light screening thin film to form a light screening film, PA1 a step N3 of forming a first insulator film, a semiconductor active film and an ohmic contact film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step N4 of patterning the ohmic contact film and the semiconductor film to form a semiconductor portion above the light screening film, PA1 a step N5 of forming a transparent conductive film on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step N6 of patterning the transparent conductive film to form a source electrode, a drain electrode, a source wiring and a pixel electrode, PA1 a step N7 of forming a second insulator film on the surface of the substrate after the third photolithographic step, PA1 a fourth photolithographic step N8 of patterning the second insulator film to form a contact hole for gate wiring and a source wiring connection, PA1 a step N9 of forming a metal film on the surface of the substrate after the fourth photolithographic step, and PA1 a fifth photolithographic step N10 of patterning the metal film to form a gate electrode above a portion between the source electrode and the drain electrode and forming a gate wiring in connection with the gate electrode. PA1 a step O1 of forming a light screening thin film on the surface of the substrate, PA1 a first photolithographic step O2 of patterning the light screening thin film to form a light screening film, PA1 a step O3 of forming a first insulator film, a first metal film and an ohmic contact film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step O4 of patterning the ohmic contact film and the first metal film to form a semiconductor channel portion, and forming a source electrode, a drain electrode and a source wiring above the light screening film, PA1 a step O5 of forming a semiconductor active film and a passivation film protecting the same on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step O6 of patterning the passivation film, the semiconductor active film and the ohmic contact film to form a semiconductor portion and forming contact hole for connecting the gate wiring and the source wiring, PA1 a step O7 of forming a transparent conductive film on the surface of the substrate after the third photolithographic step, and PA1 a fourth photolithographic step O8 of patterning the transparent conductive film to form a gate electrode above a portion between the source electrode and the drain electrode and form a pixel electrode. PA1 a first photolithographic step P2 of patterning the light screening thin film to form a light screening film, PA1 a step P3 of forming a first insulator film, a transparent conductive film and an ohmic contact film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step P4 of patterning the ohmic contact film and the transparent conductive film to form a n.sup.+ semiconductor channel portion, and forming a source electrode, a drain electrode, a source wiring and a pixel electrode above the light screening film, PA1 a step P5 of forming a semiconductor active film and a second insulator film on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step P6 of patterning the second insulator film, the semiconductor active film and the ohmic contact film to form a contact hole for connecting the gate wiring and the source wiring, PA1 a step P7 of forming a metal film on the surface of the substrate after the third photolithographic step, and PA1 a fourth photolithographic step P8 of patterning the metal film to form a gate electrode above a portion between the source electrode and the drain electrode and removing a film above the pixel electrode. PA1 a step Q1 of forming a light screening thin film on the surface of the substrate, PA1 a first photolithographic step Q2 of patterning the light screening thin film to form a light screening film, PA1 a step Q3 of forming a first insulator film and an ohmic contact film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step Q4 of patterning the transparent conductive film to form a pixel electrode, a step Q5 of forming a first metal film and an ohmic contact film on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step Q6 of patterning the ohmic contact film and the first metal film to form a semiconductor channel portion above the screening film and forming a source electrode, a drain electrode and a wiring therefor, PA1 a step Q7 of forming a semiconductor active film and a second insulator film on the surface of the substrate after the third photolithographic step, PA1 a fourth photolithographic step Q8 of patterning the second insulator film, the semiconductor conductive film and the ohmic contact film to form a semiconductor portion and removing the semiconductor active film and the second insulator film above the pixel electrode and, further, forming a contact hole for connecting the gate wiring and the source wiring, PA1 a step Q9 of forming a second metal film on the surface of the substrate after the fourth photolithographic step, and PA1 a step Q10 of patterning the second metal film to form a gate electrode and a wiring therefor above a portion between the source electrode and the drain electrode, and removing the second metal film above the pixel electrode and at the periphery of the semiconductor. PA1 a step R1 of forming a light screening thin film on the surface of the substrate, PA1 a first photolithographic step R2 of patterning the light screening thin film to form a light screening film, PA1 a step R3 of forming a first insulator film, a first metal film and an ohmic contact film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step R4 of patterning the ohmic contact film and the first metal film to form a semiconductor channel portion on the light screening film and, further, forming a source electrode, a drain electrode and a source wiring, PA1 a step R5 of forming a semiconductor active film on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step R6 of patterning the semiconductor active film to form a semiconductor portion above the light screening film, PA1 a step R7 of forming a second insulator film on the surface of the substrate after the third photolithographic step, PA1 a fourth photolithographic step R8 of patterning the second insulator film to form a contact hole for connecting the gate wiring and the source wiring and a contact hole for connecting the drain electrode and the pixel electrode on both sides of the semiconductor portion, PA1 a step R9 of forming a transparent conductive film on the surface of the substrate after the fourth photolithographic step, and PA1 a step R10 of patterning the transparent conductive film to form a gate electrode above the semiconductor portion, and forming a gate electrode wiring and forming a pixel electrode. PA1 a step S1 of forming a light screening thin film on the surface of the substrate, PA1 a first photolithographic step S2 of patterning the light screening thin film to form a light screening film, PA1 a step S3 of forming a first insulator film, a transparent conductive film and an ohmic contact film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step S4 of patterning the ohmic contact film and the transparent conductive film to form a semiconductor channel portion above the light screening film and, further, forming a source electrode, a drain electrode and a wiring therefor and a pixel electrode, PA1 a step S5 of forming a semiconductor active film and a second insulator film on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step S6 of patterning the second insulator film and the semiconductor active film to form a semiconductor portion, and forming a contact hole for connecting the gate wiring and the source wiring, PA1 a step S7 of forming a metal film on the surface of the substrate after the third photolithographic step, and PA1 a fourth photolithographic step S8 of patterning the metal film to form a gate electrode and a wiring therefor above the semiconductor portion and isolating the semiconductor portion with respect to each of the pixel electrodes.
Then, a seventh photolithographic step (7) of patterning the protection film by a method such as wet etching to form a contact hole for a source terminal for connection with the source electrode and a contact hole for a drain terminal for connection with the drain electrode, to complete the thin film transistor array substrate.
However, when the thin film transistor array substrate is produced by the method as described above, photolithographic steps have to be applied for seven times and, since there are a number of photolithographic steps, they give a significant effect by so much on the yield to bring about a problem of increasing the production cost.
Then, in a case of producing the thin film transistor array substrate of this type, it may be adopted a structure in which various thin films are stacked, a contact hole is formed to a portion of the laminate film, and a conductive film is formed to the contact hole to electrically connect the film of the upper layer with the film of the lower layer by way of the conductive film.
FIG. 172 shows an example of such a structure in which an insulator film 18 made, for example, of SiN.sub.x and a conductive oxide film 19 made of ITO are stacked on a metal film 17, for example, made of Ti formed on the substrate, and the conductive oxide film 19 is connected with the metal film 17 by way of a contact hole 18a formed to the insulator film 18.
In the structure of this example, the contact hole 18a is formed by a method of forming the insulator film 18, depositing thereover a predetermined pattern of a photoresist, etching the insulator film 18 by dry etching using, for example, SF.sub.6 +O.sub.2 gas to form the contact hole 18a, and then peeling off the photoresist with O.sub.2 plasma and subsequently forming the conductive oxide film 19. However, since the metal film 17 is exposed through the contact hole 18a to an oxidative atmosphere in the course of the process, there is a worry that the metal film 17 is oxidized.
In view of the above, Ti has been used so far as a metal capable of providing a good contact with the conductive oxide film 19 and is less oxidized by the O.sub.2 plasma atmosphere but a thin film of Al or Ta which is oxidized more readily than Ti can not be used, so that the material used for the metal film 17 suffers from restriction. By the way, in a case where a contact area of the connection portion is set to 7 um.sup.2 and a contact chain of a structure having 1,600 steps for the contact portion of the structure shown in FIG. 172 is formed, the contact resistance of the thin Al film to the thin ITO film is from 10.sup.10 -10.sup.12 ohm, whereas the contact resistance of the Ti thin film to the ITO thin film is from 10.sup.4 to 10.sup.5 ohm and the Ti thin film is apparently superior in the contact performance. It is considered that exposure to the O.sub.2 plasma atmosphere forms oxide layers at the boundary of the connection portion and, even if Ti has lower conductivity as compared with that of Al, it contrarily shows less contact resistance than the latter due to the presence of the oxide layers.
Further, in a case of using the thin Ti film as the metal film 17 described above, if the structure is applied to a thin film transistor array substrate to form gate wirings with the metal film 17, the Ti metal film 17 can be served for usual application use but it may possibly cause signal delay in the gate wirings since the specific resistivity of Ti itself is high, to result in a disadvantage in view of increase for the size of a liquid crystal panel.

Method of producing an electro-optical device


A stable positioning system for a suspended payload. A stabilizer, control unit and positioner are located above a suspended payload. The stabilizer includes a plurality of flywheels within a casing. The axis of rotation of each flywheel is aligned with one of three orthogonal axes. A central bevel gear translates the output of a high r.p.m. motor to the various flywheels. Four flywheels are arranged into two counterrotating pairs along one horizontal axis. Two flywheels counterrotate about the other axis and a single flywheel rotates about the vertical axis. The mass and arrangement of flywheels provides gyroscopic stability while neutralizing potential precessional moments.

1. Field of the Invention
The present invention relates to apparatus for positioning and controlling a suspended load. More particularly, this invention pertains to a gyroscopically-stabilized positioning system that is resistant to external forces.
2. Description of the Prior Art
Systems in a large number of endeavors employ hoist-and-payload arrangements. For example, I-beams and other structural elements are routinely moved into place while suspended from crane hoists. Cameras and grasping loads ("active" payloads) are lowered into mine shafts and otherwise-inaccessible locations for exploration and to aid in rescue and retrieval of persons and goods. Sea rescue efforts may employ cables suspended from helicopters for lowering rescuers and evacuating victims. Often, a stretcher is mounted at the bottom of the cable and the victim lifted while strapped down.
While hoisted loads enable exploration and rescue efforts from a remote platform, such efforts are often complicated and compromised by the flexible nature of the cable itself. Flexibility permits storage of substantial lengths of cable in limited spaces. However, operations may be compromised by the resultant lack of control over payload position and attitude. Elongated, flexible cables are readily subject to torquing that can result in spinning. Such torsion can be loaded into the cable through buffeting about by such external forces as wind, unintended contact with objects, etc. The very act of boarding a victim onto a stretcher will often produce this. The absence of control over the payload can be dangerous to the victim in the case of rescue efforts and can substantially compromise exploration by means of active suspended payloads.

Stable positioning system for suspended loads


A circular polarized antenna has a group of conductor lines that comprise a planar metal conductor, and a feeding point connected to a part of the conductor lines. When a current to be induced on the conductor lines is projected onto two mutually-perpendicular axes to define projections and arguments therebetween, a ratio between absolute values of the projections is 0.7 to 1.3 and an absolute value of a difference between the arguments is 80 to 100 degrees, and a reactance component of an impedance of the feeing point is nearly zero.

1. Field of the Invention
This invention relates to a circular polarized antenna, a design simulator for the antenna and a wireless module with the antenna.
2. Description of the Related Art
Circular polarized antennas are used in the field of BS (broadcasting satellite) and GPS (global positioning system) to allow good reception regardless of inclination of polarization plane. As a representative circular polarized antenna, a one-point feeding microstrip antenna is well known (e.g., Haneishi Misao et al., "Small and Planar Antennas", The Institute of Electronics, Information and Communication Engineers, pp. 142-164, 1996, Corona Corporation). A circular polarized antenna can be designed by providing the microstrip antenna with a degenerate separation element to generate two modes orthogonal spatially. However, the antenna has a limitation in size that its radiating element has one side with a length of about half its working wavelength and, therefore, it is hard to downsize.
Since it is desired that wireless modules have a small and low-profiled antenna, various methods for downsizing, low-profiling and designing thereof are researched.
Some methods for downsizing, low-profiling and designing the one-point feeding circular polarized antenna are disclosed in, e.g., JP patent No. 2826224, JP-A-H08-51312, and JP-A-2001-251132.
JP patent No. 2826224 discloses a method that a notch is formed at both ends of a conductor in the direction of lines orthogonal at ±45 degrees to two resonance mode directions orthogonal to each other and with different phases by a degenerate separation element, either of the lines orthogonal at to at ±45 degrees to the resonance mode directions is made to agree to a deviation direction of the feeding point, whereby its resonance frequency is reduced to allow the downsizing of the antenna at a certain frequency.
JP-A-H08-51312 discloses a method that the antenna is downsized by using a liner antenna element having a loop base element.
JP-A-2001-251132 discloses a method that its radiating element is formed a single-wire rectangular spiral and its outermost perimeter length is more than its working wavelength and twice or less of the working wavelength so as to downsize the antenna.
However, in the method of JP patent No. 2826224, although the downsizing can be attained while keeping the two orthogonal modes needed to generate a circular polarized wave, it is hard to have good matching to the high-frequency circuit. Although a method of adjusting the reactance of input impedance is disclosed therein, the adjustment of resistance needs many trials and errors and, therefore, the design time must be prolonged.
In the method of JP-A-H08-51312, although good circular polarized wave can be generated by adjusting the aspect ratio of the rectangular loop element and the distance between the element and the grounding conductor, it is hard to have good matching to the high-frequency circuit. Although a method of adjusting the input impedance by loading a reactance in the radiating element and a method of adjusting the input impedance by parallel connecting the plural radiating elements are disclosed therein, its systematic design is hard to conduct and, therefore, the design time must be prolonged.
In the method of JP-A-2001-251132, although the downsizing is easy attained by making the radiating element spiral, it is needed that the structure is frequently adjusted in consideration of two conditions of the generation of circular polarized wave and the matching to the high-frequency circuit. Therefore, the design time must be prolonged.

Circular polarized antenna, antenna design simulator, and wireless module with the antenna