A driving device for a liquid crystal panel having a signal generating circuit; a reference signal generating circuit; a phase comparator that compares phases of an inputted monitor signal and the reference signal and outputs phase comparison information; and an adder. The adder outputting an integrated count value for adjusting timing for generating the start signal on the basis of an initial count value set in advance and the phase comparison information from the phase comparator. The signal generating circuit generates plural timing signals including the start signal with the horizontal synchronizing signal as a trigger and with timing based on the integrated count value as a start point and supplies the timing signals to the liquid crystal panel.

1. Technical Field
The present invention related to a driving device for a liquid crystal panel of an active matrix driving system according to thin film transistor (hereinafter referred to as TFT) driving or the like and an image display apparatus including the driving device.
2. Related Art
For example, an electronic apparatus disclosed in JP-A-11-282426 is known as the image display apparatus using the liquid crystal panel of the active matrix driving system according to TFT driving. FIG. 7 is a schematic diagram of a liquid crystal panel 202 provided in the electronic apparatus disclosed in JP-A-11-282426 and a driving device 203 for the liquid crystal panel.
In the liquid crystal panel 201, a large number of scan lines Y1 to Ym and data lines X1 and Xn, which are arranged vertically and horizontally, respectively, and a large number of pixel electrodes 240 corresponding to respective intersections of the scan lines and the data lines are provided on a glass substrate. In addition to the scan lines, the data lines, and the pixel electrodes 240, peripheral circuits such as a scan line driver 230, a data line driver 220, sampling circuits SH1 to SHn, and pixel TFT circuits ST1 to STn are provided on the glass substrate. Moreover, liquid crystal cells corresponding to the respective pixel electrodes are filled between two opposed glass substrates to form the liquid crystal panel 201.
The driving device 203 is a signal generating circuit including a frequency dividing circuit or the like. An operation clock CLK and a horizontal synchronizing signal HSYNC and a vertical synchronizing signal VSYNC of an image signal are supplied to the driving device 203. The driving device 203 generates a start signal DX, a clock signal CLX, an inverted clock signal CLXN, an enable signal ENBX, and the like serving as timing signals on the basis of the operation clock CLK with the horizontal synchronizing signal HSYNC as a trigger.
The data line driver 220 including selection circuits L1 to Ln generates sampling signals S1 to Sn for determining driving timing for the sampling circuits SH1 to SHn on the basis of plural timing signals supplied from the driving device 203.
The sampling circuit SH1 to SHn including switching elements such as TFTs outputs image signals VID1 to VID6, which are expanded into six phases, to the pixel TFT circuits ST1 to STn only for a period in which the sampling signals S1 to Sn are at a high level.
Scan signals Y1 to Yn outputted from the scan line driver 230 are inputted to the pixel TFT circuits ST1 to STn. The pixel TFT circuits ST1 to STn outputs the image signals VID1 to VID6 to the pixel electrodes 240 only for a period in which the scan signals Y1 to Yn are at a high level. In this way, a video represented by the image signals VID1 to VID6 is displayed on the liquid crystal panel 201.
In the liquid crystal panel 201, when characteristics of a shift register included in the data line driver 220 and transistors constituting NAND circuits and the like of the selection circuits L1 to Ln are deteriorated, overlap occurs among the sampling signals S1 to Sn and a ghost image may be displayed.
In view of such a problem, the electronic apparatus disclosed in JP-A-11-282426 adjusts the period in which the sampling signals S1 to Sn are at a high level according to the enable signal ENBX to eliminate the overlap of the sampling signals S1 to Sn and prevent a ghost from being caused.
The ghost image may also be caused because of shift between a period in which the image signals VID1 to VID6 reach a saturated level and the period in which the sampling signals S1 to Sn are at a high level.
The image signals VID1 to VID6 are integrated by an internal circuit of the liquid crystal panel 201, whereby an edge of a waveform thereof is blunted. Therefore, if the period in which the image signals VID1 to VID6 reach a saturated level and the period in which the sampling signals S1 to Sn are at a high level do not coincide with each other, a ghost image is displayed.
The period in which the sampling signals S1 to Sn are at a high level may temporally shift from the period in which the image signals VID1 to VID6 reach a saturated level because characteristics of circuit elements and the like constituting data line driver 220 and the sampling circuits SH1 to SHn change as a result of a temperature change and aged deterioration at the time when the liquid crystal panel 201 is used.
In the electronic apparatus disclosed in JP-A-11-282426, it is possible to prevent a ghost image due to overlap of the sampling signals S1 to Sn from being caused. However, JP-A-11-282426 does not take into account a ghost image caused by shift between the period in which the image signals VID1 to VID6 reach a saturated level and the period in which the sampling signals S1 to Sn are at high level. The latter period changes as a result of a temperature change and aged deterioration at the time when the liquid crystal panel 201 is used.
A ghost image caused by temporal shift between a period in which images signals reach a saturated level and a period in which sampling signals are at a high level will be explained.
FIG. 6A is a diagram showing an appropriate image in which a ghost image is not caused and states of image signals representing the image and sampling signals.
A black substantially square window pattern 301 is displayed with a light gray background in an image 300 represented by an image signal VID. The image signal VID is expanded into six phases and supplied to the liquid crystal panel 201 as the image signals VID1 to VID6.
The image signals VID1 to VID6 are represented by a waveform having a voltage level (3V) indicating light gray and a voltage level (2V) indicating black. The image signals VID1 to VID6 are integrated by the internal circuit of the liquid crystal panel 201, whereby the edge of the waveform thereof is blunted. Thus, the image signals VID1 to VID6 need to be outputted to the pixel TFT circuits ST1 to STn in the period in which the image signals VID1 to VID6 reach a saturated level (e.g., a period as late as possible in image signal periods Ta and Tb).
A period Qa in which a sampling signal Sk is at a high level (a high-level period Qa of a sampling signal Sk) determines timing for inputting the image signals VID1 to VID6 to pixel TFT circuits corresponding to pixels P1 to P6 on a left side of the window pattern 301.
The high-level period Qa temporally coincides with a period in which the image signals VID1 to VID6 reach a saturated level (3V) of light gray in the image signal period Ta. The image signals VID1 to VID6 representing light gray are inputted to respective pixel electrodes of the pixels P1 to P6.
A period Qb in which a sampling signal Sk+1 is at a high level (a high-level period Qb of a sampling signal Sk+1) determines timing for inputting the image signals VID1 to VID6 to pixel TFT circuits corresponding to pixels P7 to P12 in the window pattern 301.
The high-level period Qb temporally coincides with a period in which the image signals VID1 to VID6 reach a saturated level (2V) of black in the image signal period Tb. The image signals VID1 to VID6 representing black are inputted to respective pixel electrodes of the pixels P7 to P12.
Thus, in a state shown in FIG. 6A, a ghost is not caused at the left end of the window pattern 201.
A line of the pixels P1 to P12 has been explained as an example. However, images are displayed at the same timing not only on the line but also on all lines on the liquid crystal panel 201. Thus, a ghost is not caused in the image 300 as a whole.
FIG. 6B is a diagram showing an image in which a ghost is caused because sampling signals are temporally ahead of image signals and states of the image signals representing the image and the sampling signals.
In FIG. 6B, the sampling signals Sk and Sk+1 temporally advance because of influences of a temperature change and aged deterioration of the liquid crystal panel 201. Thus, a part of the high-level period Qb shifts from the saturated level (2V) of black in the image signal period Tb in the image signals VID1 to VID6 and temporally overlaps a voltage level close to light gray.
Therefore, a part of the image signals VID1 to VID6 of the voltage level close to light gray are inputted to the respective pixel electrodes of the pixels P7 to P12 other than the image signals VID1 to VID6 that reach the saturated level (2V) of black. As a result, the image signals are mixed to cause a ghost of dark gray A on an inner side of the left side of the window pattern 301.
At this point, the same phenomenon occurs in continuous six pixels on an outer side of a right side of the window pattern 301. A part of the image signals VID1 to VID6 of the voltage level close to light gray are inputted to respective pixel electrodes on the right side other than the image signals VID1 to VID6 that reach the saturated level (2V) of black. As a result, the image signals are mixed to cause a ghost of dark gray B on the outer side of the right side of the window pattern 301 as well.
Moreover, the ghost is caused not only on the line of the pixels P6 to P12 but also on all the lines on the liquid crystal panel. Thus, a ghost of the dark gray A is caused on the inner side of the left side of the window pattern 301 and a ghost of dark gray B is caused on the outer side of the right side of the window pattern 301. Color strengths of the thick gray A and the thick gray B vary depending on a degree of temporal advance of the sampling signals Sk and Sk+1.
FIG. 6C is a diagram showing an image in which a ghost is caused because sampling signals are temporally delayed behind image signals and states of the image signals representing the image and the sampling signals.
In FIG. 6C, the sampling signals Sk and S+1 are temporally delayed behind the image signals VID1 to VID6 because of influences of a temperature change and aged deterioration of the liquid crystal panel 201. Thus, a part of the high-level period Qa shifts from the saturated level (3V) of light gray in the image signal period Ta in the image signals VID1 to VID6 and temporally overlaps a voltage level close to black.
Therefore, a part of the image signals VID1 to VID6 of the voltage level close to black are inputted to the respective pixel electrodes of the pixels P1 to P6 other than the image signals VID1 to VID6 that reach the saturated level (3V) of light gray. As a result, the image signals are mixed to cause a ghost of dark gray C on the outer side of the left side of the window pattern 301.
At this point, the same phenomenon occurs in continuous six pixels on an inner side of the right side of the window pattern 301. A part of the image signals VID1 to VID6 of the voltage level close to black are inputted to the respective pixel electrodes on the right side other than the image signals VID1 to VID6 that reach the saturated level (3V) of light gray. As a result, the image signals are mixed to cause a ghost of dark gray D on the inner side of the left side of the window pattern 301.
Moreover, the ghost is caused not only on the line of the pixels P6 to P12 but also on all the lines on the liquid crystal panel. Thus, a ghost of the dark gray C is caused on the inner side of the left side of the window pattern 301 and a ghost of dark gray D is caused on the outer side of the right side of the window pattern 301. Color strengths of the thick gray C and the thick gray D vary depending on a degree of temporal advance of the sampling signals Sk and Sk+1.
In the above explanation, the liquid crystal panel 201 is applied to monochrome display. However, the phenomenon described above occurs even if the liquid crystal panel 201 is applied to color display.
For example, when the liquid crystal panel 201 is a liquid crystal panel applied to color display that colors transmitted light using a color filter of R (red), G (green), or B (blue) for each of the pixels, one color is formed by three continuous pixels. Thus, the three continuous pixels are equivalent to one pixel of the liquid crystal panel applied to monochrome display.
As described above, the electronic apparatus in the past has a problem in that it is difficult to completely prevent a ghost due to temporal shift of timing signals caused by a temperature change and aged deterioration at the time when the liquid crystal panel is used.

Driving device for liquid crystal panel and image display apparatus


Embodiments of the invention provide a power supply apparatus, including an AC/DC rectifying unit converting an AC voltage into a DC voltage, a power factor correction unit correcting a power factor of the DC voltage, and a DC/DC conversion unit converting the DC voltage having the corrected power factor into a DC voltage having a different magnitude therefrom. According to various embodiments, the power supply apparatus further includes an auxiliary winding connected to a primary side winding of a transformer of the DC/DC conversion unit and generating the DC voltage having a predetermined magnitude, and an internal power generation unit connected to an output terminal of the power factor correction unit and the auxiliary winding and using a voltage of the output terminal of the power factor correction unit and a voltage generated by the auxiliary winding to generate temporary Vcc power and supply the generated temporary Vcc power as internal power of the power factor correction unit.

1. Field of the Invention
The present invention relates to a power supply apparatus, and more particularly, to a power supply apparatus capable of stably supplying internal power within a wide range from a minimum input voltage to a steady state of an output of a boost stage.
2. Description of the Related Art
In the case of a general AC-DC power supply apparatus, a latter stage of an AC-DC rectifying unit is mainly provided with a two-stage configuration of a power factor correction (PFC) unit and a DC-DC conversion unit. Recently, a type of implementing a single-stage in which functions of the PFC unit and the DC-DC conversion unit are integrated into one for high power density has been mainly used but has power factor and efficiency lower than those of a type of implementing a two-stage, and therefore is restrictively used in products. Further, in the two-stage configuration, as the PFC unit, a boost converter has been widely used and as the DC-DC conversion unit, a flyback converter, a full-bridge converter, and an inductor-inductor-capacitor (LLC) resonant converter have been widely used. The flyback converter has low efficiency but is advantageous in multi-output generation using a transformer, as compared with the LLC resonant converter. The full-bridge converter may not be used for products having low power density due to a larger number of devices and may have reduced efficiency at the time of a light load. For this reason, the LLC resonant converter, which may have high efficiency with a smaller number of devices, has been mainly used. However, the LLC resonant converter has a narrow input range with respect to a supply of internal power, and thus may not generate the internal power at a minimum input voltage like the flyback converter.
Meanwhile, in the two-stage power supply apparatus configured of the boost converter and the LLC resonant converter, the related art, which generates the internal power may largely include the following two methods.
The first method uses an additional standby stage at the outside. The method supplies the internal power from an output of the AC-DC rectifying unit (bridge diode) through the additional standby stage and therefore may achieve a stable operation. In this case, the standby stage generally uses the flyback converter. The method may be used in the case in which the use of the standby stage is essential and the case in which the required power density is low and may not be used due to a spatial disadvantage in the case in which the high power density is required.
The second method is a method of generating internal power from an output of the PFC unit through a regulator. The second method is a method of applying a voltage regulator to an output of a PFC unit to constantly supply internal power at all times within a wide range from a minimum input voltage to a boost steady output at least three times as large as an input voltage and may increase costs and the overall size of the apparatus since a loss of the output voltage of the PFC unit normally operated is large and the available regulator also needs to use a product having a large voltage threshold.

Power supply apparatus for supplying internal power from a minimum input voltage to a steady state of an output of a boost stage


A method for producing polysulfone micro-particles for 3D printing disclosed. For example, the method includes creating a mixture of polysulfone by dissolving polysulfone in an organic solvent, creating an aqueous solution of a polymeric stabilizer or a surfactant, adding the mixture of polysulfone to the aqueous solution to create a polysulfone solution, and processing the polysulfone solution to obtain polysulfone micro-particles having a desired particle size, a desired particle size distribution, and a desired shape.

Selective laser sintering (SLS) is a powder bed-based additive manufacturing (AM) technique to produce complex three-dimensional parts. When a laser beam scans the powder, the powder melts due to the rising temperature and layer-by-layer the final part approaches full density and should result in properties of the bulk material (i.e., polymer). In theory, every thermoplastic polymer that can be transformed into a powder form can be processed via this technique. However, the reality is every new material behaves differently during melting, coalescence, and consolidation, and requires optimization of the SLS processing parameters. The bed temperature and laser energy input are chosen based on the "processing" window of the polymer's thermal profile as well as its energy absorption. Laser parameters also need to be optimized based on the powder's particle size and shape.
The availability of powder materials for SLS is limited, where about 95% of the materials market consists of polyamide-12 which is a crystalline nylon grade polymer. High glass transition flexible amorphous materials such polysulfone (PSU) are not available as printable powders. Unlike semi-crystalline polymer powders, amorphous polymer powder must be heated above the glass transition temperature, at which the polymer is in a much more viscous state than semi-crystalline polymers at similar temperatures. Semi-crystalline polymers are highly ordered molecules with sharp melting points (Tm). Unlike amorphous polymers, they do not gradually soften as the temperature increases, but instead remain hard until a given amount of heat is absorbed and then rapidly transform into a viscous liquid. When a semi-crystalline material is above the Tm, it has very low viscosity and will flow and overlap with other sintered layers with rapid cooling. Amorphous polymers on the other hand will gradually soften as the temperature is increased but are not as easy flowing as semi-crystalline materials. The flow and sintering rate of amorphous powders would be less and blending between sintered layers would be more hindered and highly porous.

Method for producing sulfone polymer micro-particles for SLS 3D printing


A code conversion method and apparatus is provided for scrambling and modulating data. The method and apparatus includes scrambling an input main data unit based on any of plural types of pseudo-random number sequences, and modulating the scrambled main data unit based on any of plural types of modulation data. An output main data unit is produced from the modulated main data unit, and a calculated value representing a difference between a number of 0 bits and a number of 1 bits included in the output main data unit is obtained. Any of the modulation data is then selected dependent upon the calculated value. The method and apparatus further includes determining whether or not a variation of the calculated value has exceeded a predetermined threshold, newly selecting another pseudo-random number sequence used for the step of scrambling if it is determined that the variation of the calculated value has exceeded the predetermined threshold value, and re-scrambling the input main data unit based on the newly selected pseudo-random number sequence.

1. Field of the Invention
The present invention relates to a code conversion method and apparatus for scrambling and modulating data, a code recording medium on which the scrambled and modulated data may be recorded and code recording and reproducing apparatus for recording/reproducing the scrambled and modulated data onto/from a recording medium.
2. Description of the Related Art
Optical disks have become very popular as recording media for recording various types of software data such as video data, audio data and computer data thereon. The optical disks include various kinds of read-only type disks such as a laser disk (LD), a compact disk (CD), a compact disk read-only memory (CD-ROM) and various kinds of rewritable and/or write-once type disks such as a magneto-optic disk, a phase change disk and a recordable compact disk (CD-R).
On the other hand, in recent years, high-efficiency coding technologies also have been developed. Consequently, any type of data currently can be processed as digital data. For example, even video data can be band compressed so as to be processed as digital data. In view of these developments, increasingly it has become necessary to further increase the capacity and the recording density of an optical disk.
However, as the recording density of a recording medium is increased, the difference between the signals representing a value of "1" and the signals representing a value of "0" which have been read out from such a recording medium becomes smaller. As a result, a read margin is adversely decreased and the quality of a reproduced signal is more likely to be degraded.
In order to avoid such a degradation in quality of a reproduced signal, the low frequency components of a signal must be reduced when the signal is recorded onto a recording medium. This is because a signal reproduced from an optical disk contains a lot of low frequency noise, which must be removed by a filter in order to improve the signal to noise (S/N) ratio of a reproduced signal. Thus, since the filter also cuts the necessary low frequency components of the reproduced signal, the effects of the noise reduction may be alleviated by preliminarily reducing the low frequency components of the signal to be recorded.
Various data coding methods have been proposed for reducing the low frequency components thereof. However, even when any of these coding methods is applied, a data pattern having low frequency components which cannot be reduced may still appear for a long duration in some cases. Thus, it is effective to scramble data for reducing the possibility.
When data is recorded and/or reproduced onto/from a recording medium, recording and reproducing operations are performed on the basis of a data unit having a particular size. Such a data unit is called a "sector". The run length of the codes recorded on a sector is limited in order to narrow the frequency bandwidth of a channel for the recording/reproducing apparatus.
Once an error is generated when the data is recorded and/or reproduced onto/from the run-length limited sector, the error does not remain in the erroneous sector but is propagated into succeeding sectors of the data. In order to prevent such error propagation, predetermined patterns identifiable from the recorded data are recorded onto every sector at regular intervals. Such patterns are called "sync codes". The respective regions of a sector which are partitioned by these sync codes are called "frames".
As mentioned above, since the low frequency components of data must be reduced when the data is recorded, the data is converted before the data is recorded. The conversion is accomplished, for example, by a code conversion apparatus such as that shown in FIG. 18.
As shown in FIG. 18, when main data is input to a scrambler 101, the scrambler 101 scrambles the main data in accordance with a pseudo-random number sequence and then supplies the scrambled main data to an 8/16 modulator 102. When the scrambled main data is input to the 8/16 modulator 102, the 8/16 modulator 102 modulates the main data and then outputs the modulated main data as recording data. The recording data is transmitted to a recording/reproducing apparatus to be recorded onto a recording medium.
In addition, the higher 4 bits (i.e., bit 4 to bit 8) of the logical address (8 bits) associated with the input main data is also input to the scrambler 101 as a seed select signal. Scramble data of different types are sequentially selected within a set of 16 logical addresses (i.e., on the basis of 16 sectors). That is to say, single scramble data is represented by any of respectively different 16 types of pseudo-random number sequences. Thus, in the respective sectors, the 16 types of pseudo-random number sequences associated with the respective scramble data are sequentially selected. Moreover, the scrambler 101 scrambles the data included in one sector depending upon the selected pseudo-random number sequences, in response to a sector start signal.
The scrambling is performed by the scrambler 101 by obtaining the exclusive-OR of the main data and the data (or random numbers) generated from an M sequence (maximum length sequence) represented by the following generating polynomial (1) for every bit of both types of data. EQU X.sup.15 +X.sup.4 +1 (1)
FIG. 19 illustrates a configuration of the scrambler 101. As shown in FIG. 19, the initial bit patterns of the 16 types of pseudo-random number sequences are stored beforehand in a seed ROM 111. In response to a seed select signal, any of these initial bit patterns is selected from the seed ROM 111. A shift register 112 receives the initial bit pattern selected from the seed ROM 111 in response to a seed load signal and then sequentially shifts the initial bit pattern in synchronization with a bit clock. An exclusive-OR element 113 obtains an exclusive-OR of the bit shifted out by the shift register 112 and the fourth most significant bit stored in the shift register 112 and then returns the operation result to the shift register 112. The lower 8 bits stored in the shift register 112 are latched in a flip-flop 114 in synchronization with a word clock. A corresponding bit of the 8-bit string latched in the flip-flop 114 is applied to an individual exclusive-OR element 115. Not only the corresponding bit of the 8-bit string but also a corresponding bit of 8-bit main data word are input to each of these exclusive-OR elements 115, which obtains the exclusive-OR of each pair of bits and then outputs the operation result.
On the other hand, the 8/16 modulator 102 performs a two-stage modulation to produce an output main data from the scrambled main data. The first stage modulation is performed to produce 16-bit main data from 8-bit main data by modulating the scrambled data by means of a pit position modulation (PPM), while the second stage modulation is performed to produce 16-bit output main data from the 16-bit main data by modulating the 16-bit main data by means of a pulse width modulation (PWM).
FIG. 20 illustrates a configuration of the 8/16 modulator 102. As shown in FIG. 20, the 8-bit main data scrambled by the scrambler 101 is not only supplied to a main table 122 and a sub-table 123 via a flip-flop 121 but also directly supplied to a digital sum value (DSV) controller 124. The main data and data representing the next state as selected by a selector 125 are input to the main table 122. Similarly, the main data and the data representing the next state as selected by the selector 125 are input to the sub-table 123.
The main table 122 includes the main data shown in the following Table 1. An 8-bit main data value is searched for by state in the main table 122 and a 16-bit main data word corresponding to the next state is selected and output with reference to the main data shown in Table 1. Similarly, the sub-table 123 includes the sub-data shown in the following Table 2. An 8-bit main data value is searched for by state in the sub-table 123 and a 16-bit main data word corresponding to the next state is selected and output with reference to the sub-data shown in Table 2.
Since the range of the 8-bit main data values is from 0 to 255, 256 sets of 16-bit main data words are defined beforehand in the main table 122 for the respective 8-bit main data values (0 to 255). However, it should be noted that only a part (0 to 45) of the 8-bit main data values (0 to 255) and only a part of the 16-bit main data words corresponding to these 46 values are shown in Table 1. On the other hand, in the sub-table 123, 88 sets of 16-bit main data words are defined for a part (0 to 87) of the 8-bit main data values (0 to 255), unlike the main table 122. However, a smaller part (0 to 45) of the 88 8-bit main data values (0 to 87) and a smaller part of the 16-bit main data words corresponding to the 46 values are shown in Table 2. Furthermore, in both the tables 122 and 123, the next state is defined for each of the 16-bit main data words. Thus, when the 16-bit main data word is searched for, the next state corresponding to the 16-bit main data word is also read out.
TABLE 1 __________________________________________________________________________ Conversion table for 8/16 modulated codes(main) Main State 1 State 2 State 3 State 4 data Code Word Next Code Word Next Code Word Next Code Word Next value MSB LSB State MSB LSB State MSB LSB State MSB LSB State __________________________________________________________________________ 0 0010000000001001 1 0100000100100000 2 0010000000001001 1 0100000100100000 2 1 0010000000010010 1 0010000000010010 1 1000000100100000 3 1000000100100000 3 2 0010000100100000 2 0010000100100000 2 1000000000010010 1 1000000000010010 1 3 0010000001001000 2 0100010010000000 4 0010000001001000 2 0100010010000000 4 4 0010000010010000 2 0010000010010000 2 1000000100100000 2 1000000100100000 2 5 0010000000100100 2 0010000000100100 2 1001001000000000 4 1001001000000000 4 6 0010000000100100 3 0010000000100100 3 1000100100000000 4 1000100100000000 4 7 0010000001001000 3 0100000000010010 1 0010000001001000 3 0100000000010010 1 8 0010000010010000 3 0010000010010000 3 1000010010000000 4 1000010010000000 4 9 0010000100100000 3 0010000100100000 3 1001001000000001 1 1001001000000001 1 10 0010010010000000 4 0010010010000000 4 1000100100000001 1 1001001000000001 1 11 0010001001000000 4 0010001001000000 4 1000000010010000 3 1000000010010000 3 12 0010010010000001 1 0010010010000001 1 1000000010010000 2 1000000010010000 2 13 0010001001000001 1 0010001001000001 1 1000010010000001 1 1000010010000001 1 14 0010000001001001 1 0100000000100100 3 0010000001001001 1 0100000000100100 3 15 0010000100100001 1 0010001001000001 1 1000001001000001 1 1000010001000001 1 16 0010000010010001 1 0010000100100001 1 1000000100100001 1 1000000100100001 1 17 0010000000100010 1 0010000000100010 1 1000001001000000 4 1000001001000000 4 18 0001000000001001 1 0100000010010000 2 0001000000001001 1 0100000010010000 2 19 0010000000010001 1 0010000000010001 1 1001000100000000 4 1001000100000000 4 20 0001000000010010 1 0001000000010010 1 1000100010000000 4 1000100010000000 4 21 0000100000000010 1 0000100000000010 1 1000000010010001 1 1000000010010001 1 22 0000010000000001 1 0000010000000001 1 1000000001001001 1 1000000001001001 1 23 0010001000100000 2 0010001000100000 2 1000000001001000 2 1000000001001000 2 24 0010000100010000 2 0010000100010000 2 1000000001001000 3 1000000001001000 3 25 0010000010001000 2 0100000000100100 2 0010000010001000 2 0100000000100100 2 26 0010000001000100 2 0010000001000100 2 1000000000100010 1 1000000000100010 1 27 0001000100100000 2 0001000100100000 2 1000000000010001 1 1000000000010001 1 28 0010000000001000 2 0100000010010000 3 0010000000001000 2 0100000010010000 3 29 0001000010010000 2 0001000010010000 2 1001001000000010 1 1001001000000010 1 30 0001000001001000 2 0100000100100000 3 0001000001001000 2 0100000100100000 3 31 0001000000100100 2 0001000000100100 2 1001000100000001 1 1001000100000001 1 32 0001000000000100 2 0001000000000100 2 1000100100000010 1 1000100100000010 1 33 0001000000000100 3 0001000000000100 3 1000100010000001 1 1000100010000001 1 34 0001000000100100 3 0001000000100100 3 1000000000100100 2 1000000000100100 2 35 0001000001001000 3 0100001001000000 4 0001000001001000 3 0100001001000000 4 36 0001000010010000 3 0001000010010000 3 1000000000100100 3 1000000000100100 3 37 0001000100100000 3 0001000100100000 3 1000010001000000 4 1000010001000000 4 38 0010000000001000 3 0100100100000001 1 0010000000001000 3 0100100100000001 1 39 0010000001000100 3 0010000001000100 3 1001000010000000 4 1001000010000000 4 40 0010000010001000 3 0100010010000001 1 0010000010001000 3 0100010010000001 1 41 0010000100010000 3 0010000100010000 3 1000010010000010 1 1000010010000010 1 42 0010001000100000 3 0010001000100000 3 1000001000100000 2 1000001000100000 2 43 0010010001000000 4 0010010001000000 4 1000010001000001 1 1000010001000001 1 44 0001001001000000 4 0001001001000000 4 1000001000100000 3 1000001000100000 3 45 0000001000000001 1 0100010001000000 4 1000001001000010 1 0100010001000000 4 __________________________________________________________________________
TABLE 2 __________________________________________________________________________ Conversion table for 8/16 modulated codes(sub) Main State 1 State 2 State 3 State 4 data Code Word Next Code Word Next Code Word Next Code Word Next value MSB LSB State MSB LSB State MSB LSB State MSB LSB State __________________________________________________________________________ 0 0000010010000000 4 0000010010000000 4 0100100001001000 2 0100100001001000 2 1 0000100100000000 4 0000100100000000 4 0100100001001000 3 0100100001001000 3 2 0001001000000000 4 0001001000000000 4 0100100000001001 1 0100100000001001 1 3 0000001001000000 4 0100010000000001 1 1000001000000000 4 0100010000000001 1 4 0000000100100000 3 0100100000000010 1 1001000000000100 3 0100100000000010 1 5 0000000010010000 3 0100001000000000 4 1001000000100100 3 0100001000000000 4 6 0000000001001000 3 0100100000000100 2 1001000001001000 3 0100100000000100 2 7 0000000001001000 2 0100000100000000 4 1001000000000100 2 0100000100000000 4 8 0000000010010000 2 0100100010010000 3 1001000000100100 2 0100100010010000 3 9 0000000100100000 2 0000100000100100 2 1001000001001000 2 0100100000100100 2 10 000001000100000 4 0000010001000000 4 1001001001000000 4 1001001001000000 4 11 0000100010000000 4 0000100010000000 4 1000100001001000 3 1000100001001000 3 12 0001000100000000 4 0001000100000000 4 0100010001001000 3 0100010001001000 3 13 0010001000000000 4 0010001000000000 4 1000100000000100 3 1000100000000100 3 14 0000001000100000 3 0100100000000100 3 1001000010010000 3 0100100000000100 3 15 0000000100010000 3 0100100010010000 2 1001000100100000 3 0100100010010000 2 16 0000000010001000 3 0100001000000001 1 0100100000001000 3 0100001000001001 1 17 0000000001000100 3 0100010000000010 1 0100100010001000 3 0100010000000010 1 18 0000000001000100 2 0100100000100100 3 1001000010010000 2 0100100000100100 3 19 0010000010001000 2 0100100100100000 3 1001000100100000 2 0100100100010000 3 20 0000000100010000 2 0100100100100000 2 0100010001001000 2 0100100100100000 2 21 0000001000100000 2 0100100000010010 1 0100100000001000 2 0100100000010010 1 22 0000010010000001 1 0000010010000001 1 1000100000100100 3 1000100000100100 3 23 0000100100000001 1 0000100100000001 1 1000100010010000 3 1000100010010000 3 24 0001001000000001 1 0001001000000001 1 0100100010001000 2 0100100010001000 2 25 0010010000000001 1 0010010000000001 1 1000100000000100 2 1000100000000100 2 26 0010000001001001 1 0100010000000100 3 1000010000000001 1 0100100000000100 3 27 0000000010010001 1 0100000100000001 1 1000100000000010 1 0100000100000001 1 28 0000000100100001 1 0100010000000100 2 1001000000001001 1 0100010000000100 2 29 0000001001000001 1 0100001000000010 1 1001000000010010 1 0100001000000010 1 30 0001000001000000 4 0000100001000000 4 1000100000100100 2 1000100000100100 2 31 0001000010000000 4 0001000010000000 4 1000100001001000 2 1000100001001000 2 32 0001000100000000 4 0010000100000000 4 0100010000001001 1 0100100000001001 1 33 0000010000100000 3 0000010000100000 3 0100100001001001 1 0100100001001001 1 34 0000001000010000 3 0100010000010010 1 1000100100100000 3 0100010000010010 1 35 0000000100001000 3 0100100000010001 1 1001000000001000 3 0100100000010001 1 36 0000000010000100 3 0100000100000000 4 1001000001000100 3 0100000010000000 4 37 0000010000100000 2 0000010000100000 2 1000001000000001 1 1000001000000001 1 38 0000000010000100 2 0100010000100100 3 1000100010010000 2 0100010000100100 3 39 0000000100001000 2 0100010000100100 2 1000100100100000 2 0100010000100100 2 40 0000001000010000 2 0100100000100010 1 1001000000001000 2 0100100000100010 1 41 0000010001000001 1 0000010001000001 1 1000010000000010 1 1000010000000010 1 42 0000010010000010 1 0000010010000010 1 1000000100000000 4 1000000100000000 4 43 0000100010000001 1 0000100010000001 1 1001000001000100 2 1001000001000100 2 44 0000100100000010 1 0000100100000010 1 1001000000001001 1 1000100000001001 1 45 0001000100000001 1 0001000100000001 1 1001000010001000 3 1001000010001000 3 46 0001001000000010 1 0001001000000010 1 1001000100010000 3 1001000100010000 3 __________________________________________________________________________
In the main table 122, if an input 8-bit main data value is included within the range from 0 to 87, any of the four types of states S1 to S4 shown in Table 1 is selected in accordance with the next state specified by the selector 125. A 16-bit main data word corresponding to the input 8-bit main data value is selected from the 16-bit main data words belonging to the selected state. Then, the selected 16-bit main data word DM is output to a cross-bar switch 126.
On the other hand, if an input 8-bit main data value is included within the range from 88 to 255 in the main table 122 and any of the two types of states S1 and S4 shown in Table 1 is selected in accordance with the next state specified by the selector 125, a 16-bit main data word corresponding to the input 8-bit main data value is selected from the 16-bit main data words belonging to the selected state S1 or S4. Then, the selected 16-bit main data word D1 or D4 is output to the cross-bar switch 126. Furthermore, if an input 8-bit main data value is included within the range from 88 to 255 in the main table 122 and any of the two types of states S2 and S3 shown in Table 1 is selected in accordance with the next state specified by the selector 125, a 16-bit main data word corresponding to the input 8-bit main data value is selected from the 16-bit main data words belonging to the selected state S2 or S3. Then, the selected 16-bit main data word is output to the cross-bar switch 126.
Similarly, if an input 8-bit main data value is included within the range from 0 to 87 in the sub-table 123, any of the four types of states S1 to S4 shown in Table 2 is selected in accordance with the next state specified by the selector 125. And a 16-bit main data word corresponding to the input 8-bit main data value is selected from the 16-bit main data words belonging to the selected state. Then, the selected 16-bit main data word DS is output to the cross-bar switch 126.
At this time, not only the selected 16-bit data words but also the next states corresponding to these 16-bit data words are read out from the tables 122 and 123 and then output to the cross-bar switch 126.
It is noted that the next state is initialized to be 1 in response to a sync code at the beginning of a frame.
When an 8-bit main data value and the next state specified by the selector 125 are input to the DSV controller 124, the DSV controller 124 makes a decision based on the 8-bit main data value and the next state and then outputs a cross-bar switch select signal corresponding to the decision result to the cross-bar switch 126.
In response to the cross-bar switch select signal, the cross-bar switch 126 selects one or two main data word(s) from the 16-bit main data word provided from the main table 122 and the 16-bit main data word provided from the sub-table 123 and then outputs the one or two 16-bit main data word(s) to at least one of a first DSV arithmetic circuit 127 and a second DSV arithmetic circuit 128.
For example, if the DSV controller 124 has determined that the 8-bit main data value is equal to or smaller than 87 and the 16-bit main data word corresponding to the 8-bit main data value exists in each of the main table 122 and the sub-table 123, then the cross-bar switch 126 selects the 16-bit main data words DM and DS from the main table 122 and the sub-table 123, respectively, in response to the cross-bar switch select signal. Then, the cross-bar switch 126 outputs the 16-bit main data words DM and DS to the first and the second DSV arithmetic circuits 127 and 128.
On the other hand, if the DSV controller 124 has determined that the 8-bit main data value is equal to or larger than 88, the 16-bit main data word corresponding to the 8-bit main data value exists only in the main table 122, and either the state S1 or the state S4 has been selected by the next state specified by the selector 125, then the cross-bar switch 126 selects the 16-bit main data word D1 or D4 supplied from the main table 122 in response to the cross-bar switch select signal. Then, the cross-bar switch 126 outputs the 16-bit main data word D1 or D4 to the first and the second DSV arithmetic circuits 127 and 128.
Furthermore, if the DSV controller 124 has determined that the 8-bit main data value is equal to or larger than 88, the 16-bit main data word corresponding to the 8-bit main data value exists only in the main table 122, and either the state S2 or the state S3 has been selected by the next state specified by the selector 125, then the cross-bar switch 126 selects only a single 16-bit main data word (or the 16-bit main data word which has been read out in accordance with either the state S2 or the state S3 specified by the next state) supplied from the main table 122 in response to the cross-bar switch select signal. Then, the cross-bar switch 126 outputs the 16-bit main data word D2 or D3 to the first DSV arithmetic circuit 127.
The selections made by the cross-bar switch 126 from the 16-bit main data words DM, D1, D4 and DS are classified as shown in the following Table 3.
TABLE 3 ______________________________________ Main Data 0 to 87 88 to 255 88 to 255 Value Next S1, S2, S3, S1 or S4 S2 or S3 State S4 Data Select DM from Select D1 or Always Selection main table and D4 correspond- select DM DS from ing to S1 or specified by sub-table S4 from main next state table S2 or S3 from main table ______________________________________
However, in the case where the 8-bit main data value is equal to or larger than 88 and either the state S1 or the state S4 has been selected in accordance with the next state specified by the selector 125, if the run length of successive codes having an equal sign between an 8-bit main data word and a previous 8-bit main data word is out of the range from 2 to 10 in either the state S1 or the state S4, then the DSV controller 124 controls the cross-bar switch 126 such that only a 16-bit main data word D1 or D4 belonging to the state S1 or S4 and having a run length within the range from 2 to 10 is selectively output. Thus, in order to output the 16-bit main data words D1 and D4 from the main table 122 to the first and the second DSV arithmetic circuits 127 and 128, the run length of the successive codes having an equal sign between an 8-bit main data word and a previous 8-bit main data word is required to be within the range of 2 to 10.
Every time a 16-bit main data word is input to the first arithmetic circuit 127 and/or the second arithmetic circuit 128, the arithmetic circuit(s) calculate(s) a digital sum value (DSV) associated with the input 16-bit main data word. The algorithm used for calculating the DSV is as follows.
For example, if a 16-bit main data word such as that shown in FIG. 21A is input from the cross-bar switch 126 to a PWM modulator 129 via the selector 125, the PWM modulator 129 performs a pulse width modulation on the 16-bit main data word, thereby producing and outputting a 16-bit output main data word such as that shown in FIG. 21B.
As can be seen from the comparison between FIGS. 21A and 21B, the number of "1" bits and the number of "0" bits included in a single output main data word can be derived from a single 16-bit input main data word. Thus, every time a single 16-bit main data word is input, the number of "1" bits and the number of "0" bits included in a single output main data word corresponding to the single 16-bit input main data word are obtained and then the difference between the numbers is calculated. The differences calculated for the respective words are accumulated, thereby obtaining a DSV. The DSVs calculated by the first and the second DSV arithmetic circuits 127 and 128 are supplied to the selector 125 and a comparator 130. In actuality, the "1" bit included in a single output main data word is replaced by a value "+1" and the "0" bit included in the single output main data word is replaced by a value "-1". The total sum of the values "+1" and "-1" is calculated in each output main data word. Then, the sums are accumulated for the respective words, thereby obtaining the DSV.
In addition, the calculation is performed by the first and the second DSV arithmetic circuits 127 and 128 on a sector basis, and is continuously performed from the beginning to the end of a single sector. At the beginning of a sector, the first bit (or the least significant bit LSB) of the sector is input from the PWM modulator 129 to the first and the second DSV arithmetic circuits 127 and 128 and the first value of the output main data word is initialized or set to be equal to zero in response to the bit LSB.
When the DSVs are input from the first and the second DSV arithmetic circuits 127 and 128 to the comparator 130, the comparator 130 selects either one of the DSVs having a smaller absolute value and then provides the information indicating the arithmetic circuit 127 or 128 which has calculated the selected DSV for the selector 125. In response to the information, the selector 125 selects the arithmetic circuit 127 or 128 indicated by the comparator 130, outputs the 16-bit output main data word from which the DSV has been calculated by the arithmetic circuit 127 or 128 to the PWM modulator 129, and outputs the next state associated with the 16-bit output main data word to the main table 122, the sub-table 123 and the DSV controller 124.
That is to say, in the 8/16 modulator 102, 8-bit input main data words are modulated into corresponding 16-bit main data words, the DSV of the respective output main data words corresponding to the 16-bit main data words is calculated beforehand, the 16-bit main data words, from which a smaller DSV can be derived, are selected and then the 16-bit main data words are modulated into the 16-bit output main data words so as to be output. However, as mentioned above, if the 16-bit main data word corresponding to the input 8-bit main data value exists only in the main table 122 and either the state S2 or the state S3 has been selected by the next state specified by the selector 125, then only a single 16-bit main data word (or the 16-bit main data word which has been read out in accordance with either the state S2 or the state S3 specified by the next state) is selected from the main table 122. Thus, the modulation from the 16-bit main data word to the 16-bit output main data word is performed.
A series of processing steps performed by such a code conversion apparatus will be described with reference to the flow charts shown in FIGS. 22 and 23.
First, after the top of a frame has been identified by counting the respective bits of an input main data word (Step 201), a sync code is added to the top of the frame (Step 202) and the next state output from the selector 125 of the 8/16 modulator 102 is initialized to be S1 (Step 203). Then, if it is determined that the end of a sector has not been reached (Step 204, NO), then the processing returns to Step 201.
Subsequently, the scrambling of the frame of the input main data word is started (Step 205) and the frame of the scrambled main data word is converted into the frame of an output main data word on a word basis (Step 206). Then, if the top of the next frame is identified (Step 201), a sync code is added to the top of the frame (Step 202) and the next state is initialized again to be S1 (Step 203). Next, the scrambling and the conversion are performed (Steps 205 and 206). From then on, similar processing is repeatedly performed on the respective frames. And when the end of a sector has been reached (Step 204, YES), the processing of one sector ends.
Moreover, after Step 206 has been performed, it is also determined whether or not the 8-bit main data value is smaller than 88. As shown in FIG. 23, if the value is smaller than 88 (Step 301, YES), then a 16-bit main data word having a smaller DSV is selected from the 16-bit main data word DM supplied from the main table 122 and the 16-bit main data word DS supplied from the sub-table 123 (Step 302).
On the other hand, if the 8-bit main data value is equal to or larger than 88 (Step 301, NO), then a 16-bit main data word D1 or D4 having a smaller DSV is selected from the main table 122 (Step 303).
If an output main data word always having a smaller DSV is produced in this manner, then the low frequency components of the main data word are reduced. Thus, in a recording/reproducing apparatus for recording and/or reproducing the main data word onto/from a recording medium, the low frequency components of a reproduced signal can be reduced, the shift of the envelope of the reproduced signal can be suppressed, and a reproduction error can be prevented to a certain degree.
However, though the above-described prior art code conversion apparatus can surely reduce the low frequency components of a reproduced signal and the possibility of the abnormal increase of the low frequency components, the degree of the reduction is not satisfactorily high and a reproduction error may continue to occur in some cases.
More specifically, when there are M types of 16-bit main data words in the 8/16 modulator 102 shown in FIG. 20, N types of 16-bit main data words having bit patterns causing the DSV to diverge are included in the M types of 16-bit main data words. Thus, if 16-bit main data words having such bit patterns successively appear, then the DSV adversely increases or decreases to diverge. As a result, the low frequency components of the output main data words are disadvantageously increased.
In the above-described conventional example, M=256 and N=168. When the 8-bit main data value is within the range from 0 to 87, the DSV converges. On the other hand, when the 8-bit main data value is in the range from 88 to 255, the DSV diverges. In actuality, the divergence of the DSV occurs in about 10% of the entire main data. FIG. 24A is a graph showing the variation of the 8-bit main data values in one sector and FIG. 24B is a graph showing the increase and the decrease of the DSV in accordance with the variation of the 8-bit main data values. As can be seen from these graphs, if the 8-bit main data values are continuously included within the range from 88 to 255, the DSV diverges.
That is to say, in the prior art code conversion apparatus, though the input main data is scrambled and the scrambled main data is subjected to an 8/16 modulation, the low frequency components of the main data cannot be satisfactorily reduced. Consequently, when the main data is reproduced from a recording medium on which the main data has been recorded, the low frequency components of the reproduced signal increase, the envelope of the reproduced signal abruptly varies, and a reproduction error occurs. Even if the envelope of the reproduced signal is corrected or the main data is corrected by using an error correction code (ECC) to be added thereto, such a reproduction error cannot be totally prevented.
In addition, since a set of pseudo-random number sequences are sequentially rearranged in a predetermined order, it is possible that substantially the same signal is repeatedly rewritten on the same sector. In such a case, since the characteristics of a part of the recording medium occupied by the sector in question become nonuniform, the S/N ratio of the reproduced signal is decreased and a reproduction error occurs in some cases.

Code conversion method and apparatus, code recording medium, code recording apparatus and code reproducing apparatus

Matsushita Electric Industrial Co., Ltd.


An oceanographic sampling system includes two or more underwater vehicles disposed in an array and an array controller for controlling the array of underwater vehicles as data is acquired. Each underwater vehicle includes a propulsion system for moving the underwater vehicle independently of the other underwater vehicles, a sensor for sensing an ocean parameter and providing sensor data representative of the ocean parameter as the underwater vehicle moves, a navigation subsystem for determining position data representative of the position of the underwater vehicle as the sensor data is acquired and a synchronizing subsystem for time synchronizing the sensor data and the position data acquired by the underwater vehicle with sensor data and position data acquired by other underwater vehicles. The array of underwater vehicles may function as a large aperture phased array, and phased array analysis techniques may be applied to the time-synchronized sensor data and position data.

Oceanographic measurements play an important role in all aspects of ocean science and engineering. Typical applications in applied marine science and engineering include mapping of pollutant transport, environmental monitoring, search for pollution sources, national security, target localization, search and rescue, marine geophysics, resource exploration and resource production. In basic marine science, oceanographic measurements are a key component, together with modeling, of the development of the fundamental understanding which subsequently provides the basis for engineering, management, and policy solutions.
A common problem for all these applications of marine measurements is the fact that they have become extremely platform limited. The performance/cost ratio has grown exponentially for the computer technology used for modeling and analysis, but has been diminishing or, at best, remained unchanged in terms of the platforms. Most oceanographic measurements are still performed from ships.
The development of inexpensive autonomous underwater vehicle technology has provided a breakthrough in terms of performance/cost ratio, with the potential for revolutionizing the area of experimental oceanography in deep as well as shallow water. The concept of autonomous oceanographic sampling networks (AOSN) provides a particularly powerful technology. Autonomous oceanographic sampling networks are described, for example, by T. B. Curtin et al, in "Autonomous Oceanographic Sampling Networks ", Oceanography, Vol. 6, No. 3, 1993, pages 86-93. However, the AOSN technology has its inherent limitations because of its particular functionality.
A fundamental problem facing oceanographic measurement techniques is a tradeoff between coverage and resolution. A measurement system may cover a large area, but only be able to produce results over a very coarse grid in space and time. This is the case for ship-based collection of water samples. Other measurement techniques are highly accurate and capable of measuring small spatial and temporal variations, but cover only a very small volume. In general, the common methods applied in oceanography provide a compromise between the two extremes. While a wide variety of oceanographic measurement techniques exist, none is capable of simultaneously providing wide area coverage of the entire water column and high resolution.
One widely-used oceanographic measurement technique is acoustic tomography, which is a spin-off of the acoustic methods developed for anti-submarine warfare. Acoustic tomography uses the fact that sound speed is strongly dependent on temperature, salinity and pressure, properties which can therefore be inferred in an ocean volume by analysis of acoustic transmissions within the source-receiver network deployed in the volume. Typically, an acoustic tomography network includes five or six vertical receiver arrays spanning the water column. Each array has an acoustic source transmitting a coded sequence to the other arrays. The analysis is performed by simulating the received signals using a propagation model, the input parameters of which are varied to reproduce the measured data. Acoustic tomography provides coverage in the vertical slices between the sources and receivers, but virtually no information about regions between the slices. The spatial resolution of acoustic tomography is very limited, typically on the order of 100 meters in the horizontal direction and 10 meters in depth. Furthermore, the vertical arrays have fixed positions. The main advantage is the coverage in terms of frequent snapshots, allowing for tracking of oceanographic dynamics. Acoustic tomography is described, for example, by P. F. Worcester, et al. in "A Review of Ocean Acoustic Tomography: 1987-1990", Reviews of Geophysics, Supplement, pages 557-570, April 1991 and by W. H. Munk, et al. in "Ocean Acoustic Tomography: A Scheme for Large Scale Monitoring", Deep Sea Research, Vol. 26A, pages 123-161, 1979.
One implementation of the autonomous ocean sampling network employs moored buoys which function as network nodes for a long-term multiple underwater vehicle presence in the ocean. The objective is to provide an economically feasible capability for a repeated synoptic characterization of large scale oceanographic phenomenon. The key to such a system is a small, low-cost autonomous underwater vehicle which can be operated reliably over extended, unattended deployments at sea. The vehicles traverse the network recording temperature, salinity, velocity and other data, relaying key observations to the network nodes in real time and transferring more complete data sets after docking at a node. Each network node consists of a base buoy or mooring containing an acoustic beacon, an acoustic modem, point sensors, an energy source and one or more autonomous underwater vehicle (AUV) docks. The motivation for multiple vehicle surveys is that the quality and utility of the data obtained improves much faster than the number of vehicles for large scale dynamic ocean phenomenon.
Arrays of hydrophones are widely used. Multiple hydrophones may be spaced along a cable towed behind a ship to form a towed array. The hydrophones may be used in seismic exploration to sense seismo-acoustic energy reflected from structures below the ocean floor or may be used to localize an acoustic source, such as a submarine. Towed arrays have fixed configurations and may be difficult to maneuver. Fixed arrays of hydrophones may be used for similar applications, but lack flexibility and maneuverability.
Existing oceanographic measurement techniques have one or more drawbacks, including low resolution, lack of mobility, lack of flexibility, small acoustic apertures and an inability to adapt to changing conditions it is desirable to provide oceanographic measurement apparatus and methods which overcome one or more of these drawbacks. In particular, it is desirable to provide oceanographic measurement apparatus and methods which permit simultaneous measurement of target characteristics from different directions, which have mobility and flexibility and which permit large acoustic apertures to be implemented at low frequencies.
According to a first aspect of the invention, an oceanographic sampling system comprises a plurality of underwater vehicles disposed in an array having an array configuration and array control means for controlling the array of underwater vehicles as data is acquired. Each underwater vehicle includes a propulsion system for moving the underwater vehicle independently of the other underwater vehicles, a sensor for sensing an ocean parameter and providing sensor data representative of the ocean parameter as the underwater vehicle moves, a navigation subsystem for determining position data representative of the position of the underwater vehicle as the sensor data is acquired and a synchronizing subsystem for time synchronizing the sensor data and the position data acquired by the underwater vehicle with sensor data and position data acquired by the other underwater vehicles. The underwater vehicles function as a phased array, and phased array analysis techniques may be applied to the time-synchronized sensor data and position data.
The array control means may control the array configuration, array movement and underwater vehicle function, alone or in combination. The array may be controlled in a preprogrammed manner or may be controlled adaptively in response to a condition that is determined during acquisitions of sensor data. The array control means may be located externally of the underwater vehicles or in one of the underwater vehicles, or may be distributed among the underwater vehicles. The array control means may include means for controlling the shape of the array, the size of the array, the depth of one or more of the underwater vehicles in the array, the direction of movement of the array, the function of one or more of the underwater vehicles in the array and/or the velocity of the array.
The synchronizing subsystem and the navigation subsystem may utilize optical communication channels between selected ones of the underwater vehicles. In a first embodiment, the optical communication channels each include light-emitting diodes and photosensors for optical communication. In a second embodiment, the optical communication channels each include lasers and photosensors for optical communication. The synchronizing subsystem and the navigation subsystem may alternatively use high frequency acoustic communication channels between selected ones of the underwater vehicles. One or more of the underwater vehicles may include an acoustic excitation source.
According to another aspect of the invention, a method for oceanographic sampling is provided. Two or more underwater vehicles are disposed in an array. Each underwater vehicle includes a propulsion system for moving the underwater vehicle independently of other ones of the underwater vehicles. An ocean parameter is sensed with each of the underwater vehicles and sensor data representative of the ocean parameter is provided as the underwater vehicle moves. Position data representative of the position of each of the underwater vehicles is determined as the sensor data is acquired. The sensor data and the position data acquired by each of the underwater vehicles is time synchronized with sensor data and position data acquired by other ones of the underwater vehicles. The array of underwater vehicles is controlled as the time-synchronized sensor data and position data are acquired, The array of underwater vehicles thereby functions as a phased array.


A device for punching holes in a bicycle rim includes a flange extending radially from a base, the flange having a plurality of rails disposed thereon each for a puncher slidably disposed thereon. Each of the punchers has a first block and a second block respectively extending upwardly from two ends thereof and a cylinder disposed longitudinally to each of the first blocks having a shaft retractably extending therefrom which extends through the first block and has a pin member disposed on a free end thereof. Each of the second blocks has a longitudinal hole defined therethrough so that when a bicycle rim is disposed between the first blocks and the second blocks each of the pin members punches a hole through the rim.

1. Field of the Invention
The present invention relates to a punching device and, more particularly, to a punching device for punching holes in a bicycle rim.
2. Brief Description of the Prior Art
FIGS. 1 and 2 show a conventional device 60 for punching holes in a bicycle rim 70. The device 60 includes a first cylinder 62 and a second cylinder 64 both of which are disposed on a base 61. A sliding frame 63 slidably extending through the base 61 has a first end plate 631 extending perpendicularly from a first end thereof and a second end plate 632 extending perpendicularly from a second end thereof, wherein the first end plate 631 is connected to a first shaft 621 of the first cylinder 62 and the second end plate 632 has a clamp device 6321 disposed on a top thereof. The second cylinder 64 has a second shaft 642 retractably extending therefrom which has a pin member 646 extending longitudinally therefrom. An extending plate 643 is connected to the second shaft 642 and a block 645 is slidably disposed on the extending plate 643 wherein the pin member 646 freely extends through the block 645. A spring 648 is mounted to a casing 649 of the pin member 646 and urged between the block 645 and the second shaft 642. The block 645 has a ring member 647 disposed to a side facing the clamp device 6321 and a tube 644 is connected to the ring member 647 so that the pin member 646 extends through the tube 644. A plurality of the above mentioned devices 60 are arranged in a circle as shown in FIG. 2 and a bicycle rim 70 is disposed to a position by a robot, for example, to be clamped by the clamp devices 6321. The first cylinder 62 of each device is then actuated to extend each respective first shaft 621 so that each sliding frame 63 is moved to shift the rim 70 toward the respective pin member 646. The second shaft 642 of each of the devices 60 is then extended to depress the respective spring 648 and the tube 644 forms a recess in an inner periphery of the rim 70, and then, the pin member 646 punches a hole through a bottom defining the recess of the rim 70. An inherent shortcoming of the device 60 is that two cylinders 62, 64 have to be actuated respectively and this is time inefficient.
The present invention intends to provide a improved device for punching holes in a bicycle rim to mitigate and/or obviate the above-mentioned problem.

Device for punching holes in a bicycle rim


A blocker member is mounted on the vehicle body adjacent the floor mounted door track and includes a housing and a blocker lever which is pivotally mounted on the housing. The blocker lever is operably connected to the fuel filler door by a cable. When the fuel filler door is opened, the cable is tensioned and pivots the blocker lever to an extended position in which the blocker lever extends into the path of sliding movement the door. Thus, whenever the fuel filler door is open, the sliding door is blocked from sliding open into engagement with the fuel filler door. The blocker member preferably includes a resilient bumper against which the blocker lever seats in order to absorb energy when the door is slid into engagement with the blocker lever. The cable is preferably connected to the blocker by an actuator lever and spring arrangement by which the cable and actuator lever have a range of movement beyond the movement of the blocker lever so as to accommodate any misadjustment of the cable connecting the fuel filler and the blocker member.

It is well known in van type vehicles to provide a sliding door mounted on tracks by which the door slides rearwardly to permit access to the vehicle passenger compartment.
It is also well known that typically, fuel a fuel filler door on the side wall of a vehicle conceals a fuel filler cap.
When the sliding door is open, the fuel filler door is inaccessible. However, when the vehicle sliding door is closed, the fuel filler door may be opened to access the fuel filler cap.
A disadvantage of the aforedescribed system is that an inadvertent attempted opening of the sliding door when the fuel filler door has already been opened will cause the sliding door to interfere with the fuel filler door.

Fuel door interlock for vehicle sliding door


A fuel supply device has a container from which fuel is to be supplied to an internal combustion engine, a receptacle, a fuel feeding aggregate arranged on the receptacle, a connecting unit for receiving electrical and hydraulic connecting elements. The fuel container has a lower side provided with an opening, and the fuel feeding aggregate is insertable in the opening of the lower side of the fuel container.

The present invention relates to a fuel supply device for the fuel container from which fuel is supplied to an internal combustion engine.
Fuel supply devices for the above mentioned general type are known in the art. Upon such fuel supply devices disclosed in the German Document G4103920A1. It has a fuel container for storing fuel and an auxiliary container in which the fuel container is insertable to store a part of the fuel. The auxiliary container has a receptacle for positioning a fuel feeding aggregate. A tank flange is provided on the upper side of the auxiliary container and supports the auxiliary container in the fuel tank. The tank flange has connecting devices for electrical and hydraulic connection conduits. For filling the auxiliary container with fuel, a pump is provided in its lower region and supplied with fuel into the auxiliary container. It is controllable via a measuring device to obtain a predetermined level of the fuel to be supplied in the auxiliary container. Such an arrangement which is insertable from above in the fuel container requires a relatively accurate dimensioning of the corresponding parts to arrange the pump for the auxiliary container or for the fuel feeding aggregate near a bottom of the fuel container, so as to make available the complete volume of the fuel container for feeding to an internal combustion engine.


A method and apparatus are disclosed for detecting a fault in a transceiver of a base transceiver system. In the transceiver having a down converter, a microprocessor reads a predetermined first minimum value and a predetermined first maximum value of received input signal levels, measures an instantaneous control voltage generated from an automatic gain controller (AGC) and converts the measured instantaneous AGC control voltage into a received input signal level. When the converted received input signal level is below the predetermined first minimum value, the microprocessor determines that a fault exists in the amplifier operation of the down converter. Similarly, when the received input signal level exceeds the predetermined first maximum value, the microprocessor determines that a fault exists in the amplifier operation of the down converter. On the other hand, when the converted received input signal level stays between the predetermined first maximum and the predetermined first minimum values of the received input signal levels, the microprocessor reads a predetermined second minimum value and a predetermined second maximum value of intermediate frequency (IF) detection voltage values, and also reads an instantaneous IF detection voltage, which is measured by the AGC. When the instantaneous IF detection voltage is below the predetermined second minimum value of the IF detection voltage value, the microprocessor determines that a fault exists in the AGC operation of the down converter, and when the IF detection voltage exceeds the predetermined second maximum value of the IF detection voltage value, the microprocessor determines that a fault exists in the AGC operation of the down converter.

The present invention relates to a self-diagnosis system for detecting faults in a transceiver within a wireless receiving unit of a base transceiver station. More specifically, the present invention relates to a self-diagnostic method for diagnosing and detecting faults in an internal circuit of the transceiver unit in a radio base transceiver system (BTS) and an apparatus thereof.
In a mobile communication system, namely, in a conventional code division multiple access (CDMA) system, the system is provided with a plurality of mobile stations, a plurality of base transceiver systems (BTSs) for providing communication service to the mobile stations, a base station controller (BSC) for connecting the BTSs with a mobile switching center (MSC), and the MSC for connecting the BSC to a public switched telephone network (PSTN).
FIG. 1 is a block diagram which illustrates a radio frequency (RF) receive path of a typical CDMA cellular BTS. The BTS includes an out-door system 1 for receiving a radio frequency (RF) signal from mobile stations, and an in-door system 2 for processing the received signal.
The in-door system 2 includes a RF unit (RFU) 3 for converting the received RF signal into an intermediate frequency (IF), a digital unit (DU) 4 for demodulating the RFU transmitted signal into a digital signal, and a base station test unit (BTU) 5 coupled to the RFU for testing the BTS.
The RFU 3 includes a front-end unit (REU) 3a coupled to a receiving antenna, a transceiver unit (XCVU) 3b for down converting the received signal into an IF and for outputting the IF at a regular level, and an IF amplifier/divider 3c for transmitting the converted IF signal to the digital unit (DU) 4.
The digital unit (DU) 4 includes a digital signaling unit 4a for demodulating the received signal from the IF amplifier/divider 3c. The BTU 5 includes a RF switch 5a coupled to the front-end unit (FEU) 3a, a variable attenuator 5b for regulating an attenuation value of the signal which is transmitted to the RF switch 5a, and a test mobile (TM) 5c, coupled to the variable attenuator 5b, for providing a test signal.
In the above base transceiver system of a mobile communication system, the base station test unit (BTU) 5 is used to detect for any fault in the receive path when the fault occurs.
FIG. 2 is a flow chart which illustrates a prior method for checking a fault of a receive path of a BTS. In the prior diagnostic method, a fault diagnostic apparatus ascertains a call being currently communicated in a BTS (step 101). If a call were ongoing, the fault diagnosis is terminated since a fault diagnosis can""t be performed during the call being communicated. (step 102). When no call is currently being communicated, the output level of the test unit 5c is properly adjusted and is provided to the transceiver unit 3b via a front-end unit 3a (step 103). The fault diagnosis apparatus remembers the provided output level of the test unit 5c (step 104).
The diagnostic apparatus for detecting faults reads the received input signal level measured by the transceiver unit 3b (step 105), and then compares the received input signal level with the remembered output signal of the test unit 5c (step 106), in order to determine whether the difference of these two signals exceeds a predetermined value of 10 dB (step 107). If the difference exceeds 10 dB, it is determined that a fault exists in the receive path. Thereafter, the diagnosis apparatus reads an IF level outputted from the transceiver unit 3b (step 108) and compares the read IF level with the IF level which was previously saved in an inner memory of the transceiver unit 3b (step 109). If these two compared IF levels are different, it is determined that a fault exists in the transceiver unit 3b (step 110), and if not, it is determined that a fault exists in the front-end unit 3a.
However, if the difference does not exceed 10 dB in step 106, the diagnostic apparatus ascertains as to whether an alarm is reported in the output of the transceiver unit 3b (step 112). If an alarm is reported, it is determined that a fault exists in the IF amplifier/divider 3c, otherwise, it is determined that no fault exists in the receive path of the BTS and all diagnostic procedures are terminated.
As illustrated in the above, the prior known technique uses a base station test unit (BTU) for checking functions of a RF unit. However, the problem with the prior method is that an extra device, for example a BTU, is required for detecting any fault in the system, and moreover, it takes a long time to detect such fault due to very long and complicated diagnostic method. Also, the prior method is not applicable for detecting faults in an internal circuit of the transceiver unit, but only limited to detect faults in a RF unit.
U.S. Pat. No. 5,640,401 entitled, xe2x80x9cCommunication Circuit Fault Detector,xe2x80x9d discloses a communication detector for testing a communication circuit. The communication circuit fault detector generates a test signal and inputs the test signal to the communication circuit to compare the original test signal with the returned test signal outputted from the communication circuit. However, since such fault detector is directed only to detect for a fault in a typical data communication circuit, it is not possible to detect for a fault in an inner circuit of a transceiver unit of a BTS.
One object of the present invention to provide a self-diagnosis system of a transceiver unit for detecting faults in its internal circuit by measuring an auto gain controller control voltage value and an IF detection voltage value of a down converter, and thereafter by comparing to a reference value.
Other objects and advantages will be more easily understood by the following detailed description and accompanying drawings.
It is another object of the present invention to provide a wireless receiving unit of a base transceiver station comprising a down converter and a transceiver slave control board, wherein the down converter includes an amplifier for amplifying a received signal, an automatic gain controller (AGC) for controlling a signal level of the amplified received signal, an AGC detector for detecting an intermediate frequency (IF) detection voltage value and for determining the AGC control voltage value, a transceiver slave control board, which includes an analog to digital converter for converting the IF detection voltage value from the down converter and for converting the AGC control voltage value into digital value, an EEPROM for storing predetermined reference values, a look up table for converting the AGC control voltage values into the received input signal levels, and a maximum, minimum and average IF detection voltage values responsive to changes of the received input signal.
Another object of the present invention is to provide a self-diagnostic method for detecting faults in a transceiver comprising the steps of reading a predetermined first minimum value of received input signal level and a predetermined first maximum value of received input signal level applied to the wireless receiving unit, reading an instantaneous control voltage value of the AGC, converting the instantaneous control voltage value into a received input signal level in accordance with the look up table, and determining that a fault exists in the amplifier operation of the down converter when the converted received input signal is below the predetermined first minimum value of the received input signal level and determining that a fault exists in the amplifier operation of the down converter when the converted received input signal exceeds the predetermined first maximum value of the received input signal level, reading a predetermined second minimum value of the intermediate frequency (IF) detection voltage value and a predetermined second maximum value of the intermediate frequency (IF) detection voltage value when the converted received input signal level stays between the predetermined first minimum value and the predetermined first maximum value of the received input signal levels, reading an instantaneous IF detection voltage value which is measured by the AGC detector and determining that a fault exists in the AGC operation of the down converter when the instantaneous IF detection voltage value is below the predetermined second minimum value of IF detection voltage value and determining that a fault exists in the AGC operation of the down converter when the instantaneous IF detection voltage value exceeds the predetermined second maximum value of IF detection voltage value.
It is further object of the present invention to provide a self-diagnostic apparatus for detecting faults in a transceiver within a wireless receiving unit of a base transceiver station comprising a down converter having an amplifier for amplifying the received input signal, an automatic gain controller (AGC) for regulating the level of the amplified received input signal, an AGC detector for detecting an instantaneous intermediate frequency (IF) detection voltage value and for determining an instantaneous AGC control voltage value, and a transceiver slave control board having a microprocessor, an analog to digital converter for converting the instantaneous IF detection voltage value and the instantaneous AGC control voltage value into digital values, and a memory device for converting the instantaneous AGC control voltage value into corresponding received input signal level and for storing predetermined reference values and a maximum, minimum and average value of IF signal detection voltage value in accordance with changes of the received input signals, wherein the microprocessor compares the instantaneous AGC control voltage value provided by the down converter with a predetermined first minimum value and a predetermined first maximum value of the received input signal levels, respectively, for determining that a fault exists in the amplifying operation of the down converter when the converted received input signal level of the instantaneous AGC control voltage value is below the predetermined first minimum value of the received input signal level or exceeds the predetermined first maximum value of the received input signal level, and thereafter, if the converted received input signal level stays between the range of the predetermined first minimum value and predetermined first maximum value of the received input signal levels, compares the instantaneous IF detection voltage value provided by the down converter with the predetermined second minimum value and a predetermined second maximum value of the IF detection voltage value, respectively, for determining that the down converter""s AGC operation is faulty when the instantaneous IF detection voltage value is below the second minimum value of the IF detection voltage value or exceeds the predetermined second maximum value of the IF detection voltage value.

Self-diagnostic method for detecting faults in a transceiver within a wireless receiving unit of a base transceiver station


A fixed displacement binary pump is provided for a powertrain on a vehicle. A hydraulic system is operatively connected with first and second discharge ports of the pump and is operable to alternately permit fluid flow through both discharge ports (i.e., full displacement or volumetric output of the pump) or permit flow through only the first discharge port (i.e., partial displacement or volumetric output of the pump). The pump may be packaged in a front support of the transmission. An auxiliary pump may be provided that is operable to supplement the output of the binary pump or to be used when the binary pump is off. A method of operating the binary pump and auxiliary pump is provided.

The hydraulic system for a vehicle transmission serves important lubrication, cooling, and clutch actuation functions necessary for operation of the transmission. Generally, hydraulic pressure and flow within the hydraulic system is provided by an engine-driven hydraulic pump having a rotational speed proportional to engine speed. The hydraulic pump must be designed to meet peak demands, such as hydraulic fluid demand during shifting of the transmission, hot engine idle speed garage shifts, and, in certain transmissions, a hydraulic park mode in an electronic transmission range selector (ETRS) system. Additionally, hydraulic requirements of the transmission may still exist when the engine (and thus the engine-driven pump) is off, such as in an electric-only mode in a hybrid electromechanical powertrain. Pump torque and horsepower requirements rise with increasing pump speed, and have an associated negative effect on fuel economy; thus, it is desirable to limit the flow delivery of the pump, to the extent possible. On-demand pumps, which may include binary pumps, are operable at a full or a partial volumetric output. Thus, such pumps may be operated at a fuel-saving partial output whenever possible, operating at full output only when necessary.
Finally, packaging space may be very limited in certain vehicle designs, driving the location of and potentially the size and type of pumps that may be used. For instance, an "on-axis" hydraulic pump has a rotational axis that is aligned (i.e., coaxial) with an axis of rotation of an input member of the transmission (i.e., the transmission axis). An on-axis pump may extend the overall length of the transmission. An "off-axis" pump has an axis of rotation that is offset from and not concentric or coaxial with the transmission axis. Off-axis pumps offer increased flexibility in packaging location. However, in a rear wheel-drive vehicle, if the transmission "tunnel" running fore and aft in the vehicle (i.e., the packaging space allotted to the transmission, typically tunnel-shaped and under the vehicle floor) has relatively little free packaging space, packaging of an off-axis pump appropriately sized to handle the hydraulic requirements of the transmission may be difficult or impossible.

On-demand hydraulic pump for a transmission and method of operation


The present application is to power an electric vehicle using this compact method of transmitting rotational energy and movement with three main parts, two of which are identical (33) (34). But this type of simple design could have nanotechnology applications.

1. Field of Invention
This invention relates to mechanical drive systems, the application described is for an electric vehicle.
2. Prior Art
Vehicles powered by internal combustion engines move several parts in the engine and driveline before providing power to the wheels. Typically, flywheels, clutch assemblies, transmission shafts, gear clusters, differential gears, and final drive shafts are among these parts. Front wheel drive systems can be more efficient and the addition of automatic transmissions can be less efficient.
In all cases power and motion are translated from different rotational planes and sometimes directions before finally being used. Much of the energy required to move these parts and translate this motion is lost.
Efficiently Transmitting Vehicle Drive Power: One attempt to improve the efficiency of transmitting vehicle drive power to the wheels is U.S. Pat. No. 6,179,078 B1 Belloso (2001). This 'Fuel Efficient and Inexpensive Automobile' has independent internal combustion engines mounted at each rear wheel. In this way power is transmitted separately to each of the rear wheels to drive the vehicle forward through chains, belts and torque converters. The vehicle uses electric motors to power it in reverse. Both engines are used for acceleration. To improve fuel efficiency only one engine is used to maintain a desired speed.
This theory of operation seems reasonable. But synchronizing the operation of the separate engine drives would be difficult. An overpowered or underpowered engine or, an engine problem could unintentionally steer the vehicle. The power lost in the torque converters and the drive systems could be significant. High load or long distance rear wheel drive may not be possible.
Other improvements for efficiently transmitting vehicle drive power are shown in several electric and hybrid systems. In the following examples electric motors are directly coupled to the drive wheels or, are, part of the drive wheels. U.S. Pat. Nos.: 5,418,437 Couture et al, (1995), 5,921,338 Edmondson (1999), 6,880,654 B2 Plishner (2005), US 2005/0045392 Maslov et al. (2005), US 2006/0180365 Handa et al. (2006). But these designs lead to another problem, suspension arms with a high un-sprung weight.
High Un-Sprung Weight Suspension Arms: High un-sprung weight suspension arms are slower to move. Once in motion they are more difficult to control. And they are slower to return to their original position and be ready for additional movement.
For example, when potholes are driven over in the roadway the suspension arm(s) and drive wheel(s) are slow to move and find the new bottom. When bumps (small hills) are driven over in the roadway the suspension arm(s) and wheel(s) are slow to return to the roadway if they become airborne.
The slow movement of the high un-sprung weight suspension arm makes the drive wheel(s) stay in the air for a longer period of time. When wheels are not contacting the roadway they provide no traction. Vehicles with high un-sprung weight suspension arms hold the road poorly.


A multitrack coupled element read head and a method for manufacturing such a read head are provided. The multitrack coupled element read head includes multiple coupled magnetoresistive read elements in a spaced relationship, and a support structure between a pair of coupled read elements, the support structure also being a magnetoresistive material. The read head also includes a closure material bonded on the plurality of coupled read elements and the support structure, where the support structure provides for substantially even pressure on the pair of coupled read elements such that shorting therein is eliminated.

There are several ways to fabricate magneto-resistive (MR) sensors for read back of data on magnetic tape. In all cases, a bias method must be used in order to permit the sensor to operate in the linear portion of the MR curve. In some cases, two elements can be used at the same time, reading the same data, to reduce signal distortion by processing the signal differentially so that any nonlinearities arising from the shape of the MR curve are canceled out.
In a coupled element design, the two elements may be placed atop each other in close proximity. This allows the sensors to provide magnetic bias for each other, as well as providing the benefits of differential sensing. The design has an added benefit of high output, since it is essentially two elements occupying the same space that one would under normal circumstances.
One of the difficulties in making coupled element sensors is that for high linear densities, gap lengths must be made very small, and therefore the films making up the MR sensors must be separated by only a very thin insulator. Furthermore, because of the stacked nature of the design, all interconnection metallization must traverse steps where one material ends, and an insulating material tends to thin down.
Additionally, with narrow track widths and line widths, any misalignment of one element to the other, or misalignment of the interconnection leads to either element, can cause shorting. Finally, in current designs, the head is finished by placing a closure piece on top of the film stack, such that the pressure from bonding of the closure piece can bring on shorts where alignment is marginal.
In the multitrack environment, yield is of a paramount concern, as shorted tracks cannot be simply culled out. Instead, if any one sensor is defective, the entire array must be failed. Therefore, there exist a need for a multitrack coupled element read head design and a method for manufacturing such a read head that eliminates any avenues of shorting or discontinuities.

Multitrack coupled element read head with support structure to eliminate shorting and method for manufacturing same


A magnetic recording medium, includes a substrate; a magnetic layer; an underlayer between the substrate and the magnetic layer, the underlayer including a non-magnetic powder and a binding agent; and a back layer. In a case where wmax and wmin are respectively maximum and minimum of average values of width of the magnetic recording medium measured under four environments whose temperature and relative humidity are (10° C., 10%), (10° C., 80%), (29° C., 80%), and (45° C., 10%), respectively, wmax and wmin satisfy a relation of (wmax−wmin)/wmin≤400 [ppm]. The substrate includes polyester. A squareness ratio in a vertical direction of the magnetic medium is 65% or more, and an average thickness of the magnetic recording medium is 5.6 μm or less.

Tape-type magnetic recording media have been widely used as data storage for computers. Such magnetic recording media have been studied for various characteristics improvements, one of which is off-track characteristics improvement.
PTL 1 describes a tape-type magnetic recording medium in which environmentally-induced width-direction size changes are reduced to ensure stable recording and reproducing characteristics with reduced off-track. Furthermore, PTL 1 describes reduction of a width-direction size change amount with respect to a longitudinal-direction tension change.


A system, method, and enclosure for testing wireless devices. The enclosure includes a number of walls enclosing a testing space. The enclosure also includes a sliding cover secured between the two of the number of walls. The enclosure also includes one or more radio frequency layers disposed on the number of walls and the sliding cover.

The consumption of and development of media communications has grown nearly exponentially in recent years. The growth is fueled by larger networks with more reliable protocols and better communications hardware available to both service providers and consumers. In particular, new set-top boxes, gaming devices, televisions, and network devices are constantly being released.
Network devices are required to go through various forms of testing to ensure compliance with communications and formatting standards, and technical requirements set by standard setting organizations (SSOs), governments, industry groups, companies, service providers, or other applicable parties. Performing tests, evaluation and analysis for a single network device, such as a residential gateway or modems, may be time consuming and difficult and is complicated when performing tests for multiple network devices.

Wireless enclosure for testing electronic devices


The invention provides an immunoglobulin G Fc region binding polypeptide, which polypeptide comprises an immunoglobulin G Fc region binding motif, BM, consisting of an amino acid sequence selected from: i) EQQX4AFYEILHLPNLTEX18QX20X21AFIX25X26LRX29, (SEQ ID NO:12) and ii) an amino acid sequence which has at least 85% identity to the sequence defined in i). Also provided are methods of isolation or production of IgG Fc-containing molecules.

In the industrial production of monoclonal antibodies and Fc fusion proteins, purification is frequently carried out using affinity chromatography. Protein A from Staphylococcus aureus has long been used as affinity ligand in such applications, due to the native affinity of Protein A for the Fc portion of IgG. Protein A in its entirety, as well as the individual Fc-binding domains thereof, have subsequently served as starting points for the rational design of engineered affinity ligands with improved properties. Despite the comparable success of currently used IgG Fc affinity ligands, there is a continued need for improvement. The continued provision of agents having an affinity for IgG Fc that is comparable with, or higher than, that exhibited by Protein A remains a matter of substantial interest. For example, Protein A affinity chromatography typically uses low pH conditions, which may lead to loss of yield due to the sensitivity of several antibodies and Fc fusion proteins to low pH conditions. The provision of new IgG Fc-binding agents that allow elution at a higher pH as compared to Protein A during affinity chromatography would therefore be beneficial.
It is an object of the invention to provide new IgG Fc-binding agents, that could for example be used in the production of antibodies or Fc fusion proteins, e.g. for affinity separation and/or purification.