A guide wire that is capable of sensing pressure at its distal. The guide wire contains a non-compliant path from its distal end to a pressure transducer, at its proximal end, that has a maximum signal rating of 10-1,000 times the nominal signal.

Angioplasty procedures have gained wide acceptance in recent years as efficient and effective methods for treating types of vascular disease. In particular, angioplasty is widely used for opening stenoses in the coronary arteries although it is also used for the treatment of stenoses in other parts of the vascular system.
The most widely used form of angioplasty makes use of a dilation catheter which is threaded over a guidewire and has an inflatable balloon at its distal end. Inflation of the balloon at the site of the occlusion causes a widening of the lumen to reestablish an acceptable blood flow through the lumen.
Often it is desirable to determine the severity of the occlusion in order to properly choose a dilation catheter. Various invasive techniques have been used to determine the severity of the occlusion. One way of determining the severity of the occlusion is to measure pressure both proximal to and distal of the stenoses. Devices that are used for this purpose include catheter-like members with some type of pressure sensing device incorporated therein. For devices of the single pressure sensor type, movement of the catheter-like member must be accomplished to measure pressure at different locations. Whereas, devices with more than one pressure sensor can measure pressure simultaneously at several points.
One known device measures the pressure as a function of the deflection of a diaphragm located at the distal end of the catheter. Positioning the sensing part of the sensing device at the distal end of the catheter requires the sensing device to be made extremely small. Otherwise, the sensing device will impede blood flow and effect the pressure reading. In addition, catheters with the sensing device at the distal end do not allow for reuse of the expensive sensing device.
Another known device, called a fluid filled catheter-manometer, connects a sensing device to the proximal end of the catheter. A catheter-manometer uses a fluid column that can communicate pressure changes at the distal end of the device to a transducer located at the proximal end of the device. A catheter-manometer has the advantage of having a reusable sensor and is therefore less expensive. Unfortunately, catheter-manometers have heretofore not been accurate at physiologic frequencies. The required bandwidth, or flat frequency response, for accurate physiologic pressure measurement in the heart about 30 hertz. Large catheter-manometers (8 Fr) are typically only 20 hertz and small catheter-manometers, like guidewire systems (0.014"), may be less than 1 hertz. Further the bandwidth of catheter tip pressure devices may be several kilohertz. Clearly, prior art catheter-manometer systems have not had the required bandwidth or frequency response for accurate physiologic pressure measurement.
There are several factors causing prior art catheter-manometer systems to not have the required bandwidth or frequency response for accurate physiologic pressure measurement. One factor is that a relatively large amount of fluid mass must be moved with a relatively small amount of pressure. The movement of the mass is described by Newton's second law of motion: F=Ma, where the force F is a combination of a displacing force and restoring force. The displacing force is the pressure input and the restoring force is the natural rebound response of the system. Therefore, the density of the fluid becomes a contributing factor to the frequency response.
Another factor is resistance R. The resistance to flow in a catheter can be described by Poiseuille's equation: R=8.mu.L/.pi.r.sup.4, where r is the internal diameter and L the length of the catheter. In a fluid-filled manometer system the fluid is typically not flowing, but rather is oscillating, as originally described by Lambossy (1952). Thus, in a fluid filled manometer, the damping (resistance) varies as the square-root of the length and inversely as the cube of the radius as follows: ##EQU1##
Yet another factor is the compliance or elasticity E of the system. The catheter combined with the pressure transducer form an elastic volume in which the response is described by: ##EQU2##
Thus, the natural frequency response of the fluid filled catheter manometer will be determined by stiffness or compliance of all components in the system. Prior art systems are composed of the catheter, a manifold, tubing, fittings, and a transducer. Catheters are made of combinations of metals and plastics which may, depending on construction, have compliance which absorbs some of the pressure change. Manifolds are made of hard plastics which typically do not elastically deform. However, the tubing used is elastomeric, as are the gaskets used with the fittings. These elastomers are very flexible and will dampen pressure change in the fluid passing through them as described above.
Finally, the responsiveness of the pressure transducer within the sensing device is also a factor. As previously described, all components in the system contribute to the elasticity E, and thus the frequency response. In order to have adequate sensitivity in the physiologic pressure range (about 0-5 Psi), blood pressure transducers have traditionally been designed for full scale signal output (maximum pressure rating) at applied pressures of 300 mmHg or 5 Psi. The very flexible diaphragms used to create adequate low pressure sensitivity increases the elasticity of the system, and thus, lowers the frequency response. All of these factors have thus far contributed to making devices of this type less accurate in reproducing the exact physiologic signals and produce pressure readings which are, in some devices, only an average of a patient's blood pressure over time.
In addition to procedures like angioplasty where it is desirable to know the pressure at a given point at a given time, it is also highly desirable to know the pressure wave form for places within the heart and various vessels. Standard pressure wave forms have been documented for the healthy vasculature. A, variety of other wave forms have also been documented to correspond to particular maladies. Therefor, a device which was responsive enough to measure wave forms within the heart chambers would also be useful.
Tremulis discloses in U.S. Pat. No. 4,953,553, U.S. Pat. No. 4,964,409, and U.S. Pat. No. 5,050,606 guide wires capable of sensing pressure via a proximal sensing device. This device has the added advantage of being usable as a guidewire. Guide wires are commonly used during angioplasty as well as many other procedures. However, this device is not as sensitive as distal sensing devices because of all of the factors previously described nor does it have enough frequency response to measure accurate wave forms.
Accordingly, it is desirable to provide a device that can be used as a guidewire and simultaneously be used to measure pressure at specific points without the added expense of distal sensors and without the pressure change insensitivity of prior art proximal sensing devices. Further it would be highly desirable to combine this device with a device that could produce a true wave form of the changes in blood pressure as well as an average blood pressure measurement.


A pick attempt of a media sheet from a media tray is initiated by rotating a pick roller a number of rotations that is set to greater than one in response to the sheet having been designated as a special media sheet type and that is set to one in response to the sheet not having been so designated. In response to a pick sensor detecting the sheet after the pick attempt has been attempted, a turn roller is rotated to advance the sheet to a print engine, and while the turn roller is rotating, the pick roller is rotated to assist advancement of the media sheet. A controller manages per-sheet and per-tray pick attempt counters while the sheet is individually attempted to be picked and advanced, using the counters to determine whether to initiate another pick attempt of the sheet when a current pick attempt has failed.

Printing devices include devices like multi-function devices (MFDs) or all-in-one (AIO) devices that can both form images on media as well as perform other functions such as scanning, as well as devices like printers that can just form images on media. Different technologies that printing devices employ to form images on media like paper include inkjet printing technologies and laser printing technologies. Some types of printing devices utilize media trays, which are loaded with media sheets and then inserted into the devices. A printing device then individually "picks" the media sheets from the tray and advances them to a print engine for forming images thereon.

Hewlett-Packard Development Company, L.P.


A pair of similar U-section clips each have a pair of legs secured to a respective belt end and a plurality of spaced knuckles that are interleaved to form a transversely extending passage. A coupling rod extending through the passage and interconnecting the clips has a relatively soft and bendable core pin and a helicoidal wrap of a wear-resistant hard material surrounding and directly engaging the pin and engaging the clip knuckles. The wrap can be made of an austenitic manganese steel and the pin can be a length of highly flexible steel cable.

A connector for a flat belt comprises at least one pair of U-section end clips interconnected by a transverse coupling pin or rod. Each such clip typically is made of metal and has a pair of legs adapted to embrace the respective belt end and a bight portion interconnecting the outer ends of the legs. Each leg in turn is formed with at least two throughgoing holes that align with the holes of the leg on the opposite face of the belt, and staples are driven through the registering holes from one side of the belt and are crimped over on the other side. The bight portion is formed as at least one loop or knuckle and the loops of the clip or clips of one belt end are interleaved with those of the other belt end and the coupling pin passes through the resultant passage to couple the two belt ends together.
As a result of tensile, bending and frictional forces acting on the curved bight portions and the coupling rod, the bight portions and the rod are subjected to extremely heavy wear. The wear results eventually in damage to the rod and bight portions and consequently to the entire conveyor-belt connector. A further result of this damage is expensive repair work and breaks in operation.
For this reason, coupling rods have been developed containing a bunched steel wire core and a helically wound steel jacket. Other embodiments do without the steel jacket and consist of twisted bunches of steel wire. Attempts have even been made to use bunches of glass and carbon fibers, but have not proven effective. The bight portions of belt-connector clips are regularly doubled, either by displacement of ductile material or by crimping over. This procedure, however, does not eliminate wear, and at best delays the damage resulting from wear.
Further a coupling pin for belt connectors for inter-connecting the ends of conveyor belts is known from German 4,416,079 of W. Herold wherein core elements of a defined length are disposed inside at least one outer element. In this known coupling pin the outer element is in the form of a relatively soft material which distorts in use while the core elements each have a length sufficient to extend through more than two hinge loops of the connectors. The outer element serves only to produce the pin-like structure and for the introduction of the inner elements into the hinge loop zone of the connectors.
However, the outer element cannot withstand the stresses occurring because it is made of a relatively soft material which deforms in operation. Instead, the stresses are intended to be transmitted solely by the core elements. This cannot happen, however, simply because the considerable wear between the hinge knuckles and the coupling pin is bound to lead to early damage and finally destruction of the soft outer element. This leads to loosening of the inner core elements.


A heated apparatus, positioned in the X, Y, and Z directions, for forming fine lines of molten material on a substrate. The apparatus includes a pen having a refractory tip wetted with material in a molten state. The tip is attached to a V-shaped heater to form a heater assembly. The ends of the V-shaped heater are welded to the pins of a three lead TO-5 package base. The pen is then mounted on an apparatus adapted to direct writing. To that end, the pen is attached to a supporting device capable of moving in the X, Y, and Z directions. When the welding point of the tip/heater assembly reaches the melting point of the material to be deposited, it is dipped in a crucible containing the material in a molten state. The welding point nucleates a minute drop of the molten material, forming a reservoir. A thin film of material flows from the reservoir and wets the tip, which is then brought in contact with the substrate upon which the desired pattern is to be formed.

The use of a thin pointed tip to form ultra-fine metal lines have found wide application in VLSI semiconductor integrated circuit (IC) chips.
Conventional methods have been used thus far to form patterns of conductive material on a substrate in connection with the fabrication or repair of semiconductor IC chips. Indeed, it is often necessary to form conductive patterns with superior resolution on a semiconductor structure during the various phases of the chip fabrication. Such patterns provide the necessary contacts, electrodes, and conductors (or lines) that are required to meet the various connection/interconnection needs. Conductive materials include doped polysilicon, low melting point metals such as aluminum (Al), metal alloys such as aluminum-silicon (Al-Si), gold-silicon (Au-Si), and refractory metals such as tungsten (W), tantalum (Ta), and chromium (Cr). However, low melting point metals and metal alloys are by far, the most ubiquitous materials used throughout the semiconductor industry. typical method of forming metal patterns is to combine lithography and deposition techniques. E-beam evaporation or sputtering deposition and lift-off lithography are the standard techniques used to date. Typically, a thick photoresist layer is first formed onto a semiconductor structure. The resist is then exposed using a photomask. This exposure serves to trace a predetermined pattern in the resist inducing localized chemical reactions in the exposed regions. The resist layer is then developed in a suitable solvent and the exposed regions (in case of a positive resist) are removed. Next, a metal layer is blanket sputtered onto the structure and the remaining portions of the resist layer are removed, leaving the desired complementary metal pattern on the surface of the structure.
The above described method is extensively used in the industrial production of semiconductor IC chips. However, it has some significant limitations for customizing and repairing chips. The conventional method described above, however, is still used in customizing (or personalizing) CMOS gate arrays. For instance, eight out of the twelve photomasks of a typical CMOS process are generic. However, there is a strong demand for fast turn-around of prototypes, small production volumes and significant engineering support in the chip design and evaluation stages, all of which put pressure on gate array manufacturers. Obviously, lithography is hard pressed to cope with the short delays demanded by the marketplace to produce a customized chip or to repair a defective chip. As a result, the above described method cannot be used for instant customizing of ASICs (Application Specific Integrated Circuits) or for chip repair.
Other conventional methods have been successfully used to form patterns of an opaque material in connection with the manufacture of photomasks, but they usually use other lithographic techniques. By way of example, according to a typical fabricating photomask process, a metal (usually chromium) coated transparent glass plate is first covered with a radiation sensitive resist layer. The resist is exposed using a well collimated E-beam and developed. The remaining patterned resist layer acts as a protective layer to the underlying metal coating. In turn, the unprotected metal is etched up to the glass plate. Finally, the remaining resist layer is removed, leaving opaque zones of metal on the glass plate surface. As known to those skilled in the art, photomasks are currently used in the lithographic steps in the course of IC chip manufacture. As far as the fabrication of photomasks is concerned, this lithographic process tends to develop two groups of defects: unwanted portions are left unremoved (so-called black-spot defects) and portions needed are unintentionally etched away (so-called clear or white-spots defects). This method is extensively used in the industrial production of photomasks, but it is clearly not applicable for repair purposes. Using an additional lithographic step to repair a defective mask by performing localized metal deposition thereon makes little or no sense, and more often than not, a new mask is produced.
In summary, lithographic based methods are well adapted to mass producing semiconductor IC chips or photomasks, but are not suited for applications involving small volume production of IC chips, customizing and repair, and mask repair. In addition, lithography has an inherent high capital and operating cost, due to the sophisticated E-beam or photoaligner apparatus that are required to trace a pattern. As a result, alternate methods eliminating lithographic steps during prototyping and engineering have been sought to improve flexibility and save time and expense.
Two recent techniques, known under the name of Focused Ion Beam (FIB) and its variant Focused Ion Beam-Chemical Vapor Deposition (FIB-CVD), obviate most of the drawbacks of above the conventional lithographic processes described. In particular, they are adaptable to the ablation of metal fine lines and to the deposition of metal fine lines, respectively. Consequently, they have found a wide application in various fields of the semiconductor technology, particularly, in the repair of IC chips and masks as well as other related fields, such as process monitoring, defect/failure analysis, device evaluation, sample preparation for microscopy and micro-analysis, and the like. To date, the FIB-CVD is considered the most promising deposition technique, and it is on the verge of significant and rapid advances in the semiconductor industry.
In a standard configuration adapted to metal deposition, a FIB-CVD station is housed within a column-shaped vacuum chamber that includes an X-Y stage capable of controlled movements in the X-Y directions of an horizontal plane. The column encloses a high brightness liquid metal ion source which consists of a sharp needle wetted by a film of the metal, typically gallium (Ga) in its molten state. The molten metal travels by capillary action to the needle of the ion source where it is ionized. An extraction electrode having a difference voltage potential with the ion source extracts the ion beam from the source. There is produced a beam of charged particles, i.e. ions, that appears to emanate from a point. A E.times.B mass separator can be used to select only the desired ion species and deflect the undesired species out of the beam (as for instance, when metal alloy is used). A series of lenses is placed on the path of the ion beam to provide focus. Next, a beam deflector is used to scan the beam over the substrate. The substrate which forms the target for the FIB is generally placed on top of a heating element affixed on the X-Y stage. A thermo-couple sensor senses the substrate temperature, thereby providing control to the heating element. The substrate is heated to a temperature sufficiently high to support growth of the desired material. The compound which includes the material to be deposited on the substrate is held in a gaseous state within a reservoir. A gaseous organometallic compound such as tungsten carbonyl is typically used as a working gas. A valve controls the flow of the working gas from the reservoir through a nozzle which terminates in close proximity of the substrate, and directs a flow of gas onto the desired portion thereof. A few atomic layers of the working gas are adsorbed by the substrate surface.
The focused ion beam generated by the liquid metal ion source is projected onto the substrate and scanned thereon by the beam deflector so that the working gas is decomposed. The tungsten film is only formed in an area where the ion beam impinges on the gas. Metal fine lines are formed continuously. The focused ion beam is scanned along a predetermined locus, corresponding to a desired circuit connection line (preferably in multiple scans) to grow the metal until the desired thickness is obtained. This is clearly a lengthy process, and since the ion beam intensity can only be increased to a limited extent, it is rather difficult to trace relatively long lines, e.g., 1 mm, unless one is willing to accept an appreciable loss in terms of resolution. The secondary electrons emitted from the surface of the substrate are detected, amplified and processed for final display on an appropriate display as a high resolution SIM (Scanning Ion Microscope) image. Since a control unit drives the X-Y stage, it is possible to observe the SIM image of any desired portion of the substrate--a significant advantage for chip or mask repair.
The FIB-CVD station previously described is particularly well suited to perform additive processes, such as deposition of metals. However, it suffices not to use the working gas to transform the station into an equipment that is adapted for subtractive operations, such as etching (reverse sputtering), hole drilling, wire cutting, etc. As a result, the FIB and FIB-CVD techniques can lead to various and interesting applications. By way of example, although the FIB-CVD technique has limited use in the manufacture of IC chips to form electrical connections (wherein active and passive devices have been previously formed by appropriate lithography and implantation steps), it is widely used for repairing such chips. If there is an open in a metal interconnect line that was previously deposited (as a result of a manufacturing defect), the line can be repaired by scanning the open area to deposit new metal and fill the open as described above.
According to the FIB-CVD technique, no limitations exist in the nature of metals to be deposited. For instance, refractory metals, including tungsten, which have a high melting point temperature (of about 3370.degree. C.), are easily deposited on an insulating or a silicon substrate, when using metal carbonyl compounds. However, deposition of such refractory metals is more difficult when GaAs is the semiconductor material, because GaAs is not easily oxidized and metallized. This disadvantage has severely hampered the development of this technology to this date. For example, refractory metal gate electrodes are currently applied to GaAs MESFET devices by sputtering and E-beam evaporation. In both of these processes, damage can occur to the GaAs surface. Sputtering causes impact damage, and E-beam evaporation results in dissociation of GaAs. The preferred method of depositing refractory metals, is a variant of the FIB-CVD technique described above, the so-called photodeposition. As disclosed, for instance, in U.S. Pat. No. 4,451,503 assigned to IBM, photodeposition uses ultraviolet radiation of wavelengths less than 200 nm to photodecompose the gaseous metal carbonyl compound in the vicinity of the GaAs wafer.
For similar reasons, the FIB/FIB-CVD techniques are not well adapted to the manufacture of masks, to form opaque chromium patterns on a glass plate. They have found wider applications in repairing masks, either by depositing new metal on white spot defects that develop in the mask pattern or by ablation of undesired metal portions thereof. Again, in this instance, the SIM image is helpful in pinpointing the exact location of the mask defects to be repaired. Moreover, as mentioned above, it is rather simple to transform the FIB-CVD station into a FIB station adapted to eliminate by ablation the undesired shorts at the surface of the IC chips.
In summary, the FIB/FIB-CVD techniques have numerous applications, including the in-situ formation of metal patterns to be used as circuit connections during the repair or personalization of an IC chip, as well as for the formation of additional opaque patterns during the repair of photomasks. Unfortunately, in particular, the FIB-CVD pattern forming process has some significant drawbacks, as will be explained hereinafter.
In order to obtain good resolution, a low ion beam intensity is required, which in turn implies a ion beam having a very small size diameter size, e.g. 30-40 nm. To create a 2 .mu.m.times.1 .mu.m conductor thus requires multiple scans. The requirement of a relatively high ion dose and an ion beam that must be left on the substrate during the entire deposition process, multiple scans of the line to be deposited significantly slow down the speed at which lines are written. Furthermore, the rate of line (or pattern) build-up to a desired thickness is very low.
Since a chemical deposition is used during the manufacturing process, the resulting resolution is naturally poor. Any attempt to raise the build-up rate mentioned above requires increasing the ion beam intensity, thereby causing the ion beam to become unfocused. This, in turn, results in spreading away the sputtered material excessively.
High resistivity conductors can also be obtained. Impurities, typically, carbon and gallium atoms, are implanted during the pattern formation. When ultra-fine lines are required, the impurity level of the deposited lines may be high, i.e., in excess of 25%, thereby resulting in a sheet resistivity which is much higher than desired. As a result, for the reasons stated, the FIB-CVD technique is limited to the deposition of relatively short lines. Long lines are too resistive and also require too much time.
Organometallic products, such as tungsten carbonyl W(CO)G, molybdenum carbonyl Mo(CO)G, chromium carbonyl (Cr(CO)G, and the like, are extensively used in FIB-CVD but can lead to the formation of dangerous and toxic compounds.
A conventional FIB-CVD station is relatively complicated and expensive and has a high operating cost. It further requires operating in a vacuum environment. Generally, the FIB-CVD station is placed in the vacuum chamber of a scanning electron microscope (SEM).
The FIB-CVD process requires relatively high dosage, in the order of 10.sup.17 ions/cm.sup.2 or greater to deposit patterns or lines that are only a few hundred nanometers thick. The use of such high dosage can result in damage of the wafer surface.
The deposition step requires high temperatures (e.g., 300.degree. C.) to heat the substrate. Should the substrate be a semiconductor wafer, the presence of elevated temperature can result in detrimental phenomenon within the devices integrated therein which could alter the electrical characteristics of the device.
High aspect ratios are achieved with the FIB-CVD technique. A common problem is attributable to the sharp step of conductors that are formed, while in most instances, conductors having tapered edges would have been preferred to avoid the step coverage effect with its well known reliability problems. Thus, although ion beams can be focused to below a micron in diameter and thus have the potential for submicron resolution, a practical way to integrate rapid and efficient metal line deposition into an IC chip manufacture and repair process has not been found thus far. As a result, there still remains the pressing need for a new technique that includes a maximum of advantages of the FIC-CVD deposition technique (possibly by introducing functions not performed by the same), while retaining only a minimum of its disadvantages. Moreover, it should also be adapted to provide some of the subtractive features of the FIB technique. Finally, it would be highly desirable to have this technique adapted to the fabrication of IC chips, so that a mask free fabrication of IC chips with no lithography steps could be envisioned. This technique should also be adaptable to customizing and repairing IC chips and masks, as presently FIB-CVD and FIB techniques are capable of achieving.
Accordingly, it is a primary object of the present invention to provide a method and apparatus for depositing materials of either a conductive and non conductive type on a variety of substrates.
It is another object to provide a method and apparatus for the direct writing of a desired conductive pattern on a substrate having either a regular or irregular surface.
It is another object to provide a method and apparatus for depositing a metal pattern on a substrate to form electrical connections at relatively high speed.
It is another object to provide a method and apparatus for depositing a metal pattern on a substrate to form electrical connections having precise dimensions.
It is another object to provide a method and apparatus for depositing a metal pattern on a substrate to form electrical connections with a resistivity equivalent to the bulk metal.
It is another object to provide a method and apparatus for depositing a metal pattern on a substrate to form electrical connection lines of any desired length and width.
It is another object to provide a method and apparatus for depositing a metal pattern on a substrate that does not use toxic compounds.
It is another object to provide a method and apparatus for depositing a metal pattern on a substrate that requires a relatively inexpensive equipment with a low operating cost.
It is another object to provide a method and apparatus for depositing a metal pattern on a substrate that is capable to fill via-holes formed in the substrate.
It is still another object to provide a method and apparatus for depositing a metal pattern on a substrate without damaging the surface of the substrate.
It is still another object to provide a method and apparatus for depositing a metal pattern on a substrate that can be normally performed at room temperature.
It is still another object to provide a method and apparatus for depositing a metal pattern on an insulating substrate, whose lines have tapered edges and rounded corners for improved reliability.
It is still another further object to provide a method and apparatus for depositing a pattern of a refractory metal on a GaAs substrate.
It is still another further object to provide a method and apparatus normally constructed for depositing conductive and non conductive materials on a substrate that can be easily adapted to a subtractive process, such as scribing and electroerosion.
It is still another further object to provide a method and apparatus for depositing successive metal and insulator patterns on a substrate that could lead to a totally mask-free fabrication of IC chips.
It is still another further object to provide a method and apparatus for depositing a metal pattern on a substrate that is adapted to the personalization and repair of IC chips and photomasks.
These and other objects will be accomplished by the method and apparatus of the present invention by directly writing a desired pattern of a given material on a substrate. It is based on the use of a pen or writing head, preferably consisting of a refractory tip wetted in material in a molten state. The tip is formed by a small wire, typically of refractory metal such as tungsten, that has been electrolytically sharpened and roughened. The tip is attached, preferably by micro welding, to the top of a heater, which typically consists of a V-shaped piece of the same tungsten wire. Each end of the V-shaped heater is welded to a pin that emerges from an insulating base support, e.g., a 3-lead TO-5 package, with three pins partially casted therein. The pen is incorporated into an apparatus adapted for direct writing. The tip is attached to a supporting device, preferably adapted to move along the Z-axis, while the substrate moves on an X-Y stage, for X, Y, and Z relative movements therebetween. The two pins of the pen are connected to a power supply to resistively heat the heater. When the welding point of the tip/heater assembly reaches the melting point of the material to be deposited, it is dipped in a crucible containing material in the molten state. The welding point nucleates a minute drop of liquid material and forms a spatial reservoir in the absence of any container. A thin film of the liquid material flows from the reservoir and wets the tip surface. Finally, the wetted tip is gently brought into contact with the substrate and deposition of the material takes place. Physical contact between the tip apex and the substrate surface is not required, which helps limit the wear of the tip. Preferably, the tip/heater assembly is vibrated to facilitate deposition of the material. Alternate configurations of the tip may be used to create different patterns. For instance, ultra-fine lines of metal can be formed to define the electrical connections of an IC chip, or larger zones of opaque material in the repair of a mask.
In essence, the deposition method of the present invention consists in the direct writing of a material on a substrate using a tip wetted in the material in a molten state. These materials can either be of a conductive type including standard metals (Al), metal alloys (Al-Si, Au-Si, . . . ), or refractory metals (Cr, Ta, . . . ) or of a nonconductive type, such as organic or non-organic insulators. The substrate may be selected from a variety of supports and may encompass either a planar or non-planar surface. Moreover, with the method and apparatus of the present invention, a mask free manufacture of semiconductor IC chips, and, particularly, of the III-V type, is henceforth possible. The deposition method of the present invention has numerous advantages and applications not only in the semiconductor technology field but in other fields as well.

Heated tool positioned in the X,Y, and 2-directions for depositing fine lines on a substrate

International Business Machines Corporation


Disclosed is a directional coupler including a broadside coupled line 1031 provided with a main signal line conductor 1001 and a secondary signal line conductor 1011 arranged in parallel with the main signal line conductor 1001, and an offset broadside coupled line 1032 provided with a main signal line conductor 1002 having an end portion connected to an end portion of the main signal line conductor 1001 and a second secondary signal line conductor 1012 having an end portion connected to an end portion of the secondary signal line conductor 1011, and arranged in parallel with the main signal line conductor 1002, in which a coupled line impedance in the broadside coupled line 1031 is lower than a terminal impedance and a coupled line impedance in the offset broadside coupled line 1032 is higher than the terminal impedance.

1. Field of the Invention
The present invention relates to a directional coupler used in a microwave band or the like.
2. Description of Related Art
A directional coupler is widely used in order to carry out monitoring of electric power. As a directional coupler, there is a directional coupler having a structure of arranging two lines in a vertical direction (for example, refer to the following nonpatent reference 1). Because two lines are thus arranged in a vertical direction, coupling (broadside coupling) occurs electrically. As a result, a directional coupler can be implemented.


The present invention relates to a method for screening drugs for use in treating hypertension using the tubular renin-angiotensinogen system identified by the present invention. The invention further relates to a method to diagnose sodium status and sensitivity in an individual by measuring urinary angiotensinogen or angiotensin-I.

The present invention relates to a method for screening drugs for use in treating hypertension using the tubular renin-angiotensinogen system identified by the present invention. The invention further relates to a method to diagnose sodium status in an individual by measuring urinary angiotensinogen, angiotensin-I, des-AI-angiotensinogen or renin.
The publications and other materials used herein to illuminate the background of the invention, and in particular, cases to provide additional details respecting the practice, are incorporated by reference, and for convenience are referenced in the following text by author and date and are listed alphabetically by author in the appended list of references.
The following abbreviations are used herein: A-I-angiotensin-I; A-II-angiotensin-II; ACE-angiotensin converting enzyme; AGTxe2x80x94angiotensinogen gene; ANG or Angxe2x80x94angiotensinogen protein; -6(A)/-6(G)xe2x80x94promoter polymorphism at position -6; CCDxe2x80x94cortical collecting duct; CNTxe2x80x94cortical connecting tubule; DCTxe2x80x94distal convoluted tubule; ICxe2x80x94intercalated cells; JGAxe2x80x94juxtaglomerular apparatus; PCRxe2x80x94polymerase chain reaction; RASxe2x80x94renin-angiotensin system; RT-PCRxe2x80x94reverse transcriptase polymerase chain reaction; and HPLCxe2x80x94high pressure liquid chromatography.
Blood pressure control is intrinsically linked to fluid volume balance and electrolyte homeostasis. Regulation of plasma volume in response to variation in dietary sodium (1) is primarily controlled by the renin-angiotensin system (RAS) and its main effector angiotensin-II (A-II); this peptide hormone is released from angiotensinogen (Ang) by two cleavage steps involving renin and angiotensin-converting enzyme (ACE) (2).
The short-term effects of A-II are better understood than its long-term effects. Acute depletion of body fluid volume triggers a vasoconstrictor response mediated by the circulating renin-angiotensin system (RAS), involving renin secreted by the juxtaglomerular apparatus (JGA) in the kidney, Ang from liver, and ACE present in the luminal cell membrane of capillary endothelium.
Sustained low-dose infusion of A-II leads to progressive, long-term elevation of arterial pressure due to cumulative sodium retention primarily mediated by direct intrarenal A-II effects 1. A-II has been detected in proximal tubular luminal fluid at high concentrations (3, 4). In contrast to plasma renin (36-40 kDa), Ang (61-65 kDa) is not filtered through the glomerular basement membrane. Detection of abundant angiotensinogen mRNA in proximal tubule epithelium (5-7), strongly suggests local generation of A-II at this site by an as yet unspecified mechanism. Renin mRNA can be detected in proximal tubule only by application of the very sensitive technique of RT-PCR (8). Exogenous A-II stimulates the luminal sodium-hydrogen exchanger present in the proximal tubule cells (9, 10) and also stimulates epithelial sodium channels and possibly other transporters in the distal segments of nephron (11-14).
Fundamental questions remain unanswered, however. If intrarenal A-II directly affects sodium reabsorption, where is it generated, and by what mechanism? How is this mechanism regulated in response to sodium? At what sites does A-II impact on sodium transport along the nephron? What is the mechanism for coordinated regulation of sodium uptake in proximal and distal segments of the nephron? Can it allow for a decoupling of sodium reabsorption and potassium excretion in the distal tubule?
It is desired to address these questions and to elucidate answers which can be used for screening drugs and diagnosing sodium status of an individual.
In accordance with the present invention, it is shown that proximal tubule cells cultured as a polarized monolayer secrete Ang at their apical side, and that Ang transits through the entire nephron as it can be measured in final urine. Furthermore, it is shown that renin, in addition to being filtered, is expressed in a specific segment of the nephron, the connecting tubule. Furthermore, angiotensinogen expression in proximal tubules and renin expression in connecting segments (distal arcades) is an inverse function of dietary sodium.
The data disclosed herein suggest that filtered renin, Ang secreted into proximal tubule, and renin in connecting tubule, together with luminal angiotensin-converting enzyme (ACE) and A-II receptors, previously demonstrated in the luminal fluid and the apical cellular membranes of proximal tubules and collecting ducts (15, 16), define a tubular RAS involved in the control of sodium reabsorption as a function of dietary salt. This tubular RAS could contribute to body fluid control and blood pressure regulation. Furthermore, genetic differences in the angiotensinogen gene (17, 18) may influence susceptibility to essential hypertension through their impact on this tubular system.
Thus, the present invention relates to a method for screening drugs for use in treating hypertension using the tubular renin-angiotensinogen system identified by the present invention. The invention further relates to a method to diagnosis sodium status in an individual by measuring urinary angiotensinogen, angiotensin-I, des-AI-angiotensinogen or renin.
It has been discovered that angiotensinogen, its enzyme catalyzed products or renin excreted in urine vary with changes in dietary sodium. Thus, the sodium status of an individual is diagnosed by determining the amount of angiotensinogen or its enzyme catalyzed products or renin in the urine of the individual and comparing the determined amount with normal values. A finding of elevated levels of these compounds indicates high sodium. An individual""s sodium sensitivity can also be determined by determining the amounts of these compounds in urine. Levels of these compounds are determined using conventional techniques, and any appropriate method is suitable for use. If the levels are elevated in an individual under a high salt diet compared to reference values, the individual is sensitive to salt.
It has also been found that the expression of angiotensinogen and renin is regulated at specific sites along the kidney. This finding identifies new therapeutic targets for the blood pressure control and provides the basis for a method to screen drugs for use in treating hypertension. According to the present invention, drug candidates for treating hypertension are screened using the tubular renin-angiotensin system by testing the effects of drug candidates at the proximal and/or distal tubule.

Drug screening and diagnosis based on paracrine tubular renin-angiotensin system


A method of making a fault-tolerant memory device employing a variable domain redundancy replacement (VDRR) arrangement is described. The method includes the steps of: subdividing the memory into a plurality of primary memory arrays; defining a plurality of domains, at least one of the domains having at least a portion common to another domain to form an overlapped domain area, and wherein at least one of the domains overlaps portions of at least two of the primary arrays; allocating redundancy means to each of the domains to replace faults contained within each of the domains; and replacing at least one of the faults within one of the domains with the redundancy means coupled to the one domain, and at least one other fault of the one domain is replaced by the redundancy means coupled to another of the domains, if the at least one other fault is positioned within the overlapped domain area. Each redundancy unit supporting the primary memory arrays includes a plurality of redundant elements. Unlike the conventional fixed domain redundancy replacement scheme, redundancy units are assigned to at least two variable domains, wherein at least a portion of the domain is common to that of another domain. VDRR makes it possible to choose the most effective domain, and in particular, a smaller domain for repairing a random fault or a larger domain for repairing a clustered faults.

CMOS technology has evolved such that the computer market has rapidly opened to a wide range of consumers. Today multi-media applications require at least an 8Mb and preferably even a 16Mb memory, which increases the relative cost of the memory system within a computer. In the near future, it is likely that 32Mb and 64Mb computers will become commonplace, which suggests a potential demand for 256Mb DRAMs (Dynamic Random Access Memory) and beyond. Still in the development stage, DRAMs in the Gigabit range are already under way, which necessitate the introduction of new techniques that guarantee the reliability of the product notwithstanding the added complexity to the design and manufacture of such memory devices. In view of the huge array size and lithographic difficulties that ensue, it is more important than ever to increase the chip yield. Process engineers are constantly attempting to reduce and ultimately, eliminate or mask defects. Faults that inevitably remain in the chip are generally eliminated using special circuit designs, and more specifically redundancy replacement.
The present invention is a novel configuration based on the concept of domains. The domains referred in the present invention are not bound by stringent, well defined boundaries. Certain domains may be large and encompass a plurality of memory arrays; others may be small in size, and encompass only portions of a memory array. Regardless of its size, each domain is provided with a number of redundancy circuits to replace faults located within the domain. By allowing an overlap between domains, it becomes possible to repair faults in a given memory array with any of the redundancy circuits positioned within the common area of the overlapping domains, provided the fault is found in the array being serviced by the two domains. Clearly, if the number of faults exceeds the number of redundancies available in the domain (or domains) servicing that array, the scheme will fail and the memory is not repairable. However, in accordance with the present invention, if all the redundancies within a first domain have been exhausted, unused redundancies present within another domain overlapping the first one are used as a means for repairing the remaining faults that were left out unserviced within the first domain.
Domains may be tailored to any size and may be arranged in any configuration. Domains can overlap each other or stand side by side. An advantage of overlapping domains is that such an architecture allows servicing faults located in areas common to both domains with redundancy elements positioned in either one of the two domains. This advantage is particularly important because repair means available within one domain may be, at a given time, fully exhausted, and the availability of a second, overlapping domain may, thus, be advantageously used to assist the first domain to complete the repair job left undone.
Several domains may be contained within one array or, alternatively, several arrays may be contained within one domain. In this manner, a designer can take greater advantage of a given domain configuration and a choice of sizes to optimize the repairability of the design.
Conventional redundancy configurations typically employ a Fixed Domain Redundancy Replacement (FDRR) architecture, wherein redundancy elements are used to replace defective elements within a fixed size domain for each row and column redundancy.
Various configurations within the FDRR architecture have been successfully implemented over the years. A typical FDRR configuration, commonly used for low density DRAMs is shown in FIG. 1a. Therein are depicted a plurality of redundancy units used for replacing defective elements within the fixed size domain and which are appended to each sub-array comprising the memory. Each redundancy unit (RU) includes a plurality of redundancy elements (REs), (e.g., two RE per RU are illustrated therein), which are used to repair existing faults (labeled X) within the corresponding sub-array. This scheme, known as intra-block replacement, increases the redundancy area overhead described herein after, as the number of sub-arrays increases for high density memories, since each sub-array includes a fixed domain for the replacement, and the domains in different sub-arrays are mutually exclusive of each other. This scheme requires at least one or, preferably, two RUs in each sub-array. Thus, the efficiency of the RUs is rather poor in view of its inflexibility which reduces the chip yield substantially when faults are clustered in a given sub-array. The above-mentioned scheme is described in an article by T. Kirihata et al., entitled "A 14 ns 4Mb DRAM with 300 mW Active Power", published in the IEEE Journal of Solid State Circuits, Vol. 27, pp. 1222-1228, Sept. 1992.
Another FDRR redundancy replacement arrangement, known as a flexible redundancy replacement configuration, is shown in FIG. 1b, wherein a memory is depicted having a single redundancy array as a large fixed domain of RUs to selectively replace failing elements anywhere in the memory. In this configuration, REs within the RU can repair faults (labeled X) located in any sub-array within the memory. The advantage of this arrangement over the previously described intra-block replacement is that one section, namely, the redundancy array, having a certain number of RUs, may advantageously be used to service any number of sub-arrays forming the memory. This results in a substantial saving of area (also referred to as real estate) over the previous scheme, although it requires a substantial amount of additional control circuitry to properly service all the sub-arrays forming the memory.
More details regarding the above described configurations and the various trade-offs may be found in an article by T. Kirihata et al., "A Fault-Tolerant Design for 256Mb DRAMs", published in the Digest of Technical Papers of the 1995 Symposium on VLSI Circuits, pp. 107-108; in an article by T. Sugibayashi et al., "A 30 ns 256Mb DRAM with Multi-divided Array Structure", published in the IEEE Journal of Solid State Circuits, Vol. 28, pp. 1092-1098, Nov. 1993; and in an article by H. L. Kalter et al., "A 50 ns 16Mb DRAM with a 10 ns Data Rate and On-Chip ECC", published in the IEEE Journal of Solid State Circuits, Vol. 25, pp. 1118-1128, Oct. 1990.
In summary, a Fixed Domain Redundancy Replacement (FDRR) arrangement consists of a plurality of fixed-size domains, each of which can be independently used to replace faults contained within that domain. By expanding this concept to a chip, there may be found several domains, each having a fixed size and mutually exclusive of each other, to repair all the faults within the chip.
The FDRR architecture can be used in an intra-block replacement arrangement, wherein small domains make it possible to repair faults with minimum circuitry. However, such an arrangement is ineffective to repair clusters of faults. In the second FDRR arrangement, i.e., the flexible redundancy replacement architecture, large domains typical of such an architecture, provide good repairability of clustered faults. However, the circuit overhead is substantially increased--a significant disadvantage.
Flexible redundancy replacement is very effective in repairing a limited number of faults, especially if these faults affect bit lines, (either single bits or multiple bits); wordlines, (either single words or multiple words), and the like, all of which fall under the category of "hard faults". Yet, flexible redundancy replacement suffers from another distinct drawback in that it requires a significant number of RUs (and corresponding control circuitry) to overcome a second class of faults, known as "retention faults," in which a bit, stored in the capacitor that forms a DRAM cell, fades away over time in a weak cell, thereby producing a fault. This disadvantage is particularly troublesome because the number of retention faults far exceeds the number of hard faults.
Referring back to the hard faults within a memory, defects of this type tend to cluster. Accordingly, the intra-block replacement approach usually fails because of its poor flexibility. Hard faults are typically not too numerous, which can be ideally repaired with less RUs in a large domain. Flexible redundancy replacement is a good approach to repair hard faults, which can be serviced by a single large domain with less RUs. By way of example, if a domain contains four clustered defects, four RUs would be required to replace them in the domain. Designing four RU in each small domain with an intra-block replacement approach would require too much overhead. Even if this overhead would be acceptable, if, for instance, five clustered defects were present, the replacement of defects could potentially fail. In conclusion, increasing the domain size with the flexible redundancy approach is crucial to repair hard faults.
Retention faults, on the other hand, occur randomly throughout the memory, and their number is typically high; yet, there is a distinct advantage in that they occur randomly throughout the chip. For random faults, the intra-block replacement presents less drawbacks, because the faults are statistically distributed in many small sub-arrays. The intra-block replacement can repair a fault with less redundancy circuitry than that required for the flexible redundancy replacement. Clearly, if one RU were designed in each sub-array, with the purpose of detecting randomly occurring retention faults, then such a configuration would be ideal for detecting retention faults, provided at least one fault is present in the sub-array. Retention faults, on the other hand, are difficult to repair with a flexible redundancy replacement approach because of the large number of such faults, which frequently overwhelms the repair circuitry available in the memory device. Repairing too many faults with the flexible redundancy replacement approach is disadvantageous, because the flexibility approach requires an even greater overhead to repair such faults with the available redundancy circuitry.
In view of the foregoing, an important objective of an ideal redundancy configuration is to repair hard faults and retention faults, whether randomly distributed throughout the memory or clustered therein, without introducing an onerous burden caused by a complex redundancy area overhead. Typically, this overhead is divided into: a redundancy element overhead and redundant control circuitry overhead, both of which should be minimized to achieve good repairability and to maintain optimum performance of the memory.
Related redundancy replacement configurations, including some of the categories listed above, are described in the following references:
U.S. Pat. No. 5,491,664 to Phelan, issued Feb. 13, 1996, describes the implementation of a flexible redundancy memory block elements in a divided array architecture scheme. This configuration has both, the memory and redundancy memory blocks, coupled to a read bus to allow the redundancy memory in one memory sub-array to be shared by a second sub-array.
U.S. Pat. No. 5,475,648 to Fujiwara, issued Dec. 12, 1995, in which a memory having a redundancy configuration is described such that when an appropriate address signal agrees with the address of a defective cell, a spare cell provided by the redundant configuration is activated to replace the failing one.
U.S. Pat. No. 5,461,587 to Seung-Cheol Oh, issued Oct. 24, 1995, in which a row redundancy circuit is used in conjunction with two other spare row decoders, wherein by a judicious use of fuse boxes, signals generated by a row redundancy control circuit, make it possible to replace failing rows with spare ones.
U.S. Pat. No. 5,459,690 to Rieger at al., issued Oct. 17, 1995, describes a memory with a redundant arrangement that, in the presence of normal wordlines servicing defective memory cells, enables faulty memory cells to be replaced with redundant cells.
U.S. Pat. No. 5,430,679 to Hiltebeitel et al., issued Jul. 4, 1995, describes a fuse download system for programming decoders for redundancy purposes. The fuse sets can be dynamically assigned to the redundant decoders, allowing a multi-dimensional assignment of faulty rows/columns within the memory.
U.S. Pat. No. 5,295,101 to Stephens, Jr. et al., issued Mar. 15, 1994, describes a two level redundancy arrangement for replacing faulty sub-arrays with appropriate redundancy elements.
Whereas the prior art and previous discussions have been described mainly in terms of DRAMs, practitioners of the art will fully appreciate that the above configurations and/or architectures are equally applicable to other types of memories, such as SRAMs, ROMs, EPROMs, EEPROMs, Flash RAMs, CAMs, and the like.

Method of making a memory device fault tolerant using a variable domain redundancy replacement configuration


According to the present invention there is provided an inhalation device for dispensing medicament comprising a body (150), the body being shaped for receipt of a medicament carrier (286); and an actuator (10) having a mouthpiece (20), the actuator being reversibly movable between a dispensing position and a storage position; wherein the body includes an air channel (253), and the actuator includes an air hole (225) such that the air channel communicates with the air hole when the actuator is in the dispensing position and the air channel and air hole do not communicate when the actuator is in the storage position.

The use of inhalation devices in the administration of medicaments, for example in bronchodilation therapy, is well known. Such devices generally comprise a body or housing within which a medicament container is located. A mouthpiece (or nozzle) is typically provided which communicates with the medicament container to allow passage of medicament from the source to the mouthpiece and thence, to the patient. When the patient breathes to take in the medicament, typically air is allowed to circulate throughout the body of the device to create airflow.
However, there are certain devices where it is advantageous that the volume of the body of the device that is exposed to airflow (and therefore moisture) is reduced. Typically such devices have moisture sensitive components such as medicament (for example dry powder) or electronic or other moisture sensitive equipment.
The applicants have now found that this problem can be salved by employing a device wherein the mouthpiece and the body of the device are separated such that the airflow between these parts is minimized. A specially created air hole in the mouthpiece and air channel in the body allow air to circulate through a part of the body not containing moisture sensitive components. These air holes and air channels are only able to communicate when the device is in a dispensing position. Preferably these air holes and channels are blocked during storage to prevent the entry of contaminants.


Novel organic glass compositions are disclosed which are poled to achieve nonlinear optical properties. Novel compounds useful for making said poled compositions are also disclosed; as are a method and a device for transforming electromagnetic radiation using a nonlinear optical element formed from said compositions; and certain intermediates for making novel compounds.

Second harmonic generation (SHG) involves the conversion of optical waves having an initial wavelength to optical waves having a wavelength which is one-half of the initial wavelength. Common second harmonic generation is achieved by coupling a beam of input waves into a nonlinear optical material wherein wavelength conversion is achieved. Various types of nonlinear optical materials have been reported as suitable for second harmonic generation. Among these are crystalline solids (see, e.g., U.S. Pat. No. 4,909,964), liquid crystals (see, e.g., G. R. Meredith et al., "Characterization of Liquid Crystalline Polymers for Electro-Optic Applications" A.C.S. Symp. Ser., 1983, 233 (Nonlinear Opt. Prop. Org. Polym. Mater.), 109-33), and polymer glasses (see, e.g., K. D. Singer, et al., "Second Harmonic Generation in Poled Polymer Films", Appl. Phys. Lett. 49(5) 1986).
Generally, a glassy material is prepared for nonlinear optical applications such as second harmonic generation by poling, a process wherein the material is cooled while under an electric field from a temperature above its glass transition temperature (Tg) to a temperature below its Tg. Poling allows polar alignment within the glassy material while under an electric field above its Tg. This alignment is locked in by cooling below Tg. Reheating the material above its Tg in the absence of a field generally results in rapid loss of alignment and a corresponding rapid loss of the bulk nonlinear properties desired for applications such as second harmonic generation. The poling of glassy polymers can be restricted by the polymer backbone and/or spacer groups included within the polymer.
Recently certain nonpolymeric organic glasses have been reported in M. Eich et al., "Second Harmonic Generation in Poled Organic Monomeric Glasses", J. Opt. Soc. Am. B. 6(8) pp 1590-1597, 1989, as suitable for second harmonic generation. Reportedly, compared with the case of polymers with attached or doped nonlinear moieties, one can achieve higher densities of nonlinear active groups and hence possibly higher optical nonlinearities in the nonpolymeric organic glasses, since no polymer backbone and spacer groups are incorporated. However, the compounds used, (s)-2-N-.alpha.-(methylbenzylamino)-5-nitropyridine and 2-N-(cyclooctylamino)-5-nitropyridine, have relatively low Tgs (i.e., about 0.degree. C. and -10.degree. C. respectively). Inasmuch as these Tgs are too low for most practical applications, the utility of these materials is considered to be limited.


In one aspect, a composite binder for a battery, including an inorganic particle; a binder polymer; and an organic-inorganic coupling agent, a negative electrode including the composite binder, and a lithium battery including the negative electrode is provided.

1. Field
One or more embodiments relate to a composite binder for a battery, and an anode and a battery including the same.
2. Description of the Related Technology
Lithium batteries have high voltage and high energy density and thus, are used in various applications. For example, electric vehicles (hybrid electric vehicle (HEV) or plug-in hybrid electric vehicle (PHEV)) need to operate at high temperature, need to be charged or discharged with a large amount of electricity, and are used for a long period of time. Accordingly, they require lithium batteries having excellent discharge capacity and lifespan characteristics.
Carbonaceous materials have a porous structure and thus, during charging and discharging, they undergo less volumetric change. However, due to the porous structure of carbon, a battery using such carbonaceous materials has a small capacitance. For example, certain graphite forms having high crystallinity may theoretically have a capacity of 372 mAh/g.
A metal that is alloyable with lithium may be used as a negative active material having higher electric capacitance than the carbonaceous materials. For example, a metal that is alloyable with lithium may be Si, Sn, Al, and the like. However, metal that is alloyable with lithium may easily deteriorate and thus its lifespan characteristics may be poor. For example, Sn particles may be repeatedly aggregated and crushed when charging and discharging are repeatedly performed and thus, Sn particles may be electrically insulated.
Accordingly, there is a need to develop a binder that improves lifespan characteristics of a lithium battery by accepting and/or suppressing a volumetric change of these non-carbonaceous negative active materials.

Composite binder for battery, and anode and battery including the composite binder


A liquid supply assembly is disclosed. The liquid supply assembly may be used in combination with a spraying device or spray gun to apply liquid to a substrate. The liquid supply assembly is particularly suitable for use in systems utilizing pressurized liquid containers.

Various liquid supply assemblies have been described for use with liquid (e.g., paint) spraying devices or spray guns, including those described in International Publication Number WO 98/32539 (Joseph et al.) published on Jul. 30, 1998, U.S. Pat. No. 6,536,687 (Navis et al.), U.S. Pat. No. 6,588,681 (Rothrum et al.), the content of all of which is incorporated herein by reference. The supply assemblies include a number of components such as a mixing cup or container, a collapsible liner, a lid, an adapter for attaching a portion of the lid to a component of a spraying device, and a filter element.
While the prior art discloses various liquid supply assemblies for use in spray devices, many of the liquid supply assemblies are only suitable for relatively low pressure systems, namely, systems using a container pressure of less than about 69.0 kilopascals (kPa) (10 pounds per square inch (psi)). Such low pressure systems have shortcomings including, but not limited to, difficulty spraying highly viscous fluids such as some paints, adhesives, and the like.
There remains a need in the art for liquid supply components and assemblies suitable for use in pressurizable liquid supply assemblies for high pressure applications, namely, systems using a container pressure of greater than about 69.0 kPa (10 psi).


Technology is provided for a connector for use with an M.2 memory module. The connector comprises a connector body including a mounting surface, first and second receptacles oriented perpendicular to the mounting surface, and a plurality of terminals extending through the mounting surface and into the first and second receptacles.

Conventional M.2 connectors have a connector body with a mounting surface that is parallel with the receptacles that receive a storage device. Accordingly, conventional M.2 connectors are mounted on a printed circuit board (PCB) with the receptacles parallel to the printed circuit board. Therefore, a connected storage device lies parallel to the PCB. Thus, the storage device consumes a relatively large portion of the PCB's surface area.
The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claimed embodiments. Further, the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be expanded or reduced to help improve the understanding of the embodiments. Moreover, while the disclosed technology is amenable to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are described in detail below. The intention, however, is not to limit the embodiments described. On the contrary, the embodiments are intended to cover all modifications, equivalents, and alternatives falling within the scope of the embodiments as defined by the appended claims.


A lens barrel assembly of a camera module and a laser apparatus for assembling the lens barrel assembly are provided. The lens barrel assembly of a camera module includes: at least one lens; a barrel provided with a lens exposing hole having a predetermined size which is formed to penetrate a central portion of a closed upper surface of the barrel, wherein the lens is inserted from an lower opening of the barrel toward the lens exposing hole; and a stopping protrusion which is formed by fuse-securing a fused material on a boundary region between an outer circumference of the lens and an opened inner surface of the barrel by illumination of a laser beam on the opened inner surface of the barrel.

1. Field of the Invention
The present invention relates to a lens barrel assembly of a camera module and a laser apparatus for assembling the lens barrel assembly and, more particularly, to a lens barrel assembly of a camera module capable of improving workability and productivity by conveniently and speedily performing a process of permanently assembling a lens with a barrel without a pressing-ring process, a bonding coating process, or a bonding curing process and reducing production cost by reducing the number of parts and a laser apparatus for assembling the lens barrel assembly.
2. Description of the Related Art
Generally, in a current portable communication terminal such as a mobile phone, PDA (personal digital assistant), and a portable PC (personal computer), transmission of text, voice, and image data have been widely used.
Under the circumstances, a camera module for transmission of image data or image chatting is provided as a basic module to the current portable communicant terminal.
FIG. 1 is a perspective exploded view illustrating a general camera module 1. The camera module 1 includes a lens barrel assembly 10 in which a lens L is disposed. The lens barrel assembly 10 includes a barrel 10a of which outer surface is provided with a male screw 11 and a pressing ring 10b which is coupled with an upper end of the barrel 10a to secure the lens L. A light incident hole 13, that is, a lens exposing hole is formed on a central region of an closed upper surface of the barrel 10a to penetrate the upper surface
The lens barrel assembly 10 is coupled with a housing 20 having an inner cylindrical space. An inner surface of the inner cylindrical space is provided with a female screw 21 that is engaged with the female screw 11 of the barrel 10a. An IR filter 25 which filters light transmitting the lens L is disposed on a bottom of the inner cylindrical space.
A board 40 on which an image sensor 30 having an imaging region for imaging an object from the light transmitting the lens L is mounted is disposed under the housing 20. The lower end of the housing 20 is mounted on the one end portion of the board 40, and a connector 45 which is electrically connected to a display means (not shown) is provided to the other end portion of the board 40.
In a case where the image sensor 30 is subject to flip-chip bonding, a window 42 for exposing the imaging region is formed to be opened in the one end portion of the board 40.
A process of assembling the lens or a plurality of the lenses in the lens barrel assembly 10 of the camera module 1 is as follows. As shown in FIGS. 2 and 3, a lower-end of the barrel 10a is faced up, and a plurality of the lenses are sequentially inserted and stacked in the arrow direction A from the upper portion to the lower portion of the barrel 10a. At this time, a spacer(s) 15 is disposed so as to maintain an interval between the lenses L.
Next, the pressing ring 10b is pressed and coupled with the opened lower end of the barrel 10a so as to secure the lenses L stacked in the barrel 10a, so that the temporarily-assembled lens barrel assembly 10 in which the lenses are temporarily assembled is obtained.
As shown in FIG. 3A, the lens barrel assembly 10 in which the lenses L stacked in the barrel 10a is temporarily secured by the pressing ring 10b is mounted on a binding jig (not shown). Next, while the lens barrel assembly is rotated in the arrow direction C, a boundary region between the inner surface of the barrel 10a and the outer surface of the pressing ring 10b is uniformly coated with a UV bonding material 9 by using a dispenser 3. Next, a UV curing process is performed.
As shown in FIG. 3B, in the UV curing process, the UV bonding material 9 coated in the lens barrel assembly 10 is cured by a UV beam illuminated from a UV lamp 6 which is disposed corresponding to the UV bonding material 9, so that the permanently-assembled lens barrel assembly 10 in which the pressing ring 10b is permanently secured to the barrel 10a is obtained.
In the conventional process of permanently securing the pressing ring 10b to the barrel 10a in which the lenses L are stacked, the pressing ring 10b is forcibly pressed and inserted into the lower-end inner surface of the barrel 10a. Therefore, the assembling task is very complicated, and excessively long time is taken to perform the assembling task. In addition, various assembling defects may occur.

Lens barrel assembly of camera module and laser apparatus for assembling the same


A method for preparing a semiconductor substrate surface (28) for semiconductor device fabrication, includes providing a semiconductor substrate (20) having a pure Ge surface layer (28) or a Ge-containing surface layer (12), such as SiGe. The semiconductor substrate (20) is cleaned using a first oxygen plasma process (14) to remove foreign matter (30) from the surface (28) of the substrate (20). The substrate surface (28) is next immersed in a hydrochloric acid solution (16) to remove additional foreign matter (30) from the surface (28) of the substrate (20). The immersion step is followed by a second oxygen plasma etch process (18), passivate the surface with a passivation layer (34), and provide for an atomically smooth surface for subsequent epitaxial or gate dielectric growth.

Germanium surfaces, and more particularly Ge (100) surfaces, have received little attention over the past few decades due to the great success of silicon (Si) based complementary metal oxide semiconductor (CMOS) technology. There now exists a surging interest in Ge based field-effect transistors (FET) where Si cleaning techniques do not apply. This makes the preparing of Ge and/or Ge-containing surfaces for semiconductor device fabrication, such as epitaxial and gate dielectric growth processes, very important. Ge surface cleaning typically includes oxide removal, carbon removal, metallic surface contamination, and the like, and is very important for heterogeneous integration schemes, as well as Ge-containing surfaces, such as SiGe materials which have greater than twenty five percent (>25%) Ge at the surface.
One aspect of heterogeneous integration is epitaxial growth on Ge single crystal substrate. Providing a clean and well passivated surface, such as one passivated with GeO2, becomes important for meeting epitaxial growth requirements. If the surface cleaning is insufficient, impurity elements such as oxygen, carbon, and metal are left over on the surface, and can lead to stacking faults or point defects, leading to poor electrical device performance. In the past, researchers have used several methods or processes for the preparation of Ge and Ge-containing surfaces with various levels of success. One of these methods is a cyclic wet cleaning method which typically produces rough surfaces having high carbon levels leading to growth-related nucleation defects.
Others have used UV-ozone processes to clean carbon from the surface and produce a GeO2 passivation layer. The UV-ozone processes, however, do not address the removal of surface metallic contaminants. In addition, the UV-ozone process is lengthy and while it creates a smooth surface void of carbon, it produces a lower density oxide consistent with a higher GeOx/GeO2 ratio, where O<x<2. Furthermore, wafer fab tools built to handle large batch sizes using this UV-ozone process are not readily available. Still further, chemical surface termination processes have also been utilized to prepare Ge based surfaces, yet have proved difficult to produce a stable passivated surface.
Therefore, a need exists for a method of preparing a Ge or Ge-containing semiconductor substrate surface for subsequent semiconductor device fabrication, such as epitaxial growth or gate dielectric growth.

Method for preparing a semiconductor substrate surface for semiconductor device fabrication


According to the present invention, a photomultiplier tube is used with a high-speed feedback mechanism to continuously modulate the gain of the tube in response to the size of the input signal. The gain of the tube and the anode current are independently converted to ideal logarithms. These signals are then subtracted from one another to reconstruct a true logarithmic representation of the optical signal. This log-light-level signal has a higher dynamic range and faster temporal response than has previously been achieved by other methods.

1. Field of the Invention
The present invention relates to photodetectors. More particularly, the present invention relates to photodetection systems employing photomultiplier tubes.
2. The Prior Art
Optical sensing is the process of converting optical signals (photons) into electrical signals (electrons). In most applications, where the optical signals are large, or the temporal frequencies are low, this is done using solid state devices known as Photodiodes. Photodiodes are inexpensive (typically $1 to $30) and simple to use. They have a high dynamic range, and can be very fast when the light levels are large.
For signals which are too dim to see, photodiodes become much slower, due to the relatively high capacitance of the diode and the small currents generated by the dim signals. Even though photodiodes have excellent dynamic range (they are linear over up to 14 orders of magnitude) their output is proportional to the optical signal, so in practice their useful dynamic range is quickly limited by subsequent electronics. (high speed analog to digital converters typically have a dynamic range of only 3.6 orders of magnitude).
When the optical signals are dim, and frequencies are high, photomultiplier tubes are typically used. Photomultiplier tubes are expensive (typically $100 to over $1000), are subject to damage from overloading input signals, such as ordinary room light, and require a high voltage (typically 1000 Volts) to operate. A photomultiplier tube consists of a photocathode, one or more dynodes (typically 10) and an anode. Individual photons striking the cathode have up to a 25% chance of dislodging an electron. These photoelectrons are then accelerated towards the first dynode by an electric field. When they strike the dynode they dislodge additional electrons, thus amplifying the signal. These secondary electrons then cascade towards the next dynode where they are again amplified. At the end of the dynode chain, the electrons are collected by the anode which carries them outside of the photomultiplier tube. At this point, the signal is large enough to be easily measured using conventional electronics, such as a transimpedence amplifier, followed by an analog-to-digital converter.
The gain at each dynode is a function of the energy of the incoming electron, which is proportional to the electric potential between that dynode and the previous stage. This relation is of the form: EQU G(v)=k.times.v.sup.a
where a is typically in the range of 0.6 to 0.8. The total gain of the tube is the product of the gains from all the dynodes. Typically, and as shown in FIG. 1, the bias voltages for the dynodes are generated by connecting a string of voltage-divider resistors between the cathode, all the dynodes, and ground. Typically the resistance, and therefore the voltage, between all of the dynodes and between the last dynode and anode are the same. This resistance, R, is used as a scaling constant. Typically, the resistance between the anode and the first dynode is 1.5R to 3.5R where R is usually between 10K and 100K ohms. A large negative voltage is then applied to the cathode, and the potential is divided up evenly across the dynodes by the voltage-divider resistor chain.
This conventional biasing scheme is useful for operating the photomultiplier tube at a single programmable gain. Altering the applied cathode voltage changes the gain according to the relation: EQU G(v)=k.times.v.sup.a'
where a' is typically in the range of 7.0 to 8.0. However, the large voltages involved make it difficult to change the gain quickly, due to parasitic capacitances and the large resistor values needed to limit power dissipation in the bias string. The conventional usage is to decide on a tube gain in advance, set the appropriate cathode voltage and then operate the tube at that voltage throughout the measurement operation.
In this configuration, the dynamic range of the photomultiplier tube is limited on the low end by the noise and gain characteristics of the transimpedence amplifier and, on the high end, by the ability of photomultiplier tube to deliver anode current. The anode current is limited by space charge effects within the tube, by bias string power consumption, and by the consumable nature of the material coating the dynodes. If the optical signals to be measured are short pulses with low duty cycles, then capacitors can be placed across the last few bias resistors to improve pulse linearity. However, this trick does not help for bright signals which have a high duty-cycle, or which last more than a few tens of microseconds.
Logarithmic compression has been employed in the prior art in applications such as optical densitometers. These are devices used by photographic labs to check the darkness of an exposed and processed piece of film. However, they only operate over time scales of milliseconds to seconds. Examples of the use of this technique are found in U.S. Pat. Nos. 3,586,443, 3,653,763, and 3,733,491.
Additional examples of photomultiplier tube gain modulation appear in a number of forms, including methods for pre-setting the gains of various tubes which share a common HV supply, AGC circuits for making qualitative measurements, photomultiplier tube overload protection circuits, and fast gain switching circuits.


A lightweight caster is described that is resistant to ingress of debris into a caster bearing. The caster has a monolithic fork having an annular wheel-supporting portion and a chair-supporting portion. The wheel-supporting portion has a pass-through aperture for receiving a retainer. A rotational bearing is supported on the wheel-supporting portion, which supports a wheel rim such that the wheel rotates in the vertical plane. The rim has a pass-through aperture aligned with the pass-through aperture of the fork, and a ring at an inside edge of the bearing to retain the bearing between the rim and the fork and to inhibit debris from contacting the bearing. A retainer retains the rim on the fork and has an aperture aligned with the fork pass-through aperture. The retainer also has a bearing-retaining portion at an outside edge of the bearing to retain the bearing and to inhibit debris from migrating inwardly.

A caster generally comprises a rotational element, for example a wheel or a roller on an axle, and a mount for mounting the wheel to a chair. Casters are mounted on chairs, benches, tables and the like to permit movement of such items across a surface, for example the ground, without the need to lift the items. However, sometimes there is a need to lift the item, for example when lifting a wheelchair into a vehicle. Heavy casters cause a large torque on the wheelchair when lifted, which impacts ergonomics of activities such as getting the wheelchair into the vehicle.
Further, hair and thread and other debris picked up by a rotating tire may eventually drop down to wrap around elements of the caster, for example an axle. If not removed, the hair, threads, etc. may wind tightly around the axle and may penetrate the bearing seal. This allows corrosion of the bearing races, resulting in poor caster performance.
Thus, there is a need for lightweight casters that reduce the potential for debris to enter the bearing races.


In a brazing sheet manufacturing method, a cladding slab is prepared by overlaying at least a core-material slab composed of an aluminum material and a filler-material slab composed of an Al—Si series alloy, in which a metal element that oxidizes more readily than Al is included in at least one of the slabs. A clad sheet is prepared by hot rolling this cladding slab, which then has at least a core material layer composed of the core-material slab and a filler material layer composed of the filler-material slab and disposed on at least one side of the core material. Then, a surface of the clad sheet is etched using a liquid etchant that contains an acid. Subsequently, the clad sheet is cold rolled to a desired thickness. In flux-free brazing, such a brazing sheet is capable of curtailing degradation in brazeability caused by fluctuations in dew point and oxygen concentration.

Aluminum products, such as heat exchangers, mechanical parts, and the like, have numerous components composed of aluminum materials (which include aluminum and aluminum alloys; likewise, below). It is often the case that these components are brazed using a brazing sheet that has a core material and a filler material, which is provided on at least one surface of the core material. The core material of the brazing sheet is typically composed of an aluminum alloy whose solidus temperature is 620° C. or higher. In addition, the filler material is composed of an Al—Si alloy whose solidus temperature is approximately 577° C.
A flux-brazing method is often used as a method of brazing an aluminum material, in which brazing is performed by applying a flux to the surfaces of portions to be joined, i.e., the surfaces of a portions that are to be joined by brazing. However, in flux-brazing methods, after the brazing has been completed, flux and the residue thereof adhere to the surface of the aluminum product. The flux, the residue thereof, or the like may cause problems depending on the intended use of the aluminum product. Furthermore, to remove the flux, the residue thereof, and the like, it is necessary to perform an acid-washing process, and the cost of such a process has been viewed as a problem in recent years.
To avoid the above-described problems attendant with the use of flux, depending on the intended usage of the aluminum product, so-called vacuum-brazing methods are also used, in which brazing is performed in a vacuum without the application of flux to the surfaces of the portion to be joined. However, vacuum-brazing methods have the problems in that productivity is lower than in flux-brazing methods and the quality of the brazed joint(s) tends to deteriorate. In addition, the equipment cost, the maintenance cost, and the like are higher in brazing furnaces used in vacuum-brazing methods than in standard brazing furnaces.
Accordingly, so-called flux-free-brazing methods have been proposed, in which brazing is performed in an inert-gas atmosphere without the application of flux to the surfaces of the portion to be joined. In flux-free brazing, brazing of aluminum materials is performed utilizing an effect that breaks down an oxide film, in which a metal element, such as Mg, Li, etc., that is more readily oxidized than Al is present at the surface of the brazing sheet or of the opposing material. Consequently, brazing sheets used in flux-free brazing comprise a core material and a filler material that contains such a metal element.
However, with regard to such a metal element, because the effect of breaking down the oxide film is weaker than that of flux, if the dew point and the oxygen concentration of the atmosphere inside the brazing furnace rise, then the breakdown of the oxide film by Mg, etc. will tend to become insufficient. Consequently, in flux-free brazing, it is necessary to lower the dew point and the oxygen concentration inside the brazing furnace more than in flux brazing.
Incidentally, for various reasons, the dew point and the oxygen concentration of the atmosphere inside the brazing furnace may vary from the dew point and the oxygen concentration of the inert gas that is supplied into the brazing furnace. For this reason, in the situation in which flux-free brazing is performed, there is a problem in that brazeability tends to degrade due to fluctuations in the dew point and the oxygen concentration inside the brazing furnace.
In response to such problems, brazing-sheet manufacturing methods have been proposed (e.g., Patent Documents 1-3) in which, after a brazing sheet has been prepared, etching is performed to remove the oxide film present on the surface.


A computer-implemented method, according to one approach, is for calibrating read voltages for a block of memory. The computer-implemented method includes: determining a current operating state of a block which includes more than one word-line therein, and where more than one read voltage is associated with each of the word-lines. Moreover, for each of the word-lines in the block: one of the read voltages associated with the given word-line is selected as a reference read voltage, and an absolute shift value is calculated for the reference read voltage. A relative shift value is determined for each of the remaining read voltages associated with the given word-line, where the relative shift values are determined with respect to the reference read voltage. Furthermore, each of the read voltages associated with the given word-line are adjusted using the absolute shift value and each of the respective relative shift values.

The present invention relates to data storage systems, and more particularly, this invention relates to calibrating read voltages for blocks of memory configured in multi-bit-per-cell mode in non-volatile random access memory (NVRAM).
NVRAM is a type of random-access memory which retains information stored thereon even after the power supply is turned off, and includes a number of different forms. Using Flash memory as an example, the performance characteristics of conventional NAND Flash-based solid state drives (SSDs) are fundamentally different from those of traditional hard disk drives (HDDs). Data in conventional SSDs is typically organized in pages of 4, 8, or 16 KB sizes. Moreover, page read operations in SSDs are typically one order of magnitude faster than write operations and latency neither depends on the current nor the previous location of operations.
The raw bit error rate (RBER) of a Flash memory block will typically increase over time due to additional program/erase (P/E) cycling, charge leakage over time (i.e., data retention), and additional charge placed in the cells by read or program operations (i.e., read or program disturb errors, respectively). Typically, a Flash memory block is retired when any page in the block exhibits a code word that reaches a page retirement error count limit. This limit is typically set to be achieved in conjunction with an appropriate error correction code (ECC), resulting in the Uncorrectable Bit Error Rate (UBER) after applying the ECC for a Flash memory block being set to be similar to the UBER in traditional hard disk drives, e.g., at around 10−15, but may be more or less.
Block calibration, which refers to algorithms that adjust the read voltages, has been shown to significantly improve the RBER and therefore enhance endurance and retention, particularly for enterprise-level Flash memory systems using modern three-dimensional (3-D) triple-level-cell (TLC) or quad-level-cell (QLC) NAND Flash memory. Previous attempts to maintain efficient memory performance typically included inspecting the read voltages for each block of memory in a sweeping fashion or by a read voltage shifting algorithm that tracks and corrects the read voltages depending on how the threshold voltage distributions have changed as a result of cycling or retention or other disturbing effects.
Ideally, the read voltages for each page in a block of memory are updated individually. However, as the storage capacity of memory increases, the amount of storage consumed by maintaining a read voltage offset value for each page in each block of memory increases as well. For instance, advancing from 3 bits per cell in TLC NAND Flash memory to 4 bits per cell in QLC NAND Flash memory, each block implements 16 threshold voltage levels (instead of 8 in TLC), and 15 different read voltages (instead of 7 in TLC) to read any of the pages included therein. Moreover, with the improvements in vertical stacking and process technology, the number of layers in every new generation of 3-D NAND Flash increases as well. Subsequently, the number of pages in each block also increases. For example, current 3-D QLC NAND Flash memory may have more than 90 layers and each block may have more than 4000 pages. Thus, if all of these 15 different read voltages in 3-D QLC NAND are calibrated independently (or individually), the amount of metadata involved with storing an individual set of read offset values for each page, or group of pages, in a block and the number of calibration reads per page increases significantly.
As the storage capacity of memory continue to increase, reliability issues associated with the memory increase as well. As a result, conventional calibration engines have experienced an increasing amount of processing overhead caused by the declining reliability of the memory in addition to the increasing number of read voltage offset values that are associated with each page in each block of memory.

Calculating corrective read voltage offsets in non-volatile random access memory

International Business Machines Corporation


A bootstrap circuit is utilized in a bulk circuit using an NMOS transistor as a power switch. The bootstrap circuit includes a first PMOS transistor coupled between an internal power source and an offset capacitor, and a second PMOS transistor coupled between the gate of the first PMOS transistor and the offset capacitor, and an NMOS transistor coupled between the gate of the first PMOS transistor and ground. When the power switch is turned on, the second PMOS transistor is turned on for turning off the first PMOS transistor. When the power switch is turned off, the NMOS transistor is turned on for turning on the first PMOS transistor.

1. Field of the Invention
The present invention relates to a bootstrap circuit, and more particularly, to a bootstrap circuit applied in a bulk circuit using an N-channel Metal Oxide Semiconductor (NMOS) transistor as a power switch.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional bulk circuit 100 using an NMOS transistor as a power switch. As shown in FIG. 1, the bulk circuit 100 comprises a switch control circuit 100, a bootstrap circuit 120, a gate driving circuit GD, a transistor Q1, a diode D2, an inductor L1, two feedback resistors RFB1 and RFB2, and an output capacitor COUT. The transistor Q1 may be an NMOS transistor and is utilized as a power switch of the bulk circuit 100. The operational principle of the bulk circuit 100 is familiar to those skilled in the art and is not illustrated hereinafter for brevity.
The bulk circuit 100 is utilized for lowering down the voltage VIN (for example, 40 volts) provided by a DC voltage source VIN so as to generate a DC output voltage source VOUT to output a lowered DC voltage VOUT (for example, 35 volts). In addition, in FIG. 1, the voltage source VCC (for example, 7 volts) can be generated by the voltage source VIN through a Low Drop Out (LDO) regulator. The voltage source VSS is a ground end (providing voltage with 0 volt).
The gate driving circuit GD comprises two transistors Q2 and Q3. The transistors Q2 and Q3 are a PMOS transistor and an NMOS transistor respectively. The gate driving circuit GD is utilized for enhancing the signal outputted from the switch control circuit 110 so as to drive the transistor Q1. Furthermore, the gate driving circuit GD, in the FIG. 1, actually functions as an inverter.
The bootstrap circuit 120 comprises a diode D1 and an offset capacitor COS. It can be seen in FIG. 1 that the voltage VX and VY respectively on the nodes X and Y of the bootstrap circuit 120 are utilized as the bias voltages for the gate driving circuit GD.
The feedback resistors RFB1 and RFB2 are coupled in series to the output end of the bulk circuit 100 to form a voltage divider for providing a partial voltage of the output voltage VOUT as a feedback voltage VFB.
The switch control circuit 110 outputs the switch control signal SW1 according to the feedback voltage VFB. The switch control signal SW1 may be a Pulse Width Modulation (PWM) signal, wherein the duty ratio of the switch control signal SW1 is related to the feedback voltage VFB. The driving switch control signal SWD is obtained by the gate driving circuit GD enhancing the switch control signal SW1 so as to drive the transistor Q1, which means the enhanced switch control signal SW1 (the driving switch control signal SWD) is capable of turning on/off the transistor Q1. In addition, the switch control signal SW1 is inverted to the driving switch control signal SWD.
When the transistor Q1 is turned off, the power of the voltage source VIN is not conducted to the node Y, which means the voltage VY on the node Y is 0 volt or less at the time. Supposed that the forward voltage VD1 of the diode D1 is 0.7 volt, the voltage source VCC can charge the offset capacitor COS up to 6.3 volts by 7 volts (deducting the forward voltage VD1 of the diode D1).
When the transistor Q1 is turned on, the power of the voltage source VIN is conducted to the node Y, which means the voltage VY on the node Y is 40 volts at the time. Supposed that the forward voltage VD1 of the diode D1 is 0.7 volt and the offset capacitor COS has finished charging, the voltage VX on the node X is 46.3 volts. That is, the voltage range of the gate driving circuit GD capable of driving is from 40 volts to 46.3 volts. Therefore, at the time, supposed that the threshold voltage VTH1 of the transistor Q1 is 1.5 volts, the voltage on the gate of the transistor Q1 has to be more than 41.5 volts to turn on the transistor Q1. Since the voltage range of the gate driving circuit GD capable of driving is from 40 volts to 46.3 volts at the time, the transistor Q1 can be effectively turned on.
Consequently, by means of the bias voltages VX and VY that the bootstrap circuit 120 provides to the gate driving circuit GD, the switch control signal SW1 can effectively turn the transistor Q1 on or off by the gate driving circuit GD.
However, since the forward voltage of the diode is so high that when the transistor Q1 is turned on, the voltage range of gate driving circuit GD capable of driving is not wide enough to fully turn on the transistor Q1. In other words, for fully turning on the transistor Q1, the voltage VCC provided by the voltage source VCC must be high enough to fully turn on transistor Q1. However, since, in the modern fabrication, the size of the circuit elements on the wafer is becoming smaller and smaller, the voltage the circuit elements on the wafer can withstand is becoming lower and lower. Thus, if the voltage source VCC is too high, the circuit elements on the wafer are easily to be damaged. In this condition, either, for protecting the circuit elements on the wafer, the voltage source VCC has to be low enough, causing the transistor Q1 not to be fully turned on, or, for fully turning on the transistor Q1, the voltage source VCC has to be high enough, easily damaging the circuit elements on the wafer. Both methods are not convenient.

Bootstrap circuit and bulk circuit thereof