A dual port memory device capable of random access and serial access, having a random data input/output port arranged along a power supply wiring formed along one direction with respect to a power supply terminal, and a serial data input/output port arranged along a power supply wiring formed along the other direction with respect to the power supply terminal. Noise can be prevented from being included in a random data at an L level in inverting a serial data.

1. Field of the Invention
The present invention relates to a dual port memory device capable of accessing in random and in series a plurality of memory cells in a memory cell array, and more particularly, to an improvement of the arrangement of a data input/output port.
2. Description of the Background Art
In accordance with the development of recent image processing techniques, technical development of three dimensional display of color displays of CRTs for personal computers and CAD systems, and for enlarging/reducing images and multiwindows for screens are in progress.
Various port memory devices have been developed for storing digital video signals under such circumstances. A dual port memory device is known as a random access memory optimized for storing video data, and is capable of random and serial access.
FIG. 5 is a diagram showing the pin connection of such a 4-bit dual port memory device. Referring to FIG. 5, the dual port memory device is separated into two groups, one which is enclosed by the chain dotted line, and the other of the remaining pins. The pins separated by the chain dotted line are used for serial access, and the remaining pins are used for random access. A conventional DRAM is supplied with a port for serial access. This dual port memory comprises the following terminals. The reference characters of the terminals and the signals are identical.
Address terminals A.sub.0 -A.sub.7 receive address signals A.sub.0 -A.sub.7.
A control terminal RAS receives a row address strobe signal RAS.
A control terminal CAS receives a column address strobe signal CAS.
Control terminals WB/WE receive in a time divisional manner a write enable signal WE and a signal WB for specifying write per bit operation. This write per bit operation inhibits writing to a desired bit out of the input data of a plural bit unit.
Control terminals DT/OE receive signals DT/OE for data output of a random data input/output port, and for data transfer between a data register and a memory cell array.
A control terminal SC receives a clock signal SC for controlling the input/output of serial data.
A control terminal SE receives a serial enable signal SE.
Random data input/output terminals W.sub.0 /IO.sub.0 -W.sub.3 /IO.sub.3 receive externally applied data of 4 bits W.sub.0 -W.sub.3, as well as data IO.sub.0 -IO.sub.3 read out from 4 bits of memory cells in a memory cell array.
Serial data input/output terminals SIO.sub.0 -SIO.sub.3 receive externally applied data, as well as data read out in series from a memory cell array.
Power supply terminals V.sub.ss and V.sub.CC receive externally applied power supply voltage.
FIG. 6 is a block diagram of the dual port memory device of FIG. 5. Referring to FIG. 6, the dual port memory device comprises a memory M, an address buffer 2, a random data buffer 5, and a serial data buffer 9, in addition to the connection pins of FIG. 5. Memory M comprises a memory cell array 1 having a plurality of memory cells arranged in the row direction and the column direction, a row decoder 3, a column decoder 4, an address pointer 6, a data register 7, a serial data selector 8, and a clock generator 10. Random data buffer 5, random data input/output terminals W.sub.0 /IO.sub.0 -W.sub.3 /IO.sub.3 implement a random data input/output port W/IO. Serial data buffer 9 and serial data input/output terminals SIO.sub.0 -SIO.sub.3 implement a serial data input/output port SIO. Clock generator 10 responds to various externally applied control signals via a relevant control terminal to generate an internal control signal for controlling the internal circuit. The internal signal is denoted a reference character identical to an externally applied control signal.
Address buffer 2, row decoder 3, column decoder 4, and data buffer 5 are circuits similar to those used in a typical dynamic RAM to carry out random access control. Address pointer 6, data register 7, serial data selector 8, and serial data buffer 9 are circuits for carrying out serial access control.
FIG. 7 is a timing chart of the dual port memory device of FIG. 6. Row address strobe signal RAS, column address strobe signal CAS, and random data W/IO are in asynchronization with clock signal SC and serial data SIO. Random access control and serial access control will be explained with reference to FIGS. 6 and 7.
Random access control is carried out as follows. Row decoder 3 responds to row address strobe signal RAS to strobe a row address signal (refer to FIG. 7(1)). Then, column decoder 4 responds to column address strobe signal CAS to strobe a column address signal (refer to FIG. 7(2)). The strobed row address signal and column address signal are decoded by row decoder 3 and column decoder 4, respectively, and then provided to memory cell array 1. If write enable signal WE and data W.sub.0 -W.sub.3 are applied at this time, data W.sub.0 -W.sub.3 are read into memory cells of 4 bits of memory cell array 1 (refer to FIG. 7(3)). Conversely, if read enable signal OE is applied, data IO.sub.0 -IO.sub.3 are read out from the memory cells of 4 bits of memory cell array 1 (refer to FIG. 7(3)). The readout data are provided from random data input/output port W/IO.
Serial access control is carried out as follows. By address signals A.sub.0 -A.sub.7, row address strobe signal RAS, column address strobe signal CAS, and control signal DT/OE, data stored in the memory cells of 4 bits are transferred to data register 7. At this time, the column address strobed by column address strobe signal CAS is loaded to address pointer 6. The bits (4 bits) specified by the loaded row address are selected by serial data selector 8. The selected 4 bits of data are provided to serial data input/output terminals SIO via serial data buffer 9. Then, address pointer 6 is incremented by 1 point (refer to FIG. 7(4)) every time clock signal SC attains a H level (logical high). This causes the contents of data register 7 to be provided sequentially 1 bit at a time. Thus, the data stored in memory cells of 4 bits in memory cell array 1 are provided to serial data input/output port SIO (refer to FIG. 7(5)). Writing data from serial data input/output port SIO is carried out by an operation in a manner conversely of the reading operation. That is to say, the contents of the serial data input/output port is written sequentially into data register 7 every time clock signal SC attains an H level. Lastly, A.sub.0 -A.sub.7, RAS, CAS, DT/OE control the timing of writing to memory cell array 1.
Thus, the dual port memory can carry out random access and serial access in an asynchronous manner. The inventor of the present invention noticed that noise "a" of FIG. 7(3) is included in the random data at the rise of clock signal SC. This noise "a" may induce erroneous operation of the device that receives data from the dual port memory device. The cause of this noise "a" generation will be explained with reference to FIGS. 8 and 9.
FIG. 8 is a device diagram showing the arrangement of a dual port memory and the power supply wiring. Referring to FIG. 8, this device comprises a semiconductor substrate 20, a memory M, and power supply wirings 21a, 21b. Power supply wirings 21a and 21b are provided in parallel with each other between the inner periphery of semiconductor substrate 20 and the outer periphery of memory M. Between power supply wirings 21a and 21b, random data input/output port W/IO, serial data input/output port SIO, control terminals, power supply terminals V.sub.SS and V.sub.CC, address buffer 2, and input buffer 10a of clock generator 10 are provided.
Power supply wiring 21a is connected to power supply terminal V.sub.CC, and power supply wiring 21b is connected to power supply terminal V.sub.SS. Address buffer 2, random data buffer 5, and serial data buffer 9 receive power supply voltage from power supply wirings 21a and 21b.
A conventional dual port memory device has random data input/output terminals W/IO and serial data input/output terminals SIO mixed both in the right and left directions of power supply terminal V.sub.SS. This means that when clock signal SC attains a H level every time the data provided from random data input/output terminal W/IO is at a L level, the charge in serial data input/output terminal SIO is discharged towards power supply wiring 21a via serial data buffer 9. This discharge current generates voltage by the resistance component of power supply wiring 21a, whereby noise "a" appears in random data input/output port W/IO.
FIG. 9 is a partial enlarged diagram of FIG. 8. Since noise "a" is generated when random data and serial data are output, only the output systems of buffers 5 and 9 will be illustrated, with terminals SIO.sub.3 and W.sub.3 /IO.sub.3. Referring to FIG. 9, random data buffer 5 comprises an inverter 5a, an NOR gate 5b, an NOR gate 5c, an NMOS transistor 5d, and an NMOS transistor 5e. Random data buffer 5 provides data read out from memory M as follows. Inverter 5a inverts data read out from memory M. NOR gate 5b receives data read out from memory M and control signal DT/OE to control MOS transistor 5d. NOR gate 5e receives the data inverted by inverter 5a and control signal DT/OE to control NMOS transistor 5e. NMOS transistor 5d and NMOS transistor 5c are switched complementary to provide the data read out from memory M to random data input/output terminal W.sub.3 /IO.sub.3.
Serial data buffer 9 comprises an inverter 9a, an NOR gate 9b, an NOR gate 9c, an NMOS transistor 9d, and an NMOS transistor 9e. Serial data buffer 9 provides data read out from memory M in series as follows. The data read out from memory M every time clock signal SC attains an H level is inverted by inverter 9a. NOR gate 9b receives the data read out from memory M and control signal SE to control NMOS transistor 9d. NOR gate 9c receives the data inverted by inverter 9a and control signal SE to control NMOS transistor 9e. NMOS transistor 9d and NMOS transistor 9e are switched in a complementary manner to provide data read out from memory M to serial data input/output terminal SIO.sub.3.
When NMOS transistor 9e is turned on, charge stored in serial data input/output terminal SIO.sub.3 flows towards power supply terminal V.sub.SS via power supply wiring 21a (refer to solid line arrow of FIG. 9). This results in the generation of a voltage depending upon the discharge current and resistance component of power supply wiring 21a. If NMOS transistor 5e is at the ON state when this voltage is generated, the generated voltage noise "a" appears on random data input/output terminal W.sub.3 /IO.sub.3.
As described above, noise is generated in the data of the random data input/output terminal in the case where serial data is inverted to a L level when an L level signal is provided from random data input/output terminal in a conventional dual port memory device. To solve this problem, approaches to enlarge the width of the power supply wiring, or to provide separate power supply wirings exclusively for serial access and random access are considered. However, enlargement in the width of the power supply wiring or the increase of the numbers of power supply wirings are not desirable because it will enlarge the area of the semiconductor chip.

Multiport memory device comprising random access port and serial access port


According to one embodiment of the present invention a micro-mirror element comprises a first address portion, a second address portion, and one or more address vias. The first address portion comprises a plurality of address pads distributed in a first layer of the micro-mirror element. The micro-mirror element has a first side and a second side and at least two of the plurality of address pads are distributed on the first side. The second address portion comprises a plurality of address electrodes distributed in a second layer of the micro-mirror element. The one or more address vias are operable to conductively couple the first address portion to the second address portion for the transfer of an address voltage from the first address portion to the second address portion. The distribution of the address pads of the first address portion and the address electrodes of the second address portion causes an electrostatic force provided by the second address portion to be greater than an electrostatic force provided by the first address portion.

Spatial light modulators are capable of being used in optical communication and/or projection display systems. Where spatial light modulators are used in projection display systems, such spatial light modulators are often capable of projecting image details from media sources such as HDTV, DVD, and DVI. Some conventional spatial light modulators typically include an array of pixel elements that are capable of receiving an optical signal or light beam in one tilt or principal ray direction. Typically, each such pixel element includes a monolithically integrated MEMS superstructure cell comprised of a mirror, a beam or binge layer, and a metal 3 layer. The various components in the beam and metal 3 layers cooperate to manipulate the mirror portion for the reflection of light and the production of an image. Proper alignment of the mirror with respect to the metal 3 layer is desired for the micro-mirror element to function properly and reliably.

Digital micro-mirror device with free standing spring tips and distributed address electrodes


A device including a liquid's flow path having an upstream side and a downstream side, a plurality of flow restrictive elements providing material communication between the upstream side to the downstream side, a thermoelectric generator or a thermophotovoltaic cell in thermal connection with a portion of the device located at the downstream side with respect to the plurality of flow restrictive elements. The portion is provided with roughness elements for, in use, contacting a fluid flowing through the device and facilitating collapse of cavitation bubbles.

Batteries have always been the primary source of energy for powering many electronic appliances in households and offices. To achieve energy savings and clean technologies, energy harvesting from ambient sources such as solar power, mechanical vibrations, and thermal energy should be exploited. This approach is needed to offer solutions for solving individual increasing energy consumption problem in the world using renewable energy resources. Thus, energy harvesting is becoming more and more attractive in a wide variety of self-powered micro devices or systems including sensors, monitoring devices, biomedical devices, and implantable biodevices. The market size of energy harvesting is projected to increase to $4.2 billion in 2019 [Energy Harvesters: Market Shares, Strategies, and Forecasts, Worldwide, 2013 to 2019 (2013) Winter Green Research Code: MRS—872]. This huge budget is mostly based on demand for power generation in small scale and should be wisely managed in order to meet global energy need.
Piezoelectric, thermoelectric and pyroelectric energy harvesting, and microengines mostly involve expensive materials and moving parts.
The patent documents WO 95/16995 A1, CN 2 930 573 Y, US 2011/139405 A1, US 2012/186672 A1, U.S. Pat. No. 5,526,408 A, EP 1 706 679 A1, US 2006/159561 A1, US 2006/034705 A1, US 2011/139203 A1, US 2002/009015 A1, WO 2008/108596 A1, are related to cavitation-related technologies or systems which can be arranged for provision of cavitation bubbles. Yet, the combinations of the teachings in said documents provide only a limited efficiency in energy harvesting from flowing fluids.


A golf club head containing a face portion having a front face defining a club face for hitting a ball and a hollow portion provided behind the face portion, wherein the frequency F(fix) of a local minimum value of the first-order vibration mode in a frequency response function of the club head obtained by vibrating an input point on the club face and measuring the response at an output point on the club face is in a range of from 200 to 1400 Hz; and the frequency F(free) of the smallest local minimum value of a frequency response function of the club head obtained by hitting the input point and measuring the response at the output point is in a range of from 5000 to 9000 Hz.

The present invention relates to a golf club head and a method of making the golf club head, and more particularly to a method of adjusting the mechanical impedance of a club head to the golf ball for improving the rebound performance.
In the U.S. Pat. No. 4,928,965 filed based on the following two Japanese patent applications JP-A-61-22874 and JP-A-61-284265, the so called impedance matching theory is proposed. This theory teaches that, when the primary (1st-order) frequency of the mechanical impedance of a golf club head is matched with the primary (1st-order) frequency of the mechanical impedance of the golf ball, a loss of the energy transferred from the golf club head to the struck golf ball is reduced and, as a result, the rebound performance may be improved to increase the golf ball carry.
In the laid-open Japanese patent application JP-A-61-22874 (JP-B-4-56630), it is proposed to design a club head such that the primary frequency of the mechanical impedance of the club head falls within a frequency range of from 2500 to 4000 Hz under a state like the undermentioned strung-up free state.
In the laid-open Japanese patent application JP-A-61-284265 (JP-B-5-33071), on the other hand, it was proposed to design a club head such that the primary frequency of the mechanical impedance of the club head falls within a frequency range of from 600 to 1600 Hz under a state like the undermentioned face-fixed state.
Also in the laid-open Japanese patent application P2002-17904A, it was proposed to design a club head such that the natural vibration frequency of the club head becomes less than 600 HZ under a state like the face-fixed state.
The the present invention has realized that the mechanical impedance of a club head and frequency response function thereof vary depending on the measuring conditions and/or methods, and the present invention further studied to improve the rebound performance of a club head. As a result, optimal conditions were discovered, namely, by designing the club head to satisfy specific conditions in two different measuring methods performed under different conditions, whereby the rebound performance can be further unexpectedly improved.

Golf club head and method of making the same


To enable moving and copying structured data as block data at high speed, and tracing the moved or copied structured data at high speed. A data processing apparatus that processes structured data including a pointer includes a processing unit configured to process the structured data that uses as the pointer a relative address whose origin is the address of a word in which the pointer is stored.

In recent years, scientific computation has been put to practical use, and simulations using complicated structures that exist in the real world are now performed. In such a simulation, a complicated structure in the real world is expressed within a computer by a form of structured data that employs pointers. As a pointer in structured data, either an absolute address or a relative address is employed, and either type of address has advantages and disadvantages.
Japanese Patent Application Publication No. 63-89948 (referred to as Patent Literature 1) discloses a data processing apparatus that has two units that solve problems resulting from the use of absolute addresses and the use of relative addresses. A first unit of the data processing apparatus is the unit configured to represent a pointer in the structured data by a relative address, and convert the relative address into an absolute address. A second unit of the data processing apparatus is the unit configured to represent a pointer in the structured data by an absolute address, and add or subtract a displacement in address to or from the values of all the pointers when the structured data is copied.
According to Patent Literature 1, such relative addresses that the beginning of the structured data is an origin are used as pointers, so that there is no need to rewrite the pointers when the entire structured data is moved or copied. Furthermore, the pointers of relative addresses can be converted into the pointers of absolute addresses by adding the beginning address of the structured data in response to the kind of a tag that each element (word) of the structured data contains. As a result, the overhead in address conversion can be reduced so that the high-speed processing of the structured data that includes pointers becomes possible.
In the ordinary processing of structured data, such a problem occurs, when structured data that employs pointers of absolute addresses is moved or copied, that it is necessary to copy one element at a time while tracing the entire original structure in accordance with the pointers, which requires a considerable amount of processing time.
In the ordinary processing of structured data, it is hard to immediately determine whether each word is a pointer or a value. Therefore, it is necessary, while the structured data is being traced, to determine whether the word is a pointer or a value, and to perform such an operation as to add the difference from the beginning address if the word is a pointer, and as not to add the difference if the word is a value. It takes several ten times of the processing time required when a certain area is moved or copied as a block.
Furthermore, in the data processing apparatus described in the foregoing Patent Literature 1, such a problem occurs that it is necessary to know the beginning address of structured data and to be uniquely determined beforehand. A reason for this is that ordinary structured data has a very complicated structure and it is difficult to immediately determine the beginning address of structure. For example, when pointers are employed among a plurality of structural bodies, the beginning addresses of a plurality of the structural bodies are sometimes needed at the time of processing structured data. In that case, such a problem occurs according to the method of Patent Literature 1 that there is a shortage of the register area.
Further, such a problem occurs according to the method disclosed by the foregoing Patent Literature 1 that the structured data moved or copied in an ordinary computer is hard to be traced at high speed. A reason for this is that the data of each word is identified whether the data is a pointer by the kind of the tag in Patent Literature 1, and pointers of absolute addresses obtained by adding the beginning address of structure are used to refer to elements of the structure, but ordinary computers do not have such tags.

Data processing apparatus, data processing method and program recording medium


An apparatus for a wire cut electrical discharge machine for preventing breakage of the wire electrode during machining, and thereby increasing machining performance. Since wire electrode breakage accidents during machining are often the result of a concentration of spark discharges in the machining area, the present invention controls machining conditions to prevent wire electrode breakage by detecting any continuous generation of spark discharges in a specific zone of the machining zone and discriminating normal concentration phenomenon from a truly bias sparking condition based on the position of the detected sparks. Appropriate control over the machine or machining conditions to relieve the problem may be exerted in response to a detected biased spark discharge condition. A biased spark discharge condition is detected and discriminated when spark discharges continue to occur within a set bias area, defined as a predetermined area which is set around the position of a spark discharge. If subsequent spark discharges are detected outside the bias area, then a non-biased state is determined and a new bias area is set. Thereafter, this procedure is repeated.

A wire cut electrical discharge machining apparatus is an apparatus designed to use a thin wire of about 0.05 to 0.35 mm.phi. in diameter as an electrode tool. The wire is held in tension between a pair of positioning guide members which permit renewal of the wire electrode in the work zone by allowing movement of the electrode wire in its axial direction while maintaining a predetermined tension on it. During normal machining, the wire electrode approaches the workpiece to be machined at approximately a right angle with respect to the axis of the wire electrode, while maintaining a very small machining gap between the workpiece and the wire electrode. Machining is done by generating spark discharges on an intermittent basis. The discharges are generated by applying periodic voltage pulses across the working gap between the wire electrode and the workpiece under conditions where a working fluid fills the working gap. In such an apparatus, the machining feed device causes relative movement between the wire electrode and the workpiece as machining progresses. Unless otherwise prevented by suitable machining condition settings and control of working conditions, machining may be interrupted as a result of wire electrode breakage. Some recent arrangements for dealing with wire electrode breakage include self-recovery devices, such as, for example, a function which automatically joins broken wire electrode ends or otherwise rethreads the electrode through the workpiece. Such joining or rethreading functions are not necessarily 100 percent successful and, in any event, even if successfully accomplished, are not only wasteful of time, but also generally impair machining accuracy and the like. It is, therefore, preferable to avoid wire breakage. However, to do so in the context of prior art wire cut electrical discharge machines creates other problems. In order to machine accurately and with high performance, i.e., efficiently and at higher machining speed, working conditions, and in particular machining voltage pulse width and off time duration, mean amplitude of the discharge current, and machining feed control, must be established and controlled so that the machining is done under heavier load conditions at which there is a higher risk of wire breakage. Moreover, it is impossible to carry out precision machining wherein the wire electrode is highly tensioned without risking wire breakage, unless the machining is done at relatively low efficiency working conditions.
There are various causes of wire electrode breakage. However, wire breakage during machining may, to some extent, be avoided by detecting spark conditions, and controlling the working conditions to light-load conditions if a concentration of spark positions is detected; in other words, a condition where the sparks are only partially distributed along a limited area of the machining gap. Wire electrode breakage due to causes such as spark concentration may be avoided through the use of gap condition detection and adaptive control based on that detection. Appropriate detection, for the purpose of preventing wire electrode breakage, requires detecting the position of the sparks being generated within the working segment of the wire electrode, i.e., the length of wire electrode between the electrical feed or contact pieces positioned on both the upper and lower sides of the workpiece, and especially along the spark-generating portion of the wire electrode, i.e., the axial portion of the wire electrode which defines the machining gap between the wire electrode and the workpiece, and varyingly and responsively controlling the working conditions in accordance with the positions at which spark discharges are generated each time a machining pulse, in the form of a voltage impressed across the machining gap, is generated or in accordance with the position of a sampling of spark discharges from each machining pulse. The detection should be able to determine whether the spark discharge positions are concentrated or not to thereby determine whether conditions which may result in breakage of the wire electrode are present. In other words, the detection should be capable of discriminating whether the spark discharge positions are concentrated or only partially distributed along the wire electrode. Such detection may involve detection of spark discharge positions generated within a predetermined period of time or within predetermined numbers of spark pulses.
Most known detectors of concentrated spark conditions for conventional wire cut electrical discharge machining apparatus indirectly estimate the spark discharge positions according to parameters, such as different spark conditions, in an effort to discriminate a concentrated spark discharge situation from a normal one. For example, according to Laid-Open Japanese Patent Application No. 53-64899, spark discharge positions are detected or measured in an essentially indirect manner by providing a voltage measuring circuit in which fluctuations in electric resistance between an electrical contact point (of the wire electrode) and the sparking point is determined by measuring the voltage therebetween.
Further, according to Laid-Open Japanese Patent Application No. 59-30620, wire breakage prevention is attempted by detecting the value of the current flowing into the upper and/or lower electrical feed or contact pieces, extracting a signal indicative of a changing rate of current flowing into the feed contact pieces from the current detection signal, comparing the current rate change with a predetermined value in order to attempt to determine conditions wherein sparks are concentrated at or nearly the same location on the workpiece, and then resetting the working conditions in response to the detected signal. However, in accordance with this technique, the correlation between the moving speed of the sparking position on the wire electrode and the wire traveling speed is not taken into account and, therefore, the detection of a concentrated sparking condition at the same point on the wire electrode is not possible. In Laid-Open Japanese Patent Application No. 62-54626, the moving speed of the sparking position on the wire electrode and the traveling speed of the wire electrode are detected and when both speeds are almost coincident for more than the predetermined period of time, a concentrated sparking condition detection signal is delivered.
According to the above-stated disclosures and the like, even if the spark discharge positions could be detected or measured with some accuracy, questions remain about spark concentration, methods of discriminating between partially distributed and concentrated spark discharge positions, determination of criterion for discrimination, and the like. Therefore, the present state of the art is not yet effective for practical use.
For example, in the '620 Laid-Open Application the arrangement is such that a spark discharge position signal is detected for every voltage pulse (specifically, the machining current in the electrical feed or contact piece circuit is detected while machining voltage pulses are in a gate-off condition, the value held in a sample-hold circuit, and the value taken as a digital value using an A/D converter), and is compared with the value of the previous spark pulse to detect any difference (by using an arithmetic unit or digital comparator) and, if there is a difference, a difference signal is delivered. Every time the spark discharge position signal is output, the output is integrally counted. When a predetermined set number n is counted, the count of the counter which delivers a varying control signal for setting working conditions, is reset by the difference signal. The count is set using, for example, a preset counter. Conditions for difference detection and the values used, such as the number of times the difference detection delivers the reset signal, is carried out and the set number n for the said preset counter can be freely regulated and set by experience, data and theory, according to selected, predetermined working conditions and machining objectives. However, the machining efficiency is poor under settings which usually overemphasize safety, while smaller safety margins may result in accidental breakage of the wire electrode. Therefore, in practice, operation at preferable settings adapted to individual working conditions are not attained, and the resulting situation is impractical.
In addition, in practical usage, the spark discharge position detection apparatus according to the '620 Laid-Open Application, does not detect spark position with satisfactory accuracy levels.
Similarly, the use of means, such as a difference amplifier, as disclosed in Laid-Open Japanese Patent Application No. 62-15017, for spark discharge position detection does not provide sufficient accuracy as is needed to effectively prevent wire electrode breakage without adversely affecting other aspects of machining performance.
Also, with regard to the disclosure of the '626 Laid-Open Application, if there is a concentration of sparks attributable to chips and/or other foreign matter which has adhered to or become fixedly stuck on the surface of the wire electrode, it can be detected as is disclosed. However, in practice, such a situation is not usually a problem encountered during machining. Today, when machining under usual working conditions, the situation where the traveling speed of the wire electrode has to be used as a parameter for control is unusual. For example, machining is typically carried out using an electrode renewal feed rate of about 3 to 8 m/min for a brass wire electrode of between about 0.2 and 0.3 mm in diameter. Of course, this feed rate may vary depending on the wire electrode material and diameter and other working conditions. Different feed rates and wire electrode material may be used. Assuming conditions such as voltage pulse ON time of about 1 .mu.s or less, about 4 to 10 .mu.s of quiescent (or off) time between sparking pulses, a sparking current of about 10 to 15A, and a machining speed of between about 100 and 170 mm.sup.2 /min, then about 1000 voltage pulses are supplied and impressed between the wire electrode and the workpiece while the wire electrode moves by about 1 mm. Therefore, the appropriate detection strategy is to first detect the spark concentration conditions at locations adjacent to the initial spark discharge position, as opposed to tracing the spark discharge positions on the wire electrode, and then carrying out discrimination. In addition, if the period of concentrated spark duration times is in the range of 50 ms to several 100 ms, as discussed in the '626 Laid-Open Application, the wire electrode would move axially by between about 5 mm and several 10 mm in the time frame of interest. However, the number of machining voltage pulses detected in that time frame (to be used as discrimination data) will be approximately between 50,000 to several 100,000 pulses. From a practical standpoint, it would be difficult to use such a number as a set count number for the counter 34 and/or to determine a suitable frequency setting of the clock pulse generator 3 corresponding to predetermined wire cut spark machining conditions.
The present invention is based in part on a recognition that the spark discharge conditions in a wire cut electrical discharge machine during various machining modes, such as the advancing mode in machining, is roughly as follows.
The wire electrode moves on a renewing feed basis between a pair of contacted positioning guides, while experiencing oscillations (sometimes including superimposed higher oscillations) whose characteristics depend on such parameters as the material, diameter, distance between guides, wire tension, etc. Other oscillations, which are restricted by machining conditions imposed on the traveling portion of wire electrode, e.g., such as where the wire passes through the narrow groove inside which the working fluid is positioned, also exist. Under conditions where intermittent voltage pulses are impressed across the machining gap between the wire electrode and the workpiece, as indicated above, with the wire approaching the workpiece at machining speeds as indicated above, an intermittent sparking pulse of approximately 10 kHz to several 10 kHz on the average is initiated across the machining gap, e.g., where the wire and workpiece are in closest proximity or where foreign matter causes light spark conditions, giving rise to the characteristic EDM sparking. If everything is operating normally, the spark discharges resulting from those sparking pulses move at random along the axial direction of the wire electrode, i.e., along the thickness of the workpiece, as machining progresses. The workpiece is thus subjected to even and equally distributed spark discharges. When sparks start to occur at the same proximate location as a preceding spark, after some time interval additional chips, gas, bubbles, and the like, intervene around the sparking point as a result of the sparks. Assuming an arbitrary number of voltage pulses successively supplied and impressed across the machining gap at a frequency of up to approximately 100 kHz (e.g., using the energy formula disclosed in Laid-Open Japanese Patent Application No. 44-13195, and assuming a spark discharge takes place almost at the instant the voltage pulses are initiated, the sparking frequency and machining pulse frequency will be almost the same), usually several pulses will strike a succession of sparks at or near the same sparking point (of course, not all successive voltage pulses will strike sparks in other (i.e., distributed) locations, and some voltage pulses create no sparks at all). A condition whereby a slight concentration of sparks at or near one location may develop.
Oscillations of the wire electrode may be present from other causes. However, the gap is more likely to expand locally due to influences such as the pressure from the spark discharges and the produced gas, chips and the like which tend to diffuse and move to the circumference. As a result, as described above, most spark discharges take place in the gap at other locations and, as described above, as machining is carried out, the spark discharges move tend to to other locations immediately or after striking some arbitrary number of sparks.
Therefore, it is difficult to discriminate an undue spark concentration conditions based on the exact position of the detection of spark discharges and the procedure of processing multiple spark discharge position detection signals. The above description concerns the case where the machining gap and machining conditions are normal.
As alluded to above, detection of concentrated spark discharge conditions avoids problems. It should be appreciated that there are some cases where the cause is unknown and concentrated sparks cannot be detected. However, situations such as where the machining feed rate increases beyond the normal rate or where the workpiece is thicker in comparison to machining under the normal spark condition as described above, or where there is a deficient or unsuitable supply of working fluid in the gap due to a change in taper angle or when machining around a corner part of a profile configuration to be machined, or where foreign matter or the like adheres to the wire electrode or a local part of the workpiece, or where an overheated spot is created, all may lead to breakage of the wire electrode. Other causes may be a location in the gap wherein several sparks occur and which is not relieved of the arc-like discharges but instead develops short circuit, or where sparks are produced as a result of a machining spark phenomena in a certain location, which, for some reason becomes arc-like. Then, sparks in that location may continuously repeat for a period several times longer than that associated with the slight concentration of sparks which occurs during normal machining. In some cases, the result is an arc-like concentration of sparks leading to breakage of the wire electrode.

Wire cut electrical discharge machining apparatus


A process that allocates bits for quantizing spectral components in a perceptual coding system is performed more efficiently by obtaining an accurate estimate of the optimal value for one or more coding parameters that are used in the bit allocation process. In one implementation for a perceptual audio coding system, an accurate estimate of an offset from a calculated psychoacoustic masking curve is derived by selecting an initial value for the offset, calculating the number of bits that would be allocated if the initial offset were used for coding, and estimating the optimum value of the offset from a difference between this calculated number and the number of bits that are actually available for allocation.

Many coding systems are often used to reduce the amount of information required to adequately represent a source signal. By reducing information capacity requirements, a signal representation can be transmitted over channels having lower bandwidth or stored on media using less space.
Perceptual coding can reduce the information capacity requirements of a source audio signal by eliminating either redundant components or irrelevant components in the signal. This type of coding often uses filter banks to reduce redundancy by decorrelating a source signal using a basis set of spectral components, and reduces irrelevancy by adaptive quantization of the spectral components according to psycho-perceptual criteria. A coding process that adapts the quantizing resolution more coarsely can reduce information requirements to a greater extent but it also introduces higher levels of quantization error or "quantization noise" into the signal. Perceptual coding systems attempt to control the level of quantization noise so that the noise is "masked" or rendered imperceptible by the spectral content of the signal. These systems typically use perceptual models to predict the levels of quantization noise that can be masked by a source signal.
Spectral components that are deemed to be irrelevant because they are predicted to be imperceptible need not be included in the encoded signal. Other spectral components that are deemed to be relevant can be quantized using a quantizing resolution that is adapted to be fine enough to have the quantization noise rendered just imperceptible by spectral components of the source signal. The quantizing resolution is often controlled by bit allocation processes that determine the number of bits used to represent each quantized spectral component.
Practical coding systems are usually constrained to allocate bits such that the bit rate of an encoded signal conveying the quantized spectral components is either invariant and equal to a target bit rate or variable, perhaps limited to a prescribed range, where the average rate is equal to a target bit rate. For either situation, coding systems often use iterative procedures to determine bit allocations. These iterative procedures search for the values of one or more coding parameters that determine bit allocations such that, according to a perceptual model, quantizing noise is deemed to be masked optimally subject to bit rate constraints. The coding parameters may, for example, specify the bandwidth of the signal to be encoded, the number of channels to be encoded, or the target bit rate.
In many coding systems, each iteration of the bit allocation process requires significant computational resources because bit allocations cannot be easily determined from the coding parameters alone. As a result, it is difficult to implement high-quality perceptual audio encoders for low-cost applications such as consumer video recorders.
One approach to overcome this problem is to use a bit allocation process that terminates the iteration as soon as it finds any values for the coding parameters that result in a bit allocation satisfying the bit-rate constraint. This approach generally sacrifices encoding quality to reduce computational complexity because, in general, such an approach will not find optimal values for the coding parameters. This sacrifice may be acceptable if the target bit rate is sufficiently high but it is not acceptable in many applications that must impose stringent limitations on the bit rate. Furthermore, this approach does not guarantee a reduction in computational complexity because it cannot guarantee that acceptable values of the coding parameters will be found using fewer iterations than would be required to find optimal values.

Reduced computational complexity of bit allocation for perceptual coding

Dolby Laboratories Licensing Corporation


A tactilely setable data input structure for a battery-operated, computer-run wrist watch operable in a time mode, a calculator mode and an alphabetic mode comprising a watch casing housing a battery and clock calculator electronics and at least one visible display having multiple units therein. A first button is located on a first side edge of the housing for operating the electronics to cause the visible display to shift between a calculator, alphabetic and a time display upon depression thereof. Further, buttons about the periphery of the watch or watch band are provided. Pressing different combinations of these buttons cause the electronics to create digits zero through nine or alphabetics in a first unit of the display dependent on the combination of specific buttons simultaneously pressed. Multiple entry of digits or alphabetics into the subsequent units of the display allow for creation of multi-digit numbers and words. The numbers created can be used to set time or run normal arithmetic calculator functions. The created words can be stored in a memory in the watch and later downloaded to a computer for creating letters or E-mails, or can provide an internal address book in a watch memory. An outside computer input to create an entry into the watch memory is also provided.

The disclosure of my previous application was directed to a six button tactile actuated calculator watch having multiple time and number registers. That tactile actuated calculator watch has the advantage that a user can operate the calculator by tactilely operating the buttons in a certain pattern to create the numbers or functions rather than having to view the watch to create the numbers or functions. The key boards for normal computer watches are normally equipped with twelve keys spaced closely together, in four rows of multiple columns (similar to a telephone keyboard), with one key for each number and one key for each function (add, subtract, multiply, divide, equals, etc.). In these types of watches great care is necessary in order to enter data accurately as it is quite easy to press two buttons or the wrong button because of finger thickness. Quite often one needs to utilize a stylus to actuate the buttons. Further, one has to view the key pad to enter properly.
My previous application utilized six buttons surrounding the watch face to enter data. The instant application utilizes less than six buttons or more than six buttons around the watch periphery for the data entry, relying on combination or multiple pressing of buttons to create the number or function.
Further, the instant invention contemplates an alphabetic entry to the display or memory of the watch. The alphabetic entry can be used for reminder messages, diaries, memos, etc. In addition, the alphabetic inputs can be combined with numerics to create telephone directories similar to those found in cell phones or address lists.
Additionally, the numeric and alpha input could be stored in memories which could be down-loaded into a computer spreadsheet for processing data or down-loaded into a computer word processor for sending letters and E-mails.
The invention contemplates utilizing the same general logic as my previous invention except that five or less buttons are normally utilized. The multiple entries are obtained by multiple pushing of different buttons. Very rapid use of the instant invention is facilitated by memorizing the button combinations for the desired numerical, alphabetic or function entries. While the preferred input is shown utilizing buttons, levers could be used.
Also while the buttons or levers are shown on the edge of the watch, other locations could be used including the face of the watch or the wrist band.
The type of electronics to obtain such operations can be found in U.S. Pat. No. 4,158,285 to Heinsen et al. which type of electronics can be utilized with the instant invention and which electronics is incorporated by reference hereto as an example of the electronics necessary to operate a watch calculator of the above known type. The instant application is not dependent on the electronics to be used, but rather with a logic system that allows tactile input to such electronics.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.

Tactile actuated electronic computer wrist watch


A vehicle frame structural member assembly method includes an elongated frame member and a reinforcement member. The reinforcement member is complementarily arranged adjacent the elongated frame member.

Vehicle frames and constructions therefor are increasingly complex as vehicle manufacturers look for new ways to improve structural integrity of the vehicle frame while maintaining and/or reducing the overall weight of the vehicle frame. These are often competing concerns. That is, increasing the structural integrity of the vehicle frame (e.g., improving crash performance) often involves adding weight to the vehicle frame. Conversely, reducing the weight of the vehicle frame must be done carefully so as to avoid adversely changing the structural integrity of the vehicle frame. A number of technologies and methods are known for improving the integrity of the vehicle frame and some of these are also concerned with limiting the amount of weight added to the vehicle frame.
In particular, current mass production structural design for vehicles is dominated by stamped metal, which uses section size, material gauge and grade, and typically spot welding to achieve performance requirements. To facilitate fuel economy improvement, supported by weight reduction, new concepts are needed to deliver fundamental weight reduction at a reasonable value. Concepts which can avoid exotic lightweight materials are preferred, particularly those that preserve current manufacturing infrastructure related to spot welding and stamped metal. One known countermeasure is the employment of structural reinforcements. However, the choice of materials and/or execution of designs using such structural reinforcements have been lacking thus far.

Vehicle frame structural member assembly and method


The shelf as defined by a shelf grating formed of a plurality of first and second groups of wires disposed normal to each other and having ends thereof encapsulated by an injection molded, continuous open encapsulation, rim or border. Preferably, each of four border portions of the border each encapsulate substantially the entirety of one of the wires of the two groups to afford rigidity to the wire shelf. The border includes a Class “A” upper surface between peripheral outboard and inboard parting lines or lines of flash which provides a high degree of aesthetics to the shelf when viewed from above.

Adjustable shelves are commonly associated with both the freezer compartment and the fresh food compartment of conventional refrigerators. When the shelves are constructed as sliding shelves, opposite generally parallel sides of the shelves rest upon and slide relative to horizontally aligned ribs or grooves formed in opposing pairs in side walls or inner liners of the compartments. Other such shelves slide relative to shelf brackets which have hooks hooked into slots of vertical tracks mounted in the refrigerator compartments. Typical sliding shelves are exemplified by the disclosures of U.S. Pat. Nos. 6,422,673 B1 and 5,362,145 issued respectively on Jul. 23, 2002 and Nov. 8, 1994. In each case the shelves in their most simplistic construction are defined by a piece of tempered glass bordered by a rim or border which is either snap-secured or injection molded to the tempered glass.
It is also conventional to utilize vertically adjustable shelves in refrigerators which, instead of a tempered glass panel, utilize a supporting surface defined by crossing wires. Wire shelves typical of the latter construction are disclosed in U.S. Pat. No. 5,004,302 granted on Apr. 2, 1991. Two groups of wires are normal to each other and are welded or otherwise secured to cantilevered brackets which can be vertically adjusted within compartments of a refrigerator.
Other conventional shelves are injected molded as a single piece of material, as disclosed in U.S. Pat. No. 5,188,246, and have a hook for cantilevered support from a slat wall typically used in stores and supermarkets. Hollow ribs reduce the weight of the shelf while providing requisite rigidity for supporting articles/products thereupon.
U.S. Pat. No. 3,446,371 granted on May 27, 1969 describes the manufacture of "wire racks" by "laying many wires across two edge members and then welding the wires to the edge members. The exposed cut ends of the wires must be finished to eliminate the dangerous sharp edge. After the finishing operation, some racks are dipped in plastic for decorative and protective purposes, while others are protected by chrome plating." The disadvantages of such racks include the cut ends which create dangerous sharp edges and welding which is "an expensive step in the manufacture of present racks." This patent avoids the latter disadvantages by encasing each wire in a plastic coating, inserting the ends of each wire through slots into a metal shell and filling the shells with a plastic filling which fills the shells and forms a homogeneous bond with the plastic coated wires. Alternatively, the side shells are not utilized but instead plastic coated wires are placed atop opposite parallel metal bars and the latter are encapsulated by plastic introduced into molds which cures and is bonded to the plastic of the wires.


A method for determining crosstalk coupling between a plurality of transmission lines in digital data transmission systems, in particular DSL networks. Firstly, at least one test signal (TS) is generated having a unique identification code (UIC) in the frequency domain (f), said code (UIC) being associated with a first transmission line. Then, the test signal (TS) is sent on the first transmission line. At least a second transmission line is monitored for detecting a crosstalk signal. It is determined whether the crosstalk signal is caused by the test signal (TS) of the first transmission line by means of a signature of the unique identification code (UIC) comprised in the crosstalk signal. In this way crosstalk between individual transmission lines can be determined without having to have recourse to conservative worst case assumptions. The method can adapt dynamically to a changing user/transmission environment, while obtaining unique crosstalk determination results at all times.

The invention is based on a priority application EP 05291798.6 which is hereby incorporated by reference.
The invention relates to a method for determining crosstalk coupling between a plurality of transmission lines in digital data transmission systems, in particular DSL networks.
The invention also relates to a crosstalk determining unit for integration in or for connection to an access node of a digital data transmission system, in particular a DSL network, with a plurality of transmission lines coupled to the access node.
Furthermore, the invention relates to a digital data transmission system, in particular in the form of a DSL network, and to a computer program product for determining crosstalk coupling in digital data transmission systems, in particular DSL networks, with a plurality of transmission lines.
Crosstalk remains one of the major limiting factors for Digital Subscriber Lines (DSL) transmission, as it effectively limits the obtainable DSL bitrate (for a given loop length) or the DSL reach at a guaranteed minimum bitrate. Furthermore, crosstalk can cause errors in transmission, service interruption, and the need for time consuming re-initializations and re-synchronizations. As a consequence crosstalk plays a major role in DSL service deployment. Additionally, knowledge of crosstalk coupling is equally valuable for other DSL deployment scenarios, e.g. service upgrading, fault diagnosis, etc. For all DSL deployment phases (such as prequalification or in-service optimisation), solutions are needed that help to estimate the impact of crosstalk, or even to minimise it (such as dynamic spectrum management DSM). For instance, when DSL lines are limited by far-end crosstalk (FEXT), FEXT needs to be mitigated in order to upgrade DSL users to higher bit rates. Alternatively, for a given service FEXT mitigation can largely extend the reach of DSL. The same holds also for near-end crosstalk (NEXT).
An important issue in this context is to determine which transmission lines (hereinafter also referred to as "lines") are crosstalk-affecting one another. Typically a cable leaving a Digital Subscriber Line Access Multiplexer (DSLAM) contains thousands of lines. Crosstalk coupling is present between all line couples, but the crosstalk coupling is not equally strong for each line couple. Especially when lines inside a cable are grouped in binders, crosstalk coupling between lines in the same binder is on average higher than crosstalk between lines in separate binders. In order to optimise the performance of a DSL network and to limit its complexity, e.g. by means of DSM algorithms, an important point is to know which lines are contained in one binder. Although databases exist from which one may deduce which lines are in the same cable or cable binder, these databases are not always updated, so that their reliability is estimated to be between 60 and 80%. Furthermore, from field tests, it is well-known that there is a lot of variation of crosstalk coupling between line couples—up to 20 dB—which cannot be accurately determined solely on the basis of the mechanical design of the loop plant.
A first kind of prior art solutions for determining crosstalk levels rely on worst-case assumptions: Since the crosstalk coupling functions and the users that share the same binder are generally unknown, DSM algorithms have to resort to worst case crosstalk coupling functions, which are often overly conservative. An alternative prior art approach as described in European patent application 04 292 070.2 incorporated herein by reference includes Virtual Binder Identification through polling: This technique allows to detect which lines generate the highest amount of crosstalk towards a given transmission line of interest. It consists in continuously monitoring the on/off status and/or the noise margin of modems on different transmission lines. If a given modem is switched on and, as a consequence, a second modem switches off or experiences a loss in noise margin, the first modem/line can be identified as a dominant crosstalker with respect to the second modem/line. At the same time a crosstalk coupling constant can be estimated.
The aforementioned prior art approaches suffer from inherent disadvantages: For instance, the worst case assumption leads to overly conservative designs, wherein two users which share the same binder without affecting each other, will transmit with a "worst case" power spectral density (PSD), instead of transmitting at full power. Furthermore, the resulting spectrum management is static in nature and thus does not change when new users become active or when the loop topology is changed. Concerning Virtual Binder Identification through polling, polling the on/off status and/or the noise margin of each single line is highly complex and infeasible in practice since on/off switching of modems is controlled by the end user and not by the central agent. Hence, the agent would have to monitor all lines (at the same time) to see whether or not the status of a particular modem changes. A DSLAM, however, can only process a small number of simple network management protocol (SNMP) commands per minute, which limits the number of lines that can be monitored at a given time. Still another disadvantage concerns the uniqueness of the polling result: If two modems ("disturbers") switch on at essentially the same time, and two other modems ("victims") have to retrain or find their noise margin reduced as a result of this, it is impossible to determine which victim is affected by which disturber. Hence, the polling process of crosstalk detection is not unique, which may lead to incorrect spectrum management.

Method for determing crosstalk coupling and crosstalk determining unit for integration in digital data transmission systems


A pneumatic motion platform is disclosed, adapted to allow an open center to handle shear stress without the need for a central support. In an embodiment, the platform comprises a deck; a base; a plurality of inflatable actuators, each actuator attached to the deck at a predetermined location intermediate the base and the deck, the plurality of inflatable actuators adapted for use as an active motive force with respect to the deck in a plurality of planes; a plurality of compliant stabilizers disposed intermediate the deck and the base, at least one portion of each stabilizer disposed proximate a predetermined one of the plurality of inflatable actuators; a fluid controller in fluid communication with the plurality of inflatable actuators; and a source of fluid in fluid communication with the fluid controller. A ride vehicle may comprise a cabin attached to a deck attached to the motion platform attached to a rotator such as a turntable. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Amusement ride vehicles are increasingly called upon to impart a sense of "being there" to amusement ride guests. Similarly, simulators in general, which may be used to impart a sense of spatial reality to the occupant, attempt to convey a sense of experiencing that which is being projected or otherwise simulated.
One method by which the illusion or simulation of being in such space may be implemented is to seat one or more individuals in a seat which is part of a platform that has controllable motion in at least two planes. Controllable motion in three planes is preferable.
In certain situations, the platform may be moved in space, e.g. along a track, while motion is imparted in X, Y, and/or Z axes, i.e. roll, pitch, heave, and yaw.

Amusement ride vehicle with pneumatically actuated cabin and motion base


A storage switch in accordance with an embodiment of the invention is a highly scalable switch that allows the creation of a SAN that is easy to deploy and that can be centrally managed. Moreover, such a storage switch also allows the deployment of a global infrastructure, allowing the resources of the SAN, such as storage devices, to essentially be positioned anywhere on the globe. Further, such a storage switch allows a multi-protocol SAN, e.g., one that includes both iSCSI or Fibre Channel, and processes data packets at “wire speed.” To further enable wire-speed processing, a switch in accordance with the invention has “intelligence” distributed to each of its linecards, through which it classifies packets into data and control packets, it performs virtualization functions, and it performs protocol translation functions. A switch in accordance with the invention further performs serverless storage services such as mirroring, snapshot, and replication.

The rapid growth in data intensive applications continues to fuel the demand for raw data storage capacity. As companies rely more and more on e-commerce, online transaction processing, and databases, the amount of information that needs to be managed and stored can be massive. As a result, the ongoing need to add more storage, service more users and back-up more data has become a daunting task.
To meet this growing demand for data, the concept of the Storage Area Network (SAN) has been gaining popularity. A SAN is defined by the Storage Networking Industry Association (SNIA) as a network whose primary purpose is the transfer of data between computer systems and storage elements and among storage elements. Unlike connecting a storage device directly to a server, e.g., with a SCSI connection, and unlike adding a storage device to a LAN with a traditional interface such as Ethernet (e.g., a NAS system), the SAN forms essentially an independent network that does not tend to have the same bandwidth limitations as its direct-connect SCSI and NAS counterparts.
More specifically, in a SAN environment, storage devices (e.g., tape drives and RAID arrays) and servers are generally interconnected via various switches and appliances. The connections to the switches and appliances are usually Fibre Channel. This structure generally allows for any server on the SAN to communicate with any storage device and vice versa. It also provides alternative paths from server to storage device. In other words, if a particular server is slow or completely unavailable, another server on the SAN can provide access to the storage device. A SAN also makes it possible to mirror data, making multiple copies available and thus creating more reliability in the availability of data. When more storage is needed, additional storage devices can be added to the SAN without the need to be connected to a specific server; rather, the new devices can simply be added to the storage network and can be accessed from any point.
An example of a SAN is shown in the system 100 illustrated in the functional block diagram of FIG. 1. As shown, there are one or more servers 102. Three servers 102 are shown for exemplary purposes only. Servers 102 are connected through an Ethernet connection to a LAN 106 and/or to a router 108 and then to a WAN 110, such as the Internet. In addition, each server 102 is connected through a Fibre Channel connection to each of a plurality of Fibre Channel switches 112 sometimes referred to as the "fabric" of the SAN. Two switches 112 are shown for exemplary purposes only. Each switch 112 is in turn connected to each of a plurality of SAN appliances 114. Two appliances 114 are shown for exemplary purposes only. Each appliance is also coupled to each of a plurality of storage devices 116, such as tape drives, optical drives, or RAID arrays. In addition, each switch 112 and appliance 114 is coupled to a gateway 118, which in turn is coupled to router 108, which ultimately connects to a Wide Area Network (WAN) 118, such as the Internet. FIG. 1 shows one example of a possible configuration of a SAN 119, which includes switches 112, appliances 114, storage devices 116, and gateways 118. Still other configurations are possible. For instance, one appliance may be connected to fewer than all the switches.
Appliances 114 perform the storage management of the SAN. When the appliance 114 receives data, it stores the data in a memory in the appliance. Then, with a processor (also in the appliance), analyzes and operates on the data in order to forward the data to the correct storage device(s). This store-and-forward process typically slows down data access.
While the appliances do perform some switching, because there may be a large number of servers (many more than three), and because each appliance has few ports (usually only two or four), switches 112 are needed to connect the many servers to the few appliances. Nevertheless, switches 112 have little built-in intelligence and merely forward data to a selected appliance 114.
One limitation of appliances is the fact that an appliance typically has very few ports, e.g., only two ports. As a result, the bandwidth available through the appliance can be limited. Adding ports to an appliance, although possible, is typically very expensive. Every one or two ports are supported by an expensive CPU or server card. So generally to add ports, entire file cards (which perform virtualization and store-and-forward functions) must be added to the device, which is usually very costly. In the alternative, appliances are simply added to the SAN, but again, this tends to be very costly.
In addition, SANs, usually in the appliances 114, generally perform a function known as "virtualization." Virtualization occurs when space on one or more physical storage devices is allocated to a particular user, but the physical location of that space remains unknown to the user. For instance, a user may access its company's "engineering storage space," ENG:, accessing and "seeing" the virtual space ENG: as he or she would access or "see" an attached disk drive. Nonetheless, the ENG: space may be divided over several physical storage devices or even fragmented on a single storage device. Thus, when a server requests a virtual device (e.g., ENG:) and block number, the appliance must determine the device(s) that physically correlate to the virtual device requested and direct the data accordingly.
In general, SANs are formed using a single protocol to interconnect the devices. Although Fibre Channel is the most commonly used, Ethernet connections have also been used. Nonetheless, if both protocols are desired to be used, some kind of transition between the two protocols must occur. In such instances, a Fibre Channel SAN 119 is typically coupled to an Ethernet SAN 122 via a bridge 121. To transition from one protocol to the other, a packet is received by the bridge and stored in memory. Once the packet is stored in a memory, a processor operates on the packet to remove the headers of one protocol and build the headers of the other protocol, thereby constructing an entirely new packet. More specifically, referring to FIG. 2, when a request (which may be comprised of one or more packets) is received by bridge 121, it is received, for example, by a Host Bus Adapter (HBA) 202 over a Fibre Channel connection 204. The entire request is stored in memory 206 until a processor 208 is ready to analyze and operate on it, i.e., to rebuild the request in accordance with the outgoing protocol. Once the request has been operated on by the processor 208, the request is sent to the Network Interface Card (NIC) 210 and then out over the ethernet connection 212. Of course, the same process could occur vice versa (ethernet to fibre channel). Hence, the transition between protocols requires significant memory and processor resources, which not only cause delays in transmitting data but also increase the cost of the system in both money and real estate. Nonetheless, the only alternative currently available is to keep the protocols isolated on distinct networks.
Gateways 118 (FIG. 1), in addition to connecting a SAN to a WAN, are often used to connect two or more SANs together. Gateways usually do not transition the various protocols, but rather encapsulate the data in IP packets, as is known in the art. Nonetheless, when multiple SANs are connected, there must be a unique address for each connected device. However, although the IP protocol contains 32 bits for addressing, the Fibre Channel protocol only contains 24 bits. Hence, because most SANs use Fibre Channel, scalability can be a problem despite the use of a gateway, limiting use of SANs over the Internet.
Although SANs were introduced several years ago, interoperability problems, lack of available skills, and high implementation costs remain major obstacles to widespread use. For instance, SANs as they currently exist have high deployment costs and high management costs. Referring again to FIG. 1, each switch, appliance, and gateway typically come from different vendors, creating a lack of management standards that has resulted in the proliferation of vendor-specific management tools. As a result, to deploy a SAN, equipment must be purchased from multiple vendors. And, as shown in FIG. 1, each switch, appliance, gateway, storage device, server, and router will have its own management, shown as management stations 120. Although independent physical management stations are shown, it is to be understood that independent management is frequently in the form of independent, vendor-specific software on a single computer but which software does not communicate with one another. As a result, there is no centralized management of the SAN and its management costs are high given that there are usually multiple management stations that frequently require many people to manage.


A phase-frequency detector (110) includes an output stage (300) and a control stage (200). The output stage includes a pump up switched current source (350), a pump down switched current sink (360), and a constant current source (325) that are coupled to a charge pump output node (111). The control stage generates, in response to a divided variable frequency signal (FV) (136) and a reference frequency signal (FR) (106), a pump up control signal (246) and a pump down control signal (216).

A known technique for obtaining extremely fine frequency resolution in a phase lock loop (PLL) is to use a sigma delta modulator that modifies the value of N in a 1/N divider in the feedback loop of the frequency synthesizer. While the phase lock loop is in lock, the value of N is modified between two or more values, by use of a sequence of integer values that are typically low integer values (e.g., 0's and 1's). The sequence of integer values are coupled to the 1/N divider and an output of the 1/N divider is coupled to a phase-frequency detector. The sequence of integer values causes noise in the PLL that appears as modulation noise in the output of the PLL. An advantage of using a sigma delta modulator is that the noise is noise shaped such that its spectral content is concentrated at high frequencies. A low-pass response of the PLL attenuates the high frequency noise such that it does not significantly modulate the output of the PLL.
It has been experimentally determined that the transfer function for a PLL that uses a sigma delta modulator in this fashion must be very linear to avoid undesirable sequence value dependent responses that degrade the noise shaping properties of the sigma delta modulator. The portion of the PLL that most typically introduces such non-linearities and the resultant degradation is the phase-frequency detector, which typically is a charge pump detector.
Two types of charge pump detectors have been used in the past. Although they have both been successfully employed, both of them have undesirable characteristics that are increasingly important in modern, very low power and high frequency devices, such as pagers and cellular phones. The first type is a tri-state charge pump phase-frequency detector. In this type of phase-frequency detector, a pump up switched current source and pump down switched current sink are coupled together forming a charge pump output. When an output of the 1/N divider lags a reference signal, the pump up current source is activated, and when the output of the 1/N divider leads the reference signal, the pump down current source is activated. When the PLL is in phase lock, either the source or sink is turned on during each cycle for a very brief time. This tri-state charge pump has an advantage of very low average current drain, but the operation of the tri-state charge pump degrades the noise shaping of the sigma delta modulator due to gain and transient characteristic differences between the current source and sink that introduce a non-linear performance. It is very difficult in practice to match the gain differences and transient characteristics of the source and sink.
The second type of phase-frequency detector is a dual state phase frequency detector, in which a pump up constant current source is on continuously and a pump down current sink having twice the value of the pump up constant current source is turned on when the output of the 1/N divider leads the reference signal. This results in a 50/50 duty cycle. Switching only the pump down sink results in a very linear charge pump output characteristic. Although this approach substantially reduces noise due to non-linearity, it generates undesirable noise from the constant current source and the switched current sink, which are active a large portion of the time. The high duty cycle is particularly a problem in CMOS devices which are desirable for their low cost but which inherently have high flicker noise. This has resulted in the use of expensive bipolar or BiCMOS processes in high performance applications.
Thus, what is needed is a linear phase-frequency detector that reduces the coupling of device noise into the PLL output.

Linear low noise phase-frequency detector


The present system improves the performance of a query in a database system when a plan for the query comprises sorting an input that is at least partially sorted such that a slow materialization sort can be applied. The invention applies the slow materialization sort by determining a sequence of subsets in accordance with the partially sorted input. As each of the subsets is determined, the subset is output for further processing. Advantageously, the invention reduces the waiting period for obtaining results from a sorting operation under certain circumstances.

A common form of an information retrieval system for managing computerized records contained in a database is a relational database management system. Between an actual database (that is, data stored for use by a computer) and users of an information retrieval system for managing is a software layer known as the relational database management system (RDBMS or DBMS). The RDBMS is responsible for handling all requests for access to the database and shielding the users from the details of any specific hardware and/or software implementation. Using relational techniques, the RDBMS stores, manipulates and retrieves data in table form. Typically, these relationships are defined by a set of columns and a set of rows. The columns are also referred to as attributes, or data types. The rows are also referred to as records or tuples, of data.
A standard language for dealing with DBMSs is the Structured Query Language (SQL). SQL comprises both data definition operations and data manipulation operations. To maintain data independence, a set of SQL commands, referred to as a query, provides the RDBMS with instructions to perform. However, the query does not describe directions for performing the instructions. Thus, the RDBMS comprises a query processor for generating various query plans of execution and choosing a preferred plan. Due to the high-level nature of relational expressions and a variety of implementation techniques, automatic query optimization is possible and often necessary to ensure efficient query processing.
In accordance with well-known query translation processes, an SQL query is processed in stages. The initial stage casts the source query into an internal form such as the Query Graph Model (QGM) following the preliminary steps of lexing, parsing and semantic checking. The goal of the QGM is to provide a more powerful and conceptually more manageable representation of queries to reduce the complexity of query compilation and optimization. The internal QGM is a data structure for providing the semantic relationships of the query for use by query translator and optimizer components for rewriting the query in a canonical form. A plan optimizer produces a query execution plan such as by generating alternate plans and choosing a best plan based on estimated execution costs. A plan refinement stage may be employed to refine the optimum execution plan in accordance with run-time requirements.
Often, for the query results to be utilized in a meaningful way, the query is also sorted. However, database tables can be very large and processing tables for sorting can be expensive in terms of computer resources. Therefore, it is important that techniques for sorting tables be as efficient as possible.
Known database systems provide a sorting operation that executes completely on a table. That is, when a sorting operation is used in executing an application such as a query plan in a database system, output rows are returned from the sorting operation only when the sorting operation has been executed on the entire table. Thus, the sorting operation acts as a barrier for outputting rows. Consequently, the application or query waits until the sorting operation is completed before receiving any sorted rows. This waiting period increases the application execution time, which may be especially high for external sorting operations. External sorting operations are generally performed when the data to be sorted is too large to place in a main memory. Such sorting operations seek to minimize disk accesses for the sort. What is therefore needed is a system and associated method that reduce the waiting time for sorting operations executed on tables. The need for such system and method has heretofore remained unsatisfied.

System and method for slow materialization sorting of partially ordered inputs in a database system

International Business Machines Corporation


An MRI apparatus for performing an MRI examination to an object by sequentially applying an imaging method group, which is constituted by time-sequentially arranging a plurality of different imaging methods, to each of the imaging methods, has an imaging method group setting unit, a performing order setting unit and an imaging condition setting unit. The imaging method group setting unit sets the imaging method group. The performing order setting unit sets a performing order as a performing order of the imaging methods constituting the imaging method group. The imaging condition setting unit sets an imaging condition to each of the imaging methods. The workflow setting unit obtains an examination history data corresponding to the imaging method group, the performing order and the imaging condition from the examination history data previously stored to a storage unit, and sets a first workflow relating to the MRI examination by estimating an imaging time of each of the imaging methods in the performing order based on the obtained examination history data.

1. Technical Field of the Invention
The present invention relates to a magnetic resonance imaging (MRI) apparatus, and more particularly to an MRI apparatus capable of performing a plurality of different imaging methods time-sequentially based on a scan plan.
2. Related Art
An MRI is an imaging method of exciting the atomic nucleus spin of a tissue of an object (examined person such as a patient) placed in an static magnetic field by radio frequency signals (RF pulses) having the Larmor frequency thereof and reconstructing image data from magnetic resonance signals (MR signals) generated by the excitation.
The MRI apparatus is an image diagnosis apparatus for generating the image data based on the MR signal detected from the inside of a living body and indispensable in the present image diagnosis field because it is possible to obtain a lot of diagnosis information including not only dissection diagnosis information but also biochemical information, function diagnosis information, and the like.
In the MRI apparatus, various diagnosis image data relating to the object are collected by a main imaging to collect the image data used for a diagnosis to which, an imaging method group ordinarily constituted by time-sequentially arranging a plurality of different imaging methods, is time-sequentially applied. Then, the object is diagnosed based on the collected diagnosis image data. In this case, a scan plan is set by selecting an imaging condition of each of the imaging methods and a performing order for performing the plurality of imaging methods constituting the imaging method group using locator image data previously collected by, for example, a pilot imaging performed to the object, and the main imaging is performed based on the scan plan to collect the image data for the diagnosis (for example, it is mentioned in "Japanese Patent Application Publication No. 2006-231040").
When the scan plan is set, an imaging time necessary to perform each of the imaging methods is approximately determined by a time necessary to collect MR signals which use a predetermined pulse-sequence (data collection time) and a time necessary to an image reconstruction processing and an image processing performed to the thus obtained MR signals (data processing time). Then, prior to the MRI examination, when a doctor and an examination engineer (hereinafter, called operators) in charge of the object perform a plurality of imaging methods in parallel so that data processing periods do not overlap, they set the performing order in which an examination time necessary to perform a plurality of imaging methods time-sequentially is minimized as one of scan plans.
Incidentally, a receiving RF coil (receiving coil) disposed the MRI apparatus to detect MR signals is ordinarily composed of a plurality of coil elements (array coils) to obtain good receiving sensitivity. When the image data is generated by performing data processings such as the image reconstruction processing, the image processing, and the like to the MR signals detected by these coil elements, a high speed arithmetic operation processing unit disposed to an image data generating unit prevents an increase of a circuit scale by subjecting the MR signals of a plurality of channels obtained from the coil elements to parallel processing.
However, since a data processing time to the MR signals is also increased because recently a data amount is increased abruptly by arranging an array coil as multi-channel array coil, an imaging time in each of the imaging methods greatly depends on a data processing time in addition to a data collection time. Since the data processing time of the data obtained by each imaging method depends on whether or not the high speed arithmetic operation processing unit can perform parallel processing, how long parallel processing time the processing unit requires, and the like, it is difficult for the operators to accurately grasp the imaging time of each imaging method from the imaging condition set by the scan plan. Further, it is difficult to set a preferable performing order capable of minimizing the examination time required by the imaging method group constituted by the plurality of imaging methods.


A new and distinct cultivar of Rose plant named ‘Emparaimp’, characterized by its long and upright flowering stems; strong plants; bright yellow-colored flowers; and excellent postproduction longevity.

The present Invention relates to a new and distinct cultivar of Rose plant, botanically known as Rosa hybrida, commercially used as a cut flower Rose, and hereinafter referred to by the name 'Emparaimp'.
The new Rose plant is a product of a planned breeding program conducted by the Inventor in Aalsmeer, The Netherlands. The objective of the breeding program was to develop new freely-flowering cut flower Rose varieties with attractive flower colors and excellent postproduction longevity.
The new Rose plant is a naturally-occurring whole plant mutation of Rosa hybrida 'Empara', not patented. The new Rose was discovered and selected by the Inventor as a single flowering plant from within a population of plants of 'Empara' in a controlled greenhouse environment in Aalsmeer, The Netherlands in 2008.
Asexual reproduction of the new Rose by cuttings at Aalsmeer, The Netherlands, has shown that the unique features of this new Rose plant are stable and reproduced true to type in successive generations of asexual reproduction.


Methods of compacting sequential circuit test vector set by partitioning of faults into hard and easy faults, re-ordering vectors in a test set by moving sequences that detect hard faults to the beginning of the test set, and a combination of partitioning and re-ordering.

1. Field of the Invention
This invention relates to methods for compacting test sets for sequential circuits. More specifically, to partitioning and reordering methods for fast static test sequence compaction of sequential circuits.
This application relates to U.S. application Ser. No. 09/001,543 filed on Dec. 31, 1997 entitled, "State Relaxation Based Subsequence Removal Method for Fast Static Compaction in Sequential Circuits," which is assigned to the Assignee of the present invention and which is incorporated herein by reference.
2. Background and Description of Related Art
Since the cost of testing sequential circuits is directly proportional to the number of test vectors in a test set, short test sequences are desirable. Reduction in test set size can be achieved using static or dynamic test set compaction algorithms. Dynamic techniques such as those described in Chakradhar, S., et al., "Bottleneck Removal Algorithm for Dynamic Compaction and Test Cycle Removal," Proc. European Design Automation Conf., pp. 98-104, September 1995), Chakradhar, S., et al., "Bottleneck Removal Algorithm for Dynamic Compaction in Sequential Circuits," IEEE Trans. on Computer-Aided Design, (Accepted for Publication) 1997 and Niermann, T. M., et al., "Method for Automatically Generating Test Vectors for Digital Integrated Circuits," U.S. Pat. No. 5,377,197, 1994, perform compaction concurrently with the test generation process. These techniques often require modification of the test generator.
Static compaction techniques, on the other hand, are employed after the test generation process. Obviously, static techniques are independent of the test generation algorithm and do not require modifications to the test generator. In addition, static compaction techniques can further reduce the size of test sets obtained after dynamic compaction.
Several static compaction approaches for sequential circuits have been proposed in the following papers: Niermann, T. M., et al. "Test Compaction for Sequential Circuits," IEEE Trans. Computer-Aided Design, vol. 11, no. 2, pp. 260-67, February 1992, So, B., "Time-efficient Automatic Test Pattern Generation System," Ph.D. Thesis, EE Dept. Univ. of Wisconsin-Madison, 1994, Pomeranz, I., et al., "On Static Compaction of Test Sequences for Synchronous Sequential Circuits," Proc. Design Automation Conf., pp. 215-20, June 1996 and Hsiao, M. S. et al., "Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors," Proc. IEEE VLSI Test Symp., pp. 188-195, April 1995.
Some of these approaches (Niermann, Time Compaction, So) cannot reduce test sets produced by random or simulation-based test generators. Static compaction techniques based on vector insertion, omission, or selection have also been investigated (Pomeranz). These techniques require multiple fault simulation passes. If a vector is omitted or swapped, the fault simulator is invoked to make sure that the fault coverage is not affected. Vector restoration techniques, as described in Guo, R., et al., "Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration," Technical Report Aug. 3, 1997, Electrical and Computer Engineering Department, University of Iowa, August 1997, aim to restore sufficient vectors necessary to detect all faults, starting with the harder faults. Fast static test set compaction based on removing recurrence subsequences that start and end on the same states has also been reported recently (Hsiao). However, these test sets are not as compact as those achieved by algorithms that use multiple fault simulation passes.

Partitioning and reordering methods for static test sequence compaction of sequential circuits


Provided is a method of creating structure profiles on a substrate using faceting and passivation layers. A first plasma etch process performed generating a faceted sidewall and a desired inflection point; a second plasma etch process is performed using an oxygen, nitrogen, or combined oxygen and nitrogen plasma, generating a passivation layer; and a third plasma etch process using operating variables of an etch chemistry on the faceted sidewall and the passivation layer to induce differential etch rates to achieve a breakthrough on near-horizontal surfaces of the structure, wherein the third plasma etch used is configured to produce a target sidewall profile on the substrate down to the underlying stop layer. Selected two or more plasma etch variables are controlled in the performance of the first plasma etch process, the second plasma etch process, and/or the third plasma etch process in order to achieve target sidewall profile objectives.

Field of Invention
The present invention relates to a method and system for substrate processing, and more particularly to a method and system for patterning sidewall shapes using sidewall faceting and flash addition or passivation growth.
Description of Related Art
As feature scaling continues to dominate microelectronic development, the creation of specific structures can be a costly and complex process. Often these processes can be difficult to control. The following is a methodology to simply create a unique structure profile that has many future applications.
This invention relates to dry plasma processing using well known etch characteristics of sidewall faceting and growth of passivation layers to create new, unique, and novel silicon profiles. Employing relative etch rates of a secondary, in-situ grown, hard mask due to faceted surfaces allows for successful pattern transfer. There is a need for a set of processes that can be controlled to generate target sidewall profiles of structures for specific applications.

Partial etch memorization via flash addition