The formation of a non-woven, free from organic solvent, formed through parallel formation of fibers on a collection device is disclosed. As the individual fibers are dry prior to contact with other fibers, the different contents of the various fiber types do not interact. However, when wetted, the fibers will start to be dissolved, or swell, and the different contents will be released and then interact. For the example of thrombin and fibrinogen, the interaction will initiate the formation of a fibrin coagulum by the cleavage of fibrinogen through the action of thrombin to form fibrin monomers that spontaneously polymerize to form a three dimensional network of fibrin.

In many instances it is desired to provide a product with two different, but mixed components. One example is for control of heamostasis. Here it is desired to provide a product with both thrombin and fibrinogen to be released in in situ. However, care has to be taken to ensure the active components do not interact prior to placement in situ.
For this type of products any residual organic solvents in the product can be harmful to the wound site, and should be avoided.
WO99/56798 discloses a product of polysaccharides as polyanionic polysaccharides, alginic acid, chitin, chitosan, and dextran; synthetic materials as polyglycolide, polylactide, polycaprolactone, and fibrin. The product is produced by admixing of the components under high shear conditions to evenly disperse the materials in an organic solvent.


Generation of test cases for functional verification of a complex system-under-test is achieved by the use of a probability matrix. The probability matrix represents a non-uniform distribution function of resource combinations used in the transactions, and can be created randomly, or by application of various types of testing knowledge. The matrix is used by a test generator for selecting resources that participate in a transaction involving an interconnect between different types of system components. Applying the inventive principles increases the quality of design verification by stimulation of both the system's resources and its internal interconnects, with almost no knowledge of the structure of the system.

1. Field of the Invention
This invention relates to functional verification of a hardware system. More particularly, this invention relates to functional verification of the system-level interconnects of hardware systems or designs having different types of interconnected resources.
2. Description of the Related Art
Functional verification is widely acknowledged to be a bottleneck in the hardware system's design cycle. Indeed, up to 70% of development time and resources are typically spent on functional verification. Allowing users to find design flaws, and fixing them in a subsequent release would be unwise and costly for three main reasons: (1) harm to reputation and brand-name; (2) a high cost of recall and replacement when there is a large installed base; and (3) litigation, should design flaws cause injury.
During the last few years, complex hardware systems have shifted from custom ASIC's towards system-on-a-chip (SoC) based designs, which include ready made components. The verification of such systems requires new tools and methodologies that are up to the new challenges raised by the characteristics of systems and SoC's.
At the heart of these challenges stands the requirement to verify the integration of several previously designed components in a relatively short time.
In current industrial practice, dynamic verification is the main functional verification technique for large and complex systems. Dynamic verification is accomplished by generating a large number of tests using random test generators, simulating the tests on the system-under-test, and checking that the system-under-test behaves according to its specification.
The rationale behind verification by simulation is that one acquires confidence in the correctness of a system-under-test by running a set of test cases that encompass a sufficiently large number of different cases, which in some sense is assumed to be a representative sample of the full space of possible cases. The ability of the system-under-test to correctly handle all cases is inferred from the correct handling of the cases actually tested. This approach is discussed, for example, in the document User Defined Coverage—A Tool Supported Methodology for Design Verification, Raanan Grinwald, Eran Harel, Michael Orgad, Shmuel Ur, and Avi Ziv, Proc. 38th Design Automation Conference (DAC38), pages 158-163, 1998. When conducting simulations, it is desirable to define a particular subspace, which is considered to be "interesting" in terms of verification, and then to generate tests selected at random that cover the subspace.
Test cases developed by algorithms such as the foregoing are typically implemented on a test generator, which may optionally bias the tests based on internal testing knowledge. Such test generators are described in the following documents: Model-Based Test Generation For Processor Design Verification, Y. Lichtenstein, Y. Malka and A. Aharon, Innovative Applications of Artificial Intelligence (IAAI), AAAI Press, 1994; Constraint Satisfaction for Test Program Generation, L. Fournier, D. Lewin, M. Levinger, E. Roytman and Gil Shurek, Int. Phoenix Conference on Computers and Communications, March 1995; and Test Program Generation for Functional Verification of PowerPC Processors in IBM, A. Aharon, D. Goodman, M. Levinger, Y. Lichtenstein, Y. Malka, C. Metzger, M. Molcho and G. Shurek, 32nd Design Automation Conference, San Francisco, June 1995, pp. 279-285.
The term coverage concerns checking and showing that testing has been thorough. Coverage is the prime measurement for the quality of a set of test cases. Simply stated, the idea in coverage is to create, in a systematic fashion, a large and comprehensive list of tasks, and to check that each task is executed in the testing phase. Ultimately, higher coverage implies greater chances of exposing a design flaw.

Test-cases for functional verification of system-level interconnect

International Business Machines Corporation


In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.

Mainstream processor chips, both in high performance and low power segments, are increasingly integrating additional functionality such as graphics, display engines, security engines, PCIe™ ports (i.e., ports in accordance with the Peripheral Component Interconnect Express (PCI Express™ (PCIe™)) Specification Base Specification version 2.0 (published 2007) (hereafter the PCIe™ specification) and other PCIe™ based peripheral devices, while maintaining legacy support for devices compliant with a PCI specification such as the Peripheral Component Interconnect (PCI) Local Bus Specification, version 3.0 (published 2002) (hereafter the PCI specification).
Such designs are highly segmented due to varying requirements from the server, desktop, mobile, embedded, ultra-mobile and mobile Internet device segments. Different markets seek to use single chip system-on-chip (SoC) solutions that combine at least some of processor cores, memory controllers, input/output controllers and other segment specific acceleration elements onto a single chip. However, designs that accumulate these features are slow to emerge due to the difficulty of integrating different intellectual property (IP) blocks on a single die. This is especially so, as IP blocks can have various requirements and design uniqueness, and can require many specialized wires, communication protocols and so forth to enable their incorporation into an SoC. As a result, each SoC or other advanced semiconductor device that is developed requires a great amount of design complexity and customization to incorporate different IP blocks into a single device. This is so, as a given IP block typically needs to be re-designed to accommodate interface and signaling requirements of a given SoC.
In many computer systems, an IP block or agent can send a broadcast or multicast request to many or all other agents within the system. When this request is for a read operation, the agent will receive a completion/reply for every agent or targeted agent in the system. It is thus the agent's responsibility to aggregate the status and the data of all of these completions. The sending of these multiple completions raises complexity for the requesting agent and consumes bandwidth and other resources.

This patent is subject to a terminal disclaimer.

Aggregating completion messages in a sideband interface


Sheet finishing apparatus constructed to prevent sheet skewing during stacking conveyance, and stack-disarranging sheet slippage. A sheet-stacking tray is disposed forming a break in a discharge path below a discharge outlet. A first discharge roller unit is disposed at the discharge outlet, and a second discharge roller unit is arranged to convey, in cooperation with the first discharge roller unit, sheets downstream to the stacking tray. The second discharge roller unit is supported allowing it to rise and lower between an engage position where it catches sheet(s) on the storage tray, and a retracted position. A registering wall is provided in the stacking tray, for positionally registering the leading/trailing edge of the sheets. A gripper pressingly holds the uppermost sheet stacked on the storage tray, and a controller controls the movement of the gripper between an operational position where it engages the uppermost sheet, and a non-operational retract position.

1. Technical Field
The present invention relates to sheet finishing apparatuses that stack/store sheets sequentially conveyed out from a printer, a copier, a printing machine or other device; more particularly the invention relates to sheet finishing apparatuses for receiving sheets on which images have been formed by an image forming apparatus, and carrying out stapling, punching or stamping processes on the sheets.
2. Description of the Related Art
Generally, these kinds of sheet finishing apparatuses temporarily set onto a tray sheets on which images have been formed by an image forming apparatus, etc. After the sheets set on the tray have been finish-processed, the finished sheets are held in a downstream storage tray. In the finishing tray, depending on the process, the sheets are finished by being placed on the tray one at a time to undergo a stamping process, or a ream of sheets is placed on the tray in a bundle to undergo a stapling process. This means that the finishing tray requires a conveyance mechanism for bringing in sheets, and a conveyance mechanism for sending out finished sheets to the storage tray.
Conventionally, as a conveying-in mechanism for conveying in sheets to a finishing tray, a system wherein conveyance rollers are provided at a sheet-discharge outlet of a discharge path for ejecting sheets onto a tray arranged forming a break in the path on the downstream side of the discharge outlet, and a system wherein sheets are conveyed out by the cooperation of a first discharge roller provided at a discharge outlet, and a second discharge roller arranged on a tray are both known. While the former system affords a simple structure, the downside is that sheets can become skewed or otherwise misaligned. A known problem with the latter is that sheets can become wrinkled or otherwise damaged if the timing at which the second discharge roller on the tray engages the sheets being fed by the first discharge roller is off.
Meanwhile, as a conveyance mechanism for discharging sheets from a finishing tray, a mechanism such as that disclosed in Japanese Unexamined Pat. App. Pub. No. 2003-128332, for example, is known, in which a claw-shaped projecting member is provided for engaging the trailing edge of the sheets on the finishing tray, and the projecting member is shifted along the finishing tray to convey sheets out toward a stacking tray. Specifically, a long groove is provided in the midportion of the finishing tray, reaching from the sheet-inflow side to the sheet convey-out side. The claw-shaped projecting member is disposed in the long groove to project above the tray through the tray back side (the reverse side), and is fastened to an endless belt provided along the tray back side. Pulleys for the endless belt are drivingly rotated. Pressing on the trailing edge of the sheets with a claw-shaped member in this way enables the accurate conveyance to the storage tray of weighty sheets stacked in a bundle. It also makes it possible to neatly convey the sheets out in bundle form.
A further example of such conveyance mechanisms is a system, proposed for example in Japanese Unexamined Pat. App. Pub. No. 2002-193515 among other publications, in which, along with a sheet pushing mechanism for pushing out the trailing edge of the sheets, conveyance rollers are disposed at the discharge-outlet end of the conveyance path. According to this configuration, a claw-shaped projecting member is arranged on the finishing tray, free to travel along the convey-out direction, and a conveyance roller is arranged on the downstream side of the tray to convey out sheets. Sheets set on the finishing tray are pushed out by the claw-shaped projecting member and are then conveyed out by the conveyance roller. In other words, the claw-shaped projecting member pushes the sheets along the tray and downstream, and thereafter the conveyance roller, arranged at the discharge outlet on the downstream side, separated from the claw-shaped projecting member, takes over to convey the sheets.
With such structures known to date, in which sheets are ejected onto a tray with a discharge roller at the discharge outlet, sheets can become skewed and stacked out of alignment on the tray, or stray outside the tray in implementations in which, as described above, sheets are stacked in a finishing tray, with a break in the path from the discharge outlet being formed as described above. This means that, particularly when carrying out stapling or other finishing processes, with the sheets becoming unaligned, there will be problems inviting mishandling of the sheets. Likewise, a problem with implementations in which roller means at the discharge outlet and roller means on the tray cooperate to discharge sheets, as is disclosed in the above-cited App. Pub. No. 2002-193515, is that in rotating while pressing the sheet, the roller means arranged on the tray transfers in the sheet-discharging direction the lead sheet already stacked in a predetermined position, giving rise to displacement.
Sheets already stacked on the tray slipping out of place due to subsequent sheets being conveyed into the tray can invite erroneous finishing operations in the same manner as with the situations described above. With (flimsy) sheets lacking stiffness, such displacement is the cause of corners getting bent or folded. Particularly, in implementations in which a forward/reverse rotating roller means is provided on the stacking tray, and sheets are switched back from the discharge outlet and brought into alignment by their trailing edges landing against a registration member, at the same time that the above-described problems are brought about when sheets are conveyed in, a problem arises in which, in switching-back sheets with the roller means to bring the sheets into alignment, sheets that have been stacked may get dragged along and bend or fold at the leading edges.


Disclosed herein is a reaction chamber comprising a cavity, an upper electrode disposed in the cavity, a gas diffusion plate, and an adjustment assembly, wherein the gas diffusion plate is disposed directly above the upper electrode, and blocks the cavity, and the gas diffusion plate is provided with a plurality of air holes; the adjustment assembly is disposed on the gas diffusion plate.

In the preparation process of semiconductor, etching is a process step that chemically or physically removes unwanted material from a silicon or glass substrate selectively, and replicates the final pattern transfer of the desired pattern on a silicon sheet or glass substrate, and can be divided into wet etching and dry etching. Dry etching is a process technology that uses a plasma generated in a gaseous state, through a mask window opened by photolithography, for physical and chemical reactions with silicon wafer or glass substrate exposed to plasma to etch off exposed surface material on silicon sheet or glass substrate. The anisotropy of dry etching can realize the conversion of fine patterns, meet the requirements of smaller and smaller sizes, and has become the most important etching method for sub-micron and below.
However, since there are differences in the shape and density of the etched surface in dry etching, the etching rates for different pattern shapes and densities may be different, resulting in a difference in the depth and critical dimensions of the trenches formed by etching, such as a large area to be etched; then more etchant may be consumed, and when the concentration of the etchant decreases, the etching rate is slowed down, and conversely, the area to be etched is small, and the etching rate is relatively fast. Such phenomenon is called the loading effect. The change of the etch rate caused by the loading effect affects the uniformity of the etch rate and directly affects the overall uniformity of the etch and the quality of the etch.

Reaction chamber, dry etching machine and etching method


Provided is a driving apparatus for driving an object. The driving apparatus includes a driving device configured to displace the object; a detector configured to detect a displacement amount of the object by the driving device; and a controller configured to control the driving device based on an output of the detector. The controller is configured to obtain a thrust characteristic of the driving device with respect to the displacement amount and to set a reference with respect to the displacement amount based on the obtained thrust characteristic.

Field of the Invention
The present invention relates to a driving apparatus and an article processing apparatus.
Description of the Related Art
For example, a galvano motor or a linear motor is used in an article processing apparatus such as a laser processing apparatus, a semiconductor manufacturing apparatus, or the like. Among them, the galvano scanner performs positioning of, with high precision, a mirror attached to a shaft of a rotary motor (galvano motor), and then a laser beam which is reflected by the mirror. As a detector that detects a rotation angle for highly accurate positioning, an electrostatic capacitance sensor, an optical encoder, or a magnetic encoder is used. On the other hand, the linear motor performs positioning for an object to be processed such as a wafer, a mask, or the like with high accuracy. Furthermore, there are an absolute type and an incremental type for encoders. Among them, the incremental-type encoder (hereinafter referred to as "incremental encoder") may detect the displacement amount of an object to be processed from an increase/decrease in pulse with respect to the displacement of a scale. However, in the incremental encoder, a sensor for detecting a reference position (zero point) is separately required for specifying an absolute position. Accordingly, Japanese Patent Laid-Open No. H9-229713 discloses an incremental encoder that outputs the phase Z signal indicating a reference position in addition to the phase A and phase B signals indicating a relative position. In the electrostatic capacitance sensor, the reproducibility of a detection position is affected by an environmental condition such as temperature or humidity. In order to correct a measurement value affected thereby, a sensor for detecting a reference position may be separately required.
In the driving apparatus including the incremental encoder disclosed in Japanese Patent Laid-Open No. H9-229713, a sensor for detecting a reference position needs to be separately provided as described above, and thus, there is room for further improvement in size and cost thereof.

Driving apparatus and article processing apparatus


A multi-domain vertical alignment liquid crystal display (MVA LCD) panel has a bottom substrate, a top substrate parallel to the bottom substrate, and a liquid crystal molecule layer filled in between. The panel further has a plurality of pixel regions arranged in arrays on the bottom substrate, a plurality of common lines traversing the pixel regions, a plurality of pixel electrodes positioned in each pixel region above the common lines, a plurality of slits positioned on each pixel electrode, a common electrode layer positioned on the surface of the top substrate, and a plurality of protrusions arranged parallel to and alternatively with the slits and positioned on the surface of the common electrode layer. The protrusions and the common lines are partially overlapped.

1. Field of the Invention
The present invention relates to a multi-domain vertical alignment (MVA) LCD panel, and more particularly, to an MVA LCD panel having a high aperture ratio without suffering from the light leakage problem due to protrusions.
2. Description of the Prior Art
LCDs have been widely applied to various electronic devices, such as mobile phones, personal digital assistants, and notebook computers in recent years. With the rapid development of the large-size flat display market, LCDs have played an important role and have gradually replaced CRT displays. However, conventional LCDs are limited by their narrow view angles. Consequently, MVA LCD panels which can be viewed in wide angles are therefore designed.
Please refer to FIG. 1 and FIG. 2. FIG. 1 is a schematic diagram of a conventional MVA LCD panel 10 while no voltage is applied; FIG. 2 is a schematic diagram of the conventional MVA LCD panel 10 shown in FIG. 1 while a voltage is applied. As shown in FIG. 1, the conventional MVA LCD panel 10 includes a top substrate 12, a bottom substrate 14, a liquid crystal layer 16 filled in between the top substrate 12 and the bottom substrate 14, a color filter layer 18 positioned on the surface of the top substrate 12 facing the bottom substrate 14, a common electrode layer 20 positioned on the bottom surface of the color filter layer 18, a pixel electrode 15 positioned on the surface of the bottom substrate 14 facing the top substrate 12, at least a first protrusion 22 positioned on the bottom surface of the common electrode layer 20, and at least a second protrusion 24 positioned on the surface of the pixel electrode 15. It is noted that FIG. 1 and FIG. 2 illustrate only a single pixel region of the MVA LCD panel 10, and therefore data lines, scan lines, and thin film transistors (TFTs) are omitted for easy illustration.
While a voltage is applied to the pixel electrode 15, liquid crystal molecules are inclined so that light beams passing through the liquid crystal molecules are rotated. The rotated light beams will pass through the color filter layer 18, and therefore viewers can see brilliant colors. As shown in FIG. 2, the liquid crystal molecules are influenced by the first protrusion 22 and the second protrusion 24, and thus are inclined in different directions. This characteristic makes it possible for the conventional MVA LCD panel 10 to be viewed in wide angles.
As shown in FIG. 1, however, the liquid crystal molecules close to the first protrusion 22 and the second protrusion 24 are slightly inclined under the effect of the first protrusion 22 and the second protrusion 24 even when no voltage is applied. This leads to light leakages and color aberrations, and therefore reduces the contrast ratio of the MVA LCD panel 10. For example, when a complete black state for a pixel region is required, the sub pixels red, green, and blue are supposed to be completely dark. As long as light leakages occur, the completely black state cannot be achieved, and this reduces the contrast ratio. Additionally, if a color mixed only by red and green is required in a pixel region, the light leakage of sub pixel blue would cause the color aberration and deteriorate the display effect.
Currently, a black matrix layer is introduced between the top substrate 12 and the first protrusion 22 to solve the aforementioned light leakage problem. However, the black matrix layer solves the light leakage problems at the cost of low aperture ratio, which is not desired.

Multi-domain vertical alignment liquid crystal display panel comprising alternating and parallel slits and protrusions


The present invention is intended to provide an information carrier which has flat surfaces, is excellent in beautiful appearance, and permits necessary printing thereon after the production of the carrier, and a process for producing such a thin information carrier easily in high yield. The substrate 3 of the information storage carrier is composed of a material obtained by infiltrating a resin 8 into a reinforcer 7 made of a sheet-like material deformable in the direction of the thickness. An IC module 1 and a coil 2 are embedded in indents 34 formed by compressing the reinforcer 7 in the direction of the thickness, to smoothen both right and reverse sides of the substrate 3. Cover sheets 4 and 5 are attached to the right and reverse sides, respectively, of the substrate 3 with a bonding layer 6 to obtain the required information storage carrier. The substrate 3 having smooth right and reverse sides can be produced by placing the IC module 1 and the coil 2 on the aforesaid reinforcer impregnated with the resin and pressing the IC module 1 and the coil 2 until the surface of the resin layer and the surfaces of the IC module 1 and the coil 2 are placed on the same plane.

The present invention relates to an information carrier obtained by supporting on a substrate at least one fitting for, for example, storing, displaying or processing information, and a process for producing the same.
Various information carriers have been proposed which are obtained by supporting one or more parts such as IC chips on a substrate, store information, and give information to a reader-writer or receive information therefrom. Such information carriers are used for, for example, storing personal information on deposits, insurances, commutation tickets, licences, health, identification cards, etc., information on product management in factories, and information on commodity management in the commodity distribution field, or the employment of the information carriers for such purposes is investigated.
FIG. 29 and FIG. 30 are diagrams showing an example of such an information carrier which has been known: FIG. 29 is a partially sectioned plan view of the information carrier, and FIG. 30 a sectional view taken along the line 30--30 of FIG. 29. In these drawings, the symbol 100 shows an IC module; the symbol 101 a coil connected to the IC module 100; the symbol 102 a substrate supporting the IC module 100 and the coil 101; the symbol 103 a resin constituting the substrate 102; the symbol 104 a reinforcer for the resin 103; and the symbols 105 and 106 cover sheets attached to the right and reverse, respectively, sides of the substrate 102.
As is clear from these drawings, in this example of the information carrier, the IC module 100 and the coil 101 are placed in a cut-out hole 104a made in the reinforcer 104, and the space in the cut-out hole 104a is filled with the resin 103, which is infiltrated into the reinforcer 104, whereby the substrate 102 is formed. Since this example of the information carrier thus comprises the reinforcer 104 having the cut-out hole 104a, and the IC module 100 and the coil 101 placed in the cut-out hole 104a, a position in the substrate 102 at which the coil 101 is set can be accurately regulated by adjusting the size of the cut-out hole 104a to a suitable size for the coil 101, so that the efficient receipt of electric power from an external equipment and the efficient transmission of signals from or to the external equipment are possible.
The above well-known example of the information carrier, however, involves the following problem: since the IC module 100 and the coil 101 are placed in the cut-out hole 104a made in the reinforcer 104 and the resin 103 inside and outside the cut-out hole 104a is cured, the strength inside the cut-out hole 104a having no reinforcer 104 is low, so that when the information carrier receives an irregular external force, stress is centered on the inside of the cut-out hole 104a, resulting in easy cracking of the substrate 102.
Said information carrier also involves the following problem: since reinforcers 104 different in the size of the cut-out hole 104a have to be prepared depending on the sizes of the IC module 100 and the coil 101 which are to be placed in the cut-out hole 104a, a complicated production process is required when various information carriers are produced in the same line.
In addition, in the above well-known example of the information carrier, the reinforcer 104 is made of, for example, woven fabric obtained by plain weave of glass fiber, so that when the cut-out hole 104a is made by cutting the reinforcer 104, the glass fiber is frayed and stuck out of the cut surface to cause the following phenomenon: as shown in FIG. 31, the frayed glass fiber 107 juts out into the inside of the cut-out hole 104a or extends above or below the reinforcer 104.
When the frayed glass fiber 107 juts out into the inside of the cut-out hole 104, the following disadvantage is brought about: as shown in FIG. 32, the thickness of a portion where the IC module 100 and/or the coil 101 overlaps with the glass fiber 107 exceeds the thickness of the substrate 102, so that the surface flatness of the substrate 102 and hence that of the cover sheets 105 and 106 are deteriorated. When the frayed glass fiber 107 extends above or below the reinforcer 104, the thickness of such a portion is larger than that of the other portion of the substrate 102, so that the flatness of the cover sheets 105 and 106 is deteriorated. When the flatness of the cover sheets 105 and 106 is deteriorated, the beautiful appearance and the ease of handling are deteriorated, resulting in a decreased commercial value. Furthermore, in the case of an information carrier in which, for example, a photograph of owner's face is printed on the surface of the cover sheet 105 or 106 after the production of the information carrier, there is a disadvantage in that the photograph of the face cannot be clearly printed.
Since the woven fabric obtained by plain weave of glass fiber is hardly compressible in the direction of the thickness, pressing of the substrate 102 cannot remove the thickness nonuniformity of the substrate 102 and moreover tends to destroy the IC module 100 and the coil 101. The above-mentioned disadvantage can be removed by stopping the fraying, for example, by hardening and fixing the glass fiber 107 frayed and stuck out of the cut surface with a resin before inserting the IC module 100 and the coil 101 into the cut-out hole 104a, but a production process of the information carrier becomes complicated as much, resulting in an increased production cost of the information carrier. Therefore, this method cannot be said to be a preferable method.
The present invention was made for solving such problems and objects thereof are to provide an information carrier having a high resistance to external force (e.g. flexure) and such a flat surface that it is excellent in beautiful appearance and permits good necessary printing, and to provide a production process which makes it possible to produce such an information carrier easily in high yield.

Information carrier and process for producing same


A substrate processing apparatus comprises a substrate handling chamber, a pair of position sensors, and a substrate transfer robot. Each of the sensors comprises an emitter configured to emit a beam of light, and a receiver configured to receive the light beam. The substrate transfer robot comprises an end effector and a robot actuator. The end effector is configured to hold a substrate such that the substrate has a same expected position with respect to the end effector every time the substrate is held. The robot actuator is configured to move the end effector within the handling chamber to transfer substrates among a plurality of substrate stations. An edge of a substrate held in the expected position by the end effector can partially block a light beam of one of the position sensors, while another end of the end effector partially blocks a light beam of the other position sensor.

1. Field
The present application relates generally to substrate processing and, more particularly, to methods and apparatuses for transferring substrates through a substrate processing system.
2. Description of the Related Art
An apparatus for processing semiconductor substrates, such as silicon wafers, typically includes a processing chamber in which the substrates are processed, a substrate handling chamber through which the substrates are moved before and after processing in the processing chamber, and one or more input/output chambers that store substrates before and after the substrates are moved through the handling chamber. A substrate transfer robot is located within the handling chamber and is configured to transfer substrates to and from a plurality of stations. Such stations may be within the handling chamber, the input/output chambers, the processing chamber, or other chambers. A typical station within the processing chamber is a substrate holder, such as a susceptor, which supports a substrate during processing. A station within the input/output chamber may comprise a cassette that holds a plurality of substrates. The input/output chambers may be loading chambers or load ports that contain substrate cassettes that are accessible by the transfer robot. The input/output chambers can also be load-lock chambers in which substrates can be atmospherically isolated and purged of particulates before being moved into the handling chamber and eventually into the processing chamber. Other stations, which can be inside separate chambers or even within the substrate handling chamber, may include pre-processing stations (such as a wafer pre-cleaning station) and/or post-processing stations (such as a cooling station).
The substrate transfer robot typically includes an actuator, one or more interlinked arms, and an end effector attached to the arms. The actuator is configured to move the arms and the end effector. The end effector is adapted to pick up a substrate from a station, hold the substrate as the robot moves the end effector and the substrate to another station, and place the substrate at another station. A variety of different types of end effectors exist, including paddles and Bernoulli wands.
In so-called cluster tools, the apparatus includes a plurality of processing chambers each typically adjacent to the substrate handling chamber. The processing chambers are capable of processing substrates simultaneously, which increases the overall substrate throughput of the apparatus. The handling chamber may include more than one substrate transfer robot for improved substrate handling capability.
Substrates must often be placed with great accuracy. A typical susceptor for holding a semiconductor wafer has a wafer pocket whose size is only slightly larger than that of a wafer that the susceptor is designed to support. For example, a susceptor designed to support a 300 mm wafer might have a wafer pocket with a diameter of only 301 mm, providing a clearance of only 0.5 mm between the edge of the supported wafer and the pocket's perimeter wall. It is important that the wafer be centered in the pocket and not touch the pocket wall. If the wafer contacts the pocket wall, local temperature changes occur, resulting in temperature gradients across the wafer. This can cause non-uniformity in process results, as most semiconductor processing depends critically on temperature.
Errors in placement of the substrate relative to an end effector, known as "substrate drift," are sometimes caused by variations in substrate position in the cassette at pickup. In other words, at pickup the end effector may attach to each substrate at a slightly different location. Substrate drift can also occur during robot movement, particularly when the robot moves fast. In addition to the aforementioned problems associated with failing to center the substrate within a susceptor pocket, substrate drift can result in damage to the substrate during placement at a substrate station, such as a wafer cassette.
One method of solving these problems associated with substrate drift involves the use of at least two photosensors in the wafer handling chamber. For example, U.S. Pat. No. 7,008,802 discloses using photosensors that sense an extent to which an edge of the wafer blocks a light beam emitted by the photosensor. By measuring the extent to which the wafer edge blocks the light beams of the photosensors, the position of the wafer is calculated and compared to a pre-registered normal position to calculate an offset displacement to be applied to the robot to compensate for the calculated positioning error. Another reference that discloses using two photosensors to calculate a position of a wafer is Japanese Patent Laid-open No. 2005-93807.

Position sensor system for substrate transfer robot


Provided is a method of fabricating an ultra thin flip-chip package. In the above method, an under barrier metal film is formed on a bond pad of a semiconductor chip. Three-dimensional structured solder bumps are formed on the under barrier metal film, each of the solder bumps including a bar portion and a ball portion disposed at an end of the bar portion. The semiconductor chip including the three-dimensional structured solder bumps is bonded to a solder layer on a printed circuit board to complete a flip-chip package. According to the present invention, by employing the three-dimensional structured solder bumps, it is possible to lower the height of the solder bumps, thereby improving the reliability of an ultra thin flip-chip package.

This application claims priority from Korean Patent Application No. 2003-74660, filed on Oct. 24, 2003, the disclosure of which is incorporated herein by reference in its entirety.
1. Field of the Invention
This disclosure relates to a method of fabricating a semiconductor package, and more particularly, to a method of fabricating an ultra thin flip-chip package.
2. Description of the Related Art
To mount a semiconductor chip on a printed circuit board (PCB), flip-chip packaging can be used. Flip-chip packaging is a method of directly bonding a bond pad of a semiconductor chip to a PCB, and has advantages of occupying a small area and a fast operating speed.
FIGS. 1 through 8 are sectional views illustrating a conventional method of fabricating a flip-chip package.
Referring to FIG. 1, a semiconductor chip 17 including a bond pad 13 formed on a semiconductor substrate 11 and a passivation film pattern 15 partially exposing the bond pad 13 is prepared. A polyimide film pattern 19 exposing an upper surface of the bond pad 13 is formed on the passivation film pattern 15. The polyimide film pattern 19 protects the surface of the semiconductor chip 17.
A first under barrier metal film 21 is formed on the semiconductor chip 17 and the polyimide film pattern 19. Accordingly, a portion of the first under barrier metal film 21 is formed on the bond pad 13. The first under barrier metal film 21 is a composite film including a titanium film and a nickel film stacked sequentially.
Referring to FIG. 2, by forming a photoresist film on the first under barrier metal film 21 and patterning the photoresist film, a photoresist pattern 23 having a hole 22 exposing a region above the bond pad 13 is formed. The first under barrier metal film 21 on the bond pad 13 is exposed by the photoresist pattern 23.
Next, referring to FIG. 3, a second under barrier metal film 25 is then formed on the exposed portion of the first under barrier metal film 21. The second under barrier metal film 25 is formed by an electroplating method in which the photoresist pattern 23 is used as an electroplating-preventing film. The second under barrier metal film 25 is a nickel film.
Referring to FIG. 4, a solder bump 27 is formed on the second under barrier metal film 25 so as to fill the hole 22 of the photoresist pattern 23. The solder bump 27 is formed by an electroplating method in which the photoresist pattern 23 is used as a film for preventing an electroplating. The solder bump 27 is formed of an alloy film composed of lead and tin.
Referring to FIG. 5, the photoresist pattern 23 is removed. Then, referring to FIG. 6, the first under barrier metal film 21 is etched by using the solder bump as an etch mask. Accordingly, the first under barrier metal film 21 is disposed only below the second under barrier metal film 25.
Referring to FIGS. 7 and 8, a water-soluble flux 29 is coated on the resultant structure to cover the solder bump 27. Thereafter, the solder bump 27 is reflowed by a thermal process using the water-soluble flux 29, and is made in a rounded form. Then, although not shown in the drawings, the semiconductor chip 17 on which the solder bump 27 is formed is directly bonded to a PCB (not shown), thereby completing the fabrication of the flip-chip package.
The method of fabricating the flip-chip package in FIGS. 1 through 8 has the following drawbacks.
First, in the conventional method, the height of the solder bump 27 should be limited to a height of 100 μm so as to permit the packaging of the semiconductor chip. Due to this limitation, it is difficult to realize an ultra thin flip-chip package. Also, when the solder bump is made to the height of 100 μm, the height of the photoresist pattern used as the electroplating-preventing film should be at least 70 μm, which results in an increase in the fabrication costs.
Secondly, in the conventional method, since the increase in the integrity of a semiconductor chip requires the size of the bond pad and the height of the solder bump to be decreased, the structural reliability of the flip-chip package is lowered.
Thirdly, in the conventional method, since a joint crack generated in the solder layer is propagated after the bonding of the solder bump and the PCB, the structural reliability of the flip-chip package is lowered.
Fourthly, since the conventional method requires the complicated processes as illustrated in FIGS. 1 through 8, especially the reflow process of the solder bump, the flip-chip package is subject to thermal stress.

Method of fabricating ultra thin flip-chip package


A body mounted camera support for use with cameras of different sizes and types. This support provides a hands-free, secure support for the camera either in the horizontal or vertical position. The support includes a shoulder yoke for balance and support. Attached to the yoke, in front of the shoulder, by means of a securing device, is the hinged camera support arm. The arm has a telescoping vertical support which moves vertically and secures to the waist belt. The arm also uses a hinged, interlocking device to allow itself to sit securely either in the horizontal position while in use, or in the vertical position while at rest. The camera is connected to the support arm by means of the camera linking device, whose topside screws into the screw hole in the camera, and whose bottom side is secured into slots on the support arm. Attached around the yoke are two straps which go down the back of the user. The straps attach to a belt which goes around the user's waist. Attached to the waist belt are two pockets for the purpose of carrying accessories.

1. The filed of invention for the described invention relates to portable cameras and their accessories being supported and transported by the human body.
2. Video and film photography is a very important part of people's lives today, especially on vacation. With more and more people vacationing with small children, the ability to carry all the accessories, keep the children close by, and eat during the hectic vacation had become difficult. The use of a tripod or monopod is impractical since it adds to the things to be carried around.
This invention enables the user, any user of any age, to carry all the necessary accessories and support the camera hands-free in the two critical positions; horizontally, or in position to use the camera and vertically, or in position to store it securely when not in use. Since both are hands-free, the user can now use the camera or carry the camera while eating or keeping the kids close-by.
This carrier will also simplify the needs of those people who do videotaping such as weddings, news gathering, etc. by allowing the user to be completely mobile while carrying all the necessary pieces to do the job. This body mounted camera support is also terrific for 35 mm film camera use since it allows hands-free movement for the photographer and the ability to carry extra lenses, film, etc. without having to rely on pockets in clothing.
Several camera supports have been developed:
U.S. Pat. No. 4,895,286 to De Rosa; PA0 U.S. Pat. No. 4,437,753 to Dunn; PA0 U.S. Pat. No. 4,943,820 to Larock; PA0 U.S. Pat. No. 4,545,660 to Rudolph; PA0 U.S. Pat. No. 4,526,308 to Dovey; PA0 U.S. Pat. No. 4,244,500 to Fournier; PA0 U.S. Pat. No. 3,767,095 to Jones; PA0 U.S. Pat. No. 5,073,788 to Lingwall; PA0 None of them use the body as the main support PA0 None of them allow for shoulder adjustments PA0 None of them allow for the anatomical differences between men, women, and children PA0 None of them have hip pockets to carry the necessary accessories PA0 None of them have a hinged camera support that secures the camera next to the body and out of the way.
While all of the previous supports use some part of the body, they are all disadvantaged because:
These are the reasons that give this invention the definite advantage over all the others.


A semiconductor integrated circuit for use in a receiver can reduce fluctuations in characteristics caused by fluctuations in current to thereby reduce dissipation power. A bias current detection circuit and a current control circuit are provided to decrease a current of a high-frequency circuit if a bias current is large and, if the bias current is small, increase the current of the high-frequency circuit, so as to prevent characteristics of the high-frequency circuit from deteriorating and to reduce the current, thereby enabling reducing dissipation power.

1. Field of Invention
The present invention relates to an apparatus for correcting fluctuations in current through a semiconductor circuit so that its dissipation power can be reduced and, more specifically, technologies of a circuit current generation apparatus and method thereof, and a signal processing apparatus.
2. Description of Related Art
Recently, portable devices represented by portable telephones have come to be mounted with a variety of receivers, so that it has been required to greatly reduce power dissipated by the receivers. For example, some receivers used in analog TV sets conventionally dissipate power in excess of several hundreds milliwatt to one watt and so are not qualified for use in portable devices driven by batteries. However, digital TV sets for portable use to appear aftertime are required for a great cutback in dissipation power than ever; receivers thereof are required to have dissipation power of 100 mW or less.
To meet these requirements, circuits that constitute the receiver are mostly incorporated into a semiconductor integrated circuit, so that dissipation power of the semiconductor integrated circuit (hereinafter abbreviated as IC) determines that of the receiver.
However, manufacturing processes for an IC fluctuate significantly to fluctuate dissipation power of the IC by at least ±20% in some cases, so that a ratio between a maximum value and a minimum value of its current may become at least 1.5. Circuit performance of the receiver depends largely on high-frequency circuits. Further, a current value of the high-frequency circuits is larger than that of other bias circuits and low-frequency circuits; each of transistors thereof may require several milliamperes or more in some cases. Therefore, by reducing a current of the high-frequency circuit, dissipation power can be reduced effectively. Moreover, characteristics of the high-frequency circuit depend on a value of current through the circuit in many cases; in particular, an oscillation circuit in a local oscillator etc. may encounter a fatal problem of disruption of oscillation caused by a reduction in current. Therefore, how much a current can be reduced is limited by a value of a lowest current due to current fluctuations, thus constituting one of problems to be solved in reduction of dissipation power. Therefore, suppressing fluctuations in current is one of the important conditions for lower dissipation power.
Conventionally, a current value of a high-frequency circuit has been set with a sufficient margin for the purpose of prioritizing characteristics of the circuit, so that if the current value was too high, dissipation power of the circuit has been reduced to prevent a rise in temperature. For example, Japanese Patent Application Laid Open Publication No. Hei 9-107299 discloses taking countermeasures against a rise in dissipation current switchover temperature through a reception electric field. However, currently no measure is taken to solve deterioration in characteristics caused by fluctuations in current owing to fluctuations in manufacturing of an IC.
To solve these problems, a conventional method reduces a current of a high-frequency circuit itself and so has a problem of a deterioration in characteristics at a lowest current owing to current fluctuations as described above, which current fluctuations constitute an obstacle against a reduction in dissipation power of an IC because of a necessity to secure a margin for the current fluctuations.
Further, by reducing fluctuations in the processes and screening components in manufacturing processes, current fluctuations can be reduced, which approach, however, has a problem of increased costs and deteriorated productivity.

Circuit current generation apparatus and method thereof, and signal processing apparatus


On transistors P1, P2, N1 and N2 constituting an NAND gate, interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al1 and Al2 are stacked. A local line LL for connecting transistors P1, P2, N1 and N2 to each other is formed by the interconnection pattern W of metal having high melting point, signal lines SL and SL' for signal input/output between the NAND gate and the outside are formed by aluminum interconnection pattern Al1, and power supply lines VL and VL' for applying power supply potentials Vcc and Vss to the NAND gate are formed by the aluminum interconnection pattern Al2. As compared with the prior art in which the local line LL is formed by the aluminum interconnection pattern Al1, the degree of freedom in layout can be improved and the layout area can be reduced.

1. Field of the Invention
The present invention relates to a semiconductor integrated circuit. More specifically, the present invention relates to a semiconductor integrated circuit including a plurality of semiconductor element groups each having prescribed function, and first, second and third interconnection patterns stacked successively on the plurality of semiconductor element groups.
2. Description of the Background Art
In a semiconductor memory of mega bit order, especially in dynamic random access memories (hereinafter referred to as DRAMs), memory array architecture employing two layers of aluminum interconnection patterns Al1 and Al2 is dominant, as described in ESSCIRC PROCEEDINGS, September 1991 pp. 21-24.
FIG. 25 is a block diagram showing a structure of a conventional DRAM chip. Referring to the figure, the DRAM chip includes a plurality of memory array regions 31 and peripheral circuit region 32 provided between the memory array regions. Each memory array region 31 includes a plurality of sub arrays 33 arranged in the row direction, a plurality of sense amplifier bands 34 provided between and at opposite ends of sub arrays 33, a row decoder 35 and a column decoder 36. Peripheral circuit region 32 includes a plurality of NAND gates, NOR gates and the like.
The DRAM chip is, specifically, formed of a silicon substrate, a plurality of transistors and capacitors formed on the surface of the silicon substrate, and an interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al1 and Al2 stacked successively thereon.
FIG. 26 shows an example of a specific structure of the memory array region 31 of the DRAM chip shown in FIG. 25, which is a partial plan view showing the configuration of the sub array 33 and sense amplifier band 34. Referring to the figure, sub array 33 employs folded bit line structure and includes a plurality of memory cells MC arranged in the directions of rows and columns, and sense amplifier band 34 includes a plurality of sense amplifiers 34a provided corresponding to respective columns. In this region, the first layer of the high melting point metal interconnection pattern W is used as bit lines BL and /BL for connecting memory cells MC of each column to a sense amplifier 34a. The second layer, that is, the aluminum interconnection pattern Al1 is used as a part of a word line WL, and serves as a shunt for reducing time constant of the word line WL. The third layer, that is, the aluminum interconnection pattern Al2 is used as a column selection line CSL for transmitting an output from column decoder 36.
Bit lines BL and /BL are formed of the interconnection pattern W of metal having high melting point, in order to prevent migration of the material of bit lines BL and /BL to the silicon substrate. As the metal having high melting point, tungsten silicide (WSi) is used, as an example.
Though bit lines BL and /BL must have low resistance so as to increase the speed of data reading, what is more desirable is to reduce capacitance of the bit lines BL and /BL themselves to reduce power consumption, to increase the amount of read signal from memory cell MC so as to ensure operation margin, and to reduce capacitance between bit lines BL and /BL to reduce noise between bit lines BL and /BL, and therefore bit lines BL and /BL, that is, the interconnection pattern W of metal having high melting point, is made thin.
FIG. 27 shows an example of a specific structure of peripheral circuit region 32 of the DRAM chip shown in FIG. 25, and it is a partial plan view showing the layout of an area including a 2-input CMOS-NAND gate (hereinafter simply referred to as an NAND gate). FIG. 28 is an enlarged view of a main portion of FIG. 27. Referring to the figure, the NAND gate includes P channel MOS transistors P1 and P2 and N channel MOS transistors N1 and N2 arranged in two rows and two columns, and each of the transistors P1, P2, N1 and N2 includes a gate G extending in the Y direction in the figure and a source S and a drain D provided at opposing sides thereof. At one end of the gate G of each of the transistors P1, P2, N1 and N2, there is provided a pad PD, and pads PD of P channel MOS transistors P1 and P2 and pads PD of N channel MOS transistors N1 and N2 are provided adjacent to each other.
The third layer, that is, aluminum interconnection pattern Al2 used as the column selection line CSL in memory array region 31 is used in peripheral circuit region 32, as power supply lines VL and VL' and signal lines SL1, SL2, . . . ; SL1', SL2', . . . , extending in the X direction in the figure. Power supply line VL is provided to cover a P region in which two P channel MOS transistors P1 and P2 are arranged, and to the power supply line VL, power supply potential Vcc (H level) is applied. Power supply line VL' is provided to cover an N region in which two N channel MOS transistors N1 and N2 are arranged, and to the power supply line VL', power supply potential Vss (L level) is applied.
Signal lines SL1, SL2, . . . are provided outward from power supply line VL with a prescribed pitch therebetween, and these lines are used for signal input/output between the NAND gate portion and the outside. Signal lines SL1', SL2', . . . are provided outward from power supply line VL' with a prescribed pitch, and they are used for signal input/output between the NAND gate and the outside.
The second layer, that is, the aluminum interconnection pattern Al1 used as the shunt of word line WL in memory array region 31 is used, in this region, as a local line LL for internal connection of NAND gate.
More specifically, P channel MOS transistors P1 and P2 have their sources connected to local lines LL2 and LL3, respectively, through contact holes CH, while local lines LL2 and LL3 are connected via through holes TH to power supply line VL. P channel MOS transistors P1 and P2 and N channel MOS transistor N1 have their drains D connected to local line LL4 through contact holes CH, and local line LL4 is connected to signal line SL1', for example, via a through hole TH. Signal line SL1' serves as an output signal line for the NAND gate.
The source S of N channel MOS transistor N1 and the drain D of N channel MOS transistor N2 are commonly connected to local line LL5 through contact holes CH. N channel MOS transistor N2 has its source connected to local line LL6 through a contact hole CH, and local line LL6 is connected to power supply line VL' via a through hole TH.
P channel MOS transistor P1 and N channel MOS transistor N1 have their gates G commonly connected to local line LL1 through pads PD and contact holes CH, and local line LL1 is connected to signal line SL2, for example, via through hole TH. Signal line SL2 serves as one input signal line A of the NAND gate.
P channel MOS transistor P2 and N channel MOS transistor N2 have their gates G commonly connected to local line LL7 through pads PD and contact holes CH, and local line LL7 is connected to signal line CL3', for example, via through hole TH. Signal line SL3' serves as the other input signal line B of the NAND gate.
Transistors P1, P2, N1 and N2 constitute an electric circuit such as shown in FIG. 29, that is, a NAND gate generally represented by such signs as shown in FIG. 30.
In the conventional DRAM chip, the first layer, that is, the interconnection pattern W of metal having high melting point is used as bit lines BL and /BL in the memory array region 31, while it is hardly utilized in the peripheral circuit region 32. The reason for this is that the conventional interconnection pattern W of metal having high melting point which is formed of tungsten silicide (WSi) has high sheet resistance, resulting in significant signal delay when it is used as the local line LL for connecting transistors P1, P2, N1 and N2 between each other.
However, recently, interconnection pattern W of metal having high melting point having relatively small sheet resistance as compared with the conventional pattern has come to be available. Specific example of the material includes tungsten (W) and titanium silicide (TiSi). By using the interconnection pattern W of metal having high melting point formed of such material as the lines in peripheral circuit region 32, the problem of signal delay can be solved. Accordingly, a new layout utilizing the interconnection pattern w of metal having a high melting point, which has been used only as the bit lines BL and /BL in the prior art, becomes possible.

Semiconductor device comprising a plurality of interconnection patterns


In some example implementations, there is provided a method. The method may include generating a first page for presentation at a user interface, wherein the first page further comprises a first portion presenting one or more lines of code being developed and a toolbar portion, wherein the toolbar portion includes a comment element configured to generate a comment window and a propose change element configured to generate a change window; and receiving, in response to the generated first page, metadata including at least one of a comment and a proposed change associated with the one or more lines of code. Related systems, methods, and articles of manufacture are also provided.

Code development is considered an extremely complex process. So it is not surprising that code development is commonly done in teams. The coders in the team may be assigned portions of code to develop. And, at some point, these portions are combined and compiled into executable code, which when executed provides a system, such as an enterprise resource planning system and/or any other type of system as well. To reduce errors and enhance quality, team code development may also utilize pair wise coding, which refers to code being developed by at least a pair of coders working together. For example, a first coder may write a portion of code, which is then checked by a second coder.


Nanowire-based photodiodes are disclosed. The photodiodes include a first optical waveguide having a tapered first end, a second optical waveguide having a tapered second end, and at least one nanowire comprising at least one semiconductor material connecting the first and second ends in a bridging configuration. Methods of making the photodiodes are also disclosed.

Nanotechnology and quantum information technology involve the design of extremely small electronic and optical circuits. It would be desirable to provide nanometer-scaled, opto-electronic devices including nanowires that are suitable for nanotechnology and quantum information technology applications, where such devices offer efficient performance and can be fabricated by low-cost fabrication techniques in a manufacturing environment.

Nanowire photodiodes and methods of making nanowire photodiodes

Hewlett-Packard Development Company, L.P.


Corticotropin releasing factor (CRF) antagonists of Formula (I):

Corticotropin releasing factor (herein referred to as CRF), a 41 amino acid peptide, is the primary physiological regulator of proopiomelanocortin (POMC)-derived peptide secretion from the anterior pituitary gland [J. Rivier et al., Proc. Nat. Acad. Sci. (USA) 80:4851 (1983); W. Vale et al., Science 213:1394 (1981)]. In addition to its endocrine role at the pituitary gland, immunohistochemical localization of CRF has demonstrated that the hormone has a broad extra hypothalamic distribution in the central nervous system and produces a wide spectrum of autonomic, electrophysiological and behavioral effects consistent with a neurotransmitter or neuromodulator role in brain [W. Vale et al., Rec. Prog. Horm. Res. 39:245 (1983); G. F. Koob, Persp. Behav. Med. 2:39 (1985); E. B. De Souza et al., J. Neurosci. 5:3189 (1985)]. There is also evidence that CRF plays a significant role in integrating the response of the immune system to physiological, psychological, and immunological stressors [J. E. Blalock, Physiological Reviews 69:1 (1989); J. E. Morley, Life Sci. 41:527 (1987)].
Clinical data provide evidence that CRF has a role in psychiatric disorders and neurological diseases including depression, anxiety-related disorders and feeding disorders. A role for CRF has also been postulated in the etiology and pathophysiology of Alzheimer's disease, Parkinson's disease, Huntington's disease, progressive supranuclear palsy and amyotrophic lateral sclerosis as they relate to the dysfunction of CRF neurons in the central nervous system [for review see E. B. De Souza, Hosp. Practice 23:59 (1988)].
In affective disorder, or major depression, the concentration of CRF is significantly increased in the cerebrospinal fluid (CSF) of drug-free individuals [C. B. Nemeroff et al., Science 226:1342 (1984); C. M. Banki et al., Am. J. Psychiatry 144:873 (1987); R. D. France et al., Biol. Psychiatry 28:86 (1988); M. Arato et al., Biol Psychiatry 25:355 (1989)]. Furthermore, the density of CRF receptors is significantly decreased in the frontal cortex of suicide victims, consistent with a hypersecretion of CRF [C. B. Nemeroff et al., Arch. Gen. Psychiatry 45:577 (1988)]. In addition, there is a blunted adrenocorticotropin (ACTH) response to CRF (i.v. administered) observed in depressed patients [P. W. Gold et al. Am J. Psychiatry 141:619 (1984); F. Holsboer et al., Psychoneuroendocrinology 9:147 (1984); P. W. Gold et al., New Eng. Med. 314:1129 (1986)]. Preclinical studies in rats and non-human primates provide additional support for the hypothesis that hypersecretion of CRF may be involved in the symptoms seen in human depression [R. M. Sapolsky, Arch. Gen. Psychiatry 46:1047 (1989)]. There is preliminary evidence that tricyclic antidepressants can alter CRF levels and thus modulate the numbers of CRF receptors in brain [Grigoriadis et al., Neuropsychopharmacology 2:53 (1989)].
It has also been postulated that CRF has a role in the etiology of anxiety-related disorders. CRF produces anxiogenic effects in animals and interactions between benzodiazepine/non-benzodiazepine anxiolytics and CRF have been demonstrated in a variety of behavioral anxiety models [D. R. Britton et al., Life Sci. 31:363 (1982); C. W. Berridge and A. J., Dunn Regul. Peptides 16:83 (1986)]. Preliminary studies using the putative CRF receptor antagonist a-helical ovine CRF (9-41) in a variety of behavioral paradigms demonstrate that the antagonist produces "anxiolytic-like" effects that are qualitatively similar to the benzodiazepines [C. W. Berridge and A. J. Dunn Horm. Behav. 21:393 (1987), Brain Research Reviews 15:71 (1990)].
Neurochemical, endocrine and receptor binding studies have all demonstrated interactions between CRF and benzodiazepine anxiolytics, providing farther evidence for the involvement of CRF in these disorders. Chlordiazepoxide attenuates the "anxiogenic" effects of CRF in both the conflict test [K. T. Britton et al., Psychopharmacology 86:170 (1985); K. T. Britton et al., Psychopharmacology 94:306 (1988)] and in the acoustic startle test [N. R. Swerdlow et al., Psychopharmacology 88:147 (1986)] in rats. The benzodiazepine receptor antagonist (Ro15-1788), which was without behavioral activity alone in the operant conflict test, reversed the effects of CRF in a dose-dependent manner while the benzodiazepine inverse agonist (FG7142) enhanced the actions of CRF [K. T. Britton et al., Psychopharmacology 94:306 (19878)].
The mechanisms and sites of action through which the standard anxiolytics and antidepressants produce their therapeutic effects remain to be elucidated. It has been hypothesized however, that they are involved in the suppression of the CRF hypersecretion that is observed in these disorders. Of particular interest is that preliminary studies examining the effects of a CRF receptor antagonist (a-helical CRF9-41) in a variety of behavioral paradigms have demonstrated that the CRF antagonist produces "anxiolytic-like" effects qualitatively similar to the benzodiazepines [for review see G. F. Koob and K. T. Britton, In: Corticotropin-Releasing Factor: Basic and Clinical Studies of a Neuropeptide, E. B. De Souza and C. B. Nemeroff eds., CRC Press p 221 (1990)].
It has been further postulated that CRF has a role in cardiovascular or heart-related diseases as well as gastrointestinal disorders arising from stress such as hypertension, tachycardia and congestive heart failure, stroke, irritable bowel syndrome post-operative ileus and colonic hypersensitivity associated with psychopathological disturbance and stress [for reviews see E. D. DeSouza, C. B. Nemeroff, Editors; Corticotropin-Releasing Factor: Basic and Clinical Studies of a Neuropeptide, E. B. De Souza and C. B. Nemeroff eds., CRC Press p 221 (1990) and C. Maillot. M. Million, J. Y. Wei, A. Gauthier, Y. Tache, Gastroenterology, 119, 1569-1579 (2000)].
Over-expression or under-expression of CRF has been proposed as an underlying cause for several medical disorders. Such treatable disorders include, for example and without limitation: affective disorder, anxiety, depression, headache, irritable bowel syndrome, post-traumatic stress disorder, supranuclear palsy, immune suppression, Alzheimer's disease, gastrointestinal diseases, anorexia nervosa or other feeding disorder, drug addiction, drug or alcohol withdrawal symptoms, inflammatory diseases, cardiovascular or heart-related diseases, fertility problems, human immunodeficiency virus infections, hemorrhagic stress, obesity, infertility, head and spinal cord traumas, epilepsy, stroke, ulcers, amyotrophic lateral sclerosis, hypoglycemia, hypertension, tachycardia and congestive heart failure, stroke, osteoporosis, premature birth, psychosocial dwarfism, stress-induced fever, ulcer, diarrhea, post-operative ileus and colonic hypersensitivity associated with psychopathological disturbance and stress [for reviews see J. R. McCarthy, S. C. Heinrichs and D. E. Grigoriadis, Cur. Pharm. Res., 5289-315 (1999); P. J. Gilligan, D. W. Robertson and K. Zaczek, J. Medicinal Chem., 43, 1641-1660 (2000), G. P. Chrousos, Int. J. Obesity, 24, Suppl. 2, S50-S55 (2000); E. Webster, D. J. Torpy, I. J. Elenkov, G. P. Chrousos, Ann. N.Y. Acad. Sci., 840, 21-32 (1998); D. J. Newport and C. B. Nemeroff, Curr. Opin. Neurobiology, 10, 211-218 (2000); G. Mastorakos and I. Ilias, Ann. N.Y. Acad. Sci., 900, 95-106 (2000); M. J. Owens and C. B. Nemeroff, Expert Opin. Invest. Drugs, 8, 1849-1858 (1999); G. F. Koob, Ann. N.Y. Acad. Sci., 909, 170-185 (2000)].
The following publications each describe CRF antagonist compounds; however, none disclose the compounds provided herein: WO95/10506; WO99/51608; WO97/35539; WO99/01439; WO97/44308; WO97/35846; WO98/03510; WO99/11643; PCT/US99/18707; WO99/01454; and, WO00/01675.

4-(2-Butylamino)-2,7-dimethyl-8-(2-methyl-6-methoxypyrid-3-yl)pyrazolo-[1,5-A]-1,3,5-triazine, its enantiomers and pharmaceutically acceptable salts as corticotropin releasing factor receptor ligands

Abstract: and its use in treating anxiety, depression, and other psychiatric, neurological disorders as well as treatment of immunological, cardiovascular or heart-related diseases and colonic hypersensitivity associated with psychopathological disturbance and stress.


The present invention relates to a cosmetic composition for skin care, comprising coumestrol or a bean extract containing coumestrol.

As the average life span of human beings increases, it is becoming important how to maintain youth for a long time rather than how long to live. Aging is a process that cannot be avoided as one gets old. In particular, in the modern society where environmental pollution and stress are becoming severer and exposure to UV is increasing, aging starts earlier than before.
All human organs age gradually and skin aging is greatly affected by the external environment. Most of early skin aging begins with skin dryness. As the skin becomes dry, it loses elasticity and becomes prone to wrinkling. As skin aging proceeds, it takes longer for skin regeneration, the skin becomes rough due to keratinization, wrinkles are formed because of decreased collagen synthesis, pigmentation such as freckles, live spot, etc. occurs due to decreased defense against UV, and the skin becomes vulnerable to drugs or external stimulation because of decreased skin protection.

Cosmetic composition comprising coumestrol or a bean extract containing coumestrol for skin care


Ionographic imaging members include an electrically conductive layer and a dielectric layer which contains boron nitride. The dielectric layer may contain boron nitride alone or boron nitride dispersed in a binder. Methods are provided for preparing and using such imaging members.

This invention relates to ionographic imaging members and, more particularly to ionographic imaging members comprising an electrically conductive layer and a dielectric layer.
In ionography, a latent image is created by writing on the surf ace of the imaging member with an ion head. The imaging member is preferably electrically insulating so that the charge applied by the ion head does not disappear prior to development. Therefore, ionographic receivers possess negligible, if any, photosensitivity. The absence of photosensitivity provides considerable advantages in ionographic applications. For example, the electroreceptor enclosure does not have to be completely impermeable to light and radiant fusing can be used without having to shield the receptor from stray radiation. Also, the level of dark decay in these ionographic receivers is characteristically low, thus providing a constant voltage profile on the receiver surface over extended time periods.
Electroreceptors are useful in ionographic imaging and printing systems such as those commercially available as the Xerox Corporation 4060(tm) and the Xerox Corporation 4075(tm), which utilize an electrically resistive dielectric image receiver, i.e., an electroreceptor. In one simple form of the systems, latent images are formed by depositing ions in a prescribed pattern onto the electroreceptor surface with a linear array of ion emitting devices or ion heads, creating a latent electrostatic image. Electrostatic images of sufficient electric field and potential are created and retained at the surface of the electroreceptor. The latent image may be formed by applying a surface charge density on the receiver surface of from about 10 to about 100 nano-Coulombs per square centimeter. These electrostatic patterns are suitable for development with toner and developer compositions.
To develop latent images, charged toner particles are passed over these latent images, and the toner particles remain where a charge has previously been deposited. This developed image is then transferred to a substrate such as paper, and permanently affixed thereto.
An alternative developing method is liquid immersion development. In a liquid development process, a charged imaging surface is passed through a liquid medium which includes toner particles dispersed in a liquid carrier. Liquid development processes typically use a low molecular weight hydrocarbon as the liquid carrier.
A typical ionographic charge receiver, schematically shown in FIGURE 1, includes a conductive substrate 11 and a dielectric layer 12 positioned over the substrate 11. The substrate 11 depicted in FIGURE 1 is in the shape of an endless seamless belt.
It is important that the dielectric layer act as a loss-less capacitor, since the purpose of the dielectric layer is to store electric charge on its surface, minimizing the amount of charge that leaks therefrom. Any such leakage makes it necessary to provide greater amounts of charge initially. Similarly, it is preferable to provide a dielectric layer which does not permit charge to migrate into the bulk of the dielectric layer, which results in instabilities in capacitance and degrades image formation.
Prior art dielectric layers sometimes become degraded during use so that their loss-less character is impaired. Similarly, degradation can increase the possibility of charge migration in the dielectric layer. Thus, it is important that the dielectric layer be resistant to its operating environment, in particular, resistant to degradation brought about by the powerful oxidants and U.V. light emitted by corona charging devices which are typically used to form charge images. The dielectric layer should also have properties which are not substantially altered by changes in the temperature or humidity of its operating environment. Since typical toning and cleaning operations can be quite abrasive, it is important that the dielectric layer also be able to withstand significant abrasion, scratching and other physical wear related contacts.

Ionographic imaging members and methods for making and using same


Golf ball 2 has a center 8, a mid layer 10 and a cover 6. The base polymer of the mid layer 10 includes an ionomer resin as a principal component. The surface hardness H1s of the center 8 is greater than the hardness H2 of the mid layer 10. The Shore D hardness H3 of the cover 6 is equal to or greater than 57. The weight W2 of the mid layer 10 is greater than the weight W3 of the cover 6. The total weight (W2+W3) of the weight W2 of the mid layer 10 and the weight W3 of the cover 6 is 8.4 g or greater and less than 12.0 g. The total volume (V2+V3) of the volume V2 of the mid layer 10 and the volume V3 of the cover 6 is equal to or less than 10.0 cm3.

1. Field of the Invention
The present invention relates to golf balls. More particularly, the present invention relates to multi-piece golf balls having a center, a mid layer and a cover.
2. Description of the Related Art
Golf balls make a flight with accompanying back spin. Top concern to golf players for golf balls is their flight performances. The flight performance correlates with back spin rate. The flight with small spin rate results in an appropriate trajectory, whereby a great flight distance can be achieved. In light of the flight performance, golf balls which are less likely to be spun have been demanded.
Golf balls hit with an ideal swing are not accompanied by side spin. However, the side spin is inevitable according to common swings. Golf players expect golf balls that are excellent in the directional stability. The golf balls follow a curved trajectory owing to the side spin. Also in light of the directional stability, golf balls that are less likely to be spun have been desired.
The golf players place great importance also on feel at impact of the golf balls. Golf players prefer soft feel at impact.
Japanese Unexamined Patent Application Publication No. Hei 7-24085 (U.S. Pat. No. 5,553,852) discloses a golf ball having a center, a mid layer and a cover. The specific gravity of this mid layer is smaller than the specific gravity of the center. In this type of golf ball, the mass distribution has a disproportionate pattern indicating greater weighing in the inner part. This golf ball will generate excessive spin.
Japanese Unexamined Patent Application Publication No. Hei 9-313643 (U.S. Pat. No. 5,830,085) discloses a golf ball having a core, a mid layer and a cover. The hardness of this mid layer is greater than the surface hardness of the core. This mid layer may deteriorate the feel at impact of the golf ball.
Japanese Unexamined Patent Application Publication No. Hei 11-253578 (U.S. Pat. No. 6,129,640) discloses a golf ball having a core, a mid layer and a cover. This mid layer includes polyurethane as a principal component. Such a mid layer may deteriorate the resilience performance of the golf ball. This golf ball is inferior in the flight performances.
Japanese Unexamined Patent Application Publication No. 2006-289059 (US2006/211517) discloses a golf ball having a core, a mid layer, a reinforcing layer and a cover. In this type of golf ball, the mass distribution has a disproportionate pattern indicating greater weighing in the inner part. This golf ball will generate excessive spin.
Japanese Unexamined Patent Application Publication No. 2006-289060 (US2006/211517) discloses a golf ball having a core, a mid layer, a reinforcing layer and a cover. In this type of golf ball, the mass distribution has a disproportionate pattern indicating greater weighing in the inner part. This golf ball will generate excessive spin.
Requirements for golf balls by golf players have been increasingly escalated. An object of the present invention is to provide a golf ball that is excellent in the flight performance, directional stability and feel at impact.


A scaffold comprising at least two horizontally adjacent scaffold sections, the scaffold sections being defined substantially by lengthwise ledgers, transverse ledgers and uprights, characterized in that the scaffold comprises a guide adapted to be able to displace in substantially horizontal direction therealong a displaceable platform corresponding thereto and guided thereby; a method for erecting the scaffold, and a mobile platform.

It is known that erection and dismantling of a scaffold is very labour-intensive. This means that a relatively large amount of time is lost in the erection of particularly larger scaffolds. The physical load for people erecting the scaffold is further a heavy one, so that many people can only perform this task for a limited part of their life.
There is a need for scaffold systems which can be erected and dismantled relatively quickly.

Scaffold with scaffolding elements and methods for erection thereof


A method for using a silicon germanium (SiGe) surface layer to integrate a high-k dielectric layer into a semiconductor device. The method forms a SiGe surface layer on a substrate and deposits a high-k dielectric layer on the SiGe surface layer. An oxide layer, located between the high-k dielectric layer and an unreacted portion of the SiGe surface layer, is formed during one or both of deposition of the high-k dielectric layer and an annealing process after deposition of the high-k dielectric layer. The method further includes forming an electrode layer on the high-k dielectric layer.

In the semiconductor industry, the minimum feature sizes of microelectronic devices are approaching the deep sub-micron regime to meet the demand for faster, lower power microprocessors and digital circuits. The downscaling of CMOS devices imposes scaling constraints on the gate dielectric material. The thickness of the standard SiO2 gate dielectric oxide is approaching a level (˜10 angstroms (Å)) at which tunneling currents may significantly impact transistor performance. To increase device reliability and reduce electron leakage from the gate electrode to the transistor channel, semiconductor transistor technology is using high-k gate dielectric materials that allow increased physical thickness of the gate dielectric layer while maintaining an equivalent gate oxide thickness (EOT) of less than about 10 Å. The variable "k" refers to the dielectric constant of a material.
Integration of high-k materials into semiconductor microstructures can result in formation of an interfacial oxide (SiO2) layer due to oxidation of the Si substrate. The presence of an oxide interfacial layer lowers the overall dielectric constant of the microstructure, thereby reducing the advantage of using a high-k dielectric material instead of SiO2. To reduce the effect of an oxide interfacial layer on the overall dielectric constant of the microstructure, the oxide layer may need to be thin. Deposition of a high-k dielectric layer onto a Si substrate can result in uncontrolled growth of an oxide interfacial layer that is too thick for current semiconductor transistor technology.

Silicon germanium surface layer for high-k dielectric integration


The present invention is directed to a computer mouse cleaning apparatus for providing a cleaning mechanism including a cylindrical tube, a compressible rubber boot, a brush, and power source to allow a person to clean the inner portion of a computer mouse.

An object of this invention is to provide a computer mouse cleaning apparatus that is easy to use, small in size, and effective, without being costly. Another object of this invention is to create a compact device that creates a vacuum effect to remove any dirt or particles found in the inner portion of a computer mouse.


A process and machine for the preparation of pile ware uses a single needle bedded warp knitting machine, having pile sinkers. During the swing-through of the guides subsequent to the underlap into the overlap position, first the ground threads and then the left pile threads, are laid to the rear of the needles, and run along these, with separation from each other. The pile sinkers are introduced into the space between the ground threads and the left pile threads, during or after the swing-through, and stay there until the knock-over of the stitch. The threads are provided to the guide bars in a one full/one empty order, only every second needle serving for stitch formation. The number of pile sinkers equals half of the number of needles. Right pile threads are provided which are overreached by the pile sinkers together with the ground threads laid about needles not serving for stitch formation and are then knocked over.

1. Field of the Invention
The present invention relates to:
A. A process for the preparation of pile ware utilizing a single needle bed warp knitting machine, having pile sinkers, in which during the swing-through of the guides subsequent to the underlap, into the overlap position, first the ground threads and then the left pile threads are laid to the rear of the needles, and upon these needles with separation from each other, and in which the pile sinkers during or after the swing-through are introduced in the space between the needle ground threads and the left pile threads, and stay there until the knock-over of the stitch. PA1 B. The fabric produced thereby. PA1 C. A warp knitting machine for the production of such pile ware, comprising a needle bar, sidewardly displaceable guide bars for ground and left pile threads and a pile sinker bar whose pile sinkers may be swung into the needle gaps for the purpose of pile production, and thus may be led into the space between the ground threads and the left pile threads. When used to describe the fabric sides, the left and right refer to the technical back and technical face, respectively.
2. Description of Related Art
Such a procedure and such a warp knitting machine having pile sinkers moveable into the needle gaps are known from DE 38 278 265 C2. The pile sinkers are provided with a separation of one needle space. The guide bars are fully charged with ground and pile threads. There is thus provided a dense pile on the left side of the fabric.
In DE 11 88 754 C, it is known to anchor the pile threads in a first working cycle by stitch formation in the fabric ground and in the subsequent working cycle to lay threads around needles not participating in the formation of the ground ware, from which they are knocked over. This leads to a fabric having a half pile density. When the pile loops are located on the left side of the fabric, the loops must be additionally mechanically raised, for example, by means of a brush arrangement.
In DE 42 23 226 C2, there is a disclosure of the production of pile ware having pile provided on both sides of the fabric. For this purpose, pile sinkers resting permanently in the needle gaps are utilized by means of which the pile loops are provided to the left side, whereas on the opposite side loops are formed with the assistance of an additional hook bar. This latter however leads to a lower production speed since in the overlap phase utilizing the hooks, the thread reserve must be formed which leads to an interval in the stitch building process. Since, because of the positioning of the pile sinkers in the needle gaps, it is only possible to consider certain lapping patterns of ground threads, for example tricot, one can only obtain higher stability by means of additional weft threads, which stretch over the entire width of the machine, which necessitate the corresponding feeding arrangements.
The purpose of the present invention is to provide a new type of warp knitted fabric having pile loops on both sides thereof.

Single needle bed machine process for manufacturing of pile warp knit fabric


A magnetic actuator. A yoke includes a first opening and a second opening, a frame, and a path. A first magnet is disposed in the first opening in the vicinity of the frame. A second magnet is disposed in the second opening in the vicinity of the frame. A coil comprises a wire surrounding the path. A light shield is connected to an end of the coil. A guiding element disposed outside the path is connected to an end of the coil. When current passes through the coil, the coil moves along the path by magnetic induction between the first magnet and the second magnet such that the iris diaphragm is adjustable by the light shield. When there is no current through the coil, dynamic force produced by the guiding element returns the light shield to its original position.

The invention relates to a magnetic actuator, and in particular to a magnetic actuator used with an iris diaphragm.
Optical devices such as optical projectors, rear projectors, or cameras comprise a light control device such as an iris diaphragm controller, adjusting light intensity to produce images of different light intensity. Conventional iris diaphragms are controlled by a dynamic or magnetic mechanism. When the conventional iris diaphragm controller is not in use, however, the light shield automatically returns to its default position, normally by spring force.
A conventional iris diaphragm controller comprising elastic restoring force is shown in FIGS. 1A to 1E, comprising a yoke 10, a first magnet 11, a second magnet 12, a coil 15, a light shield 16, a shaft 17, and a spring 18. The yoke 10 is a rectangular piece with a hole 107 defined therein. Conventionally, the yoke 10 comprises two U-shaped pieces with ends thereof facing each other. The first magnet 11 and second magnet 12 are disposed in the hole 107 of the yoke 10, respectively on opposing sides thereof. The first magnet 11 and second magnet 12 are arranged with opposite polarities facing each other, as shown in FIG. 1C. The North pole of the first magnet 11 is located at the left side of the coil 15, and the South pole thereof is located at the right side. The polarity of the second magnet 12 is opposite that of the first magnet 11 such that an upward magnetic field is generated on the right side of the coil 15, and a downward magnetic field is generated on the left side. The coil 15 comprises electric wires, located between the first magnet 11 and the second magnet 12. The shaft 17 extending from a side of the coil 15 comprises an opening 170. The light shield 16 is connected to the coil 15 on an opposite end of the shaft 17. The light shield 16 is normally disposed along the light path, perpendicular to thereto to block light. The shaft 17 has a spring 18 disposed thereon. The spring 18 has two ends thereof fixed on the shaft 17 and the yoke 10, respectively.
As shown in FIGS. 1C to 1E, when current passes through the coil 15 in the direction shown by the solid arrows in FIG. 1D, since current flows from right to left on the upper side of the coil 15, the magnetic field is perpendicular thereto and oriented from the FIG. 1D. According to the right hand rule, the coil 15 produces upward force. Since the shaft 17 is connected to a side of the coil 15, and another shaft (not shown) pivots on the opening 170, the coil 15 moves with respect to the opening 170 as a center point along the cross section line A-A′. That is, the coil 15 moves counterclockwise as shown by the hollow arrow of FIG. 1D. The lower side of the coil 15 is used as an example. When current flows from left to right, the magnetic field is perpendicular thereto and oriented into the FIG. 1D. According to the right-hand-rule, the coil 15 produces upward force. The coil 15 moves around the opening 170 as a center point along the cross section line A-A′, in a counterclockwise direction shown by the hollow arrow of FIG. 1D. As a result, the coil 15 moves the light shield 16 with respect to the opening 170, as shown in FIG. 1E in a counterclockwise direction. If current volume is adjusted accurately, angle of the circular motion of the coil 15 can be controlled such that the light shield 16 controls the size of the iris diaphragm.
If there is no current through the coil 15, magnetic field between the coil 15 and the first and second magnets 11, 12 is not induced. After the spring 18 is extended, an elastic restoring force is generated. Consequently, the coil 15 is moved with respect to the opening 170 along the cross section line A-A′ in a clockwise direction, as shown by the hollow arrow in FIG. 1E. Thus, the spring 18 returns the coil 15, the shaft 17, and the light shield 16 to their original position.
However, the structure of the coil is complicated and difficult to fabricate, elevating manufacturing costs. Furthermore, since the magnetic fields generated by the magnetic structure thereof are not uniform, the relationship between the current volume in the coil and the circular motion is difficult to control. To achieve sufficient actuating force for the magnetic actuator, volume is increased. The width thereof cannot be reduced. Moreover, restoring force produced by the spring increases with extension of the spring, making it difficult to control. Lifetime of the spring is short, with elasticity thereof depleting over time.


In the preferred embodiment, a gate dielectric and an electrode are formed on a substrate. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. Spacers are preferably formed of SiCO based material or SiCN based material. The source and drain are then formed. A contact etch stop (CES) layer is formed on the source/drain regions and the spacers. The CES layer is preferably formed of SiCO based material or SiCN based material. An Inter-Level Dielectric (ILD) is then formed on the CES layer.

In deep sub micron microelectronic manufacturing, silicon nitride films are widely employed as stop layers during contact etching. As is well known in the art, the inter-level dielectric (ILD) is formed to provide insulation between the MOS devices and overlying metal lines that will be formed subsequently. The contact openings are made through the ILD layer to the source, drain and gate. The ILD layer is relatively thick, and it is hard to control the etching process in order to not over etch. The contact etch stop layer is formed prior to the formation of the ILD layer. A first highly selective etching is conducted to etch the ILD layer and stop at the etch stop layer. A second selective etching is conducted to etch the stop layer so that the underlying layer is exposed.
The conventionally used silicon nitride etch stop layer has several disadvantages. It has a high dielectric constant value (also known as k value), typically about 7.5 to 8. The high k value increases high parasitic capacitance, which degrades the device performance. Additionally, the deposition rate of the silicon nitride film is low and the deposition temperature is high, which are not desirable process characteristics.

Silicon oxycarbide and silicon carbonitride based materials for MOS devices

Taiwan Semiconductor Manfacturing Company, Ltd.


The contents of a cache of specialized code interpreted into an intermediate language may be recompiled for execution in a managed execution environment in accordance with an automated process in such a manner to minimize any impact on machine resources.

Software components may be distributed in an intermediate language (IL) format rather than in a native platform execution format at install time, and methods and systems have been developed to recompile the IL modules to native code. However, between install time and runtime, changes may be made to an application, program, method, function, or other assemblage of programmable and executable code to which the IL components correspond. Thus, components loaded at install time may not be useful at runtime.


A hydraulic system for actuating a clutch and/or a variable speed drive unit of a belt-driven conical-pulley transmission of a vehicle, such as a commercial vehicle, and having a variable transmission ratio and a torque sensor. The hydraulic system includes at least one hydraulic energy source. A selector and check valve is provided for supplying additional components besides the torque sensor and is connected between the hydraulic energy source, the additional components, and the torque sensor in such a way that the torque sensor includes priority in being supplied with hydraulic medium.

The present invention relates to a hydraulic system for actuating a clutch and/or a variable speed drive unit of a belt-driven conical-pulley transmission of a vehicle with a variable transmission ratio, in particular a commercial vehicle, and having at least one hydraulic energy source. In a preferred exemplary embodiment, the hydraulic system includes a torque sensor. However, the invention also includes exemplary embodiments without torque sensors.
An object of the invention is to provide a hydraulic system which enables greater efficiency or reduction in the size of the hydraulic energy source. In particular, the supplying of various components is to be improved.

LuK Lamellen und Kupplungsbau Beteiligungs KG