An analog/digital converter includes: a ramp signal generation circuit that generates a ramp signal; a comparison circuit that compares potential of an input analog signal with potential of the ramp signal and outputs a comparator output signal if the potential of the ramp signal satisfies the predetermined condition; a count control circuit that divides a predetermined ramp period in which the ramp signal generation circuit outputs the ramp signal into a predetermined number n of divided ramp periods and outputs a count-stop signal; a counter circuit that counts time in the divided ramp period and outputs a count value of the counted time; and a decoder circuit that generates a digital signal according to a count value and a digital value corresponding to any one of the divided ramp periods in which the counter circuit has started counting of time and outputs the generated digital signal.

Field of the Invention
The present invention relates to an analog/digital converter and a solid-state imaging device.
Description of the Related Art
In recent years, a complementary metal oxide semiconductor (CMOS) image sensor has gathered attention as a solid-state imaging device and has been practically used. The CMOS image sensor can be manufactured using an ordinary semiconductor manufacturing process, whereas a charge coupled device (CCD) image sensor is manufactured using a dedicated manufacturing process. Thus, a multi-functional CMOS image sensor can be realized by incorporating various functional circuits in the sensor, for example, as a system-on chip (SOC).
In recent years, there is an increasing number of examples of a solid-state imaging device including an analog/digital converter (hereinafter referred to as an "A/D conversion circuit") as a solid-state imaging device mounted on a digital camera, a digital video camera, or an endoscope. A single-slope A/D conversion circuit which uses ramp waves is used as an A/D conversion circuit included in such a solid-state imaging device. The single-slope A/D conversion circuit is provided in each column of a solid-state imaging device to form a single-slope column A/D conversion circuit (for example, see Japanese Patent No. 4655500). In the following description, an A/D conversion circuit is assumed to indicate a single-slope A/D conversion circuit.
FIG. 9 is a block diagram showing a schematic configuration of a conventional solid-state imaging device. A conventional solid-state imaging device 600 shown in FIG. 9 includes a vertical scanning circuit 601, a pixel array portion 602, an analog signal processing circuit 603, a ramp signal generation circuit (hereinafter referred to as "DAC") 604, a column A/D conversion circuit 605, a horizontal scanning circuit 606, and a control circuit 607.
The solid-state imaging device 600 removes noise from pixel signals output from respective pixels 61 in the pixel array portion 602, converts analog signals Vin obtained after the noise removal to digital signals Dout with the aid of A/D conversion circuits 609 provided in the column A/D conversion circuit 605, and sequentially outputs the digital signals Dout.
The vertical scanning circuit 601 selects the pixels 61 in the pixel array portion 602 disposed in each row of the pixel array portion 602 respectively according to a control signal input from the control circuit 607 and outputs pixel signals generated by the respective pixels 61 of the selected row to the analog signal processing circuit 603. In the following description, a period of time from a certain row of the pixel array portion 602 being selected to the next row being selected is referred to as a "horizontal period".
The pixel array portion 602 is a pixel array in which a plurality of pixels 61 are disposed 2-dimensionally in row and column directions. Each of the pixels 61 includes a photodiode, and the photodiode provided in the pixel 61 generates a pixel signal corresponding to the amount of light which is incident in a certain storage period. The pixel array portion 602 outputs a pixel signal generated by the selected pixel 61 to the analog signal processing circuit 603 according to the selection from the vertical scanning circuit 601.
The analog signal processing circuit 603 removes reset noise and 1/f noise from the pixel signal input from the pixel array portion 602 according to the control signal input from the control circuit 607 and amplifies the pixel signal obtained after the noise removal. The analog signal processing circuit 603 outputs the amplified pixel signal to the column A/D conversion circuit 605 as the analog signal Vin.
The DAC 604 generates a ramp wave Vramp, which is an analog signal of which the potential decreases with time at a certain rate in each horizontal period according to the control signal input from the control circuit 607, and outputs the generated ramp wave Vramp to the column A/D conversion circuit 605.
The control circuit 607 outputs a control signal configured to control the driving of the vertical scanning circuit 601, the analog signal processing circuit 603, the DAC 604, and the horizontal scanning circuit 606.
The column A/D conversion circuit 605 includes a number of A/D conversion circuits 609 corresponding to the number of columns of the pixels 61 disposed in the pixel array portion 602 each of the A/D conversion circuits 609 has the same configuration, which includes a comparator 62 and a data processing circuit 63 including a counter, a memory, and the like.
In the A/D conversion circuit 609 corresponding to each column of the pixel array portion 602, the comparator 62 performs a process (hereinafter referred to as a "comparison process") of comparing a potential of the input analog signal Vin and the potential of the ramp wave Vramp in each horizontal period. Moreover, in each A/D conversion circuit 609, the counter in the data processing circuit 63 counts the time (counts the number of clock cycles) from a time of an initial value of the ramp wave Vramp to a time of a completion of a comparison process of the comparator 62. Further, each A/D conversion circuit 609 outputs a digital signal indicating the time counted by the counter in the data processing circuit 63 as a digital signal Dout generated according to the magnitude of the analog signal Vin input to the A/D conversion circuit 609.
The horizontal scanning circuit 606 selects the digital signal Dout converted by each A/D conversion circuit 609 provided in the column A/D conversion circuit 605 in respective columns of the pixel array portion 602 according to the control signal input from the control circuit 607 and sequentially outputs the digital signal Dout of the selected column as the output of the solid-state imaging device 600.
In this manner, the conventional solid-state imaging device 600 outputs the digital signal Dout obtained by the column A/D conversion circuit 605 converting the analog signal Vin obtained after removing noise from the pixel signal generated by each pixel 61 of the pixel array portion 602.
Here, the operation of the A/D conversion circuit 609 provided in the conventional solid-state imaging device 600 will be described. FIG. 10 is a timing chart showing the operation of the A/D conversion circuit 609 provided in the conventional solid-state imaging device 600. FIG. 10 shows waveforms of the analog signal Vin and the ramp wave Vramp input to the comparator 62 provided in the A/D conversion circuit 609 in one horizontal period of the solid-state imaging device 600 and a comparator output signal CMPOUT output as a result of the comparison process of the comparator 62.
In an analog/digital conversion operation of the A/D conversion circuit 609, the comparator 62 provided in the A/D conversion circuit 609 compares the potential of the input analog signal Vin and the potential of the ramp wave Vramp in a reset period and a signal read period. More specifically, the comparator 62 compares the analog signal Vin with a reset level in the reset period and compares the analog signal Vin with a signal level in the signal read period. As shown in FIG. 10, the comparator 62 outputs the comparator output signal CMPOUT when the potential of the ramp wave Vramp is equal to or lower than the potential of the analog signal Vin in the respective periods.
In this case, the data processing circuit 63 provided in the A/D conversion circuit 609 counts the time (counts the number of clock cycles) from the time of the initial value ramp wave Vramp to a time at which the comparator output signal CMPOUT is output from the comparator 62 in each of the reset period and the signal read period. More specifically, the counter in the data processing circuit 63 counts the time (counts the number of clock cycles) of a period tr shown in FIG. 10, from the time of the initial value of the ramp wave Vramp to the time at which the comparison process of the comparator 62 is completed in the reset period. In this way, as shown in FIG. 10, a digital signal (that is, digital value Dr) corresponding to the magnitude (that is, the value of a reset signal of the pixel 61) of the reset level of the analog signal Vin is obtained. Moreover, the counter in the data processing circuit 63 counts the time (counts the number of clock cycles) of a period ts shown in FIG. 10, from the time of the initial value of the ramp wave Vramp to the time at which the comparison process of the comparator 62 is completed in the signal read period. In this way, as shown in FIG. 10, a digital signal (that is, digital value Dr+digital value Ds) corresponding to the magnitude (that is, the sum of the values of the reset signal and the pixel signal of the pixel 61) in which the reset level and the signal level of the analog signal Vin are combined is obtained.
The data processing circuit 63 outputs a digital signal Dout corresponding to the magnitude of the analog signal Vin input to the A/D conversion circuit 609 based on the digital signal indicating the time (the number of clock cycles) counted by the counter in the reset period and the signal read period. More specifically, the data processing circuit 63 performs a digital correlated double sampling (CDS) process of subtracting the digital signal (that is, digital value Dr) obtained in the reset period from the digital signal (that is, digital value Dr+digital value Ds) obtained in the signal read period and outputs a digital signal Dout having the value (that is, digital value Ds) of a pixel signal corresponding to the amount of light incident on the pixel 61.
In this manner, in the conventional solid-state imaging device 600, the counter in the data processing circuit 63 provided in each A/D conversion circuit 609 disposed in each column counts the time (counts the number of clock cycles) elapsed from the time of the initial value of the ramp wave Vramp to the time at which the comparison process of the comparator 62 is completed in each horizontal period, whereby the digital signal Dout having the value (that is, digital value Ds) of the pixel signal corresponding to the amount of light incident on the pixel 61 is output.

Analog/digital converter and solid-state imaging device


A urinary collection receptacle (10,50,650) with a handle seal (22,52,654) defining a handle opening is provided with one or more tear-controlling features to prevent a user from tearing through the handle seal when creating a spout to empty urine. The receptacle is be configured to require a user to create a generally linear tear (30) that extends from one edge (16) of the bag to the opposite edge (18) without passing through the handle seal. Alternatively a tear-stopping formation (62) is positioned adjacent to the handle seal to terminate a fear propagating toward the handle seal. Alternatively, a tear-starting formation (652) is positioned adjacent to the handle seal to direct a tear away from the handle seal. Such a receptacle further includes a frangible region that can be broken to dissociate a torn portion of the receptacle from the remainder of the receptacle.

Intermittent catheterization is a good option for many people who suffer from various abnormalities of the urinary system. Those with such abnormalities often find it desirable to use individually-packaged, sterile catheter assemblies designed for a single use. These catheter assemblies typically include a catheter that is advanced into the urethra to drain urine therefrom. The urine flows through the catheter and into a waste bag in fluid communication with the catheter. Urine is emptied from the bag and then the bag is disposed of.
Urinary collection bags may be differently configured, including the configuration shown in FIG. 1. In the embodiment of FIG. 1, a urinary collection bag B is formed of flexible first and second opposing walls defined by first and second sheet materials or by a single flexible sheet material folded in half in a V-shape format, which are joined about their perimeters at a perimeter seal P to define opposing edges L and R and opposing ends F and S. A handle seal H is defined adjacent to an intersection of one of the edges R and one of the ends F, which is typically the end F through which urine flows into the bag B. The handle seal H defines a handle opening O, into which a user may place one or more digits for handling and manipulating the bag B. Bag B includes a port A that defines a flow path into bag B and serves as an attachment point for the non-insertable end of a catheter.
As shown in FIG. 1, urine collection bag B may also include an anti-reflux valve V including a series of discrete tacks or welds spaced along the edge of anti-reflux valve V, as described in U.S. Patent Application Publication US2015/0105756, the contents of which are incorporated herein by reference.
According to one method of using the bag 13 of FIG. 1, the user creates a tear T in the bag B (FIG. 2) to create a spout for emptying urine from the bag B (e.g., into a toilet), while the bag B is separately disposed of (e.g., in a garbage can).
FIG. 2 illustrates a risk of using such a conventional bag B, which is that the tear T created by the user may extend from an edge L to and through the handle seal H. If such a tear T is created, then the handle opening O becomes unusable, which may lead to the user dropping the bag B or otherwise allowing urine to spill out of the bag B. Accordingly, it would be advantageous to provide a urinary collection bag or receptacle that decreases the risk of a user tearing through the handle seal.

Receptacles having tear-controlling features


The invention relates to an L-shaped supporting body for accommodating a fish and for conveying said fish tail first through a cutting unit having a circular blade pair of a fish processing apparatus, which has a continuously revolving conveyor, wherein the supporting body has a main body for fastening said supporting body to the conveyor and a bearing web, which protrudes beyond a side wall of the main body and which has a supporting edge arranged at the top for accommodating the backbone of the fish to be accommodated, the bearing web having a groove arranged on the underside, which groove is designed as a counter-support for the circular blade pair. In addition, the invention relates to a corresponding apparatus for processing fish.

1. Field of the Invention
The invention relates to an L-shaped supporting body for accommodating a fish and for conveying said fish tail first through a cutting unit with a circular blade pair of a fish processing apparatus, which has a continuously revolving conveyor, wherein the supporting body has a main body for fastening said supporting body to the conveyor and a bearing web, which protrudes beyond a side wall of the main body and which has a supporting edge arranged at the top for accommodating the backbone of the fish to be accommodated.
2. Related Technology
Moreover, the invention relates to an apparatus for processing fish, comprising a cutting unit, wherein the cutting unit has a circular blade pair for cutting free the backbone and a conveyor unit with a continuously revolving conveyor and at least one L-shaped supporting body for accommodating the fish and for conveying said fish tail first through the cutting unit wherein each supporting body has a main body attached to the conveyor and a bearing web protruding beyond a side wall of the main body and which has a supporting edge arranged at the top for accommodating the backbone of each fish to be processed.

Nordischer Maschinenbau Rud. Baader GmbH + Co. KG


A light-reflection band device has a protection band, a flexible plate disposed on the protection band, a base band disposed on the flexible plate, a transparent layer disposed on the base band, and a liquid solution and a large number of light-reflection particles disposed between the transparent layer and the base band. A periphery of the protection band, a periphery of the flexible plate, a periphery of the base band, and a periphery of the transparent layer are melted together.

The present invention relates to a light-reflection band device. More particularly, the present invention relates to a light-reflection band device which can reflect light at night.
Conventional light-reflection clothes often have a plurality of buttons. In general, the conventional light-reflection clothes are too large. Therefore, it is not convenient for the users to wear the light-reflection clothes.

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A power-supply unit for automobiles, connected to an electrically-driven brake device which generates braking forces by being electrically driven, an electric generator capable of generating braking forces for a vehicle by power generation, and a storage device for storing electric power, the power-supply unit comprising a first power supply line for connecting the electric generator with the storage device, a second power supply line for connecting the first power supply line with the electrically-driven brake device, and power-source connection means provided on the second power supply line and have interrupting function.

The present invention relates to a power-supply unit for automobiles, and more particular, to a power-supply unit for automobiles, in which electric power is supplied to an on-board electrically-driven brake device for generating braking forces with the use of electric power supplied from an electric power supply source.
Conventionally, an electrically-driven brake device for actuating electric motors with electric power and electric signals to generate braking forces has been known, which comprises two independent electric power sources E1, E2 and in which four wheel units are divided diagonally into two systems, the electric source E1 supplies energy to two wheel units for a left front wheel and a right rear wheel, and the electric source E2 supplies energy to two wheel units for a right front wheel and a left rear wheel (for example, see JP-A-2000-16262, page 3 & FIG. 1).
With the above device, a power-supply unit of the electrically-driven brake device comprises two electric power supply sources, and the two electric power supply sources independently supply electric power to the two divided systems of the device. Therefore, even when failure occurs in one of the electric power supply sources and so one system of the electrically-driven brake device does not operate normally, the other system of the electrically-driven brake device operates normally, so that it is possible to realize an electrically-driven brake device of high reliability.
In the above-described conventional electrically-driven brake device, reliability is heightened by the two electric power supply sources and the divided two systems, so that the electrically-driven brake device and the power-supply unit are in some cases made complex in constitution. In order to supply an electrically-driven brake device of high reliability while holding down an increase in cost, the electrically-driven brake device and the power-supply unit are desirably able to ensure sufficient braking forces at all times without complexity in constitution.

Power supply unit for automobiles, which can provide braking force even when abnormality occurs in the power supply unit of electrically driven brake devices


An exercise device having a base that forms a ring, and at least one connection point. A resistance band is connected to the connection point, and an anchor. The base may be moved in varying directions against resistance from the resistance band to provide exercise for a user.

1. Field of the Invention
The present invention relates generally to personal exercise or work-out devices. More particularly the present invention relates to an elastic based workout device capable of being used in multiple positions.
2. Description of Related Art
Today, even with added stress being placed upon physical fitness and body development, many people have found little or no time to devote to the physical fitness such as, going to the gym, or outdoor exercises such as participant sports, cycling, running, walking, etc. Many of these people have turned to mechanical devices designed to exercise the body in a multitude of ways during a short interval of use.
The exercising devices that have proven most effective and beneficial for general exercise are the well known tread mills, rowing machines and cycling machines. The primary drawback with these machines is their great expense for the average user, the large amount of floor space required for storage and use, and possible mechanical malfunction.
Further, many people do not live in homes that have space for these large indoor devices. Further still, going to the gym is not practical for many because of their busy schedules.
Therefore, what is needed is a device that may provide a full body workout in a short period of time, at a low cost and in a small space.


A vehicular lamp with a light source unit that includes a main reflector for reflecting light irradiated from a first light source, a projection lens that condenses and radiates light reflected by the main reflector, and a shade that blocks a part of the light reflected by the main reflector, wherein the light source unit further includes a second light source, which is disposed on the opposite side from the projection lens provided on the shade, and the shade is formed with a light transmission portion which is an opening that allows the light irradiated from the second light source to pass therethrough to the projection lens.

1. Field of the Invention
The present invention relates to a vehicular lamp having a projection lens that condenses light irradiated from the light source and more particularly to a vehicular lamp further provided with a second light source.
2. Description of the Related Art
Lamps known as projector-type lamps have recently been used as front lamps (headlamps) and auxiliary lamps (fog lamps) for automobiles. Such projector-type lamps generally include a projection lens that is formed by a condenser lens and is provided in front of the light source; and in such projector-type lamps, light irradiated from the light source is reflected by a reflector and condensed at a rear-side focal point of the projection lens or a nearby position thereof, so that the condensed light is projected by the projection lens. This type of projector-type lamps provide a wide illumination range while enabling downsizing of the light irradiation surface on the front surface of the lamp, and thus they are advantageous in terms of achieving lamps of a smaller size.
In addition, some projector-type lamps use a semiconductor light-emitting element, such as a light-emitting diode (LED), as the light source; and such projector-type lamps that use LEDs have been proposed greatly in recent years since such lamps further contribute downsizing of the reflector and projection lens as disclosed in, for example, United States Patent Application Publication No. 2006/0104077.
In such a projector-type lamp as described above, in order to obtain a targeted light distribution pattern (illumination pattern), a shade for blocking light is internally disposed so that it is located between the reflector and the projection lens. A part of light flux reflected by the reflector and incident to the projection lens is, as a result, blocked so that the light flux irradiated from the projection lens is limited.
The lamp disclosed in, for example, Japanese Patent Application Laid-Open (Kokai) No. 01-67804 is provided with a shade which is formed such that an upper edge portion thereof follows horizontal and oblique cut-off lines in order to provide a low-beam light distribution pattern for an automobile. Furthermore, the lamp proposed in the above-described publication has a configuration that a second light source is provided inside the lamp body, so that the second light source can be selectively lit in order to increase the variety of obtainable light distribution patterns and achieve light illumination that adapts to various running conditions of the automobile.
The lamp of the above-described publication uses incandescent bulbs for its light source (which is a first light source) and second light source. However, two incandescent bulbs inside the lamp results in an extremely large amount of heat when both incandescent bulbs are lit at the same time, thus resulting in an issue of heat release. Particularly problematic matters are significant temperature increases in the shade provided to face the first light source and of the projection lens provided to face the second light source. As a result, use of a semiconductor light-emitting element such as an LED for the second light source is a conceivable solution. For example, by using an LED as the second light source, at least the temperature increase in the opposing projection lens can be suppressed.
However, in the lamp of the above-described publication (Japanese Patent Application Laid-Open (Kokai) No. 01-67804), since the second light source is provided between the projection lens and the front side of the shade, the second light source is exposed through the projection lens and consequently worsens the overall outer appearance of the lamp. Also, since no shade to control the light flux with respect to the second light source is provided, it is difficult to secure a space for providing a shade. This in turn makes it difficult to provide a desired light distribution pattern when the second light source is lit.


A method and apparatus for efficiently switching cells through a switch fabric are provided. According to one aspect of the present invention, logic for forwarding and filtering multicast data is distributed among various layers of a network device, such as a switch, router, bridge, or the like. Data is received at a first port of an input/output (I/O) card. A multicast group identifier corresponding to the data is determined. The data and the multicast group identifier are then transferred to a switching card which indexes into a first set of correlation data with the multicast group identifier to identify a set of egress forwarding paths that lead to I/O cards having members of the multicast group. The switching card forwards the data to the I/O cards via the set of egress forwarding paths identified. For their part, the I/O cards identify a set of ports associated with the multicast group by indexing into a second set of correlation data and forwarding the data to each of the ports identified. According to another aspect of the present invention, a network device comprises a backplane, multiple I/O cards, and a switch core. Correlation data, e.g., in the form of tables indexed by multicast group identifiers, is distributed between the I/O cards and the switch core. The I/O cards each include multiple ports, a first set of correlation data, and a forwarding and filtering mechanism. The first set of correlation data maps multicast group identifiers to ports that are members of the corresponding multicast groups. The forwarding and filtering mechanism is configured to forward multicast data based upon the first set of correlation data The switch core includes a second set of correlation data and a forwarding and filtering mechanism. The switch core""s forwarding and filtering mechanism is configured to forward multicast data to member I/O cards based upon the second set of correlation data which maps multicast group identifiers to I/O cards that include member ports.

Contained herein is material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction of the patent disclosure by any person as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all rights to the copyright whatsoever.
1. Field of the Invention
The invention relates generally to the field of computer networking devices. More particularly, the invention relates to a method and apparatus for efficiently forwarding data, such as multicast data, from a source port to one or more destination ports of a networking device.
2. Description of the Related Art
Point-to-multipoint transmission is becoming increasingly important as the number of Internet and Local Area Network (LAN) applications that rely on multicast transmission continues to rise. As used herein xe2x80x9cmulticastxe2x80x9d refers to the transmission of information to a group of recipients (e.g., a multicast group) via a single transmission by the source. Without multicast services, applications dependent upon such services would be forced to send information to groups of users with unicast packets. This means that a server, for instance, would have to send an individual copy of each data packet to all the users in an interest group (e.g., a Virtual LAN (VLAN), or other multicast group, such as an Internet Protocol (IP) multicast group). Unicasting to dispersed groups of users is inefficient for both the data source and the network, thus, network-based multicast services allow servers and other data sources to send out a single packet that is automatically copied and distributed by network devices, such as backbone routers or switches, to every endstation in the target group of users. Network devices that are configured to process multicast traffic typically maintain an internal mapping of multicast groups to member ports. In this manner, the network device can avoid unnecessary flooding of the data by forwarding multicast traffic only on those interfaces known to reach a member of the specified multicast group.
A prior approach for internally mapping multicast groups to interfaces having members is illustrated with reference to FIG. 1. A network device 100 includes a plurality of ports 105-108, switching logic 115, and a shared memory 110. The switching logic 115 maintains one or more output queues 111-113 in the shared memory 110 for each of the plurality of ports 105-108. The switching logic 115 determines with which output queues to associate received multicast data with reference to a multicast table 120. The multicast table 120 maps multicast group identifiers to corresponding per port bit vectors that identify members of the multicast groups. A processor (not shown) within the network device 100 may execute one or more well known multicast protocols, such as a group membership protocol (e.g., Internet Group Management Protocol (IGMP)) and a multicast routing protocol (e.g., Multicast Open Shortest Path First (MOSPF), Distance Vector Multicast Routing Protocol (DVMRP), Protocol Independent Multicasting (PIM)), to facilitate initialization and maintenance of the multicast table 120.
Because the switching logic 115 operates at a port level, a disadvantage of this prior approach is that the switching logic 115 must keep track of a substantial number of output queues in the shared memory 110. Additionally, the switching logic 115 interfaces with each of the ports 105-108. As a result, the switching logic 115 is complex and inefficient. Therefore, a more efficient mechanism for forwarding data through a networking device is needed.
A method and apparatus for efficiently switching data through a switch fabric are described. According to one aspect of the present invention, logic for forwarding and filtering multicast data is distributed among various layers of a network device. Data is received at a first port of an input/output (I/O) card. A multicast group identifier corresponding to the data is determined. The data and the multicast group identifier are then transferred to a switching card which indexes into a fast set of correlation data with the multicast group identifier to identify a set of egress forwarding paths that lead to I/O cards having members of a multicast group corresponding to the multicast group identifier. The switching card forwards the data to the I/O cards via the set of egress forwarding paths identified. For their part, the I/O cards identify a set of ports associated with the multicast group by indexing into a second set of correlation data and forwarding the data to each of the ports identified. Advantageously, rather than tracking information for each port, the switching logic requires only general knowledge regarding which I/O cards have ports that are members of a multicast group, thereby offloading the switching logic and reducing the complexity of the switching logic.
According to another aspect of the present invention, a network device comprises a backplane, multiple I/O cards, and a switch core. Correlation data is distributed between the I/O cards and the switch core. The I/O cards each include multiple ports, a first set of correlation data, and a forwarding and filtering mechanism. The first set of correlation data maps multicast group identifiers to ports that are members of the corresponding multicast groups. The forwarding and filtering mechanism is configured to forward multicast data based upon the first set of correlation data. The switch core includes a second set of correlation data and a forwarding and filtering mechanism. The second set of correlation data maps multicast group identifiers to I/O cards that include one or more member ports. The switch core""s forwarding and filtering mechanism is configured to forward multicast data to member I/O cards based upon the second set of correlation data.
Other features of the present invention will be apparent from the accompanying drawings and from the detailed description which follows.

Efficient path based forwarding and multicast forwarding


A railbound manganese frog assembly having ramps and grooves adapted to receive the false flange formed on the rim of a worn railroad car wheel to prevent the flange from impacting components of the frog assembly.

A railroad frog is a device which is inserted at the intersection of a mainline rail and a turnout line rail to permit the flanges of wheels moving along one of the rails to pass across the other. The frog supports the wheels over the missing tread surface between the frog throat and the frog point and provides flangeways for aligning the wheels when passing over the point so that they will be afforded the maximum bearing area. Generally, standard turnout frogs may be classified as rigid frogs which have no movable parts or movable wing frogs in which one or both of the wings move outward to provide flangeways for railroad car wheels. The rigid frogs include manganese railbound frogs, solid manganese frogs and self guarded frogs. Movable frogs include railbound manganese spring frogs.
Rigid railbound manganese frogs are constructed by combining carbon steel rails with manganese steel castings. Railbound manganese spring frogs have a rigid, carbon steel, wing rail which encompasses a wing which is formed on a manganese steel cast insert and which is aligned substantially with a long point or heel rail connected to a turnout traffic rail and a flexible spring wing rail which is aligned substantially with a short point or heel rail which is connected to a mainline traffic rail.
Railbound manganese frogs are preferred over frogs which do not encompass manganese castings inasmuch as manganese steel has a resistance to abrasion and impact which exceeds that of carbon steel by as much as ten times.
In recent years, the frequency, the weight and the speed of rail traffic have increased. Consequently, the wear surfaces of manganese insert castings in railbound manganese frogs have been found to fail and become unacceptable for use within relatively short periods of time in certain zones. This increased wear and failure of the manganese insert casting has been found to occur primarily at three wheel transfer zones within the frog. The wear and failure occurs in these zones primarily because of wheel transfer impacts. Wheel transfer impacts normally occur as a result of an abrupt change in the path of a wheel and because of changes which occur in the wheel's profile as the wheel wears.
Railroad car wheels are made of either wrought steel or cast steel and have a carbon content of between 0.65% and 0.77% which approximately equals the carbon content of rail steel. Making the composition of railroad car wheels substantially the same as rails extends the wear life of both elements. However, when in use over a period of time the shape of a railroad car wheel changes substantially. This change in shape contributes greatly to failure of manganese insert castings caused by wheel transfer impacts as will be explained hereinbelow. The change in shape of a railroad car wheel with wear may be seen by referring to FIG. 3 of the drawings. This figure represents a part sectional view of the tread of a railroad car wheel. The dotted lines represent a new railroad car wheel whereas the solid lines depict a car wheel which has reached the condemning limits of wear and must be removed from service. When a wheel is new, the tread tapers inwardly from the inside of the flange to the outside edge of the wheel. This taper amounts to approximately one inch in twenty inches. In service, the inner vertical edge of the wheel flange bears against the gage side of a rail head, this being the side of the rail that faces the rail on the opposite side of the tie and the wheel tread bears against the top surface of a rail head. Consequently, the gage side of a wheel flange wears as does the tread of the wheel adjacent the flange. This wear may be seen by referring to FIG. 3 which illustrates the erosion of the gage side of the wheel flange and the loss of metal on the wheel tread adjacent the flange. The flange of a new wheel has a thickness of 1.375 inches and a depth of one inch. The wheel must be removed from service when the flange thickness decreases to 0.9375 inches or the flange depth increases to 1.50 inches. As a wheel wears, a false flange develops on the wheel opposite the flange which bears against the gage line of the rail. The false flange impacts the components of a manganese frog in the wheel transfer zones and contributes to or results in surface failure of the manganese insert castings.
As mentioned above, there are three primary transfer zones where the false flange formed on a worn railroad car wheel may cause damage to the manganese insert of a frog through impact. The first zone occurs at the toe end of the frog adjacent the throat of the insert. In this area the flange of a railroad car wheel transfers from a wing rail to a wing formed on the manganese insert as the wheel approaches the tip of the insert point moving in a facing direction. Movement in a facing direction for a railroad car wheel occurs as the wheel moves from the toe end of the frog to the heel end of a frog whereas a wheel undergoes a trailing direction movement when it passes from the heel end of a frog to the toe end of a frog. A second transfer zone where the false flange of a wheel may damage a surface of a manganese insert occurs as a wheel passes from a manganese wing to a running surface on the point of the insert. The third zone where the false flange on a railroad car wheel may impact a surface on the frog occurs at the heel end of the frog where a heel rail attaches to a heel extension formed at one end of the manganese insert point in alignment with the running surfaces of the point. In part, the impact is created by the physical discontinuity or gap which occurs at the interface of the manganese heel extension and the high carbon heel rail. In this location the traditional manganese casting has the smallest cross sectional area which gives rise to the greatest amount of wear.
Thus, it becomes desirable to provide manganese railroad frogs which accommodates worn railroad car wheels having false flanges in such a manner that the false flanges are prevented from impacting surfaces on the manganese casting to prevent unnecessary wear.


A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a processing engine and a memory system such that write data is buffered and information based upon reads and writes is recorded. Memory read data is returned speculatively since the packet processing engine is processing packets in parallel and not necessarily in sequence. Information is maintained allowing the detection of a speculative read that was incorrect (i.e. a memory conflict). When a memory conflict is detected, a restart signal is generated and the information for the associated packet identifier or sequence number is flushed.

Internet networking hardware involves processing of packets of information for many purposes and at many stages in a network. Routers, firewalls, gateways, load balancers and servers all process packets of information in some way. Where in the network the processing takes place (i.e. in the core or close to the edge) has a great deal to do with what types of processing needs to take place and how fast that processing must occur. In general, processing closer to the core takes place faster and involves less work. For example, many core routers perform only layer 2 packet forwarding (i.e. link layer header modification), which can be done with minimal processing overhead. Edge routers, however, typically perform more functions, such as traffic shaping, monitoring, billing and quality of service enforcement. In both situations, the need for processing is constantly evolving, and there is an increasing need to do more at faster rates.
Two key trends are the increase in network speed and the increase in the amount of processing that needs to take place at each stage in the network. Together these trends are forcing packet processing solutions into greater degrees of parallelism. FIG. 1 illustrates this point with four different scenarios for a packet processor. Here the term "packet processor" is used to generally refer to any processing engine that can perform programmable operations on packets of information.
In the first scenario of FIG. 1, the processing time of the packet is the same or smaller than the transmission time of the packet. In this scenario, the code need not be concerned with dependencies between packets, and ordinary single-threaded non-parallel processors can be used. In the other scenarios of FIG. 1, the processing time for a packet is substantially longer than the transmission time of one packet of information. The common trend is that the need for more complex operations (and thus larger workloads) and/or the increase in network speeds has lead to these situations.
In many cases the workload time is dominated by memory latency due to poor locality of data references and large working set sizes. This means that the limitation on packet throughput is driven by memory throughput, which has tended to increase at a rate even slower than single-threaded processor performance, further driving packet processing solutions into parallel packet processing scenarios.
In the case that all packets can be operated on independently, as shown in the second scenario of FIG. 1, processing can be pipelined neatly and no conflict arises between code processing simultaneous packets. This would be the case in certain types of stateless firewalls and forwarding engines, where each packet is evaluated according to static rules and does not depend on any other packets. Thus, no state is changed by packet that affects a future packet. The forwarding tables and firewall rules might be dynamically modified, but this typically happens on a time scale orders of magnitude greater then the time to process a single packet. A parallel packet processing solution for this second scenario is relatively easy to implement. The code working on one packet need not be aware of other packets and there is no need to synchronize memory operations between packets.
In the more general case that dependencies can arise between packets, a more complicated situation exists. This is shown in the third and fourth scenarios of FIG. 1. This would be the case if both packets are from the same TCP connection and due to, for example, encryption or TCP state maintenance, there is a need to update state in memory between the processing of the two packets. One or more memory locations written by one packet will be read by the other packet. Note that packet #3 in these scenarios is independent from both packets and can be processed as soon as it arrives.
Other examples in which packet dependencies can arise would be the updating of traffic management counters and the updating of routing or address translation tables. In the latter case, two packets may be dependent even if they are from completely independent connections if they hash to the same table entry. One packet may want to modify a table entry while another packet is querying the same entry. The fourth scenario in FIG. 1 illustrates that in some, if not most cases it does not matter which order two dependent packets are processed, as long as they are serialized to prevent incorrect results.
In these cases where simultaneous processing of packets is required, and where dependencies can exist between packets, it can be complicated to enforce those dependencies. Currently, there are two common approaches to this problem. The first solution is a software solution, where software locks are included in the code to cause dependent packet processing to be delayed until an earlier packet has been completed. These software semaphores are used to lock out subsequent dependent packets from accessing state until the first packet has updated it. The second solution involves hardware, where packet classification hardware serializes all packets that can possibly be dependent. In a multiprocessor, this can involve generating a hash function that sends all packets of the same flow to the same processor, and distributes the load across multiple processors.
Unfortunately, packet processing code is often large and complex and modifying it to incorporate new locking mechanisms is not trivial. Even when such code is relatively simple, guaranteeing that software locks have been correctly programmed for all possible network traffic scenarios can be hard to verify. Furthermore, requiring hardware to enforce sequentiality when it is not needed lowers performance. This is because often the entire packet processing is not dependent such that a partial overlap is possible. The importance of a partial overlap of packet workload can be appreciated by referring to FIG. 2. In the case that a packet reads data as its first instruction and writes that same address as its last instruction, indeed there can be no overlap of processing. This is generally not the case however. The second scenario of FIG. 2 illustrates the case that the second packet can start before the first packet is completed, even though they are dependent. It is also the case that due to conditional branches, packets that are sometimes dependent may not always be dependent. Thus conservative locking and large grained locking can yield significantly sub-optimal solutions.
It is also the case that hardware solutions that group flows for multiprocessors suffer from the problem of guaranteeing that the grouping is relatively uniform over time in order to balance work across the multiple processing elements. The classification of packets to direct them to processing elements is constrained by having to preserve correctness and can't take advantage of a more dynamic load balancing approach.
What is needed is a hardware mechanism to preserve packet dependencies without requiring changes to software and allowing optimal enforcement of dependencies, such that packets are not serialized unless necessary by the overlying application.

This patent is subject to a terminal disclaimer.

Method and apparatus for hardware enforced virtual sequentiality


A portable, flexible, fabric-composite-based, tank system with internal baffles capable for transporting water and other liquids on a non-dedicated truck is herein disclosed. A heavy textile tank is impregnated with a polytetrafluoroethylene (PTFE) is available in multiple sizes capable of being transported by pickup, flatbed or tractor-trailer trucks. The fabric tank have a series of internal inflatable baffles to aid in the stability of the tank by preventing sloshing of the liquid contents while traveling with the tank partially filled. The internal baffles inflate to sizes large enough to force liquids out of the tank through the discharge valve by displacing fluid with air without the need for a pump. When finished with use, the fabric tanks can be cleaned, dried, and collapsed for storage, thus allowing the truck's transport platform to be used for other tasks if necessary.

There are many areas of the world that are not provided with drinkable water by a centralized piping distribution system. In such cases, water is typically provided by tanker truck. The tanker truck is capable of delivering large quantities of water, or other liquids, where and when needed. However, the tanker truck has disadvantages. First, it is a dedicated vehicle, and as such is not suited for other uses when not serving as a liquid delivery vehicle. Second, when not in use, it requires considerable storage space. Third, it can be dangerous to transport a partially filled tank due to the effect sloshing liquid has on vehicle dynamics in panic or emergency driving situations. A final disadvantage is when removing the liquid from a tanker, a discharge pump is usually required to dispense the contained fluids. There does not exist an apparatus that addresses and solves the disadvantages as herein described. Accordingly, there is a need for a means by which large quantities of liquid can be transported without the disadvantages as listed above. The development of this invention fulfills these needs.

Transportable and collapsible fabric tank system with integral balloon baffle system


The invention includes methods of forming conductive metal silicides by reaction of metal with silicon. In one implementation, such a method includes providing a semiconductor substrate comprising an exposed elemental silicon containing surface. At least one of a crystalline form TiN, WN, elemental form W, or SiC comprising layer is deposited onto the exposed elemental silicon containing surface to a thickness no greater than 50 Angstroms. Such layer is exposed to plasma and a conductive reaction layer including at least one of an elemental metal or metal rich silicide is deposited onto the plasma exposed layer. At least one of metal of the conductive reaction layer or elemental silicon of the substrate is diffused along columnar grain boundaries of the crystalline form layer effective to cause a reaction of metal of the conductive reaction layer with elemental silicon of the substrate to form a conductive metal silicide comprising contact region electrically connecting the conductive reaction layer with the substrate. Other aspects and implementations are contemplated.

Integrated circuits typically use various combinations of insulative materials, conductive materials, and semiconductive materials (including conductively doped semiconductive materials). One type of conductive material which is utilized is elemental metals. In the context of this document, an "elemental metal" is defined to mean any one or more metal element(s) in element form, including any alloy of two or more metal elements. In many instances, it is desired to form a metal into electrical connection with a crystalline silicon substrate, for example conductively doped crystalline silicon. However, the physical contact of an elemental metal with a crystalline silicon substrate inherently creates undesired excessive electrical resistance between the two materials.
One common way of reducing this resistance is to form an interfacing silicide region at the junction or interface of the metal with the silicon. Thereby, a silicon-silicide-metal interfacing electrical connection is formed. One manner of forming the silicide is merely by heating the substrate with the two contacting layers to a suitable temperature for a sufficient period of time, typically in an inert atmosphere, to cause a reaction of metal and silicon to form the metal silicide. Alternately or in addition thereto, the deposition conditions for the metal material deposited over the silicon can be effectively high to impart a reaction of the depositing metal with the underlying silicon in situ during deposition. Regardless, the silicide which forms results from reaction of the metal with the underlying silicon substrate. The reaction is typically self-limiting such that further processing or exposure to temperature at some point stops resulting in silicide formation.
Integrated circuitry fabrication continues to strive to make ever denser and smaller electronic devices of the circuitry. One place where silicide contact structures are utilized is in the electrical connection of source/drain diffusion regions of field effect transistors with overlying conductive metal lines. As the device components get smaller and denser, it is highly desirable to precisely control the amount of silicide which is formed in such contacts, as well as in other devices where silicide interfaces between metal and silicon are desired to be formed. For example in some instances in present-generation processing, it is desirable to fabricate the silicide regions over the substrates to have thicknesses of from 50 Angstroms to 100 Angstroms. Further, it is expected that the thickness of silicide regions in later-generation processing will fall below 50 Angstroms. Regardless, the variation in thickness of silicide regions formed over a substrate using typical prior art processing has been found to be anywhere from 20 Angstroms to 25 Angstroms across the substrate. This variability is undesirable and constitutes a 20% to 25% thickness variation for desired 100 Angstroms thick silicide regions, and a 40% to 50% variation in thickness for desired 50 Angstroms thick silicide regions. It would be desirable to develop methods which enable tighter thickness control of silicide regions which are formed across a substrate, and particularly where the silicide regions being formed have thicknesses that are no greater than 100 Angstroms where the above problem particularly manifests.
While the invention was motivated in addressing the above described issues, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded, without interpretative or other limiting reference to the specification, and in accordance with the doctrine of equivalents.


A method, system and program product for controlling memory overload for a computer system. The invention determines heap utilization of a server; determines a maximum session lifetime a configured percentile of at least one session; determines a traffic rate (comprised of an average traffic rate received from a proxy server and a variance of traffic rate received from a proxy server); and calculates a maximum traffic rate, wherein the maximum traffic rate determines the heap utilization at a maximum heap percentage.

In a typical computer system topology, a proxy server receives work and forwards that work to a server. If a traffic rate, the rate at which proxy server sends work to server, is too rapid, server can run out of one or more resources required to perform work. If traffic rate is too slow, throughput can be suboptimal. An alternation between too rapid and too slow subjects server to erratic work flow creating difficulties for optimizing heap utilization.
One requirement of memory overload protection is that proxy server must not forward work to server too quickly. Otherwise an out-of-memory exception may occur.
Another requirement of memory overload protection is that proxy server must forward work to server quickly enough in order to make good use of the memory resources of server. Further, overall throughput to server must not be too erratic.

International Business Machines Corporation


A rechargeable battery includes an electrode assembly comprising a positive electrode, a negative electrode, and a separator interposed therebetween, the electrode assembly having an uncoated region; a case for housing the electrode assembly; an outer terminal; a cap assembly combined with the case and sealing the case, and combined with the outer terminal; and a tab. The tab includes a terminal element connected with the outer terminal; left and right connection elements extended from ends of the terminal element and disposed to correspond to each other in parallel; and left and right inward junction elements connected at respective sides of the left and right connection elements through respective bending areas to form gaps relative to a part of the respective left and right connection elements and electrically connected with the uncoated region of the electrode assembly through the gaps.

Rechargeable batteries generally include an electrode assembly which is formed by spirally winding sheet-shaped positive and negative electrodes and a separator serving as an insulator, or by stacking positive and negative electrodes and an insulating separator in a multi-layer structure. Leads or tabs are attached to the electrodes and to outer terminals.
Since large-capacity batteries for so-called Hybrid Electric Vehicles (HEVs) have bigger positive and negative electrodes in proportion to the size thereof, and thereby have increased resistances, they need a separate tab to maximize a current collecting area. Such a tab can connect an uncoated region of an electrode assembly with a terminal in a prismatic secondary battery.

Rechargeable battery and method of manufacturing the same


Embodiments of methods and/or apparatus for 3-D volume image reconstruction of a subject, executed at least in part on a computer for use with a digital radiographic apparatus, can obtain image data for 2-D projection images over a range of scan angles. For each of the plurality of projection images, an enhanced projection image can be generated. In one embodiment, a first scatter intensity distribution through the plurality of projection images can be modulated based on a first scaling function and a SPR to generate a second scatter intensity distribution through the plurality of projection images, which can be combined with the original plurality of projection images.

Cone-beam computed tomography or CBCT scanning makes it possible to improve image capture and processing speeds by directing a cone-beam source through the patient or other subject to obtain an image on a flat-panel X-ray detector. In cone-beam computed tomography scanning, a volume or 3-D image is reconstructed from numerous individual scan projections, each taken at a different angle, whose image data is aligned and processed in order to generate and present data as a collection of volume pixels or voxels.
Generation of scatter in X-ray radiographic and flat panel based CT imaging is very complex. Incident X-ray photons are scattered inside the object, and when scattered photons reach the detector, an overestimation of the registered total intensity in each projection, which can be equivalent to an underestimation of attenuation coefficients associated with the materials inside the object, can result. Scatter may lead to image artifacts such as "cupping" in homogeneous object or dark streaks between image regions of high attenuation. As a result of the contamination of collected data with scattered photons, the low-contrast detectability of a CBCT system is decreased.
Related art scatter correction methods can include hardware scatter rejection (e.g., systems equipped with bowtie filter and/or anti-scatter grids), measurement of scatter using beam stop methods, or image processing methods (e.g., software applications) such as Monte Carlo modeling of photon transport through the patient, convolution-superposition methods, analytical scatter models, heuristic methods based on approximate geometry; or image enhancement methods.
Cone-beam computed tomography (CBCT) scanning is of significant interest for applications such as biomedical, dental, and industrial applications.
Improved scatter correction or image processing methods of scatter correction on projection images that can reduce artifacts in the reconstructed image domain is desirable. There is a compelling need for improved methods for scatter correction in volume imaging techniques.

Methods and apparatus for scatter correction for CBCT system and cone-beam image reconstruction


Embedded controller(s) in an information handling system have real-time status and activities represented by indicators, such as light emitting diodes (LEDs), associated with the embedded controller(s). These indicators may be monitored for example by operating (management software, e.g., Embedded Server Management (ESM) software. In addition, edge triggered latches and a timer detect and store flash patterns of these LED indicators so that the flash pattern information may be read by the operating management software as static signals.

1. Field of the Invention
The present invention is related to information handling systems, and more specifically, to providing real-time status of embedded controllers in the information handling systems.
2. Description of the Related Art
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes, thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems, e.g., computer, personal computer workstation, portable computer, computer server, print server, network router, network hub, network switch, storage area network disk array, RAID disk system and telecommunications switch.
Recent trends in information handling systems such as workstations, computer servers and associated storage disk arrays are being developed with embedded high-speed input/output (I/O) controllers, e.g., Gigabit Ethernet and Fibre Channel controllers, and the like. Typically, these embedded controllers have light emitting diodes (LEDs) proximate their I/O connectors to indicate link/activity status of the high-speed connection thereto. These LEDs are usually the only indication of a specific controller's status and/or activities.
While static information from, e.g., plug and play, and power-on system testing (POST) may disclose the presence of embedded controllers in an information handling system, there is no way of determining remotely, e.g., software monitoring and display screens, the health and/or activities of these embedded controllers.
A prior technology, represented in U.S. Pat. No. 5,761,527, obtains PCI bus hard disk activity information by monitoring the PCI GNT signal. The advantage of this technology is that it can be adapted to both PCI add-on cards and embedded PCI devices. However, the PCI GNT signal does not represent an accurate indication of the activity on high-speed Ethernet or fibre channel (FC) networks because the Ethernet and FC controllers often buffer large blocks of data before going onto the PCI bus to request the host processor to process the data. Thus, PCI bus activity cannot properly represent either Ethernet or FC network activities. Other existing technologies may display the static characteristics of the controllers such as IP address, storage area network (SAN) connectivity, and the like.
Therefore, a problem exists, and a solution is required for monitoring real-time status and activity information of embedded controllers in information handling systems.

Method, system and apparatus for providing real-time led status of embedded controllers to system management software


Swellable metal assemblies that have a reactive metal and a polymer, and are located around or inside an oilfield tubular. The oilfield tubular and the swellable metal assembly can be provided in a wellbore to form a seal therein.

When drilling a wellbore into a subterranean formation for the purposes of hydrocarbon or other fluid recovery from a subterranean formation, seals can be provided in the annulus between an oilfield tubular and the wellbore or casing for various purposes. Seals can also be provided inside an oilfield tubular for various purposes.
Corrosion from high salinity and/or high temperature environments is an ongoing challenge with seal integrity. Moreover, wellbore operations can be affected until the seal is formed; thus, faster sealing times can improve wellbore operations.

Thermoplastic with swellable metal for enhanced seal


According to one embodiment taught herein, a method of determining impairment correlations between a plurality of delays of interest for a received CDMA signal comprises generating kernel functions as samples of a net channel response of the received CDMA signal taken at defined chip sampling phases for delay differences between the plurality of delays of interest. In a parametric Generalized Rake (G-Rake) receiver embodiment, the delays of interest represent the delay positions of the fingers being used to characterized received signal. In a chip equalizer receiver embodiment, the delays of interest represent the delay positions of the equalizer taps. The method continues with determining impairment correlations based on convolving the kernel functions. Corresponding receiver circuits, including an impairment correlation estimation circuit configured for parametric G-Rake operation, may be implemented in a variety of communication devices and systems, such as in wireless communication network base stations and mobile stations.

Interference cancellation stands as an important component of contemporary and developing communication systems. For example, interference cancellation performance affects transmission power requirements and link utilization efficiencies in both the uplinks and downlinks of wireless communication systems, such as cellular communication networks based on the Wideband Code Division Multiple Access (WCDMA) or IS-2000 standards. Put simply, better interference cancellation enables data transmission at lower power levels and/or at higher data rates than would otherwise be possible.
As might be expected, the particulars of interference cancellation vary as a function of many variables, such as the communication signal types and protocols involved, details of the transmitting and receiving equipment, etc. However, providing good interference cancellation performance not infrequently requires significant signal processing resources, owing to the need for characterizing and suppressing received signal interference in real time.
For example, G-Rake receivers use extra despreading fingers to improve demodulation. To determine the finger delays, a probing approach may be used, in which weights are computed for a candidate set of delays and then re-computed for a selected set of finger delays. In general, candidate delays and finger delays are referred to as processing delays. Similarly, chip equalizers use processing delays corresponding to equalizer tap locations.
Impairment cross-correlations can be represented as an impairment covariance matrix Ru, and that matrix in turn can be used to generate the combining weights used by the G-Rake receiver in combining despread data values. By computing the combining weight vector, w, as,w=Ru−1h  Eq. (1)the G-Rake receiver uses the impairment covariance matrix to whiten colored interference in the received signal(s) of interest, where h is the net channel response vector.
There are several approaches for generating Ru in the G-Rake context, depending on the involved variant of G-Rake receiver. For example, "parametric" G-Rake receivers consider the impairments covariance matrix as a sum or combination of different interference contributions, including contributions from own-cell interference, white noise, and other-cell interference. With this parametric model, and assuming the reception of signals from J+1 network base stations, the impairment covariance matrix is given by
                              R          u                =                                                            E                c                                                          R                I                                      +                                          N                0                                                          R                n                                      +                                          ∑                                  j                  =                  1                                J                                                                                E                  c                  j                                                                  R                  O                  j                                                              =                                                    N                0                                                          R                n                                      +                                          ∑                                  j                  =                  0                                J                                                                                E                  c                  j                                                                  R                  O                  j                                                      -                          hh              H                                                          Eq        .                                                    (          2          )                    where Ec=average energy transmitted per chip of own-cell base station, N0=one-sided power spectral density of white noise, Ecj=average energy transmitted per chip of jth other-cell base station, RI=own-cell interference covariance matrix, Rn=white noise passed through pulse shaping filter covariance matrix, and ROj=jth other-cell interference covariance matrix. (Note that the second formulation of Eq. (2) emphasizes that the own-cell interference term can be computed in a fashion similar to that used for other-cell interference, provided that a benign signal term is subtracted—e.g., RI=RO0−hhH. Assuming that other-cell interference is not modeled as white noise, the computation of RI contributes significantly to the overall complexity of a parametric G-Rake receiver operation.
One mechanism for calculating entries for RI is given by,
                                          R            I                                          (                                          d                1                            ,                              d                2                                      )                          =                              ∑                          l              =              0                                      L              -              1                                                                                ∑                              q                =                0                                            L                -                1                                                                                g                l                                                          g                q                *                                                                            ∑                                                            m                      =                                              -                        ∞                                                              ,                                          m                      ≠                      0                                                                            m                    =                    ∞                                                                                R                      p                                                                                (                                                                        d                          1                                                -                                                  mT                          c                                                -                                                  τ                          l                                                                    )                                                                                R                      p                      *                                                                                (                                                                        d                          2                                                -                                                  mT                          c                                                -                                                  τ                          q                                                                    )                                                                                Eq        .                                                    (          3          )                    where gl represents the lth medium coefficient, dk is the kth finger delay, τj is the jth channel delay, Tc is a CDMA chip period, and Rp(*) is the autocorrelation of the receive pulse shaping filter. (Note that if the transmit and receive pulse filters are not the same, then Rp(*) includes convolution of the transmit and receive pulse filters.)
By manipulation, Eq. (3) is shown to be equivalent to
                                                        R              I                                                  (                                                d                  1                                ,                                  d                  2                                            )                                =                                    ∑                              l                =                0                                            L                -                1                                                                                ∑                                  q                  =                  0                                                  L                  -                  1                                                                                g                  l                                                                                g                    q                    *                                                                          [                                                                                R                          pp                                                                                (                                                                                Δ                              1                                                        -                                                          Δ                              2                                                                                )                                                                    -                                                                                R                            p                                                                                (                                                          Δ                              1                                                        )                                                                                R                            p                            *                                                                                (                                                          Δ                              2                                                        )                                                                                ]                                                                                where                                                                                Δ              1                        =                                                            d                  1                                -                                                      τ                    l                                                                                and                                                                                Δ                    2                                                              =                                                d                  2                                -                                  τ                  q                                                              ,                                                                              and                                                                                R                  pp                                                                  (                                                            Δ                      1                                        -                                          Δ                      2                                                        )                                                      =                                          ∑                                  m                  =                                      -                    ∞                                                  ∞                                                                                R                    p                                                                          (                                                                  Δ                        1                                            -                                              mT                        c                                                              )                                                                                R                      p                      *                                                                                (                                                                        Δ                          2                                                -                                                  mT                          c                                                                    )                                                        .                                                                                Eq        .                                                    (          4          )                    Rpp(*) can be pre-computed, thereby saving run-time computations, such that the signal processing implementation of Eq. (4) reduces to a few table lookups and a multiplication. However, the table lookup for Rpp(*) is somewhat complicated because it depends not only on the difference between Δ1 and Δ2, but also at what sample phase the difference occurs. Also, because Rpp(*) is not symmetric, one must also account for positive and negative delay differences in selecting lookup table entries.
Because of the above complications, the required table lookup operations depend on a greater number of variables, meaning more processing decisions have to be made to identify proper table entries, which in turn requires greater processing power or speed and a greater amount of working memory. Such complications detract from the efficiency gains otherwise afforded by the implementation of Eq. (4) for RI computation in a parametric G-Rake receiver.
Another approach expresses RI as,
                                                                                R                  I                                                                  (                                                            d                      1                                        ,                                          d                      2                                                        )                                            =                                                                    ∑                                          l                      =                      0                                                              L                      -                      1                                                                                ∑                                              q                        =                        0                                                                    L                        -                        1                                                                                g                        l                                                                                g                          q                          *                                                [                                                                              R                                                                                (                                                                                n                                  1                                                                ,                                                                  n                                  2                                                                                )                                                                                -                                                                                1                                                              N                                2                                                                                ∑                                                                  m                                  =                                                                      1                                    -                                    N                                                                                N                                  -                                  1                                                                                (                                                                      N                                    -                                                                                                                  m                                                                                                                  )                                                                                R                          p                                                (                                                                              d                            1                                                    -                                                                                mT                        c                                                                                -                                  τ                  l                                                      )                                                        R              p              *                                                  (                                                d                  2                                -                                  mT                  c                                -                                  τ                  q                                            )                                      ]                            Eq        .                                                    (          5          )                    From inspection, Eq. (5) has similarities to the formulation given in Eq. (4) but with R(n1,n2) equivalent to (and replacing) Rpp(*), and a more complicated expression involving the sum of products of Rp(*). Under limited reception conditions—i.e., minimal time dispersion in the propagation channel—the lookup tables for R(n1,n2) and Rp(*) need only span a few CDMA spreading chips to yield acceptable performance. However, Eq. (5) does not necessarily yield good performance over a range of channel conditions, and still entails significant computational complexity.

Method and apparatus for interference estimation in a generalized RAKE receiver


The invention provides a substrate for an electronic device including a conductive oxide layer which is formed by epitaxial growth with cubic crystal (100) orientation or pseudo-cubic crystal (100) orientation and which contains a metal oxide having a perovskite structure, a method for manufacturing a substrate for an electronic device, and an electronic device provided with such a substrate for an electronic device. A substrate for an electronic device includes a Si substrate, a buffer layer which is formed by epitaxial growth on the Si substrate and which contains a metal oxide having a NaCl structure, and a conductive oxide layer which is formed by epitaxial growth with cubic crystal (100) orientation or pseudo-cubic crystal (100) orientation on the buffer layer and which contains a metal oxide having a perovskite structure. The Si substrate is preferably a (100) substrate or a (110) substrate from which a natural oxidation film is not removed. The buffer layer preferably has an average thickness of 10 nm or less.

1. Field of Invention
The present invention relates to a substrate for an electronic device, a method for manufacturing this substrate for an electronic device, and an electronic device.
2. Description of the Related Art
In the related art, ferroelectric memories which are nonvolatile memories using ferroelectrics has been used.
These ferroelectric memories are classified into a capacitor type, in which a 1T/1C structure, etc., is formed using ferroelectrics as capacitors, and an MFSFET type, in which ferroelectrics are used as gate insulating films of field-effect transistors in place of SiO2.
The MFSFET type ferroelectric memory has advantages over the capacitor type, for example, it increases the packing density and non-destructive read-out. However, the MFSFET type is difficult to manufacture with respect to the structure. Thus, under present circumstances, development and commercialization of the capacitor type ferroelectric memory have been more advantageous.
Ferroelectric materials adopted in the capacitor type ferroelectric memories are divided into two materials, Pb(Zr1-xTix)O3 (PZT) and SrBi2Ta2O9 (SBT). Among them, the PZT materials having compositions in the neighborhood of the rhombohedron-tetragonal phase boundary (MPB) are superior in the residual dielectric polarization and coercive electric field property, and are the materials which are more advantageous than the others in commercialization.
In the related art, Pt has been used as a PZT-based ferroelectric material for a lower electrode. Since Pt has a face-centered cubic lattice structure that is a close-packed structure, it has a strong self-orientation property, and therefore brings about cubic crystal orientation even on amorphous, such as SiO2.
However, since the orientation property is strong, there have been problems in that when a columnar crystal of Pt has grown, Pb, for example, is likely to diffuse in a substrate along grain boundaries, adhesion between Pt and SiO2 is degraded, and the like.
Although Ti may be used to enhance this adhesion between Pt and SiO2, and furthermore, TiN, etc., may be used as diffusion barrier layers against Pb, etc., electrode structures become complicated, and in addition, oxidation of Ti, diffusion of Ti into Pt, and reduction in crystallinity of PZT accompanying that are brought about, and therefore degradation of the polarization electric field (P-E) hysteresis characteristic, the leakage current characteristic, and the fatigue characteristic occur.
In order to address or avoid problems of Pt electrodes as described above, RuOx, IrO2, and other conductive oxide electrode materials have been researched. Among them, in particular, SrRuO3 having a perovskite structure has the same crystal structure as that of PZT, and therefore has superior joining property at the interface, is likely to realize epitaxial growth of PZT, and has superior characteristics as a diffusion barrier layer against Pb.
Consequently, the related art has researched ferroelectric capacitors using SrRuO3 as an electrode.

Substrate for electronic device, method for manufacturing substrate for electronic device, and electronic device


The present invention relates to simple, safe, high-yield methods of synthesizing VNP40101M, 1,2-bis(methylsulfonyl)-2-(2-chloroethyl)-2-(methylaminocarbonyl)hydrazine, an anti-neoplasia agent. One particularly preferred method uses methyl chloroformamide in a one-pot reaction at elevated temperatures to provide VNP40101M in high yield.

VNP40101M, an anti-neoplasia agent, demonstrates potent anti-tumor activity through alkylation or cross-linking of deoxyribonucleic acid. The compound is classified as a sulfonylhydrazine prodrug, and the proposed mechanism of action suggests formation of a chloroethylating species with a relative specificity for O6-guanine alkylation. An additional decomposition product, methyl isocyanate, may inhibit various DNA repair enzymes (See, Penketh, et al. Biochem Pharmacol 2000, 59(3): 283-291).
A three-step process with a total yield less than 10% has been previously reported published in the following patents and journal articles: U.S. Pat. No. 5,637,619 (Jun. 10, 1997 for VNP40101M); U.S. Pat. No. 4,684,747 (Aug. 4, 1987 for intermediate VNP4090CE); WO97/02029 (Jan. 23, 1997); Journal of Medicinal Chemistry, 1990, 33(8): 2259-2264; Journal of Medicinal Chemistry, 1996, 39(3): 796-801, as illustrated in FIG. 1. 2-Hydroxyethylhydrazine (HEH) was used a starting material and reacted with methanesulfonyl chloride to obtain 1,2-bis(methylsulfonyl)-1-[2-(methylsulfonyloxy)ethyl]hydrazine (BMH) at −20° C. for 18 hours, using pyridine as base. The crude intermediate BMH was treated with lithium chloride in acetone under reflux for 3 days to afford 1,2-bis(methylsulfonyl)-1-(2-chloroethyl)hydrazine (VNP4090CE). After purification by flash column chromatography, an approximately 20% yield was reached for the two steps. VNP4090CE was condensed with methyl isocyanate at room temperature using triethylamine (TEA) as a base. After crystallization from ethanol, 1,2-bis(methylsulfonyl)-1-(2-chloroethyl)-2-(methylcarbamoyl)hydrazine (VNP40101M) with an approximately 42% yield. The total yield of this process was less than 10%. It is noted that the process used methyl isocyanate, which is extremely dangerous for manufacturing in scaleup kilogram amounts. For this reason, the present inventors investigated the synthesis and have developed new methods to prepare VNP40101M.

Process for the synthesis of anti-neoplasia agent VNP40101M


A method and apparatus for storing, transporting and distributing kegs. The apparatus comprising a keg shelving assembly with two or more stacked shelves. The shelves containing individual keg slots formed by two or more horizontally disposed rails. Stored kegs within the keg slots are accessed by a vertical sliding frame within a fixed frame vertical guidance assembly. A hinged platform is fixed to the vertical sliding frame having an open, horizontal position and a close vertical position relative to the vertical sliding frame. The apparatus further comprises a braking assembly that utilizes the downward force created by a load on the platform, to create a braking action opposing the downward force. This action allows a user to easily and efficiently lower a keg from one of the stacked shelves.

The present invention relates to an apparatus that pertains to loading, storing, transporting and unloading one or more kegs of various sizes efficiently and effectively.
The distribution of kegs is well known to be difficult, time consuming and sometimes dangerous due to their excessive weight, size and irregular shape. Lifting and carrying of kegs can cause strain on the neck, back and shoulders resulting in injury.
A keg typically resembles the shape of a cylinder or is more commonly recognized as a barrel. Kegs are made of stainless steel or aluminum, and contain several gallons of beer. In the U.S., brewers typically sell kegs varying in capacity ranging from 5 Gallons to 15.5 Gallons weighing up to 170 lbs. Kegs vary significantly in size with diameters commonly ranging from 9¼ inches up to 16 inches and keg heights commonly ranging from 13⅞ inches and 23⅜ inches.
Customary to the industry, various size kegs carrying different products are distributed to many different locations during a delivery route. Lately this issues has been magnified by the popularization of craft beer produced by an exploding number of microbreweries. Typical bars no longer carry just the big brand names, but a myriad of local and region craft beers as demanded by the consumer. Thus, the number of desired kegs containing different kinds of beer has vastly increased.
Moreover, because of the differences in keg shape, size, weight, delivery destination, time schedules and demand, it can be a challenge to organize existing distribution trucks to efficiently load in an orderly, space efficient, and timely manner for unique delivery routes. While out for delivery, deliverymen sometimes have to shuffle around many kegs within the truck in order to properly select the correct keg(s) for a certain delivery. This process is carried out numerous times throughout the course of a delivery route. This collectively wastes time and energy while increasing the risk of injury.
The present invention provides a device for reducing these problems. The difficulties inherent in the art are therefore overcome in a way which is simple and efficient, while providing better and more advantageous results.

Apparatus for storing, transporting and distributing kegs