A pixel compensation circuit and an OLED display device are disclosed. Two or more TFTs are controlled by the scanning signal output from the scanning signal line in the same row in the pixel compensation circuit proposed by the present disclosure. Further, the OLED and the storage capacitor are both connected to the reset voltage signal line. So the OLED and the storage capacitor are reset after receiving the reset voltage signal. The size of the pixel structure in the horizontal direction is compressed in the pixel compensation circuit of the present disclosure, thereby providing space for the improvement of the PPI and facilitating the design of the high PPI panel successfully.

The present disclosure relates to the field of display, and more particularly, to a pixel compensation circuit and an organic light-emitting diode (OLED) display device.
The rapid development of organic light emitting diode (OLED) display technology has promoted the rapid entry of curved surface and flexible display products into the market in recent years. The technological update in related fields is also changing with each passing day. OLED refers to a diode that emits light by carrier injection and recombination under the electric field driven by an organic semiconductor material and a luminescent material. The OLED display device has wider application range due to its advantages of light weight, self-illumination, wide viewing angle, low driving voltage, high luminous efficiency, low power consumption, and fast response speed. In an OLED pixel circuit, OLED illumination in a pixel circuit can be driven by a thin film transistor (TFT), which is called a driving transistor. The brightness of the OLED is related to the current flowing through the OLED so the electrical performance of the TFT as the driving transistor directly affects the display effect. Especially, a threshold voltage of the TFT often drifts. The stability is degraded after the bias is turned on for a long time. The drift of the driving current is produced. The brightness of the entire OLED display device is uneven. To improve the display effect of the OLED display device, pixel compensation is generally performed on the OLED to eliminate the influence of OLED drive current drift (i.e., the threshold shift of the driving transistor), which is called a pixel compensation circuit.
An active-matrix organic light emitting diode (AMOLED) display device is a display device where an OLED device is driven with the current to emit light to form an image. To obtain better picture with uniformity, more accurate current control capability is required. Therefore, both external compensation and internal compensation are generally configured to achieve the above-mentioned effects. Internal compensation means that each subpixel adopts a pixel compensation circuit, such as 7T1C (a structure of seven TFTs plus one storage capacitor), a 6T1C (a structure of six TFTs plus one storage capacitor), and a 6T2C (a structure of six TFTs plus two storage capacitors), to control and regulate an output current through the driving transistor.
Please refer to FIG. 1A and FIG. 1B. FIG. 1A is a schematic diagram of a pixel structure including a pixel compensation circuit of the related art. FIG. 1B is a circuit schematic diagram of the pixel compensation circuit as illustrated FIG. 1A. The pixel compensation circuit is a 7T1C circuit, including first to seventh transistors M1-M7, a storage capacitor Cst, and an organic light-emitting diode (OLED) OELD1.
In FIG. 1A, a first metal layer includes a scanning signal line (Scan), a light emission control signal line (EM), and a lower plate of the storage capacitor Cst. A second metal layer includes an upper plate of the storage capacitor Cst and a voltage signal line VI. A third metal layer includes a driving voltage signal line VDD and a data signal line Data. In FIG. 1A, reference numeral M7′ indicates that the seventh transistor M7′ is controlled by a scanning signal line Scan(n−1) in a previous row. The seventh transistor M7′ is a transistor in another 7T1C circuit unit. The transistors M1-M6 for the same 7T1C circuit are controlled by the scanning signal line Scan(n). The seventh transistor M7 for the same 7T1C circuit unit is controlled by the scanning signal line Scan(n) (not illustrated in FIG. 1A) as well.
In FIG. 1B, a gate of the first transistor M1, a gate of fifth transistor M5, and a gate of sixth transistor M6 are all connected to the light emission control signal line EM(n) in an nth row. A gate of the second transistor M2, a gate of the third transistor M3, and a gate of the seventh transistor M7 are all connected to the scanning signal line Scan(n) in the nth row. The fourth transistor M4 is a TFT of a double-gate structure (including M4-1 and M4-2 portions). The gate of the fourth transistor M4 is connected to the scanning signal line Scan(n−1) in the (n−1)th row. A source of the second transistor M2 and a source of the fifth transistor M5 are both connected to a drain of the first transistor M1. A source of the first transistor M1 and a source of the third transistor M3 are both connected to a drain of the sixth transistor M6. A drain of the third transistor M3 is connected to the light emission control signal lines EM(n) in the nth row. A drain of the second transistor M2 is connected to the data signal line Data. A drain of the fifth transistor M5 is connected to the driving voltage signal line VDD (usually at a high level), and is electrically connected to the upper plate of the storage capacitor Cst. A source of the fourth transistor M4 is electrically connected to the lower plate of the storage capacitor Cst. A drain of the fourth transistor M4 and a drain of the seventh transistor M7 are both connected to the reset voltage signal line VI. A source of the sixth transistor M6 and a source of the seventh transistor M7 are both connected to the anode of the OLED OLED1. A cathode of the OLED OLED1 is connected to a common ground voltage signal line VSS (typically at a low level).
The fourth transistor M4 and the seventh transistor M7 are controlled by different scanning signal lines. When the scanning signal line Scan(n−1) in the (n−1)th row outputs a scanning signal, the fourth transistor M4 is turned on. Thereby, the lower plate of the storage capacitor Cst is connected to a reset voltage signal line VI and is reset after receiving the reset voltage signal. When the scan signal signal Scan(n) in the nth row outputs a scanning signal, the seventh transistor M7 is turned on. Thereby, the anode of the OLED OLED1 is connected to the reset voltage signal line VI to be reset after receiving the reset voltage signal.
However, the source of the fourth transistor M4 (like the terminal 12 illustrated in FIG. 1A) is electrically connected to the lower plate of the storage capacitor Cst. The drain (like the terminal 11 illustrated in FIG. 1A) is electrically connected to the reset voltage signal line VI. The drain of the seventh transistor M7′ in another 7T1C circuit unit (like the terminal 11 illustrated in FIG. 1A) is electrically connected to the reset voltage signal line VI. The source (like the terminal 13 illustrated in FIG. 1A) is connected to the anode of the OLED OLED1. Since the fourth transistor M4 or the seventh transistor M7 (same structure as the seventh transistor M7′ in the other 7T1C circuit unit) has one or more TFT of a double-gate structure (for example, the fourth transistor M4 is double in FIG. 1A is a TFT of a double-gate structure, including the M4-1 and M4-2 portions). Moreover, the fourth transistor M4 and the seventh transistor M7′ are arranged at both sides of the terminal 11, respectively, causing polysilicon (Poly) for the active layers of the two TFTs to be S-shaped traces after 90 degree rotation (i.e., three polysilicon traces in the vertical direction). Due to the layout of components in pixel compensation circuits such as 7T1C, 6T1C, and 6T2C, the size of the pixel structure is further reduced, which limits the increase in pixels per inch (PPI).

Pixel compensation circuit and OLED display device

Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.


The invention relates to an apparatus for heating an electrically conductive fluid, such as potable water, and to a method of heating the same. The heating apparatus includes a plurality of electrodes in an array, and a controller for selectively energizing the plurality of electrodes, in different combinations, to thereby adjust the electrical resistance observed across the electrode array, in order to maximize the current drawn by the apparatus.

Kettles are well known devices for boiling water in the home and office, generally for use in preparing food and drinks for human consumption. In most cases, kettles are powered by electrical energy, since it is a clean and convenient power source. Electric kettles are currently designed to give maximum heating rates and efficiency, as well as having an appealing aesthetic appearance. The most usual way to apply electrical energy to heat water in a kettle, is via one or more resistive heating elements immersed in the water.
However, the use of heating elements to rapidly heat water gives rise to high temperature gradients between the element and the water in contact with the heating element. This, together with the fact that the heating element provides multiple nucleation points for bubble formation, leads to the creation of many small bubbles of steam, which then collapse in the bulk water to produce a noise.
Furthermore, the extreme temperature gradient present at the heating element surface results in the precipitation of minerals and other chemicals dissolved in the water. This results in both the build up of precipitates around the heating element, which reduces the heating efficiency of the heating element, and across the bottom of the kettle in general, which can result in these precipitates finding their way into the food and drinks prepared using the heated water. These are both undesirable traits in kettles according to the conventional art.
A technique known as 'ohmic heating' can also be used to heat electrically conductive fluids such as water. Ohmic heating of water allows rapid, highly efficient heating of the water. Ohmic heating provides a more uniform heating of a fluid, and also has the advantage that none of the surfaces of the heating apparatus become much hotter than the fluid. Thus the use of ohmic heating does not result in the formation of bubbles of steam throughout the majority of the heating cycle with the result that the operation of an ohmically heating kettle is virtually silent, until the full bulk of the water boils, at which time the heating operation is complete.
Arrangements are known where current is passed through a liquid to cause it to heat. In particular, document GB 2268671 discloses an ohmic heater for heating a fluid by passing electricity through it.


A water heater appliance and method for operating a water heater appliance are provided. The method includes measuring a temperature of water within the water heater appliance, operating a heating element of the water heater appliance if the temperature of water within the water heater appliance is less than a threshold temperature and deactivating the heating element of the water heater appliance when the temperature of water within the water heater appliance exceeds the threshold temperature.

Certain water heaters operate such that water with the water heater's tank is maintained at a set temperature. Generally, a user can select the set temperature using a dial or other input on the water heater. Heat pump water heaters are gaining broader acceptance as a more economic and ecologically-friendly alternative to electric water heaters. Heat pump water heaters include a sealed system for heating water to the set temperature. Certain heat pump water heaters also include a supplemental heating element for heating water. Sealed systems generally heat water less quickly than the supplemental heating elements. However, supplemental heating elements generally heat water less efficiently than the sealed systems.
The sealed systems and the supplemental heating elements are operated in a variety of manners depending upon the current heating mode of the associated water heater appliance. For example, during a vacation mode, neither the sealed system nor the supplemental heating elements are operated. Vacation modes can correspond to when water within the water heater appliance is at the set temperature and/or when the water heater appliance is deactivated by a user. As another example, during an electric heating mode, only the supplemental heating elements are activated and the sealed system is deactivated. A user can select the electric heating mode when the user desires water to be heated rapidly by the water heater appliance. During a heat pump mode, only the sealed system is used to heat water within the water heater appliance. As discussed above, the heat pump mode can heat water efficiently but can also heat water more slowly than the electric mode.
During hybrid heating operations, both the sealed system and the supplemental heating element are used to heat water. Hybrid heating operations are generally initiated when a temperature of water within the water heater falls below a threshold temperature, such as after large water draw events. The sealed system and the supplemental heating element are generally operated simultaneously until the temperature of water within the water heater is restored to the set temperature. Hybrid heating operations can assist with rapidly heating water within the water heater after large water draw events. However, operating both the sealed system and the supplemental heating element consumes valuable energy and can negatively affect an efficiency of the water heater.
Accordingly, methods for operating a water heater appliance efficiently would be useful. In particular, methods for operating a heat pump water heater appliance efficiently during hybrid heating operations would be useful.

Water heater appliance and a method for operating a water heater appliance


The instant invention is a light shield formed integral with chemiluminescent devices to effectively block ambient light thereby inhibiting photo degradation of chemical reagents when exposed to external light sources. The light shield displaces conventional foil or the like product packaging designed to protect against light yet permits instant and easy activation of chemiluminescent reagents without interfering with the chemiluminescent reaction. The integral light shields further simplify packaging and extend the product shelf life of the chemiluminescent reagents.

Chemiluminescent devices are non-incandescent products which produce light from a mixture of chemicals. These devices are most valuable for emergency lighting applications such as when normal electrical power service is interrupted. Power interruptions often accompany storms, floods, hurricanes, fires, earthquakes and the like natural disasters. Additionally, because chemiluminescent devices do not rely on electricity for operation, they are readily and reliably used in wet environments, even under water, where electrically powered devices could short out and fail.
Also unique to chemiluminescent devices are their ability to produce light without generating heat. Since chemiluminescent devices are not electrically operated or sources of ignition, they are ideally suited to emergency situations such as the aforementioned disasters. For instance, in situations where flammable vapors such as gasoline or natural gas may be present, conventional illumination such as candles, lanterns or even flashlights pose extreme danger as potential sources of ignition.
The production of light from a chemiluminescent device is conventionally based upon the reaction of a catalyzed hydrogen peroxide mixture (activator) with an oxalate. Chemiluminescent devices are also commercially available in a variety of visible colors as well as non-visible infrared which may be viewed through the use of special optical systems. A great variety of chemical reagents for producing light by chemiluminescent reaction are known. A typical commercially available chemiluminescent device that produces a yellow color can be created from the following constituents: Dibutyl Phthalate 66.45%; Dimethyl Phthalate 20-35%; CPPO bis(2,4,5-trichloro-6-carbopentoxyphenyl) oxalate 8.33%; T-butyl alcohol 3.3%; 90% aq. Hydrogen Peroxide 1.32%; CBPEA 1-chloro-9,10-bis(phenylethynyl) anthracene 0.23%; and Sodium Salicylate 0.0025%. One example of such a chemiluminescent device is taught in U.S. Pat. No. 5,043,851.
The activator reagent is typically contained within a breakable vial (s) which, when broken, admixes with the oxalate reagent to produce the chemiluminescent light. The activator and oxalate placement may be reversed. Since the object of this type of device is to produce usable light output, the containment vessel is made of a clear or translucent material such as polyethylene or polypropylene which permits the light produced by the chemiluminescent device to pass through the vessel walls.
Numerous packaging schemes for chemiluminescent devices are also well known whereby the chemical mixtures are kept separate until such time as light production is desired. U.S. Pat. No. 4,814,949 discloses a separation scheme whereby both chemical solutions are sealed in frangible vials which are housed together in a larger, flexible vessel. U.S. Pat. No. 4,379,320 discloses a co-axial vial system. U.S. Pat. No. 5,067,051 discloses a structure that maintains chemical separation by use of a disk which is situated diametrically within a plastic tube, thereby forming a barrier between the chemicals positioned on either side of the disk. When activation is desired, externally applied forces cause the disk to flip more or less 90 degrees thereby permitting mixing of the chemicals. U.S. Pat. No. 5,552,968 discloses a sphere or ball for separation of oxalate and activator component. The oxalate component in the above device may contain Dibutyl Phthalate, CPPO and CBPEA while the activator may contain the Dimethyl Phthalate, T-butyl alcohol, 90 aq. Hydrogen Peroxide, and Sodium Salicylate.
Both the oxalate and activator reagents described in the above chemiluminescent devices are prone to photo chemical degradation. That is, the chemical components undergo changes and break down upon exposure to light. While high energy, ultraviolet radiation is potentially the most damaging light to these chemical systems, even visible light causes product degradation. If these degradation processes are unchecked, the chemical solutions will eventually be degraded to such point whereby the device will fail to function. Many fluorescers such as CBPEA used in many chemiluminescent devices are severely degraded after just one day's exposure to sunlight. Additionally, hydrogen peroxide will degrade upon exposure to light. This combined degradation limits shelf life and product usefulness.
Product packaging is typically how chemiluminescent chemicals are protected from light to promote product shelf life. For example, product packaging for chemiluminescent light sticks have been produced from optically opaque, metallic foil and plastic film laminates to shield the chemiluminescent reagents from photo degradation whether from natural or artificial light. Another method to protect chemiluminescent products from photo degradation is to package the chemiluminescent devices in bulk, either in metal buckets or cardboard tubes. In either event, external product packaging, whether it be a foil wrapper or cardboard tubes, once opened or damaged may allow light to contact the chemical reagents leading to the photo degradation.
Another problem with external product packaging is the need to open the package before usage of the chemiluminescent device. In an emergency situation, should an individual's hand be wet or in a weakened condition, this extra step may render the device unusable. In emergency situations it is impractical to remove a chemiluminescent device from foil wrappers prior to activation. Also, tools may not be readily available to open the buckets or cardboard tubes of bulk packaged products. Additionally, metal films are subject to corrosion when in the prolonged presence of moisture which limits their effective application in this instance. External packaging, if improperly discarded, presents a waste product that is not readily recycled and hence is usually relegated to incineration or a landfill.
U.S. Pat. No. 4,814,949 discloses a chemiluminescent device formed from two polymeric sheets, one of which has a cavity formed into it for receipt of an absorbent article and chemiluminescent reagents. The second polymeric sheet is sealed peripherally to the first sheet to seal in the aforementioned absorbent article and receptacles. Activation may be accomplished through the application of a force on the polymeric sheet which causes the receptacles to rupture and the reagents to mix. While '949 protects chemical reagents from actinic light, the device is simply a heat sealed pouch fabricated from a polyolefin/foil laminate. Metallic foil laminates are expensive and if a pouch is used instead of vials, chemical migration through the heat seal layer is possible. Hydrogen peroxide activators exhibit a propensity for migration through polyolefins and most other polymers. Even small traces of these peroxygens are capable of rendering the oxalate reagent incapable of producing light.
Thus, what is lacking in the art is a chemiluminescent product having a light shield formed integral thereto for the protection of chemical reagents from photo degradation while maintaining a chemiluminescent device having similar properties of light production and easy instant activation when needed.

Chemiluminescent devices having integral light shields


At least one high aspect ratio via is formed in the backside of a semiconductor substrate. The at least one via is closed at one end by a conductive element forming a conductive structure of the semiconductor substrate. The backside of the semiconductor substrate is exposed to an electroplating solution containing a conductive material in solution with the active surface semiconductor substrate isolated therefrom. An electric potential is applied across the conductive element through the electroplating solution and a conductive contact pad in direct or indirect electrical communication with the conductive element at the closed end of the at least one via (or forming such conductive element) to cause conductive material to electrochemically deposit from the electroplating solution and fill the at least one via. Semiconductor devices and in-process semiconductor devices are also disclosed.

1. Field of the Invention
The present invention relates generally to the field of integrated circuits formed on a semiconductor substrate, such as a silicon wafer or die, including vias formed therethrough and, more particularly, although not necessarily limited to, semiconductor substrates that include through-vias filled with conductive material and methods for their fabrication.
2. State of the Art
In order to function, integrated circuits must be in electrical communication with signal inputs and outputs as well as power and ground or bias connections external to the integrated circuit. For example, power and ground or other reference voltage must be supplied for operation of the integrated circuit, and other connections, such as for input, output and timing signals, may also be required. These connections are typically made through leads or other conductive elements connected to bond pads present on the active surface of a semiconductor die.
As electronic devices have become smaller and more sophisticated, the challenge of expanding capabilities while minimizing the space or "real estate" used by an integrated circuit has continued to increase. Techniques for reducing the space required by a semiconductor die or chip include the use of a redistribution layer (RDL) as an additional level of wiring to reposition bond pads providing inputs and outputs for a semiconductor die from the perimeter or along the centerline to alternative locations, for example, to define an array of locations for flip-chip attachment to a substrate. Use of bond pad redistribution may be necessary if perimeter or central bond pads have to be rerouted into another I/O layout. For example, if perimeter or central bond pad pitch (spacing) is too fine or is otherwise unsuitable for connection to the terminal pad layout of a carrier substrate, repositioning may be required.
Where present, the traces of an RDL may be embedded into a dielectric material. Suitable dielectric materials may include benzocyclobutene (BCB), polyimide, and photosensitive dielectrics. The process steps depend on whether the redistribution traces are aluminum or copper. For aluminum traces, the aluminum is sputtered onto the wafer surface and the traces are etched using a photolithography-defined etch mask pattern comprising a resist. In the case of copper traces, the metal is electroplated onto the wafer surface and then selectively etched to form traces. A redistribution layer is typically applied on the active surface of a semiconductor die to enable flip-chip mounting of the resulting "chip-scale" package on a carrier substrate such as an interposer or a printed circuit board.
Another technique for reducing the real estate required on a carrier substrate is the use of stacked semiconductor chips in a single package. In stacked chip-scale packages, two or more semiconductor chips will be mounted in a stack and electrically interconnected to a carrier substrate and/or to one another. This reduces the space taken on the underlying carrier substrate in comparison to mounting separate chips directly to the substrate.
Stacked chip-scale packages may require vias to be formed through the entire thickness of a semiconductor die between the active surface and backside thereof, allowing electrical connection therethrough to one or more dice stacked thereon. Such vias may require high aspect ratios (the ratio of via depth to diameter) due to the limited available area for positioning the vias in the semiconductor die, making them difficult to fill with electrically conductive material. Electroless plating of vias with a conductive material typically requires the placement of a seed layer of conductive material, such as copper or aluminum, in the via. Typically, this is accomplished by a sputtering or chemical vapor deposition ("CVD") process, which can experience difficulty in depositing the conductive material on the bottom of a relatively high aspect via, for example, 10:1 or greater. Such high aspect ratio vias may even have aspects of 15:1 or greater. Where a portion of the seed layer is deposited on the side of a high aspect ratio via, the material deposited during filling can fill across the via above the bottom, funneling or bridging off the underlying portion of the via. Other techniques, such as depositing conductive material over the surface of the wafer to fill the vias can similarly lead to the funneling or bridging off of a high aspect ratio via near the top of the via. Conventional electroplating typically requires the via to be open on both ends to enable a conductive contact plate to be placed on one side of the wafer to cover the bottom of the via and the electroplating solution to enter the via from the other side. This technique may thus limit the placement or order of the via fill in the wafer fabrication process. Some electroplating techniques also may require placement of a seed layer, resulting in similar funneling or bridging off problems. For example, a relatively new process employs metal organic chemical vapor deposition (MOCVD) to place a copper seed layer prior to electroplating of copper in the via. In addition to the extra step required to place the seed layer, there are reliability issues with this approach.
Accordingly, a method or system for effectively filling high aspect ratio vias without the need for placing a seed layer would be an improvement in the art. Such a technique that might be used for filling blind (or closed end) vias would constitute a further improvement in the art.

Semiconductor devices and in-process semiconductor devices having conductor filled vias


A phase-frequency detector generates output signals at a first and a second output end based on input signals received at a first and a second input end. The phase-frequency detector includes two latch circuits, two pulse generators, two inverting circuits, two sensing devices, and a reset control circuit. The sensing devices control the pulse generators based on signals received at corresponding first ends of the sensing devices. The inverting circuits generate signals to the first and second output ends of the phase-frequency detector based on signals received at corresponding first ends of the inverting circuits. The reset control circuit generates reset signals based on signals received at the first and second output ends of the phase-frequency detector.

1. Field of the Invention
The present invention relates to a phase-frequency detector, and more particularly, to a phase-frequency detector capable of reducing dead zone.
2. Description of the Prior Art
In a prior art phase lock loop (PLL), a phase-frequency detector (PFD) is used for detecting the phase and frequency differences between an input signal and a feedback signal. Based on the results of the PFD, a charge pump, a loop filter and a voltage-controlled oscillator (VCO) is used for adjusting the operations of the PLL so that the phase and frequency of the feedback signal matches those of the input signal.
Reference is made to FIG. 1 for a functional diagram of a prior art PLL 100. The PLL 100 includes a PFD 110, a charge pump 120, a loop filter 130, a VCO 140, and a frequency divider 150. The PFD 110 detects the phase and frequency differences between clock signals FIN and FREF and generates corresponding output clock signals UP and DOWN. Based on the output clock signals UP and DOWN, it is determined whether the phase of the clock signal FREF needs to be adjusted in the forward or backward directions. Next, the charge pump 120 generates a corresponding control current signal for the loop filter 130 based on the output clock signals UP and DOWN. The loop filter 130 then generates a corresponding control voltage signal for the VCO 140 based on the control current signal. Last, the VCO 140 generates a corresponding output clock signal FOUT based on the control voltage signal. Meanwhile, the output clock signal FOUT is transmitted to the PFD 110 via the frequency divider 150. Based on the output clock signal FOUT, the frequency divider 150 generates the clock signal FREF so that the frequency of the output clock signal FOUT is a multiple of the frequency of the clock signal FREF. Therefore, the PLL 100 can adjusts the phase of the clock signal FREF until the phase and frequency of the clock signal FIN matches those of the clock signal FREF.
Reference is made to FIG. 2 for a diagram illustrating the output signals of a prior art PFD. In FIG. 2, the vertical axis represents the voltage level VAVG corresponding to the average output signal of the prior art PFD (VAVG equals to the average value of the output clock signals UP and DOWN), and the horizontal axis represents the phase difference ΔΦ between the clock signals FIN and FREF. In the ideal case as illustrated in FIG. 2, the voltage VAVG corresponding to the average output signal of the prior art PFD 110 is proportional to the phase difference ΔΦ. However in actual operations, the PFD has two non-ideal output regions: dead-zone and blind-zone. Dead-zone occurs when the phase difference ΔΦ between the clock signals FIN and FREF is very small. Under these circumstances, the signal rising edges of the clock signals FIN and FREF are very close to each other, and there may not be sufficient time for the output clock signals UP and DOWN to reach the voltage levels corresponding to the phase difference ΔΦ. Therefore, the control voltage signals generated by the charge pump 120 and the loop filter 130 are very small, and the PFD 110 may not be able to adjust the phase difference ΔΦ between the clock signals FIN and FREF accurately. Blind-zone occurs when the phase difference ΔΦ between the clock signals FIN and FREF is a multiple of 2π. Under these circumstances, the reset of the PFD 110 is very close to the rising edge of the signals in the next period, and the PFD 110 may not be able to determine the exact value of the phase difference ΔΦ. A PFD capable of reducing dead-zone and blind-zone can provide good performance. It is also preferable for a PFD to use as few active devices as possible so as to reduce the noise in the PLL.
Reference is made to FIG. 3 for a functional diagram of a prior art PFD 300 using RS flip-flops. The PFD 300 includes two RS flip-flops 310, 320, and an AND gate 330. The RS flip-flops 310 and 320 are edge-triggered flip-flops in which a Q terminal generates corresponding outputs when the signals received at an R terminal and an S terminal are on the rising edge. The S terminals of the RS flip-flops 310 and 320 respectively receive the clock signals FIN and FREF, the R terminals of the RS flip-flops 310 and 320 receive the reset signal FRESET, and the Q terminals of the RS flip-flops 310 and 320 respectively generate the two output signals UP and DOWN of the PFD 300.
Reference is made to FIG. 4 for a diagram illustrating the tri-state operation of the prior art PFD 300. The PFD 300 has three operational states: (1) the output clock signals UP and DOWN both have a low logic level (logic 0); (2) the output clock signal UP has a low logic level and the output clock signal DOWN has a high logic level (logic 1); and (3) the output clock signal UP has a high logic level and the output clock signal DOWN has a low logic level. When the output clock signals UP and DOWN both have a low logic level, the PFD 300 switches to another operational state in which the output clock signal UP has a high logic level and the output clock signal DOWN has a low logic level upon detecting the signal rising edge of the clock signal FIN. Meanwhile, the PFD 300 switches back to the original operational state in which the output clock signals UP and DOWN both have a low logic level upon detecting the rising edge of the clock signal FREF. Similarly, when the output clock signals UP and DOWN both have a low logic level, the PFD 300 switches to another operational state in which the output clock signal UP has a low logic level and the output clock signal DOWN has a high logic level upon detecting the rising edge of the clock signal FREF. Meanwhile, the PFD 300 switches back to the original operational state in which the output clock signals UP and DOWN both have a low logic level upon detecting the rising edge of the clock signal FIN.
Reference is made to FIG. 5 for a circuit diagram of a prior art PFD 500. The PFD 500 includes two pulse generators 512 and 522, two latch circuit 514 and 524, a reset control circuit 510, and inverters 51 and 52. The PFD 500 respectively receives the clock signals FIN and FREF at a first input end and a second input end, and respectively generates the output clock signals UP and DOWN at a first output end and a second output end.
The latch circuits 514 and 524 respectively include inverters 53, 54 and inverters 55, 56. The input end and the output end of the inverter 53 are respectively coupled to the output end and the input end of the inverter 54. The input end and the output end of the inverter 55 are respectively coupled to the output end and the input end of the inverter 56. Therefore, the latch circuits 514 and 524 can provide voltages having a high logic level (logic 1) or a low logic level (logic 0) at the output end.
The reset control circuit 510 includes two P-type metal-oxide semiconductor (PMOS) transistors TRESET, Two N-type metal-oxide semiconductor (NMOS) transistors TISO, an NAND gate 50, and inverters 57, 58. When the output ends of the latch circuits 514 and 524 have a low logic level, the transistor TISO is turned off and the latch circuits 514 and 524 are thus electrically isolated from the pulse generators 512 and 522, respectively. The two input ends of the NAND gate 50 are respectively coupled to the output ends of the latch circuits 514 and 524 via the inverters 57 and 58. When the output ends of the latch circuits 514 and 524 have a low logic level, the NAND gate 50 outputs a reset signal FRESET at the output end for turning on (short-circuiting) the transistor TRESET. Therefore, the output ends of the latch circuits 514 and 524 are reset, thereby having a high logic level.
The pulse generators 512 and 522 each include two NMOS transistors TSTART and TSTOP, and respectively include inverters 59 and 60. The gates of the NMOS transistors TSTART in the pulse generators 512 and 522 are coupled to the first and second input ends of the PFD 500, respectively. The gates of the NMOS transistors TSTOP in the pulse generators 512 and 522 are respectively coupled to the first and second input ends of the PFD 500 via the inverters 59 and 60 for detecting the clock signals FIN and FREF. Since the inverters 59 and 60 are coupled between the gates of the transistors TSTART and TSTOP, the inverters 59 and 60 can provide signal delay for respectively controlling the clock signals generated by the pulse generators 512 and 522.
The prior art PFD 500 provides signal delay for controlling the clock signals generated by the pulse generators 512 and 522 using inverters so that the tri-state illustrated in FIG. 4 can be achieved. However, the intrinsic characteristics of each inverter may vary or deviate from its nominal value due to process variations. Therefore, the prior art PFD may not be able to function efficiently.

Phase-frequency detector capable of reducing dead zone


A source station for synchronization of transmission and reception of data in a cooperative communication system includes a first receiver to receive, from a destination station, a first request frame including information regarding a first point in time when a first response frame is to be transmitted; a first transmitter to transmit the first response frame to the destination station, at the first point in time; a second transmitter to transmit, to a relay station, a second request frame including information regarding a second point in time when a second response frame is to be transmitted; a second receiver to receive the second response frame transmitted by the relay station at the second point in time; and a time estimator to estimate a first propagation delay time between the source station and the relay station, based on a time in which the second response frame is received.

In a general wireless communication system, for example a Wireless Local Area Network (WLAN) or Wireless Personal Area Network (WPAN) environment, such as an Institute of Electrical and Electronics Engineers (IEEE) 802.11, terminals may be operated independently. Accordingly, it is difficult to control a signal transmitted from a transmission terminal to be received to a reception terminal at the same time after a frequency offset is corrected.
Additionally, in the above-described wireless communication environment, a common preamble structure is employed. When at least two transmission terminals simultaneously transmit data, a point in time when a signal is received to a reception terminal is difficult to be included within a predetermined margin of error. Since it is impossible to correct a frequency offset between different available frequencies for each terminal, even when the point in time is included within the predetermined margin of error, the received signal may be distorted due to multiple frequency offsets.

This patent is subject to a terminal disclaimer.

Station for data transmission/reception synchronization

ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE


Provided are methods of enhancing an immune response and methods for reducing the recruitment of monocytes to a lymph node by administering to an individual an angiotensin II receptor blocker or a compound of Formula (I) in conjunction with an antigen. The invention also provides relate methods for amplifying vaccine immunity by administering to an individual an angiotensin II receptor blocker or a compound of Formula (I) in conjunction with an vaccine. The invention also provides related methods of inhibiting tumor growth and metastasis by administering to an individual with cancer an angiotensin II receptor blocker or a compound of Formula (I) in conjunction with an anti-tumor preparation. In addition, related compositions comprising an ARB or a compound of Formula (I) and an antigen, vaccine, or anti-tumor preparation are provided.

Vaccine adjuvant-induced inflammation augments vaccine immunity in part by recruiting antigen presenting myeloid cells (monocytes and neutrophils) to vaccine draining lymph nodes (LNs) (Serafini et al. (2004) Cancer Res. 64:6337-6343; Martino et al. (2010) J. Immunol. 184: 2038-2047). However, recent evidence indicates that monocyte recruitment to LNs suppresses local B cell and T cell activation and proliferation (Mitchell et al. (2012) J. Immunology 189: 5612-5621; Mitchell et al. (2012) Int. Immunopharmacol. 15: 357-363). Lowered immune responses following vaccination can lead to decreased vaccine efficacy.
Moreover, the role of immature and immune suppressive myeloid cells, including neutrophils, monocytes, and tumor-associated macrophages, in promoting the growth of primary tumors is well established1-10. Additionally, myeloid cells, and especially monocytes play an important role in creating favorable conditions for the seeding and growth of tumor metastases in the lungs, in part by establishing the so-called metastatic niche15-17. Inflammatory monocytes recruited in response to tumor-derived signals have been shown to play a key role in promoting the growth of tumor metastases. The major chemokine regulating monocyte recruitment is MCP-1 (CCL2), which signals primarily via activation of the receptor CCR2 expressed principally on inflammatory monocytes.
What are needed in the art, are methods for administering vaccines and related vaccine compositions that enhance the immune response to an antigen and augment vaccine efficacy by inhibiting the suppressive effects of monocytes at LNs and enhancing B cell and T cell responses. What is also needed in the art, are methods for inhibiting the migration of myeloid cells, and in particular inflammatory monocytes, to the site of tumors where they act to promote tumor growth and metastasis. The present invention is directed to overcoming these deficiencies in the art.

Methods and compositions for enhancing an immune response, blocking monocyte migration, amplifying vaccine immunity and inhibiting tumor growth and metastasis

Colorado State University Research Foundation


The system and method for detecting water and/or gas leaks by monitoring usage patterns is described. In one embodiment, the existence of a leak is detected by looking for usage patterns wherein water or gas is always being used, at least at a low rate. A leak is indicated if usage does not drop to zero, at least for a period of time, during a given time interval (e.g., during a 24-hour period). The severity of the leak is indicated by the minimum amount of usage during the given time period. In one embodiment, the leak detection system is provided in connection with an Automatic Meter Reading (AMR) system.

1. Field of the Invention
The present invention relates to a system and method for electronic utility (e.g., water and gas) metering and leak detection.
2. Description of the Related Art
In a home or building, utilities such as water and gas are used for various reasons throughout the day and night. For example, in homes, water is used randomly and for varying time intervals through the day and night. Although water usage tends to be less at night, water is still used (e.g., for toilets, automatic sprinklers, etc.). The water usage in commercial buildings follows a similar pattern. This makes it difficult to test for leaks, since there is no predictable time during the day or night that water usage drops to zero.
As is known, some waterline leaks can be easily detected because of the presence of detected ground water or the presence of water puddles in the vicinity of a water pipe. However, other waterline leaks go undetected until a water bills become unusually high or water damage is discovered.
Gas leaks are potentially more dangerous than water leaks, and can be more difficult to detect.
Owners of large apartment buildings and commercial buildings face additional problems in monitoring water usage and leak detection. The amount of water and other utilities used by such commercial structures is typically much larger than the usage of a residence or other smaller structure. Moreover, the plumbing and sprinkler systems of such structures tend to be more complex than the systems found in a residence. Thus, any inefficiencies in the usage of utilities is magnified in a large commercial structure, and the costs of such inefficiencies are magnified. For example, in a large commercial structure, water is used for toilets, industrial processes, heating and air-conditioning, fire sprinkler systems, and irrigation sprinkler systems. The management of a large commercial building often does not have an accurate accounting of water usage by the various systems. A maintenance issue as minor as a broken irrigation sprinkler head can cause increased and unnecessary water usage.
Conventional water and gas meters used in connection with residential and commercial structures measure the total amount of water or gas used, but do not monitor the usage patterns. Thus, conventional meters do not provide the information needed to detect leaks.

System and method for utility metering and leak detection


A flexible address mapping method and mechanism allows mapping regions of a microcontroller""s memory and I/O address spaces for a variety of applications by defining memory regions which are mapped to one of a set of physical devices by a programmable address mapper controlled by a set of programmable address registers. The mapping allows setting attributes for a memory region to prohibit writes, caching, and code execution. A deterministic priority scheme allows memory regions to overlap, mapping addresses in overlapping regions to the device specified by the highest priority programmable address register.

1. Field of the Invention
The present invention relates generally to a computer system addressing architecture, and more particularly to an addressing architecture which allows mapping a single memory address space onto multiple physical devices.
2. Description of the Related Art
Many computer systems provide the ability to address physical devices by assigning address ranges to each device. Operating systems and application software access system memory and other addressable devices by writing to or reading from an address in memory space. Other devices are accessed through reading and writing special addresses or xe2x80x9cportsxe2x80x9d defined in an I/O address space. An example of the former is the boot ROM; an example of the latter are modems.
In the conventional computer system, each device is typically defined at a fixed range of addresses in either memory or I/O address space, assigned by either an industry standard or a specific manufacturer. Typically, the system ROM is addressed in the 640K region immediately below 1M. Below that, systems reserve space for BIOS extensions and video RAM. Old memory management systems such as Expanded Memory Specification (EMS) used holes left in this 640K to 1M space for mapping accesses to regions above the 1M line.
Conventional memory controllers define a xe2x80x9cholexe2x80x9d into which ROMs can be mapped. Other conventional controllers allow defining attributes for certain fixed regions of memory.
Early memory controllers provided mechanisms for defining a hole in a block of RAM into which the system ROM could be addressed. More modem conventional controllers shadow (or copy) ROM code and data into that 640K to 1M space in RAM for performance reasons. However, modem controllers still provide the capability to define a hole in RAM for similar purposes. For example, one modem chip set allows defining a hole at either 512K-640K or 15M-16M. A problem with these conventional systems is that the ability to define these holes is limited to fixed specific address ranges.
A second limitation in conventional systems is the ability to define attributes to control access to certain regions of memory space. Some conventional memory controllers allow defining attributes such as write-only, read-only, and non-cacheable to a set of fixed address regions of RAM. Conventional systems typically do not flexibly define attributes to arbitrary memory regions or to ROM. Conventional systems also typically do not define areas to prevent code execution.
In a conventional system, an address which exceeds the upper limit of the addressability of a target device is typically wrapped so that addresses at the beginning of the address space are used instead. This wrapping is not always desirable.
In a system according to the preferred embodiment, a microcontroller contains an address decoder mechanism for mapping addresses in a memory address space and an I/O address space to memory and non-memory resources. The address decoder provides a number of programmable address registers for controlling a programmable address mapper. The programmable address registers and programmable address mapper provide for a flexible mechanism for assigning devices to a particular address in an address space, allowing defining attributes for controlling access to a region of address space, without requiring complicated programming.
One advantage of this mechanism is that the computer system provides compatibility with legacy computer systems, for use with DOS or WINDOWS(copyright). Further, the mechanism can provide improved flexibility in mapping devices into memory and I/O space, such as providing flexibility to overlay devices onto memory ranges and mask out the corresponding region of RAM, which would be useful to help configure multiple devices. Further, according to one aspect of an embodiment of the present invention, the mechanism provides for limiting the mapping to the addressable limit of the device.
Another advantage is the ability to define arbitrary regions of RAM or ROM to have attributes limiting the valid access to those regions. Although conventional computer systems can control the same attributes by use of a paging unit and paging tables plus a segmented code model and descriptor attributes, implementing the attribute definition mechanism in the programmable address mappers can be advantageous because the programmable address mappers are easier to use and provide greater performance. If the CPU""s paging unit is enabled, the entire system performance is degraded because all virtual addresses must be translated to physical addresses. Also, defining execution prohibited areas is difficult, requiring 48-bit code pointers and a fully segmented 32-bit code model. These performance penalties are not incurred when using the programmable address registers.

Method and apparatus for overlapping programmable address regions


A distributed printing system that more optimally distributes job requests within a distributed printing system based on more detailed information about the particular attributes of each output device. In particular, additional printer attributes are used that allow greater utilization of a plurality of attached printers having differing capabilities. These attributes include "max-concurrent-jobs-processing" (MCJP), "number-of-jobs-on-device" (NJOD) and "number-of-cascaded-jobs" (NCJ), and a attribute value "saturated" for the attribute "printer-state". The attribute MCJP is an integer value that is based on the capabilities of the printer. NJOB and NCJ attributes allow monitoring of jobs sent to each printer for supported and unsupported printers. If NJOB or NCJ are greater than MCJP, then the attribute "printer-state" is set to "saturated", prohibiting further spooling of print jobs to that particular printer.

1. Field of the Invention
The invention relates to improved load balancing of distributed printing systems, such as a client/server printing system, through use of enhanced printer attributes.
2. Description of Related Art
Known distributed printing systems, such as client/server printing networks, include one or more servers and multiple printers associated with the server. In such systems, first-in-first-out (FIFO) queuing is often used. Typically, a job from a particular user is sent to a particular user-defined and selected printer. Such a system does not optimally utilize its resources, as certain printers inevitably handle more job requests than other available printers. In such a scenario, one particular printer may have a long job queue and long delay times in printing while other networked printers are in an idle state (i.e., not in current use).
Recently, distributed printing systems have been designed in an attempt to improve on this by providing some degree of load balancing. In such systems, if a selected output device is in use, the job request will be spooled to an available printer within the distributed system. Such a system provides limited load balancing (i.e., if three printers are provided, each will receive on average about 1/3 of the search requests).
Additionally, while some printers within certain distributed printing system environments are capable of providing information back to the server (i.e., idle, printing), some "dumb" printers or foreign printers (i.e., printers not supported by a particular printing system) may not be capable of returning feedback information useful in determining load balancing.

Load balancing of distributed printing systems using enhanced printer attributes


A compact constant current generator that can operate with a positive supply voltage of 1.22 V (or lower) and minimize noise is provided. The constant current generator can include a bandgap reference circuit and a single gain stage. Notably, the bandgap reference circuit can advantageously generate differential node voltages. The gain stage can amplify those differential node voltages and generate a constant current having a temperature coefficient substantially equal to zero. Advantageously, this single gain stage can minimize the number of components, thereby resulting in a compact and efficient current generator.

1. Field of the Invention
The present invention relates to a constant current generator that minimizes silicon resources and noise contribution.
2. Discussion of the Related Art
In many integrated circuits, the analog sections can be biased using either constant currents or constant "IR" currents. A constant current Ic can be generated by applying a fraction (f) of a bandgap reference voltage (VREF) across an external resistor (Rext), i.e. Ic=f*VREF/Rext. FIG. 1A illustrates an exemplary voltage-to-current converter 100 for generating a constant current Ic. In converter 100, a bandgap reference voltage circuit 101 can generate a reference voltage VREF, which is provided to a positive terminal of an operational amplifier 102. The output terminal of operational amplifier 102 is connected to a gate of an NMOS transistor 103. The source of NMOS transistor 103 is connected to a low voltage source VSS via an external resistor 104 as well as to the negative terminal of operational amplifier 102. The drain of NMOS transistor 103 provides the constant current Ic.
In a typical embodiment, bandgap reference voltage circuit 101 includes another operational amplifier. For example, FIG. 1B illustrates an exemplary bandgap reference voltage circuit 101 that includes an operational amplifier 116, which provides its output to a node 117. The collectors and bases of two pnp transistors 113 and 115 are connected to low voltage source VSS. The emitter of pnp transistor 113 is connected to node 117 via two resistors 112 and 111, which are connected in series. A node between resistors 111 and 112 is connected to the negative input terminal of operational amplifier 116. The emitter of pnp transistor 115 is connected to the positive input terminal of operational amplifier 116 and to a resistor 114, which is also connected to node 117.
A bandgap reference voltage VREF can be created by adding a diode voltage, which has a well-known negative temperature coefficient, with a voltage that is proportional to absolute temperature (ptat) in such a way that the temperature coefficient of the combination is nearly zero. In the configuration of bandgap reference voltage circuit 101, resistors 111, 112, and 114 as well as pnp transistors 113 and 115 can be appropriately sized to ensure that the temperature coefficient of VREF is balanced, i.e. substantially zero. This balancing can occur when VREF is approximately 1.22 V.
A constant IR current can be similarly generated by applying a fraction of a bandgap reference voltage across an internal resistor (e.g. polysilicon) (Rint), i.e. constant IR current=f*Vbg/Rint. Because a device may require both a constant current as well as a constant IR current, such a device generally includes a bandgap reference voltage circuit (e.g. bandgap reference voltage circuit 101) and two voltage-to-current converters, i.e. a first voltage-to-current converter for the constant current (e.g. converter 100) and a second voltage-to-current converter for the constant IR current (identical to converter 100, wherein resistor 104 is an internal resistor).
Unfortunately, the bandgap reference voltage circuit and its corresponding voltage-to-current converters have many components that use significant area on an integrated circuit. Moreover, distributing a reference voltage can undesirably contribute to noise and offset in a device. An ideal voltage reference presents a zero impedance source of voltage. Unfortunately, interconnections on integrated circuits have finite impedances, which may allow noise from adjacent traces to be capacitively coupled to a voltage reference line. Further, a voltage reference must be compared to some other voltage, typically "ground." If the absolute voltage of "ground" at the point of voltage reference generation is not the same as "ground" at the point where the reference is used, then the reference voltage will appear to have an error equal to the difference in ground potentials. A difference in ground potentials is a common problem in large-scale integrated circuit design. Additionally, as process technologies scale and voltage supplies are lowered, even generating bandgap reference voltages becomes challenging. For example, positive voltage supplies can now be at 1.8 V or below.
Therefore, a need arises for a more compact, noise minimizing constant current generator that can operate with a positive voltage supply equal to or less than 1.22 V.


A system and method for context-aware computer management is disclosed. The method of the present invention includes the steps of, assigning database information clearance levels; assigning smart badges one of the clearance levels; identifying smart badges having a lowest clearance level; and providing access to database information having clearance levels no higher than the lowest clearance level. The system of the present invention includes a database storing information differentiated by several clearance levels; a beacon; a set of smart badges, in visible communication with the beacon and assigned one of the clearance levels; a system service module, connected to the beacon, for identifying a lowest clearance level assigned to the smart badges; and a software application, connected to the service module and the database, for providing access to information within the database having clearance levels no higher than the lowest clearance level.

1. Field of the Invention
The present invention relates generally to systems and methods for context-aware computing, and more particularly for context-aware computer management using a smart badge.
2. Discussion of Background Art
Context-aware computing is a field of computer science where computers are provided with sensors for detecting their orientation with respect to persons, places or things. Smart identification badges are an example of context-aware computing devices which contain an array of mini-sensors and wireless technologies for gathering information on their environment and communicating with other computers in order to provide such services as unlocking doors, and selective access to sensitive database information within various secure environments.
The mini-sensors can use a variety of biometric and standard technologies to monitor environmental conditions such as light, humidity, temperature, and sound levels, as well as spatial motions, voice patterns, and perhaps pheromones. Software programs then process this sensor information to conclude such things as who is wearing a smart badge and for how long. Researchers in the area of context-aware computing include Dr. Mark Smith at Hewlett-Packard Labs in Palo Alto and Gerald Maguire, professor of data communications at the Swedish Royal Institute of Technology.
Dr. Smith, for example, has developed a badge size SecurePAD which an employee picks up each morning, registers and authenticates in a secure booth, and carries on their person while at work. The badge communicates with beacons distributed throughout an office environment which respond to the badge by selectively opening doors and providing predetermined sets of information and functionality on secure computer systems. At the end of the day the badge is selectively inactivated. Presideo Inc., of Sebastian, Fla. also manufactures similar security systems as described on their web site at http://www.presideo.com.
FIG. 1 is a dataflow diagram of a prior art system 100 for interfacing with smart identification badges. In the system 100 credentials for several wearers are authenticated and downloaded into their respective smart badges 102, 104, 106, and 108. A computer 110 connected to a narrow infrared (IR) beacon 112 selectively communicates with the badges 102-108. The beacon 112 by design has a short distance and narrow visibility range so that only one smart badge worn by an employee sitting right in front of the computer 110 is visible to the beacon 112 at any one time. The prior art considers this narrow range of visibility as a way to increase the system's 100 overall security.
A system service module 114 within the computer 110 communicates 111 with the smart badges through the beacon 112. When a first one 104 of the smart badges 102-108 becomes visible to the beacon 112, the service 114 queries the badge 104 for a set of credentials and, if the credentials are authentic, instructs the computer 110, perhaps using Microsoft Corporation's Graphical Identification and Authentication (GINA) 116 and OS Logon 118 modules, to log the employee carrying the badge 104 on to the computer 110. If the badge 104 is no longer visible to the beacon 112, the service 114 the GINA 116 to lock the computer 110 and blank the computer display even though the employee remains logged on. Then, should the badge 104 become visible again, the service 114 instructs the GINA 116 to unlock the computer 110 and reactivate the computer display. If a second smart badge 106 becomes visible 120 to the computer 110, during a time when the first badge 104 is invisible to the beacon 112, the system service 114 instructs the GINA 116 to log-off the employee assigned to the first badge 104, and log-on the employee assigned to the second badge 106.
The system 100 is limited to allowing only one wearer to be logged on at any one time and requires that such wearer sit right in front of the computer 110 before unlocking the computer and display. Database security is thus achieved by logging only one wearer on a time. The wearer then runs a software application to access data in the database. The GINA's 116 role in controlling access to the database is by controlling which wearer logs on to the computer 110. In many operational settings, however, such an implementation is awkward to use. Furthermore, the prior art system 100 does not even begin to exploit the smart badge's 102-108 full capabilities for providing contextual information to the computer 110.
What is needed is a system and method for context-aware computer management using a smart badge that overcomes the problems of the prior art.

System and method for providing context-aware computer management using smart identification badges

Hewlett-Packard Development Company, L.P.


The present invention provides an optical amplifier pre-emphasis and equalization method that alleviates the optical amplifier gain ripple penalty experienced in conventional optical communications systems. This method includes storing measured communications channel signal gain ripple information, acquired during factory calibration, in the internal memory of each optical amplifier module. When the optical amplifiers are assembled into a chain, system software retrieves this communications channel signal gain ripple information from each optical amplifier module and computes the pre-emphasis or equalization required for each channel in order to obtain a flat SNR at a receiver. The method also includes measuring the ambient temperature of each optical amplifier module and applying a correction based on the expected change in gain response of each optical amplifier. The method further includes, for Raman amplifiers and the like, applying a fiber type, gain setting, GFF error, etc. correction based on the expected change in gain response of each optical amplifier. The method relies on using VOAs at the sources or DGEs/RBFs in the optical signal path to pre-emphasize or equalize the optical channels.

In optical communications systems that use wavelength division multiplexing (WDM), multiple wavelengths of light are used to support multiple communications channels on a single fiber. Optical amplifiers, such as erbium-doped fiber amplifiers (EDFAs), Raman amplifiers, and the like, are used in these optical communications systems to amplify optical signals that experience attenuation over multi-kilometer fiber optic links. Due to the length of such multi-kilometer fiber optic links, which may be on the order of hundreds or thousands of kilometers, many of these optical amplifiers may be used.
The intrinsic gain spectrum of an EDFA, for example, is not flat. Unless the signal spectrum is equalized, different wavelengths of light are amplified by different amounts as they propagate through multiple optical amplifiers. This results in degraded bit error rate (BER) performance for some communications channels. This degradation is referred to as the "optical amplifier gain ripple penalty." It comes from two different sources, namely erbium-doped fiber (EDF)/gain flattening filter (GFF) mismatch and the temperature dependent change in the gain spectrum of the optical amplifiers, and it is compounded by the use of many optical amplifiers, increasing linearly with the number of optical amplifiers used. The gain ripple penalty stems from the optical amplifiers and, to a lesser extent, from dispersion compensating modules (DCMs), the fiber plant, etc., and it is usually a reach-limiting constraint for an optical communications system.
Conventional approaches for alleviating the optical amplifier gain ripple penalty involve the use of a dynamic gain equalizer (DGE) or the like. The DGE has a loss spectrum that tracks the gain spectrum of the optical amplifiers, thereby introducing losses to offset gain peaks. Conventional approaches for alleviating the optical amplifier gain ripple penalty also involve the use of an optical performance monitor (OPM) or the like for the active measurement of communications channel signal gain ripple at a receiver or an intermediate point in the optical amplifier chain and a feedback mechanism to provide this communications channel signal gain ripple information to a controlling element, such as a variable optical attenuator (VOA), DGE, or the like. The drawback to these approaches is that OPM and DGE elements are relatively expensive, especially when used in low channel count optical communications systems.
Thus, what is needed in the art is an approach for alleviating the optical amplifier gain ripple penalty that does not necessarily use OPM and DGE elements, or feedback mechanisms, thereby limiting optical communications system cost.

Optical amplifier pre-emphasis and equalization method and optical communications system incorporating same


A method of handing off radio resources from a first base station to a second base station includes transmitting route information and speed information associated with a client device from the client device to the first base station or to an application server. A time is selected at which the radio resources are to be handed off from the first base station to the second base station. The selection is performed by the first base station or the application server. The selection is performed dependent upon the route information and speed information.

1. Field of the Invention
The present invention relates to a method for wireless communication, and, more particularly, to a method for wireless communication with increased performance and reliability within a vehicle.
2. Description of the Related Art.
It is known for wireless communication to be established between various systems within a vehicle, such as an automobile, and external applications such as an internet search engine, for example. Attaining reliable wireless communication with a vehicle is problematic, however, because wireless communication is deeply affected by the quality of the wireless signals as received by the vehicle as it travels toward and away from various base stations. The quality of the signals received by the vehicle is highly dependent upon the distance between the vehicle and the nearest transmitting base station as well as on the level of traffic on the communication channel between the vehicle and the base station.
The handoff process is always one of the major challenges in providing pervasive and ubiquitous mobile wireless services. Handoff is defined as the transfer of radio resources from a previously used base station to a new base station. Normally handoff is carried out when the reception from the current base station is below a certain threshold as illustrated in FIG. 1. A client vehicle may travel in direction 11. The level of signal power from base stations A and B as received at the client vehicle is shown as PrxA and PrxB, respectively. Base station A may have an area of coverage indicated by 16A, and base station B may have an area of coverage indicated by 16B. When the level of signal power from base station A falls below a threshold power level Pth (i.e., PrxA<Pth), as at 12, then handoff is initiated. The actual handoff may occur at 14.
Depending on the technology used, handoff may be of either the hard type or the soft type. A hard handoff (also known as break before make) involves releasing current resources before acquiring the new ones. This hard type of handoff is common with Time Division Multiple Access (TDMA)/Frequency Division Multiple Access (FDMA) based technologies, though new generation cellular systems have mitigated this issue to some extent. A soft handoff (also known as make before break), on the other hand, involves establishing communication with a new base station while still maintaining the old base station. This soft type of handoff is very common for Code Division Multiple Access (CDMA) based systems.
Current solutions for transferring resources from an old base station to the new one are not sufficient to provide the required Quality of Service (QoS) for continuous streaming applications. The present invention provides several methods of using location based information to assist the handoff process and thereby enhance the overall network performance for all applications.
What is neither disclosed nor suggested in the art is a method for mobile wireless communication that overcomes the above-mentioned problems and disadvantages. More specifically, what is neither disclosed nor suggested in the art is a method for mobile wireless communication in which handoffs can be planned based on information pertaining to the expected route to be taken by the vehicle to its destination. That is, the prior art does not disclose or suggest using vehicle route information proactively rather than reactively to assist handoffs in wireless networks.

Method for performing proactive wireless communication handoffs using a mobile client's route information


Provided is a battery pack that can uniformly cool a plurality of electric cells, prevent a breakdown of the electric cells, and provide high performance of all electric cells. The battery pack includes a packaging case in which: each adjacent ones of a plurality of electric cells in the first direction define a ventilation space; first and second passages are defined that extend in the first direction and that are arranged to have the plurality of electric cells located between the first and second passages in a second direction intersecting the first direction, wherein gas supplied to the first passage flows through the ventilation spaces to the second passage; and a flow rate limitation device is provided that is arranged in an upstream area of the first passage and that limits a flow rate of the gas flowing through one of the plurality of ventilation spaces, which leads to the upstream area of the first passage, to a predetermined flow rate.

Conventionally, there are various types of power sources for various devices that require a large amount of power. A battery pack that includes a plurality of electric cells and a packaging case accommodating the plurality of electric cells is known as an example of the power sources.
In recent years, hybrid electric vehicles that emit less CO2 and electric vehicles that do not emit CO2 (hereinafter, the vehicles will be collectively referred to as "electrically powered vehicles") are widely used from the viewpoint of environmental protection. The battery packs are adopted as driving sources of the electrically powered vehicles and as power sources for supplying power to control systems.
This type of battery pack adopts a rechargeable secondary cell as an electric cell. However, the electric cell (secondary cell) tends to generate heat due to charge and discharge, and an excessive temperature rise of the electric cell causes a reduction in performance of the electric cell and a shortened life span.
Consequently, a battery pack has been proposed in which a plurality of electric cells are aligned and accommodated in a packaging case, and first and second passages are arranged with the plurality of electric cells interposed therebetween.
In the battery pack, the plurality of electric cells are arranged so that ventilation spaces through which gas flows are formed between adjacent electric cells. Therefore, if gas, such as open air, is supplied to the first passage, the gas flows from the first passage to the second passage through the ventilation spaces (cf., JP-A-2000-243461, for example).
As a result, the gas flowing though the ventilation spaces cools the electric cells on both sides of the ventilation spaces in the battery pack, preventing an excessive temperature rise of the electric cells. It is therefore supposed that the life span of the electric cells is not reduced, and the electric cells can provide necessary performance.
However, the gas is supplied to the first passage from a predetermined location of the first passage in the battery pack, and therefore the electric cells in a downstream area of the first passage may not be sufficiently cooled.
Specifically, if the number of electric cells arranged in the packaging case is larger, the length of the first passage is longer in accordance with the number of electric cells. Therefore, the pressure loss of the first passage cumulatively increases from the upstream to the downstream. More specifically, a large amount of gas flows into the ventilation spaces in an upstream area with a small pressure loss in the first passage, while the gas is not sufficiently supplied to the ventilation spaces in the downstream area with a large pressure loss. Therefore, the electric cells in the downstream area of the first passage may not be sufficiently cooled in the battery pack.
Therefore, not only the possibility of a breakdown of the electric cells in the downstream area of the first passage increases in the battery pack, but there are also variations in temperature between the electric cells in the upstream area of the first passage and the electric cells in the downstream area of the first passage. There is a problem that the performance of all electric cells cannot be sufficiently achieved.

Battery pack and electrically powered vehicle including the battery pack


A stand knob lock is employed to connect a stand plate and a neck frame of an LCD monitor. The stand plate has an opening and two holders. It also includes two ribs and two pins around the opening. The stand knob includes a shaft and two flanges on one side and an “I”-type notch in the opposite side. The shaft of the stand knob is led through the opening of the stand plate and rotated clockwise such that two flanges are secured between the pins and the ribs. The shaft can fit into the slot of the neck frame to connect the stand plate and the neck frame.

1. Field of Invention
The present invention relates to a knob lock mechanism. More particularly, the present invention relates to a knob lock mechanism to assemble a LCD base.
2. Description of Related Art
As the liquid crystal display (LCD) manufacturing technology advances rapidly, LCD monitors are applied in various fields and replace CRT monitors.
In order to meet various customer demands for an LCD monitor, more products are specialized for specific demands. For instance, an LCD monitor can be installed on a wall by means of a base, which attaches to the wall firmly; some LCD monitors are placed on a desk by means of a normal base, which supports the LCD monitor. Moreover, the height of an LCD monitor pedestal must be adjustable to meet the various needs of desks, persons or chairs of different heights.
Furthermore, a conventional LCD monitor pedestal is usually wider or thicker than the LCD monitor itself. If an LCD monitor and its pedestal are not disassembled for packing, the package size thereof is very large.


A handheld misting device has a housing having a dispensing window is arranged and configured to contain a sonic generator, a power source coupled to the sonic generator, a plurality of reservoirs, each containing a liquid, and a plurality of nozzles, each nozzle arranged and configured for removable coupling to the sonic generator. Each nozzle is associated with and in liquid communication with a single reservoir. The sonic generator includes a converter and an elongate horn having a proximal end coupled to the converter and a distal end, and the nozzle is removably coupled to the distal end of the horn. Thus, the device delivers the liquid through a delivery opening formed in the nozzle, and activating the sonic generator energizes the liquid in the nozzle to generate an aerosol plume that is delivered through the dispensing window.

Spray and/or misting devices are often used to delivery cosmetic and general health care liquids. Low cost systems employ droppers and/or squeeze bottles with some form of nozzle through which the liquid is forced to provide a relatively uncontrolled dosage and droplet size.
Expensive systems may employ metering pumps and/or expensive aerosol forming components. For example, Hseih et al. U.S. Pat. No. 7,992,800 and Hseih et al. US Pub. Pat. Appn. No. 20120318260 disclose nebulizers driven by piezo-electric and/or magnetic drives to generate an aerosol mist.
Other examples include The Technology Partnership PLC, EP615470B1, Hailes et al., U.S. Pat. No. 7,550,897, and Brown et al. U.S. Pat. No. 7,976,135, which disclose liquid projection apparatus employing transducers to project liquid droplets from an outer face of a nozzle.
Finally, Terada et al. U.S. Pat. No. 6,863,224, Yamamoto et al. U.S. Pat. No. 6,901,926, and Esaki et al. U.S. Pat. No. 8,286,629 disclose ultrasonic liquid atomizing devices.
Unfortunately, these expensive components can be contaminated through repeated uses and require careful cleaning or disposal.
What is needed is a relatively low cost system for delivering controlled doses and particle/droplet size aerosol mists.


Provided is a base material having a conductor pattern formed thereon, which is obtained by forming, at a high productivity on a base material, a conductor pattern having a lower surface resistivity and a higher conductivity than in the related art. A receiving layer 5 made of a cellulose acetate alkylate is formed on a surface of a base material 4. A conductor pattern 6 is formed by printing a conductive paste 3 in a predetermined pattern shape onto the surface of the receiving layer 5.

Intaglio printing processes such as gravure printing have hitherto been used to form conductor patterns such as electromagnetic shielding patterns in electromagnetic shielding materials for use in, e.g., plasma display panels (PDP) (see, for example, Patent Documents 1 to 8). One such example, the transparent base material with electromagnetic shielding film described in Patent Document 1, is manufactured by forming an underlayer over the entire top side of a transparent base material; using a gravure printing process to form on the underlayer a catalyst ink layer in a predetermined pattern; then using a plating process to form on the catalyst ink layer a metal layer of the same pattern shape as the catalyst ink layer.
Here, the underlayer is formed using a material containing, for example, oxide fine particles and an organic polymer; a porous structure is thought to form on account of the presence of the oxide fine particles. The catalyst ink layer is formed using a catalyst ink containing, for example, noble metal fine particle-supporting oxide fine particles, an organic polymer and an organic solvent. When the catalyst ink layer is formed on the underlayer by a gravure printing process, as shown in FIG. 13, first, the organic solvent within the catalyst ink 23 that has been filled into the pattern grooves 22 on the plate cylinder 21 is absorbed into the porous underlayer 24, as a result of which the viscosity of the catalyst ink 23 rises. Apparently, the catalyst ink 23 which has hardened to an appropriate degree grips the porous underlayer 24, enhancing adherence between the catalyst ink 23 and the underlayer 24 by an anchoring effect, and the catalyst ink 23 is pulled from the pattern grooves 22 on the plate cylinder 21. In FIG. 13, "12" represents a doctor for scraping off excess catalyst ink 23, "25" is a transparent base material, and the arrows indicate the direction of flow by the organic solvent.

Base material with a conductor pattern,and a method of forming a base material with a conductor pattern

PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.


A semiconductor device includes a gate stack over a semiconductor substrate, a lightly doped n-type source/drain (LDD) region in the semiconductor substrate and adjacent the gate stack wherein the LDD region comprises an n-type impurity, a heavily doped n-type source/drain (N+ S/D) region in the semiconductor substrate and adjacent the gate stack wherein the N+ S/D region comprises an n-type impurity, a pre-amorphized implantation (PAI) region in the semiconductor substrate wherein the PAI region comprises an end of range (EOR) region, and an interstitial blocker region in the semiconductor substrate wherein the interstitial blocker region has a depth greater than a depth of the LDD region but less than a depth of the EOR region.

As the dimensions of transistors are scaled down, the reduction of vertical junction depth and the suppression of dopant lateral diffusion, in order to control short-channel effects, become greater challenges. MOS devices have become so small that the diffusion of impurities from source/drain extension regions and deep source/drain regions will significantly affect the characteristics of the MOS devices. Particularly, impurities from source/drain extension regions are readily diffused into the channel region, causing short channel effects and leakage currents between the source and drain regions. Methods for controlling diffusion are thus explored.
A first method of confining the diffusion of p-type or n-type impurities is discussed below. As is shown in FIG. 1, a gate electrode 6 is formed over a substrate 2. N-type dopants and/or p-type dopants are introduced into the gate electrode 6 and source/drain regions 8 of NMOS devices and PMOS devices, respectively. Arrows 10 symbolizes the implantation. For n-type devices, nitrogen and fluorine are co-implanted to source/drain regions 8, and for p-type devices, nitrogen and carbon are co-implanted to source/drain regions 8. Nitrogen, carbon, and fluorine have the function of retarding the diffusion of dopants. Therefore, the diffusion of the dopants is controlled when the MOS devices are annealed, and thus the source/drain regions 8 have higher impurity concentrations and more confined profiles.
A second method for confining the profile of phosphorus in deep source/drain regions 16 of NMOS devices is illustrated in FIG. 2. After the formation of a gate electrode 12 over a substrate 20, LDD regions 14 are formed by introducing an n-type dopant such as arsenic. Spacers 11 are then formed. Symbolized by arrows 22, phosphorus is introduced to form deep source/drain regions 16. Carbon or fluorine is also implanted into the same regions. The addition of carbon or fluorine makes relatively high concentrations of phosphorus possible since less is diffused away, and transistor drive current is improved without unduly compromising the short channel characteristics.
For high performance devices, shallow and highly activated lightly doped source/drain (LDD) regions are desired. Typically, arsenic is preferred for forming LDD regions for its low diffusion length. However, the corresponding sheet resistance is relatively high due to its low activation level, thus limiting device performance, such as drive currents, of NMOS devices. Another commonly used n-type dopant, phosphorus, is known to have a high activation level but a long diffusion length, thus the junction depth is adversely affected, and diffusion into the channel region is also significant. Therefore, the formation of shallow and highly activated LDD regions is one of the challenges in integrated circuit fabrication technologies.

Semiconductor device having ultra-shallow and highly activated source/drain extensions

Taiwan Semiconductor Manufacturing Company, Ltd.


A tool cutting apparatus includes a chuck table for holding a workpiece, and rotatable cutting means having a cutting tip for cutting the front side of the workpiece. Pure water and an additive are mixed to prepare a cutting fluid, and a cutting fluid nozzle supplies the cutting fluid to the cutting tip and the workpiece held on the chuck table.

1. Field of the Invention
The present invention relates to a tool cutting apparatus including a cutting tool for cutting a workpiece and also to a tool cutting method for a workpiece.
2. Description of the Related Art
There are various techniques for realizing a reduction in size and weight of a semiconductor device. For example, a mounting technique called flip chip bonding has been put to practical use. This mounting technique is such that a plurality of metal projections called bumps each having a height of about 10 to 100 μm are formed on the front side of each device formed on a semiconductor wafer and these bumps are directly bonded to electrodes formed on a wiring board. The bumps on the device surface of the semiconductor wafer are formed by plating or a stud bump method. Accordingly, the heights of the individual bumps are not uniform, so that it is difficult to uniformly bond all the bumps to the electrodes of the wiring board.
Further, as a technique for realizing high-density wiring, there is an integrated circuit mounting technique such that an anisotropic conductive film (ACF) is interposed between the bumps and the wiring board to be bonded. In this mounting technique, the heights of the bumps must be uniformed because the lack of the height of any bump causes faulty bonding. It is therefore desirable to cut the plural bumps formed on the front side of a semiconductor wafer so that the heights of all the bumps become a desired height. As a method of cutting the bumps to a desired height, there has been proposed a cutting method using a tool cutting apparatus as disclosed in Japanese Patent Laid-Open No. 2010-36300.
The tool cutting apparatus includes a tool wheel composed of a wheel base and a tool unit provided on the wheel base, wherein the tool unit includes a cutting tip formed of diamond. In cutting a workpiece by using the tool cutting apparatus, the tool wheel is mounted on a spindle and rotated by rotating the spindle, and the cutting tip of the tool unit is brought into abutment against the workpiece, thereby making the cutting tip slide on the tool wheel and the workpiece

Tool cutting apparatus and tool cutting method for workpiece


An electro-mechanical electrostatic air cleaner that combines a low air resistance dielectric fibrous filter material positioned between and electrically charged by two electrically resistant carbon coated screens. The screens are charged by a remotely mounted bi-polar power supply. A pair of post ionization electrodes charge particles in the air with opposite charges, causing the particles to agglomerate. A plurality of screens may be placed in an array for increased one-pass filtration.

Dust, pollen, smoke, smog, bacteria, virus, mold and odors are all comprised of particles which can be suspended in the air. These airborne particles are small, ranging in size from 0.001 microns to 10 microns. Larger particles of 10 to 50 microns tend to settle out quickly while smaller particles, the main hazard to health, remain airborne.
These suspended particles can be removed from the air by either mechanical or electrical means. The most common mechanical techniques include fan/filter systems, gravity settling, centrifugal separation, and scrubbing.
In ordinary fan/filter systems air is drawn through a filter which mechanically traps particles in a web of synthetic or glass fibers. The efficiency of these filters is dependent on the filter surface area and the density of the web network. At low air resistance densities, these filters are only effective for large particles exceeding 10 microns. Fan/filter systems may also involve activated carbon and/or silica gel materials to remove odors. The efficiency and effectiveness of these approaches are grossly limited, so that scents or perfumes are often used to make the filtered air smell "clean".
For small particle removal, a high efficiency, particle air (HEPA) filter having accordion-like pleats is used. These are expensive and used for special applications where a single pass efficiency is required, such as in hospitals and clean rooms, and they must be changed frequently before they become clogged and overburden the air circulation fan.
Electrical particle removal may be achieved by either electrostatic precipitation or open-air ion generation. Electronic deposition of particles is accomplished by charging the particles to be deposited with one polarity and grounding the objects on which the particles are to be deposited with the opposite polarity or common line ground.
The accepted theory of operation of a conventional electrostatic precipitation system involves air being drawn by a fan past an electrode that gives the airborne particles a relatively strong electric charge. The air then passes by a set of parallel collector plates of opposite charge to which the particles are attracted and stick. Essentially, electrostatic precipitation uses electrical forces of charged bodies to separate particles from the air where the polarization forces are perpendicular to the direction of the air flow. This process is highly effective on small airborne pollutants ranging in size from 0.001 to 10 microns (0.0000003 to 0.0004 inches).
A further issue involves the presence of free air ions. The air in typical indoor spaces is almost totally devoid of free air ions because any existing ions become attached to dust particles which then become attracted to and attached to nearby wall and floor surfaces. Thus the indoor air is essentially scrubbed free of nearly all free air ions, and there are no natural sources indoors to replace them. Outdoors, there are numerous sources of free air ions such as the effects of sunlight, waterfalls, ocean waves, and even pine forests.
Air ions function outdoors to naturally remove bacteria and small particles from the air, and their absence in indoor air can lead to easier spreading of infectious diseases. Air ions are also thought to affect moods, with an over-abundance of positive ions causing depression, and with a balanced level of free air ions being optimum for well-being.
U.S. Pat. No. 4,978,372 to Pick discloses a pleated charged media air filter for an electrostatic air filtration system of the charged media type wherein contact between the filter media and the electrostatic charging media of the filter is minimized or eliminated to increase the efficiency of the filter. The fibrous filter media is either corrugated to minimize its contact with the charging media or separated from the charging media by nonconductive spacers. This dramatically increases the efficiency of the filter by reducing the voltage drop on the charged media caused by conduction across a filter medium in close contact with both a charged and a grounded medium.
U.S. Pat. No. 5,474,600 to Volodina, et al. describes an apparatus for biological purification and filtration of air. The apparatus includes a coarse filter, an ionizer, an additional plate and a fine filter, which are installed in this order along the path of the gas flow, and a power source. The coarse filter is essentially an electrostatic precipitator consisting of three plates adjacent to each other, the outer-most of which are made of a cellular metal and are connected electrically to the opposite-in-sign terminals of the power source, whereas the central plate is made of polyurethane foam. The coarse filter abuts closely on the cylindrical nondischarge electrode of the ionizer.
U.S. Pat. No. 5,593,476 to Coppom teaches a method and apparatus for use in electronically enhanced air filtration. A high efficiency air filtration method and apparatus utilizes a fibrous filter medium that is polarized by a high potential difference which exists between two electrodes. The electrodes include an insulated electrode and an uninsulated electrode. A corona precharger is positioned upstream of the electrodes and filter. The corona precharger creates charged particles that have an opposite charge (e.g., a positive of negative charge) determined with respect to a polarization dipole proximal to the insulated electrode. These particles cancel a trapped charge that tends to accumulate on the filter surfaces proximal to the insulated electrode.
U.S. Pat. No. 5,855,653 to Yamamoto teaches an induced voltage electrode filter system with a disposable cartridge. A filter apparatus for trapping particles suspended in gaseous fluid stream generally includes a first and a second electrode with a porous filter therebetween along with electrical contacts for applying a DC voltage across the first and second electrodes. A third electrode is provided and a frame is included for removably supporting a porous filter, along with the first, second, and third electrodes in order to electrify, by induction, the third electrode with a voltage in the third electrode in order to increase trapping of the particles by the filter apparatus.
The foregoing patents reflect the current state of the art of which the present inventor is aware. Reference to, and discussion of, these patents is intended to aid in discharging Applicant's acknowledged duty of candor in disclosing information that may be relevant to the examination of claims to the present invention. However, it is respectfully submitted that none of the above-indicated patents disclose, teach, suggest, show, or otherwise render obvious, either singly or when considered in combination, the invention described and claimed herein.

Electronic bi-polar electrostatic air cleaner


A drill in which a cutting head is releasably mounted on a tool shank. The cutting head is axially supported by the tool shank at four spaced apart axial support regions on shank support surfaces.

Such a rotary cutting tool is disclosed in U.S. Pat. No. 5,957,631. The cutting tool comprises a cutting head and tool shank each having two coupling portions and two chip flutes defined therebetween. Each coupling portion of the cutting head and tool shank has a stepped configuration with a raised base surface adjacent one flute and a lowered base surface adjacent the other flute. If the cutting head and tool shank are designed to be coupled together with both the raised and lowered base surfaces in contact, then these surfaces have to be manufactured such that the distance between them is the same to within a high degree of accuracy. If on the other hand, the cutting head and tool shank are designed to be coupled together with only one of the raised and lowered base surfaces in contact, then the coupling will be less stable.

Drill with releasably mounted cutting head