An electric lamp is described, which has a quartz glass lamp vessel (10) accommodating an electric element (3, 4). The lamp vessel locally has a light-absorbing, non-reflective coating (11, 12). The coating mainly consists of iron, iron oxide, silicon, and silicon dioxide, the ratio of the weight percentages of iron (compounds) and silicon (compounds) being in the range of 0.17<=iron (compounds)/silicon (compounds)<-12, and the ratio of the weight percentages of silicon and silicon dioxide being in the range of 0.5<=silicon/silicon dioxide<=50.

An electric halogen incandescent lamp of this type is known from DE 3827451. Besides iron oxide, the known light-absorbing coating further comprises titanium oxide, manganese oxide and magnetite, FeO4, as pigments and, before being burned onto the glass of the lamp vessel, ethyl silicate as an adhesive. The known coating is obtained from a suspension which additionally comprises sodium metaphosphate, glycol, monobutyl glycol ether, and ethanol. The suspension has a relatively complicated composition. The known suspension has the disadvantage of a relatively short shelf life of about 3 days, and when burned onto the lamp vessel and being converted into the light-absorbing coating, this light-absorbing coating can be knocked off the lamp vessel comparatively easily. Furthermore, the manganese oxide often comprises lead (oxide) as a contaminant and is therefore relatively harmful to the environment.
An electric lamp is known from GB 1422491 which has a light-absorbing coating of approximately one-third by weight of glass frit comprising more than 70% by weight of lead oxide, and in addition silicon oxide and boron oxide, as well as the oxides of iron, cobalt and manganese as pigments. It was found that this coating adheres permanently to a lamp vessel made of hard glass, i.e. aluminosilicate glass or borosilicate glass, for example, having a coefficient of thermal expansion in the range of 3*10−6<=coeff. of thermal exp.<=7*10−6, but it quickly starts flaking off glass with an SiO2 content of at least 96% by weight, such as quartz glass, which has a much lower coefficient of thermal expansion than hard glass. Another disadvantage is that this coating comprises substances which are harmful to the environment: cobalt oxide in the pigment and lead oxide in the glass frit. This coating has the further disadvantage that it transmits comparatively much light. This disadvantage becomes proportionally more aggravating as the luminance of the light source is higher, as is the case with, for example, a high-pressure discharge lamp. Such a high-pressure discharge lamp suitable for use as a vehicle headlamp is described in EP 708978. The light-absorbing coating of the lamp disclosed in this document is obtained from, for example, a suspension comprising only silicon powder and iron powder, which is described in patent DE 2837280.

Electric lamp with light-absorbing coating, precursor suspension for such a coating and method of making such a lamp


A method (100) and system (300) is described for processing video data comprising a plurality of images. The method and apparatus is for obtaining for labeling of a plurality of objects or regions in an image of a sequence of images followed by label propagation to other images in the sequence based on an inference step and a model.

The identification of objects in video has different applications in Medical Imaging, Content Analysis, the Film Industry, transport and vehicle control. For objects to be identified, at least during training of the system, typically a human operator label them explicitly. If all images are to be labelled manually this is time consuming.
Label propagation is a very challenging problem because it requires tracking of object regions which lack "visual identity". Adjacent video images in a sequence often have a large noise level making label propagation inherently unstable. Different problems related to labelling and performing segmentation have been discussed in the literature and solutions for facilitating these task have been proposed. One example is the use of an interactive approach whereby a distinct foreground object is precisely extracted from its background. In this approach, the user is closely involved in the refinement of the segmentation of the images. A related problem to label propagation is the colourisation problem. With a few coloured strokes on a greyscale video image, the user specifies how to colourize it in a realistic manner. Whereas the use of colourization is widely spread, converting the produced colours into a label map is not straightforward.

Methods and systems for semantic label propagation


In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.

1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly, to a configuration for reducing power consumption of a semiconductor memory device. More particularly, the present invention relates to a configuration for reducing power consumption of an embedded type DRAM (dynamic random access memory) used in a system LSI.
2. Description of the Background Art
In a system LSI constituted of DRAM and a logic such as a processor, ASIC (application specific integrated circuit) or the like in a merged manner, DRAM and the logic are interconnected to each other using an internal data bus of multiple bits such as 128 bits to 512 bits. This internal data bus is on-chip interconnection lines, and a parasitic capacitance and a parasitic resistance thereof are small as compared with those of on-board interconnection lines. Therefore, such a system LSI can achieve a high data transfer speed as compared with a general-purpose high speed DRAM. Furthermore, as compared with a configuration in which a general-purpose DRAM is mounted external to a logic and both are interconnected through on-board interconnection lines, the number of external data input/output pin terminals of the logic can be decreased and a load capacitance of a data bus line between the logic and DRAM can also be reduced by more than one order of magnitude. Therefore, this system LSI can decrease a consumed current greatly. Owing to these advantages, a system LSI has largely contributed to improvement of a performance of information equipment handling a great amount of data such as those in three-dimensional graphic processing, image and speech processing and others.
FIG. 96 is a diagram schematically showing a configuration of a whole of a conventional embedded DRAM used in a system LSI. In FIG. 96, the embedded DRAM includes: a plurality of memory cell arrays MA0 to MAn; sense amplifier bands SB1 to SBn each arranged between the memory cell arrays MA0 to MAn; and sense amplifier bands SB0 and SBn+1 arranged outside the respective memory cell arrays MA0 and MAn. Each of the memory cell arrays MA0 to MAn is divided into a plurality of memory cell sub arrays MSA by sub word driver bands SWDB.
In a memory cell sub array MSA, memory cells are arranged in rows and columns, and sub word lines SWL are provided corresponding to respective rows. A main word line MWL is commonly provided to memory cell sub arrays MSA divided by the sub word driver bands SWDB A in a memory sub array MA. Main word lines MWL are each provided corresponding to a prescribed number of sub word lines in a memory cell sub array MSA.
In a sub word driver band SWDB, sub word drivers are provided corresponding to the sub word lines SWL. Each sub word driver drives a corresponding sub word line to a selected state according to a signal on a corresponding main word line MWL and a sub decode signal, not shown.
In each of the sense amplifier bands SB0 to SBn+1, sense amplifier circuits are provided corresponding to the columns of a corresponding memory cell array. Each sense amplifier circuit of the sense amplifier bands SB1 to SBn is shared between adjacent memory cell arrays. Row decoders each selecting a main word line according to a row address signal are provided corresponding to the respective memory cell arrays MA0 to Man, and column decoders transmitting a column select signal for selecting a column in a memory cell array according to a column address signal onto a column select line CSL are provided in alignment with the row decoders. Column select lines CSL are provided in respective sense amplifier bands and each connect a prescribed number of sense amplifier circuits to a group of internal data bus line pairs GIOP when selected.
The internal data bus line pairs GIOP are arranged extending over the memory arrays MA0-Man in a column direction. A prescribed number of internal data line pairs GIOP are coupled with selected sense amplifier circuits through local data lines LIO. Row decoders and column decoders are arranged in alignment in a row/column decoder band RCDB, and a propagation distance of a column select signal on a column select line CSL is decreased to achieve high speed column selection.
Internal data line pairs GIOP are provided by 128 bits to 512 bits or more and coupled with a data path band DPB including preamplifiers and write drivers. In the data path band DPB, the preamplifiers and the write drivers are provided corresponding to respective global data line pairs GIOP. A global data line pair GIOP may be a data line pair transmitting both of write data and read data, or may include a bus line pair transmitting read data and a write data line pair transmitting write data may be used independently of each other.
The embedded DRAM further includes: a row address circuit/refresh counter RAFK, a column address input circuit CAK receiving an external address A0 to A12 of, for example, 13 bits applied from a logic; a command decoder/control circuit CDC receiving external control signals applied from the logic to generate internal control signals specifying various operations; and a data input/output controller DIOK for performing transfer of data between the data path band DPB and the logic.
The command decoder/control circuit CDC receives a clock signal CLK, a clock enable signal CKE, a row address strobe signal /RAS a column address strobe signal /CAS, a write enable signal /WE and a data mask signal DM, and determines an instructed operating mode according to logical states of the control signals CKE, /RAS, /CAS, /WE and DM at a rising edge of the clock signal CLK. The term "command" indicates a combination of logical states of the plurality of control signals CKE, /RAS, /CAS and /WE at a rising edge of the clock signal CLK. The data mask signal DM instructs write masking, with a byte being a unit, for data applied to the data input/output controller DIOK. The command decoder/control circuit CDC decodes a command applied from the logic to generate an operating mode instructing signal instructing an operating mode specified by the command and furthermore generates various internal control signals for performing the specified operating mode. Commands include: a row active command for setting a row to a selected state; a read command instructing data reading; a write command instructing data writing; a precharge command for placing a selected row in a non-selected state; an auto-refresh command for performing a refresh operation; and a self refresh command for performing self refresh of storage data.
The row address input circuit/refresh counter RAFK takes in external address bits A0 to A12 as a row address under control of the command decoder/control circuit CDC, when a row active command is supplied, to generate an internal row address. The row address input circuit/refresh counter RAFK includes: an address buffer for buffering received address bits; and an address latch for latching an output signal of the buffer circuit. A refresh counter included in the row address input circuit/refresh counter RAFK generates a refresh address specifying a refresh row when an auto-refresh command or a self-refresh command is supplied. A count value of the refresh counter is incremented or decremented each time the refresh operation is completed. The column address input circuit CAK takes in, for example, lower external address bits A0 to A4 to generate an internal column address signal under control of the command decoder/control circuit CDC when a read command or a write command is supplied. The column address input circuit CAK also includes an address buffer and an address latch.
An internal row address signal from the row address input circuit/refresh counter RAFK is applied to a row predecoder RPD, while an internal column address signal from the column address input circuit CAK is applied to a column predecoder CPD. The row predecoder RPD predecodes the received row address signal to apply the predecoded signal to a row decoder included in the row/column decoder band RCDB. The column predecoder CPD predecodes the internal column address from the column address input circuit CAK to apply the predecoded signal to a column decoder included in the row/column decoder band RCDB.
The command decoder/control circuit CDC generates internal control signals for controlling the operations of data input/output controller DIOK and a preamplifier or a write driver included in the data path band DPB. The clock signal CLK is used as a reference signal determining timings of internal operations of the embedded DRAM.
The data input/output controller DIOK performs data inputting/outputting operation in synchronization with the clock signal CLK, and a row address input circuit in the row address input circuit/refresh counter RAFK and the column address input circuit CAK takes in and latch applied address bits in synchronization with the clock signal CLK.
The embedded DRAM further includes: a block PHK including an internal voltage generating circuit for generating internal voltages VPP, VCCS, VCCP, VBL and VCP; and a self-refresh timer activating a refresh request signal FAY at prescribed intervals when a self-refresh mode is specified (a self-refresh command is supplied). The internal voltage VPP is a voltage transmitted onto a selected sub word line SWL, and is normally higher than an operating power supply voltage. The voltage VCCS is an operating power supply voltage of a sense amplifier circuit included in the sense amplifier bands SB0 to SBn+1, and is generated by an internal voltage down converter, not shown. The voltage VCCP is a peripheral power supply voltage or an operating power supply voltage applied to peripheral circuits such as row decoders and column decoders included in the row/column decoder band RCDB, and to preamplifiers and write drivers included in the data path band DPB. The voltage VBL is a bit line precharge voltage described later. The voltage VCP is a cell plate voltage applied to a cell plate of a memory cell, and is at an intermediate level between an H level voltage and an L level voltage of memory cell data. The voltages VBL and VCP each are an intermediate voltage, which is normally at half a level of the array power supply voltage (a sense power supply voltage) VCCS.
A self-refresh timer of the block PHK is activated after entry into the self-refresh mode, to issue refresh request signals at prescribed intervals with a maximum refresh time tREFmax such that refresh of all the rows of the memory cell arrays MA0 to MAn is completed once in the refresh time. When the number of refreshes required for all the rows of the memory arrays MA0 to MAn is represented by Nref, the refresh request signals are issued in a cycle of tREFmax/Nref. For example, in a 4K refresh mode with Nref=4096, the refresh request signal FAY is repeatedly issued every 16 μsec if the maximum refresh time tREFmax is set to 64 ms.
In the self-refresh mode, refresh of memory cell data is performed in a memory cell array at a prescribed period, for holding stored data in memory cells. The self-refresh mode is normally set in a sleep mode, or while the system LSI is in a standby state over a long period. Hence, in the sleep mode, what is required is only to hold storage data of memory cells; and therefore, a refresh interval is preferably set as long as possible from the viewpoint of low power consumption.
FIG. 97 is a diagram representing a configuration of a sense amplifier circuit included in a sense amplifier band and a peripheral section thereof. In FIG. 97, a sense amplifier SAK is coupled with bit lines BLL and ZBLL through a bit line isolation gate BIGL and also coupled with bit lines BLR and ZBLR of another memory block through a bit line isolation gate BIGR. The bit line isolation gates BIGL and BIGR become conductive/non-conductive in response to bit line isolation instructing signals BLIL and BLRR, respectively.
The sense amplifier SAK differentially amplifies a potential on a common bit line CBL coupled with the bit lines BLL and BLR through the bit line isolation gates BIGL and BIGR and a potential on a common bit line ZCBL coupled with the bit lines ZBLL and ZBLR through the bit line isolation gates BIGL and BIGR. The sense amplifier SAK includes: a pair of cross-coupled P channel MOS transistors P1 and P2, and a pair of cross-coupled N channel MOS transistors N1 and N2. There are provided, as a sense amplifier drive circuit, a P channel MOS transistor P3 for sense amplifier activation that is rendered conductive in response to activation of a sense amplifier activating signal ZSOP to transmit the sense power supply voltage VCCS to a sense power supply node S2P of the sense amplifier SAK, and an N channel MOS transistor N3 for sense amplifier activation that is rendered conductive in response to a sense activating signal SON to couple a sense ground node S2N to a ground node. The common bit lines CBL and ZCBL are further coupled with a pair of local data lines LIO through a column select gate CSG. The pair of local data lines LIO is coupled with global data lines GIO and ZGIO.
Furthermore, the bit lines BLL and ZBLL are provided with a bit line precharge/equalize circuit BEQL activated in response to activation of a bit line equalize instructing signal BLEQL, to transmit the bit line precharge voltage VBL onto the bit lines BLL and ZBLL. The bit lines BLR and ZBLR are provided with a bit line precharge/equalize circuit BEQR activated in response to activation of a bit line equalize instructing signal BLEQR, to transmit the bit line precharge voltage VBL onto the bit lines BLR and ZBLR.
Sub word lines are provided crossing the bit lines BLL and ZBLL, and the bit lines BLR and ZBLR, and memory cells MC are placed corresponding to the crossings. In FIG. 88, a sub word line SWL crossing the bit lines BLL and ZBLL and a memory cell MC placed at a location corresponding to a crossing between the sub word line SWL and the bit line ZBLL are representatively shown. A memory cell MC includes: a memory capacitor MQ for storing information; and an access transistor MT constituted of an N channel MOS transistor and made conductive in response to a potential of the sub word line, to couple the memory capacitor MQ with the bit line ZBLL. A potential on a storage node SN of the memory capacitor MQ is determined according to the stored information, while a cell plate arranged facing to the storage node is supplied with the cell plate voltage VCP.
In the standby state, the bit line isolation instructing signals BLIL and BLIR are at H level of, for example, the boosted voltage VPP level. Thus, the bit line isolation gates BIGL and BIGR are in a conductive state, and the bit lines BLL, CBL and BLR are coupled with each other, and the complementary bit lines ZBLL, ZCBL and ZBLR are coupled with each other. In this state, the bit line equalize instructing signal BLEQL and BLEQR are also in an active state, and the bit lines BLL, CBL and BLR and the complementary bit lines ZBLL, ZCBL and ZBLR are precharged and equalized at the precharge voltage VBL by the bit line precharge/equalize circuits BEQL and BEQR.
When a row active command is applied and a row access is to be made, a bit line isolation gate of a memory cell block including a selected row (sub word line) stays in a conductive state, while a bit line isolation gate for a non-selected memory cell array sharing a sense amplifier with the selected memory cell array (the memory cell array including the selected sub word line) enters a non-conductive state. Now, consider a case where the sub word line shown in FIG. 97 is selected. In this case, the bit line equalize signal BLEQL is in an inactive state at L level, and the bit line precharge/equalize circuit BEQL is deactivated. Furthermore, the bit line isolation instructing signal BLIR is driven to L level, the bit line isolation gate BIGR enters a non-conductive state and the bit lines BLR and ZBLR are disconnected from the common bit lines CBL and ZCBL. In this state, the bit lines BLL and ZBLL of a selected memory cell array enter a floating state at the precharge voltage VBL. The bit line equalize instructing signal BLEQR is in an active state at H level, and the bit lines BLR and ZBLR are held at the bit line precharge voltage VBL level by the bit line precharge/equalize circuit BEQR.
Then, a row select operation is performed and a potential of a selected sub word line rises. When a level of the sub word line SWL rises, the memory access transistor MT of a memory cell MC is made conductive to couple the storage node SN of the memory capacitor MQ with a corresponding bit line (ZBLL). Accordingly, an electric charge accumulated in the capacitor MQ of the memory cell is read onto the associated bit line ZBLL. Since the selected memory cell is not connected to the bit line BLL, the bit line BLL is held at the bit line precharge voltage VBL of the intermediate level. Now, when parasitic capacitance values of the bit lines BLL and ZBLL are represented by CB, a capacitance value of the memory capacitor MQ by CS and a potential on the storage node SN by V(SN), a potential difference ΔV between the bit lines BLL and ZBLL is expressed by the following formula:ΔV=0.5·V(SN)·CS/(CS+CB).
Then, the sense amplifier activating signals ZSP and SON are activated, the MOS transistors P3 and N3 for sense amplifier activation are made conductive, and the sense power supply voltage VCCS and the sense ground voltage are transmitted to sense power source nodes S2P and S2N. When the sense power supply voltage VCCS and the sense ground voltage are transmitted to the sense power source nodes S2P and S2N, the sense amplifier SAK is activated to start a sense operation. Generally, since threshold voltages of the N channel MOS transistors N1 and N2 are smaller in absolute value than threshold voltages of the P channel MOS transistors P1 and P2, an N sense amplifier constituted of the MOS transistors N1 and N2 starts a sense operation first to amplify a potential difference transmitted from the bit lines BLL and ZBLL to the common bit lines CBL and ZCBL. That is, a common bit line of a lower potential level of the common bit lines CBL and ZCBL is driven to the ground voltage level by the MOS transistors N1 and N2. A little later, another common bit line of a higher potential level of the common bit lines CBL and ZCBL is driven to the sense power supply voltage VCCS by the P channel MOS transistors P1 and P2.
When L level data is transmitted onto the common bit lines CBL and ZCBL, a voltage on a common bit line receiving the data of L level is lower than the precharge voltage VBL. On the other hand, when H level data is read out, a voltage of a common bit line receiving the data of H level is higher than the precharge voltage VBL. Hence, since a gate to source voltage of the MOS transistors N1 and N2 is lower when data of L level is read out as compared to the case where data of H level is read out, a sense operation of the N channel MOS transistors N1 and N2 is slower when the data of L level is read out as compared to the case where the data of H level is read out.
A magnitude of the voltage that the sense amplifier SAK senses is proportional to the voltage V(SN) on the storage node SN of the memory cell MC. Hence, in order to increase a sense margin to operate the sense amplifier SAK correctly, it is needed to increase an amount of electric charges read out from the memory cell as much as possible. A potential level on the storage node SN when data of L level is stored is the ground voltage VSS level, and a voltage V(SN) on the storage node SN is the sense power supply voltage VCCS level when data of H level is stored. In order to raise a voltage level on the storage node SN to the possible maximum when data of H level is stored, the boosted voltage VPP is transmitted onto the sub word line SWL. The boosted voltage VPP is a voltage sufficiently higher than the sum of the sense power supply voltage VCCS and a threshold voltage of the access transistor MT. By transmitting the boosted voltage VPP onto the sub word line SWL, the sense power supply voltage VCCS can be transmitted onto the storage node SN without a loss due to the threshold voltage of the memory access transistor MT.
When the sense operation by the sense amplifier SAK is completed, the bit lines BLL and ZBLL are driven to the sense power supply voltage VCCS and the ground voltage level. Thereafter, a read command or a write command (a column access command) is supplied, a column select operation is performed, and a column select signal on the column select line CSL is activated. Responsively, the column select gate CSG for the selected column is made conductive, and the common bit lines CBL and ZCBL are coupled with the global data lines GIO and ZGIO through the local lines LIO, and data writing or reading is performed.
FIG. 98 is a diagram schematically showing a cross sectional structure of a memory cell. In FIG. 98, N type impurity regions 901a and 901b are formed spaced from each other on a surface of a P type substrate region 900. A first conductive layer 902 serving as a word line is formed above a channel region between the impurity regions 901a and 901b with a gate insulating film, not shown, interposed therebetween. The impurity region 901a is connected to a second conductive layer 903 serving as a bit line, while the impurity region 901b is connected to a third conductive layer 904 serving as a storage node SN. The third conductive layer 904 has a leg region connected to the impurity region 901b and a hollow cylindrical region on the leg region. A fourth conductive layer 906 serving as a cell plate electrode is formed on the cylindrical region with a capacitor insulating film 905 interposed therebetween. The fourth conductive layer 906 serving as the cell plate extends across a corresponding to memory cell sub array with a memory cell sub array being a unit, and memory cells in the corresponding memory sub array on the cell plate commonly receive the cell plate voltage VCP at the cell plate nodes. The cylindrical region in an upper portion of the third conductive layer 904 and an facing region of the fourth conductive layer 906 through the capacitor insulating film 905 function as a memory capacitor.
The memory access transistor MT is constructed of the impurity regions 901a and 901b, and the first conductive layer 902. The substrate region 900 functions as a back gate of the memory access transistor MT and receives a negative voltage Vbb. A potential of the third layer 904 is determined according to stored data. However, as shown with a broken line in FIG. 98, electric charge accumulated in the memory capacitor decreases by various leakage currents such as a leakage current through a junction capacitance of the storage node SN (a capacitance of a PN junction between the impurity region 901b and the substrate region 900), a leakage current in a channel region beneath the second conductive layer 902 and a leakage current through the capacitor insulating film 905 and others.
FIG. 99 is a graph representing a change over time in the potential level of the storage node SN. FIG. 99 shows a change in the voltage V(SN) when the precharge voltage VBL (=VCCS/2) is applied on the bit line BL and the ground voltage VSS is applied on the word like WL (the sub word line SWL). The voltage V(SN) on the storage node SN has a time dependency expressed by the following formula due to leakage current:V(SN)≈Vbb+(VCCS−Vbb)·exp(−T/τa), where T indicates a time and a coefficient τa is an electric charge holding characteristic value of a memory cell storing data of H level. As the characteristic value τa is larger, an electric charge holding time of a memory cell is longer.
When data of H level has been written onto the storage node SN, a voltage V(SN) of the storage node SN is at a level of the sense power supply voltage VCCS. The storage node voltage V(SN) gradually decreases with time T due to a leakage current through a PN junction. If a memory cell data is read out onto the bit line when the storage node attains a voltage Vcr at time T1, a potential difference between bit lines, at that time, (Vcr−VBL)·Cs/(Cs+Cb) is lower than a sensitivity of the sense amplifier, where Cs and Cb indicate respective capacitance values of the memory cell capacitor and a bit line parasitic capacitance. That is, after the time T1 elapses, the sense amplifier malfunctions, read error for H data arises in which H level data may be amplified into L level data. Hence, refresh need be performed on this memory cell within a time of T1 to rewrite or restore the data. The characteristic value τa of each memory cell is different from others (due to variation in fabrication parameters), and therefore, a refresh time is determined taking the worst case into consideration. That is, the maximal refresh time tREFmax is determined based on the memory cell with the shortest data holding time, in other words, based on the smallest characteristic value τa available.
In a fabrication process for an embedded DRAM, the same process as that for a logic integrated on the same chip is employed. Therefore, in order to obtain full performances of transistors in the logic, a salicidation process or the like applied on source and drain diffusion layers of a transistor, which has been a standard step in a process for the logic, has been introduced into the process for an embedded DRAM. Hence, a thermal budget (a product of time and temperature in an annealing process) in a high temperature processing applied in formation of the memory capacitor is reduced. For this reason, an impurity region and an insulating film cannot be subject to a thermal process at a prescribed temperature for a sufficient time, resulting in an increased junction leakage current and in an increased leakage current through a capacitor insulating film, although by a small amount.
Furthermore, in a case where a stacked capacitor cell structure of a cylindrical shape is adopted as shown in FIG. 98, a high step is caused between a DRAM section and a logic section. Such a step cannot be perfectly eliminated even when an interlayer insulating film between interconnection lines is planarized to some extent by a CMP (a chemical mechanical polishing) process. Accordingly, a pitch of metal interconnection lines cannot be reduced sufficiently because of irregular reflection and others at steps in an exposure process of a photolithographic process. Hence, a metal interconnection line pitch required for a high density library of a logic is difficult to be achieved. Therefore, with a capacitance value of a memory capacitor sacrificed to some extent, a height of a storage node is decreased (a height of a cylindrical section is decreased) to achieve a complete planarization of an interlayer insulating film between interconnection lines, to eliminate a step between the DRAM section and the logic section for increasing a gate density of a logic library. Therefore, a capacitance value of a memory capacitor is smaller than in a general purpose DRAM and thus, an amount of accumulated electric charges is accordingly reduced.
Furthermore, an embedded DRAM is integrated together with a logic section operating at high speed on the same semiconductor chip. Therefore, temperature of the embedded DRAM section tends to be higher as compared with that of a general purpose DRAM due to heat conduction from the logic. In addition, a power supply line of the embedded DRAM section and the substrate are apt to be affected by noise due to a high speed operation of the logic section. Refresh characteristics of the embedded DRAM are deteriorated as compared with a general purpose DRAM by these various factors in the fabrication process or a chip operation. Moreover, during operation, a refresh time of an embedded DRAM is required to be short as compared with a general purpose DRAM, thereby increasing a current consumed for data holding.
Furthermore, in a case where a logic section ceases its operation as in the sleep mode or the like, a self-refresh is required to be periodically performed in order to hold stored data in the embedded DRAM. In this case as well, a refresh time in the self-refresh mode becomes short as compared with a general purpose DRAM. Therefore, a consumed current in the sleep mode increases. Especially, in a case where a system LSI with an embedded DRAM is applied in products such as a portable information equipment and digital camera driven by a battery, a power consumption is a more predominant factor than increase in storage capacity. Accordingly, increase in consumed current associated with poor refresh characteristics is a serious problem against application to a battery driven equipment.

Refresh-free dynamic semiconductor memory device


This invention relates to a new compound represented by formula (I). Particularly, the new compound is used as an additive in copper electroplating. A chemical structure for the leveler, an electroplating bath containing the same, a method of preparing the additive and a method of electroplating a substrate with the electroplating bath containing the additive are disclosed. The additive compound/molecule of the present invention provides a branched structure at each ends, wherein each of the branches comprises a positively charged nitrogen moiety. The additive compound/molecule is formed by linking the branches having the positive charged nitrogen moieties to the backbone of the additive compound/molecule. This leads to a high charge density novel additive compound/molecule.

During electroplating, a voltage drop variation typically exists along an irregular surface of a substrate which can result in an uneven metal deposit on the substrate. Some parts of the substrate would have been overplated while other parts would have been underplated. This would particularly be a problem when there is a hole on the surface of the substrate. For example, FIG. 1 shows a scanning electron micrograph ("SEM") of a hole 20 on a substrate having copper 22 electroplated on it by a conventional electroplating process (i.e. electroplating a substrate by submerging it into an electroplating bath without any additives). As shown in FIG. 1, the edge of the hole 20 is overplated with copper 22, while the inner walls of the hole 20 are underplated. As a result, the inner volume of the hole 20 is not properly filled and the resulting conductivity of the substrate plated with copper 22 would be greatly affected.
Levelers have been added into the electroplating bath in order to achieve a uniform metal deposit on a substrate surface. Although the conventional levelers improve the quality of metal deposit done by electroplating on the substrate surface, the quality is still not as desired.

Hong Kong Applied Science and Technology Research Institute Company Limited


A method for controlling the mutual angle between the parts of an artificial hip joint during an operation for insertion of the artificial hip joint, is described. The stem of the femoral hip prosthesis is fastened permanently or removable in the usual manner in the proximal end of the femur. A tool for controlling of the mutual angle between the stem of the prosthesis and the cup of the prosthesis is fastened to the stem. The femur of the patient is then oriented in a predefined position and the cup is then brought into its intended position by means of the femur of the patient and the mentioned tool. A tool for controlling the mutual angle between the parts of the artificial hip joint is also described.

The present invention regards the area of orthopaedic surgery, and in particular a method of and devices for ensuring that prosthesis components are inserted correctly upon implantation of artificial hip joints into humans. In particular, the invention is directed at a method of and devices for ensuring the correct mutual positioning of the prosthesis components.
An artificial hip joint has two main components; a prosthesis stem and a cup. One end of the prosthesis stem is provided either with a spherical ball head or a prosthesis neck on which can be placed a ball head, where the ball head is designed for a close, sliding fit in a spherical recess in the cup. Together, the prosthesis stem with the ball head and the cup will act as a ball joint to replace the natural ball joint.
The other end of the prosthesis stem comprises an elongated part designed to be attached to the hollow femoral canal in the patient's femur.
The cup is designed to be attached to the cavity on the patient's pelvis. The hemispherical shaped recess in the cup is linked with an exterior surface designed to be attached to the pelvis, via a side face. The exterior surface may have various shapes, all according to the method of attachment to the pelvis and other choices made by the supplier. Several of the cups that are in use are shaped as an approximate hemisphere, where the outer hemispherical surface is designed to be cemented to the pelvis. The side face that connects the recess and the exterior surface may be flat or possibly inwardly sloping towards the recess, which is preferably approximately centred in the side face.
The prosthesis stem and the cup may be fixed to the femur and the pelvis respectively by using cement, or through a cement-free force fit. The invention may be used with both fixation techniques.
When replacing a worn out hip with a prosthesis, the head of the femur is replaced. This is done by cutting the neck of the femur and hollowing out the top of the femoral canal in order to make room for the elongated prosthesis stem that is either cemented into the hole or force fitted.
The cavity on the pelvis is milled out to receive the cup, which is then fixed either by means of cement or a force fit.
If the ball head is detachable, this is placed on the prosthesis stem before the ball head is placed in the cup, the joint is assembled by lifting the patient's leg up to a natural position and inserting the ball head in the recess in the cup, whereupon the incision is closed.
Such a prosthesis should give the patient a mobility that approximates that which is provided by the natural joint. Moreover, it is important that a "natural" movement of the joint does not cause the patient to get in a situation where the leg ends up in positions where the neck of the prosthesis rides on the edge of the cup. This may cause luxation of the joint, where the head of the prosthesis jumps out of the cup. This happens through simple leverage. Luxation occurs in the case of between 3 and 10% of all patients who have had a femoral prosthesis put in. If this happens, the patient must be anaesthetised before the joint is put back into place. Some patients must have a new operation. The risk of luxation is much greater in patients whose prosthesis components are assembled so as to have an incorrect mutual positioning, than in those where the mutual positioning of the components is correct.
The inventor has previously shown that an optimum mutual relationship between the prosthesis stem and the cup under experimental conditions (not published) results in a reduced risk of luxation because the patient can go through the everyday natural range of motion (ROM) without the parts of the prosthesis ending up in such mutual positioning so as to entail a risk of luxation.
The inventor has previously shown (not published) that the most adequate ROM is achieved by assembling both prosthesis components in a manner so as to give them a forward angle of about 15 degrees relative to the frontal plane of the body, while the cup forms an angle of 45 degrees with the horizontal plane. In medical terminology, forward angling is termed anteversion.
The inventor has also previously shown (not published) that even though the optimum is to have each of the components angled forwards at 15 degrees, the result is nearly as good if the sum of the forward angling of the two components is 30 degrees. Thus a prosthesis joint where the cup is angled forwards at 5 degrees and the prosthesis stem is angled forwards at 25 degrees will result in a ROM for the patient that is nearly as adequate as if both components were angled forward at 15 degrees, the sum of the forward angling being 30 degrees is both cases
Today there are no means available to ensure that the surgeon installs the prosthesis components with this correct mutual relationship. With today's methods therefore, this is done as judged by the eye. This judgement may be sufficient, especially for experienced surgeons who carry out a considerable number of this type of operation each year. It is estimated that 80% of all implantations of artificial hip joints are carried out by surgeons who do less than 20 of these every year. This number is not sufficient to get enough practice. It is therefore desirable to have a method and means that ensure a correct mutual positioning of the main parts of the prosthesis in order to reduce the possibility of errors, and thereby also reduce the risk of luxation with the resulting pain for the patient, and a possible second operation.

Tool for controlling the mutual angle between the parts of an artificial hip joint


There is provided an information processing apparatus among a plurality of information processing apparatuses included within an information processing system, the information processing apparatus including a memory, a processor coupled to the memory and configured to perform information processing, and a controller configured to acquire a plurality of sensor data items output from each a plurality of sensors arranged in a liquid cooling system cooling the plurality of information processing apparatuses and abnormality information relating to the liquid cooling system stored by another information processing apparatus among the plurality of information processing apparatuses, detect an abnormality of the liquid cooling system based on the acquired sensor data items and the abnormality information, obtain a range of influence of the detected abnormality of the liquid cooling system based on the detected abnormality, and control the information processing apparatus based on the range of influence.

A liquid cooling technology in a server (x86 server) adopting an x86 based central processing unit (CPU) and an architecture is also applied to a supercomputer system in a high-performance computing (HPC) field.
FIG. 1 illustrates an example of a cooling system combined with a liquid cooling technology in the related art and an air cooling technology. A heat exchanger 102 is provided on an information technology (IT) device side including a server 101, and an air conditioning device 103 and a cooling facility 104 are provided on a facility side. The cooling facility 104 is a cooling tower, a chiller, or the like. A fan 111 and a pump 112 are provided in the server 101 and a pump 113 and a blower 114 are provided in the cooling facility 104.
Heat discharged from a CPU, a memory, and the like, which are main heat generating components in the server 101 is transferred to the heat exchanger 102 by the secondary side cooling water circulated by the pump 112. The heat exchanger 102 cools the secondary side cooling water by performing heat exchange between the secondary side cooling water and the primary side cooling water circulated by pump 113. The cooling facility 104 cools the primary side cooling water by taking outside air by the blower 114.
Meanwhile, other components such as a hard disk drive (HDD) in the server 101 are cooled by air from the fan 111 and the air conditioning device 103. For example, the proportion of waste heat cooled by liquid cooling is approximately 80%, and the proportion of waste heat cooled by air cooling is approximately 20%.
There are also known an information processing system that detects the states of a plurality of information processing apparatuses of other cases by a plurality of information processing apparatuses of an own case and shuts down a power supply, and a system that shuts down a server when water droplets are detected (for example, see Japanese Laid-open Patent Publication No. 2015-156102 and Japanese Laid-open Patent Publication No. 2015-53004).

Information processing apparatus and information processing system


A semiconductor chip includes an active inner circuit; a die seal ring surrounding the active inner circuit; a first circuit structure fabricated at a first corner of the semiconductor chip outside the die seal ring and electrically connected to the die seal, wherein the first circuit structure has a first solder pad; and a second circuit structure fabricated at a second corner of the semiconductor chip outside the die seal ring and electrically connected to the die seal, wherein the second circuit structure has a second solder pad.

1. Field of the Invention
The present invention relates generally to the reliability test of semiconductor integrated circuit chips and, more particularly, to an on-chip test circuit constructed at corners of an integrated circuit chip or die for assessing chip integrity.
2. Description of the Prior Art
Semiconductor manufacturers have been shrinking transistor size in integrated circuits (IC) to improve chip performance. This has resulted in increased speed and device density. For sub-micron technology, the RC delay becomes the dominant factor. To facilitate further improvements, semiconductor IC manufacturers have been forced to resort to new materials utilized to reduce the RC delay by either lowering the interconnect wire resistance, or by reducing the capacitance of the inter-layer dielectric (ILD). A significant improvement was achieved by replacing the aluminum (Al) interconnects with copper, which has ˜30% lower resistivity than that of Al. Further advances are facilitated by the change of the low-k dielectric materials.
However, one shortcoming associated with the use of low-k dielectrics is that almost all low-k dielectric materials possess relatively lower mechanical strength than that of conventional silicon oxide dielectrics such as FSG or USG. The use of low-k dielectrics poses this industry another problem that the adhesion ability, either at the interface between two adjacent low-k dielectric layers or at the interface between a low-k dielectric layer and a dissimilar dielectric layer, is somewhat inadequate to meet the requirements in the subsequent wafer treatment processes such as wafer dicing, which is typically performed to mechanically cut a semiconductor wafer into a number of individual IC chips.
Delamination or cracking that occurs during scribing, dicing or temperature cycling test is problematic and may cause circuit chip failures. One approach to monitoring of the interface delamination or chip cracking is so-called Scanning Acoustic Tomography (SAT) or Scanning Acoustic Microscopy (SAM) technique. The SAM technique, which can be implemented either after dicing (i.e., bare die check) or after chip packaging (i.e., packaged IC check), utilizes superimposed ultrasonic pulse and echo signals to detect the delamination or cracking defects formed in the integrated circuit chips or packages.
However, the SAM technique has some drawbacks. During the bare die check after dicing, very small cracks are difficult to detect because of the detection limit of the SAM tools. Typically, the detection limit of the commercial SAM tools is about 1 micrometer. On the other hand, even the delamination defect is detectable it is often difficult to characterize the specific location of the defect for the packaged IC check. That is, the information whether the defect is in the interlayer of the IC chip or at the interface between the IC chip and packaging material is not available.
Therefore, a need exists in this industry for a sensitive, but inexpensive approach to the detection of the delamination or cracking defects formed in the integrated circuit chips or packages.

On-chip test circuit for assessing chip integrity


A method of and a system for broadband/infrastructure providers to set, control, operate a coercive/disruptive controller (CDC) to manage and provide broadband content to an end user device. A controller controls broadband content and communication from a broadband network access device to an end user device. The controller utilizes content-specific quality of service (QoS) parameters and operation logic to selectively process broadband content transmitted to the end user devices. The controller operates independently or is dynamically set and controlled by a remotely coupled controller or server. Broadband content is managed and administered according to the QoS parameters, where the QoS parameters are content specific. As such, the QoS parameters are set/reset, assigned/reassigned based on the broadband content, making the QoS related to the broadband content independent of the content provider.

Current broadband transmission occurs from broadband infrastructure providers to end users via such infrastructure as telephone DSL, TV cable, satellite, etc. Broadband content, such as movies, music, TV shows, web access, etc., that is transmitted over the broadband transmission infrastructure is provided by content providers. Some broadband infrastructure providers determine which content providers can provide content over their networks. For example, a cable television service provider determines which channels, such as HBO, ESPN, or CNN, are available to their end user customers.
Current state of the art of QoS (Quality of Service) is available for the broadband transmission infrastructure, that is the physical infrastructure from the broadband infrastructure service provider location to end user premise located broadband network devices, such as a DSL/cable termination, DSL/cable modem, wireless/wired router, or general access point. The QoS is applied to the physical transmission medium, and as such, the quality of all content provided over any given physical medium is dependent on the QoS of that given physical medium. All content provided over the given physical medium is subject to the same QoS.
However, the broadband infrastructure provider has no control over the actual content that is provided by the content providers. The broadband infrastructure provider may wish to manage, or even block, certain content within the content provided by the content provider, but is unable to modify the content provided. A QoS is not available for broadband "content", especially from the end user broadband network device to an end user device such as a computer, TV, or telephone. In other words, current QoS methodologies enable broadband transmission infrastructures with required quality levels, but do not provide selective control of the "content" that is transmitted over these same infrastructures.

This patent is subject to a terminal disclaimer.

Apparatus for controlling broadband access and distribution of content and communications through an access point


In an embodiment, a computer-implemented method of selecting sampling locations in a field is disclosed. The method comprises receiving, by a processor, input data including a map for a management zone in a field indicating one or more values of a set of agricultural characteristics for each of a plurality of locations in the management zone. The method further comprises identifying, by the processor, a set of values for the set of agricultural characteristics for each of a group of locations in the management zone based on map. In addition, the method comprises normalizing a set of model values for the set of agricultural characteristics used by an agricultural modeling tool and the set of values of the set of agricultural characteristics for each of the group of locations in the management zone. The method also comprises selecting one of the group of locations as a sampling location based on the normalized set of model values, the normalized sets of values for the group of locations, and a first distance constraint related to a distance to a boundary of the management zone. Finally, the method comprises causing display of information regarding the selected location.

The approaches described in this section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section.
Application of an agricultural treatment to a crop field, such as a soil fertilizer, can help improve the health of the crop field and increase yield. As an agricultural treatment may require a substantial investment of time, labor, or money, an agricultural modeling tool could assist in applying such an agricultural treatment in a precise, cost-effective manner. For example, the agricultural modeling tool can predict the amount of nitrate currently in the soil based on the soil's physical properties, field topography, or other environmental factors, and growers could use the model-predicted nitrate levels to determine the amount of nitrogen fertilizers that need to be added to the soil to achieve a certain crop yield. However, variability often exists in one of the soil's physical properties across a crop field, for example. Modeling results produced by the agricultural modeling tool would be more accurate when the actual field condition is similar to the field condition assumed by the agricultural modeling tool.

Location selection for model assessment sampling


Disclosed herein are methods for humanizing antibodies based on selecting variable region framework sequences from human antibody genes by comparing canonical CDR structure types for CDR sequences of the variable region of a non-human antibody to canonical CDR structure types for corresponding CDRs from a library of human antibody sequences, preferably germline antibody gene segments. Human antibody variable regions having similar canonical CDR structure types to the non-human CDRs form a subset of member human antibody sequences from which to select human framework sequences. The subset members may be further ranked by amino acid similarity between the human and the non-human CDR sequences. Top ranking human sequences are selected to provide the framework sequences for constructing a chimeric antibody that functionally replaces human CDR sequences with the non-human CDR counterparts using the selected subset member human frameworks, thereby providing a humanized antibody of high affinity and low immunogenicity without need for comparing framework sequences between the non-human and human antibodies. Chimeric antibodies made according to the method are also disclosed.

Antibodies are natural proteins that the vertebrate immune system forms in response to foreign substances (antigens), primarily for defense against infection. For over a century, antibodies have been induced in animals under artificial conditions and harvested for use in therapy or diagnosis of disease conditions, or for biological research. Each individual antibody producing cell produces a single type of antibody with a chemically defined composition, however, antibodies obtained directly from animal serum in response to antigen inoculation actually comprise an ensemble of non-identical molecules (i.e., polyclonal antibodies) made from an ensemble of individual antibody producing cells.
Hybridoma technology provided a method to propagate a single antibody-producing cell for an indefinite number of generations with a screening method to identify clones of cells producing an antibody that would react with a particular antigen. Development of this technology allowed production in unlimited quantities of structurally identical antibodies with essentially any desired antigenic specificity. Such antibodies are commonly called monoclonal antibodies, and most originate from rodents. Sequencing of monoclonal antibody genes allowed the primary amino acid structure of the antibody be defined.
The advent of recombinant DNA methodology enabled structural engineering of antibody genes and production of modified antibody molecules with properties not obtainable by hybridoma technology. In the therapeutic arena, one aim of this methodology has been to reduce the immunogenicity in humans of rodent monoclonal antibodies by modifying their primary amino acid structure. Reduction of the immunogenicity of therapeutic antibodies is desirable because induction of an immune response can cause a spectrum of adverse effects in a patient, ranging from accelerated elimination of the therapeutic antibody, with consequent loss of efficacy, to fatal anaphylaxis at the most extreme.
One strategy to reduce immunogenicity of foreign monoclonal antibodies has been to replace the light and heavy chain constant domains of the monoclonal antibody with analogous domains of human origin leaving the variable region domains of the foreign antibody intact. The variable region domains of the light and heavy chains are responsible for the interaction between the antibody and the antigen. The joining domains connecting variable domains to constant domains are situated in a region remote from the site of antigen binding, therefore, the joining domains between variable and constant domains generally do not interfere with antigen binding. Chimeric antibody molecules having mouse variable domains joined to human constant domains usually bind antigen with the same affinity constant as the mouse antibody from which the chimeric was derived. Such chimeric antibodies are less immunogenic in humans than their fully murine counterparts. Nevertheless, antibodies that preserve entire murine variable domains tend to provoke immune responses in a substantial fraction of patients. For example, INFLIXIMAB™, a widely prescribed chimeric antibody that is considered safe, induced a human anti-chimeric antibody response in 7 out of 47 Crohns Disease patients. (Rutgeerts, P., et al (1999) Efficacy and safety of retreatment with anti-tumor necrosis factor antibody (INFLIXIMAB) to maintain remission in Crohn's disease. Gastroenterology 117, 761-769).
That humans would mount an immune response to whole murine variable domains was predictable, thus, efforts to obtain variable domains with more human character had begun even before clinical trials of such standard chimeric antibodies had been reported. One category of methods frequently referred to as "humanizing," aims to convert the variable domains of murine monoclonal antibodies to a more human form by recombinantly constructing an antibody variable domain having both mouse and human character. Humanizing strategies are based on several consensual understandings of antibody structure data. First, variable domains contain contiguous tracts of peptide sequence that are conserved within a species, but which differ between evolutionarily remote species, such as mice and humans. Second, other contiguous tracts are not conserved within a species, but even differ even between antibody producing cells within the same individual. Third, contacts between antibody and antigen occur principally through the non-conserved regions of the variable domain. Fourth, the molecular architecture of antibody variable domains is sufficiently similar across species that correspondent amino acid residue positions between species may be identified based on position alone, without experimental data.
Humanized strategies share the premise that replacement of amino acid residues that are characteristic of murine sequences with residues found in the correspondent positions of human antibodies will reduce the immunogenicity in humans of the resulting antibody. However, replacement of sequences between species usually results in reduction of antibody binding to its antigen. The art of humanization therefore lies in balancing replacement of the original murine sequence to reduce immunogenicity with the need for the humanized molecule to retain sufficient antigen binding to be therapeutically useful. This balance has been struck using two approaches.
In one approach, exemplified by U.S. Pat. No. 5,869,619 to Studnicka and by Padlan (1991) A possible procedure for reducing the immunogenicity of antibody variable domains while preserving their ligand binding properties, Molecular Immunology 28:489-498, characteristically human residues are substituted for murine variable domain residues that are determined or predicted (i) to play no significant chemical role in the interaction with antigen, and (ii) to be positioned with side chains projecting into the solvent, Thus, exterior residues remote from the antigen binding site are humanized, while interior residues, antigen binding residues, and residues forming the interface between variable domains remain murine. One disadvantage of his approach is that rather extensive experimental data is required to determine whether a residue plays no significant chemical role in antigen binding or will be positioned in the solvent in a particular three dimensional antibody structure.
In another more general approach, exemplified by U.S. Pat. No. 5,225,539 to Winter and by Jones et al (1986) Replacing the complementarity determining regions in a human antibody with those from a mouse, Nature 321:522-525, contiguous tracts of murine variable domain peptide sequence considered conserved are replaced with the correspondent tracts from a human antibody. In this more general approach, all variable domain residues are humanized except for the non-conserved regions implicated in antigen binding. To determine appropriate contiguous tracks for replacement, Winter, and Jones et al (1986) utilized a classification of antibody variable domain sequences that had been developed previously by Wu and Kabat (1970).
Wu and Kabat pioneered the alignment of antibody peptide sequences, and their contributions in this regard were several-fold: First. through study of sequence similarities between variable domains, they identified correspondent residues that to a greater or lesser extent were homologous across all antibodies in all vertebrate species, inasmuch as they adopted similar three-dimensional structure, played similar functional roles, interacted similarly with neighboring residues, and existed in similar chemical environments. Second, they devised a peptide sequence numbering system in which homologous immunoglobulin residues were assigned the same position number. One skilled in the art can unambiguously assign what is now commonly called Kabat numbering, to any variable domain sequence, without reliance on any experimental data beyond the sequence itself. Third, for each Kabat-numbered sequence position, Kabat and Wu calculated variability, by which is meant the finding of few or many possible amino acids when variable domain sequences are aligned. They identified three contiguous regions of high variability embedded within four less variable contiguous regions. Other workers had previously noted variability approximately in these regions (hypervariable regions) and posited that the highly variable regions represented amino acid residues used for antigen binding. Kabat and Wu formally demarcated residues constituting these variable tracts, and designated these "complementarity determining regions" (CDRs), referring to chemical complementarity between antibody and antigen. A role in three-dimensional folding of the variable domain, but not in antigen recognition, was ascribed to the remaining less-variable regions, which are now termed "framework regions". Fourth, Kabat and Wu established a public database of antibody peptide and nucleic acid sequences, which continues to be maintained and is well known to those skilled in the art.
The humanization method disclosed by Winter and Jones using the Kabat classification results in a chimeric antibody comprising CDRs from one antibody and framework regions from another antibody that differs in species origin, specificity, subclass, or other characteristics. However, no particular sequences or properties were ascribed to the framework regions, indeed, Winter taught that any set of frameworks could be combined with any set of CDRs. Framework sequences have since been recognized as being important for conferring the three dimensional structure of an antibody variable region necessary retain good antigen binding. Thus, the general humanizing methods described by Winter and Jones have the disadvantage of frequently leading to inactive antibodies because these references do not provide information needed to rationally select among the many possible human framework sequences, those most likely to support antigen binding required by a particular CDR region from a non-human antibody. Subsequent developments in the field have been refinements within the scope of Winter to deal with loss of avidity for antigen observed with some humanized antibodies relative to the avidity of the corresponding mouse antibodies. (Avidity is a quantitative measure of partitioning of an antibody, in the presence of antigen under conditions approximating chemical equilibrium, between free and antigen-bound forms. For reactions in solution not subject to multivalent binding effects, avidity is the same as affinity, the biochemical equilibrium constant).
U.S. Pat. No. 5,693,761 to Queen et al, discloses one refinement on Winter for humanizing antibodies, and is based on the premise that ascribes avidity loss to problems in the structural motifs in the humanized framework which, because of steric or other chemical incompatibility, interfere with the folding of the CDRs into the binding-capable conformation found in the mouse antibody. To address this problem, Queen teaches using human framework sequences closely homologous in linear peptide sequence to framework sequences of the mouse antibody to be humanized. Accordingly, the methods of Queen focus on comparing framework sequences between species. Typically, all available human variable domain sequences are compared to a particular mouse sequence and the percentage identity between correspondent framework residues is calculated. The human variable domain with the highest percentage is selected to provide the framework sequences for the humanizing project. Queen also teaches that it is important to retain in the humanized framework, certain amino acid residues from the mouse framework critical for supporting the CDRs in a binding-capable conformation. Potential criticality is assessed from molecular models. Candidate residues for retention are typically those adjacent in linear sequence to a CDR or physically within 6 Å of any CDR residue.
In other approaches, criticality of particular framework amino acid residues is determined experimentally once a low-avidity humanized construct is obtained, by reversion of single residues to the mouse sequence and assaying antigen binding as described by Riechmann et al, (1988). Another example approach for identifying criticality of amino acids in framework sequences is disclosed by U.S. Pat. No. 5,821,337 to Carter et al, and by U.S. Pat. No. 5,859,205 to Adair et al. These references disclose specific Kabat residue positions in the framework, which, in a humanized antibody may require substitution with the correspondent mouse amino acid to preserve avidity. One of the disadvantages of the refinements by Queen, and the approaches of Ricechmann, Carter and Adair, is that a very large number of human framework sequences are required for comparison, and/or the guidelines for preserving critical amino acid residues are not completely sufficient to predict functionality. Accordingly, the resulting frameworks constructed, which are part human and part mouse, still frequently exhibit human immunogenicity or lowered antigen binding, thereby requiring numerous iterations in framework construction to obtain a suitable framework for therapeutic uses.
A second type of refinement to Winter is exemplified by Padlan et al (1995) Identification of specificity-determining residues in antibodies, FASEB J. 9:133-139; and Tamura et al (2000) Structural correlates of an anti-carcinoma antibody: identification of specificity-determining residues (SDRs) and development of a minimally immunogenic antibody variant by retention of SDRs only. J. Immunol. 164:1432-1441. These references share the premise that increasing the proportion of characteristically human sequence in a humanized antibody will reduce that antibody's immunogenicity, and accordingly disclose methods for grafting partial CDR sequences. Determination of the three-dimensional structure of antibody-antigen complexes showed that many residue positions assigned to the CDRs defined by Kabat and Wu rarely were directly involved in antigen binding. These references showed that grafting a subset of CDR residues would adequately transfer antigen binding in a humanized antibody. However, humanized framework sequences are still required, and these references do not teach methods for selecting adequate human framework sequences for use with a given set of mouse CDRs.
There is therefore, a need in the art for methods of humanizing antibodies that reliably identify suitable human framework sequences to support non-human CDR regions and to provide humanized antibodies that retain high antigen binding with low immunogenicity in humans, without the need for direct comparison of framework sequences, without need for determining critically important amino acid residues in the framework, and without need for multiple iteration constructions to obtain humanized antibodies with suitable therapeutic properties.

Method of humanizing antibodies by matching canonical structure types CDRs


To provide a backup method that allows a reliable backup when a fault occurs in a way that improves a backup speed. The backup method for requesting a backup system to back up files (31) stored on a predetermined NAS of plural NASs (1 and 2) in response to a backup request given from a client computer, includes: selecting backup target files based on the backup request given from the client computer; allocating the selected backup target files (31) respectively to the plural NASs (1 and 2); and causing the respective NASs to request the backup system to back up the allocated files (31) in parallel (102 and 202).

The present invention relates to an improvement of a technology of backing up files stored on a NAS(Network Attached Storage).
A technology known, in which when the backup is conducted by use of plural computers, if a fault occurs on one computer, the other computer resumes the backup (refer to, e.g., JP 2000-353104 A).
Further, in this example, if the fault occurs on one computer, the other computer resumes the backup after rewinding a tape drive.

Control system of NAS, backup method, and program therefor


The present invention provides rotary positioning structure of the ratchet screwdriver. The rotary positioning structure includes two radial grooves, penetrating radially between the body of the ratchet screwdriver and the central axle hole. There are two -shaped snappers having a transverse rack and two vertical racks, and each is mounted separately into two radial grooves. The two vertical racks are inserted into two vertical slots. The transverse rack is placed opposite to the top flange of gear of the shaft lever. A flexible locker is used to press down the two -shaped snappers. A rotating drum is mounted and limited externally onto the body, while two troughs are arranged at intervals onto an inner wall of the retaining block opposite to the lower rivet holder, thereby forming a rotary positioning structure and offering a higher stability of positioning and ease-of-operation.

1. Field of the Invention
The present invention relates generally to a ratchet screwdriver, and more particularly to a ratchet screwdriver with a rotary positioning structure.
2. Description of Related Art Including Information Disclosed Under 37 CFR 1.97 and 37 CFR 1.98
The ratchet screwdriver is exclusively designed such that the shaft lever could be positively driven (otherwise in an idle state), or reversely driven (otherwise in an idle state), or driven in both directions. The multiple drive modes are implemented through a rotary positioning structure for the ratchet screwdriver.
For the rotary positioning structure of a typical ratchet screwdriver, Taiwanese patent bulletin No. 500022 refers to "an improved structure of a ratchet screwdriver (one)" by the present inventor. FIG. 1 of the bulletin depicts the rotary positioning structure of the typical ratchet screwdriver. The shaft lever 10 for the screwdriver permits the body 11 to be screwed into central axle hole 13 through the pigeon hole 12. The leading edge of gear 14 of the shaft lever 10 is limited by inserting a spacing board 16 into an embedding groove 15 from the bottom of the body 11, such that the shaft lever 10 cannot slide. In addition, the body 11 is fitted with a tube shell 17, and a toggle button 18 is positioned between stop plates 19 and the preset mounting hole 21 of the tube shell 17, such that the toggle block 22 on top of toggle button 18 can be fixed into the mounting hole 21.
The following problem is observed from such typical structure during applications. The shaft lever 10 is fixed by two stop plates 19 and a spacing board 16. Yet, these two stop plates 19 are laterally placed at the gear 14 of the shaft lever 10, and the stop plates 19 are abutted with the gear 14 only through a flange of the plate. Thus, another spacing board 16 shall be designed, and an embedding groove 15 shall be placed at the bottom of the body 11 for insertion of the spacing board 16. But, the shaft lever 10 cannot be fixed stably. So, the positioning structure of shaft lever 10 for the typical ratchet screwdriver still lacks robustness.
Another problem is that the switching of a typical ratchet screwdriver is achieved through the slide of the toggle block 22 in order to control the swaying state of two stop plates 19. However, the switching distance of three modes (positive, reverse and bi-directional) is extremely short (approx. 5 mm) due to the short motion of brake disc 23 of toggle block 22 on the stop plate 19. In such case, it often leads to stronger application of force and excessive toggling, so the user has to adjust its force to achieve the switching.
Thus, to overcome the aforementioned problems of the prior art, it would be an advancement in the art to provide an improved structure that can significantly improve efficacy.
To this end, the inventor has provided the present invention of practicability after deliberate design and evaluation based on years of experience in the production, development and design of related products.

Rotary positioning structure of a ratchet screwdriver


A hearing aid (60A) configured to be worn by a hearing-impaired user has a speech detector (10A) and a speech enhancer (40A) for enhancing speech being present in an input signal of the hearing aid (60A). The speech detector (10A) has means (11, 12) for independently detecting the presence of voiced and unvoiced speech in order to allow for the speech enhancer (40A) to increase the gain of speech signals suitably fast to incorporate the speech signals themselves. The hearing aid (60A) has means (49A, 50A) for communicating information regarding the detected speech signals wirelessly to a similar hearing aid (60B) worn contralaterally by the user for the purpose of mutually enhancing speech signals in the two hearing aids (60A, 60B) when speech is detected to be originating from the front of the user, and means (52B) for suppressing speech enhancement in the contralateral hearing aid (60B) when speech is detected to be originating from the ipse-lateral side of the user. The invention further provides a method of enhancing speech in a hearing aid.

1. Field of the Invention
This application relates to hearing aids. The invention, more specifically, relates to hearing aids having means for enhancing speech reproduction. The invention further relates to a method of processing signals in a hearing aid.
A hearing aid is defined as a small, battery-powered device, comprising a microphone, an audio processor and an acoustic output transducer, configured to be worn in or behind the ear by a hearing-impaired person. By fitting the hearing aid according to a prescription calculated from a measurement of a hearing loss of the user, the hearing aid may amplify certain frequency bands in order to compensate the hearing loss in those frequency bands. In order to provide an accurate and flexible means of amplification, most modern hearing aids are of the digital variety. Digital hearing aids incorporate a digital signal processor for processing audio signals from the microphone into electrical signals suitable for driving the acoustic output transducer according to the prescription. In a digital hearing aid, the reproducible frequency range may be conveniently split up into a plurality of frequency bands by a corresponding plurality of digital band-pass filters. This band-split allows the hearing aid to process each frequency band independently with respect to e.g. gain and compression, providing a highly flexible means of processing audio signals.
2. The Prior Art
WO-A1-98/27787 presents a hearing aid with a percentile estimator for determining noise levels and signal levels in an input signal for the hearing aid. A noise level is determined as a 10% percentile level of the input signal, and a signal level is determined as a 90% percentile level of the input signal. It is possible for the signal processor of the hearing aid to make an educated guess about the presence and the level of speech given the difference between the 90% percentile level and the 10% percentile level. In other words, the difference between the 90% percentile and the 10% percentile determines the level of speech. In the following, this method is denoted the percentile difference method. This way of detecting speech works to satisfaction in steady noise or in quiet surroundings, but may not perform adequately in sound environments where the noise varies a lot, e.g. in a cafeteria, at parties, or where background music is present, because the percentile difference method is rather sensitive to modulated noise.
WO-A1-2004/008801 discloses a hearing aid having means for calculating a speech intelligibility index (SII) of an input signal, and means for enhancing a speech signal by optimizing the SII value of the input signal. During use of the hearing aid, the SII value is constantly analyzed and the signal processing is continuously altered in order to keep the SII at an optimal value for the purpose of enhancing speech and reducing noise. The precision of this system is very high, but its adaptation speed is poor due to the complex and involved nature of the calculation of the speech intelligibility index. Whenever the noise level rises, the adaptation speed of the speech intelligibility noise reduction system is approximately 1.8-2 dB/s, and about 17 dB/s whenever the noise level falls, and this adaptation speed may not be sufficient, e.g. in sound environments where modulated noise is present.

Hearing aid and a method of enhancing speech reproduction


A temporal data control system that uses a hand held, mobile scrubwheel that includes two position indicators and an activation switch. As a user moves the scrubwheel about on a surface of a position sensing tablet a computer controls the movement of a cursor on a display. The computer also displays one or more temporal sequences, such as video sequences, on the display. Movement of the scrubwheel is detected by the computer allowing the user to position the cursor on a sequence to be controlled which the computer interprets as selecting the sequence. The computer detects rotation of the scrubwheel and controls the forward and backward motion (and speed) of the sequence responsive to the rotation. By moving the device to another location on the surface the user can select another sequence to control. The user can "point-and-scrub" temporal sequences.

1. Field of the Invention
The present invention is directed to system for controlling the display of temporal data, such as a video sequence and, more particularly, to a system that provides a mobile scrubwheel that can be used to not only select the temporal data to be controlled but also to make the temporal data move forward or backward in time.
2. Description of the Related Art
In editing motion video images the editor is typically provided with a control board that allows the user to cause a temporal image or a video sequence to move forward and backward at various speeds as well as to pause. The forward and backward motion is often controlled by a wheel set within the control board that is sometimes called a "scrubwheel" or a "jog/shuttle wheel". As the editor rolls the scrubwheel one direction the video sequence moves forward and as the wheel is rolled in the other direction the sequence goes backward. Typically a single control board can be used to control several monitors and video sequences with a monitor dedicated to a particular video sequence. The set of controls for the particular monitor include the scrubwheel providing a scrubwheel that is dedicated to the particular monitor and video sequence. When the editor wants to control a different video sequence a different set of controls (scrubwheel) may be used or a single control unit may be used (switching between the various video signals using pushbuttons).
Today, video as well as other temporal data editing, such as for animation sequences and music, is being done with computers. These editing systems often show two or more sequences on the same display with the sequences being controlled by the single computer. The temporal data is often divided into frames such that one picture of a video sequence corresponds to one frame. Typically, the user must use an input device, such as a mouse, to select a video sequence to be controlled, to select a displayed tool with which to control the sequence, such as a slider, and to then manipulate the displayed tool to control the motion of the sequence. The user must go through the same steps to control a different video sequence. This type of control is awkward and slow.
What is needed is a system that allows the user to display several video sequences simultaneously and use the same device to select and control the sequences without the need for displayed tools.


Techniques and circuitry are provided for programmatically controlling signal offsets in integrated circuitry. In one embodiment, a buffer circuit having an offset cancellation circuit receives a signal and transmits the signal to programmable logic circuit. The programmable logic uses programmable resources and/or one or more algorithms to measure integrated circuit operations and/or operational errors associated with the offset. The control signal is fed back to an input of the offset cancellation circuit. In one embodiment, the offset cancellation circuit adjusts the offset of the signal in response to the magnitude of the offset cancellation signal received until changes associated with the offset and/or the magnitude of the operational errors are no longer attributable to the offset.

The present invention relates to techniques for controlling signal offsets, and more particularly, to techniques for dynamically correcting offsets associated with integrated circuit buffers and amplifiers using programmable resources.
Generally, interface circuitry such as input and output buffer circuits are used to amplify and/or condition signals for detection or transmission. In the case of an input buffer in a telecommunication system, the circuit receives an input signal that has typically undergone degradation and attenuation as it propagated through a transmission link. The function of the input buffer is therefore to amplify and recondition the received signal, and in some cases to provide frequency equalization, so that the receiver circuitry can properly resolve the incoming bits. In the case of an output buffer, the circuit is typically required to drive an output signal at the appropriate levels for a given transmission link. In either case, any signal offset that may be caused by the buffer circuitry can contribute to operational error. For example, any offset in the first stage of a typical multi-stage limiting amplifier in the analog front-end of a receiver is amplified by subsequent stages. The amplified offset reduces the available timing margins needed to resolve incoming data bits. This causes an increase in the bit error rate (BER) of the receiver circuit. The amount of overall voltage offset grows proportionally to square root of sum of squares of individual stage offsets, where summation is done for all stages, hence the number of cascaded buffer circuits in the signal path and the greater the amount of offset, the greater the potential increase in BER. This is further exacerbated as integrated circuits shrink in size and operate at reduced voltage margins. In the case of output buffers, offsets cause undesirable duty cycle distortion for the output signal. Various offset cancellation techniques have therefore been developed to eliminate or reduce the adverse effects of offset signals.
Generally, offset cancellation schemes either provide for a one-time correction of signal offset usually upon power-up or initial configuration, or use an internal feedback loop to continuously monitor and correct for offset. Conventional one-time offset calibration techniques require addition circuitry to enable/disable offset cancellation and are only accurate at the time the device is calibrated. Furthermore, circuits using one-time offset calibration are typically affected by environmental variations such as changes in temperature after calibration which reduces their efficacy. Conventional dynamic offset cancellation circuits with an internal feedback loop typically assume that input signals are DC-balanced, and require additional front-end circuitry specific to a particular analog or digital system to complete the feedback loop. They therefore tend to require more complex circuitry which also adds to loading conditions.
There is therefore a need for circuits and methods to reduce or eliminate signal offsets in order to improve integrated circuit operational performance.

Programmable logic enabled dynamic offset cancellation


The result of an analog to digital conversion is stored in a first storage unit, the contents of the first storage unit are transferred to a second storage unit, and the contents of these storage units are compared by an arithmetic unit to determine whether the result of the analog to digital conversion increases or decreases over time.

1. Field of the Invention
The present invention relates to a microcomputer comprising an A/D converter and capable of detecting whether the result of conversion by the A/D converter increases or decreases.
2. Description of the Prior Art
FIG. 7 is a schematic diagram of the configuration of a microcomputer comprising a conventional A/D converter. For simplification, a 2-bit A/D converter is shown here. In the figure, reference symbol 1A represents a CPU, 1B an A/D converter, 10 a low-order bit data line of the conversion result of the A/D converter 1B, 11 a high-order bit data line of the conversion result of the A/D converter, 13 a tri-state buffer, 14 a system bus and 15 a latch. As shown in FIG. 8, when T is at "H", data inputted from D is inputted into the latch 15 which keeps the data latched while T remains at "L" and outputs the inverted data of the data latched by Q to Q. Reference numeral 16 represents A/D conversion result storage means which consists of two units of the latch 15 for storing the above-mentioned low-order and high-order bit data, that is the conversion result of the A/D converter 1B, R3 a read signal which becomes active when it reads the contents of this A/D conversion result storage means for output to the system bus 14, and T5 a signal indicative of the completion of A/D conversion by the A/D converter 1B which is also active at "H".
The operation of the microcomputer will be explained hereafter. When the A/D conversion operation of the A/D converter 1B is completed, the A/D conversion complete signal T5 becomes active ("H"), and the result of A/D conversion is stored in the storage means 16 for storing the result of A/D conversion. The contents of the result can be read and outputted to the system bus 14 through the tri-state buffer 13 by the R3 signal.
Since the microcomputer comprising the conventional A/D converter is structured as described above, the microcomputer does not have means for detecting whether the result of A/D conversion increases or decreases with the passage of time. However, for its application, correction control (for instance, compensation for the influence of a superimposed direct current when the amount of an alternating current is sampled for digital conversion) is performed according to an increase or decrease in analog voltage. Furthermore, according to whether an absolute value of a change is abnormal or not, the step goes to an exception process (in the above case, supposing that the amount of the alternating current is a sine wave, data on the next input amount predicted from the current input amount and the previous input amount is compared with the actual next input amount. When there is a difference between them, it is determined that the amount of the alternating current is abnormal, and the step enters a program processing routine). These processes are controlled by software. If this processing of this important data obtained from the A/D converter is performed by a conventional A/D converter, a large overhead (longer processing time and a greater load on the CPU 1A) occurs on the processing of data such as data saving and arithmetic operation, thus making difficult high-speed and advanced control.

Microcomputer that detects whether the output of an analog to digital convertor is increasing or decreasing overtime


A rotary machine, which can be a turbine or a rotary compressor, is provided. The rotary machine includes a stationary housing and a rotating shaft supported in the housing by a magnetic bearing, whereby the magnetic bearing includes a laminated bearing journal with a shaft-mounted rotating lamination and a corresponding housing-mounted stationary lamination surrounding the rotating lamination, whereby both laminations extend axially to the shaft within a bearing portion, limited on one side by the end of the shaft. In addition, an axial duct extends axially through the shaft from the end to at least one substantially radial duct connecting the axial duct with an orifice in the shaft surface adjacent the other side of the bearing portion, and whereby a stationary tube is inserted in the axial duct supplying it with fluid. This arrangement provides sufficient cooling for a laminated bearing journal of the rotary machine.

A flywheel according to this constitution is disclosed in U.S. Pat. No. 5,398,571.
High-output rotary machines those mechanical components rotate at high revolution speeds—e.g. turbines or rotary compressors—are equipped with magnetic bearings to achieve less bearing friction and smooth running. For improvement of magnetic flux, bearing journals incorporated in magnetic bearings can be made up of a laminated construction. Heat induced in magnetic bearing has to be dissipated by appropriate cooling means to prevent lamination from thermal failure.
Aforesaid US-Patent does not provide any detailed information relating to means for cooling the rotating elements. Other solutions are not known.


An image processing device includes a background noise detecting device configured to detect from image data of an image, background noise data of the image data. An image memory stores the image data, and an inputting/outputting device inputs and outputs the image data into and from the image memory. A background noise data removing device removes the background noise data from the image data outputted from the image memory by the inputting/outputting device. An on/off device turns on and off a background noise data removing operation of the background noise data removing device according to an external control signal.

1. Field of the Invention
The present invention relates to the removal of background data from image data by an image processing device or image reading apparatus.
2. Discussion of the Background
In the field of image processing and image reading, it is often desirable to remove background noise from image data representing an image. The removal of background noise is an improvement in the quality of a duplicated image.
A disadvantage of a conventional image processing device or image reading apparatus, such as a digital copying machine, is that a background noise removing function cannot be switched on and off during a print job. This is disadvantageous, as in some documents, it is desirable for only portions of the document to have background noise removed. For example, it would be desirable in a document that included both text and pictures to remove any background noise below a certain threshold in the text portion, while not removing any of the background noise in the picture portion. The removal of background noise from duplicated text will insure that the text appears in its original form, while removal of background noise in a duplicated picture may cause deterioration of the quality of the duplicated picture. Accordingly, there is a long felt need for an image processing device or image reading apparatus that can selectively remove background noise.

Removal of background noise of image data by an image processing device or image reading apparatus


A insole pad (1; 51) for placement on top of an inner sole of footwear and adapted in use to cover only an area of that inner sole that is substantially smaller than the human footprint. The insole pad (1; 51) includes a relatively thin, sheet-like body that has an upper surface (33) and a lower surface (41) and an outer periphery (25). The lower surface (41) has sticky or adhesive properties, and is interrupted by recessed areas arranged in a pattern (5; 55). The pattern (5; 55) is configured to include a plurality of channels combined to be at least intersecting or joining, so as to define a plurality of differently sized non-recessed lower surface areas. At least a portion of the channels vary in width, while the pattern has a varying density to provide high and low cushioning values in predefined areas A, B, C; G).

The invention relates to an insole pad, such as a partial insole, for placement on top of an inner sole of footwear. The invention may however also be applied to full-length insoles. Partial insoles could include a ball of foot, or forefoot pads and a heel pads, but is not limited thereto. The partial insoles to which the invention relates are preferably smaller than the human footprint and are then used exclusively to cover only a portion of the inner soles of footwear.
Partial insoles, such as for supporting the ball of foot area of the human foot, are known. A way to provide cushioning properties to such pads is by providing them with protruding structures, such as ribs or columns to the bottom surface thereof. Usually these are arranged as geometric shapes that are distributed more or less uniformly over the area providing the cushioning properties. For cushioning energy during walking or running these uniformly arranged geometric structures are often allowed to buckle or collapse, as this was believed to improve the cushioning properties. However it is also important for partial insoles to have good adherence of the lower or bottom surface to the location of the inner sole of footwear, for which they are intended. Good adherence does benefit from possibly large adherence surfaces and adherence surfaces that show as little as possible deformation during use. In this regard the known structures have shown certain shortcomings, because the surface area available for adherence has been generally smaller that the surface area interrupted by the voids between the geometric structures. Overcoming these drawbacks by using stronger adhesives has introduced the problem of footwear damage when it was attempted to remove or replace the partial insoles at the end of their useful life.