A projection system includes a projection unit configured to project a projected image on a surface for projection; an image capturing unit configured to capture an image of an image-capturing area representing an area; an operation detection unit configured to detect any user operation on an operation target image representing a targeted image for the user operation by using the captured image; a calculation unit configured to calculate image-capturing area coordinates for specifying a position of the image-capturing area in the projected image based on the captured image and the projected image; a position determination unit configured to determine a position of the operation target image in the projected image based on the image-capturing area coordinates; and a projected image generating unit configured to generate a projected image in which the operation target image is laid out on the determined position.

1. Field of the Invention
The present invention relates to a projection system, an image generating method, and a computer-readable storage medium.
2. Description of the Related Art
Conventional technologies for operating projection devices have been known, in which a pointing position is moved using a pointing device such as an electronic pen on a projected image projected on the surface for projection such as a screen by projection devices such as a projector. By contrast, with some technologies, projection devices can be operated without using a pointing device. For example, a technology has been known, in which a predetermined action of a user, i.e., a gesture is recognized by a camera and the operation corresponding to the gesture is executed on the projection device. With another technology, if a user performs an action for operating a target for operation such as a button included in the projected image, the action is recognized by a camera and the process corresponding to the operation on the target for operation is executed on the projection device. These technologies are assumed to be used for a presentation in a meeting or a display of content information to a user in a shop.
With the technologies, it is preferable that the current pointing position can be detected with high accuracy based on operations on projection devices operated according to the pointing positions in projected images. Examples of technologies for detecting pointing positions with high accuracy include the following: a predetermined position on the surface for projection is marked, the marked image is stored, then the marked image and the current projected image are compared to each other for detecting the pointing position. With this technology, the current pointing position can be detected without always displaying the marker.
In the conventional technologies, however, some user operations on projection devices cannot be detected. Specifically, if a projection device is operated by recognizing a user action by a camera and if an image-capturing area in which the camera can capture images is smaller than the projected image, some operations on the projection device cannot be detected. The image-capturing area is smaller than the projected image when the surface for projection and the camera are close to each other, that is, the distance between the surface for projection and the camera is too short. That is, when using a projection device for the purpose of presentation or display of content information and if no sufficient distance between the surface for projection and the camera can be ensured, the above-described issue may occur.
Therefore, there is a need to provide a projection system, an image generating method, and a computer-readable storage medium that can improve detection accuracy of a user operation on a projection device.

Projection system, image generating method, and computer-readable storage medium


There are provided an electronic component production method and an electronic component by which the number of scribing processes can be reduced and the productivity can be made higher while surely preventing short circuiting during the production. An electronic component including a short ring residue portion and a method of producing the electronic component are provided.

1. Field of the Invention
The present invention relates to an electronic component including an electronic element disposed on a base member (e.g., substrate) and a take-out electrode connected to the electronic element, and a method of producing the same.
2. Related Background Art
An electronic component including an electronic element and a take-out electrode is disclosed in Japanese Patent Application Laid-Open No. H07-181516 (JP 07-181516A).
JP 07-181516A relates to a thin film transistor panel and describes transistors, gate lines connected to the transistors, and terminals thereof. The gate lines are connected to a conductive portion which is provided along side surfaces of a base member and then separated from the conductive portion by scribing. The thin film transistor panel is disposed on a large-size base member and respective liquid crystal display elements are obtained by scribing.
JP 07-181516A describes that the respective liquid crystal display elements are separated from the large-size base member. However, when small-size base members are to be obtained from the large-size base member, it is necessary to perform scribing at least ten times. Here, of the ten-time scribing, eight-time scribing must be accompanied by troublesome handling of the small-size base members. The present inventors have paid attention to such complication.
That is, when four regions "A" are obtained from the large-size base member such as shown in FIG. 2 of JP 07-181516A, firstly two-time scribing is performed for dividing the large-size base member into the respective regions. Because the conductive portion which is provided along the side surfaces of the large-size base member is connected to the gate lines, the conductive portion can be said to be a short ring. Therefore, when the short ring is cut before the first two-time scribing, prevention of a short circuiting cannot be ensured in subsequent steps. In other words, such cutting should not be performed.
Each of four components separated from one another through the first two-time scribing still has a conductive portion.
Because the conductive portion is provided on two sides of each of small-size base members of the four components, it is necessary to perform scribing for removing the conductive portion two times for each component.
The scribing for removing the conductive portion is performed after the large-size base member is divided into small-size base members.
Such scribing is performed for each of the four components, so that the total number of scribing processes is eight (2×4=8).
Therefore, it is necessary to perform scribing ten times in total (2+2×4=10). Further, of the ten-time scribing, eight-time scribing needs to be performed for each base member which has been subjected to the division to become the small piece. However, the handling of the small-size base members is complicated. Thus, the present inventors have considered that there is a room for improving the productivity.

Method of producing electronic component comprising electrodes and ring residues


A semiconductor package includes a substrate, a first passivation layer disposed on the substrate, and an under bump metallurgy layer disposed on the first passivation layer. An additional under bump metallurgy layer is disposed on the first passivation layer, isolated from the under bump metallurgy layer; and a conductive pillar disposed on the additional under bump metallurgy layer.

Field of the Invention
The present invention relates to a semiconductor package, and in particular, to a passive device of semiconductor package.
Description of the Related Art
For the conventional flip chip package, one criterion of inductors is low resistance, so that a high quality factor (Q factor) can be achieved. The quality factor (Q factor) of an inductor is the ratio of its inductive reactance to its resistance at a given frequency, and is a measure of its efficiency. The higher the Q factor of the inductor, the closer it approaches the behavior of an ideal, lossless, inductor.
The conventional flip chip package fabrication process usually uses additional metal layers of an interconnection structure of a chip to improve the quality factor (Q factor). However, the additional metal layers will increase fabrication costs and negatively affect fabrication throughput.
Thus, a novel inductor with an increased Q factor is desirable.


The present invention provides compounds useful as inhibitors of ATP citrate lyase (ACLY), compositions thereof, and methods of using the same.

ATP citrate lyase (ACLY) is a homotetrameric enzyme that catalyzes the ATP dependent cleavage of citrate into acetyl coenzyme A (acetyl-CoA) and oxaloacetate (OAA). Acetyl-CoA is an important cellular metabolite and second messenger, thus ACLY enzymatic activity is positioned at the nexus of intermediary metabolism. The acetyl-CoA forming reaction is initiated upon phosphorylation of ACLY at histidine 760, which then catalyzes the formation of citryl phosphate followed by the formation of a citryl-CoA intermediate after a CoA attack. Finally, the citryl-CoA intermediate is cleaved, and acetyl-CoA and OAA are released. ACLY derived acetyl-CoA serves as the carbon source for the production of cholesterol in the mevalonate pathway and fatty acids (FA) in the de novo lipogenesis (DNL) pathway, and is also required for protein acetylation, thus linking cellular metabolism with the epigenome and gene regulation. Acetyl-CoA production therefore functions as a key metabolic checkpoint used by cells to coordinate cellular metabolism in response to nutrients and plays a key role in sterol and lipid production in a number of tissues. Thus, direct inhibition of ACLY activity may have important therapeutic implications for treating a wide range of diseases including hypercholesteremia and cardiovascular disease (CVD), obesity, diabetes, insulin resistance, fatty liver disease, metabolic syndrome and cancer.


A strong lightweight composition containing inorganic coated microparticles which, when dispersed in a binder, produce a matrix having broad band absorption properties for electromagnetic radiation in the infrared and microwave regions and is useful as a thin coating or as a structural composite material in various applications for multispectral absorbers. The microparticles have a mean diameter of from 1 to 500 microns and are coated with the reaction product of a metal and a nonmetal.

The above-noted commonly owned and co-pending U.S. Pat. Nos. 4,624,798 and 4,624,865 disclose novel electrically conductive microparticles in the form of metal coated magnetic ceramic microspheres, methods for producing these microspheres, and also describe their usefulness in forming electrically conductive coatings or composites for various applications. We have now discovered novel infrared absorbing compositions consisting of microparticles coated with certain inorganic materials.
Various materials, such as carbon black and other dark pigments, have been used in the past to absorb infrared radiation. While various pigments used in the past absorb a portion at the infrared region, they become highly reflective in other portions of the infrared. These compositions all suffer the disadvantage that the binder used to hold the pigment is reflective in the infrared region and detracts from the effectiveness of the absorber particle. These systems utilize a dispersion of the absorber particles such that the energy must penetrate some distance into the binder to reach the particles. A further disadvantage of this approach is the difficulty of simultaneously obtaining the critical dispersion distance for the particles and the strict requirements for the particle size. Prior technology utilizing such pigments is unable to obtain uniform and strong absorption over the 0.5 to 25 micron bandwidth. Coatings utilizing the prior art could not be integrated into ultrawide band electromagnetic absorbers due to the inherent high dielectric constant of the pigments which cause high reflectivity of the coatings in the microwave region of the electromagnetic spectrum.
The present invention provides a strong, light-weight composition containing coated microparticles. The composition has very broad band absorption properties for electromagnetic radiation in the infrared region and is effective when used as a thin coating or as a structural composite material. It can withstand very high temperatures (900 degrees C.) and is generally limited only by the binder in this respect. In contrast to the prior art, these coated particles require much less of the reflective binder to achieve good physical properties and the size of the coated particles is such that the particles extend above the binder surface exposing the absorber to the incident radiation with little interference by the binder. The composition has the advantage of being transparent in the microwave region and may readily be used in conjunction with other absorbers to obtain an absorber which is effective in both the microwave and infrared regions. It has the added advantage of absorbing sound and is a good thermal insulator displaying decreased emissions when placed over substrates radiating in the far infrared. It may be easily applied to a substrate with conventional spray equipment.

Electromagnetic radiation absorptive composition containing inorganic coated microparticles


A printer has a controller unit and an engine unit, which are connected via a video interface. Upon reception of a designating command for designating a type of condition, whose condition change is to be reported, from the controller unit, the engine unit supplies a designated condition change signal to the controller unit immediately after the condition of the designated type has changed. The controller unit requests the engine unit to output detailed data associated with the status change in response to reception of the designated condition change signal.

1. Field of the Invention
The present invention relates to an image forming apparatus, which connects an image processing means for generating pixel data and an image forming means for forming an image on a recording medium via a communication means, and a method used therefor.
2. Related Background Art
An image forming apparatus, which is constituted by a video controller for converting code data described in a printer command system such as a page description language into pixel data, and a printer engine for forming an image on the basis of the pixel data supplied from the video controller and transferring and fixing the formed image on, e.g., a recording paper sheet, is known.
A video interface connecting the video controller and the printer engine will be described below. FIG. 11 is an explanatory view showing a list of signals of the video interface. In FIG. 11, "output" represents an output from an engine controller in the printer engine to the video controller, and "input" represents an input from the video controller to the engine controller.
A signal /BD is a horizontal synchronization signal, in the main scanning direction, of the printer engine. The video controller outputs video data /VDO for one main scanning line in synchronism with the trailing edge of the signal /BD. A signal /PPRDY indicates that a power supply is connected to the printer engine, initialization of the engine controller is completed, and it is ready to communicate command status signals between the engine controller and the video controller.
A signal /RDY indicates that the printer engine is ready to perform a print operation in response to a print start command (signal /PRNT is true). The signal /RDY changes to true under conditions that the temperature of a heating roller in a fixing unit is proper (i.e., a sufficiently high temperature for fixing a toner image on a paper sheet), a recording paper sheet has not jammed, a polygonal mirror is normally rotated at a prescribed rotational speed, the signal /BD is normally output at a prescribed period, and so on.
A signal /TOP is a print synchronization signal, in the sub-scanning direction, in the printer engine. The video controller sets the image write start position in the sub-scanning direction in synchronism with the trailing edge of the signal /TOP. The position of a paper feed sensor is determined so that the time required from when the leading end of a recording paper sheet is detected by the paper feed sensor until the recording paper sheet reaches a transfer roller equals the time required until a latent image formed on a photosensitive body by a laser beam reaches the transfer roller upon rotation of the photosensitive drum. For this reason, when the engine controller detects that a paper feed sensor signal (PFSNS) from the paper feed sensor changes to true, it immediately sets the signal /TOP to be true for one sec.
A signal /SBSY is a level signal which indicates that the printer engine is transmitting a status signal (the condition of the printer) to the video controller using a signal line /SC. At this time, as the signal /SC, serial information in units of 8 bits is transmitted to the engine controller, and this signal is called a status signal.
A signal /PPOUT notifies the video controller of the fact that a recording paper sheet on which the print operation has been completed is ejected.
A signal /CBSY is a signal which indicates that the video controller is transmitting a command (a command for the engine controller) using the signal line /SC. At this time, as the signal /SC, serial information in units of 8 bits is transmitted from the video controller to the engine controller. A signal /SCLK is a synchronization clock used upon serial transmission of the signal /SC (status and command).
A signal /PRNT is a signal with which the video controller instructs the printer engine to start the print operation. In a continuous print mode, this signal means continuation of the print operation.
A signal /CRPDY indicates that a power supply voltage is supplied to the video controller, the initialization of the video controller is completed, and the video controller is ready to communicate commands and status signals with the printer controller.
A signal /VDO is an image signal to be printed by the printer engine. This image signal is output by converting image code data received by the video controller from a host computer into dot data.
The formats of commands sent from the video controller to the engine controller and the status signals sent from the engine controller to the video controller exchanged via serial communications will be explained below.
As described above, command information and status information are 8-bit serial signals. When 1-byte command information is supplied from the video controller to the engine controller in synchronism with the signal /SCLK, the engine controller sends back 1-byte status information to the video controller. This command information includes two commands, i.e., a status request command for checking the status of the printer engine, and an execution command for instructing the printer to perform some operation.
Each of the command information and status information has the eighth bit as a parity bit, and an odd parity is added upon transmission. The status information sent back by the engine controller has the first bit as a command error bit. That is, when a command supplied from the video controller is not predetermined data, or a parity error has occurred, the engine controller sets "1" in the first bit of status information, and sends back the status information.
FIG. 12 is an explanatory view showing an example of status information when no command error has occurred, i.e., the first bit is "0". FIG. 13 is an explanatory view showing status information when an error has occurred. When an error has occurred, "1" is set in the first bit, and the type of the error is specified by the second to seventh bits.
Basic status information when no error has occurred is sent back when the video controller sends "01" as a status request command, and six different types of status information except for the command error bit (first bit) and the parity bit (eighth bit) are included in this information.
More specifically, when "1" is set in the second bit, it indicates that the printer engine is ready to receive a signal PRNT. When "1" is set in the third bit, it indicates that the printer engine is transporting a recording paper sheet. When "1" is set in the fourth bit, it indicates that a recording paper sheet jam or a print error has occurred in the printer engine, and print data must be re-transmitted to the engine controller.
When "1" is set in the fifth bit, it indicates that the printer engine is waiting since the temperature of the heating roller in the fixing unit has not reached an appropriate temperature. When "1" is set in the sixth bit, it indicates that the printer engine is pausing due to a pause command from the video controller.
When "1" is set in the seventh bit, it indicates that the printer engine has failed and must be corrected by calling a service person or operator.
In addition, the engine controller has status signals for reporting, to the video controller, a recording paper sheet jam, the absence of paper sheets, the open state of the front door, a fixing failure, a motor failure and the like in response to the command from the video controller.
However, in such apparatus, since the video controller supervises the conditions of the printer engine using serial communications, the following problem is posed.
That is, even when the condition of the printer engine remains the same, the video controller must perform serial communications to supervise a plurality of status bits, and the communication processing exerts a heavy load on the video controller.

Image forming apparatus and method which transmits information on internal conditions to an image processor


Toric contact lenses are provided with markings that enable identification of the offset between the cylindrical axis of the toric zone and the ballast axis. Surfaces of the lenses include two markings, a first identifiable marking that is aligned with the cylindrical axis, and a second identifiable marking that is aligned with the ballast axis.

This invention relates to markings for toric contact lenses. The markings are useful for identifying the offset between the cylindrical axis and the ballast axis.
Contact lenses having a toric optical zone (commonly referred to as xe2x80x9ctoric contact lensesxe2x80x9d) are used to correct refractive abnormalities of the eye associated with astigmatism. The toric optical zone provides cylindrical correction to compensate for the astigmatism. Since astigmatism requiring vision correction is usually associated with other refractive abnormalities, such as myopia (nearsightedness) or hypermetropia (farsightedness), toric contact lenses are generally prescribed also with a spherical correction to correct myopic astigmatism or hypermetropic astigmatism. The toric surface may be formed in either the posterior lens surface (back surface toric lens) or in the anterior lens surface (front surface toric lens).
Whereas spherical contact lenses may freely rotate on the eye, toric contact lenses have a ballast to inhibit rotation of the lens on the eye so that the cylindrical axis of the toric zone remains generally aligned with the axis of the astigmatism. For example, a section of the lens periphery may be thicker (or thinner) than another section to provide the ballast. Toric contact lenses are manufactured with a selected relationship (or offset) between the cylindrical axis of the toric optical zone and the orientation of the ballast. This relationship is expressed as the number of degrees (rotational angle) that the cylindrical axis is offset from the orientation axis of the ballast. Accordingly, toric contact lens prescriptions specify this offset, with toric lenses generally being offered in 5 or 10-degree increments ranging from 0xc2x0 to 180xc2x0.
U.S. Pat. No. 4,976,533 discloses various prior methods for marking a toric contact lens, the markings being arranged in a manner that the ballast axis is identifiable. As an example, FIG. 2 of U.S. Pat. No. 4,976,533 illustrates a prior art toric contact lens including three visible line segments in a peripheral section of the lens, a first line segment lying on the ballast axis and two line segments arranged symmetrically about the first. As another example, FIGS. 3 and 5 of U.S. Pat. No. 4,976,533 disclose one or two line segments lying perpendicular to the ballast axis. Such lenses are useful for measuring the rotation of the lens on the eye, i.e., a practitioner can evaluate the lens when placed on the eye, and use the markings to measure any deviation of the lens from its intended rotational position, and to evaluate whether rotation of the lens on the eye is effectively inhibited as intended.
The invention relates to markings for toric contact lenses that include a posterior surface and an anterior surface, one of the surfaces including a toric optical zone having a cylindrical axis, and the surfaces being shaped to form a ballast oriented about a ballast axis. The lens surfaces include two markings, a first identifiable marking that is aligned with the cylindrical axis, and a second identifiable marking that is aligned with the ballast axis. The two markings provide a simple and reliable means to identify the offset between the cylindrical axis of the toric optical zone and the ballast axis.
The invention also provides a method for marking a toric contact lens with identifiable markings, that comprises applying a first identifiable marking to a surface of the contact lens that is aligned with the cylindrical axis, and applying a second identifiable marking to a surface of the contact lens that is aligned with the ballast axis.


In an embodiment, a switching circuit is provided that includes a Group III nitride-based semiconductor body including a first monolithically integrated Group III nitride-based transistor device and a second monolithically integrated Group III nitride based transistor device that are coupled to form a half-bridge circuit and are arranged on a common foreign substrate having a common doping level. The switching circuit is configured to operate the half-bridge circuit at a voltage of at least 300 V.

To date, transistors used in power electronic applications have typically been fabricated with silicon (Si) semiconductor materials. Common transistor devices for power applications include Si CoolMOS®, Si Power MOSFETs, and Si Insulated Gate Bipolar Transistors (IGBTs). Group III nitride-based semiconductor devices, such as gallium nitride (GaN) devices, are now emerging as attractive candidates to carry large currents, support high voltages and to provide very low on-resistance and fast switching times.
Two or more Group III nitride-based semiconductor devices may be formed in a Group III nitride-based body. US 2017/0154885 A1 discloses a nitride semiconductor layer on a conductive substrate including two lateral transistor devices. The substrate includes isolation regions in the form of trenches in the substrate such that each device is positioned above a region of the substrate whose potential can be independently controlled. An isolation structure is also provided inside the nitride semiconductor layer to electrically isolate the transistor devices from each other.
Devices with two or more monolithically integrated Group III nitride-based devices that have improved operational reliability are, however, desirable.

Switching circuit, gate driver and method of operating a transistor device


A disposable nonwoven cleansing mitt adapted to be retained on a user's hand during use is provided. The disposable nonwoven cleansing mitt is releasably carrying a personal care composition.

Personal care products, particularly cleansing and conditioning products, have traditionally been marketed in a variety of forms such as bar soaps, creams, lotions, and gels. Typically, these products must satisfy a number of criteria to be acceptable to consumers. These criteria include cleansing effectiveness, skin feel, mildness to skin, hair, and ocular mucosae, and lather volume. Ideal personal cleansers should gently cleanse the skin or hair, cause little or no irritation, and should not leave the skin or hair overly dry after frequent use. Further, cleansing compositions, particularly shampoos, designed for use with children should exhibit mildness to the ocular mucosae, and no or minimal eye sting, should material from the cleansing composition be placed in the eye.
It is highly desirable to deliver cleansing and conditioning benefits from a disposable substrate. Disposable products are convenient because they obviate the need to carry or store cumbersome bottles, bars, jars, tubes, and other forms of clutter associated with cleansing products and other products capable of providing therapeutic or aesthetic benefits. Disposable products are also a more sanitary alternative to the use of a sponge, washcloth, or other cleansing implement intended for extensive reuse, because such implements can develop bacterial growth, unpleasant odors, and other undesirable characteristics related to repeated use.
However, while disposable personal care articles, such as disposable washcloths or disposable mitts, which can be easily used by young children, are desirable they have their own problems. Retention on the hand of a user of such disposable mitts, especially during vigorous scrubbing, is one such problem. If the mitt is prone to fall off during use the user is more concerned with retaining the cleansing mitt on their hand instead of actually using the mitt to wash themselves.
The need remains for disposable cleaning products which are easy to use and suitable for use by consumers of ages, children, sizes and/or stages of development, especially products which are suitable children of different ages. Furthermore, the need remains for a wash mitt which is retained on a user's hand such that the consumer can focus on the task at hand, namely washing and cleaning, without having to be concerned with retaining the wash mitt on their hand.


When performing an inspection using a charge control function in a SEM wafer inspection apparatus, acceleration voltage, control voltage and deceleration voltage are changed in conjunction so that incident energy determined by “acceleration voltage−deceleration voltage” and bias voltage determined by “deceleration voltage−control voltage” do not change. By this means, charge of a wafer can be controlled, while restraining electrostatic lens effect generated near a control electrode. As a result, an inspection using a charge control function at low incident energy and in a wide viewing field can be performed, and a highly sensitive inspection of semiconductor patterns subject to damages due to electron beam irradiation can be realized. Acceleration voltage, control voltage and deceleration voltage are changed in conjunction so that incident energy determined by “acceleration voltage−deceleration voltage” and bias voltage determined by “deceleration voltage−control voltage” do not change.

In the manufacturing processes of semiconductor devices, the quality of processes including lithography process, etching process, ion implantation process and the like has great influences upon the yield of the semiconductor devices. Therefore, it is important to detect occurrences of defects and the types thereof at an early stage and feed them back to manufacturing conditions, thereby improving the yield.
In order to inspect circuit patterns formed on a semiconductor wafer in the course of their manufacture, an inspection apparatus in which a scanning electron microscopy is applied (hereinafter, referred to as SEM wafer inspection apparatus) has been employed. The objects to be inspected by this inspection apparatus range widely such as conduction/non-conduction defects, attachment of foreign matters, shape defects of patterns and others.
The SEM wafer inspection apparatus extracts conduction/non-conduction defects by the use of voltage contrasts generated by charging a wafer surface positively or negatively. Herein, the inspection for non-opening defects where a remaining film of an insulator exists at the bottom of a contact hole is taken as an example of the inspection using the voltage contrasts. In the non-opening portion, the remaining film at the bottom of a hole is charged when electron beam is irradiated, and accordingly, a field distribution different from that in the opening portion is formed on the pattern surface. As a result, the number of secondary electrons detected in the opening portion differs from that in the non-opening portion, and these differences are observed as contrasts in an image. In other words, only the defective portions can be detected by comparing the brightness of the contact holes.
In the inspection using the voltage contrasts, it is extremely important to control the charge of the wafer surface. As the method for charging the wafer surface, there are the method using the secondary electron emission efficiency and the method using a control electrode disposed just above a wafer.
In the method using the secondary electron emission efficiency, the polarities of charge are determined by the energy of electrons that enter the wafer and the material of an inspection object. That is, when the secondary electron emission efficiency is 1 or higher, the wafer is charged into a positive polarity, and when it is 1 or lower, the wafer is charged into a negative polarity. In this method, since the charge of the wafer continues until the secondary electron emission efficiency becomes nearly 1, in order to control the charge potential, the incident energy has to be adjusted by the material of patterns.
The method using a control electrode will be described with reference to FIG. 2. In both FIG. 2A and FIG. 2B, only minimum required structural components for describing this method are shown. Acceleration voltage (Va) is applied to an electron source 1, deceleration voltage (Vr) is applied to a wafer 2, and control voltage (Vc) is applied to a control electrode 3, respectively. The electron beam emitted from the electron source 1 is accelerated to the acceleration voltage (Va) and enters the wafer 2 at the energy equivalent to "acceleration voltage (Va)−deceleration voltage (Vr)". It is assumed here that the energy with which the electron beam enters the wafer 2 at this moment is under the condition that the secondary electron emission efficiency is 1 or higher. The charge of the surface of the wafer 2 is determined by "bias voltage=deceleration voltage (Vr)−control voltage (Vc)", and FIG. 2A shows the case where the surface of the wafer 2 is charged positively and the condition of the bias voltage>0 and FIG. 2B shows the case where the surface of the wafer 2 is charged negatively and the condition of the bias voltage<0. In the case of FIG. 2A, since the secondary electron emission efficiency is 1 or higher just after the electron beam is irradiated to the wafer 2, the surface of the wafer 2 is charged positively. Then, when the bias voltage and the charge of the surface of the wafer 2 become nearly equal to each other, the number of secondary electrons 33 passing through the control electrode 3 and the number of primary electrons 41 that enter the wafer 2 become nearly equal to each other, and the charge of the surface of the wafer 2 becomes stable. In the case of FIG. 2B, just after the electron beam is irradiated to the wafer 2, many of the secondary electrons 33 emitted from the wafer 2 are returned to the wafer 2 due to the influence of the bias voltage, and the surface of the wafer 2 is charged negatively. Then, when the bias voltage and the charge of the surface of the wafer 2 become nearly equal to each other, the number of secondary electrons 33 passing through the control electrode 3 and the number of primary electrons 41 that enter the wafer 2 become nearly equal to each other, and the charge of the surface of the wafer 2 becomes stable. The advantage of this method lies in that the charge of the wafer surface can be controlled by the bias voltage if the incident energy of the electron beam is under the condition of the secondary electron emission efficiency>1. More specifically, it is possible to control the charge of almost all insulators by an arbitrary incident energy of several 100 to 1000 eV (refer to, for example, Japanese Patent Application Laid-Open Publication No. 11-121561 (Patent Document 1)).

Inspection apparatus and inspection method


The battery assembly system 100 includes a battery assembly including a plurality of storage batteries C1 to Cn connected in series, a voltage detector 3 for detecting respectively voltages generated in the storage batteries, a current detector 4 for detecting a current flowing in the plurality of storage batteries, a state-of-charge (SOC) calculator 2 for calculating the state of charge (SOC) of the storage batteries, respectively, based on the voltages detected respectively by the voltage detectors 3 and the current detected by the current detector 4, and a charging/discharging unit 1 for charging or discharging at least one of the plurality of storage batteries so as to equalize the SOC of the storage batteries calculated respectively by the SOC calculator 2.

1. Field of the Invention
The present invention relates to a battery assembly system for reducing the variations of the state of charge (SOC) of a plurality of storage batteries connected in series and an electric-motor vehicle system using this battery assembly system.
2. Description of the Prior Art
In order to make an effective use of the capacity of a plurality of storage batteries connected in series, a technology for reducing the variations of SOC of the plurality of storage batteries based on a terminal voltage of each of the storage batteries is known. In a conventional technology, a discharging circuit is provided to an individual storage battery one by one, and the storage battery having a high SOC is discharged by the discharging circuit and the SOC thereof is reduced and adjusted to the SOC of the storage battery having a low SOC. Thus, the variations of the SOC are reduced.
For example, JP 61 (1986)-206179A discloses a technology of providing an individual battery with a Zener diode for bypassing a charging current when a terminal voltage of a storage battery reaches a charging termination voltage. JP 08 (1996)-213055A discloses a technology of supplying a current into a by-pass circuit when a terminal voltage of an individual storage battery exceeds the upper-limit voltage. JP 10 (1998)-322925A discloses a technology including detecting the variations of the SOC of a plurality of storage batteries by statistically processing an open circuit voltage of an individual storage battery and reducing the SOC of the storage battery with high SOC by discharging the storage battery with high SOC by the use of a discharging circuit provided to each individual storage battery so as to be adjusted to the SOC of the storage battery with low SOC. Furthermore, conventional technologies judge whether or not an abnormality is present based on the variations of the terminal voltages of the plural of storage batteries.
FIG. 8 is a block diagram showing a configuration of a conventional electric-motor vehicle system 80. The electric-motor vehicle system 80 is a general hybrid electric vehicle. The electric-motor vehicle system 80 is provided with an engine 81. The engine 81 generates power by using gasoline as fuel. The power generated by the engine 81 is transmitted to a motor 92 via a transmission 14 and further transmitted to wheels 15 via a differential gear 16.
To the motor 92, a battery assembly system 90 is connected via an inverter 93. The battery assembly system 90 supplies a discharged electric power to the motor 92 via the inverter 93 in order to assist the power transmitted from the engine 81 to the motor 92 via the transmission 14 at the time of acceleration. The battery assembly system 90 receives the electric power which the motor 92 generates while generating a braking power via the inverter 93 and is charged with the received power at the time of deceleration.
The electric-motor vehicle system 80 is provided with a control ECU 85. The control ECU 85 brings the engine 81 into operation with an optimum fuel efficiency based on a vehicle information such as information about a degree of opening of an accelerator, and the like, information obtained from the engine 81, and information obtained from the battery assembly system 90, and at the same time controls the engine 81 and the inverter 93 in order to prevent the overcharge, overdischarge and overload of the storage battery provided in the battery assembly system 90.
The battery assembly system 90 judges whether the electric-motor vehicle system 80 is running or parking or stopping based on a signal from a control ECU 85. When the electric-motor vehicle system 80 is running, the control ECU 85 controls the engine 81, inverter 93 and motor 92 so that the SOC of storage batteries provided in the battery assembly system 90 is in the range from about 20% to about 80% based on the information from the battery assembly system 90. This is carried out in order to protect the storage batteries provided in the battery assembly system 90 from being overcharged and overdischarged.
FIG. 9 is a block diagram showing a configuration of the battery assembly system 90 provided to a conventional electric-motor vehicle system 80. The battery assembly system 90 is provided with a battery assembly. The battery assembly includes n storage batteries C1, C2, . . . Cn−1 and Cn connected in series (n is an integer of 2 or more). Each of the storage batteries C1, C2, . . . Cn−1 and Cn is formed of lithium (Li) ion secondary battery and its standard capacity is 10 Ah.
The battery assembly system 90 is provided with a resistance discharger 91. The resistance discharger 91 has 7 ohms (Ω) discharging resistance R1, R2, . . . Rn−1, and Rn provided to each of the individual storage batteries C1, C2, . . . Cn−1 and Cn.
The battery assembly system 90 is provided with a voltage detector 82. The voltage detector 82 detects terminal voltages of the storage batteries C1, C2, . . . Cn−1 and Cn, respectively.
The battery assembly system 90 is provided with a multiplexer 95. The multiplexer 95 connects any one terminal of n storage batteries C1, C2, . . . Cn−1 and Cn to the voltage detector 82 in accordance with a switching signal from a battery ECU 86.
The battery assembly system 90 is provided with a current detector 4. The current detector 4 measures voltages at both ends of the resistor SH1 connected in series to n storage batteries in order to detect a current flowing in the storage batteries.
The battery assembly system 90 is provided with a temperature detector 9. The temperature detector 9 detects a temperature of the storage battery by the use of a temperature sensor.
In the thus configured battery assembly system 90, the battery ECU 86 judges whether or not the electric-motor vehicle system 80 is running based on the information from the control ECU 85. When the battery ECU 86 judges that the electric-motor vehicle system 80 is not running, the battery ECU 86 makes the battery assembly system 90 in a dormant state. This is carried out in order to minimize electric power consumption of the battery assembly system 90 by not supplying the battery assembly system 90 with the electric power from the outside when the electric-motor vehicle system 80 is not running.
When the battery ECU 86 judges that the electric-motor vehicle system 80 is running, the ECU 86 switches the multiplexer 95 at high speed of several miliseconds/channel (CH) or less so that the voltage detector 82 detects the terminal voltages of the storage batteries C1, C2, . . . Cn−1 and Cn, respectively. Since the terminal voltage of the storage battery is susceptible to the load fluctuation, the detection of the terminal voltages of the storage batteries C1, C2, . . . Cn−1 and Cn should be finished while the load fluctuation is small, or while the electric-motor vehicle system 80 is stopping. Then, the temperature detector 9 detects temperatures of the storage battery at an appropriate period.
Next, the battery ECU 86 outputs charging request, discharging request, charging permission, or discharging permission to the control ECU 85 based on the terminal voltage of each of the storage batteries C1, C2, . . . Cn−1 and Cn detected by the voltage detector 82. The discharging permission is limited by a storage battery having the lowest terminal voltage, that is, a storage battery having the lowest SOC. The charging permission is limited by a storage battery having the highest terminal voltage, that is, a storage battery having the highest SOC. The battery ECU 86 is operated by a driving electric power supplied from each of the storage batteries C1, C2, . . . Cn−1 and Cn.
FIG. 10 is a graph to illustrate the relationship between the variations of the SOC and the range of usable SOC of each storage battery provided to the conventional battery assembly system 90. The abscissa shows the SOC of the storage battery; and the ordinate shows a terminal voltage of the storage battery. When the variations 17 of the individual storage batteries constituting the battery assembly are expanded to the variations 18, the interval 19 between the SOC in the state of the charging permission and the SOC in the state of the discharging permission is reduced to the interval 20. Therefore, the capacity of the battery assembly that can be used as the battery assembly system is reduced. That is, the region capable of charging/discharging storage battery is reduced.
The SOC shows 50%±20% normal distribution. In order to avoid the above-mentioned situation, the battery ECU 86 controls switches provided between resisters R1, R2, . . . and Rn and storage batteries C1, C2, . . . and Cn, respectively, and equalizes the terminal voltages of the storage batteries. Thus, the SOC of the storage battery can be equalized. As a result, the capacity that can be used as the battery assembly is restored.
Specifically, the battery ECU 86 appropriately turns the switches connected respectively to the resisters R1, R2, . . . and Rn ON based on the terminal voltages of each of the storage batteries C1, C2, . . . and Cn detected by the voltage detector 82. However, the switch connected to the storage battery having the minimum terminal voltage is not turned on.
Then, the detection of the terminal voltage of each storage battery continues. In order to stop the discharge of the storage battery whose terminal voltage is equal to the minimum terminal voltage, the switch connected to the storage battery is turned OFF. When the discharge is stopped, since the polarization by discharge is dissolved, the terminal voltage is increased. Then, the switch connected to the storage battery is turned ON again.
FIG. 11 is a graph showing a distribution of the SOC of storage batteries before being equalized by the resistance discharger 91 provided for the conventional battery assembly system 90. FIG. 12 is a graph showing the distribution of the SOC after being equalized. By repeating the above-mentioned operations, the terminal voltage of the storage batteries is converged from the voltage having the variations shown in FIG. 11 to the minimum terminal voltage shown in FIG. 12.
In this conventional technology, the discharge current is set to be about 1/50C. Even if the vehicle is operated for only about an hour a week, the discharge current of 1/50C is able to correct a shift in battery capacity that normally is seen in the course of one year. The equalization ability of this level is necessary from the conventional actual result in the market.
However, since the above-mentioned switching element provided to the resister discharging circuit for equalization requires the leakage current of several tens of micro amperes (μA) or less and the control current of about the level of several hundred milli amperes (mA), the switching element is expensive. Furthermore, it is also necessary to wire the switching element with the discharge resistor and the storage battery.
Furthermore, in the above-mentioned conventional configuration, since it is necessary to provide a discharging resistor for each storage battery, the configuration of the circuit of the assembly battery system becomes complicated, and the size is increased. Therefore, there is a problem that the cost of the battery assembly system is increased.
Furthermore, since the SOC is equalized by discharging the storage battery having high SOC so as to become the same SOC as that of the storage battery having the minimum SOC, it is necessary to discharge a large amount of electricity with respect to the battery assembly as a whole. Therefore, there is a problem that an energy loss is large.
Furthermore, in the method for bypassing the discharging current during charging, the period in which a discharger can be driven is limited, and it is necessary to provide a large size discharger capable of flowing the discharge current of 1/50 C or more. The capacity of the discharging storage battery is about 10 Ah and in this case, the discharging current becomes 0.5 amperes (A) or more. Therefore, there is a problem that the discharging current of the discharger becomes larger, and it is necessary to provide a large-size current element in order to turn a large current ON/OFF.
Furthermore, in the method of discharging the storage battery having high terminal voltage by connecting a resister, and opening the connection when the voltage is the same, it is necessary to repeat turning the discharge ON/OFF many times so that the SOC becomes the same. Therefore, there is a problem that it takes a long time to equalize the SOC.
Furthermore, in the conventional configuration, if the electric motor vehicle system parks for a long time, a part of the storage batteries self-discharge. As a result, there is a problem that if the other batteries are discharged so as to be adjusted to the storage battery that is largely self-discharged, the other batteries are subjected to deep discharge, making it difficult to equalize the SOC.
Furthermore, a deteriorated storage battery in the short-circuit mode may be one of the causes for expanding the variations of the SOC. When the deterioration of the storage battery advances, the variation of the SOC is expanded at higher speed than at the speed of the ability of the SOC equalization circuit. Although the method for detecting the deteriorated battery due to the variations of the terminal voltage of the storage battery has been proposed, the variations of the terminal voltage are reduced by such a current by-pass circuit and the deteriorated battery cannot be detected until the deterioration is quite advanced. Therefore, there is a problem that it is difficult to secure the battery assembly system.
It is an object of the present invention to provide a battery assembly system capable of equalizing the SOC of the battery assembly by a simple configuration and an electric motor vehicle system using the same.

This patent is subject to a terminal disclaimer.

Battery assembly system and electric-motor vehicle system using the same

Matsushita Electric Industrial Co., Ltd.


A thermodynamic cycle is disclosed that uses compression and expansion to generate refrigeration or power in which at least some of the compression is effected by hydrostatic head of the heat-exchange medium used in the cycle. In a refrigeration cycle, the head of a heat-exchange medium in the refrigeration cycle is used to compress the heat-exchange medium. A vaporous heat-exchange medium is introduced into the upper end of a down riser that extends downwardly through a heat sink. The vaporous heat-exchange medium descends through the down riser and the head of the heat-exchange medium compresses the heat-exchange medium. The heat generated by the compression is transferred to the heat sink. The heat-exchange medium is then pumped up through a return riser and passed through a pressure expansion means and evaporator. From the evaporator the heat-exchange medium is returned to the upper end of the down riser for recycling.

The invention relates generally to an improved thermodynamic cycle in which a heat-exchange medium goes through a cyclic process of compression, condensation, and expansion to produce power or to produce cooling. More specifically, the invention relates to an improved thermodynamic cycle that uses hydrostatic head to effect compression.
Thermodynamic power-producing cycles and refrigeration cycles use various cyclic combinations of compression, heat rejection, expansion, and heat addition. In these cycles, the cost of energy to effect compression is a significant part of the cycles"" capital cost as well as the cycles"" operating cost.
Common features of thermodynamic power-producing cycles include (1) a compression process wherein one or more compressors or pumps increase the pressure of a heat-exchange medium, (2) a thermal addition process in which energy is added to he heat-exchange medium from a suitable heat source such as air, water, or fossil fuel, 3) an expansion process during which work is done by the system on the surroundings, and (4) a rejection process in which thermal energy is transferred to the surroundings. In the process, thermal energy is converted into mechanical energy.
Refrigeration is used in the oil and gas industry to recover heavier hydrocarbons from produced fluids. This is desirable for various reasons, including hydrocarbon dewpoint conditioning and recovery of natural gas liquids (NGLs) that are more valuable as a liquid than as a gas. Refrigeration is also used in the production of liquefied natural gas (LNG). In the production of offshore oil and gas, the refrigeration is often on offshore structure where space is a premium. The refrigeration system typically requires equipment to compress, condense, and expand a heat-exchange medium to produce cooling. Having a compressor on an offshore structure takes up space and increases safety risks associated with having a mechanical apparatus using a pressurized heat-exchange medium which is often combustible. It would be desirable therefore to have a refrigeration system available for use in offshore operations without having a compressor on the surface facilities.
It would be beneficial from the standpoint of both initial and operating costs to eliminate the need for a conventional compressor in power-producing cycles and refrigeration cycles.
The present invention is direct to a thermodynamic cycle that uses compression and expansion to generate refrigeration or power in which a substantial portion of the compression is effected by hydrostatic head of the heat-exchange medium used in the cycle.
In one embodiment, a refrigeration cycle uses the head of a heat-exchange medium in the refrigeration cycle to compress the heat-exchange medium. Vaporous heat-exchange medium is introduced into the upper end of a down riser or conduit that extends downwardly through a suitable heat sink. The vaporous heat-exchange medium descends through the down riser and the head of the heat-exchange medium compresses the heat-exchange medium. The heat generated by the compression of the heat-exchange medium in the down riser is transferred to the heat sink, which surrounds the down riser. Preferably, the heat-exchange medium leaves the bottom of the down riser in a liquid phase. The heat-exchange medium liquid is then pumped up through a return riser and passed through a pressure expansion means and evaporator. From the evaporator the heat-exchange medium is returned to the upper end of the down riser for recycling.
In this embodiment of the present invention eliminates the need for the mechanical compressor of a conventional refrigeration system. Compression and heat rejection phases of this refrigeration system are simultaneously performed in a down riser. A heat-exchange medium pump is the only moving part of the refrigeration system. Compression of the heat-exchange medium is virtually isothermal at the temperature of the heat sink.
In another embodiment of this invention, a thermodynamic power cycle uses hydrostatic compression to condense a heat-exchange medium. In this embodiment, a heat-exchange medium is compressed by downward flow in a gravitational field from an initial elevation to a second, lower elevation. Examples of suitable systems for achieving the elevation difference can comprise a wellbore or a conduit extending between the top and bottom of a body of water. At the lower elevation, the heat-exchange medium is pumped back to the initial, upper elevation. The heat-exchange medium is then heated, thereby at least partially vaporizing the heat-exchange medium. The heated heat-exchange medium is then passed through an expansion device, preferably one or more hydraulic turbines, to expand the heat-exchange medium to a lower pressure whereby energy is produced. From the expansion device the heat-exchange medium is preferably cooled by a heat exchanger before being recycled.
The present invention can substantially reduce the cost of compressing the gas to a liquid compared to the cost of an adiabatic process performed by a conventional compressor. One advantage of this invention over power cycles used in the past is that gravity is used to carry out a substantial portion of the compression of the heat-exchange medium.

Thermodynamic cycle using hydrostatic head for compression


A method is provided for cleaning paint residue from the walls of an enclosed chamber and providing for reclamation of the cleaning solution. The method includes providing a regulated flow of cleaning solution under pressure to a hand held scrubbing apparatus for removing paint residue from the wall surface. The cleaning solution with the paint residue entrained therein drips down the walls and is collected in a series of troughs lining the perimeter of the paint booth. Taking advantage of gravity, the liquid drains from the troughs into a temporary storage container located below the paint booth. The liquid may then be pumped into a permanent storage container that could be in a remote location. The liquid is now available for reclamation.

1. Field of the Invention
The present invention relates to a method for cleaning paint residue from the walls of an enclosed chamber and providing for reclamation of the cleaning solution.
2. Description of The Related Art
Vehicle manufacturers are continuously striving to improve the process by which motor vehicles are assembled, in order to improve quality of the final product and at the same time reduce manufacturing costs. For instance, the typical method for painting a vehicle involves placing the vehicle in an enclosed chamber, typically called a paint booth, and spray painting the surface of the vehicle. As much as 40% of the paint used ends up as waste due to overspray, resulting in an accumulation of paint residue on the wall surfaces of the paint booth. A characteristic of paint commonly used on motor vehicles is that heat must be applied to cure the paint. As a result, the paint residue that collects on the walls of the paint booth typically is tacky. Periodic removal of the paint residue is necessary to prevent the buildup of paint, which tends to attract dirt that could become imbedded in the surface of the freshly painted vehicle.
In the past, removal of paint residue from the wall surfaces of the paint booth had been accomplished by filling a container with cleaning solution, dipping a scrub brush into the container and proceeding to wash the walls. This method is time consuming, and cleaning solution is wasted because it tends to drip from the scrub brush before use and also due to lack of a means for recovering the used cleaning solution.

Method for cleaning paint residue from walls of a paint booth


A threshold compensating circuit generates a bias potential VBIAS, that is, a threshold voltage of a MOS transistor offset by a given value. A gate-source voltage having compensation for variation in threshold voltage is thus applied to a transistor. By using a differential amplifier having this transistor as a current source, a voltage down-converter less susceptible to variation in threshold voltage caused by process variation and temperature can be implemented.

1. Field of the Invention
The present invention generally relates to a semiconductor device. More particularly, the present invention relates to a semiconductor device having a voltage down-converter.
2. Description of the Background Art
Recently, transistors for use in semiconductor devices are increasingly miniaturized in order to implement reduced costs, reduced power consumption and increased operation speed. A power supply potential must be reduced in order to ensure reliability of the miniaturized transistors.
A semiconductor device is a fundamental component that is used together with various components in various equipments. However, reduction in voltage has not been implemented for most other components that are used in equipments including a semiconductor device. In view of matching between a semiconductor device and other components, a semiconductor device using a miniaturized transistor must operate with an external power supply potential that is high enough to degrade reliability if it is directly applied to the transistor.
Therefore, a voltage down-converter is required. The voltage down-converter is mounted within the semiconductor device, and serves to down-convert a high external power supply potential to the level acceptable to the miniaturized transistor in terms of reliability.
FIG. 23 is a circuit diagram showing the structure of a conventional voltage down-converter 524.
Referring to FIG. 23, voltage down-converter 524 includes a reference potential generator 534 for outputting reference potentials VREF, VBGR, and a down-converting portion 536 for receiving reference potentials VREF, VBGR, down-converting an external power supply potential EXTVDD and outputting an internal power supply potential INTVDD. Internal power supply potential INTVDD is supplied to a load circuit 526. Reference potential generator 534 and down-converting portion 536 have the same structure as that of a reference potential generator 34E and a down-converting portion 36 described later. Therefore, description thereof will not be given herein. In the figure, a resistor R2A has the same resistance value as that of a resistor R2.
Down-converting portion 536 is a circuit for receiving an external power supply potential EXTVDD and generating a lower internal power supply potential INTVDD based on a reference potential VREF generated by reference potential generator 534. Internal power supply potential INTVDD is given by the following expression (1):
                    INTVDD        =                                            R5              +              R6                        R5                    *                      VREF            .                                              (        1        )
Accordingly, internal power supply potential INTVDD varies with variation in reference potential VREF. In order to prevent this, a semiconductor device is designed so that reference potential VREF is less susceptible to the internal power supply potential, process variation, and temperature variation.
FIG. 23 shows a bandgap-type reference potential generator 534. A bandgap-type reference potential generator is also called a "bandgap voltage reference", and is commonly used as a reference potential generator causing less variation in reference potential VREF.
Hereinafter, a voltage generated by the bandgap-type reference potential generator will be described. In general, a current flowing through a diode is given by the following expression (2), where Is is a saturation current, q is the amount of charges of electron, k is a Boltzmann's constant, T is an absolute temperature and Vbe is a base-emitter voltage:
                    I        =                  Is                                (                                          ⅇ                                  qVbe                  kT                                            -              1                        )                                              (        2        )                                                                            ≃                      Is            *                          ⅇ                              qVbe                kT                                                                                (                                  ∵                                      Vbe                    ⪢                                          kT                      q                                                                      )                            .                                                                                From                                                              the                                                              expression                                                                          (            2            )                          ,                  Vbe          =                                    kT              q                        *            ln                                                      I                Is                            .                                                          (        3        )                                Accordingly        ,                  in                                                                          Fig            .                                                              23                          ,                            (        4        )                                          Vbel          -          Vbe2                =                              kT            q                                          (                                          ln                                                  I1                  Is                                            -                              ln                                                  I2                  Is                                                      )                                                                                =                                    kT              q                        *                                          ln                                                  (                                      n                    *                                          I1                      I2                                                        )                                            .                                                                                Provided                                                                          that                                                                                V                                            (                W12                )                                              =                      V                                      (              W13              )                                      ,                  I1          =                      I2            .                                                              Therefore                          ,                            (        5        )                                          Vbel          -          Vbe2                =                              kT            q                    *                                    ln                                            (                n                )                                      .                                                                              Moreover        ,                              since                                                                          Vbe2                    =                                    VBGR              -                                                (                                      R1                    +                    R2                                    )                                                I2                                                                                and                                                                                Vbel                                      =                          VBGR              -              R2I1                                      ,                                                                      R2I1          +                                    (                              R1                +                R2                            )                                    I2                          =                              kT            q                                          ln                                      (              n              )                                                                                R1R2          =                                    kT              q                                                  ln                                            (                n                )                                                    ,                  I1          =                      I2            =                                                                                kT                    q                                                                          ln                                                              (                      n                      )                                                                      R1                            .                                                          (        6        )                                          From                                                              the                                                              expression                                                                          (            6            )                          ,                                                            VBGR        =                  R2I1          +          Vbe1                                    (        7        )                                                                            =                      Vbe1            +                                          R2                R1                            *                              kT                q                            *                                                ln                                                        (                    n                    )                                                  .                                                                                Therefore        ,                                                            VREF        =                              R3                          R3              +              R4                                          VBGR                                    (        8        )                                                                            =                                    R3                              R3                +                R4                                                                                (                                  Vbe1                  +                                                            R2                      R2                                        ·                                          kT                      q                                        ·                                          ln                                                                    (                        n                        )                                                                                )                            .
Note that the expression (5) is obtained on the assumption that V(W12)=V(W13). The reason for this is as follows: since transistors P1, P2 of the same size are used, the same current flows through transistors P1, P2. In this case, by using transistors N1, N2 of the same size, a differential amplifier 38E controls the gate of a transistor P6 so that V(W12)=V(W13).
Potentials VBGR, VREF generated by reference potential generator 534 in FIG. 23 are thus given by the above expressions (7), (8), respectively.
Reference potential VREF is adjusted by adjusting the resistance value of resistors R3, R4. The level of internal power supply potential INTVDD is thus adjusted.
Resistors R1, R2 are formed from the same material so as to have the same variation in characteristics and the same temperature dependency. Similarly, resistors R3, R4 are formed from the same material so as to have the same variation in characteristics and the same temperature dependency. Similarly, resistors R5, R6 are formed from the same material so as to have the same variation in characteristics and the same temperature dependency. In the figure, resistors R2, R2A have the same resistance value and are formed from the same material.
It is known that process variation is a factor that cannot be ignored for a threshold voltage Vth of a MOS (Metal Oxide Semiconductor) transistor. In contrast, as described in "Analog Integrated Circuit Design Technology for VLSI", Vol. 2, P. R. Gray, R. G. Meyer, Baifukan Co., Ltd, p. 310, Vbe is approximately unique to a material such as silicon and has little variation. However, Vbe has temperature dependency of about −2 mV/° C. Accordingly, ∂VBGR/∂T=0 is achieved by determining the resistance value of resistors R1, R2 so as to satisfy the following expression (9):
                              R2          R1                =                              -                                                            ∂                  V                                                                                be                                            ∂                T                                              *                                    q              k                        ÷                                          ln                                                  (                  n                  )                                            .                                                          (        9        )
As a result, potential VBGR generated by bandgap-type reference potential generator 534 is less susceptible to power supply voltage, process variation and temperature.
Accordingly, reference potential VREF is also less susceptible to power supply voltage, process variation and temperature.
Thus, internal power'supply potential INTVDD can be generated without being significantly affected by power supply voltage, process variation and temperature.
Recently, reduction in power consumption is increasingly required for the semiconductor devices, and therefore reduction in current consumption in the standby period is a prime task in the industry. In the semiconductor devices such as static random access memory (SRAM) and dynamic random access memory (DRAM), the value of a semiconductor device is determined mainly based on how fast the semiconductor device can start operation such as read and write operations after it transitions from standby to active state.
However, the voltage down-converter must drive a huge load circuit. Therefore, quick start operation cannot be implemented if the voltage down-converter is not operated until the semiconductor device transitions to the active state (i.e., if the voltage down-converter is stopped while the semiconductor device is in the standby state for the purpose of power saving).
Accordingly, the voltage down-converter must be operated from the standby state of the semiconductor device. Current consumption of the voltage down-converter thus accounts for a large percentage of a standby current of the semiconductor device. It is a bias current Ibias flowing through the differential amplifier that accounts for a large percentage of current consumption of the voltage down-converter. The circuit is therefore designed so as to minimize bias current Ibias.
However, as described in "VLSI Memory Chip Design", Kiyoo Ito, Springer-Verlag Telos, 2001. 4, pp. 297–298, reducing bias current Ibias degrades responsiveness of the differential amplifier, thereby causing increase in voltage drop.
FIG. 24 illustrates a problematic voltage drop caused by a reduced bias current.
Referring to FIG. 24, the semiconductor device transitions from standby to active state at time t1. If bias current Ibias is reduced, responsiveness of the differential amplifier is degraded, whereby the potential on a node W17 drops with time delay. This increases the drop Vdrop of internal power supply potential INTVDD right after transition from standby to active state.
Although a certain level of voltage drop may be accepted, the drop Vdrop exceeding a prescribed allowable range would significantly affect the high speed operation of the semiconductor device.
In the structure of FIG. 23, the threshold voltage of an N-channel MOS transistor N3 in a differential amplifier 40 of down-converting portion 536 varies depending on process variation and temperature. Bias current Ibias of the differential amplifier is determined by Vgs−Vth of N-channel MOS transistor N3, that is, VBGR−Vthn. Even if the bandgap-type reference potential generator is designed so that potential VBGR does not vary as described before, variation in threshold voltage Vthn causes significant variation in bias current Ibias.
In other words, as threshold voltage Vthn is increased, bias current Ibias is reduced. This may excessively increase the voltage drop Vdrop.
On the other hand, as threshold voltage Vthn is reduced, bias current Ibias is increased. This may significantly increase the standby current.

Semiconductor device less susceptible to variation in threshold voltage


A zoom lens includes: a first lens group having a positive refractive power and statically positioned along an optical axis when a power of the zoom lens is varied or the zoom lens is focused; a second lens group having a negative refractive power; a third lens group having a positive refractive power; a fourth lens group having a positive refractive power; a fifth lens group. The second and fourth lens groups are moved for varying the power of the zoom lens and the fourth lens group is further moved for focusing the zoom lens. The first lens group includes a reflective optical element for bending an optical path. The second lens group includes a cemented lens including a positive lens and a negative lens. The fourth lens group includes two positive lenses, and the fifth lens group includes one positive lens having at least one aspherical surface.

Recently, in the image pickup apparatus such as a small sized digital still camera, a video camera in which a small sized image pickup unit provided with a solid state image pickup element such as CCD (Charge Coupled Device) or CMOS (Complementary Metal-Oxide Semiconductor) type image sensor is mounted, the requirement for a zoom lens having the higher imaging performance is increased following to the high pixelation of the solid state image pickup element. Further, for the zoom lens of a small sized image pickup apparatus, the more size-reduction is required.
As a small sized zoom lens for a small sized image pickup apparatus, there is a zoom lens which is provided with a first lens group with a positive refractive power, a second lens group with a negative refractive power, a third lens group with a positive refractive power, and a fourth lens group with a positive refractive power, and in which the size-reduction in the thickness direction of the zoom lens is intended by being arranged a prism which bends the optical path in the first lens group (for example, refer to Patent Document 1).
(Patent Document 1) Tokkai No. 2000-131610
However, the conventional zoom lens as disclosed in Patent Document 1 has the longer entire length compared with the focal length thereof, and it is improper to use for the small sized image pickup apparatus.


Semiconductor apparatus comprising a substrate having a substrate surface; a first dielectric layer comprising molecules of a first compound, the molecules of the first compound having first ends and second ends, the first ends being covalently bonded to a first region of the substrate surface, the second ends having aromatic regions; and a polycrystalline semiconductor layer comprising organic semiconductor molecules with aromatic portions, the polycrystalline semiconductor layer being on the first region of the substrate. Integrated circuits comprising apparatus, and methods for making apparatus and integrated circuits.

Semiconductor devices are typically formed as multilayer structures in which the semiconductor materials are present in a patterned array that defines channels for the transport of charge carriers. For example, an inorganic semiconductor layer may be applied to a dielectric substrate surface. A mask may then be applied to protect patterned regions of the semiconductor layer, intended to constitute charge carrier channels, from a subsequently applied etchant. The etchant then removes the semiconductor in the unmasked regions, leaving behind a finely patterned array of semiconductor channels on the substrate. In the absence of such patterning, the semiconductor devices may be inoperable or be subject to excessive crosstalk.
Inorganic semiconductors typically are rigid and brittle at ambient temperatures. Hence, semiconductor devices formed with inorganic semiconductors generally are rigid as well. As the myriad end use applications for semiconductor devices have evolved, availability of semiconductor devices that can be flexed and bent without damage has become desirable. Flexible semiconductor device structures also offer a potential capability for fabrication of large area device arrays at low unit costs.
Much work has been done to develop organic semiconductors for applications where flexible semiconductor devices are needed. However, organic semiconductors generally cannot survive the harsh conditions required in order to carry out an etching step to generate a patterned array of channels for charge carrier transport. Printing processes have accordingly been sought in order to directly provide a patterned semiconductor channel array without a need to remove regions of a continuous layer of semiconductor material. However, in some cases the fine feature definition that is needed to generate microarrays of semiconductor channels has not been attained with acceptable reproducibility by direct printing of organic semiconductors.
Tetracene, for example, is an organic semiconductor of great interest due to its high charge carrier mobility in a single crystal. Single plate-like crystals of tetracene having dimensions as large as 5 millimeters long, 5 millimeter wide, and 0.25 millimeter thick have been produced. For example, individual thin film field effect transistors comprising single tetracene crystals have been made with high channel mobilities within a range of between about 0.1 centimeters squared per volt-second (cm2/Vs) and about 1 cm2/Vs, at room temperature. However, tetracene thin film field effect transistors in general have low mobilities and on/off current ratios, and their integration into a circuit may require further development. Furthermore, vacuum evaporation of tetracene leads to poorly defined and irregular boundaries between crystal grains that leads to low mobility and makes such grains unusable in fabricating semiconductor devices such as transistors or arrays comprising transistors.
One effort to generate a patterned array of semiconductor film channels comprising an aromatic acene semiconductor involved the direct printing of a pentacene precursor, which was then converted into pentacene. See, for example, Dimitrakopoulos et al. U.S. Pat. No. 5,981,970, issued on Nov. 9, 1999 and entitled, "Thin-film field-effect transistor with organic semiconductor requiring low operating voltages." See also, Afzali, A., Dimitrakopoulos, C. D., and Breen, T. L., "High-performance, solution-processed organic thin film transistors from a novel pentacene precursor," J. Am. Chem. Soc. 124 (30), pp. 8812–8813, Jul. 31, 2002. The entireties of both of the foregoing documents are hereby incorporated herein in their entirety.
Another process for forming patterned organic semiconductor films is disclosed in Katz U.S. Pat. No. 6,403,397 issued on Jun. 11, 2002, which is entitled "Process For Fabricating Organic Semiconductor Device Involving Selective Patterning", the entirety of which is hereby incorporated herein. This process involves treating a surface to selectively provide regions of greater affinity and lesser affinity for either an organic semiconductor or an organic semiconductor solution. When the organic semiconductor, or solution comprising the semiconductor, was deposited on the treated surface, either the organic semiconductor or the organic semiconductor solution dewetted from the lesser affinity regions or the resultant film adhered only weakly to the lesser affinity regions such that selective removal was readily performed. Even where such removal was not performed, the portions of the organic semiconductor film on the greater affinity regions exhibited higher conductivity and better film continuity relative to the other portions of the film.
There remains a need for semiconductor devices comprising organic semiconductors having finely patterned regions of high charge carrier mobility. There further is a need for methods of making semiconductor devices with organic semiconductors that are not easily patterned.

Devices having patterned regions of polycrystalline organic semiconductors, and methods of making the same


A processing system for treating a substrate includes a process chamber, a substrate holder, a gas distribution system, and a flow modulation element. The process chamber has a pumping system to evacuate the process chamber. The substrate holder is coupled to the process chamber and supports the substrate. The gas distribution system is coupled to the process chamber. The gas distribution system introduces a process gas to a process space above an upper surface of the substrate. The flow modulation element is coupled to the substrate holder beyond a peripheral edge of the substrate. The flow modulation element includes one or more gas distribution openings that introduce an additive process gas beyond the peripheral edge of the substrate in a direction substantially away from the substrate. The additive process gas has a directional component substantially parallel to the upper surface of the substrate.

1. Field of the Invention
The present invention relates to a method and system for thin film deposition, and more particularly to a method and system for uniformly depositing a thin film using chemical vapor deposition (CVD).
2. Description of Related Art
During material processing, such as semiconductor device manufacturing for production of integrated circuits (ICs), vapor deposition is a common technique for forming thin films, as well as conformal thin films over and within complex topography, on a substrate. Vapor deposition processes can include chemical vapor deposition (CVD) and plasma enhanced CVD (PECVD). For example, in semiconductor manufacturing, such vapor deposition processes may be used for gate dielectric film formation in front-end-of-line (FEOL) operations, and low dielectric constant (low-k) or ultra-low-k, porous or non-porous, dielectric film formation and barrier/seed layer formation for metallization in back-end-of-line (BEOL) operations, as well as capacitor dielectric film formation in DRAM production.
In a CVD process, a continuous stream of film precursor vapor is introduced to a process chamber containing a substrate, wherein the composition of the film precursor has the principal atomic or molecular species found in the film to be formed on the substrate. During this continuous process, the precursor vapor is chemisorbed on the surface of the substrate while it thermally decomposes and reacts with or without the presence of an additional gaseous component that assists the reduction of the chemisorbed material, thus, leaving behind the desired film.
In a PECVD process, the CVD process further includes plasma that is utilized to alter or enhance the film deposition mechanism. For instance, plasma excitation generally allows film-forming reactions to proceed at temperatures that are significantly lower than those typically required to produce a similar film by thermally excited CVD. In addition, plasma excitation may activate film-forming chemical reactions that are not energetically or kinetically favored in thermal CVD.

Method and system for improving deposition uniformity in a vapor deposition system


Provided is a method of printing barcodes from an Enterprise Resource Planning (ERP) system. A label name is added to a barcode data in the ERP system, wherein the label name is unique to a barcode in the barcode data. The label name and the barcode data are transmitted to a server. The label name is analyzed to identify the barcode in the barcode data, and the identified barcode is replaced with a PostScript program, unique to the identified barcode, for visually rendering the identified barcode. The PostScript program, unique to the identified barcode, is transmitted for printing the identified barcode.

Usage of Enterprise Resource Planning (ERP) systems has gained popularity among enterprises over the last few years. An increasing number of businesses around the world have either implemented or are in the process of implementing an ERP program or module to manage one or more aspects of their functions such as inventory control, human resource, marketing, finance, distribution, etc. Such widespread acceptance has led to a tremendous increase in printing of documents from ERP systems.

Printing barcodes from an enterprise resource planning (ERP) system

HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.


A method for adjusting signal data detected in a structural health monitoring (SHM) system to compensate for the effects of environmental variables acting thereon includes constructing a baseline data space comprised of sets of signal data. Current signal data sets are collected for comparison to the baseline data space. The collected current signal data sets are amended to best match baseline signal data sets in the baseline data space. A set of indices are computed for comparing the amended current signal data set to the baseline signal data sets. A threshold for detection is determined by outlier detection for the computed indices. A signal in the collected signal data set is determined to be detected on the basis of the threshold. A representation of the detected signal strength is provided on the basis of the computed indices.

Current state-of-the-art methodologies in structural health monitoring and damage detection rely heavily on the use of baseline data collected from the structure in the undamaged state. The methodologies are based on comparing the current sensor response signal data to the previously recorded baseline sensor response signal data, and using the differences to glean information about structural damage therefrom. It is known that environmental effects (such as temperature) can cause changes in the recorded signals, including baseline data, which in turn, will adversely affect most damage detection and evaluation schemes. However, a prior set of baseline data may not be readily obtainable, or environmental sensors may not be able to function under all operational conditions. Therefore, to overcome this difficulty, it is desirable to have a method for dynamically compensating sensor response signal data for the effects of environmental variables, such as temperature or other environmental variables, using sparse data acquired during the operation of a SHM system without the need to measure the environmental variables.

Dynamic environmental change compensation of sensor data in structural health monitoring systems