A seat, preferably an aeroplane seat, includes a seat base (12) which can be positioned on the floor and seat components which are provided for each seat and are arranged on the seat base (12). The seat components can be a seat back (1) and a seating element (2) with a front region (3) and a rear region (4). The rear region is located at the point where the seating element joins the seat back (1). The seat back can be displaced from an upright position to an inclined position and vice versa, simultaneously adjusting the inclination of the seating element (2). The front region (3) of the seating element (2) essentially maintains its height above the floor. The rear region (4) sinks as the seat back (1) increasingly inclines. The seat back (1) has at least one first part (5) and one second part (6) which at least partially support each other with the adjacent surfaces and which can be displaced in relation to each other during the adjustment of the inclination of the seat back (1). The inclination of the seating element (2) is automatically adjusted. As a result, the rear region of the seating element significantly sinks as soon as the seat back is slightly inclined towards the rear, with the front region of the seating element maintaining the same position.

WO 00/29249 discloses a vehicle seat, with a seat part and a seat back part held on the seat frame by side cheeks and movable relative to the frame by an actuating drive. The actuating drive has body position detectors control-connected for moving the respective seat part or seat back part forward or backward to the body position assumed by the seat occupant or according to the body movement of the seat occupant. In this known approach, the seat part and the seat back part are adjustably guided in a type of restricted guidance, and are pivotally connected to one another by an articulated axis. The seat part and the seat back part are each guided with a distance to the articulated axis and are rotatable around their guide axes. The indicated body position detector is designed as a distance measuring means, but can also be a pressure sensor or pressure switch which allows adjustment motion of the seat controlled by the operator.
The known seat design is ergonomically perfected and allows a plurality of adjustment possibilities. The seat part and seat back part can also be controlled and adjusted separately from one another. Based on the indicated sensor technology by the body position detectors, the associated control cost for the seat is correspondingly high so that the known seat design is expensive and complex to produce. As a result of the plurality of components and the indicated control, failures in operation cannot be avoided. Furthermore, the known seat is relatively heavy, indicating that its use in the aircraft domain is not altogether practical, so that the pertinent seats are used preferably in the first class section of aircraft.
U.S. Pat. No. 5,636,898 and EP-A-1 057 725 disclose comparable seat designs. The front area of the seat part is raised automatically with the tilt adjustment of the seat back into a backward position, by which the tilt adjustment for the seat part itself inevitably arises. Since the raising of the thigh of the seat occupant is associated with the raising of the front edge of the seat part, overall the legs are moved away from the respective floor of the vehicle. This movement is perceived as not always pleasant from the ergonomic standpoint of the operator or passenger.
Conversely, DE-C-42 22 222 and U.S. Pat. No. 5,133,587 have already proposed essentially fixing the front area of the seat part by a type of rotary or swivel function in height relative to the floor and swivelling the seat back together with the seat part. The seat back and seat part are designed as a common shell for a change in the position of the seat components relative to the front edge of the seat part. In the pertinent designs, generally a distinct tilt adjustment of the seat back, in addition to its lowering into the backward position, is necessary in order to be able to lower the seat part in an ergonomically favorable manner in the back area. For a correspondingly comfortable adjustment process, the seat back, therefore, has to be inclined far back. This arrangement entails loss of comfort for the individual in the row of seats behind.


A word line is connected to a control gate of memory cell transistor, and a bit line and a source line are connected to a drain and a source of the memory cell transistor, respectively. A write clock having a certain crest value is applied to the source line, and an earth potential or a power supply potential is applied to the bit line in response to a read clock having a phase which is opposite to that of the write clock. A row selection clock which synchronizes with the write clock and a crest value of which is de-escalated is applied to the word line.

1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device which enables storing analog information and multiple-valued information using memory cell transistors having floating gates.
2. Description of the Related Art
In an electrically erasable programmable ROM (EEPROM) in which a memory cell is composed of a single transistor, each memory cell is formed by a double gate transistor having a floating gate and a control gate. In such a double gate memory cell transistor, data are written to the memory cell transistor by accelerating and injecting hot electrons generated on the drain region side of the floating gate. On the other hand, data are read out from the memory cell transistor by detecting a difference in performance characteristics of the memory cell transistor which may arise depending on whether or not electric charges are injected into the floating gate.
FIG. 1 is a top view of the memory cell portion of a nonvolatile semiconductor memory device having floating gates, and FIG. 2 is a sectional view along its X--X line. These drawings show split gate structure in which a part of a control gate is arranged side by side with a floating gate.
On the surface area of a P-type silicon substrate 1, a plurality of isolated regions 2 composed of oxide film (LOCOS), which is thickly formed in selective, are formed in rectangular pattern, and element regions are marked off by the oxide film (LOCOS). On the oxide film 3 formed on the silicon substrate 1, a plurality of floating gates 4 are arranged such that each of these gates stretches over two neighboring isolated regions 2. The floating gates 4 are independently arranged at every memory cell. Further, oxide film 3a is thickly formed on the central part of each of the floating gates 4, thereby causing the edge of the respective floating gates 4 to form an acute angle. This facilitates electric field enhancement at the edge of the respective floating gates 4 when data is erased. On the silicon substrate 1 where a plurality of floating gates 4 are arranged, control gates 5 are arranged in such a manner that each control gate 5 corresponds to the floating gate 4 in every row. These control gates 5 are arranged in such a manner that a portion of each control gate 5 lies on the oxide film 3a and faces the corresponding floating gates 4 and the remaining part lies upon the oxide film 3 and faces the silicon substrate 1. These floating gates 4 and control gates 5 are arranged in such a manner that the respective neighboring rows have a plane symmetry with each other. In a substrate region between neighboring control gates 5 and a substrate region between neighboring floating gates 4, N-type first diffusion layers 6d and second diffusion layers 6s are formed. Each of the first diffusion layers 6d is surrounded by the isolated region 2 between neighboring control gates 5 and is thereby independent. The second diffusion layers 6s are arranged between neighboring floating gates 4 successively in a direction which the control gates 5 are extended. A memory cell transistor is composed of one floating gate 4, one control gate 5, one first diffusion layer 6d, and one second diffusion layer 6s. Here, the first diffusion layer 6d becomes a drain, whereas the second diffusion layer 6s becomes a source. On the oxide film 7 formed on each control gate 5, aluminum wiring 8 is arranged in a direction which the aluminum wiring 8 intersects the control gates 5. The aluminum wiring 8 is connected to the first diffusion layers 6d through contact holes 9.
For a memory cell transistor having such double gate structure, an ON-state resistance value between the source and the drain fluctuates with the amount of electric charge injected into the floating gate 4. Thus, by selectively injecting into the floating gate 4 an amount of electric charge which is in proportion to memory information, an ON-state resistance value of specified memory cell transistor may be varied in multiple stages.
FIG. 3 is a circuit diagram of the memory cells portion shown in FIG. 1. This diagram shows memory cells arranged in four rows of four.
In memory cell transistors 11 having a double gate structure, the control gates 5 arranged in the same row are connected to one of the word lines 12, and the first diffusion layers 6d (drains) arranged in the same column are connected to one of the bit lines 13 while the second diffusion layers 6s (sources) are connected to source line 14. The respective bit lines 13 are connected to a data line 16 via selection transistors 15 and also connected to a sense amplifier (not shown in drawings) to read out a voltage value.
The source line 14 to which each row of the memory cell transistors 11 is connected in common provides a write clock having a regular cycle .phi.W to each of the memory cell transistors 11. Further, the data line 16, which is selectively connected to each of the bit lines 13 via each of the selection transistors 15, selectively provides a read clock .phi.R to each of the memory cell transistors 11. In the case of an ordinary device, the respective control gates 5 which are formed at the same row of the memory cell transistors 11 in common are used as word lines 12, whereas the aluminum wirings 8 to be connected with the first diffusion layers 6d are used as bit lines 13. Further, the second diffusion layers 6s extended in parallel with the control gates 5 are used as source lines 14.
Row selection signals LS1 to LS4 are generated based on row address information. By selecting one of the word lines 12, a specified row of the memory cell transistors 11 is activated. Column selection signals CS1 to CS4 are generated based on column address information. By turning on one of the selection transistors 15, a specified column of the memory cell transistors 11 is activated. Thus, one of the plurality of memory cell transistors 11 to be arranged in a queue is designated based on the row address and column address information, and connected to the data line 16.
When data are written into one of the memory cell transistors 11, an earth potential (for example, 0V) is applied from one of the bit lines to the memory cell transistor 11, and a write potential (for example, 14V) is applied thereto from the source line 14. Thus, data are written into a specified memory cell transistor 11 which is selected in response to the row selection signals LS1 to LS4 and the column selection signals CS1 to CS4. In other word, electric charges are injected into the floating gate 4 of a specified memory cell. Further, when the data written into the memory cell transistor 11 are read out, a read potential (for example, 5V) is applied from one of the bit lines 13 and an earth potential (for example, 0V) is applied from the source line 14 to the memory cell transistor 11, respectively. Current then flows through the selected memory cell transistor 11 and a potential of the bit lines 13 fluctuates according to an ON-state resistance value of the memory cell transistor 11. The potential of the bit line at this time can be read out by the sense amplifier.
When analog information is written into the memory cell transistor 11, injection of electric charges (writing of data) and confirmation of the amount of the injection (reading of data) are repeated at a short interval in order to enhance recording accuracy. More specifically, while data are written into the memory cell transistor 11 little by little, all data are read out each time. When contents of the data to be stored coincides with the result of reading out, writing is terminated. For example, as shown in FIG. 4, write clock .phi.W and read clock .phi.R are set in reverse phase to each other, and either a write potential and a read potential or an earth potential are alternately applied to the bit lines 13 selected and source line 14 at regular intervals. Thus, the write clock .phi.W is raised and a write potential is applied to the source line 14, whereby a period of applying an earth potential to the bit line 13 becomes a writing period W. Further, the read clock .phi.R is raised and a read potential is applied to the selected bit lines 13, whereby a period of applying an earth potential to the source line 14 becomes a reading period R. When the result of reading out reaches a desired potential corresponding to memory information in reading operation, the write clock .phi.W is terminated and writing operation completes.
FIG. 5 is a block diagram showing the constitution of a sense amplifier to detect an ON-state resistance value of the memory cell transistor 11 which is connected to the bit line 13.
The sense amplifier is composed of a pair of load resistances 21 and 22, a pair of current amplifiers 23 and 24, a reference transistor 25, a controlled potential generating circuit 26, a differential amplifier 27, and a determination control circuit 28. The pair of load resistances 21 and 22 have the same resistance value and are connected to a power source. The pair of current amplifiers 23 and 24 are composed of transistors and inverters, and are connected to the pair of load resistances 21 and 22 connected to the power source. The bit line 13 to be connected to the memory cell transistor 11 is connected to the current amplifier 23 on one side, whereas the reference transistor 25 is connected to the current amplifier 24 on the other side. The reference transistor 25 is connected between the current amplifier 24 and an earth point, and varies a resistance value in response to a reference potential VRG which is applied to a gate of the reference transistor 25. The controlled potential generating circuit 26 generates the reference potential VRG which is corresponding to multiple-valued information to be stored in the memory cell transistor 11, and then provides the reference potential VRG to a gate of the reference transistor 25. For example, when the memory cell transistor 11 stores information of four values (two-bit portions), three kinds of gate potentials VRG are successively generated so as to vary the resistance value of the reference transistor 25 in three stages.
Two inputs of the differential amplifier 27 are connected to contact points with both the pair of load resistances 21 and 22 and the pair of current amplifiers 23 and 24. The differential amplifier 27 compares potentials VBL and VRL of each contact point, and provides a comparison output CO to a determination control circuit 28. The determination control circuit 28 controls generation of the reference potential VRG by the controlled potential generating circuit 26. It also discriminates the comparison output CO provided from the differential amplifier 27 and generates data D1 and D2 of multiple bits corresponding to multiple-valued information. For example, when information of four values is discriminated, the intermediate reference potential among three levels of reference potentials is first generated in order to determine a superior bit, and then either of higher and lower potentials among the three levels of reference potentials is generated according to the result of determination of the superior bit in order to determine an inferior bit.
When data are read out from the memory cell transistor 11, as the source of the memory cell transistor 11 is grounded, the load resistance 21 and the memory cell transistor 11 are connected in series between a power supply and an earth via the current amplifier 23. Similarly, the load resistance 22 and the reference transistor 25 are connected in series between a power supply and an earth via the current amplifier 24. A potential VBL at the contact point of the load resistance 21 and the current amplifier 23 is determined based on a ratio of the load resistance 21 to the memory cell transistor 11 in driving force. Similarly, a potential VRL at the contact point of the load resistance 22 and the current amplifier 24 is determined based on a ratio of the load resistance 22 to the reference transistor 25 in driving force. Therefore, based on the comparison output CO from the differential amplifier 27, it is possible to determine a range in which a resistance value of the memory cell transistor 11 is, as compared with the reference transistor 25 whose resistance value is varied in stages. Such a sense amplifier is, for example, disclosed in 1995 IEEE/International Solid-State Circuit Conference/Session 7/Flash Memory/Paper TA 7.7.
In the case of a split gate type memory cell transistor 11, whenever writing is performed by the write clock .phi.W (electric charges are injected into the floating gate), an ON-state resistance value becomes high. Therefore, at the time of reading operation which is alternately repeated with writing operation, a potential VBL of the bit line 13 varies in stages from an earth potential to a power supply potential as the writing operation is repeated, as shown in FIG. 6. A variation of the potential VBL at the bit line 13 resulting from the writing operation performed once is large in the beginning of the writing operation, but gradually becomes small with the progress of the writing operation. Further, when it finally reaches the power supply potential VDD, the potential VBL at the bit line 13 no longer varies.
When the memory cell transistor 11 is made to store multiple-valued information, a range between the earth potential and the power supply potential is equably divided by the number of steps of memory information, and the number of writing operations is controlled in order that the bit line potential VBL at the time of a reading operation corresponds to one of the divided potentials to be written. For example, as described above, when the memory cell transistor 11 is made to store information of four values, for the purpose of enabling reading out two kinds of intermediate values, the number of writing operations is controlled so that the bit line potential VBL coincides with either of the potentials VDD/3 or 2VDD/3 which are two parts of a trisection of the power supply potential VDD (the earth potential is 0V). However, if an amount of electric charges in writing operation at a time is large, in other words, if a rate of change of the bit line potential VBL is large (a sharp rise of the curved line shown in FIG. 6), it will be difficult to accurately control the bit line potential VBL and therefore there will be a large error in the values between a desired potential to be written and a bit line potential VBL to be read out. Consequently, resolution of the memory cell transistor 11 is deteriorated, thereby making it difficult to achieve a multiplicity of values of memory information.

Non-volatile semiconductor memory device


The present invention relates to a mobile audio player, comprising memory means adapted to store music data and non-music data, input means adapted to receive a user input with user preferences, radio program generating means adapted to generate, without a connection to an external entity, an individualized radio program from stored music data and non-music data depending on user preferences input via the input means, and audio output means adapted to output audio signals representing a generated radio program.

(1) Field of the Invention
The present invention relates to a mobile audio player adapted to output an individualized radio program.
Mobile audio players adapted to store and output audio signals representing music, speech and so forth are in widespread use, either as devices which exclusively store and play audio signals, such as so-called "MP3" players and the like, or as part of mobile phones, PDAs, laptops and the like. Typically, a user stores music data and/or non-music data from an external source, such as the Internet, a personal computer and so forth, into the mobile audio player and is then able to listen to the stored content anytime and anywhere. Most mobile audio players have something like a "playlist" functionality in which a user can select music and/or non-music content according to his or her preferences, but in any case the selection is limited to pre-generated and pre-stored content. Some mobile audio players additionally have a radio functionality, i.e. are adapted to receive AM or FM signals from radio stations, so that the user can listen to a wanted radio broadcast while being in reach of a corresponding radio transmitter. Hereby, the listening experience is restricted to general broadcast content which is generated centrally in a remote radio station and broadcast to a large number of users simultaneously. Further, it is necessary that the mobile audio player is within the reach of a transmitter of a radio station in order to be able to receive the radio signals and output audio signals representing the respective radio program.
(2) Description of Related Art Including Information Disclosed Under 37 CFR 1.97 and 1.98.

Mobile audio player with individualized radio program


A method for controlling a display device, according to one embodiment of the present invention, comprises: displaying, on a main screen of a display device, content including at least one object; receiving an input for selecting a specific object from the at least one object displayed on the main screen; specifying the specific object by corresponding to the received selection input, expanding a specific area including the specific object; displaying a window including the content displayed on the main screen; displaying the expanded specific area on the main screen; and displaying, within the displayed window, an indicator for displaying the expended specific area, wherein the specific area changes according to a position of the specific object, and the content corresponds to a video.

Recently, a display device such as a smart TV has been used by many users. As the high-price customized content markets are extended and types thereof are diversified, the demands of the users for customizing images also increase.
In the related art, a function of detecting an object that a user desires to enlarge and watch has not been supported. Thus, when the user performs the screen enlargement function on a video such as sports where object movement frequently occurs, the zoom screen should be moved whenever a position of the object, which the user is interested in, is changed.
For example, when a user desires to watch a soccer game focusing on a soccer ball and enlarge a screen at the center of the ball on a sports channel broadcasting the soccer game, there may be a problem because the screen cannot be partially enlarged in the related art. That is, since when the ball moves, it is difficult to continuously trace the ball movement, the user may experience inconvenience.

Display device and control method therefor


A sheet feeding apparatus including a stacking portion for stacking a plurality of sheets thereon, a sheet feeding portion for feeding the sheets stacked on the stacking portion, a fan for sending air to the sheets to loosen the sheets stacked on the stacking portion, a heater for warming the air sent by the fan, a temperature detecting portion for detecting the temperature of the heater, and a control portion for starting the driving of the fan in conformity with the temperature detecting portion having detected a predetermined temperature after temperature control for adjusting the heater to a target temperature has been started.

1. Field of the Invention
The invention relates to a sheet feeding apparatus for sending warm air to a sheet to be fed.
2. Related Background Art
There has been proposed a construction for flowing warm air against paper in a sheet feeding paper deck mounted on an image forming apparatus such as a copying machine to thereby loosen the paper (for example, Japanese Patent Application Laid-Open No. 2001-048366).
In this example of the prior art, basically the temperature controlling operation of an air heater and a sheet loosening operation (for example, the start of fan rotation and the start of swing shutter motor rotation) are started at a time. That is, the fan starts rotation simultaneously with the start of the temperature control of the air heater.
Therefore, much time is required until the air heater temperature, i.e., warm air temperature assumes a predetermined value, and this leads to the disadvantage that the time until the loosening operation is terminated and the sheet feeding operation becomes possible is slow with a result that the performance of the entire apparatus is lowered.
Also, in order to avoid the above-noted disadvantage peculiar to the above-described example of the prior art, there is conceivable a construction for starting the loosening operation before the air heater temperature reaches the predetermined value, but in this case, the loosening operation (air assisting operation) is started before the warm air temperature rises sufficiently, and this leads to the disadvantage that loosening becomes insufficient.
Generally, in an air assisting construction wherein warm air is blown against the sheets in the paper deck to thereby loosen the sheets to reliably loosen the sheets, it is necessary to flow warm air of a predetermined temperature or higher for a predetermined value of time or longer, and flowing air of a temperature lower than the predetermined temperature is little effective for the loosening of the paper. Also, in case of blowing an air of low temperature against the sheets of paper, the sheets of paper may get damp. As a result, this may affect the loosening operation, and deteriorate quality of images to be formed on the sheets of paper.


The new digital level and laser clipper liner kit is concerned with providing a means for measuring and cutting hairlines, beards and mustaches in straight lines or at a desired angel with precision. Existing level-type devices for hair care are generally useful for a single hair maintenance task, whereas the new digital level and laser clipper kit provides a means for accurately performing all traditional haircutting tasks. The digital level and laser clipper liner kit contains: a digital level clipper liner, a front laser level tool, a side laser level tool, and skin-safe marking pens.

The new digital level and laser clipper liner kit is concerned with providing a means for measuring and cutting hairlines, beards and mustaches in straight lines or at a desired angel with precision. It is known that the accuracy of current industry clippers is dependent on the user to determine angles and straight lines while trimming various hair lines and matching up two sides at exact angles (i.e. side burns, beards, mustaches, hairlines). It is also known that clippers are sold and operated by individuals as well as professionals. However, it has not been possible heretofore for hair care professionals or personal users to guarantee exact angles and cut straight lines with certainty, nor has their been in an industry-friendly tool specifically allowing for these types of measurements or this degree of accuracy.
Level devices have been introduced to the market for use on hair clippers or shavers—such as those disclosed in U.S. patent application publications 2008/0222906 A1, 2008/0060667 A1 and 2004/0139615 A1—as well as for use on one's finger during the hair cutting process—such as that disclosed in U.S. Pat. No. 8,056,248 B2. Each such device is generally useful for a single hair maintenance task, whereas the new digital level and laser clipper kit provides a means for accurately performing all traditional haircutting tasks.

Digital level and laser clipper liner kit


An audio power amplifier includes a pre-amplifier, an error amplifier, a comparator, a bridge circuit, and a feedback circuit, in which the gain of the pre-amplifier gradually increases when the audio power amplifier is powered on. The comparator generates a PWM signal by comparing a reference signal and an amplified audio signal. The bridge circuit has switches controlled according to the PWM signal such that a driving current alternately flows to and from a load. The feedback circuit generates the feedback signal indicating a condition of the load.

1. Field of Invention
The present invention relates to a power amplifier. More particularly, the present invention relates to a power amplifier for amplifying an audio signal.
2. Description of Related Art
Many types of electronic audio amplifiers are used today for commercial public address systems, automobile stereo systems as well as portable battery operated products including two-way radios. These audio amplifiers have varying power requirements and amplification characteristics. One general type of audio amplifier is a Class D amplifier. Class D amplifiers exhibit a high efficiency and are commonly used with pulse width modulated (PWM) drivers. As is well known in the art, a class D audio power amplifier typically uses a complementary metal oxide semiconductor (CMOS) inverter whose logic state is switched depending on the PWM pulse.
Pulse width modulation (PWM), sometimes referred to as pulse duration modulation, is a signal processing technique in which a sample value of an input information signal is represented by some property of a resultant pulse other than an amplitude value. When PWM is used, the samples of a message are used to vary the duration of the individual pulses. Thus with PWM, input information is encoded into the time parameter instead of amplitude. The modulating input wave may vary the time of occurrence of the leading edge, trailing edge or both edges of the resultant pulse train.
However, when the audio power amplifier powers on, there might be a large dc current flowing into the amplifier and the load driven by the amplifier, which might damage the load and produce the unpleasant pop noise.
Hence, there is a need for a new audio power amplifier which can prevent the pop noise, and prevent the load from being damaged by the large dc current when the amplifier powers on.

Audio power amplifier and a pre-amplifier thereof


A rapid near-infrared instrument for measuring constituents of nonhomogeneous samples is disclosed which alleviates the need for taking successive measurements of the sample, and repositioning the sample for each successive measurement, by providing a novel illumination system including a light pipe which transmits near-infrared energy to the sample at a plurality of substantially separate and independent location. This arrangement permits a plurality of subsample measurements to be taken simultaneously which enables accurate constituent measurements to be made quickly and easily.

1. Field of the Invention
This invention relates to methods and instrumentation for nondestructively measuring constituents, such as protein, moisture and oil in nonhomogeneous samples using near-infrared radiation, and particularly the rapid near-infrared measurement of such nonhomogeneous samples. More particularly, this invention provides an easy to use, low-cost instrument for analyzing constituents of nonhomogeneous samples, such as grain samples.
2. Description of the Prior Art
Near infrared measuring instruments that provide an accurate measure of constituents, such as protein, moisture and oil in nonhomogeneous organic products and other products utilizing near-infrared radiation are known in the art and have become commercially successful. Such instruments are particularly useful for measuring protein, oil and moisture in cereal grain in a totally nondestructive mode to a high degree of accuracy. Such instruments are commercially available from Trebor Industries, Inc. in Gaithersburg, Md. For example, in the grain industry, thousands of country elevators are currently using the TREBOR-90XL to provide protein and moisture measurements in wheat and barley. Similarly, in the food industry, the TREBOR-99 and the TREBOR-30A instruments are widely used in the near-infrared analysis of snack food, candy products, etc. These instruments are described in U.S. Pat. Nos. 3,286,327, 4,379,238, 4,404,462, 4,466,076 and 4,692,620, each assigned to Trebor Industries, Inc.
Although these known instruments have proven to be commercially successful, they, nevertheless, do have certain limitations. One such limitation is that these known devices require successive measurements from multiple locations, so that the resultant constituent measurements represent a meaningful average of the total product. Taking these multiple successive measurements of a single nonhomogeneous sample can result in larger time consumption and additional mechanical complexity. Specifically, the prior art devices require the nonhomogeneous sample to be moved, then stopped, in front of the near-infrared source and detector, and measurements made. The sample to be analyzed must then be again moved, stopped and measured wherein this process is repeated several times. In general, this process has to be done approximately 10 to 20 times in order to provide acceptable accuracy and precision. The process of repeatedly stopping, moving and measuring a single nonhomogeneous sample to obtain its constituent measurements can be burdensome and time consuming, typically lasting thirty seconds or longer. (See U.S. Pat. No. 4,692,620).
Further, accomplishing these multiple starts and stops requires the use of mechanical components which have an inherent lower reliability and add to the instrument's overall complexity.
While a number of prior art devices have proposed fiber optic containing assemblies for transmitting energy from a source to a sample, the use of fiber optics will lead to undue expense in the cost of manufacture. While fiber optics have many unique characteristics, we have found these characteristics to be unnecessary in the present application of near-infrared analytical technology.
Thus, there is a great need for an accurate, reliable near-infrared instrument having increased sample measuring speed and which is not subject to the mechanical "weakness" and complexity inherent in the current generation of instruments. Further, there is a need for an inexpensive analytical instrument which does not employ fiber optic technology in the interest of maintaining costs to manufacture at a minimum.

Rapid near-infrared measurement of nonhomogeneous samples


Apparatuses and methods are provided to generate customizable databases and/or analyze performance. In an example embodiment, a method of generating customizable databases is provided. The method includes receiving a calculation expression relating to one or more defined characteristics. The calculation expression may be defined by a user. The method also includes loading data into a data warehouse. The data includes at least one of the one or more defined characteristics. The method further includes generating a data cube based on the received calculation expression and the data loaded into the data warehouse. The data cube includes an accessible table. A corresponding apparatus is provided. Additional method and apparatus to analyze performance are also provided.

Various other data analytic platforms lack the flexibility and customizability of the present disclosure. For example, users are restricted to use only system pre-defined metrics. Traditional data analytic platforms do not allow for altering of the computation expression or adding new key performance indicator(s) (KPIs). Through applied effort, ingenuity, and innovation, many identified problems have been solved by developing solutions that are included in embodiments of the present disclosure, many examples of which are described in detail herein.

Methods and apparatus for monitoring configurable performance indicators


A vessel protector system includes an outer sheath, an inner tube disposed within the outer sheath and moveable in a longitudinal direction relative to the outer sheath and at least one protector coupled to the inner tube, each of the at least one protector having a body formed from a filtering material and extending between a leading end and trailing end coupled to the inner tube, the body having a collapsed configuration and an expanded configuration. A snare is coupled to the leading end of the body at one end, and having a second end passing through the interior of the outer sheath, whereby the exertion of a pulling force on the second end of the snare contracts the at least one protector.

The present invention is related to protecting against embolism, and more particularly to devices, systems, and methods for the filtration and removal of debris within blood vessels.
A frequent risk in medical procedures is the risk that the procedure will give rise to the formation of potentially life-threatening debris in the patient's bloodstream. Such debris may take the form of plaque or thrombi, which may travel through the patient's vasculature and become lodged in a position that blocks blood flow. For example, during coronary interventions, plaque may become dislodged and/or thrombi may form, both of which could migrate to the carotid arteries, possibly blocking the carotid arteries and causing a stroke.
Moreover, during a heart attack the left atrium can stop beating or go into fibrillation, which will cause temporary stagnation of blood. This blood can coagulate and form clots that can migrate once the heart is returned to normal rhythm. Emergency angioplasty or stent placement may be performed to treat the attack but such procedures typically don't alleviate the problems associated with the coagulated blood.

St. Jude Medical, Cardiology Division, Inc.


The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.

Magnetic random access memories (MRAMs) employ magnetic multilayer films as storage elements. When in use, an MRAM cell stores information as digital bits, which in turn depend on the alternative states of magnetization of thin magnetic multilayer films forming each memory cell. As such, the MRAM cell has two stable magnetic configurations, high resistance representing a logic state 0 and low resistance representing a logic state 1, or vice versa.
A typical multilayer-film MRAM includes a number of bit or digit lines intersected by a number of word lines. At each intersection, a film of a magnetically coercive material is interposed between the corresponding bit line and word line. Thus, this magnetic material and the multilayer films from the digit lines form a magnetic memory cell which stores a bit of information.
The basic memory element of an MRAM is a patterned structure of a multilayer material, which is typically composed of a stack of different materials, such as copper (Cu), tantalum (Ta), permalloy (NiFe) or aluminum oxide (Al2O3), among others. The stack may contain as many as ten different overlapping material layers and the layer sequence may repeat up to ten times. Fabrication of such stacks requires deposition of the thin materials layer by layer, according to a predefined order.
FIG. 1 shows an exemplary conventional MRAM structure including MRAM stacks 22 which have three respective associated bit or digit lines 18. The digit lines 18, typically formed of copper (Cu), are first formed in an insulating layer 16 formed over underlayers 14 of an integrated circuit (IC) substrate 10. Underlayers 14 may include, for example, portions of integrated circuitry, such as CMOS circuitry. A pinned layer 20, typically formed of ferromagnetic materials, is provided over each digit line 18. A pinned layer is called "pinned" because its magnetization direction does not change during operation of the memory device. A sense layer 21 is provided over each associated pinned layer 20. The MRAM stacks 22 are coupled to a word line 23 that intersects three pinned layers 20 and associated sense layers 21. The word line 23 and bit line 18 may also be interchanged.
An MRAM device integrates magnetic memory elements and other circuits, for example, a control circuit for magnetic memory elements, comparators for detecting states in a magnetic memory element, input/output circuits, etc. These circuits are fabricated in the process of CMOS technology in order to lower the power consumption of the MRAM device. The CMOS process requires high temperature steps which exceeds 300° C. for depositing dielectric and metal layers and annealing implants, for example.
In addition, a magnetic memory element includes very thin layers, some of them are tens of angstroms thick. The performance of the magnetic memory element is sensitive to the surface conditions on which magnetic layers are deposited. Accordingly, it is necessary to form a flat surface at certain stages of fabrication to prevent the characteristics of an MRAM device from degrading. The present invention provides a method of fabricating an MRAM having a more planar surface prior to deposition of the magnetic stack.

This patent is subject to a terminal disclaimer.

Layered magnetic structures having improved surface planarity for bit material deposition


The invention has objects of providing an olefin production method which can produce an olefin with high efficiency by the dehydration reaction of an alcohol even in the presence of a ketone without the occurrence of side reactions such as the Aldol condensation of the ketone, as well as providing an olefin production method which can produce an olefin with high activity and high selectivity in a single reaction step by directly reacting a corresponding ketone and hydrogen. The former olefin production method of the invention produces an olefin from an alcohol using a silica gel (A) as a dehydration catalyst which is obtained by bringing a silica gel (X) prepared from an alkyl orthosilicate into contact with a water-soluble aluminum compound and calcining the contact product or is obtained from a wet-process silica gel (Y) prepared from an alkali silicate and which contains an aluminum compound at 10 to 1000 ppm in terms of aluminum element as well as an alkali metal and an alkaline earth metal at a total of 0 to 350 ppm. The latter olefin production method produces an olefin from a ketone and hydrogen in a single reaction step in the presence of the silica gel (A) and a silver-containing inorganic substance (B).

A reaction between benzene and propylene gives cumene. The oxidation of cumene results in cumene hydroperoxide. The cumene hydroperoxide is acid decomposed into phenol and acetone. A combination of these known reactions is the cumene process which is currently a mainstream method for the production of phenol.
The cumene process gives acetone as a by-product. This by-production is advantageous when both phenol and acetone are demanded. However, if the amount of by-product acetone is in excess of demand, the economic efficiency can be deteriorated due to the price difference between acetone and propylene which is a starting material. Methods have been then proposed in which the by-product acetone is converted into propylene through various reactions and is reused as a material in the cumene process.
Acetone is readily hydrogenated into isopropyl alcohol. A process has been then proposed in which isopropyl alcohol thus obtained is intramolecularly dehydrated into propylene and the propylene is reacted with benzene to give cumene. That is, acetone is reused as a material in the cumene process by being converted into propylene through reactions in two stages (Patent Literature 1).
Further, Patent Literatures 2 and 3 propose methods for producing propylene from acetone and hydrogen in one stage, namely, through a single reaction step. In order to implement the reuse of acetone on an industrial level through such a one-stage reaction, it is necessary not only that the process be a practical process capable of producing propylene from acetone with high activity and high selectivity but also that the catalyst used in the process be easily available or readily producible at low cost. For example, phosphotungstates described in Patent Literature 3 as examples of heteropoly acid salts are allegedly effective for catalyzing the dehydration reaction of isopropyl alcohol. However, the production of such phosphotungstates entails multiple reaction steps. Further, the establishment of a practical method capable of converting acetone into propylene as well as of producing olefins from corresponding general ketones with high selectivity is valuable in various fields of industry other than the phenol industry.
For example, Patent Literature 4 describes a method in which propylene is obtained in one stage through the hydrogenation of acetone at 400° C. in the presence of a Cu (25%)-ZnO (35%)-Al2O3 (40%) catalyst. However, the acetone conversion is as low as 89% in spite of the fact that the reaction temperature is high at 400° C. Further, the propylene selectivity obtained by this method is as low as 89% because of the side reaction hydrogenating the produced propylene into propane. According to the findings by the present inventors, it has been confirmed that the hydrogenation of acetone into propylene in the presence of a mixed catalyst including a hydrogenation catalyst and a general dehydration catalyst can be accompanied by the Aldol condensation of acetone by the dehydration catalyst with the result that the formed Aldol reaction product can further undergo a dehydration reaction, a decomposition reaction and a hydrogenation reaction. That is, by-products are likely to be derived from acetone that is a starting material. Further, the use of a general dehydration catalyst can induce other reactions such as the oligomerization of formed propylene. Thus, the present inventors consider that the design and selection of a catalyst, in particular a dehydration catalyst, are the technical key to successfully producing propylene from acetone and hydrogen.


A temperature condition of a motor is estimated more accurately based on a drive amount of the motor. An apparatus for determining overheating of a motor, includes: an information obtaining section that obtains information about a drive amount of a motor and information about a stop time etc. between drive operations of the motor; a calculating section that executes a calculation of calculating an integrated value by successively adding up the drive amount of the motor based on the information about the drive amount obtained by the information obtaining section, and a calculation of subtracting, from the integrated value, a subtraction value corresponding to the stop time etc. that is obtained based on the information about the stop time etc. obtained by the information obtaining section; and a determining section that determines that the motor is in an overheated state when the subtracted integrated value obtained by the calculating section reaches a predetermined value.

1. Field of the Invention
The present invention relates to apparatuses for determining motor overheating, methods for determining motor overheating, computer-readable media, motor control apparatuses, motor control methods, and printing apparatuses.
2. Description of the Related Art
Various types of motors are installed in printing apparatuses such as inkjet printers, including carry motors for carrying media such as paper to be printed and motors for moving printing sections which are for printing on media such as paper. When these motors are driven continuously, they may sometimes rise in temperature due to generation of heat and go into a high temperature condition. Since there is a risk of faults such as coil burnout when the motor is in a high temperature condition, printing apparatuses are provided with monitoring devices to ensure that the motor does not go into a high temperature condition.
One such monitoring device (see JP 2002-186285A) is a device that monitors the motor temperature based on the amount of drive of the motor. This device successively adds the amount of drive of the motor and examines whether or not the motor is in a high temperature condition by checking whether or not the integrated value has reached a predetermined value. In other words, the temperature of the motor is inferred from the amount of drive of the motor by focusing on the relationship between the amount of drive of the motor and the heat produced by the motor. A determination is made that the motor is in a high temperature condition when the integrated value of the amount of drive of the motor reaches the predetermined value, and a transition is made to heat restriction control to restrict motor heating by suppressing motor drive. By transitioning to this control, driving of the motor is continued while preventing the temperature of the motor from rising further. It should be noted that it is proposed that when the motor has not been driven for a short while, the integrated value of the amount of drive of the motor should be gradually reduced, and when the motor has not been driven for a long time, the integrated value of the amount of drive of the motor should be reset to zero.
By monitoring the motor temperature condition based on the amount of drive of the motor, it is possible to obviate various sensors such as temperature sensors so that it is possible to achieve monitoring without increasing the number of components and without incurring much cost.
However, devices that monitor motor temperature conditions based on the amount of drive of the motor have the following problems. That is, the integrated value is reduced corresponding to the motor temperature condition by, for example, gradually reducing the amount of drive of the motor when the motor has not been driven for a short while, or by resetting the integrated value of the amount of drive of the motor to zero when the motor has not been driven for a long time. However, there has been no measure in place for when the motor is stopped for an extremely short time, for example, when the drive of the motor is stopped for an extremely short period of around one second, such as several tens to several hundreds of milliseconds. For this reason, sometimes the motor is judged to be in a high temperature condition and heat restriction control is activated despite the motor not being in a high temperature condition. This has sometimes caused problems of extra time being required for printing and printing speeds being reduced.

Apparatus for determining overheating of motor, method for determining overheating of motor, computer-readable medium, motor control apparatus, motor control method, and printing apparatus


An optical device includes: a focusing optic that focuses a light beam in a focal plane; at least two phase filters for selectively focusing the light beam and effecting a phase shift of the light beam; and a filter wheel supporting the at least two phase filters which are individually introducible along an optical axis of the light beam, where the filter wheel is rotationally adjusted in relation to the optical axis by a stepper motor and linearly adjusted in an r-direction along a plane of the filter wheel by a linear adjustment mechanism.

The invention relates to an optical device with a focusing optic which focuses a minimum of one light beam in a focal plane, and a phase filter to form the focus of the light beam such that the phase filter effects a phase shift of the light beam.
The invention further relates to a scanning microscope with a focusing optic which focuses a light beam in a focal plane, and with a phase filter to form the focus of the light beam such that the phase filter effects a phase shift of the light beam.
In scanning microscopy, a sample is illuminated with a light beam for the purpose of observing the reflected or fluorescent light emitted by the sample. The focus of the illumination light beam is moved in an object plane with the help of a controllable beam deflection device (scanning device), generally by tilting two minors, with the deflection axes usually positioned perpendicular to each other so that one minor deflects in the x-direction and the other in the y-direction.
A confocal scanning microscope generally comprises a light source, a focusing optic with which the light from the source is focused on a pinhole aperture, a beam splitter, a beam deflector to control the beam, a microscope optic, a detection aperture, and detectors to detect the detection light or fluorescent light. The illumination light is coupled via a beam splitter. The fluorescent light or reflection light coming from the object returns to the beam splitter via the beam deflector, traverses this, and is subsequently focused on the detection aperture, behind which are located the detectors. Detection light that does not originate directly from the focal plane takes another light path and does not pass through the detection apertures so that one obtains point information by which a three-dimensional image is constructed by sequential scanning of the object. In most cases, a three-dimensional image is achieved fromdatafrom layered imaging.
The resolution of a confocal scanning microscope is, among other things, dependent on the intensity distribution and the spatial spread of the focus of the excitation light beam. One possibility for increasing the resolution is provided by STED (Stimulated Emission Depletion) microscopy as it was developed by Prof. Stefan Hell. Here, the lateral edge regions of the focus volume of the excitation light beam are illuminated with a light beam of another wavelength, the so-called stimulation light beam or by the de-excitation light beam, which is preferably emitted by a second laser, in order, stimulated there by the sample regions excited by the first laser (i.e., the fluorescent molecules located there), to be brought back to the ground state. Only the spontaneously emitted light from the regions not illuminated by the second laser are detected so that an overall improvement in resolution is achieved.
It has been demonstrated that it is possible to achieve an improvement in resolution both laterally and axially if the focus of the stimulation light beam can ideally be formed on the inside as a zero position, namely in all three spatial directions. Visually, this means that a hollow sphere is formed in the inside of the intensity profile of the stimulation light beam in which the intensity of the stimulation light beam is zero, i.e., no beam is present. The form of the stimulation focus results from the Fourier transforms of the phase filter function. A number of different phase filters are known. For example, there is the so-called vortex phase filter or axial phase filter as, for example, described in Appl. Phys. Lett., Vol. 82, No. 18, 5 May 2003, 3125-3127. Using an axial phase filter, the light that traverses the central part of the plate is delayed by half a wavelength opposite the edge region of the plate. In the process, the portion of the light that traverses the central region must be the same as the portion that traverses the edge region. This leads by means of interference effects to an extinguishing of the light beam in the central region. In practice, it is often not possible to achieve a very great improvement in resolution in both the lateral and in the axial direction equally because the ideal hollow sphere depicted is difficult to produce. Therefore, the decision is often made for an arrangement by which high resolution may be achieved either in the lateral or in the axial direction, depending on the particular application.
In addition, different wavelengths for the excitation and de-excitation light must be used for different fluorescent dyes. However, the known phase filters have a disadvantage in that they precisely implement only one phase shift which leads to the desired intensity distribution in the focus for only one particular light wavelength. They are therefore generally applicable for only a narrow wavelength band of approximately 60 nm around the central wavelength. This is, however, a great disadvantage because fluorescent dyes occur in a broad range of wavelengths, and various fluorescent dyes are used for certain biological applications. Then, however, because the phase filters are not attuned to this fluorescent dye, only poorer resolution is achievable.


A device for abrading and finishing excess cured filler material from a bullnose outside cornerbead connected between immediately adjacent sheets of drywall. The device includes an elongated rigid body having a generally concave-shaped central longitudinal portion which preferably replaceably receives a sheet of somewhat compressible open fibrous adhesive material which is preferably substantially coextensive with, and arcuately formed to match the bullnose cornerbead convex contour, by the central longitudinal portion. In the preferred embodiment, a guide rail extends along either longitudinal margin of the central longitudinal portion which, in cooperation with the abrasive layer mateingly engaged against the bullnose cornerbead, substantially match the outside angle between the adjacent drywall sheets.

1. Scope of Invention
This invention relates generally to devices for sanding and finishing drywall installations, and more particularly to a device for cleaning and finishing outside bullnose joints between adjacent sheets of drywall.
2. Prior Art
There are a number of prior art devices used for finishing drywall installation corners and surfaces. Some of these devices known to applicants are directed to the application of cementious drywall filler compound, the majority of these devices however are directed to the sanding, scraping or finishing of the cured drywall compound prior to painting or wallpapering the finished drywall surfaces.
The following U.S. patents are known to applicant which generally fit into this category of prior art devices:
______________________________________ U.S. Pat. No. 5,544,384 Forselius, et al. U.S. Pat. No. 3,878,581 Perna U.S. Pat. No. 5,545,287 Carlson U.S. Pat. No. 4,907,955 Snipes U.S. Pat. No. 4,948,360 Brown U.S. Pat. No. 5,069,610 Milburn U.S. Pat. No. 4,619,013 Yon U.S. Pat. No. 4,230,441 Heronema U.S. Pat. No. 5,368,461 Murphy ______________________________________
All of these above prior art devices are either adapted to fill or finish flat drywall surfaces or inside or outside drywall joint areas which have sharp or crisp inside or outside corners.
A recently introduced feature for drywall outside corner joints is typically referred to as a "bullnose" cornerbead or joint. Those outside cornerbeads are formed of elongated metal strips which define an arcuate or radiused quarter circle cylindrical surface when attached to the adjacent edges of drywall panels. Applicants are not yet aware of an effective means for cleaning and sanding excess drywall filler compound from these bullnose corners without significantly abrading the immediately adjacent cured drywall filler compound.
However, the invention disclosed in U.S. Pat. No. 5,638,570 invented by Gruner teaches a drywall bullnose cleaner tool which scrapes excess filler compound from the radiused surfaces of an outside bullnose corner joint of such a drywall installation. However, scraping action may not be best suited for optimal smooth finishing of the bullnose corner. Another device for the scraping, cleaning and finishing of bullnose joints is disclosed by Stoltzfus in U.S. Pat. No. 5,392,484. Again, the scraping of the cylindrical bullnose surface is not fully effective in producing a smooth, high quality finished surface ready for painting.
The present invention teaches a cleaning and finishing device for bullnose cornerbeads or joints which more gently and uniformly abrades away excess cured or hardened drywall filler compound without concern for overly abrading and grooving the drywall filler compound immediately adjacent the edge of the metal bullnose joint. Further, by including a somewhat resilient or compliant abrasive fibrous pad which accomplishes the cleaning and finishing action, any non-uniformity of the bullnose joint is easily accommodated.

Sanding and cleaning device for drywall bullnose cornerbeads


An image forming apparatus for outputting an image through an electrophotographic process in accordance with a digital image signal includes an electrophotographic photosensitive member; an optical system for applying light information to the photosensitive member; a developing device for forming a toner image on the photosensitive member; an input path for a plurality of digital image signals containing a bi-level digital image signal and a multi-level digital image signal; a controller for changing developing condition of the developing device when the image is outputted in accordance with the bi-level digital image signal, and changing an image forming condition which is different from the developing condition when an image is outputted in accordance with a multi-level digital image signal.

The present invention relates to an image forming apparatus for outputting images in accordance with digital image signals through an electrophotographic process. Examples of such an apparatus include a digital printer and a digital copying machine or the like.
There are conventional image forming apparatuses for forming visualized images corresponding to digital image signals bearing density information for pixels.
A laser beam printer or the like is widely used, in which a laser beam emitted in accordance with the image signal scans a surface of an image bearing member such an an electrophotographic photosensitive member or the like having been uniformly charged by charging means so that an electrostatic latent image is formed on the surface of the image bearing member, and the electrostatic latent image is developed into a toner image, which in turn is transferred onto a transfer material by transfer means and then is fixed on a transfer material by fixing means. As a developing means for this use, there is a developing device in which a developer carrying member supplied with a bias voltage having at least a DC voltage component, is faced to the image bearing member, by which the electrostatic latent image is developed into a toner image on the surface of the image bearing member.
In an image forming apparatus for visualizing a digital image signal, it would be considered that there are provided a plurality of input paths, and one path is selected therefrom, and the image forming operation is carried out in accordance with the image signal supplied through the selected input path. The digital image signals are classified into the following two groups. The first is bi-level digital image signals for reproducing dots, lines and two dimensional solid images, such as image signals for documents or the like generated by image signal generating means such as a computer. The second is a multi-level digital image signal which alqo bears tone level (density level) in addition to the shape of the image, such as an image signal read from an original or the like by image reading means using CCD or the like.
In the case of the above-described first type signal, the laser beam printer or the like simply turns on and off the laser beam, since what is required is only to reproduce the shape of the image. In this case, that is, the bi-level image signal, it is desirable that the output is such that the size of one pixel is larger than the theoretical size of one pixel by 10-30% approximately, since then the dot and the line corresponding to one or two pixels approximately, are easily recognized by human eyes. Heretofore, it has been proposed that the size of the one pixel is reproduced to be larger by increasing the developing contrast of the developing means. FIG. 4 shows an example of a relationship between the development contrast and the width of a line of one dot width. A printer which visualizes the bi-level image signal requires means for changing the output property so as to change the thickening of the line width. For this purpose the developing bias voltage is adjusted so as to provide a thin line (larger than the theoretical value by 10%), normal line (20%), or thick line (30%).
In the case of the second type signal for visualizing multi-level image signals, a copying machine type laser beam printer is required to reproduce the tone levels in addition to the shape of the image. To accomplish this, as indicated by a line 2 in FIG. 7, it produces an output bearing information indicative of the density of the image which is linear with respect to the signal level supplied for respective pixel. The relationship between the input signal and the output signal when the laser beam emits the quantities of light proportional to the multi-levels for each pixel (without xcex3 conversion), is determined by the developing property of the developing means and the photosensitive property of the image bearing member. The relation without the xcex3 conversion is not rectilinear in the case of the image bearing members and developing means having been used. FIG. 6 shows an example of the relation without the xcex3 conversion. In the prior art, in order to convert this relation to a rectilinear output-density property, the multi-level image signal supplied to the printer is subjected to a xcex3 conversion process so that the laser is actuated such that the quantity of light for each pixel is proportional to the signal level of the multi-level signal after the xcex3 conversion. This means is widely used.
In the printer or the like which visualizes the multi-level image signals, means for changing the output property in accordance with the state of the original, is required. More particularly, the xcex3 conversion process is changed so that only the background fog is reduced when the original is of the nature tending to produce the background fog, and such that the density is increased when the image density of the original is generally low, in order to provide the output property indicated by lines 1 and 3 in FIG. 7.
The following defects are predicted when there are provided two digital image signal input paths (bi-level and multi-level), one path is automatically or manually selected from the paths, and the image is formed in response to the image signals supplied through the selected input path. When a means for changing the developing contrast is used as a means for changing the image output property, the property of the output image of the multi-level image signal does not change as shown in FIG. 7. In addition, in case of the image produced in response to the multi-level signal or the like, the size of one pixel changes with the result of reduction of the tone gradation in the case of halftone dot image. On the other hand, means for changing the xcex3 conversion process is used to change the image output property, an area of a black portion can not be changed in an image formed by a combination of only white and black dots, line and solid images using bi-level image signals, because the xcex3 conversion is for the multi-level signal. These problems are found when an attempt is made to adjust the image quality when an image is outputted after development of an electrostatic latent image formed in accordance with bi-level and multi-level digital image signals. It is considered that this results from a difference in the electrostatic latent images formed by the bi-level and multi-level signals.
Accordingly, it is a principal object of the present invention to provide a solution to the problem arising when one image forming apparatus processes bi-level and multi-level image signals.
It is another object of the present invention to provide an image forming apparatus and method in which sufficient image quality adjustment is enabled for the bi-level and multi-level image signals.
It is a further object of the present invention to provide an image forming apparatus and method in which the operativity is improved in the image quality adjustment at the time of the image formation by the bi-level and multi-level image signals.
According to an aspect of the present invention, there is provided an image forming apparatus for outputting an image through an electrophotographic process in accordance with a digital image signal, comprising: an electrophotographic photosensitive member; optical means for applying light information to the photosensitive member; developing means for forming a toner image on the photosensitive member; an input path for a plurality of digital image signals containing a bi-level digital image signal and a multi-level digital image signal; control means for changing developing condition of the developing means when the image is outputted in accordance with the bi-level digital image signal, and changing an image forming condition which is different from the developing condition when an image is outputted in accordance with a multi-level digital image signal.
These and other objects, features and advantages of the present invention will become more apparent upon a consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings.

Image forming apparatus for outputting image in response to digital image signal


The present invention provides antibodies, or antigen binding fragments thereof, that bind to human TIGIT (T cell immunoreceptor with Ig and ITIM domains), as well as uses of these antibodies or fragments in therapeutic applications, such as in the treatment of cancer or chronic viral infection. Such method of treatment include combination therapy with inhibitors of other immunomodulatory receptor interactions, such as the PD-1/PD-L1 interaction. The invention further provides polynucleotides encoding the heavy and/or light chain variable region of the antibodies, expression vectors comprising the polynucleotides encoding the heavy and/or light chain variable region of the antibodies, cells comprising the vectors, and methods of making the antibodies or fragments by expressing them from the cells.

TIGIT (T cell immunoreceptor with Ig and ITIM domains) is a co-inhibitory receptor protein also known as WUCAM, Vstm3 or Vsig9. TIGIT was discovered in genomic searches for proteins specifically expressed on T cells, and has an immunoglobulin variable domain, a transmembrane domain, and an immunoreceptor tyrosine-based inhibitory motif (ITIM), and contains signature sequence elements of the PVR protein family. It is known to interact with poliovirus receptor (PVR; CD155) and with nectin2 (CD112). See e.g. Stengel et al. (2012) Proc. Nat'l Acad. Sci. (USA) 19:5399; WO 2006/124667; WO 2009/126688. Although PVR may interact with the co-activating receptor DNAM-1 (CD226) to enhance tumor killing, the high affinity TIGIT/PVR interaction would inhibit such killing, and may act to prevent killing of normal (self) cells that also express PVR. Stanietsky et al. (2009) Proc. Nat'l Acad. Sci. (USA) 106:17858. The dominance of this inhibitory interaction may be important in suppression of anti-self immune reactions, but in the tumor context it suppresses tumor eradication. Id.
TIGIT suppresses T cell activation by promoting the generation of mature immunoregulatory dendritic cells. Yu et al. (2009) Nat. Immunol. 10:48. TIGIT and other such co-inhibitory molecules (e.g. CTLA-4, PD-1, Lag3 and BTLA) may play a role in evasion of immunosurveillance by tumor cells. Experiments have shown that PVR/CD155 is over-expressed on melanoma cells (Inozume et al. (2014) J. Invest. Dermatol. 134:S121—Abstract 693) and various other tumors. It is possible that the TIGIT/PVR interaction can shield such tumor cells from immune-mediated eradication by inhibiting anti-tumor responses of T and NK cells. Stanietsky et al. (2009) Proc. Nat'l Acad. Sci. (USA) 106:17858 and Lozano et al. (2012) J. Immunol. 188:3869. Other experiments have identified a TIGIT+ subset of regulatory T cells (Tregs) that selectively suppress Th1 and Th17 responses (Joller et al. (2014) Immunity 40:569), suggesting an alternative mechanism by which an anti-TIGIT antibody may enhance anti-tumor immune response.
TIGIT may act to "turn off" the immune response similarly to other co-inhibitory receptors such as CTLA-4, PD-1 and BTLA. Id. Antibodies targeting CTLA-4 (ipilimumab) and PD-1 (nivolumab, pembrolizumab) have been approved for the treatment of human cancers, validating this therapeutic approach. Antibodies that bind to human TIGIT might also find use in treatment of cancers. See e.g. WO 2006/124667. In mouse models, antibody blockade of both PD-L1 and TIGIT leads to a synergistic enhancement of CD8+ T cell mediated tumor rejection. Grogan et al. (2014) J. Immunol. 192(1) Suppl. 203.15; Johnston et al. (2014) Cancer Cell 26:1-15. Similar results have been obtained in animal models of melanoma. Inozume et al. (2014) J. Invest. Dermatol. 134:S121—Abstract 693. Some experiments suggest that TIGIT blockade is effective to enhance anti-tumor CD8+ T cell response only in the presence of the co-activating receptor DNAM-1/CD226, which competes with TIGIT for binding to PVR/CD155. Johnston et al. (2014) Cancer Cell 26:1-15.
Recent experiments have demonstrated that intratumoral bacteria expressing Fap2 protein may inhibit NK cell mediated tumor killing by binding to TIGIT (Gur et al. (2015) Immunity 42:344), suggesting that eliminating such bacteria, blocking the interaction of TIGIT with Fap2, or blocking the activity of TIGIT generally, may be useful in treatment of cancer, e.g. colorectal cancer. Hampton (2015) JAMA 313:1305.
The need exists for improved methods of treating cancer and chronic viral infections and medicaments, such as therapeutic monoclonal antibodies, for use in the methods. Medicines for use in such improved methods of treatment may comprise antibodies or antibody fragments that specifically bind to TIGIT and reverse or partially reverse the TIGIT-mediated suppression of anti-tumor or anti-viral immune responses.


A semiconductor memory device includes a memory cell array including a plurality of memory cell array blocks, a plurality of pairs of first data lines for transceiving data with corresponding memory cell array blocks, a plurality of column selection signal lines disposed in an orthogonal direction to the pairs of first data lines, and a plurality of pairs of second data lines to transceive data with corresponding pairs of first data lines of the pairs of first data lines. The memory cell array includes a signal interference compensator that shifts a voltage level of a second data line signal of one of the pair of second data lines interfered by a column selection signal line, to a voltage level of a first data line signal of other of the pair of second data lines not interfered so as to compensate for a signal interference.

1. Technical Field
The present disclosure relates to a semiconductor memory device and, more particularly, to a method of compensating for signal interference of the semiconductor memory device.
2. Discussion of the Related Art
In order to realize high-capacity high-speed semiconductor memory devices, pairs of local data input/output lines are disposed as data input/output lines, and column selection signal lines and pairs of global data input/output lines are disposed in a direction orthogonal to the pairs of local data input/output lines.
However, as the integration density of semiconductor memory devices increases, signal intensity decreases and the number of signal lines increases. Thus, it is necessary to dispose a greater number of signal lines and circuits in limited areas of the semiconductor devices so as to minimize the load of signal lines.
In a conventional semiconductor memory device, when a signal is applied to a column selection signal line to read data from a memory cell, data is transmitted via a pair of global data input/output lines to a global data input/output multiplexer in response to the applied signal.
The column selection signal line is a full-swing signal line that transitions from a power supply voltage to a ground voltage, and the pair of global data input/output lines are a pair of small-swing signal lines that transition from a precharge level to a complementary level. When the column selection signal line is in a full swing, the pair of global data input/output lines are affected by interference due to coupling capacitances between the column selection signal line and the pair of global data input/output lines.
That is, when a signal is applied to a column selection signal line disposed adjacent to the pair of global data input/output lines, interference occurs at the pair of small-swing global data input/output lines so that a signal applied to the pair of small-swing global data input/output lines is delayed, as compared to when no interference occurs, before it is transmitted to the global data input/output multiplexer.
As a result, a data read speed of the entire semiconductor memory device is degraded. Furthermore, with the development of high-capacity semiconductor memory devices, the length of the pair of global data input/output lines continues to increase, further degrading the data read speed and affecting the performance of the entire semiconductor memory device.
Various methods have been proposed to address the above issues. For example, a signal line for transmitting global input/output data signals with very low intensity may be shielded using power lines to avoid coupling with other signal lines. Alternatively, interference caused by a column selection signal line may be reduced by half using a pair of twisted global data input/output lines GI01-GI0B, as shown in FIG. 1.
FIG. 1 is a block diagram of a conventional semiconductor memory device using a pair of twisted global data input/output lines.
Referring to FIG. 1, the semiconductor memory device includes four memory cell array blocks BL1 to BL4, a plurality of local data input/output lines (LIO1, LIO1B) to (LIO4, LIO4B), a word line WL, a plurality of column selection signal lines CSL1 to CSLn, a plurality of global data input/output lines (GIO1, GIO1B), (GIO2, GIO2B), . . . , and a column address decoder 10.
An upper left memory array region of the semiconductor memory device including the memory cell array blocks BL1 to BL4, the local data input/output lines (LIO1, LIO1B) to (LIO4, LIO4B), the column selection signal lines CSL1 to CSLn, and the global data input/output lines (GIO1, GIO1B), (GIO2, GIO2B), . . . will be described. A memory cell MC, a bit line sense amplifier BLSA, and a column selection circuit 20 are connected between the word line WL and a pair of bit lines BLP1. A local input/output sense amplifier Local IOSA is disposed at an intersection point between the pair of local data input/output lines LIO1 and LIO1B and the pair of global data input/output lines GIO1 and GIO1B. Also, an input/output sense amplifier IOSA and a global input/output multiplexer GIOMUX are connected between the pair of global data input/output lines GIO1 and GIO1B.
As can be seen from FIG. 1, the word line WL and the plurality of column selection signal lines CSL1 to CSLn are adjacently arranged in the same direction as, or in an orthogonal direction to, the plurality of local data input/output lines (LIO1, LIO1B) to (LIO4, LIO4B), and the plurality of global data input/output lines (GIO1, GIO1B), (GIO2, GIO2B), . . . are twisted pairs.
Functions of respective blocks of the conventional semiconductor memory device will now be described with reference to FIG. 1.
A memory cell MC receives a signal of the word line WL, which is enabled in response to a row address, and outputs written/stored data to a pair of bit lines BL and BLB.
The bit line sense amplifier BLSA receives charges stored in a capacitor of the memory cell MC via the pair of bit lines BL and BLB and amplifies a voltage corresponding to the charges.
The column address decoder 10 receives a column address CA, decodes the column address CA, and enables one of a plurality of column selection signals CSL1, CSL2, . . . , and CSLn of the four memory cell array blocks BL1 to BL4.
The column selection circuit 20 is composed of two NMOS transistors N1 and N2 each having one terminal to which a pair of output signals LIO and LIOB of the bit line sense amplifier BLSA are applied, respectively, and gate terminals to which the column selection signal CSL1 is applied. The column selection circuit 20 externally receives a column address along with a read command, turns on the NMOS transistors N1 and N2 in response to the enabled column selection signal CSL1, and transmits data signals of the pair of sensed bit lines BL and BLB to the pair of local input/output lines LIO and LIOB.
The local input/output sense amplifier Local IOSA receives data of the transmitted bit line signals BL and BLB, amplifies a voltage difference between the bit line signals BL and BLB, and outputs an amplified signal, thereby preventing an operating speed from being degraded due to a load mismatch between the pair of local input/output lines LIO and LIOB having a small load, and the pair of global input/output lines GIO and GIOB having a large load.
The global data input/output multiplexer GIOMUX receives the amplified signal from the local input/output sense amplifier Local IOSA through the global input/output lines GIO and GIOB, converts N-bit parallel data of the pair of global input/output lines GIO and GIOB into M serial data, and outputs the converted data.
The input/output sense amplifier IOSA receives the converted serial data of the global input/output lines GIO and GIOB, amplifies a voltage difference between the received data, and outputs an amplified signal.
FIG. 2 is a circuit diagram for modeling a coupling capacitance between a column selection signal line (CSL1) and a pair of global data input/output lines (GI01, GI01B) in the conventional semiconductor memory device shown in FIG. 1.
The column selection signal line CSL1 and the pair of global data input/output lines GIO1 and GIOB1 are divided into three portions. A coupling capacitance between the column selection signal line CSL1 and the global data input/output line GIO1 includes capacitances CA1, CB3, CC1, and CD3. A coupling capacitance between the pair of global data input/output lines GIO1 and GIO1B includes capacitances CA2, CB2, CC2, and CD2. Also, a coupling capacitance between the column selection signal line CSL1 and the global data input/output line bar GIO1B includes capacitances CA3, CB1, CC3, and CD1.
During the enabling and disabling of the column selection signal line CSL1, the sum (CA1+CC1) of the coupling capacitances between the column selection signal line CSL1 and the global data input/output line GIO1 affects the global data input/output line GIO1 causing a voltage variation in the global data input/output line GIO1. Also, the sum (CB1+CD1) of the coupling capacitances between the column selection signal line CSL1 and the global data input/output line bar GIO1B affects the global data input/output line bar GIO1B causing a voltage variation in the global data input/output line bar GIO1B.
Accordingly, the voltage variations in the pair of twisted global data input/output lines GIO1 and GIO1B caused by a voltage variation in the column selection signal line CSL1 are reduced compared to when a pair of global data input/output lines GIO1 and GIO1 are not twisted.
For example, assuming that each of the coupling capacitances CA1, CB1, CC1, and CD1 is equal to a capacitance C, in the conventional semiconductor memory device including the pair of untwisted global data input/output lines GIO1 and GIO1B, a voltage of the global data input/output line GIO1 is largely affected by a voltage variation in the column selection signal line CSL1 due to a coupling capacitance 4C between the column selection signal line CSL1 and the global data input/output line GIO1. In contrast, in the semiconductor memory device shown in FIG. 1, the coupling capacitance between the column selection signal line CSL1 and the global data input/output line GIO1, and the coupling capacitance between the column selection signal line CSL2 and the global data input/output line GIO1B, is reduced to a capacitance 2C, thereby reducing a voltage variation in the pair of global data input/output lines GIO1 and GIO1B caused by a voltage variation in the column selection signal line CSL1. FIG. 3 is a timing diagram illustrating the operation of a memory cell array block BL1 of the conventional semiconductor memory device shown in FIG. 1.
The operation of the memory cell array block BL1 is affected by the input and output of a row address strobe signal RASB, a column address strobe signal CASB, an address signal ADD, a write enable signal WEB, a word line enable signal WL, a precharge signal PRE, a first column selection signal CSL1, a second column selection signal CSL2, a pair of bit line signals BLP1, a pair of local data input/output line signals LIO1 and LIO1B, and a pair of global data input/output line signals GIO1 and GIO1B.
In FIG. 3, assuming that a high-level inverted write enable signal WEB is applied to read low-level data from the pair of bit lines BLP1, when a low-level row address strobe signal RASB is applied, the address signal ADD loads a row address X, and when a low-level column address strobe signal CASB is applied, the address signal ADD loads a column address Y1.
The row address X is decoded to generate a high-level word line enable signal WL, and the column address Y1 is decoded to generate a high-level column selection signal CSL1.
Also, when a high-level precharge signal PRE is generated before the high-level word line enable signal WL is generated, the pair of bit lines BLP1, the pair of local data input/output lines LIO1 and LIO1B, and the pair of global data input/output lines GIO1 and GIO1B are precharged in response to the high-level precharge signal PRE.
When the high-level word line enable signal WL is generated, a voltage difference between data signals transmitted to the pair of bit lines BLP1 develops, and the bit line sense amplifier BLSA amplifies the voltage difference between the data signals transmitted to the pair of bit lines BLP1 to a complementary level.
When the high-level column selection signal CSL1 is generated, the data signals of the pair of bit lines BLP1 are respectively transmitted to the pair of local data input/output lines LIO1 and LIO1B, transmitted to the pairs of global data input/output lines GIO1 and GIO1B, and amplified by the input/output sense amplifier IOSA.
Meanwhile, after a predetermined time elapses, when the column address strobe signal CASB returns to a low level and the address signal ADD loads a column address Y2, the column address decoder 10 decodes the column address Y2 and generates a high-level second column selection signal CSL2.
Thus, when the first column selection signal CSL1 is enabled to a high level, a voltage difference between data signals transmitted to the pair of bit lines BLP1 develops so that the bit line sense amplifier BLSA amplifies the voltage difference between the data signals transmitted to the pair of bit lines BLP1 to a complementary level, and the data signals of the pair of bit lines BLP1 are respectively transmitted to the pair of local data input/output lines LIO1 and LIO1B and the pair of global data input/output lines GIO1 and GIO1B, and amplified by the input/output sense amplifier IOSA.
However, since the global data input/output line bar signal GIO1B is being interfered by the second column selection signal CSL2, the phases of the pair of global data input/output line signals GIO1 and GIO1B are opposite to the phases of the pair of global data input/output line signals GIO1 and GIO1B generated when the global data input/output line signal GIO1 is being interfered by the first column selection signal CSL1.
When the voltage difference between the data signals transmitted to the pair of global data input/output lines GIO1 and GIO1B is produced, the input/output sense amplifier IOSA senses and amplifies the voltage difference between the data signals transmitted to the pair of global data input/output lines GIO1 and GIO1B. Therefore, because the moment when the voltage difference between the data signals transmitted to the pair of global data input/output lines GIO1 and GIO1B is earlier, a read access time becomes shorter.
However, in the conventional semiconductor memory device, when the twisted pair of global data input/output lines GIO1 and GIO1B is disposed adjacent to the column selection signal line CSL1, a coupling capacitance exists between the twisted pair of global data input/output lines GIO1 and GIO1B as shown in FIG. 2. Thus, the coupling capacitance between the twisted pair of global data input/output lines GIO1 and GIO1B affects the data signals transmitted thereto.
In other words, during the enabling and disabling of the column selection signal line CSL1, a voltage of the twisted pair of global data input/output lines GIO1 and GIO1B is affected by a small capacitance and instantaneously rises or drops to a voltage that is lower by ΔV1 than in the conventional semiconductor memory device including the pair of untwisted global data input/output lines GIO1 and GIO1B.
Thus, because the moment when the voltage difference between the data signals transmitted to the pair of global data input/output lines GIO1 and GIO1B is produced is earlier by ΔT1 than in the conventional semiconductor memory device, including the pair of untwisted global data input/output lines GIO1 and GIO1B, a read data access time is improved.
However, since the conventional semiconductor memory device shown in FIG. 1 includes the twisted pair of global data input/output lines GIO1 and GIO1B, layers of the pair of global data input/output lines GIO1 and GIO1B need to be changed using contacts (e.g., vias). As a result, transmitted signals are delayed due to proper resistance elements, and the pair of global data input/output lines GIO1 and GIO1B is highly likely to be positionally deviated during a semiconductor fabrication process.
Furthermore, since data written to or read from the actual memory cell MC is transmitted through the pair of global data input/output lines GIO1 and GIO1B, when the pair of global data input/output lines GIO1 and GIO1B is positionally deviated, not only data read performance but also data write performance may be degraded, and data encoding must be reversed at portions where the pair of global data input/output lines GIO1 and GIO1B are twisted, thereby complicating circuit design.

Semiconductor memory device and method of compensating for signal interference thereof


An apparatus for reducing unwanted brake noise has a ring damper affixed around a periphery of a brake rotor in a disk brake system in a manner that permits relative motion and slippage between the ring damper and the rotor when the rotor vibrates during braking. In a preferred embodiment, the ring damper is disposed in a groove formed in the periphery of the disk and is pre-loaded against the rotor both radially and transversely. The ring damper is held in place by the groove itself and by the interference pre-load or pre-tension between the ring damper and the disk brake rotor.

Disk brakes are commonly used in automobiles, trucks, buses, off-road and construction vehicles, aircraft, and light rail vehicles. In the disk brake type of braking system, a disk or rotor turns with the vehicle's wheel. When the brakes are applied, stationary (i.e., non-rotating) brake pads are pressed against the rotor under high hydraulic pressure by a brake caliper. The frictional forces between the brake pads and the rotor bring the vehicle wheel to a stop.
A common problem associated with brake systems is that unwanted noise and vibration are often generated during the braking process. This unwanted noise is a frequently recurring problem that causes numerous customer complaints and significant warranty expenditures on the part of motor vehicle manufacturers.
It is an object of this invention to reduce brake noise.
It is a further object of this invention to reduce unwanted brake noise by the use of a simple damping arrangement that minimizes the amount of additional forming operations required in the manufacture of the brake system.
It is another object of this invention to provide a ventilated disk brake rotor with improved vibration and noise damping characteristics.
It is another object of this invention to provide a disk brake rotor with noise and vibration damping members that are cooled along with the disk brake rotor.