A shift register minimizing bias stress applied to transistors is disclosed. A shift register including n stages outputting scan pluses that are sequentially delayed in a forward or reverse direction thereof, where n is positive integer and wherein each stage includes: a scan direction controller that provides a first or second voltage to a scan direction control node according to a first or second enable signal and controlling the forward or reverse direction output; a first node controller that controls a first node according to a voltage on the scan direction control node; a second node controller that controls a second node according to the voltage on the scan direction control node and a voltage on the first node; an output unit that outputs a clock signal as scan pulse according to voltages on the first and second nodes; a third node controller that provides one of the first and second voltages to a third node according to the first and second enable signals; a first discharge circuit unit that discharges the voltage on the first node according to voltages of the second and third nodes; and a second discharge circuit unit that discharges the voltage on the third node according to one of a third enable signal and a fourth enable signal.

1. Field of the Invention
The present invention relates to a shift register, and more particularly, to a shift register minimizing a bias stress applied to a switching element.
2. Discussion of the Related Art
Recently, various flat-panel display devices have appeared on the market to overcome the disadvantages of a cathode ray tube (CRT), such as, weight, volume, etc. Such flat-panel display devices include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), a light emitting display (LED), etc.
A conventional LCD displays images thereon as the light transmission of a liquid crystal layer is controlled using electric fields. To this end, the LCD includes an LCD panel in which liquid crystal (LC) cells are aligned in matrix form and a drive circuit for driving the LCD panel.
The LCD panel is configured such that gate lines and data lines cross. Liquid crystal (LC) cells are located in the crossings. More specifically, the LCD panel includes pixel electrodes and common electrodes to apply electric fields to the respective LC cells. The pixel electrodes are connected to the data lines via sources and drains of thin film transistors (TFT) that function as switching elements. The gates of the TFTs are connected to the gate lines.
The LCD panel is configured such that a plurality of gate lines and a plurality of data lines cross. The areas formed where the gate lines and the data lines cross define pixel areas. Also, the LCD panel has pixel electrodes and common electrodes to apply electric fields to the respective pixel areas.
On the other hand, the drive circuit includes a gate driver for driving the gate lines and a data driver for driving the data lines. The gate driver sequentially provides scan pulses to the gate lines such that the LC cells of the LCD panel may be sequentially operated a specific number of times per minute.
The data driver provides pixel voltage signals to the respective data lines each time when the scan pulse is provided to one of the gate lines.
Therefore, the LCD device displays images thereon as the light transmission of each LC cell is adjusted by electric fields that are applied to the pixel electrodes and the common electrodes in the LC cells, according to the pixel voltage signals.
The gate driver includes a shift register to sequentially output scan pulses as mentioned above. The data driver includes a shift register for outputting sampling signals to sample digital data. The shift registers may output scan pulses or sampling signals uni-directionally or bi-directionally.
FIG. 1 illustrates a conventional shift register including a plurality of stages.
With reference to FIG. 1, the conventional bi-directional shift register includes n stages, ST1-STn that are connected to first and second clock pulse providing lines, first and second voltage providing lines, a drive voltage providing line and a ground voltage providing line. Here, first voltage Vd1 and second voltage Vd2, which are provided to the first and second voltage providing lines, respectively, have opposite phases to one another according to a scan direction. The first and second clock signals CLK are provided to the first and the second clock pulse providing lines, respectively, while their phases are opposite to one another. The first clock pulse is provided to odd stages, and the second clock pulse is provided to even stages.
When the conventional bi-directional shift register operates in the forward direction, stages, ST1 to STn, are sequentially operated to output the scan pulses in the forward direction according to a first start pulse, at least two clock pulses, a first voltage Vd1 with a high level, and a second voltage Vd2 with a low level that are provided to the first stage and is not shown in FIG. 1. Here, stage ST2 to stage STn are enabled by output signals from previous and next stages, respectively.
On the other hand, when the conventional bi-directional shift register is operated in the reverse direction, stages, STn to ST1, are sequentially operated to output the scan pulses in a reverse direction according to a second start pulse, at least two clock pulses, a first voltage Vd1 with a low level, and a second voltage Vd2 with a high level that are provided to stage STn and is not shown in FIG. 1. Here, stage STn−1 to stage ST1 are enabled by output signals from previous and next stages, respectively.
FIG. 2 illustrates a detailed circuit of stage STi of the plurality of stages in the conventional shift register.
Referring to FIG. 2 along with FIG. 1, the stage STi include: a scan direction controller 10 for providing a first voltage Vd1 or a second voltage Vd2 to a scan direction control node QS according to first and second enable signals VOi−1 and VOi+1 to control forward or reverse direction output of a scan pulse; a first node controller 20 for controlling a first node Q1 according to a voltage of the scan direction control node QS; a second node controller 30 for controlling a second node Q2 according to a voltage of the scan direction control node QS and a voltage of the first node Q1; an output unit 50 for outputting input clock signals CLK as scan pulses according to voltages of the first and second nodes Q1 and Q2; a controller 40 of a third node Q3 for providing the first voltage Vd1 or the second voltage Vd2 to the third node Q3 according to the first and second enable signals VOi−1 and VOi+1; and a discharge circuit unit 60 for discharging the voltage of the first node Q1 according to the voltages of the second node Q2 and the third node Q3.
The scan direction controller 10 includes: a 1st transistor T1 that is electrically connected between a first drive voltage input line to which the first voltage Vd1 is input, and to the scan direction control node QS; and a 2nd transistor T2 that is electrically connected between a second drive voltage input line to which the second voltage Vd2 is input, and the scan direction control node QS. Here, the 1st transistor T1 is controlled by the first enable signal VOi−1 that is an output signal output from the stage STi−1, and the 2nd transistor T2 is controlled by the second enable signal VOi+1 that is an output signal output from stage STi+1.
The first node controller 20 includes a 3rd transistor T3 that is electrically connected between a drive voltage input line to which a drive voltage Vdd is input, and the first node Q1. The 3rd transistor T3 is controlled by the voltage of the scan direction control node QS.
The second node controller 30 includes: a 4th transistor T4 forming a diode circuit that is connected to the drive voltage input line, in which the 4th transistor T4 is controlled by the drive voltage Vdd; a 5th transistor T5 connected between the drive voltage input line and the second node Q2, in which the 5th transistor T5 is controlled by the drive voltage Vdd via the 4th transistor T4; a 6th transistor T6 connected between the drive voltage input line via 4th transistor T4 and the ground voltage input line to which the ground voltage Vss is provided, in which the 6th transistor T6 is controlled by the voltage of the first node Q1; a 7th transistor T7 connected between the second node Q2 and the ground voltage input line, in which the 7th transistor T7 is controlled by the voltage of the first node Q1; and an 8th transistor T8 connected between the ground voltage input line and the second node Q2, in which the 8th transistor T8 is controlled by the voltage of the scan direction control node QS.
The discharge circuit unit 60 includes: a 9th transistor T9 connected between the ground voltage input line and the first node Q1, in which the 9th transistor T9 is controlled by voltage of the third node Q3; and a 10th transistor T10 connected between the ground voltage input line and the first node Q1, in which the 10th transistor T10 is controlled by a voltage of the second node Q2.
The third node controller 40 includes: a 12th transistor T12 connected between the first voltage input line to which the first voltage Vd1 is provided, and the third node Q3; and a 13th transistor T13 connected between the second voltage input line to which the second voltage Vd2 is provided, and the third node Q3. Here, the 12th transistor T12 is controlled by the second enable signal VOi+1, and the 13th transistor T13 is controlled by the first enable signal VOi−1.
The out unit 50 includes: a 14th transistor T14 connected between the clock signal CLK1 input line and an output lead; and a 15th transistor T15 connected between the ground voltage input line and the output lead. Here, the 14th and 15th transistors are controlled by the voltages of the first node Q1 and the second node Q2, respectively.
On the other hand, the scan direction controller 10 may be configured to further include an 11th transistor T11 which is connected between the scan direction control node QS and the ground voltage input line, in which the 11th transistor T11 is controlled by the scan pulse output from the output unit 50.
FIG. 3 illustrates waveforms when the circuit of FIG. 2 is operated in the forward direction.
Referring to FIG. 3 along with FIG. 2, operation in the forward direction of the conventional bi-directional shift register will be described in detail as follows:
First, regarding the forward direction scan, the high first voltage Vd1 is provided to the first voltage input line, and the low second voltage Vd2 is provide to the second voltage input line, respectively.
During the interval t1, stage STi receives an first enable signal VOi−1 with a high level from stage STi−1, and a second enable signal VOi+1 with a low level from stage STi+1. Also, during the interval t1, a clock signal CLK with a low level is provided to the clock signal input line.
During the interval t1, the 1st transistor T1 of the scan direction controller 10 is turned on by the high first enable signal VOi−1, and the 2nd transistor T2 is turned off by the low second enable signal VOi+1. Therefore, the scan direction controller 10 provides the high first voltage Vd1 to the scan direction control node QS through the 1st transistor T1.
Here, the high first voltage Vd1 that is applied to the scan direction control node QS, turns on the 3rd transistor T3 of the first node controller 20 and the 8th transistor T8 of the second node controller 30, simultaneously.
The drive voltage Vdd is provided to the first node Q1 via the turned-on 3rd transistor T3. The 6th and 7th transistors T6 and T7 in the second node controller 30 are turned on by the drive voltage Vdd of the first node Q1. Also, as the drive voltage Vdd of the drive voltage input line is provided to the gate of the 5th transistor T5 via the 4th transistor T4, the 5th transistor T5 is turned on, such that the drive voltage Vdd is provided to the second node Q2. Therefore, the ground voltage Vss is provided to the second node Q2 through the 7th and 8th transistors T7 and T8, and, at the same time, the drive voltage Vdd is also provided to the second node Q2 via the 5th transistor T5. However, because the number of transistors providing the ground voltage Vss to the second node Q2 is greater than that of transistors providing the drive voltage Vdd, the second node Q2 is provided with the ground voltage Vss.
Also, during the interval t1, the third node controller 40 is operated such that the 13th transistor T13 is turned on by the high first enable signal VOi−1 to provide the low second voltage Vd2 to the third node Q3, thereby turning off the 9th transistor T9 of the discharge circuit 60. On the other hand, the 10th transistor T10 of the discharge circuit 60 is turned off by the ground voltage Vss of the second node Q2.
In addition, the 14th transistor T14 of the output unit 50 maintains its turned-on state by the drive voltage Vdd of the first node Q1, and the 15th transistor T15 of the output unit 50 also maintains its turned-off state by the ground voltage Vss of the second node Q2. Therefore, the output unit 50 outputs the clock signal CLK1 with a low level that is provided to the clock signal input line to the output lead through the 14th transistor T14. On the other hand, the clock signal CLK1 with a low level that is output from the output unit 50 is provided to a next stage as a first enable signal VOi−1.
During the interval t2, as the first enable signal VOi−1 is in a low level state, and the clock signal CLK1 is in a high level state, the 1st transistor T1 and the 3rd transistor T3 are turned off. Also, the 14th transistor of the output unit 50 is turned on. Namely, since the first node Q1 is floated as the 1st transistor T1 and the 3rd transistor T3 are turned off, it is bootstrapped by parasitic capacitor Cgs (not shown) between the gate and source of the 14th transistor T14 of the output unit 50, according to the high clock signal. Therefore, its voltage is greater than the drive voltage Vdd, and thus the 14th transistor T14 of the output unit 50 is firmly turned on. As the 14th transistor T14 is turned on, the high clock signal CLK is quickly provided to the output lead through the 14th transistor T14. Therefore, stage STi can output an output signal VOi with a high level.
On the other hand, during the interval t2, the stage STi+1 is operated like during the interval t1 of stage STi. Namely, stage STi+1 provides the drive voltage Vdd to the first node Q1 in response to the first enable signal VOi−1 to be input to the stage STi+1, which corresponds to the high output signal VOi, which is output from the stage STi.
After that, during the interval t3, the first enable signal VOi−1 maintains its low level, and the clock signal is in a low level state. Therefore, the 1st transistor T1 and the 3rd transistor T3 are turned off.
On the other hand, during the interval t3, as the high second enable signal VOi+1 is provided to the 12th transistor T12 of the third node controller 40 from the stage STi+1, the third node Q3 is charged with the first voltage Vd1 such that its level is high. Therefore, the 9th transistor T9 of the discharge circuit unit 60 is turned on by the first voltage Vd1 of the third node Q3, such that the ground voltage Vss can be provided to the first node Q1.
Because the ground voltage Vss is provided to the first node Q1 through the 9th transistor T9 of the discharge circuit unit 60, the first node Q1 is in a low level state. The 14th transistor T14 of the output unit 50 is turned off by the ground voltage Vss provided to the first node Q1. The drive voltage Vdd is provided to the second node Q2 through the 5th transistor T5. Here, as the 6th and 7th transistors T6 and T7 are turned off by the ground voltage Vss of the first node Q1, the 5th transistor T5 is turned on by the drive voltage Vdd provided through the 4th transistor T4. Therefore, the output unit 50 outputs the ground voltage Vss, or an output signal VOi with a low level, to the output lead through the 15th transistor T15.
After that, during the interval t4, as the second enable signal VOi+1 is in a low level state, and the 12th transistor T12 is turned off, the third node Q3 is floated and maintains its high level.
FIG. 4 illustrates waveforms when the circuit of FIG. 2 is operated in the reverse direction.
Referring to FIG. 4 along with FIG. 2, reverse operations of the conventional bi-directional shift register will be described in detail as follows:
Regarding the reverse direction scan, the low first voltage Vd1 is provided to the first voltage input line, and the high second voltage Vd2 is provided to the second voltage input line, respectively.
During the interval t1, stage STi receives the first enable signal VOi−1 with a low level from stage STi−1, and the second enable signal VOi+1 with a high level from stage STi+1. Also, during the interval t1, a first clock signal CLK1 with a low level is provided to the clock signal input line.
During the interval t1, the 2nd transistor T2 of the scan direction control unit 10 is turned on by the high second enable signal VOi+1, or an output signal of stage STi+1, and the 1st transistor T1 of the scan direction controller 10 is turned off by the first enable signal VOi−1 with a low level that is output from the stage STi−1. Therefore, the scan direction controller 10 provides the high second voltage Vd2 that is provided to the second voltage input line to the scan direction control node QS through the 2nd transistor T2.
Here, the high second voltage Vd2, which is applied to the scan direction control node QS, turns on the 3rd transistor T3 of the first node controller 20 and the 8th transistor T8 of the second node controller 30, simultaneously.
The drive voltage Vdd is provided to the first node Q1 via the turned-on 3rd transistor T3. The 6th and 7th transistors T6 and T7 in the second node controller 30 are turned on by the drive voltage Vdd of the first node Q1.
Also, as the drive voltage Vdd of the drive voltage input line is provided to the gate of the 5th transistor T5 via the 4th transistor T4 and the 5th transistor T5 is turned on, such that the drive voltage Vdd is provided to the second node Q2. Therefore, the ground voltage Vss is provided to the second node Q2 through the 7th and 8th transistors T7 and T8, and, at the same time, the drive voltage Vdd is also provided to the second node Q2 via the 5th transistor T5. However, because the number of transistors providing the ground voltage Vss to the second node Q2 is greater than the number of transistors providing the drive voltage Vdd, the second node Q2 is provided with the ground voltage Vss.
Also, during the interval t1, the third node controller 40 operates such that the 12th transistor T12 is turned on by the high second enable signal VOi+1 to provide the low first voltage Vd1 to the third node Q3, thereby turning off the 9th transistor T9 of the first discharge circuit 60. On the other hand, the 10th transistor T10 of the first discharge circuit 60 is turned off by the ground voltage Vss of the second node Q2.
In addition, the 14th transistor T14 of the output unit 50 maintains its turned-on state due to the drive voltage Vdd of the first node Q1, and the 15th transistor T15 of the output unit 50 also maintains its turned-off state due to the ground voltage Vss of the second node Q2. Therefore, the output unit 50 outputs the clock signal CLK1 with a low level, which is provided to the clock signal input line, to the output lead through the 14th transistor T14. On the other hand, the clock signal CLK1 with a low level, which is output from the output unit 50, is provided to the previous stage as a first enable signal VOi−1.
During the interval t2, as the second enable signal VOi+1 has a low level state and the clock signal CLK1 has a high level state, the 2nd transistor T2 and the 3rd transistor T3 are turned off. Also, the 14th transistor of the output unit 50 is turned on. Namely, because the first node Q1 is floated as the 2nd transistor T2 and the 3rd transistor T3 are turned off, it is bootstrapped by parasitic capacitor Cgs between the gate and source of the 14th transistor T14 of the output unit 14, according to the high clock signal. Therefore, its voltage is greater than the drive voltage Vdd, and thus the 14th transistor T14 of the output unit 50 is turned on. As the 14th transistor T14 is turned on, the high clock signal CLK is quickly provided to the output lead through the 14th transistor T14. Therefore, stage STi outputs an output signal VOi with a high level.
On the other hand, during the interval t2, the first node Q1 of stage STi−1 provided with the drive voltage Vdd in response to the second enable signal VOi+1 to the stage STi−1, which corresponds to the output signal VOi with a high level that is output from the stage STi.
After that, during the interval t3, the second enable signal VOi+1 maintains its low level, and the clock signal CLK is in a low level state. Therefore, the 2nd transistor T2 and the 3rd transistor T3 are turned off.
On the other hand, during the interval t3, the first enable signal VOi−1 has a high level. As the high first enable signal VOi−1 is provided to the 13th transistor T13 of the third node controller 40 from the stage STi−1, the third node Q3 is charged with the second voltage Vd2 such that its level is high. Therefore, the 9th transistor T9 of the discharge circuit unit 60 is turned on by the second voltage Vd2 of the third node Q3, such that the ground voltage Vss is provided to the first node Q1.
Because the ground voltage Vss is provided to the first node Q1 through the 9th transistor T9 of the discharge circuit unit 60, the first node Q1 is in a low level state. The 14th transistor T14 of the output unit 50 is turned off by the ground voltage Vss provided to the first node Q1 because the first node Q1 maintains its discharge state. On the other hand, as the 6th and 7th transistors T6 and T7 are turned off by the ground voltage Vss of the first node Q1, the 5th transistor T5 is turned on by the drive voltage Vdd provided to the 4th transistor T4, the drive voltage Vdd is provided to the second node Q2 through the 5th transistor T5. Therefore, the output unit 50 outputs the ground voltage Vss, or an output signal VOi with a low level, to the output lead through the 15th transistor T15.
After that, during the interval t4, the first enable signal VOi−1 is in a low level state, and the 12th transistor T12 is turned off. But, the third node Q3 is floated and maintains its high level.
Although the conventional bi-direction shift register is operated such that the 9th transistor can input a successive high voltage to its gate as the voltage of the third node Q3 is maintained at a low level during the intervals t1 and t2 and kept at a high state during the other intervals, it has disadvantages in that the 9th transistor suffers from aging due to bias stress caused by a voltage with a high level applied to the gate, in which the high voltage is provided to the third node Q3.


The present disclosure relates to a database (DB) synchronization apparatus of a transmission network system which includes a plurality of network elements (NEs) and an Element Management System (EMS). Each of the NEs may include a common memory in which DB information and alarm state information are rearranged and a sync-related memory of the same pattern as the common memory for maintaining DB identity with the EMS. The EMS may include a EMS sync-related memory for storing the DB and the information of the sync-related memory of the plurality of NEs, and a EMS common memory corresponding to the common memory (CM) of the NE. A common memory which reflects database information and the current alarm information to the NEs, and a sync-related memory which stores data prior to a T-second period are built on the NEs, and these two memories are compared in block units to thereafter transmit only modified block data to the EMS. Accordingly, there is the advantage that since synchronization is established by the comparison of the memories, an initialization execution time is very fast, and a real-time data monitoring and management is convenient.

1. Field of the Invention
The present invention relates to an EMS(Element Management System) and, in particular, to a method for a database synchronization between an EMS and NEs(Network Elements).
2. Description of the Prior Art
Generally, in a transmission network system, since a network element management system processes real-time data, a status of a network element (hereinafter referred to as NE) must be analyzed accurately and rapidly for thereby reporting to the network element management system.
FIG. 1 is a view illustrating a network EMS(hereinafter referred to as EMS) and network elements in the conventional art.
As shown in FIG. 1, each of the NEs has its NE_DataBase(hereinafter referred to as NE_DB). In the case that a data such as a DB, DB information, alarm state information, etc. is modified, the NE reports its changed status to the EMS, and the EMS performs a network management using a newly reported data.
As described above, the process in which each of the NEs reports its DB, DB information, alarm state information, etc. to the EMS, and, as a result, each NE and the EMS have the same information, is referred to as an identity maintaining process. The process in which the modified data is detected by the EMS at a certain time (period) T1 and thereby a network management is performed using a modified database1 is referred to as a synchronization.
There are two methods of maintaining the identity of the DB. One is a method in which the EMS periodically demands a synchronization from the NEs. The other is a method in which the NEs automatically report their modifications when the NEs are modified.
However, the former method has a disadvantage that since the EMS demands that each NE reports its modified DB by item and by pattern, the initialization process for synchronization between the EMS and each NE is lengthened. Accordingly, there arises a problem that it is difficult to apply the modified DB generated between the EMS and the NEs to the EMS accurately and rapidly.
In addition, the latter method is a method in which each NE reports its modifications to the EMS whenever its DB is modified. There is a possibility of a trade-off between a reporting period(T) and sync-related data. Therefore, when the reporting period is shortened, the amount of traffic is increased. On the contrary, when the reporting period is lengthened, the amount of sync-related data is increased, making it difficult to apply a real-time data.

Database synchronization apparatus in element management system and method therefor


A method is provided for determining the depth to the saturated soil at a selected site. A first and second instance wherein the depth of the water table equals the depth to the saturated soil is identified (142). The rate of change of the depth to the saturated soil is calculated (146) as a function of the specific yield, amount of time between the instances, total precipitation occurring between the instances, and depth of the water table at each instance. Then, the depth to the saturated soil for a third instance is calculated (148) as a function of the rate of change of the depth to the saturated soil. The calculated depth to the saturated soil for a third instance may be adjusted as a function of precipitation occurring at the site.

Wetlands may include marshes, bogs, and swamps. Wetland delineation tends to be controversial because such a determination often pits the interest of environmental protectionists against the interests of landowners. Therefore, standards or guidelines have been created to standardize wetland delineation. These guidelines also attempt to balance the interests of the public and private landowner. According to typical guidelines, whether a particular parcel of land qualifies as a wetland generally depends upon the percentage of the growing season that the surface of the soil is continuously saturated with water.
One example of wetland delineation guidelines includes the Corps of Engineers' Wetlands Delineation Manual of January 1987 ("'87 Manual"). The '87 Manual provides guidelines that may be used to determine whether a particular parcel of land is a wetland. Generally, land qualifies as a wetland if it is continuously saturated to the surface between 5% and 12.5% of the growing season. However, the '87 Manual indicates that many sites are not wetlands despite being continuously saturated to the surface between 5% to 12.5% of the growing season. A delineation in these cases is left to the judgment of the delineator. According to the '87 Manual, sites not continuously saturated at least 5% of the growing season are not wet enough to be considered wetlands.
The '87 Manual provides that, delineators (persons who determine whether a site is a wetland) may consider three parameters, soil characteristics, vegetation, and hydrology, when evaluating whether a site is a wetland. Soil characteristics may be used to determine whether the soils at the site are hydric soils. Hydric soils form under conditions of saturation including flooding that persists long enough to develop anaerobic conditions in the soil. These anaerobic conditions, characteristic of hydric soils, may be observed as color changes in the soils.
The hydrology determination, i.e., the depth to saturation in the soil, is the most controversial determination because a delineator cannot directly observe the hydrologic condition of the ground. Therefore, the delineator must rely on other indicators such as vegetation and soil characteristics to make the hydrology determination. Accurately evaluating the site in this manner requires numerous visits to the site. However, it is not uncommon for a delineator to make a delineation based on only a single visit. After the hydrology determination is made, it may be compared with standard hydrological criteria, such as those found in the '87 Manual.
Digging a pit in the ground and measuring the depth at which water appears in the pit will yield the depth of the water table (the upper boundary of a free groundwater body at atmospheric pressure). However, the depth of the upper boundary of saturated soil. (referred to hereafter as the depth to the saturated soil) is not necessarily equal to the depth of the water table. Capillary action, described in more detail below, may draw water up through the grains of soil to a level above the water table causing saturated soil to occur above the water table. The volume of water located between the depth to the saturated soil and the water table is known as the capillary fringe. Both the depth to the saturated soil and the water table may rise during rainfall and shrink when depletion mechanisms such as drainage, evaporation, and transpiration deplete water from the soil.
Referring FIGS. 1A–1E, the capillary fringe will be explained in greater detail. FIG. 1A depicts a barrel 10 of soil grains 14 and water 12. In FIG. 1A, the water 12 extends above the top surface of the soil grains 14 and water 12. In FIG. 1A, table 16 extends above the surface of the soil, there is no capillary tension. FIG. 1B depicts barrel 10 after water 12 has been depleted from the barrel 10 to the point that the depth to the saturated soil and the water table 16 are at the top of the surface of the soil grains 14. Therefore, there is no capillary fringe.
FIG. 1C depicts barrel 10 after one additional drop of water has been depleted from the barrel depicted in FIG. 1B. Menisci 20 form between soil grains 14 at the surface of the soil. As can be seen in FIG. 1C, the water table 16 has dropped to well below the surface of the soil while the depth to the saturated soil remains at the surface of the soil. Each menisci 20 has water 12 on one side and air on the other. Because the water 12 is attracted to the soil grains 14, the water 12 relentlessly seeks to encompass more soil grains 14. Capillary forces draw the water 12 upward to the surface of the soil forming a zone of negative pressure, known as a capillary fringe 22, between the depth to the saturated soil and the water table 16. The surface of the capillary fringe 22 is formed by menisci 20. The surface of the capillary fringe 22 may also be referred to as the capillary front. The capillary fringe 22 is depicted as a gray area between the water table and the surface of the soil. The capillary fringe 22 will move upward until negative pressure behind it reaches the maximum the menisci 20 can support. In this manner, the capillary forces create a pressure differential across the menisci 20 between the saturated soil and the air above the menisci 20. Above the menisci 20, the pressure is atmospheric. Below the menisci 20, the pressure may be as low as minus 12 inches of water. The negative pressure along the surface of the soil makes a visual observation of the depth to the saturated soil difficult because the surface of the soil may appear dry despite the fact that the soil grains directly underneath the surface grains are fully saturated with water.
FIG. 1D depicts barrel 10 after an additional drop of water has been depleted. In this figure, the water table 16 has fallen to the maximum distance the menisci 20 will support. This is evidenced by the fact that air entry 26 has occurred at the surface of the soil. Because the negative pressure between the menisci 20 and the water table is at its maximum, as the water table drops, it will pull the depth to the saturated soil downward with it. Under the conditions depicted in FIG. 10, the capillary fringe 22 is at its maximum length, which may be as large as approximately 12 inches of water. Again, the negative pressure along the surface of the soil will make the soil appear dry despite the fact that ground remains saturated to the surface of the soil.
Further water depletion from the barrel, as depicted in FIG. 1E will produce a non-saturated condition at the surface of the soil. Under these conditions, the depth to the saturated soil (i.e., depth to the surface of the capillary fringe 22), and the water table 16 will change depths at the same time separated by the full extent of the capillary fringe 22 (up to 12 inches).
Specific yield is the fraction of the saturated soil consisting of water that will drain by gravity when the water table drops. The magnitude of the drop in the depth to the saturated soil from FIG. 1D to FIG. 1E is a function of the specific yield of the soil contained in barrel 10.
In FIGS. 1A through 1E, as water was depleted from the barrel 10, no additional water was added. Of course, this is generally not the case in the field. When water is added, such as by precipitation, the surface of the capillary fringe becomes disturbed when new water fills in the menisci and relaxes the tension between the surface of the capillary fringe and the water table. When the tension is relaxed, the pressure in the area of negative pressure increases to atmospheric and the water table moves upward to the depth to the saturated soil. Under these circumstances, the water table and saturated soils may occur at the same depth which may be above, at, or below the surface of the soil. When the rain ends and the excess surface water has been depleted, the volume of water in the saturated soil decreases restoring the tension between the depth to the saturated soil and the water table.
Referring to FIG. 2, an idealized hydrograph 40 of a wetland can be viewed. Arrow 42 depicts time increasing from the left-hand side to the right-hand side of FIG. 2. In this figure, the capillary fringe 50 spans the distance between the surface of the soil 44 and the water table 48. A period of rain starting at time 54 and ending at time 56 causes the water table 48 to move upward to a location above the surface of the soil 44 creating a volume of water 58 above the surface of the soil 44. At this period of time, the capillary fringe collapses. After the period of rain, water is depleted. Water may be depleted by depletion mechanisms such as drainage, evaporation, and/or transpiration. When sufficient water has depleted, the water table 48 drops in depth and the capillary fringe 50 is reformed. However, the depth to the saturated soil 46 remains at the surface of the soil 44 with the capillary fringe 50 spannning the distance between the surface of the soil 44 and the water table 48. Therefore, FIG. 2 depicts a site where the surface of the soil is continuously saturated with water such as certain types of wetlands.
Referring to FIG. 3, an idealized hydrograph 80 of an upland site may be viewed. Arrow 82 depicts time increasing from the left-hand side to the right-hand side of FIG. 3. Initially, both the water table 88 and the depth to the saturated soil 86 are separated by the capillary fringe 90. Both surfaces continuously drop until the start 94 of a period of rain when the capillary fringe 90 collapses and both the depth to the saturated soil 86 and the water table 88 rise to the surface of the soil 84. As water is added, surface water 98 is appears above the surface of the soil 84. Shortly after the end 96 of the period of rain, water is depleted by depletion mechanisms such as drainage, evaporation, and/or transpiration. As a result of the depletion of water, the water table 88 drops and the capillary fringe 90 is reformed. The capillary fringe 90 maintains the depth to the saturated soil 86 at the surface of the soil 84 only briefly. As the water table 88 drops, the depth to the saturated soil 86 also drops. Therefore, in this idealized depiction of uplands, the depth to the saturated soil reaches the surface of the soil only during periods of precipitation and for a short time thereafter.
In summary, the capillary fringe causes the depth to the saturated soil to be as much a 12 inches above the water table. As mentioned above, the depth of the water table can be determined by the depth at which water occurs in a pit dug into the ground. Such a pit is typically 18 inches deep. However, the depth to the saturated soil cannot be accurately determined in this manner because the membrane of menisci and soil grains forming the surface of the capillary fringe may follow the wall of the pit holding water in the soil and preventing water from entering the pit. Under these circumstances, water will not seep into the pit from the saturated soil so long as the negative pressure of the capillary fringe opposes the seepage of water into the pit. Furthermore, the negative pressure along the pit wall obscures visual observation of the saturated soils (i.e., the soil along the pit wall adjacent to the saturated soils will appear dry despite the fact that the soil behind it is saturated with water). Determining which sites are wetlands is therefore complicated because determining the depth to the saturated soil is difficult.
One method of directly measuring the depth to the saturated soil involves using a tensiometer to measure suction or tension in the soil. This method works by using the tensiometer to determine the depth at which the pressure in the soil changes from atmospheric to below atmospheric (i.e., negative pressure). However, this method has the drawback of requiring blind searching to locate the depth to the saturated soil.
Determining the depth to the saturated soil is useful in determining whether a site qualifies as a wetland. The depth to the saturated soil can be used to determine the duration of continuous saturation at the surface of the soil. The duration of continuous saturation at the surface of the soil can be compared with wetland standards, such as those found in the '87 Manual, to determine whether a particular site should be considered a wetland.
It is clear from the above discussion of the capillary fringe that a determination of the depth of the water table alone is insufficient to determine the depth to the saturated soil. Therefore, a need exists for a more accurate method of determining the depth to the saturated soil in the ground. Further, a need exists for a system capable of performing such a method.

Method and system for measuring depth to saturated soils


The present invention is a multiple pump transmission jack for use with removing and repairing transmissions. The jack has two hydraulic pumps mounted on a base which are connected with interrelated oil passages or conduits formed within the base, which is operated by a pedal connected with the two pumps for drawing hydraulic oil from a reservoir and into an oil pressure cylinder to easily and quickly raise a piston rod within the oil pressure cylinder saving the operator's effort and increasing the efficiency of operation. The jack also includes an overload system that prevents the operator from placing a load on the jack which is greater than its rated load, thus preventing danger.

In maintenance or repair of an automobile transmission, a vehicle hoist is used to raise the automobile from the ground and then a jack is used to support and raise or lower the transmission as necessary when removing or installing the vehicle's transmission. A conventional transmission jack as is known in the prior art is seen generally at 100 in FIG. 1. This conventional transmission jack has a base 102, a hydraulic cylinder 112, a pump 104 mounted to the base 102 which is operated by a pedal 106. Optionally, legs 108 and castors 110 can be attached to the base 102.
As is seen in FIG. 2, the hydraulic cylinder device 112 has an oil pressure cylinder 116 and a reservoir 118. The oil pressure cylinder 116 has a piston rod 114, to which a bracket is affixed at the upper end of the piston rod 114 to accept a transmission. The pump 104 is connected to the reservoir 118 by way of an oil withdrawing conduit 120 provided within the base 102. The oil pressure cylinder 116 is connected to the oil withdrawing conduit 120 by way of oil exit conduit 124.
Referring to FIG. 3, a check valve 136 is shown. An oil pressure release conduit 128 is provided above for connecting the oil exit route 124 and the reservoir 118. Pressure release valve 126 is installed for controlling the release volume. Further, an overload conduit 122, is used to connect reservoir 118 and the oil exit conduit 124 and is controlled by a safety valve 130.
In operation, an operator repeatedly steps on the pedal 106 of the pump 104, forcing the oil in the reservoir 118 to flow through the oil withdrawing conduit 120, through the oil exit conduit 124 and then into the oil pressure cylinder 116 of the oil cylinder 112 to raise the piston rod 114. In order to lower the piston rod 114 of oil cylinder 112 the oil release valve 126 is used to connect the oil release conduit 128 with the oil exit conduit 124 allowing the oil in the oil pressure cylinder 116 to return to the reservoir 118 so that the piston rod 114 is lowered to its original position. In the event that the load is beyond its rated load, oil delivered by stepping on the pedal 106 cannot be pumped out through the oil exit conduit 124, but pushes upon the check valve 132 in the overload conduit 122 and flows back to the reservoir 118 thus not allowing the operator to overload the jack and avoiding danger.
However, conventional transmission jacks as described above have been found to have problems in that the time taken to raise a single pump transmission jack through depressing the pedal was too long and the operator would fatigue and be unable to operate effectively. The transmission jack of the present invention remedies this problem by incorporating two pumps into a transmission jack which increases the amount of oil that is drawn out of the reservoir and pumped into the oil pressure cylinder to raise the piston rod and in turn the transmission at a faster rate.


A baseboard management controller (BMC) for a server includes a memory configured to store instructions; and a processor configured to execute the instructions to: collect failure information of hardware of the server when a failure of the hardware or a restoration of the hardware is detected by monitoring the hardware; and analyze and determine stability of the server based on the failure information.

There is a system that monitors shared devices via a baseboard management controller (BMC) of a server without providing dedicated monitoring hardware for monitoring devices shared between servers.
Japanese Unexamined Patent Application, First Publication No. 2016-149924, Japanese Unexamined Patent Application, First Publication No. 2016-092898, and Japanese Unexamined Patent Application, First Publication No. 2013-127723 disclose a technology related to a BMC as a related technology.

BMC, server system, device stability determination method, and non-transitory computer-readable recording medium


An apparatus for forming an image by use of a plurality of light beams, which are simultaneously modulated according to image signals and joined together on a photoconductive surface to form the image. The apparatus includes a photoconductive drum having a photoconductive surface and a reference mark, a pattern supplying unit which supplies image data in synchronization with a detection of the reference mark associated with a rotation of the photoconductive drum, and drawing systems which (i) create moiré stripes on the photoconductive surface by simultaneously drawing overlapping sets of slanted lines with the respective light beams according to the image data, and (ii) draw a reference position mark alongside the moiré stripes on the photoconductive surface according to the image data.

1. Field of the Invention
The present invention generally relates to image forming apparatuses which join a plurality of light beams together on a photoconductive drum where the light beams are modulated independently of each other by image signals, and particularly relates to an image forming apparatus which detects and corrects the position of the light beams where drawing starts
2. Description of the Related Art
Japanese Patent Application Publication No. 2000-187171 discloses a technology that achieves a compact-size optical scan system having a wide scanning span by controlling two drawing systems with one deflection means and by joining the two drawing systems together. This technology provides two sets of drawing systems, a single deflection means shared by the two drawing systems. Two beams are guided to different deflection surfaces of the deflection means for deflection in respective directions. The two beams are then directed to the same scan surface, thereby scanning the scan surface by dividing a single scan area on the scan surface into respective halves. It is also disclosed that the two scan beams are swept in opposite directions from a seam where the two scan lines join together toward the opposite ends.
Japanese Patent Application Publication No. 2000-267027 discloses an image forming apparatus based on an optical scanning unit that uses two beams simultaneously deflected by the same deflection means, and scans a scan area on the scan surface by dividing the scan area by half in the main scan direction.
According to this technology, a single polygon is used for the scanning of two drawing systems to start beam scans from around the center of an image, and joins the beams together in the main scan direction. This achieves a compact-size drawing system providing a wide span at a low cost. A crossing point detecting means (one dimensional CCD) for detecting a beam crossing position in the sub-scan direction is provided to detect the positional error of a scan line in the sub-scan direction caused by temperature variation (which occurs due to a minute displacement of a beam path attributable to the thermal expansion of the housing and/or the lens system). The error is then corrected to achieve satisfactory precision of a positional setting in the sub-scan direction, thereby suppressing an error in the sub-scan direction along the seam line.
Japanese Patent Application Publication No. 2000-187171 described above teaches a basic technology regarding an apparatus using two scan beams and a single deflection means. No measure, however, is taken to cope with a displacement in the main scan direction at a seam where the two scan beams join together.
Japanese Patent Application Publication No. 2000-267027 described above takes into account the correction of error in the sub-scan direction at a seam where two scan beams join together. No consideration, however, is given to the correction of error in the main scan direction.
Along the seam, error in the main scan direction has a detrimental effect on an image. An error of ½ dot, for example, will appear as a white streak in a halftone image. A dot pitch is 42.3 micrometers in a 600-dpi image, for example, so that a tolerable dot error would be about 21 micrometers. Since two optical systems join together, a tolerable error of each optical system is 10 micrometer, which is half of 21 micrometers.
Factors that cause error in the main scan direction include:    1) signal delay caused by temperature characteristics of a synchronization detecting sensor;    2) variation in magnification factors of lens systems caused by a temperature rise;    3) a change in a distance relative to the photoconductive surface due to a temperature rise of machinery;    4) a change in a distance relative to the photoconductive surface caused by eccentricity that appears during rotation of the photoconductive drum.
Errors in the main scan direction were measured to be 60 micrometers in the case of 1), 20 micrometers in the case of 2), 10 micrometers in the case of 3), and 70 micrometers in the case of 4) (when the eccentricity is 100 micrometers). In total, an error of 160 micrometers was generated.
The assignee of this application has already addressed the detection and correction of respective errors in the cases of 1) through 3). With respect to error in the case of 4), the assignee of this application has also proposed measuring the eccentricity of a photoconductive drum by mechanical means and correcting error based on the measured eccentricity.
There is a need for a new scheme that detects and corrects a positional error in the main scan direction at a low cost where such an error is caused by the eccentricity of a photoconductive drum along the seam where beams of the two optical systems join together.

Positional correction for apparatus having a plurality of drawing systems


The invention relates to a hyperthermia system for treating a patient, comprising an RF power unit, one or more RF antenna's connected to the RF power unit for generating a focused three-dimensional RF field, a controller for adjusting the RF power source and/or the one or more RF antenna's for steering the focused three-dimensional RF field; a sensor for sensing a parameter representative of the focused three-dimensional RF field; a communication environment for inputting data from the said sensor and/or additional information provided by the patient, said communication environment being capable of generating trigger signals to the controller for in use steering the focused three-dimensional RF filed in real time. The invention further relates to a method for generation a focused three-dimensional RF field.

An embodiment of a hyperthermia system is known from U.S. Pat. No. 5,097,844. The known system is arranged to generate a three-dimensional focusing hyperthermia. The known system comprises a controller connected to a signal modifier capable of modifying a phase and a power amplitude of a multiple channel RF power system. A switching assembly is used to connect to a suitable antenna group forming the applicator of the known hyperthermia apparatus.
In order to determine a temperature at or near a target area of the focused three-dimensional RF power system, the known hyperthermia apparatus comprises a non-invasive thermometry sensor. The thermometry sensor is connected to the controller via a temperature monitor.
Hyperthermia systems known in the art usually operate using a treatment planning system which is configured to simulate the envisaged treatment and to calculate suitable settings for the RF antenna or RF antenna's for implementing the treatment. Should, however, in use, the determined temperature in the target region substantially deviate from a planned temperature, the controller may be activated automatically or manually for steering the RF antenna or antenna's for correcting the temperature profile or position of the hot region.
It is a disadvantage of the known hyperthermia system that limited control of the correspondence between the planned treatment and the actual treatment is available.

Hyperthermia system and a method for generating a focused three-dimensional RF field

ERASMUS UNIVERSITY MEDICAL CENTER ROTTERDAM


An apparatus and a method for routing data in a radio data communication system having one or more host computers, one or more intermediate base stations, and one or more RF terminals organizes the intermediate base stations into an optimal spanning-tree network to control the routing of data to and from the RF terminals and the host computer efficiently and dynamically. Communication between the host computer and the RF terminals is achieved by using the network of intermediate base stations to transmit the data.

In a typical radio data communication system having one or more host computers and multiple RF terminals, communication between a host computer and an RF terminal is provided by one or more base stations. Depending upon the application and the operating conditions, a large number of these base stations may be required to adequately serve the system. For example, a radio data communication system installed in a large factory may require dozens of base stations in order to cover the entire factory floor.
In earlier RF data communication systems, the base stations were typically connected directly to a host computer through multi-dropped connections to an Ethernet communication line. To communicate between an RF terminal and a host computer, in such a system, the RF terminal sends data to a base station and the base station passes the data directly to the host computer. Communicating with a host computer through a base station in this manner is commonly known as hopping. These earlier RF data communication systems used a single-hop method of communication.
In order to cover a larger area with an RF data communication system and to take advantage of the deregulation of the spread-spectrum radio frequencies, later-developed RF data communication systems are organized into layers of base stations. As in earlier RF data communications systems, a typical system includes multiple base stations which communicate directly with the RF terminals and the host computer. In addition, the system also includes intermediate stations that communicate with the RF terminals, the multiple base stations, and other intermediate stations. In such a system, communication from an RF terminal to a host computer may be achieved, for example, by having the RF terminal send data to an intermediate station, the intermediate station send the data to a base station, and the base station send the data directly to the host computer. Communicating with a host computer through more than one station is commonly known as a multiple-hop communication system.
Difficulties often arise in maintaining the integrity of such multiple-hop RF data communication systems. The system must be able to handle both wireless and hard-wired station connections, efficient dynamic routing of data information, RF terminal mobility, and interference from many different sources.


A method and system for testing a modular data-processing component. Register information associated with a modular data-processing component to be tested at a test location can be identified and stored. The modular data-processing component can then be tested and removed from said test location. Thereafter, the register information can be retrieved and provided for use with testing of a new data-processing component at said test location without losing said register information during testing of multiple modular data-processing components. The register information can be, for example, PCI configuration data and the modular data-processing component can be an HAB.

A host adapter board ("HAB") plugs into a host computer system to provide added functionality to the computer system. For example, the HAB facilitates communication between a peripheral component interconnect ("PCI") bus of the host computer system and a peripheral device (e.g., a storage subsystem, a network communication medium, etc.). The HAB often includes one or more components that provide the interface to the PCI bus and one or more components (e.g., an I/O controller) that provide interfacing to the peripheral device.
The PCI bus standards define certain PCI signal timing specifications. The PCI bus signal standards may be found, for example, at http://www.pcisig.com/specifications. Among the signaling standards specified therein are slew rate and clock-to-signal-valid delay. "Slew rate" defines a maximum rate of change in an output signal, for example four volts per nanosecond within a defined operating voltage range. "Clock-to-signal-valid" delay defines the time (e.g., five nanoseconds) between an initial clock signal and a ready state, which can be used to initiate data transfer to the HAB. To function properly, the HAB must process PCI signals from the bus within these PCI timing specifications.
One of the problems with current manufacturing tests for HAB and other modular data-processing components is that the operators or users are required to manually reboot the test system or select an option that will reboot the test system once they have changed out the HAB under test. In a manufacturing environment, the test system remains powered up while the slot for the HAB is powered down. This allows the operator to change out the HAB being tested. The PCI configuration, however, is lost. Without the PCI configuration information, the test system is unable to communicate to the HBA. Rebooting is required in order for the test system to communicate with the PCI or other similar card and the entire configuration space must be re-build for all associated devices found on the PCI bus. This process of rebooting and recreating the PCI configurations is very time consuming and costly in a manufacturing environment.
In the HAB functional test side of manufacturing, one of the main concerns is testing time. Because rebooting a system is factored into the testing time, test times are large and costly. There have been some approaches implemented for solving the reboot time consumption. The current solution involves rebooting the system and having the PCI configurations restored during the reboot process. The reboot process, however, is also time consuming and adds to the manufacturing costs of such HAB's.

Methods and systems for eliminating test system reboots between functional tests of host adapter boards


A broad band cholesteric liquid crystal film of the present invention is a cholesteric liquid crystal film obtained by coating a liquid crystal mixture containing a polymerizable mesogen compound (a), a polymerizable chiral agent (b) and a photoisomerizable material (c) on a substrate to ultraviolet polymerize a coat of the liquid crystal mixture, and has a reflection bandwidth of 200 nm or more. A broad band cholesteric liquid crystal film of the present invention has a broad reflection band, is of a thin type and can be manufactured in less of manufacturing steps.

Generally, a liquid crystal display has a structure in which a space between glass plates forming transparent electrodes is filled with a liquid crystal and polarizers are arranged before and after the glass plates. A polarizer used in such a liquid crystal display is manufactured in a procedure in which iodine or a dichloic dye is subjected to be adsorbed to a polyvinyl alcohol film and the film is stretched in a given direction. The polarizer thus manufactured itself absorbs light vibrating in one direction and transmits only light vibrating in the other direction therethrough to thereby produce linearly polarizing light. Therefore, an efficiency of the polarizer could not exceed 50% theoretically, which works as the greatest factor to reduce an efficiency of a liquid crystal display. As the matters worse about the absorbed light, if a liquid crystal display is operated with an increased output of a light source beyond a level, it results in inconveniences that a polarizer is broken down by heat generation due to thermal conversion of absorbed light or that a display quality is degraded under thermal influence onto liquid crystal layer in a cell.
A cholesteric liquid crystal having a circularly polarized light separating function has a selective reflection characteristic reflecting only circularly polarized light having a direction thereof coinciding with a helical rotation direction of the liquid crystal and a wavelength equal to a helical pitch length of the liquid crystal. With this selective reflection characteristic used, only a specific circularly polarizing light of natural light in a given wavelength band is transmission-separated and the other light components are reflected and recycled, thereby enabling a polarizing film with a high efficiency to be manufactured. In the context, transmitted circularly polarized light passes through a λ/4 plate and thereby converted to linearly polarizing light, and coincidence of a direction of the linearly polarized light with a transmission direction of an absorption polarizer used in a liquid crystal display enables a liquid crystal display with a high transmittance to be realized. That is, in a case where a cholesteric liquid crystal film is combined with a λ/4 plate and the combination is used as a linearly polarizer, the linearly polarizer could achieve a brightness twice as that of a conventional absorption polarizer singly used, which absorbs 50% of incident light, due to no light loss theoretically.
There has been, however, difficulty in covering all the range of visible light, since a selective reflection characteristic of a cholesteric liquid crystal is restricted to only a specific wavelength band. A selective reflection wavelength bandwidth Δλ is expressed by following formula:Δλ=2λ·(ne−no)/(ne+no)where no: ordinary light refractive index of a cholesteric liquid crystal molecule, ne: extraordinary light refractive index of the cholesteric liquid crystal molecule, and λ: central wavelength in selective reflection.
The selective reflection wavelength bandwidth Δλ depends on a molecular structure of the cholesteric liquid crystal itself. According to the above formula, if (ne−no) is larger, a selective reflection wavelength bandwidth Δλ can be broader, while (ne−no) is usually 0.3 or less. With this value being larger, other functions as a liquid crystal (such as alignment characteristic, a liquid crystal temperature or the like) becomes insufficient, causing its practical use to be difficult. Therefore, a selective reflection wavelength bandwidth Δλ has been actually on the order of 150 nm at highest. A cholesteric liquid crystal available in practical aspect has had a selective reflection wavelength bandwidth Δλ only of the order in the range of 30 to 100 nm in many cases.
A selective reflection central wavelength λ is given by the following formula:λ=(ne−no)P/2where P: helical pitch length required for one helical turn of cholesteric liquid crystal.
With a given pitch length, a selective reflection central wavelength λ depends on an average refractive index and a pitch length of a liquid crystal molecule.
Therefore, in order to cover all the range of visible light, there have been adopted methods, in one of which plural layers having respective different selective reflection central wavelengths are laminated, and in another of which a pitch length is continuously changed in the thickness direction to thereby form a positional distribution of selective reflection central wavelengths.
For example, there can be exemplified a method in which a pitch length is continuously changed in the thickness direction (for example, see a publication of JP-A No. 6-281814, a specification of JP No. 3272668 and a publication of JP-A No. 11-248943). This method is such that when a cholesteric liquid crystal composition is ultraviolet exposure-cured, exposure intensities on sides of exposure and light emission are differentiated therebetween to alter a polymerization speed therebetween, which provides a change in compositional ratio of a liquid crystal composition having a different reaction speed in the thickness direction.
The bottom line of this method lies in that exposure intensities on sides of exposure and light emission are greatly different therebetween. Therefore, in many of the examples of the prior art described above, there has been adopted a method in which an ultraviolet absorbent is mixed into a liquid crystal composition so as to cause absorption thereof in the thickness direction to thereby amplify a difference in exposure dosage according to an optical path length.
In a method disclosed in a publication of JP-A No. 6-281814, in which a pitch length is continuously altered, necessities arise for a liquid crystal thickness required for revealing the function to be on the order in the range of from 15 to 20 μm, and for more of an expensive liquid crystal in amount in addition to a problem of precise coating of a liquid crystal layer, which disables cost-up to be avoided. Moreover, an exposure time is necessary to be on the order in the range of from 1 to 60 min, which leads to a need for a long manufacturing line with an exposure line length in the range of from 10 to 600 m in order to obtain a line speed of 10 m/min. With a reduced line speed adopted, a line length can be reduced, while a lower manufacturing speed cannot be avoided.
This is because, as described in the publication of JP-A No. 6-281814, a quick change in pitch is difficult to be realized due to a theoretical issue in controlling a cholesteric pitch caused by a difference in ultraviolet exposure intensity in the thickness direction for a change in pitch length in the thickness direction and by a change in compositional ratio due to material transfer caused by a difference in polymerization speed accompanying the difference in ultraviolet intensity. Since, in the publication of JP-A No. 6-281814, pitch lengths in the short pitch side and the long pitch side are different therebetween by as large as on the order of 100 nm, a compositional ratio is necessary to change to a great extent and in order to realize it, a further necessity arises for a considerable thickness of liquid crystal, a very weak ultraviolet illumination and a long exposure time.
Since in a method disclosed in a publication of JP-A No. 11-248943, transfer of a material changing a pitch is better than an example material used in the publication of JP-A No. 6-281814, an exposure dosage of the order of 1 min enables a film to be formed. In this case as well, a necessary thickness is 15 μm, however.
While, in a specification of JP No. 3272668, a temperature condition in a first exposure is altered from that in a second exposure and a time necessary for a change in compositional ratio in the thickness direction is separately provided in a dark place, a wait time for material transfer due to a change in temperature is necessary to be in the range of from 10 to 30 min.
A liquid crystal coat thickness, even in the specification of JP No. 3272668 and the publication of JP-A No. 11-248943, is about 15 μm and in comparison of the specification and the publication described above with the publication of JP-A No. 6-281814 in which the liquid crystal coat thickness is required to be about 20 μm, it is understand that a necessity arises for a larger cholesteric liquid crystal thickness and a longer time for material transfer in order to cover all the range of visible light with a change in pitch caused by a change in compositional ratio in the thickness direction of one liquid crystal layer.
In a publication of JP-A No. 9-189811, at least three layers are necessary in order to cover all the range of visible light, and a long wavelength side is covered for betterment of a viewing angle characteristic, and the number of necessary laminated layers increases to as large as 4 to 5 in a case where a measure is taken against oblique incident light, which leads to more complexity in manufacture steps and increase in the number of steps, thereby unavoidably resulting in reduction in production yield.
With combination of such a broad band circularly polarizing plate with a retardation plate, a diffuse light source is enabled to emit collimated light. Adoption of such a collimated light source and a diffuse plate enables a construction of a viewing angle magnification system in a liquid crystal display.
For example, as shown in a specification of JP No. 2561483 and a publication of JP-No. 10-321025, by inserting a retardation plate controlled in a way such that a retardation value in a vertical direction of incidence and a retardation value in an oblique direction of incidence are specifically different from each other between polarizers, an angular distribution of transmitted light receives a restraint and in this case, if an absorption polarizer is used, light only in the vicinity of the front face is transmitted, while peripheral light are all absorbed. By using a circularly polarizing plate (a reflection polarizer), light only in the vicinity of the front face is transmitted while peripheral light is all reflected. If such an effect is adopted, emission light of a backlight can be condensed and collimated without being accompanied by absorption loss.
With combination of such a collimated backlight source and a diffuse plate less of backscattering and occurring no polarization cancellation, a viewing angle magnification system can be constructed. As described above, in a conventional method in which multiple liquid crystal layers are laminated, however, (the publication of JP-A No. 9-189811), there has arisen a problem of increased number of steps due to lamination of multiple layers, while in a method as disclosed in the publication of JP-A No. 6-281814 or the specification of JP No. 3272668 in which a liquid crystal layer is thick, there has occurred a problem of cost-up.

Broad-band-cholesteric liquid-crystal film, process for producing the same, circularly polarizing plate, linearly polarizing element, illiminator, and liquid-crystal display


The programming of programmable memory devices, e.g. one-time programmable (OTP) memory device is presented. In particular, efficient methods and systems for generating the supply voltage for programming a programmable memory device are described. A controller configured to control the programming of a data word into a programmable memory device is described. The controller is configured to set one or more digital control signals for programming the data word into the programmable memory device. Furthermore, the controller is configured to, subsequent to setting the one or more digital control signals, increasing a device supply voltage for the programmable memory device from a default operation level to a programming level.

OTP memory devices, which may also be referred to as programmable read-only memory (PROM), are used in various different applications to provide flexible means for storing program code or other data (e.g. calibration data). By way of example, OTP memory devices may be provided in conjunction with a controller on an integrated circuit (IC). In a particular example, OTP memory may be used on a driver circuit for a solid state lighting device (e.g. an Light Emitting Diode, LED, lamp) to store calibration data, which is determined and programmed at the end of the manufacturing process of such a solid state lighting device.
An OTP memory device typically comprises a plurality of pins which have different functions for the programming phase (when programming the OTP memory device to store data) and/or for the reading phase (when providing the stored data during operation of the IC which comprises the OTP memory device). A particular one of these pins is the supply voltage VPP pin (also referred to as the OTP supply voltage pin, or more generally to the device supply voltage pin). The OTP supply voltage VPP which may be applied to the OTP memory device typically takes on at least two different values: a read level (e.g. 1.5V) which is used during normal operation (i.e. during the reading phase) of the OTP memory device for reading the data which has been stored in the OTP memory device, and a programming level (e.g. 7.5V) which is used during the programming phase for allowing the OTP memory device to be programmed.

On-chip voltage generation for a programmable memory device


A process for preserving cellular structures includes the steps of pre-treating the structures with a polymeric water solution, drying the structures and then post-treating the structures with an organic solvent, non-water-base solution. Once the structure has been treated with the pre-treatment solution, the specimen is allowed to sit for a predetermined period of time in order for the active ingredients of the solution to penetrate the surface area of the specimen. The specimen is then preferably freeze-dried. The specimens are then treated with a non-water-based post-treatment solution of water-resistant, film-forming polymeric resin to form a barrier coat on the finished product.

The preservation of flowers and other naturally occurring materials has been practiced for many years, and many processes for such preservation have been described in literature. The main problem with the processes conventional in the art is that the preservation process has usually affected the appearance, shape and/or texture of the cellular structure. Thus, the natural colors of flowers tend to fade, and the cellular structures may be brittle, fragile and highly susceptible to damage due to extreme temperature or humidity.
It is therefore a general object of the present invention to provide a process and composition of matter for the preservation of cellular structures which will result in natural coloring, flexibility and freshness characteristics for relatively long periods of time after the preservation process.
Another object of the invention is to provide an economical and affordable method and process of preserving cellular material not previously known.
Another object of the present invention is to provide a freeze-drying process which significantly enhances the preservation of the cellular structure preserved thereby.
These and other objects will be apparent to those skilled in the art.


A data interface method includes differentially amplifying differential data signals based on a mode control signal indicating a first mode, transmitting the amplified differential data signals to a receiving semiconductor device via first and second transmission lines, and driving one of the differential data signals and a strobe signal to the first and second transmission lines, respectively, based on the mode control signal indicating a second mode, for transmitting the one of the differential data signals and the strobe signal to the receiving semiconductor device. The receiving semiconductor device samples the received differential data signals according to differential signaling, in response to a controlled sampling clock signal based on the mode control signal indicating a first mode; and samples the one of the differential data signals in response to a strobe signal, received from the transmitting semiconductor device, based on the mode control signal indicating a second mode.

In systems that include semiconductor memory devices, power consumed during data interface is proportional to a clock frequency used for the data interface. Accordingly, power consumed during a high-speed data interface is greater than that consumed during a low-speed data interface. Also, as the transmission rate of an input/output (I/O) interface increases, skew caused by different delays occurring in channels between the interfacing semiconductor devices also increases. Accordingly, per pin deskewing is necessary for pins corresponding to the respective channels in the semiconductor devices.
In order to compensate for skew, clock and data recovery (CDR) may be performed. In order to accomplish high-speed data transmission, differential signaling is more advantageous than single ended signaling, which is sensitive to supply noise, cross-talk and inter-symbol interface, for example. Generally, CDR and differential signaling may be used together for a high-speed data interface.


A device for time delay and integration imaging comprises: an array of pixels being arranged in rows and columns extending in a first and second direction, respectively. Pixels may accumulate generated charges in response to received electro-magnetic radiation along each column. The rows comprise at least one lateral charge shifting row to selectively shift accumulated charges in a column to an adjacent column and a controller configured to receive at least two angle correction input values. Each angle correction input value is based on a received intensity of electro-magnetic radiation on a measurement line, wherein the at least two angle correction input values are acquired by measurement lines extending in directions defining different angles in relation to the second direction, wherein the controller is configured to, based on the received at least two angle correction input values, control activation of the at least one lateral charge shifting row.

Time delay and integration (TDI) image sensing is a popular technique used for inspection of scenes with inherent linear motion such as in machine vision or earth observation. TDI image sensing may be particularly useful in light starved applications with low irradiance on the focal plane, typically a consequence of imaging faint objects and/or high speed imaging requirements, since integration of the low irradiance levels is allowed.
In TDI imaging, charges generated by light being incident on a pixel may be transferred along columns in an array of pixels of an imaging device in synchronization with a movement of the imaging device in relation to the scene. This implies that the charges may be accumulated (integrated) over time in the columns of the array so as to enable acquiring image information with a high signal-to-noise ratio.
However, in order for a signal from a part of the scene to be properly integrated by a column, the column may need to be nearly perfectly aligned with the movement of the imaging device in relation to the scene. If there is an angular misalignment between the columns and the direction of movement of the imaging device in relation to the scene, a given column will not image the same point of the scene during the integration and the TDI column will integrate the signal from different parts of the scene. The result is a reduction of the contrast of the image and appearance of blur.
This implies that the imaging device may be very accurately arranged in relation to a movement direction, such that the columns are aligned with direction of movement of the imaging device in relation to the scene. Hence, installation of the imaging device, e.g. for inspection of objects on a conveyor belt, may involve tedious work in aligning the columns of the imaging device with the movement of the conveyor belt.
US 2012/0162359 discloses an apparatus of correcting image distortion using an orthogonal transfer charge-coupled device array. A wide field of view line-scan remote sensing system includes an array of orthogonal transfer charge-coupled devices (OTCCDs) configured to record image data of an optical image of a moving object received from a lens. Further, the system includes a processor coupled to the array of OTCCDS, in which the processor is configured to scan the optical image across the array of OTCCDs; and shift pixel charges along a first axis and a second axis that substantially matches an actual image motion of the moving object while the optical image is being scanned in order to reduce an amount of image distortion across the array of OTCCDs.
Thus, the possibility of transferring charges along both a first axis and a second axis implies that the transfer of charges may be adapted to the moving object. However, set up of acquiring of a TDI image may still be simplified.

Device for time delay and integration imaging and method for controlling time and integration imaging


Apparatus and systems comprise a forward error correction (FEC) encoder to encode a data block to produce an encoded data block in a radio link control media access control (RLC-MAC) module. The EFC encoder may be coupled to a punctured subset selector to select a punctured subset of the encoded data block for transmission across a communication link. The punctured subset selector may be coupled to a modulator to modulate the punctured subset of the encoded data block using a selectable modulation type selected by a modulation selector coupled to the modulator. Hybrid automatic repeat request (HARQ) logic may be coupled to the modulation selector to receive at least one of an acknowledgement (ACK) or a no-acknowledgement (NACK) that a previously-transmitted punctured subset of the encoded data block was successfully decoded at a receiving end of the communication link. Additional apparatus, systems, and methods are disclosed.

An evolving family of standards, specifications, and technical reports is being developed by the Third Generation Partnership Project (3GPP™) to define parameters associated with second and third generation wireless communication systems. These systems include a Global System for Mobile communication (GSM) and data access technologies such as General Packet Radio Service (GPRS), enhanced GPRS (EGPRS), and Enhanced Data rates for GSM Evolution (EDGE). The acronyms GSM, GPRS, EGPRS, and EDGE are subsumed in "GSM EDGE radio access network (GERAN)." Additional information regarding these technologies may be found in European Telecommunications Standards Institute (ETSI) Technical Specification TS 101 855 V8.17.0, Digital Cellular Telecommunications System (Phase 2+); Technical Specifications and Technical Reports for a GERMAN-based 3GPP™ System (3GPP™) TS 01.01 version 8.17.0 Release 1999) (published June 2005). Additional information regarding the 3GPP™ may be found at its website.
Current GERAN standardizations may use modulation and forward error correction (FEC) coding schemes (MCSs) that include a one-third rate convolution coding operation followed by puncturing to a desired code rate. A resulting punctured block may be modulated according to one of several modulation types and interleaved across several time-division multiple-access (TDMA) frames. These MCSs may be denoted MCSI thru MCS9. For example, MCS7, MCS8 and MCS9 may operate using coding rates of R=0.75, 0.82, and 1.0, respectively, and may be encoded and modulated to provide data rates of approximately 45.0 to 59.4 kilobits (kbits)/s per timeslot
A particular MCS may be selected, depending on prevailing signal conditions, to transmit one or more radio link control (RLC) packet data units (PDUs) segmented from a logical link control (LLC) layer. For example, an MCS6radio block may utilize two 37-octet radio bursts to transmit a 74-octet RLC PDU utilizing 8-PSK modulation. An MCS3 radio block, on the other hand, may utilize a single 37-octet radio burst to transmit a 37-octet RLC PDU utilizing GMSK modulation.
A success or failure of decoding the RLC PDU may be sensed at a receiving end of a link and reported to a transmitting end of the link via acknowledge (ACK) or no-acknowledge (NACK) signaling, respectively. If a NACK is received at the transmitting end of the link, the transmission may be repeated utilizing a mechanism referred to as "automatic repeat request" (ARQ). Successive retransmissions may utilize successively more robust MCS levels to increase a likelihood of a successful decode.
Alternatively, encoded bits associated with an RLC PDU and received from a first transmission may be supplemented with a set of additional encoded bits associated with the same RLC PDU sent via a second transmission. An FEC decoder at the receiving end of the communication link may utilize sets of encoded bits from successive transmissions to enhance a decoding probability until a successful decode is obtained. The latter mechanism may be referred to as "hybrid ARQ" (HARQ).
One implementation of HARQ, referred to as "Type II incremental redundancy," may select each set of additional encoded bits for successive transmissions using a different puncturing scheme for each. This technique may effectively increase a code rate. An information block of N information bits, [S0S1 . . . S10-1], may be encoded as [s0p00p01s1p10p11 . . . sN-1p(N-3)0p(N-3)1], where pk0 and pk1 are parity bits output with a kth systematic bit. Using a simplified example, assume that N=16 without loss of generality, and that any code tail bits are neglected. Until the codeword is correctly decoded, transmission redundancy versions might follow a pattern similar to the following:                Transmission 1: [S0S1 . . . S15]        Transmission 2: [P00P11P20P33 . . . P14,0P15,1]        Transmission 3: [P00P10P23P30 . . . P14,1P15,0]
On the first transmission, N systematic bits may be sent. If the block is not received correctly, Transmission 2 may be sent using a punctured version of N of the parity bits. This may be combined at the receiver for an additional attempt to decode. If the block is again received incorrectly, Transmission 3 may be sent using another redundancy version of the parity bits. At this point all bits may have been transmitted at least once. A further attempt at decoding may be made. Should the further attempt fail, the redundancy version sequence may be repeated until the block is correctly decoded. Following each transmission, newly-received bits may be combined with those received in previous punctured versions of the block. This may increase an initial data input to the FEC decoder.
Successively-transmitted differently-punctured sets of encoded bits may be sent with successively more robust MCS levels. However, the latter technique may be incompatible between certain MCS levels. Consider, for example, a 74-octet RLC PDU formatted into a 74-octet MCS6 radio block and sent as a first transmission. If the first transmission is not successfully decoded, it may be desirable to re-segment the 74-octet RLC PDU as two 37-octet RLC PDUs for retransmission using MCS3. Since the RLC PDU sizes are different, the data may be re-encoded for the retransmission. The resulting set of encoded bits may be compatible with the set of encoded bits received as the first transmission, for purposes of an FEC decoding operation. It may thus be necessary to discard the set of encoded bits received as the first transmission.
Additional information regarding EGPRS block lengths may be found in 3GPP™ TS 43.064 V6.5.0 (2004-11) Technical Specification 3rd Generation Partnership Project Technical Specification Group GSM/EDGE Radio Access Network; General Packet Radio Service (GPRS); Overall description of the GPRS Radio Interface; Stage 2 (Release 6) (published November 2004).

Incremental redundancy using high-order modulation and coding schemes


A liquid crystal display device that reduces the likelihood of liquid crystal misalignment and driving errors is presented. The liquid crystal display device also improves color reproductively. The device includes a first substrate, and second substrate, and a liquid crystal layer placed between the first substrate and the second substrate. The first substrate includes a gate line and a data line that define a pixel region, a thin film transistor provided at an intersection area of the gate line and the data line, an organic film formed on the thin film transistor and having a depressed portion, a reflective film formed on the organic film, a black matrix, a color filter layer formed in the pixel region, and a pixel electrode formed on the color filter layer. The color filter layer has a different thickness in the depressed portion than in the rest of the pixel region.

1. Field of the Invention
The present invention relates generally to a liquid crystal display device and more particularly to a liquid crystal display device having a transflective color filter on an array (COA) structure.
2. Description of the Related Art
In general, a liquid crystal display (LCD) device includes a liquid crystal display panel, a backlight unit, a driving unit, a chassis and the like. The LCD panel is composed of a thin film transistor (TFT) substrate having a TFT formed thereon, a color filter substrate bonded to the TFT substrate and having a color filter layer formed thereon, and a liquid crystal layer disposed between the two substrates.
During the manufacturing of a LCD panel, the TFT substrate and the color filter substrate are bonded to each other. During this bonding process, a precise alignment of the two substrates is required. Problematically, even a minute misalignment of the substrates produces a defect in the LCD panel and specifically, in a reduction in the LCD panel's opening rate. In order to solve these problems, a color filter on array (COA) structure has been developed wherein both the TFT and the color filter are formed on the same substrate. More specifically, a TFT is formed on a TFT insulating substrate and a color filter layer is formed on the TFT to prepare a first substrate, and an opposing second substrate is prepared by forming only a common electrode on a second insulating substrate. The COA structure eliminates the need for precise alignment between the TFTs and the color filters upon bonding, thus advantageously reducing alignment errors upon bonding the substrates.
An LCD panel is a non-light emitting element and thus a backlight unit for supplying light is disposed on the rear side of the TFT substrate. The light radiated from the backlight unit changes its light transmissivity with arrangement of the liquid crystal layer.
An LCD device is categorized into a transmissive LCD device that uses only the light supplied from a backlight unit and a transflective LCD device that uses external light in addition to light from a backlight unit.
The transflective LCD device simultaneously uses light from a backlight unit that is transmitted through a transmissive area and external light from a source outside the device itself (such as the sunlight or ambient light). Thus, in outdoor or daytime environment where there is an abundance of ambient light, light incident on the LCD panel can be used by being reflected off a reflective film in a reflective area of the display that is formed on a TFT substrate. This ability to take advantage of ambient light reduces power consumption to one third of that used by a comparable transmissive LCD device. Thus, the service life of the light source and the battery can be extended by operating an LCD device in a transflective mode. A longer battery life improves the general performance of portable communication devices that incorporate the LCD.
For these reasons, LCD devices having a transflective COA structure have become increasingly popular. A transflective COA structure combines the low power consumption advantage of a transflective LCD panel and the low defect rate of the COA structure. However, in the current transflective COA structure, a difference in the light path through the color filter layer occurs between the transmissive area and the reflective area, thus causing a difference in the lengths of light paths between the transmissive and reflective areas. This difference in the light path lengths create inconsistencies in the reproduced colors, thereby decreasing color reproductivity. In order to achieve consistency in color and enhance color reproductivity, a light hole is formed on the color filter layer in the reflective area. Lights passing through the color filter layer and the light hole of the reflective area are mixed to match the color produced in the transmissive area, enhancing color reproductivity.
However, when forming the light hole, a stepped portion forms in the hole area during patterning. The presence of the stepped portion causes unintended orientations of the liquid crystal in the reflective area and defective driving of the liquid crystal by creating a difference in the cell gap among the hole area, the reflective area and the transmissive area.

Liquid crystal display device with reduced defect rate and improved color reproductivity


A voltage control circuit comprises a transformer (18) having primary (17) and secondary (20, 21) windings, an input coupled to said primary winding, first and second switch devices (11, 12) each coupled to said primary winding of the transformer, and a clamping capacitor (28) coupled to the transformer and at least one of the first and second switches. An output filter (25, 26) is coupled through a rectifier (23, 24) to the secondary winding of the transformer and an output is taken from the output filter. Means comprising a feedback circuit (13, 14, 15) coupled on one side to the output filter and on the other side to control terminals of the first and second switches cause the first and second switches to conduct current alternately. Operation of the circuit is stabilized by including an interconnection (29) of the clamping capacitor to the feedback circuit for generating a signal that modifies the energy applied by the feedback circuit to the control terminals of the first (11) and second (12) switches.

The copending application of Jacobs et al., Ser. No. 07/981,638, filed Nov. 25, 1992 hereby incorporated herein by reference, describes a DC-DC converter which uses a pair of FET switches, interconnected by a clamping capacitor, to drive a transformer. A pulse width modulator (PWM) causes the FET switches to conduct alternately and to switch when there is a low or possibly zero voltage across the FET switches. The zero-voltage switching results in high efficiency energy conversion, and the use of the external capacitance permits the circuit designer to reduce the rate at which drain-to-source voltages of either FET changes, thereby to reduce the level of conducted or radiated high-frequency electromagnetic wave interference (EMI) which may be undesirably generated by the circuit. The application also discusses how output voltage ripple can be reduced.
Circuit analysis shows that DC-DC converters of this type, which, because of the clamping capacitor, are referred to generally as "clamped mode" circuits, may be unstable if special care is not taken. Design to avoid instability typically results in a deteriorated transient response, output impedance and audio susceptibility. Accordingly, there is still a long-felt need in the industry for reliable, stable DC-DC converters having a high conversion efficiency, and good transient response, output impedance and audio susceptibility characteristics.


A paver includes a main vehicle body and a set of fore-wheels. The set of fore-wheels is connected to the main vehicle body via a hydraulic wheel suspension system which, in at least a paving mode of the paver, allows hydraulic level compensation for each wheel of the set of fore-wheels. The paver further includes a hydraulic motion control assembly adapted to selectively provide hydraulic spring suspension and/or hydraulic dampening to at least one wheel of the set of fore-wheels.

In road construction, it is common to use pavers to build at least portions of the road, in particular a basic layer and a topcoat of the road. A paver generally comprises a self-propelled tractor with a front hopper adapted to receive and store material, such as asphalt. At the bottom of the hopper, a scraper type of conveyor belt transports the material to the back of the machine. There, the material is spread out by one or more augers. A screed is positioned behind the one or more augers to thereby flatten and level the material and compact the layer using vibration and tamper drives. When a paver travels for the purpose of carrying out a road finishing operation, the paving screed is in a levelling position at which it rests on the road surface layer and carries out movements relative to a chassis of the paver.
EP 1 247 904 A2 discloses a paver with a pair of rear wheels and a set of fore-wheels. The paver illustrated in EP 1 247 904 A2 further comprises a screed located rearwards of the pair of rear wheels, as seen in an intended direction of travel of the EP 1 247 904 A2 paver. During a paving operation, the screed is generally in contact with the ground resulting in that a normal force is imparted on the screed, as consequence of which the pair of rear wheels, as well as the set of fore-wheels, are loaded in an appropriate manner.
However, in a transport operation, the screed may be raised such that it loses ground contact and this may in turn result in that the weight of the screed will be imparted on the paver rather than on the ground. Since the screed is located rearwards of the pair of rear wheels, the pair of rear wheels will in such a situation be imparted a relatively large load whereas the set of fore-wheels will generally be imparted a relatively low load. Such a load distribution between the pair of rear wheels and the set of fore-wheels may result in an undesired dynamic behaviour of the paver. For instance, during a transport operation, the paver may oscillate e.g. vertically or around a transversely extending axis.
As such, it would be desirable to improve the motion characteristics of the above-mentioned paver.