The present invention is directed to a remotely controlled power supply system that can change output polarity at a high slew rate without using switching devices. The system comprises a control circuit and two individual high voltage DC-DC converter power supply sections, one positive and one negative, connected in series. By nature of the control circuitry, either a positive or negative controllable current is produced depending upon a programmed voltage input. The two individual power supply sections are each self-oscillating single transistor circuits. The self-oscillating circuits contain an RC network tuned to provide attenuation at the second harmonic of the natural oscillating frequency of the circuit. This reduces and/or eliminates the tendency of this circuit to begin oscillation at the wrong harmonic of the natural frequency. A power-on delay circuit is used to suppress the outputs of the two power supply sections no matter the command of the input control programming signal. An enable signal input allows for suppression of the power supply system output at any other time.

Switching power supplies are used in many electronic systems of varying applications, including telecommunications, networking, test and measurement, and imaging. These power supplies can convert unregulated input into direct current (DC) power at predetermined voltage and power levels and provide a load with either a positive or negative voltage. Switching power supplies typically provide power through low loss components such as capacitors, inductors, and transformers, and by the use of transistors operating in either the cutoff state, where there is a high voltage across the pass unit but no current flow, or the saturation state, where there is a high current through the pass unit but at a very small voltage drop. The transistors essentially create an alternating current (AC) voltage from an input DC voltage. This AC voltage can then be stepped-up or down by transformers and then filtered back to DC voltage at the output.
Early high voltage switching power supplies required the user to manually switch output polarity. To do so, the user had to reconfigure the high voltage circuits by physically disconnecting and connecting key electrical nodes. This practice was unsafe in that it required the user to be exposed to energized high voltage circuits. Another disadvantage to using these power supplies was the significant time required for the user to manually change the output polarity.
Improved high voltage switching power supplies utilized mechanical means to change polarity instead of the manual switching procedure. As an example, new circuitry included control circuits, driver circuits, low voltage relays, high voltage relays, and transformers. Relay control logic was used to control the switching of the relays to produce either a negative or positive polarity. While these more advanced power supplies eliminated the danger of manual switching, the cost of the power supplies increased due to expensive relays. Additionally, even with mechanical switching means, the rate of output polarity change still did not occur at a very high rate. To illustrate, a circuit using high voltage relays generally requires tens to hundreds of milliseconds to switch. Thus, it would take a significant amount of time to warm-up devices that rely upon rapid output polarity change to heat a tube or a lamp used as a heating apparatus. There is also a limited voltage output range available as a result of the constraint in switching speed. For this reason, switching power supplies are commonly used for fixed output or limited adjustment range output designs. It is important for a power supply to be programmable for a wide range of output currents to satisfy the complex and varying needs of today's highly-sophisticated technological devices. A power supply using mechanical switching means does not meet this need.
An additional shortcoming of using mechanical switching means is in the production of bouncing and other undesired effects. A circuit that contains undesired effects is inefficient and can wear out its components after many cycles. This occurrence not only can lead to increased power supply costs for the consumer, but can also lead to the damage of any devices that are connected to the power supply.
A need therefore exists for a for a low power, high voltage power supply that is programmable for a wide range of output current, has the capability of either positive or negative current polarity output, does not use mechanical means for switching polarity, and can be commanded to systematically, efficiently, and effectively change polarity within a few milliseconds without undesired effects that can damage circuit components. Among others, devices that employ a lamp or tube as a heating source will greatly benefit from this type of power supply, as the warm-up time of the lamp or tube will essentially be eliminated.


A storage system and method for prestaging data in a cache based on relative changes in the frequency of data access and relative changes in the effectiveness of previous prestage operations. The relative changes in the frequency of data access are determined by storing statistics of data access to all regions in the system and comparing recent access statistics to the stored data. Access statistics include data location, I/O size and access frequency. The relative changes in the effectiveness of previous prestage operations are detected by recording the number of previous prestaging operations for a region, recording the number of I/O requests for data that has been prestaged, and dividing the number of I/O requests for previously prestaged data in a region during a time period by the number of previous prestage operations for the region during the same time.

Storage systems are one type of auxiliary computing storage devices where each system includes a large number of disk drive units. Large enterprise-level storage systems must have relatively high performance characteristics to meet the performance of high-performing application servers, file servers and database systems supported by the storage systems. In these storage systems, reading data from and writing data to the disk drive units are fairly time-consuming because of the lengthy mechanical operations within the disk drives. Examples of these operations include the arm movement in a disk drive or the rotational delay of the disk associated with getting a read/write head into a reading position or a writing position. To provide fast access to frequently accessed data, cache memories are typically used in the storage systems to temporarily hold this data. Since the read latency for data from a cache memory is less than that for a disk drive unit, the presence of the cache memory significantly improves the overall throughput of a storage system.
To further reduce the read latency, storage systems also use prestage operations to retrieve data from a disk drive into a cache before the data is retrieved by the next host I/O request. This can be done by the host issuing a prestage command, such as the extent channel command used in mainframe programs to indicate that a sequential access will take place, to the storage system to move data to cache. Alternatively, the storage system anticipates the next host I/O request and retrieves the data without any special hint or command from host application.
Since a cache memory has a much higher cost per byte than the data storage, its size is significantly smaller than the total storage. Resource management of the cache is typically done through a Least-Recently-Used (LRU) algorithm. The time duration since the last use of the data in the cache is an indication of its frequency of use. Data stored in the cache memory is aged from the point of time of its last use. Due to the limited capacity of the cache, data is continuously removed from the cache's address space as it becomes the least recently used data. While infrequently accessed data periodically enters the cache, it will tend to age and fall out of cache under the Least-Recently-Used algorithm.
Prior art prestage algorithms assume that data that is sequentially accessed is likely to be accessed in close temporal order or vice versa. In current storage systems, prestage algorithms use metadata to identify a perfect sequentially access I/O pattern to signal to the systems that a prestage operation is necessary. As an example, assume that LBAx, LBAx+y, LBAx+2y, LBAx+3y and so on are contiguous chunks of logical block addresses (LBAs) on a disk drive unit. There are different ways how the host can access the data, which affect the prestage algorithms as a result.
If the order of accesses is LBAX, LBAx+y, LBAx+2y and LBAx+3y, the storage system will prestage LBAx+2y and LBAx+3y only after LBAX, LBAx+y and more perfectly sequential data are accessed one following the other.
If the order of accesses is LBAx, LBAx+2y, LBAx+y and LBAx+3y, the storage system will fail to prestage LBAx+3y after LBAx is accessed.
If the order of accesses is LBAx, LBAx+2y, LBAx+4y, LBA+6y and so on, the storage system will also fail to issue any prestage in the region at all.
The size of the metadata associated with perfectly sequential access data is limited to the size of the memory in the storage systems. This configuration limits the overall accuracy and comprehensiveness of the recorded metadata. Since the gap between the size of the metadata memory in the storage system and its total storage capacity is growing rapidly, the recorded metadata does not accurately represent the I/O behavior.
U.S. Pat. No. 6,44,697 describes a method for prestaging data into a cache to prepare for data transfer operations. The method determines addressable locations of the data to be cached and generates a data structure capable of indicating contiguous and non-contiguous addressable locations in the storage system. A prestage command then causes the data at the addressable locations in the data structure to be prestaged into the cache. This prestage method does not take into consideration relative changes in the data access frequency and relative improvements in previous prestage operations.
U.S. Pat. No. 6,260,115 describes a method for prestaging data in a storage system by detecting a sequential access pattern and then prestaging a number of data tracks ahead of the current request based on the available storage. Data accesses are maintained in a list in the most-recently-used order from which sequential access patterns are detected. A key disadvantage of this method is that its benefits are realized only if there is a perfect sequentiality in the I/O stream.
Therefore, there remains a need for a storage system and method for efficiently prestaging data without the drawbacks of the prior art methods described above.

Storage system and method for prestaging data in a cache for improved performance

International Business Machines Corporation


An apparatus and method are provided for extending a microprocessor instruction set beyond its current capabilities to allow for extended size operands specifiable by programmable instructions in the microprocessor instruction set. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions for execution by the microprocessor. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies an extended operand size for an operand corresponding to a prescribed operation, where the extended operand size cannot be specified by an existing instruction set. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within the existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions and performs the prescribed operation using the operand.

1. Field of the Invention
This invention relates in general to the field of microelectronics, and more particularly to a technique for incorporating extended data modes into an existing microprocessor instruction set architecture.
2. Description of the Related Art
Since microprocessors were fielded in the early 1970's, their use has grown exponentially. Originally applied in the scientific and technical fields, microprocessor use has moved over time from those specialty fields into commercial consumer fields that include products such as desktop and laptop computers, video game controllers, and many other common household and business devices.
Along with this explosive growth in use, the art has experienced a corresponding technology pull that is characterized by an escalating demand for increased speed, expanded addressing capabilities, faster memory accesses, larger operand size, more types of general purpose operations (e.g., floating point, single-instruction multiple data (SIMD), conditional moves, etc.), and added special purpose operations (e.g., digital signal processing functions and other multi-media operations). This technology pull has resulted in an incredible number of advances in the art which have been incorporated in microprocessor designs such as extensive pipelining, super-scalar architectures, cache structures, out-of-order processing, burst access mechanisms, branch predication, and speculative execution. Quite frankly, a present day microprocessor is an amazingly complex and capable machine in comparison to its 30-year-old predecessors.
But unlike many other products, there is another very important factor that has constrained, and continues to constrain, the evolution of microprocessor architecture. This factor—legacy compatibility—furthermore accounts for much of the complexity that is present in a modern microprocessor. For market-driven reasons, many producers have opted to retain all of the capabilities that are required to insure compatibility with older, so-called legacy application programs as new designs are provided which incorporate new architectural features.
Nowhere has this legacy compatibility burden been more noticeable in the development history of x86-compatible microprocessors. It is well known that a present day virtual-mode, 32-/16-bit x86 microprocessor is still capable of executing 8-bit, real-mode, application programs which were produced during the 1980's. And those skilled in the art will also acknowledge that a significant amount of corresponding architectural "baggage" is carried along in the x86 architecture for the sole purpose of supporting compatibility with legacy applications and operating modes. Yet while in the past developers have been able to incorporate newly developed architectural features into existing instruction set architectures, the means whereby use of these features is enabled—programmable instructions—are becoming scarce. More specifically, there are no more "spare" instructions in certain instruction sets of interest that provide designers with a way to incorporate newer features into an existing architecture.
In the x86 instruction set architecture, for example, there are no remaining undefined 1-byte opcode states. All 256 opcode states in the primary 1-byte x86 opcode map are taken up with existing instructions. As a result, x86 microprocessor designers must presently make a choice to either provide new features or to retain legacy compatibility. If new programmable features are to be provided, then they must be assigned to opcode states in order for programmers to exercise those features. And if spare opcode states do not remain in an existing instruction set architecture, then some of the existing opcode states must be redefined to provide for specification of the new features. Thus, legacy compatibility is sacrificed in order to make way for new feature growth.
One area of growth that continues to plague microprocessor designers is operand size. Early microprocessor designs provided 8-bit operations using 8-bit operands. Then, as computations within application programs became more complex, the size of the operands and commensurate computations grew to 16 bits. The present state of the art in microprocessors for desktop/laptop computing applications provides for 32-bit operands/operations. The size of operands/operations in a microprocessor is commonly referred to as a data mode. Hence, to retain compatibility with legacy application programs, a present day desktop/laptop microprocessor is capable of operating in a 32-bit data mode, a 16-bit data mode, and even perhaps an 8-bit data mode.
But even at present, there are application programming areas that are disadvantageously impacted because present day microprocessors do not support extended data modes such as 64-bit data mode and 128-bit data mode. Yet, to support these extended data modes within an architecture that has no spare opcode values would require redefinition of existing opcodes, thereby abandoning support for legacy applications.
Therefore, what is needed is an apparatus and method that incorporate extended data modes into an existing microprocessor instruction set architecture having a completely full opcode set, where incorporation of the extended data modes additionally allows a conforming microprocessor to retain the capability to execute legacy application programs.

This patent is subject to a terminal disclaimer.

Apparatus and method for extending data modes in a microprocessor


The present invention provides a compound represented by the following formula (I)

Conventionally, medicaments having a renoprotective effect (suppression of proteinuria, suppression of renal hypofunction) have been used for the treatment of diabetic nephropathy. Of such medicaments, only the antihypertensive agents of angiotensin II receptor blocker (ARB) and angiotensin converting enzyme inhibitor (ACEI) showed efficacy in large scale clinical trials (New England Journal of Medicine (GB), vol. 329, pp. 1456-1462 (1993)). Since ARB and ACEI have a hypotensive action, their usefulness for patients without hypertension has not been clarified, and suppression of progress of diabetic nephropathy only with the current medicaments is considered to be difficult. Therefore, the development of a potent renoprotective agent free of hypotensive action has been strongly demanded.
In the meantime, AGEs have been known to result from modification of protein by a reactive carbonyl compound produced due to hyperglycemia and oxidative stress in the lesion of diabetic nephropathy. Recently, it has been proved that several kinds of medicaments of ARB and ACEI inhibit formation of AGEs, and the renoprotective effect of ARB and ACEI is exerted independent of the hypotensive action. In addition, it has also been clarified that renal disorder depends on the-amount of AGEs contained in the kidney tissue rather than the blood pressure, and that the administration of ARB decreases the amount of AGEs as well as the renoprotective effect.
From the foregoing, since the amount of AGEs contained in kidney tissue could be a significant index of disorder in diabetic nephropathy, the development of a medicament that specifically inhibits AGEs formation is considered to lead to the production of a powerful renoprotective agent free of a hypotensive action.
WO02/083127 discloses a compound having a partially common structure with the phenylene derivative of the present invention, and showing an AGEs formation inhibitory action. However, the compound is different from the compound of the present invention in that a biphenyltetrazole skeleton is essential.
In addition, JP-A-10-310524 discloses a compound having a partially common structure with the phenylene derivative of the present invention, and showing a nephritis inhibitory action. However, the compound is different from the compound of the present invention in that a biphenyltetrazole skeleton is essential and it has an angiotensin II receptor antagonistic action.

Phenylene derivative having tetrazole ring or thiazolidinedione ring

Abstract: wherein A is a cyclic group etc., B is a 1H-tetrazol-5-yl group or a 2,4-dioxothiazolidin-5-yl group, and Y is a single bond or a C6-10 arylene group, or a pharmacologically acceptable salt thereof or an ester thereof.


An apparatus for determining a pose(s) of an object(s) may include a processor and memory storing executable computer code causing the apparatus to at least perform operations including receiving a detected image of at least one face and analyzing the image of the at least one face based on data of at least one model identifying one or more poses. The poses may be related in part to at least one of a position or an orientation of respective faces. The computer program code may further cause the apparatus to determine that the face corresponds to one of the poses based in part on one or more items of data of the image passing criteria identified by the model as corresponding to the pose. Corresponding methods and computer program products are also provided.

The modern communications era has brought about a tremendous expansion of wireline and wireless networks. Computer networks, television networks, and telephony networks are experiencing an unprecedented technological expansion, fueled by consumer demand. Wireless and mobile networking technologies have addressed related consumer demands, while providing more flexibility and immediacy of information transfer.
Current and future networking technologies continue to facilitate ease of information transfer and convenience to users. Due to the now ubiquitous nature of electronic communication devices, people of all ages and education levels are utilizing electronic devices to communicate with other individuals or contacts, receive services and/or share information, media and other content. One area in which there is a demand to increase ease of information transfer relates to services for performing image processing. In this regard, for example, improving the reliability of accurately determining a pose of one or more objects in an image or video may enhance image processing.
At present, a pose of a detected object may be performed by pose based object detectors. Although a conventional pose based object detector may detect and classify a specific pose of an object, the chance of conventional pose based object detectors detecting a pose incorrectly may be higher than desirable. This is typically because training of a classifier of a pose is generally performed by using many samples of a same pose in which the variations in the samples may be huge due to irregularities in cropping, and/or feature selection may not be robust enough to effectively represent a pose of an object.
In particular, conventional pose based object detectors may encounter problems in pose detection in instances associated with border faces, errors due to process of detection, cropping irregularities, etc. For instance, by utilizing conventional pose based detectors, the discrimination between two poses may typically be less at the border. For example, faces at the edge of an image may be more difficult to detect. As such, pose detection of these border faces utilizing conventional approaches often result in pose detection error. Additionally, conventional posed based detectors may encounter errors due to process of detection. For instance, if a scanning window encloses a partial frontal face, in an instance in which the scanning window should enclose the full face, the conventional pose based detectors oftentimes determine that a detected face corresponds to a half profile pose (e.g., yaw<45 degrees) instead of a frontal pose of the face, due to the view in the window being closer to a half profile than a frontal profile. This may be due to the inherent nature of window scanning. Moreover, by utilizing conventional pose based detectors, errors in pose detection may occur due to one or more cropping irregularities of an image.
In view of the foregoing drawbacks, it may be beneficial to provide a mechanism for efficiently and reliably determining a pose of one or more detected objects.

Methods, apparatuses and computer program products for performing accurate pose estimation of objects


A method for purging a fuel cell system comprises detecting a signal for stopping an operation of a fuel cell system, cutting off an electricity output of the fuel cell system, driving a steam generator of a fuel supply unit of the fuel cell system for a certain time and thereby generating steam, certifying whether a purging operation of the fuel cell system has been completed or not, and stopping the fuel cell system, in which the fuel cell system is purged by using steam generated by the steam generator. Since an additional container for storing nitrogen is not required, a fabrication cost is reduced. Also, inconvenience caused by periodically containing nitrogen in the container is solved. Furthermore, when the fuel cell system is used at home, an additional space for installing the nitrogen container is not required and the fuel cell system can be easily installed.

1. Field of the Invention
The present invention relates to a method for purging a fuel cell system, and more particularly, to a method for purging a fuel cell system capable of emitting combustible gas remaining in a fuel cell system outwardly at the time of stopping the fuel cell system.
2. Description of the Background Art
FIG. 1 is a schematic view showing a conventional fuel cell system of a proton exchange membrane fuel cell (PEMFC) method in which a hydrocarbon-based fuel such as LNG, LPG, CH3OH, gasoline, etc. is used as a fuel by refining only hydrogen by a desulfurizing process, a reforming process, and a hydrogen refining process.
As shown, the conventional fuel cell system comprises a fuel supply unit 10 for supplying only hydrogen extracted from LNG to a stack unit 30, an air supply unit 20 for supplying air to the stack unit 30 and the fuel supply unit 10, and a stack unit 30 for generating electricity by supplied hydrogen and air.
As a fuel and steam perform a reforming process in the fuel supply unit 10, hydrogen is generated. In order to generate the steam, the fuel supply unit 10 is provided with a steam generator 10b and a burner 10a for supplying heat to the steam generator 10b.
In order to drive the burner 10a, a fuel is supplied to the burner 10a, and then off-gas remaining in the stack unit 30 after generating electricity is supplied to the burner 10a.
When a signal for stopping an operation of the fuel cell system is applied to the fuel cell system, combustible gas (methane, city gas, hydrogen, etc.) remaining in the fuel supply unit 10 and the stack unit 30 is purged by using nitrogen thereby to be exhausted outwardly.
However, in case of purging combustible gas by using nitrogen, an additional container for storing the nitrogen is required and thus a fabrication cost is increased. Also, when the nitrogen is used up, new nitrogen has to be periodically contained in the container. Furthermore, when the fuel cell system is used at home, there is a difficulty in obtaining an additional space for installing the nitrogen container.


A fin field effect transistor arrangement comprises a substrate and a first fin field effect transistor on and/or in the substrate. The first fin field effect transistor includes a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. A second fin field effect transistor is provided on and/or in the substrate including a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. The second fin field effect transistor is arranged laterally alongside the first fin field effect transistor, wherein a height of the fin of the first fin field effect transistor is greater than a height of the fin of the second fin field effect transistor.

In CMOS technology, circuits are formed that are integrated on a substrate, the circuits having n-channel field effect transistors and p-channel field effect transistors. When the transistors of different conduction types are dimensioned identically, it happens that an n-channel transistor of a CMOS circuit has a different current driver capability than a p-channel transistor of the circuit.
In the case of integrated circuit components in CMOS technology that have n-MOS transistors and p-MOS transistors (for example inverters, oscillators, etc.), the different current driver capability of the transistors of different conduction types is compensated for in accordance with the prior art by providing p-MOS transistors having a different transistor width than n-MOS transistors. A p-channel transistor having a larger (e.g., double to triple) width than the corresponding n-channel transistor is often provided.
However, increasing the transistor width of the p-channel transistor in a CMOS circuit has the disadvantage that this enlarges the area requirement for realizing the circuit on a silicon chip. Valuable silicon area is lost as a result, which is disadvantageous in view of the cost pressure in semiconductor technology.
A description is given below, referring to FIG. 1A, FIG. 1B, of an n-MOS field effect transistor 100 and a p-MOS field effect transistor 110 of a CMOS circuit in accordance with the prior art.
The n-MOS field effect transistor 100 from FIG. 1A contains a first source/drain region 101 and a second source/drain region 102, between which a channel region 103 is formed. The electrical conductivity of the channel region 103 can be controlled by means of applying an electrical voltage to a gate region 104. The transistor width of the n-MOS field effect transistor 100 is designated by d1 in FIG. 1A.
FIG. 1B shows a p-MOS field effect transistor 110, which is intended to have the same current driver capability as the n-MOS field effect transistor 100. The p-MOS field effect transistor 110 likewise has a first source/drain region 111 and a second source/drain region 112, between which a channel region 113 is formed. The electrical conductivity of the channel region 113 can be controlled by means of applying an electrical signal to a gate region 114.
As shown in FIG. 1B, the transistor width d2 of the p-MOS field effect transistor 110 is significantly greater than the transistor width d1 of the n-MOS field effect transistor 100.
The different transistor widths d1, d2 are necessary in order to achieve identical current driver capabilities of the transistors in a CMOS arrangement in which the n-MOS field effect transistor 100 and the p-MOS field effect transistor 110 are integrated. Consequently, the p-MOS field effect transistor 110 requires approximately triple the area of the n-MOS field effect transistor 100 in order to achieve the same current driver capability in both transistors 100, 110. This is disadvantageous since the necessary chip area for forming the transistors 100, 110 is thereby enlarged.
In view of the demand for increasingly smaller integrated components and transistors, which enable good control of the electrical conductivity of the channel region even with continued scaling, alternatives to conventional field effect transistors are the subject of current research and development. One such novel type of field effect transistor is the so-called fin field effect transistor. In the case of a fin field effect transistor, in a thin fin, that is to say in a thin semiconductor fin having a width of, for example, 50 nm or less, two end sections are formed as source/drain regions, a channel region being formed between the two source/drain regions in the fin. The channel region is covered by a gate insulating layer. A gate electrode is formed on the gate insulating layer, that is to say above the fin, and enables lateral driving of the electrical conductivity of the fin.
However, even in fin field effect transistors the problem arises that p-fin field effect transistors have current driver capabilities or generally transistor properties which differ from the current driver capabilities or transistor properties of an n-fin field effect transistor given identical dimensioning.
Anil, K G, et al. (2003) "Layout Density Analysis of FinFETs," ESSDERC 2003, 16.-18.09.2003 Estoril, Portugal, discloses a fin field effect transistor arrangement in which the fins of an n-MOS fin field effect transistor and the fin of a p-MOS fin field effect transistor are divided into a plurality of semiconductor partial fins formed alongside one another, it being possible for the current driver capability of the two transistors to be coordinated with one another by virtue of a different number of partial fins in the n-MOS fin field effect transistor and in the p-MOS fin field effect transistor. However, this concept has the disadvantage that the space requirement of the transistor arrangement is increased by means of dividing the fin into a plurality of partial fins, which counteracts the endeavor to increase the integration density.
A description is given below, referring to FIG. 1C, of an n-MOS fin field effect transistor 120 and, referring to FIG. 1D, of a p-MOS fin field effect transistor 130 in accordance with the prior art in which similar current driver capabilities are sought by providing in each case a plurality of partial fins that differ in their number.
The n-MOS fin field effect transistor 120 contains two silicon partial fins 125, 126. One end section of the silicon partial fins 125, 126 of the n-MOS fin field effect transistor 120, which are arranged parallel to one another, forms a first source/drain region 121, and another end section of the silicon partial fins 125, 126 of the n-MOS fin field effect transistor 120, which are parallel to one another, forms a second source/drain region 122. A channel region 123 is formed between the first source/drain region 121 and the second source/drain region 122, and the conductivity of the channel region can be controlled by a gate region 124 formed on the silicon partial fins 125, 126. A gate insulating layer (not shown) is arranged between the gate region 124 and the silicon partial fins.
The p-MOS fin field effect transistor 130 contains six silicon partial fins 135. One end section of the silicon partial fins 135 of the p-MOS fin field effect transistor 130, which are parallel to one another, forms a first source/drain region 131, and another end section of the silicon partial fins 135 of the n-MOS fin field effect transistor 130, which are arranged parallel to one another, forms a second source/drain region 132. A channel region 133 is formed between the first source/drain region 131 and the second source/drain region 132, and the electrical conductivity of the channel region can be controlled by a gate region 134 formed on the silicon partial fins 135. A gate insulating layer (not shown) is arranged between the gate region 134 and the silicon partial fins 135.
As emerges from FIG. 1C, FIG. 1D, the area requirement of a field effect transistor having a plurality of partial fins is all the greater, the larger the number of partial fins. Consequently, the provision of a plurality of partial fins considerably increases the area requirement.
Furthermore, U.S. Pat. No. 6,413,802 (the '802 Patent) describes a fin field effect transistor device, in which case, in accordance with one embodiment described therein, a plurality of field effect transistors are provided, which are stacked one above another and are insulated from one another by a dielectric layer in each case. For this stack of transistors, the '802 Patent furthermore describes that the ratio of the widths of the NMOS field effect transistors and PMOS field effect transistors can be adapted by means of adapting the thicknesses of the semiconductor layers.
U.S. patent application Publication No. 2004/0023506 discloses a method for producing a gate oxide layer with two regions having a different layer thickness.
U.S. Pat. No. 4,996,574 describes a MIS field effect transistor whose channel region is significantly smaller than double the maximum propagation of the depletion region that can form in the channel region.

Fin field effect transistor arrangement and method for producing a fin field effect transistor arrangement


One embodiment of the present invention provides a system for operating a key distribution center (KDC) that provides keys to facilitate secure communications between clients and servers across a computer network, wherein the system operates without having to store long-term server secrets. The system operates by receiving a communication from a server at the KDC. This communication includes an identifier for the server, as well as a temporary secret key to be used in communications between a client and the server for a limited time period. In response the communication, the system attempts to authenticate the server. If the server is successfully authenticated, the system stores the temporary secret key at the KDC, so that the temporary secret key can be subsequently used to facilitate communications with the server. Upon subsequently receiving a request at the KDC from a client that desires to communicate with the server, the system produces a session key to be used in communications between the client and server, and then creates a ticket to the server by encrypting an identifier for the client and the session key with the temporary secret key for the server. Next, the system assembles a message that includes the identifier for the server, the session key and the ticket to the server, and sends the message to the client in a secure manner. The system subsequently allows the client to forward the ticket to the server in order to initiate communications between the client and the server.

1. Field of the Invention
The present invention relates to providing security in communications across computer networks. More specifically, the present invention relates to a method and an apparatus for providing a key distribution center for clients and servers on a computer network that operates without having to store long-term server secrets.
2. Related Art
The advent of computer networks has led to an explosion in the development of applications that transfer information between computer systems across computer networks.
One problem with sending information across computer networks is that it is hard to ensure that sensitive information is kept confidential. This is because a message containing sensitive information can potentially traverse many different computer networks and many different computer systems before it arrives at its ultimate destination. An adversary can potentially intercept a message at any of these intermediate points along the way.
One way to remedy this problem is to "encrypt" sensitive data using an encryption key so that only someone who possesses a corresponding decryption key can decrypt the data. (Note that for commonly used symmetric encryption mechanisms the encryption key and the decryption key are the same key.) For example, a person sending sensitive data across a computer network can encrypt the sensitive data using the encryption key before it is sent across a computer network. At the other end, the recipient of the data can use the corresponding decryption key to decrypt the data.
Standards, such as Kerberos, have been developed to manage hundreds and potentially thousands of different keys that can be used to encrypt communications in a distributed computer system. Under Kerberos, a system can make use of a key distribution center (KDC) that stores a long-term secret for each principal in a domain. If a principal, Alice, wants to talk to another principal, Bob, Alice authenticates to the KDC, and then requests from the KDC a session key to use to talk to Bob as well as a "ticket to Bob". (Note that Alice can authenticate to the KDC using a password or long term secret. Alternatively, Alice can authenticate beforehand.) The "ticket to Bob" is a message to Bob encrypted with a secret shared between Bob and the KDC. This message includes Alice's name and the session key to be used in communicating between Bob and Alice. Alice can then send Bob this "ticket to Bob" in order to enable Alice to communicate with Bob using the session key.
Kerberos also specifies how to create a "ticket granting ticket" (TGT). In order for a workstation not to keep a principal's long term secret around for a long time, when a principal first logs on to a workstation (and presumably before he can start running potentially malicious software), the workstation requests a TGT from the KDC. This TGT is encrypted with a key known to the KDC and includes the principal's name and a session key to be used in communicating between the principal and the KDC. By using the TGT, the workstation is able, for the next several hours, to forget the principal's long-term secret and only needs to remember the session key and the TGT. Note that it is advantageous not to keep the principal's long-term secret on the workstation for a long period of time, because the long-term secret can potentially fall into the hands of an adversary who momentarily obtains access to the workstation.
Note that using a KDC introduces a security vulnerability because someone who captures the database used by the KDC has access to all of the principals' long-term secrets. Also note that long term secrets typically include principal's passwords and server's pre-shared keys. Hence, momentary compromise of the KDC can allow an unauthorized party to impersonate clients and servers until these long-term secrets are changed.
It is preferable for the KDC to only maintain public keys for the principals. These public keys can be used to encrypt messages so that only entities holding corresponding private keys (the principals) can decrypt the messages. Note that an adversary who captures a public key stored in the KDC is unable to decrypt a message encrypted with the public key. To this end, an Internet Engineering Task Force (IETF) draft entitled, "Public Key Cryptography for Initial Authentication in Kerberos" (http://search.ietf.org/internet-drafts/draft-ietf-cat-kerberos-pk-init-12.txt) discloses how users can initially authenticate to the KDC with public key cryptography by storing public keys for users at a KDC, or having users present a certificate.
Unfortunately, performing decryption using a private key is a computationally intensive task, which requires considerably more computational effort than performing decryption using a symmetric key. What is needed is a method and apparatus for facilitating encryption and decryption that provides the security of using a private key without sacrificing the performance of using a symmetric key.

Method and apparatus for providing a key distribution center without storing long-term server secrets


A stator core comprises a circumferentially deformable part formed on a radially outer peripheral side of a yoke; circumferentially facing divided parts formed on a radially inner peripheral side of the yoke, each having a dividing line that is oriented in a radial direction and reaches a portion between teeth and divided surfaces that face each other without a gap; and radially facing divided parts formed at the center between the radially inner and outer sides of the yoke along the circumferential direction at the predetermined interval, and each having divided surfaces that face each other in the radial direction, and being continuous at one ends with the respective circumferentially facing divided parts. The circumferentially facing divided parts each have a compressive stress being smaller than a compressive stress acting on the circumferentially deformable part or being zero.

Conventionally, there are ones disclosed in Patent Documents 1, 2 and 3 as illustrated in FIGS. 21 to 24. FIG. 21 is a front main part view illustrating a state of a stator core attached to a core case by shrink-fitting. FIG. 22 is a front main part view illustrating the stator core. FIG. 23 is a front main part view illustrating a state of a stator core attached to a core case by shrink-fitting. FIG. 24 is a sectional view illustrating a state of a stator core attached to a core case by shrink-fitting.
In all FIGS. 21 to 24, stator core segments 103A, 103B and 103C of stator cores 101A, 101B and 101C of motors are joined to form an annular shape and are received and fixed by shrink-fitting in core cases 105A, 105B and 105C.
Where, there is a problem that iron loss increases due to compressive stress generated in the stator core segments 103A, 103B or 103C at the time of the shrink-fitting so that output efficiency of a motor comes down.
To address this, the stator core 101A of FIGS. 21 and 22 has slits 101Aa made therein so as not to generate compressive stress, and the stator cores 10B and 103C of FIGS. 22 and 24 have holes 103Ba and 103Ba to reduce compressive stress.
However, the slits 101Aa and the holes 103Ba and 103Ca make an increase of magnetic resistance and result in a problem of deteriorating magnetic properties.
On the other hand, in the case of the slits 101Aa, it is conceivable to compressively deform contacting portions on the outer peripheral side toward a direction to eliminate the slits (circumferential direction) by the compressive stress.
However, only the deformation amount due to the distortion around the contacting portions on the outer peripheral side results in the small amount of the compressive deformation of the contacting portions, and it is physically difficult to eliminate the slit 101Aa.
Such a problem also exists in stator cores other than a divided-type stator core.    Patent Document 1: JP 2005-51941 A    Patent Document 2: JP 2009-261162 A    Patent Document 3: JP 2002-136013 A

Stator core of motor, and manufacturing method


Stereoscopic image display is described. In an embodiment, a location of the eye pupils of a viewer is determined and tracked. An image is displayed within a first focus for viewing with the left eye of the viewer, and the image is displayed within a second focus for viewing with the right eye of the viewer. A positional change of the eye pupils is tracked and a sequential image that corresponds to the positional change of the eye pupils is generated for stereoscopic viewing. In another embodiment, an image is displayed for stereoscopic viewing and a head position of a viewer relative to a center of the displayed image is determined. A positional change of the viewer's head is tracked, and a sequential image that corresponds to the positional change of the viewer's head is generated for stereoscopic viewing.

A conventional stereoscopic display system typically includes special glasses, a virtual reality helmet, or some other user attachable device. The user attachable device provides cues and feedback information corresponding to the relative position of a viewer to track positional changes of the viewer. The stereoscopic display system then displays an image for stereo viewing based on the positional feedback from the user attachable device.
Stereoscopic display systems can be implemented in gaming systems and other 3D ("three-dimensional") viewing systems to provide a stereo, or 3D, view of video images. While stereo viewing provides realistic and 3D interaction, many users would prefer to be unencumbered by a user attachable device that provides the user positional feedback to coordinate displaying the video images for stereo viewing. Accordingly, users of such stereoscopic display systems may prefer a system that locates and tracks a user without a user attachable device, such as special glasses or a virtual reality helmet.


The invention concerns a computer-implemented method for tracking and reshaping a human-shaped figure in a digital video comprising the steps: acquiring a body model of the figure from the digital video, adapting a shape of the body model, modifying frames of the digital video, based on the adapted body model and outputting the digital video.

Digital retouching of photographs is an essential operation in commercial photography for advertisements or magazines, but is also increasingly popular among hobby photographers. Typical retouching operations aim for visual perfection, for instance by removing scars or birthmarks, adjusting lighting, changing scene backgrounds, or adjusting body proportions. However, even commercial-grade image editing tools often only provide very basic manipulation functionality. Therefore, many advanced retouching operations, such as changing the appearance or proportions of the body, often require hours of manual work. To facilitate such advanced editing operations, researchers have developed semantically-based retouching tools that employ parametric models of faces and human bodies in order to perform complicated edits more easily. Examples are algorithms to increase the attractiveness of a face, or to semi-automatically change the shape of a person in a photograph.
While such semantically-based retouching of photographs is already very challenging, performing similar edits on video streams has almost been impossible up to now. Existing commercial video editing tools only provide comparatively basic manipulation functions, such as video object segmentation or video retargeting, and already these operations are computationally very demanding. Only a few object-based video manipulation approaches go slightly beyond these limits, for instance by allowing facial expression change, modification of clothing texture, or by enabling simple motion edits of video objects. The possibility to easily manipulate attributes of human body shape, such as weight, height or muscularity, would have many immediate applications in movie and video post-production. Unfortunately, even with the most advanced object-based video manipulation tools, such retouching would take even skilled video professionals several hours of work. The primary challenge is that body shape manipulation, even in a single video frame, has to be performed in a holistic way. Since the appearance of the entire body is strongly correlated, body reshaping solely based on local operations is very hard. As an additional difficulty, body reshaping in video has to be done in a spatio-temporally coherent manner.

Computer-implemented method and apparatus for tracking and reshaping a human shaped figure in a digital world video

MAX-PLANCK-GESELLSCHAFT ZUR FORDERUNG DER WISSENSCHAFTEN


A regenerative braking coordination device has a braking operating member receiving an input from a driver in the form of an operation amount, an input shaft operable for transmitting the operation amount, and a braking force boosting device operable to generate a hydraulic braking pressure corresponding to the operation amount transmitted by the input shaft. The device further includes a hydraulic pressure braking device to generate a braking force and an operation amount absorber for absorbing the operation amount of the input shaft. The operation amount absorber includes a cylinder, a piston dividing the interior of the cylinder into first and second hydraulic chambers and an orifice connecting the first and second hydraulic chambers. The orifice can be in the piston or in a flow channel.

Japanese Kokai Patent Application Number Hei 11[1999]-171287 discloses that when a high braking force is required for rapid braking, both regenerative braking and friction braking are performed in order to guarantee the rapid braking response. The depression speed of the brake pedal is detected, and the higher the detected depression speed is, the smaller the proportion of the regenerative braking force is provided. The stroke speed (operating speed) of the brake pedal is detected from the moment that the brake pedal is depressed. When the operating speed becomes high enough, the friction braking proportion is increased.

Regenerative braking coordination device


A computer program product and/or system for determining storage requirements includes means for receiving a plurality of files to be stored, means for classifying the plurality of files based on business value, means for classifying the plurality of files based on contractual obligations, means for classifying the plurality of files based on empirical characteristics, and determining a storage medium based on the classified business value, classified contractual obligation, and classified empirical characteristics. The system further includes means for determining storage requirements based on the determined storage mediums, means for determining a normalization factor, means for determining a product of the determined normalization factor and summed individual used storage capacity, means for determining at least one secondary information class based on the product, and means for storing at least one of the received plurality of files based on the determined storage medium.

1. Field of the Invention
The present invention generally relates to information life cycle management. More specifically, the invention relates to methods for developing information life cycle management policies and solutions on an enterprise level.
2. Description of the Related Art
The ability to store increasing amounts of data leads to spiraling information life cycle management problems. Even as storage media are able to store an increasing amount of data at decreasing cost on a per unit basis, the growth in data collection results in undesirable data storage costs.
As information technology management objectives shift to include cost control efforts, an increased emphasis on IT environment optimization has been felt in many IT departments. Controlling information becomes a higher priority as the strategic alignment of business with IT becomes increasingly defined and mature. Indeed, many IT budgets have storage as the largest line item, resulting in increased pressure to contain storage costs. In response to increasing cost pressures, IT management is driven to review the information itself.
It is therefore a challenge to develop a method to develop information life cycle strategies to overcome these, and other, disadvantages.

Developing enterprise information life cycle management policies and solutions


A three-dimensional geometry processing system and method for converting boundary representations solid data in a first format into output solid data in a second format which includes a surface conversion and division mechanism configured to convert surface information in the boundary representations solid data into geometry data, and divide a surface which needs to be divided according to restriction of the second format to generate topology information of the divided surfaces, a topology information addition mechanism configured to map topology information of the boundary representations solid data to the topology information of the divided surfaces, and a surface join mechanism configured to join the divided surfaces based on the mapped topology information to generate the output solid data in the second format.

1. Field of the Invention
The present invention relates to a three-dimensional geometry processing system and method, and more particularly to a three-dimensional geometry processing system and method for a solid computer-aided design (CAD) apparatus restricted in surface representations to import solid data in boundary representations.
2. Discussion of the Background
Practical three-dimensional computer-aided design (CAD) apparatuses mainly deal with solid data. Most of the three-dimensional CAD apparatuses deal with the solid data in boundary representations. The three-dimensional CAD apparatuses generally exchange data in a standard format such as IGES. Generally, when the standard format is used for data exchange, a system which receives data joins surfaces to generate solid data from information on surfaces only. Recently, solid data can be represented in the standard format, and the solid data can be exchanged as is.
Exchanging solid data mainly involves two technical difficulties. The difficulties are related to accuracy and restriction in representations of a CAD apparatus for receiving data. When the CAD apparatus has relatively high accuracy, there can be an exchanging data problem related to accuracy. However, a modification mechanism has been developed to overcome the difficulty related to accuracy. For example, a solid data modification method is available. In the solid data modification method, when there is a deviation from a tolerable range of a target system or a gap at a vertex portion or between a boundary curve and a surface, the gap between an end point and another end point, or between the boundary curve and the surface is filled so that data can be within the tolerable range of the target system having high accuracy. In detail, coordinates of end points of boundary curves of faces representing a shell of a solid are expected to meet at the vertex portion. When the gap between the coordinates is out of the tolerable range of the target system, however, a coordinate of a vertex is determined within the tolerable range based on the end points of the boundary curves gathering at the vertex portion and information of coordinates on a surface corresponding to the end points. Then, the boundary curves are modified so as to have the coordinate of the vertex as the end points thereof. Further, when the gap between the boundary curve and the surface is out of the tolerable range, a geometry of the surface is changed so that the boundary curve and the surface mate within the tolerable range of the target system.

Three-dimensional geometry processing system and method for CAD apparatus restricted in surface representations to import solid data


An Internet protocol based system and method facilitate communication and improve the overall network performance between remote user terminals and Web servers across the parts of the Internet (or IP-based Intranets), that are configured by a communications network, including an asynchronous transfer mode (ATM) network. In particular, the system includes a plurality of Local Area Networks (LANs), such as Ethernet LANs, each comprising a plurality of user terminals or PCs. The system further comprises at least one network switch (such as an ATM switch), and at least one digital subscriber line (xDSL) access router, each connected between a corresponding LAN and the network switch. The xDSL access routers function both as a router and a digital subscriber line multiplexor. Thus, each user terminal communicates directly with its default router, and vice-versa, obviating the requirement of communicating via the network switch (e.g., ATM switch) to the default IP edge routers. Further, in the case where Quality of Service is required, the xDSL access router serves as the default router for the Web server, and the physical path between the Web server and the terminal can be minimized to one pass through the network switch and thereby reducing traffic through the communications network.

The present invention relates generally to an Internet protocol (IP) based system, and more particularly, to an IP based system that facilitates communication and quality of service (QoS) between remote user terminals and Web servers across parts of the Internet that are configured by an asynchronous transfer mode (ATM) network or other communication networks.
An asynchronous transfer mode network is a network that can transfer information from one or more sources to one or more destinations. The ATM network can be deployed for configuring parts of the Internet, thus comprising a communication network. The communication network itself may be composed of multiple communicating nodes (e.g., terminals, routers, servers, switches, etc.) that are interconnected to each other by physical communication links (wires, cables, optical fibers, RF channels, etc.). An ATM-equipped node transmits a signal containing a bit stream to an adjacent node via the communication link that connects the two adjacent nodes. The transmitted bit stream is organized into fixed sized packet or xe2x80x9ccellxe2x80x9dslots for carrying, e.g., 53 byte packets called cells. Illustratively, each cell has a 5 byte header for communicating control information, and a 48 byte payload for communicating a message to be conveyed between nodes. A node allocates a xe2x80x9cvirtual channelxe2x80x9d to each communication, which, amongst other things, identifies an adjacent node to which cells of the communication must be transmitted. A sequence of virtual channels of nodes on a path between a source node and a destination node identifies a virtual channel connection.
The source node transmits cells to the destination node via this sequence of virtual channels, i.e., from node to node on the path, in a bucket brigade like fashion. Prior to transmitting the information, the source node segments the information into 48 byte sized messages and appends a 5 byte header to each such message to form a cell. The source node writes a virtual address, such as a virtual channel identifier, which enables each node on the path that receives the cell to determine the outgoing virtual channel on which to transmit the cell. A destination node receiving the cells extracts the messages from the payloads and reassembles the messages (in the appropriate order) into the originally transmitted information.
It is important to note that, when communicating between Local Area Networks (LANs) (such as Ethernets) on the Internet which is configured by various links and networks including the ATM network, the data-link layer communications in LAN networks are different than those in the ATM networks. Thus, bridges are utilized to receive information from one network (e.g., LAN) transmitted according to the respective data-link layer and retransmit the information in the other network (e.g., ATM network) according to its respective data-link layer. In other words, bridges decouple the two incompatible data-link layers from each other, yet enable communication between nodes in each of the two networks.
At the network layer, all of the nodes may communicate using the same protocol, e.g., the Internet protocol (IP). Like the Ethernet protocol, each node that can serve as a source or destination node is assigned an IP identifier, or IP address. Information is transmitted from a source node to a destination node in a bit stream that is organized into packets. As previously stated, each packet has a header and a payload. The IP address of the source node is written in a source field of the packet header, and the IP address of the destination node is written in a destination field of the packet header. The data is then written in the payload. The packet is then transmitted according to the appropriate data-link layer protocol for the network (e.g., formed into Media Access Control (MAC) frames, divided into ATM cells, etc.) and then transmitted to its respective destination node. IP provides a routing function for routing a packet from node to node in a sequence of nodes until the packet arrives at its destinations using routing tables.
Such communications networks are becoming increasingly important vehicles for delivering video, audio and other data to and from remote user terminals. For example, such networks are used to support video-on-demand, near video-on-demand, and pay-per-view applications. However, problems are evident in terms of adequate bandwidth.
Typically, wideband (1-10 Mb/s) access technologies are relatively expensive and specialized (such as T1 lines), such that their use has been primarily by large institutional customers, such as large corporations, universities, and government agencies. However, a number of new network access technologies are now moving from the research labs into general availability. For example, some network providers have started to deploy hybrid fiber coax access lines, as well as cable modems. Further, trials and limited deployments of a variety of Digital Subscriber Line (xDSL) (e.g., Asymmetrical Digital Subscriber Linesxe2x80x94ADSL) technologies are also ongoing. All of this activity is intended to bring broadband networks to the mass market. The ATM network, as previously described, is intended to xe2x80x9cbridge the gapxe2x80x9d in providing wideband transmission rates to a remote user in an Internet environment.
A conventional IP based system is shown in FIG. 1. System 10 includes groups 12a, 12b through 12N of remote user terminals 15, where each group is part of an Ethernet or other LAN system. Each group 12a, 12b through 12N is connected to a respective Ethernet bridge, illustratively an Asymmetrical Digital Subscriber Line (ADSL) termination unitxe2x80x94remote side (as opposed to a central office side) ATU-R 18a, 18b through 18N, respectively, for providing an Ethernet bridge between the LAN system and the respective default IP router. ATU-Rs 18a, 18b, 18c through 18N are also connected to respective telephones 16a, 16b, 16c through 16N.
System 10 further includes a plurality of ADSL based Digital Subscriber Line Access Multiplexors (DSLAM) 20a through 20N, each of which is connected to a plurality of ATURs. Each DSLAM provides basic transport and multiplexing functions between each respective ATU-R 18 and an ATM switch 22. ATM switch 22 is further connected to a plurality of Web servers 28a through 28N, IP edge routers 26a through 26N and IP backbone router 24 for connection to the Internet. The function of each will be described below.
First, we describe the ADSL technology. ADSL was motivated by the goal of achieving wideband transmission rates over existing copper loops. The concept has achieved a growing acceptance by the telecommunications industry and resulted in a standardization effort.
The main idea behind ADSL is that overlapping parts of the spectrum should be present only for signals that are propagating in the same direction within a single bundle of copper wire pairs. This approach reduces the effect of near-end and far-end crosstalk, and hence makes wideband transmission rates feasible for reasonably large loop lengths (up to 18,000 ft). Several characteristics of traditional ADSL systems are specifically tailored to their intended application in residential local loops. These include the asymmetry of bandwidth and the support for life-line telephony as an inseparable component. Note that ADSL technology is suitable for Internet access service. For example, a 10 baseT (10 bT) interface is located at the ATU-R for personal computer protocols.
A DSLAM is utilized in the IP based system to support ATM bearer service for IP applications. In an ATM bearer service scenario, the interface on the user side is configured as an ATM user to network interface over an ADSL. On the ATM network (trunk) side, the interface is configured as a network to network interface over a synchronous optical network (SONET) transport. Typically, DSLAMs are located in the central office; however they can also be remote such that they are connected over significant distances by single mode fiber links.
DSLAMs support life-line telephony and an asymmetric high/low speed data channel. The DSLAM upstream data channels typically support data rates of 9.6-156 kb/s. The downstream bit rate is either fixed or distance-dependent. For some early commercial products, a 2.3 Mb/s rate was specified for distances of no more than 3 km, and about 4 Mb/s can be supported over loops shorter than 4 k m.
The number of subscriber lines per OC-3c trunk is a function of the Quality of Service (QoS), which is required from the ATM bearer service to support the target set of applications. Each OC-3c interface on the ATM network side of the DSLAM provides a line rate of 155.52 Mb/s, giving an effective ATM cell rate close to 150 Mb/s, which leaves an effective bit rate of about 135 Mb/s. If, for example, a non-blocking streaming service is supported for video applications of a constant bit rate of 2.5 Mb/s, then a DSLAM can be configured to support 48 ADSL lines (2.5 Mb/sxc3x9748=120 Mb/s). Note that DSLAMs have been designed to provide access to a broadband backbone, characterized by the ATM transport service on the top of the SONET broadband digital hierarchy.
As described above, ADSL-based DSLAMs provide subscriber line multiplexing functionality for Internet Protocol based system. As shown in FIG. 1, DSLAMs 20 crossconnect the user terminals 15 or Ethernet 12 to the IP edge routers 26, via ATM switch 22.
A conventional router suffers performance degradation due to processing overloads since it typically support a large population of users. Accordingly, it is common for the router administrators to turn off some important functions (e.g., packet filtering, RSVP, etc.) to improve the router performance.
FIG. 2 illustrates the protocol stack for the system of FIG. 1. As shown, protocol stack 30 from the user terminals (or PCs) 15 includes a network layer, a data link layer and the physical or PHY layer. The network layer comprises the IP which includes the destination and source addresses, the data link layer comprises the link layer control (LLC) and media access control (MAC) which includes information pertaining to when to transmit and how to construct the frame, and the PHY comprises the 10bT which represents a 10 MHz NRZI signal.
Protocol stack 32 from the ATU-Rs 18 consists of ADSL layer (physical and data link), ATM, and ATM adoption layer (AAL) on the DSLAM side and 10bT and MAC layer on the user side. Protocol Stack 38 at the IP Router includes the SONET, ATM, AAL, and LLC on the ADSL (user) side and SONET, ATM, and AAL on the network side. Protocol stack 34 from the DSLAM comprises ATM and ADSL on the user side and ATM and SONET on the network side. The ATM switch 22 maintains the layer protocols. Protocol stack 38 provides simulation of the Ethernet bridge on the user side by injecting the LLC-layer.
An example of the operation of the conventional Internet based system 10 is as follows. Consider that Web server 28a wishes to communicate with user terminal 15 that resides on LAN 12b. Now, depending on which IP edge routers are assigned to Web server 28a and to this terminal, there will be at least two passes of the data packets through the ATM switch 22. Consider a best case scenario in which Web server 28a and terminal 15 on LAN 12b are both assigned to IP edge router 26N. Thus, the minimum path between Web server 28a and terminal 15 on LAN 12b must include a link from Web server 28a to IP edge router 26N through ATM switch 22. Then a link must be established from IP edge router 26N, through ATM switch 22, to LAN 12b, via DSLAM 20a. This path passes twice through ATM switch 22, thus contributing to traffic. Of course, if the Web server and terminal were assigned to different IP edge routers, then a minimum of three passes through ATM switch 22 are necessary, since an additional link would also have to be established from the IP edge router assigned to the terminal and the IP edge router assigned to the Web server via the ATM switch 22.
Note that under the architecture of FIG. 1, the DSLAMs functionality are limited to providing transport and multiplexing functions. The IP edge routers, in addition to the IP routing mechanism, provide the Ethernet bridging capability in order to be able to address the user""s LANs. Accordingly, the system of FIG. 1 suffers from a number of performance deficiencies.
Specifically, the IP edge routers become bottlenecks due to the large amount of processing that they have to perform on in-bound and on out-bound packets. It becomes tw difficult to support QoS in the routers since the bandwidth and processing resources are in a deficit. Consider if a user requires a stream of video information to be transmitted from a Web server, then this stream needs to follow a path from the Web server to an appropriate edge router, take one or more hops between the Web server""s edge router and the edge router to which the user is assigned, and then follow a path from the edge router assigned to the user to the user terminal. Only then will the stream of video information reach the user""s LAN.
Another disadvantage is that the Address Resolution Protocol (ARP) mechanism requires the router to broadcast the address to be resolved on the LANs. Thus, since the router simulates the LAN bridge, the ARP must be transmitted over the ATM network. Accordingly, additional traffic is added on the ATM network.
It is therefore an object of the present invention to overcome the deficiencies evident in the prior art.
An aspect of our present invention is an Internet protocol based system and method for facilitating communication and improving communications between remote user terminals and Web servers across parts of the Internet configured by a communications network, such as an ATM network.
The system includes a plurality of LAN networks, such as Ethernet LANs, each comprising a plurality of user terminals or PCs. The system further includes a network switch, illustratively an ATM switch, and at least one digital subscriber line (xDSL) access router, each connected between a corresponding LAN and the network switch. The xDSL be (e.g. ADSL) access routers function both as a router and a digital subscriber line multiplexor. Thus, each user terminal can communicate directly with its default router, and vice-versa, obviating the requirement of communicating with its default router via the ATM switch and reducing traffic in the ATM network.
In addition, the IP based system further comprises at least one bridge, such as an ADSL termination unit (ATU-R), each coupled between a respective LAN and a respective xDSL access router. Further, the IP based system further comprises an IP backbone router for connecting the ATM-configured network to the rest of the Internet.
Because each xDSL access router of our inventive IP based system supports a relatively small number of customers (from a few tens to a few hundreds), vis-a-vis an IP edge router, the xDSL access router can process traffic more efficiently and with far less risk of overload. In contrast, conventional routers suffer performance degradation due to processing overloads since they support much greater populations of users. Accordingly, it is common for the router administrators to turn off some important functions (e.g., packet filtering, RSVP, etc.) to improve the router performance.
In special situations, when uncompromised QoS is required (e.g., for Video On Demand Applications) the xDSL access router could serve as the default router for specialized Web servers, thus allowing direct connections from user terminals to the Web servers for better support of the IP QoS by utilizing any kind of the QoS mechanism (e.g. based on RSVP protocol) which typical servers do not utilize due to traffic constraints.


The present invention relates to modular assemblies and systems for conducting cell analyses. In particular embodiments, an assembly has micron-scale fluidic structures, thereby minimizing sample use, and possesses a modular architecture that facilitates disassembly of the apparatus. Thus, one such modular assembly facilitates on-chip cell growth and on-chip assays; and then, as needed, the assembly can be disassembled to provide direct access to the cells that were incubated and treated within the chip. Methods of making and using such assemblies, as well as systems thereof, are further described herein.

Complex cell interactions provide key insights into organ and tissue function. Yet, such interactions are difficult to elucidate in vivo. In vitro platforms are an attractive alternative that simplifies testing, while providing viable mechanistic correlations that can be later confirmed by way of in vivo testing. Various monolithic in vitro platforms have been developed, in which the components of the platform are sealed together, thereby providing limited direct access to cells that were grown or tested within the platforms. Direct access, at times, would be helpful, e.g., such as to conduct additional laboratory-scale testing on a certain cell colonies or subpopulations of cells. In addition, platforms having simplified architectures are desired, thereby allowing the platforms to be employed without the use of specialized training or complicated equipment. Accordingly, there is a need for simplified platforms that can be used to study cell interactions, while also providing direct access to such cell populations.

Modular assemblies and systems for cell cultures and methods thereof

National Technology & Engineering Solutions of Sandia, LLC


A method of providing microelectromechanical structures (MEMS) that are compatible with silicon CMOS electronics is provided. The method provides for processing and manufacturing is steps limiting a maximum exposure of an integrated circuit upon which the MEMS is manufactured during MEMS manufacturing to below a temperature wherein CMOS circuitry is adversely affected, for example below 400° C., and sometimes to below 300° C. or 250° C., thereby allowing direct manufacturing of the MEMS devices onto electronic integrated circuits, such as Si CMOS circuits.

Microelectromechanical systems (MEMS) are small integrated devices or systems that combine electrical and mechanical components. The components can range in size from the sub-micrometer level to the millimeter level, and there can be any number, from one, to few, to potentially thousands or millions, in a particular system. Historically MEMS devices have leveraged and extended the fabrication techniques developed for the silicon integrated circuit industry, namely lithography, doping, deposition, etching, etc. to add mechanical elements such as beams, gears, diaphragms, and springs to silicon circuits either as discrete devices or in combination with integrated silicon electronics. Whilst the majority of development work has focused on silicon electronics additional benefits may be derived from integrating MEMS devices onto other existing electronics platforms such as silicon germanium (SiGe), gallium arsenide and, indium phosphide for RF circuits and future potential electronics platforms such as organic based electronics, nanocrystals, etc.
Examples of MEMS device application today include inkjet-printer cartridges, accelerometers, miniature robots, micro-engines, locks, inertial sensors, micro-drives, micro-mirrors, micro actuators, optical scanners, fluid pumps, transducers, chemical sensors, pressure sensors, and flow sensors. New applications are emerging as the existing technology is applied to the miniaturization and integration of conventional devices. These systems can sense, control, and activate mechanical processes on the micro scale, and function individually or in arrays to generate effects on the macro scale. The micro fabrication technology enables fabrication of large arrays of devices, which individually perform simple tasks, or in combination can accomplish complicated functions.
The MEMS market is currently projected to exceed US $10 Billion in 2011, doubling from its estimated 2005 revenues of $5 Billion, according to Semiconductor Partners (Phoenix) ("Driving MEMS beyond Automotive" September 2007). Whilst historically the automotive MEMS market has dominated and will still show robust growth as the number of MEMS devices per vehicle increases from an average of 40 per mid-range vehicle to ˜60 MEMS for the same class of vehicle in 2011, it is the potential for growth in the consumer, communication and portable device markets that is more significant. Such applications include monolithic microphones and loudspeakers, oscillators, handheld controls for gaming devices and cellular telephones, hard disk drives, RF switches and ink-jet print heads. The MEMS mobile cellular telephone market alone is expected to exceed US $0.5 Billion in 2008 according to Research and Markets ("Mems4Mobile 06: Updated Analysis of the Applications and Markets of MEMS in Mobile Communications" February 2006). Such MEMS devices incorporated into cellular telephones potentially including silicon microphones, 3D accelerometers, gyroscopes for camera stabilization and GPS navigation, microfuel cells, personal weather stations, and biochips for health care monitoring.
MEMS have become a successful sensing and actuating technology. Because of their extensive optical, electrical to mechanical functionalities, MEMS devices are suited to applications in many different fields of science and engineering. However, because of this vast range of functionality, MEMS fabrication processes, unlike the microelectronics industry, are difficult to gear towards general applications. As a result most processes are aimed at the fabrication of a few devices, and usually performance of the devices is hindered by process variability. As MEMS devices are typically sensing weak analog signals, for example pressure, acceleration, vibration, magnetic or electric fields, with capacitive based elements, there is considerable benefit in being able to integrate analog front-end electronics to buffer, amplify and process these weak electronic signals and either facilitate their direct processing, such as with RF signals, or their digitization for sensing and measurements applications.
Historically CMOS electronics has become the predominant technology in analog and digital integrated circuits. This is essentially because of the unparalleled benefits available from CMOS in the areas of circuit size, operating speed, energy efficiency and manufacturing costs which continue to improve from the geometric downsizing that comes with every new generation of semiconductor manufacturing processes. In respect of MEMS systems, CMOS is particularly suited as CMOS circuits dissipate power predominantly during operation and have very low static power consumption. This power consumption arises from the charging and discharging of various load capacitances within the CMOS circuits, mostly gate and wire capacitance, but also transistor drain and transistor source capacitances, whenever they are switched. The charge moved is the capacitance multiplied by the voltage change. Multiply by the switching frequency to get the current used, and multiply by voltage again to get the characteristic switching power, P, dissipated by a CMOS device, and henceP=CV2f  (1).
Historically, CMOS designs operated at supply voltages (Vdd) much larger than their threshold voltages (Vth), for example Vdd=5V and Vth=700 mV for both NMOS and PMOS. However, today CMOS manufacturers have adjusted designs and materials such that today an NMOS transistor may have a Vth of 200 mV and allow operation from voltages as low as Vd=1V offering a significant power reduction which is important in sensing, mobile, chemical and biomedical applications.
However, combining CMOS and MEMS technologies has been especially challenging because some MEMS process steps—such as the use of special materials, the need for high temperature processing steps, the danger of contamination due to the MEMS wet etching processes etc.—are incompatible with the requirements of CMOS technology. Thus, strong attention has to be paid to avoid cross contaminations between both process families. Accordingly today MEMS processes exist that are discrete and standalone, such as Robert Bosch's (U.S. Pat. No. 5,937,275 "Method of Producing Acceleration Sensors", MEMSCAP's "Multi-User MEMS Processes" (MUMPs® including PolyMUMPs™, a three-layer polysilicon surface micromachining process: MetalMUMPs™, an electroplated nickel process; and SOIMUMPs™, a silicon-n-insulator micromachining process), and Sandia's Ultra-planar Multi-level MEMS Technology 5 (SUMMiT V™ Fabrication Process which is a five-layer polycrystalline silicon surface micromachining process with one ground plane/electrical interconnect layer and four mechanical layers).
Other processes have been developed to allow MEMS to be fabricated before the CMOS electronics, such as Analog Devices' MOD-MEMS (monolithically integrate thick (5-10 um) multilayer polysilicon MEMS structures with sub-micron CMOS), and Sandia's iMEMS. Finally, processes have been developed to provide MEMS after CMOS fabrication such as Sandia's micromechanics-last MEMS, Berkeley Sensor & Actuator Center (BSAC), and IMEC silicon-germanium processes. Additionally DALSA Semiconductor have a highly publicized "low temperature" micro-machining with silicon dioxide process, see L. Ouellet et al (U.S. Pat. No. 7,160,752 "Fabrication of Advanced Silicon-Based MEMS Devices", Issued Jan. 9, 2007) wherein low stress structures were fabricated at temperatures between 520° C. and 570° C., being just below the temperature of eutectic formation in aluminum-silicon-copper interconnections.
However, the mechanical properties of silicon do not make it the most suitable structural material for MEMS. Recently, silicon carbide (SiC) has generated much interest as a MEMS structural material because of its distinctive properties. SiC boasts better suited mechanical properties such as higher acoustic velocity, high fracture strength and desirable tribological properties. Its ability to sustain higher temperatures, and resist corrosive and erosive materials makes SiC, unlike silicon, a potential candidate material for use in harsh environments. SiC is also being investigated and shows promise as a biocompatible material, see for example "Porous Silicon Carbide as a Membrane for Implantable Biosensors" (A. J. Rosenbloom et al, Biomedical Microdevices, Vol. 6, No. 4, December 2004, Springer), "Biocompatibility of Silicon Carbide in Colony Formation Test in Vitro" (S. Santavirta et al, Archives of Orthopedic and Trauma Surgery, Vol. 118, Nos. 1-2, November 1998), and "SiC Based Artificial Dental Implant" (U.S. Pat. No. 5,062,798, K. Tsuge et al). These factors, along with the maturation of deposition and patterning techniques, make SiC a potential choice for high-performance MEMS processing.
However, difficulties with SiC processing have made its use non-trivial as it is non-conductive and difficult to deposit and dope at CMOS compatible temperatures. Stress control is also difficult because of the high intrinsic stresses that can develop in such a material. Because of its intrinsic inertness, selective etching of SiC is difficult. As most materials are etched at a faster rate than SiC, issues arise when masking SiC for patterning and ensuring a reliable etch-stop. Whether it is for doping or for deposition, SiC needs to generally be processed at high temperatures. As such prior art SiC MEMS processes have not lent themselves well to CMOS integration. Further as most MEMS applications require electrical signal processing, integration of MEMS to transistor-able processes, such as CMOS, is paramount.
It would be advantageous to overcome at least some of the disadvantages of the prior art.

Low temperature ceramic microelectromechanical structures

The Royal Institution for the Advancement of Learning/McGill University


A permanently implanted insulin pump or combined insulin and glucagon pumps, controlled by a valve that expands and contracts due to osmosis as a result of changes in the blood sugar level. The valve is constructed from tissues harvested or grown from the patient's body tissues to prevent rejection, infection or thrombosis. It operates the pump(s) though a blood vessel via a magnetic strip within the valve tissue and a reed switch located outside the blood vessel. The pump battery is recharged by electromagnetic induction in response to low battery warnings. Glucagon and/or insulin are refilled in response to low-level warning indicators, using self-sealing septa located near to the surface of the skin.

This invention is a medical device principally for the treatment of insulin dependent diabetes (IDDM).
IDDM is an autoimmune disease of the pancreas, which results in the destruction of the Islets of Langerhans (IL). The IL contains two main types of endocrine cells: alpha cells which produce glucagon and beta cells which produce insulin. These antagonistic hormones increase and lower the blood sugar level (BSL) respectively, thereby keeping the BSL within the optimum range of 4 to 7 mmols per liter.
IDDM is generally treated by daily injections of insulin. As this involves the release of predetermined amounts of insulin into the bloodstream, however, the amount of carbohydrate (CHO) and exercise have to be carefully balanced against this to avoid the BSL going too low (hypoglycaemia) or too high (hyperglycaemia).
To maintain a reasonable balance many diabetics have to take several injections and blood tests a day. Even with close monitoring, however, hypoglycaemic episodes ('hypos') are virtually impossible to avoid altogether, and these are particularly dangerous during sleep, as they can quickly lead to unconsciousness or even coma.
If a diabetic's BSL is particularly erratic, an insulin pump may be used instead of traditional injections to provide a steadier release of insulin into the bloodstream. Some of the latest insulin pumps also employ a glucose sensor, which monitors the BSL to determine when and how much insulin should be released. The sensor works by detecting changes in the level of glucose in the interstitial fluid found between the body's cells (IFSL), and then feeding this information to a microprocessor.
One difficulty with existing insulin pumps is that they are situated outside the body, to allow the battery to be recharged and insulin and sensor parts to be replaced. As a result, there is a risk of infection at the insertion sites of the pump and the glucose sensor. There is also a risk that parts of the pump may become detached during sleep, and restless nights are not uncommon, particularly when there are problems with a diabetic's BSL. In addition, it may not be practical to keep the pump on all of the times during the day, for example when washing, swimming, during intimacy, or when taking part in certain sports.
The main problem with insulin pumps that employ glucose sensors is the inevitable delay between changes in the BSL and the IFSL. To compensate for this, the glucose sensor is controlled by a complicated computer programme, which requires data to be input regularly regarding BSL readings and the amount of exercise and CHO taken. Even with these safeguards, however, it is impossible to rule out hypos altogether, which may be acerbated if the pump continues to deliver insulin when the BSL is already dangerously low.
One final problem with pumps is something known as ketoacidosis, a potentially dangerous condition that can arise as a result of hyperglycaemia. It is known that the risk of ketoacidosis is higher with insulin pumps, as they cannot use longer-acting insulins, which provide some protection against this condition.
These problems with the conventional treatments of IDDM have led researchers to consider creating beta cells from a person's T cells and then implanting them in the patient's body. The new beta cells would then secrete insulin in response to changes in the BSL, removing the need for injections or insulin pumps altogether.
To date, techniques for growing large numbers of beta cells are still at a relatively early stage. In addition, as IDDM is an autoimmune disease, there is a high risk that the diabetic's immune system would destroy cells that were identical to the original beta cells. As a result, the implanted cells would have to be protected with a durable coating, which contained microscopic pores that were large enough to let insulin out but small enough to prevent the body's defence systems from entering. Although some protective coatings have been developed, these are also still some way from being perfected.
As with U.S. Pat. No. 4,538,616 of 3 Sep. 1985, this invention employs the principle of osmosis to drive the sensor mechanism. The former device failed, however, due to problems associated with placing a foreign body in the bloodstream, which were highlighted in International Patent WO 98/28605 of 2 Jul. 1998.
U.S. Pat. No. 4,538,616 also contemplated the use of a membrane that was impermeable to other solutes that affect the osmotic pressure of the blood, in particular sodium chloride and sodium lactate. As a result, the device could be adversely affected by changes in osmotic pressure caused by variations in these solutes.
Since U.S. Pat. No. 4,538,616, osmotic devices to control blood sugar level have been designed for use outside the blood stream. International Patent WO 98/28605 of 2 Jul. 1998, therefore, involved an osmotic transducer solely for use in the body tissues. It also does not overcome the problems created by other substances that can affect osmotic pressure, in particular sodium lactate. The device cannot therefore be used when lactic acid rises, e.g. during hard exercise (page 17, line 25).
International Patent WO 91/04704 A of 18 Apr. 1991 suggests an alternative mechanism for measuring osmolality, which would isolate changes in osmotic pressure that were caused by glucose alone. However, this sensing device is made of synthetic substances, and is therefore only suitable for use in the body tissues ('interstitial regions'), as opposed to the bloodstream.
International Patent WO 03/061475 A is very similar to International Patent number WO 91/04704 A, but uses a more sophisticated arrangement of valve chambers to minimise the effects of bio-fouling (page 3, lines 11-13). Once again, therefore, it could not be used in the bloodstream for any length of time.


Polymer microparticles having immobilized therein a water-insoluble substance such as oil-soluble dyes or pigments are produced by a method which includes the steps of forming droplets of a solution of a self-emulsifiable resin in a nonaqueous solvent containing the water-insoluble substance and an ethylenically unsaturated monomer suspended in an aqueous medium, and then allowing the monomer in the droplets to polymerize in situ.

Heretofore water-based inks used in various writing intruments such as founting pens, felt pens, or draftman's pens as well as those used in ink-jet plotter or printer machines for information recording purposes have the conventionally contained a water-soluble dye. Such water-based inks containing water-soluble dyes, however, have the defect that when writing or printing with such inks, letters or printed objects may often become blurred. Furthermore, they are not water-resistant and durable even after drying. Japanese Kokai (laid open) Patent Application No. 172076/87 discloses a water-based ink produced by adding an oil-soluble dye dissolved in an organic solvent to an aqueous suspension of a water-insoluble polymer, and allowing the oil-soluble dye to diffuse into the polymer particles. According to this technique, however, it is not possible for the polymer particles to carry an amount of dyes desirable for imparting the ink with optimal chromatic parameters. This is because the diffusion coefficient of particular dyes is the limiting factor. Japanese Kokai (laid open) Patent Application No. 273274/87 proposes a water-based ink employing pigments as a colorant. This ink comprises a polymer dispersion produced by emulsion polymerizing monomers in the presence of a protective colloid but the polymer particles themselves are discrete from the pigment particles. Thus, they are susceptible to phase separation upon storage.
A need exists for a water-based ink which eliminates or ameliorates various defects of the prior art water-based inks noted as above.

Production of polymer microparticles having water-insoluble chemicals immobilized therein