A plasma display device includes a first substrate, an address electrode formed on an upper surface of the fist substrate, a first dielectric layer formed on the upper surface of the first substrate and embedding the address electrode, a second substrate which is transparent and forms a discharge space by being coupled to the first substrate, a plurality of maintaining electrodes formed on a lower surface of the second substrate to form a predetermined angle with the address electrode, each of the maintaining electrodes including first and second electrodes, a second dielectric layer formed on the second substrate where the maintaining electrodes are formed and embedding the maintaining electrodes, at least a portion where an electrical field is concentrated formed between the first and second electrodes constituting the maintaining electrodes, and a partition installed between the first and second substrates for sectioning the discharge space.

1. Field of the Invention
The present invention relates to a plasma display device, and more particularly, to a plasma display device having an improved dielectric layer in which a maintenance electrode is embedded and a method of manufacturing the same.
2. Description of the Related Art
A general discharging device includes at least a pair of electrodes and discharge is generated when a voltage is applied to the electrodes. As an example of the discharging device, there is a discharge lamp such as a fluorescent lamp, a gas laser generating apparatus, and a plasma display device.
Due to superior display performance such as large display capacity, high brightness, high contrast, and wide viewing angle, the plasma display device is widely recognized as a flat panel display panel having a performance close to a cathode ray tube.
Plasma display devices are classified as a direct current plasma display device panel and an alternating current plasma display panel according to operation principle. Also, the plasma display device is divided into an opposing discharge type and a surface discharge type according to the configuration of the electrodes.
FIG. 1 is a view showing an example of a surface discharge type plasma display device.
As shown in the drawing, a plasma display device includes a substrate 10, an address electrode 11 on the substrate 10, a dielectric layer 12 on the substrate 10 where the address electrode 11 is located, a partition 13 on the dielectric layer 12 for maintaining a discharge distance and preventing electrical and optical cross talk between cells, and a front substrate 16 coupled to the substrate where the partition 13 is located and having maintaining electrodes 14 and 15 in a predetermined pattern on the bottom surface, crossing the address electrode 11. A fluorescent layer 17 is located at at least one side inside a discharge space sectioned by the partition 13. A dielectric layer 18 and a protective layer 19 in which the electrodes are embedded are located on the bottom surface of the front substrate 16. A discharge gas mixed with neon (Ne) and xenon (Xe) is injected into the discharge space.
In the plasma display device having the above structure, driving methods are divided into driving for an address discharge and driving for a maintaining discharge. The address discharge is generated due to an electrical field between the address electrode 11 and the maintaining electrode 14 (80V−(−170V)=250V). At this time, wall charges are formed. The maintaining discharge is generated due to a difference in electrical potential between the maintaining electrodes 14 and 15 disposed at the discharge space where wall charges are formed. The maintaining discharge becomes a main discharge for displaying an actual image.
The maintaining discharge generated due to a difference in electrical potential applied between the maintaining electrodes 14 and 15 becomes weak as time passes. This is because the initial discharge voltage must be over 160 V, in general, since the distance between the maintaining electrodes 14 and 15 is about 80–100 μm in an electrode structure of a conventional surface discharge type AC plasma display panel.
When the initial discharge voltage becomes great, much electrical power is consumed and simultaneously the rated capacity of a driving circuit becomes great. Also, induced potential is generated to an adjacent electrode, which causes cross talk. When the distance between the maintaining electrodes 14 and 15 is narrowed to lower the initial discharge voltage, the electrostatic capacity becomes too large.
Alternatively, the quantity of Xe in the discharge gas is increased to increase the efficiency of discharge. However, since the initial discharge voltage becomes great, there is a limit in increasing the quantity of Xe.
A surface discharge type plasma display device to solve the above problems is disclosed in U.S. Pat. No. 5,742,122. In the surface discharge type plasma display device, as shown in FIG. 2, the thickness T1 of a dielectric layer 23 on an upper surface of a transparent electrode 22 of a first substrate 21 is thinner than the thickness T2 of the dielectric layer 23 corresponding to a bus electrode 24 on and parallel to the transparent electrode 22.
In the above surface discharge type plasma display device, by removing ineffective discharge on the bus electrode 24, the efficiency of light emission can be improved while reducing power consumption and preventing cross talk between pixels. However, since the dielectric layer 23 has a uniform thickness on an upper surface of the transparent electrode, there is a limit in reducing the initial discharge voltage.

Plasma display device having portion where electrical field is concentrated


A connector apparatus has a first connector, a second connector to be mated with and unmated from the first connector, and a mating detecting member for detecting a mated state and an unmated state of the first and the second connectors. The first connector has a lock lever to be engaged with the second connector. The mating detecting member has a detecting portion for detecting the mated and the unmated states, a holding portion for locking the mating detecting member at a standby position, and an operating portion for locking the mating detecting member at an assurance position. The detecting portion has a locking portion to be engaged with the lock lever. The holding portion is displaced in a direction different from the mating and the unmating directions to be engaged with the first connector.

This invention relates to a connector apparatus having a mating detecting member for detecting a mated state and an unmated state of a connector and a mating connector.
Japanese Patent Publication (JP-B) No. H7-19631 corresponding to U.S. Pat. No. 4,634,204 discloses an electrical connector apparatus comprising a male connector, a female connector to be mated with the male connector, and a mating detecting member for detecting a mated state of the male connector and the female connector.
The mating detecting member is slidable in a mating direction and an unmating direction opposite to the mating direction. When the male and the female connectors are mated to each other, the mating detecting member is inserted into the male connector to detect complete mating of the male and the female connectors. Thus, the mating detecting member is a component for assuring (confirming) that these connectors are completely mated at a proper position. The mating detecting member is called connector position assurance (CPA).
Further, the mating detecting member allows an operator to find an unmated state where the male and the female connectors are not properly mated.
However, the above-mentioned mating detecting member is disadvantageous in the following respects. Even if the male and the female connectors are in an unmated state, the mating detecting member can slide in the mating direction to be inserted into the male connector if an excessive force is applied by the operator. In this event, it is impossible to detect and confirm the mated state or the unmated state of the male and the female connectors.
When the male connector is released and removed from the female connector, the mating detecting member is not held by the male connector. Therefore, the mating detecting member may possibly be lost.
In the state where the electrical connector is mounted to an electronic apparatus, the mating detecting member may be released and separated from the male connector under an external force exerted by unexpected vibration, mechanical shock, or the like.
As described above, the mating detecting member is inserted into the male connector after the male and the female connectors are mated to each other. It is desired but is not realized that the mating detecting member can be inserted into the male connector with a small force so as to easily perform a normal operation.

Connector apparatus with a mating detecting member called connector position assurance

Japan Aviation Electronics Industry, Limited


A characteristic evaluating method of precisely obtaining a resistance value of an offset region in a semiconductor memory element constructed so that the resistance value of the offset region positioned below a memory function element formed on one side or both sides of a gate electrode changes according to an amount of charges or a polarization state of charges accumulated in said memory function element includes: a step of obtaining each of a resistance value between two diffusion regions inclusive formed on both sides of a channel region disposed just below the gate electrode of the semiconductor memory element via a gate insulating film, a resistance value of the channel region, and a resistance value of the diffusion regions; and a step of calculating the resistance value of the offset region which isolates the channel region and the diffusion region from each other on the basis of a result of subtracting the resistance value of the channel region and the resistance value of the diffusion regions from the resistance value between the two diffusion regions.

1. Field of the Invention
The present invention relates to a method and apparatus for extracting a model parameter for a circuit simulation for a semiconductor memory element. More particularly, the present invention relates to a method of calculating a resistance value of an offset region in a semiconductor memory element having a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed just below the gate electrode via the gate insulating film, two diffusion regions formed on the both sides of the channel region, a memory function element formed on one side or both sides of the gate electrode and having a charge retaining function, and an offset region positioned below the memory function element and isolating the channel region and the diffusion region from each other, and constructed so that the diffusion region formed on the side where the memory function element exists and the channel region are isolated from each other by the offset region and the resistance value of the offset region changes according to the amount of charges or a polarization state of charges accumulated in said memory function element, and relates to a method and apparatus of extracting a model parameter of a semiconductor memory element by using a model formula precisely expressing a calculated resistance value.
2. Description of the Related Art
As a conventional nonvolatile semiconductor memory element generally spread, there is a flash memory constructed by a transistor having a floating-gate structure. In the flash memory, as shown in FIG. 31, a floating gate 902, an insulating film 907, and a word line (control gate) 903 are formed in this order over a semiconductor substrate 901 via a gate insulating film. On both sides of the floating gate 902, a source line 904 and a bit line 905 are formed by a diffusion region, thereby constructing a memory cell. A device isolation region 906 is formed around the memory cell (see, for example, JP-A 05-304277 (1993)).
The memory cell in the flash memory stores information in accordance with an amount of charges in the floating gate 902. In a memory cell array constructed by arranging memory cells, by selecting a specific word line and a specific bit line and applying a predetermined voltage, an operation of rewriting/reading a desired memory cell can be performed. In such a flash memory, when the amount of charges in the floating gate changes, a drain current (Ids)-gate voltage (Vgs) characteristic as shown in FIG. 32 is displayed. When the amount of negative charges in the floating gate increases, the threshold increases and the Ids-Vgs curve shifts almost in parallel to the Vgs increasing direction.
In such a flash memory, however, the insulating film 907 which separates the floating gate 902 and the word line 903 is necessary from the viewpoint of functions, and in order to prevent leakage of charges from the floating gate 902, it is difficult to reduce the thickness of the gate insulating film. Consequently, it is difficult to effectively reduce the thickness of the insulating film 907 and the gate insulating film, and it disturbs reduction in the size of the memory cell.
There is a move afoot to provide a novel semiconductor memory element of which size is easily reduced by employing a semiconductor memory element disclosed in International Publication WO 03/044868 as a semiconductor memory element constructed so that the resistance value of an offset region positioned below a memory function element changes according to an amount of charges or a polarization state of charges accumulated in the memory function element formed on one side or both sides of a gate electrode.
There is also a semiconductor memory element disclosed in JP-A 05-81072 (1993) which has a structure and forms an offset region similar to those of the semiconductor memory element disclosed in International Publication WO 03/044868.
As described above, a semiconductor memory element constructed so that the resistance value of the offset region positioned below the memory function element changes according to an amount of charges or a polarization state of charges accumulated in the memory function element formed on one side or both sides of the gate electrode has, first, a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions formed on both sides of the channel region and having a conduction type opposite to that of the channel region, and memory function elements formed on both sides of the gate electrode and having a charge retaining function. The memory function of the memory function element and a transistor operating function of the gate insulating film are separated from each other. Therefore, while maintaining the sufficient memory function, the gate insulating film can be thinned and it is easy to suppress a short channel effect. Further, as compared with an EEPROM, the value of current flowing between diffusion regions largely changes by rewriting. Thus, it becomes easier to discriminate between the programming state and the erasing state of the semiconductor memory element.
Further, the semiconductor memory element of the present invention can be formed by a process which is very compatible with a normal transistor forming process on the basis of the configuration. Therefore, as compared with the case of using a conventional flash memory as a nonvolatile memory device together with a normal transistor, the number of masks and the number of processes can be dramatically reduced. Consequently, the yield of a chip on which both the semiconductor memory element and a normal transistor circuit are formed can be improved. Due to this, the manufacturing cost is reduced and, accordingly, reliability improves.
To perform a circuit simulation on a circuit including the semiconductor memory element having the excellent characteristics, a set of model parameters of a model for a circuit simulation expressing electric characteristics of the semiconductor memory element is necessary. The semiconductor memory element is different from a general IGFET (insulated gate field-effect transistor, a MOSFET being a kind of the IGFET) with respect to the points that an offset region is provided on both sides or one side of the channel region disposed just below the gate electrode and a memory function element is provided on both sides or one side of the gate electrode.
However, it is difficult to precisely extract a model parameter with respect to an electrostatic characteristic of the semiconductor memory element by using a normal IGFET model (for example, BSIM3 developed mainly by University of California, Berkley, U.S.A.) as a conventional technique by the differences for the following reason. The resistance value of resistance of the offset region existing on both sides or one side of the channel region just below the gate electrode changes according to an amount of charges or a polarization state of charges accumulated in the memory function element positioned on both sides or one side of the gate electrode, and the gate voltage dependency, substrate voltage dependency, and drain voltage dependency of the offset region are largely different from those of the channel region just below the gate electrode. There is a problem such that, in particular, when the memory function element on one side or both sides is in a programming state, it is impossible to extract a model parameter with high precision.
Further, at the time of extracting a model parameter with respect to an electrostatic characteristic of the semiconductor memory element, it is very important to obtain, not channel resistance of the offset and channel regions in a lump, but the resistance of the channel region just below the gate electrode and the resistance of the offset region on both sides or one side separately and to accurately grasp the state (erase or program) of the memory function element and an offset resistance value under voltage conditions of the each region (the gate electrode, semiconductor layer, and diffused region).
However, the offset region is a very small region positioned below the memory function element and it is actually impossible to directly connect an electrode to the offset region. Consequently, the actual condition is that it is difficult to directly measure the resistance of the offset region, and a characteristic evaluating method of precisely obtaining the resistance value of the offset region and a model formula and a model parameter for precisely expressing the resistance value of the offset region obtained by the characteristic evaluation do not exist.

Method of evaluating characteristics of semiconductor memory element, and method of extracting model parameter of semiconductor memory element


Well completion apparatus and associated methods of completing wells provides repositioning of sand control screens and perforating guns without requiring movement of a packer in the wellbore. In a preferred embodiment, a well completion apparatus has a packer, a release apparatus, a telescoping expansion joint, a ball catcher, a sand control screen, and a perforating gun. In another preferred embodiment, a well completion method includes the steps of lowering a packer, release apparatus, telescoping expansion joint, ball catcher, sand control screen, and perforating gun into a well, perforating the wellbore casing, dispensing a sealing ball into the release apparatus, applying pressure to release the release apparatus, and applying pressure to expand the telescoping joint.

The present invention relates generally to apparatus utilized in the completion of subterranean wells and methods of completing such wells, and, in a preferred embodiment thereof, more particularly provides an apparatus which facilitates the placement of sand control screens and perforating guns opposite formations in the wells.
In the course of completing an oil and/or gas well, it is common practice to run a string of protective casing into the wellbore and then to run the production tubing inside the casing. At the wellsite, the casing is perforated across one or more production zones to allow production fluids to enter the casing bore. During production of the formation fluid, formation sand is also swept into the flow path. The formation sand is typically relatively fine sand that tends to erode production equipment in the flow path.
One or more sand screens are typically installed in the flow path between the production tubing and the perforated casing. A packer is customarily set above the sand screen to seal off the annulus in the zone where production fluids flow into the production tubing. In the past, it was usual practice to install the sand screens in the well after the well had been perforated and the guns either removed from the wellbore or dropped to the bottom of the well.
Well completion methods continue to utilize time and resources more efficiently by running the guns, sand screens, and packer into the well on the production tubing in only one trip into the well. From the end of the production tubing down, the completion tool string typically consists of a releasable packer (one capable of being set, released, and reset in the casing, whether by mechanical or hydraulic means), sand control screens, and perforating guns. The completion string is lowered into the well until the guns are opposite the formation to be produced, the packer is set to seal off the annulus above the packer from the formation to be produced, the guns are fired to perforate the casing, the packer is unset, the completion string is again lowered until the sand screens are opposite the perforated casing, the packer is reset, and the formation fluids are then produced from the formation, through the sand screens, into the production tubing, and thence to the surface.
This method has several disadvantages, however. One disadvantage is that a significant amount of rig time is consumed while unsetting, repositioning, and resetting the packer. The rig operator must typically lift the production tubing, manipulate the tubing to unset the packer, lower the tubing into the well a predetermined distance, manipulate the tubing to set the packer, apply tubing weight to the packer, and, finally, perform tests to determine whether the packer has been properly set.
Another disadvantage of the method is that the above-described packer unsetting, repositioning, and resetting must be performed after the casing has been perforated. A necessary consequence of this situation is the possibility that formation fluids may enter the wellbore, and in an extreme situation may even cause loss of control of the well. For this reason, during the packer unsetting, repositioning, and resetting, the well is overbalanced at the formation during these operations--meaning that the pressure in the wellbore is maintained at a level greater than the pressure in the formation. This, in turn, means that wellbore fluids enter the formation through the perforations in the casing, possibly causing damage to the formation.
Furthermore, the method suffers from problems encountered when attempting to reset a packer. In general, modern releasable packers are fairly reliable when lowered into a wellbore and set in casing at a particular location. When, however, a releasable packer is set and then unset and moved to another location, its reliability is greatly diminished. The slips (which grip the interior wall of the casing) may no longer hold fast, and the packer rubbers (which seal against the casing) may not seal adequately a second time.
Additionally, there are other circumstances where, in the drilling, completion, rework, etc. of a well, it is necessary to reposition equipment in the well. Frequently, in these circumstances, it is inconvenient to reposition the equipment by manipulating tubing at the surface, repositioning a packer, or by other methods heretofore known. As an example, in modern practice it is common to run more than one set of perforating guns into a well in one trip. The guns are typically spaced apart with tubing such that each set of guns is positioned opposite a separate formation or pay zone before the guns are fired. If the guns could be repositioned after a first set of guns were fired into a formation, so that a subsequent set of guns would be positioned opposite another formation, the tubing used to space apart the guns could be eliminated and the production string could be shortened.
From the foregoing, it can be seen that it would be quite desirable to provide well completion apparatus which does not require repositioning a releasable packer, but which permits sand control screens to be run into the well with perforating guns in one trip and then positions the sand control screens opposite the formation after the casing has been perforated. It is accordingly an object of the present invention to provide such a well completion apparatus and associated methods of completing wells.
In addition, it is desirable to provide apparatus for positioning equipment in a wellbore. It is accordingly another object of the present invention to provide such positioning apparatus and associated methods of positioning equipment in a wellbore.

Wellbore equipment positioning apparatus and associated methods of completing wells


Apparatuses and methods for cancelling interferences between signals are provided. The apparatuses includes: a receiving unit that receives an orthogonal coded signal from a transmitter and generates a received vector; a channel estimation unit that estimates a state of a wireless channel from the transmitter to the apparatus where the cancelling of the interference between signals is performed and generates a channel state matrix; a Q-R decomposition unit that performs Q-R decomposition with respect to the generated channel state matrix and generates a Q matrix and an R matrix, and generates a decision statistic vector based on the generated Q matrix and the received vector; and a signal determination unit that determines a received signal with interference from the orthogonal coded signal being decreased based on the generated decision statistics vector.

1. Field
Example embodiments relate to apparatuses and methods for receiving a signal being transmitted using a transmission diversity scheme in a mobile communication system, and more particularly to apparatuses and methods that can increase reception performance by cancelling interferences between orthogonal coded signals.
2. Description of Related Art
With rapid development of mobile telecommunication systems, a served amount of data provided by a mobile telecommunication system rapidly increases. A channel state of a wireless link between a base station and a terminal of the mobile telecommunication system changes over time, and this is referred to as a fading phenomenon.
In the case of high-speed data transmission in the mobile telecommunication system, an amplitude and a phase of a received signal is distorted due to the fading phenomenon occurring on the wireless channel.
The fading phenomenon occurs on the wireless link in between the base station and the terminal, and is one of the main reasons that service quality of the mobile telecommunication system deteriorates.
Various diversity schemes are used to overcome the fading phenomenon. As an instance of the various diversity schemes, a space diversity scheme using a plurality of antennas which are spaced from each other over a predetermined distance is used. A reception diversity scheme receiving a transmitted signal using a plurality of antennas is difficult to be applied to a downlink in a mobile communication environment due to a limited size of a terminal. Accordingly, research and development with respect to a transmission diversity scheme that transmits a signal using a plurality of antennas has been conducted. An orthogonal coding scheme, one type of transmission diversity schemes, encodes a plurality of data to transmit in a transmitter, generates a plurality of data streams being orthogonal with each other, and transmits the generated data streams to a receiving apparatus using a plurality of time durations or a plurality of frequency bands.

Apparatus and method for cancelling interferences between orthogonal coded signals in mobile communication system


A power transmission device includes a transmission mechanism configured to transmit power generated by an electric motor to an output shaft, to which power generated by an internal combustion engine is transmitted, via engaging sections of a plurality of rotating members, and the transmission mechanism has a play to the engaging sections along a rotating direction, the play being larger than a relative displacement amount between the rotating member on the internal combustion engine side and the rotating member on the electric motor side when a rotation variation phase difference between the internal combustion engine and the electric motor is maximum. Therefore, there can be provided the power transmission device capable of suppressing an occurrence of noise.

As a conventional power transmission device mounted on a vehicle and the like, for example, Patent Literature 1 discloses a power transmission device which is applied to a hybrid vehicle including both an internal combustion engine and an electric motor as power sources for travelling and has a first gear to which a drive force is input and a second gear which is meshed with the first gear in a state that it has a predetermined backlash and transmits the drive force to a load. When there is predicted an occurrence of collision between tooth surfaces due to a mesh between a first gear provided with a permanent magnet and a second gear provided with a coil disposed at a position where a magnetic flux from the permanent magnet links, the power transmission device reduces gear noise caused by a gear-tooth hammering shock without increasing a size of the device by controlling a current flowing to the coil by a control means so that the coil generates a flux linkage for suppressing a change of an interlinkage magnetic flux from the permanent magnet due to a change of an inter-tooth-surface relative distance.


Showerhead electrodes for a semiconductor material processing apparatus are disclosed. An embodiment of the showerhead electrodes includes top and bottom electrodes bonded to each other. The top electrode includes one or more plenums. The bottom electrode includes a plasma-exposed bottom surface and a plurality of gas holes in fluid communication with the plenum. Showerhead electrode assemblies including a showerhead electrode flexibly suspended from a top plate are also disclosed. The showerhead electrode assemblies can be in fluid communication with temperature-control elements spatially separated from the showerhead electrode to control the showerhead electrode temperature. Methods of processing substrates in plasma processing chambers including the showerhead electrode assemblies are also disclosed.

In the field of semiconductor material processing, semiconductor material processing apparatuses including vacuum processing chambers are used, for example, for etching and chemical vapor deposition (CVD) of various materials on substrates, and for resist stripping. Some of these processes utilize corrosive and erosive process gases and plasma in such processing chambers. It is desirable to minimize particle and/or metal contamination of substrates processed in the chambers. Accordingly, it is desirable that process-exposed components of such apparatuses have low-particle performance.

Showerhead electrodes and showerhead electrode assemblies having low-particle performance for semiconductor material processing apparatuses


The present invention relates to novel prodrug forms of 3S,4aR,6S,8aR-6-(((4-carboxy)phenyl)methyl)-1,2,3,4,4a,5,6,7,8,8a-decahydroisoquinoline-3-carboxylic acid, to pharmaceutical compositions containing the prodrug forms, and to methods of using the prodrug forms.

The present invention relates to novel prodrug forms of 3S,4aR,6S,8aR-6-(((4-carboxy)phenyl)methyl)-1,2,3,4,4a,5,6,7,8,8a-decahydroisoquinoline-3-carboxylic acid, to pharmaceutical compositions containing the prodrug forms, and to methods of using the prodrug forms.
European Patent Application Publication No. 590789A1 and U.S. Pat. No. 5,446,051 disclose that certain decahydroisoquinoline derivatives are AMPA receptor antagonists, and as such are useful in the treatment of many different conditions, including pain. In addition, WO 98/45270, published Oct. 15, 1998, discloses that certain selective GluR5 antagonists are useful for treating pain.
It is an object of the present invention to provide diesters of 3S,4aR,6S,8aR-6-(((4-carboxy)phenyl)methyl)-1,2,3,4,4a,5,6,7,8,8a-decahydroisoquinoline-3-carboxylic acid which provide substantially improved bioavailability of the parent diacid in a patient. In addition, it is an object of the present invention to provide diesters of 3S,4aR,6S, 8aR-6-(((4-carboxy)phenyl)methyl)-1,2,3,4,4a,5,6,7,8,8a-decahydroisoquinoline-3-carboxylic acid which are substantially converted to the parent diacid in the patient.
It has now been found that novel diesters of the diacid, 3S,4aR,6S,8aR-6-(((4-carboxy)phenyl)methyl)-1,2,3,4,4a,5,6,7,8,8a-decahydroisoquinoline-3-carboxylic acid, possess substantially improved bioavailability as compared to the diacid. In addition, the diesters are substantially converted to the diacid in the patient. The diacid is generically disclosed in U.S. Pat. No. 5,446,051, issued Aug. 29, 1995, and specifically disclosed in, WO 98/45270, published Oct. 15, 1998, as a selective GluR5 antagonist for treatment of pain.
Thus, the present invention provides compounds of formula I:
wherein R1 and R2 are each independently C1-C20 alkyl, C2-C6 alkenyl, C1-C6 alkylaryl, C1-C6 alkyl(C3-C10) cycloalkyl, C1-C6 alkyl-N, Nxe2x80x94C1-C6 dialkylamine, C1-C6 alkyl-pyrrolidine, C1-C6 alkyl-piperidine, or C1-C6 alkyl-morpholine; or a pharmaceutically acceptable salt thereof.
The present invention further provides a method of antagonizing the GluR5 receptor, which comprises administering to a patient an effective amount of a compound of formula I.
In addition, the present invention provides a method for the treatment of pain, which comprises administering to a patient an effective amount of a compound of formula I.
The present invention further provides a method for the treatment of migraine, which comprises administering to a patient an effective amount of a compound of formula I.
The present invention further provides the use of a compound of formula I for the manufacture of a medicament for the treatment of pain.
The present invention further provides the use of a compound of formula I for the manufacture of a medicament for the treatment of migraine.
As used herein, the term xe2x80x9cprodrugxe2x80x9d refers to a diester derivative of a dicarboxylic acid functional drug, which derivative, when administered to a patient is converted into the diacid (drug). The enzymatic and/or chemical hydrolytic cleavage of the compounds of the present invention occurs in such a manner that the parent dicarboxylic acid (drug ) is released.
As used herein the term xe2x80x9cCompound Axe2x80x9d refers to 3S,4aR,6S,8aR-6-(((4-carboxy)phenyl)methyl)-1,2,3,4,4a,5,6,7,8,8a-decahydroisoquinoline-3-carboxylic acid.
As used herein the term xe2x80x9cCompound Bxe2x80x9d refers to 3S,4aR,6S, 8aR-6-(((4-carboxy)phenyl)methyl)-1,2,3,4,4a,5,6,7,8,8a-decahydroisoquinoline-3-carboxylic acid HCl, diethyl ester.
As used herein the term xe2x80x9cCompound Cxe2x80x9d refers to 3S,4aR,6S, 8aR-6-(((4-carboxy)phenyl)methyl)-1,2,3,4,4a,5,6,7,8,8a-decahydroisoquinoline-3-carboxylic acid HCl, dimethyl ester.
As used herein the term xe2x80x9cCompound Dxe2x80x9d refers to 3S,4aR,6S, 8aR-6-(((4-carboxy)phenyl)methyl)-1,2,3,4,4a,5,6,7,8,8a-decahydroisoquinoline-3-carboxylic acid HCl, diisopropyl ester.
As used herein the term xe2x80x9cCompound Exe2x80x9d refers to 3S,4aR,6S, 8aR-6-(((4-carboxy)phenyl)methyl)-1,2,3,4,4a,5,6,7,8,8a-decahydroisoquinoline-3-carboxylic acid HCl, diisobutyl ester.
As used herein the term xe2x80x9cC1-C4 alkylxe2x80x9d refers to a straight or branched, monovalent, saturated aliphatic chain of 1 to 4 carbon atoms and includes, but is not limited to methyl, ethyl, n-propyl, isopropyl, n-butyl, isobutyl and the like.
As used herein the term xe2x80x9cC1-C6 alkylxe2x80x9d refers to a straight or branched, monovalent, saturated aliphatic chain of 1 to 6 carbon atoms and includes, but is not limited to methyl, ethyl, n-propyl, isopropyl, n-butyl, isobutyl, t-butyl, n-pentyl, n-hexyl, and the like.
As used herein the term xe2x80x9cC1-C10 alkylxe2x80x9d refers to a straight or branched, monovalent, saturated aliphatic chain of 1 to 10 carbon atoms and includes, but is not limited to methyl, ethyl, propyl, isopropyl, n-butyl, isobutyl, tertiary butyl, pentyl, isopentyl, hexyl, 2,3-dimethyl-2-butyl, heptyl, 2,2-dimethyl-3-pentyl, 2-methyl-2-hexyl, octyl, 4-methyl-3-heptyl and the like.
As used herein the term xe2x80x9cC1-C20 alkylxe2x80x9d refers to a straight or branched, monovalent, saturated aliphatic chain of 1 to 20 carbon atoms and includes, but is not limited to, methyl, ethyl, propyl, isopropyl, butyl, isobutyl, t-butyl, pentyl, isopentyl, hexyl, 3-methylpentyl, 2-ethylbutyl, n-heptyl, n-octyl, n-nonyl, n-decyl, n-undecyl, n-dodecyl, n-tridecyl, n-tetradecyl, n-pentadecyl, n-hexadecyl, n-heptadecyl, n-nonadecyl, n-eicosyl and the like.
As used herein, the terms xe2x80x9cMexe2x80x9d, xe2x80x9cEtxe2x80x9d, xe2x80x9cPrxe2x80x9d, xe2x80x9ciPrxe2x80x9d, xe2x80x9cBuxe2x80x9d and xe2x80x9ct-Buxe2x80x9d refer to methyl, ethyl, propyl, isopropyl, butyl and tert-butyl respectively.
As used herein the term xe2x80x9cC2-C6 alkenylxe2x80x9d refers to a straight or branched, monovalent, unsaturated aliphatic chain having from two to six carbon atoms. Typical C2-C6 alkenyl groups include ethenyl (also known as vinyl), 1-methylethenyl, 1-methyl-1-propenyl, 1-butenyl, 1-hexenyl, 2-methyl-2-propenyl, 1-propenyl, 2-propenyl, 2-butenyl, 2-pentenyl, and the like.
As used herein, the term xe2x80x9carylxe2x80x9d refers to monovalent carbocyclic group containing one or more fused or non-fused phenyl rings and includes, for example, phenyl, 1- or 2-naphthyl, 1,2-dihydronaphthyl, 1,2,3,4-tetrahydronaphthyl, and the like.
As used herein, the term xe2x80x9cC1-C6 alkylarylxe2x80x9d refers to a straight or branched, monovalent, saturated aliphatic chain of 1 to 6 carbon atoms which has an aryl group attached to the aliphatic chain. Included within the term xe2x80x9cC1-C6 alkylarylxe2x80x9d are the following:
and the like.
As used herein the term xe2x80x9c(C3-C10)cycloalkylxe2x80x9d refers to a saturated hydrocarbon ring structure containing from three to ten carbon atoms. Typical C3-C10 cycloalkyl groups include cyclopropyl, cyclobutyl, cyclopentyl, cyclohexyl, cycloheptyl, cyclooctyl, and the like. It is understood that xe2x80x9c(C3-C8)cycloalkylxe2x80x9d and xe2x80x9c(C4-C6)cycloalkylxe2x80x9d is included within the term xe2x80x9c(C3-C10)cycloalkylxe2x80x9d.
As used herein, the term xe2x80x9cC1-C6 alkyl(C3-C10)cycloalkylxe2x80x9d refers to a straight or branched, monovalent, saturated aliphatic chain of 1 to 6 carbon atoms which has a (C3-C10)cycloalkyl attached to the aliphatic chain. Included within the term xe2x80x9cC1-C6 alkyl(C3-C10)cycloalkylxe2x80x9d are the following:
and the like
As used herein the term xe2x80x9cN,Nxe2x80x94C1-C6 dialkylaminexe2x80x9d refers to a nitrogen atom substituted with two straight or branched, monovalent, saturated aliphatic chains of 1 to 6 carbon atoms. Included within the term xe2x80x9cN,Nxe2x80x94C1-C6 dialkylaminexe2x80x9d are xe2x80x94N(CH3)2, xe2x80x94N(CH2CH3)2, xe2x80x94N(CH2CH2CH3)2, xe2x80x94N(CH2CH2CH2CH3)2, and the like.
As used herein the term xe2x80x9cC1-C6 alkyl-N,Nxe2x80x94C1-C6 dialkylaminexe2x80x9d refers to straight or branched, monovalent, saturated aliphatic chain of 1 to 6 carbon atoms which has an N,Nxe2x80x94C1-C6 dialkylamine attached to the aliphatic chain. Included within the term xe2x80x9cC1-C6 alkyl-N,Nxe2x80x94C1-C6 dialkylaminexe2x80x9d are the following:
and the like.
As used herein the term xe2x80x9cC1-C6 alkyl-pyrrolidinexe2x80x9d refers to a straight or branched, monovalent, saturated aliphatic chain of 1 to 6 carbon atoms which has a pyrrolidine attached to the aliphatic chain. Included within the scope of the term xe2x80x9cC1-C6 alkyl-pyrrolidinexe2x80x9d are the following:
and the like.
As used herein the term xe2x80x9cC1-C6 alkyl-piperidinexe2x80x9d refers to a straight or branched, monovalent, saturated aliphatic chain of 1 to 6 carbon atoms which has a piperidine attached to the aliphatic chain. Included within the scope of the term xe2x80x9cC1-C6 alkyl-piperidinexe2x80x9d are the following:
and the like.
As used herein the term xe2x80x9cC1-C6 alkyl-morpholinexe2x80x9d refers to a straight or branched, monovalent, saturated aliphatic chain of 1 to 6 carbon atoms which has a morpholine attached to the aliphatic chain. Included within the scope of the term xe2x80x9cC1-C6 alkyl-morpholinexe2x80x9d are the following:
and the like.
The designation
refers to a bond that protrudes forward out of the plane of the page.
The designation
refers to a bond that protrudes backward out of the plane of the page.
This invention includes the hydrates and the pharmaceutically acceptable salts of the compounds of formula I. A compound of this invention can possess a sufficiently basic functional group which can react with any of a number of inorganic and organic acids, to form a pharmaceutically acceptable salt.
The term xe2x80x9cpharmaceutically acceptable saltxe2x80x9d as used herein, refers to salts of the compounds of formula I which are substantially non-toxic to living organisms. Typical pharmaceutically acceptable salts include those salts prepared by reaction of the compounds of the present invention with a pharmaceutically acceptable mineral or organic acid. Such salts are also known as acid addition salts.
Acids commonly employed to form acid addition salts are inorganic acids such as hydrochloric acid, hydrobromic acid, hydroiodic acid, sulfuric acid, phosphoric acid, and the like, and organic acids such as p-toluenesulfonic, methanesulfonic acid, oxalic acid, p-bromophenylsulfonic acid, carbonic acid, succinic acid, citric acid, benzoic acid, acetic acid, and the like. Examples of such pharmaceutically acceptable salts are the sulfate, pyrosulfate, bisulfate, sulfite, bisulfite, phosphate, monohydrogenphosphate, dihydrogenphosphate, metaphosphate, pyrophosphate, bromide, iodide, acetate, propionate, decanoate, caprylate, acrylate, formate, hydrochloride, dihydrochloride, isobutyrate, caproate, heptanoate, propiolate, oxalate, malonate, succinate, suberate, sebacate, fumarate, maleate, butyne-1,4-dioate, hexyne-1,6-dioate, benzoate, chlorobenzoate, methylbenzoate, hydroxybenzoate, methoxybenzoate, phthalate, xylenesulfonate, phenylacetate, phenylpropionate, phenylbutyrate, citrate, lactate, xcex1-hydroxybutyrate, glycolate, tartrate, methanesulfonate, propanesulfonate, naphthalene-1-sulfonate, napththalene-2-sulfonate, mandelate and the like. Preferred pharmaceutically acceptable acid addition salts are those formed with mineral acids such as hydrochloric acid and hydrobromic acid, and those formed with organic acids such as maleic acid, oxalic acid and methanesulfonic acid.
It should be recognized that the particular counterion forming a part of any salt of this invention is usually not of a critical nature, so long as the salt as a whole is pharmacologically acceptable and as long as the counterion does not contribute undesired qualities to the salt as a whole. It is further understood that such salts may exist as a hydrate.
As used herein, the term xe2x80x9cstereoisomerxe2x80x9d refers to a compound made up of the same atoms bonded by the same bonds but having different three-dimensional structures which are not interchangeable. The three-dimensional structures are called configurations. As used herein, the term xe2x80x9cenantiomerxe2x80x9d refers to two stereoisomers whose molecules are nonsuperimposable mirror images of one another. The term xe2x80x9cchiral centerxe2x80x9d refers to a carbon atom to which four different groups are attached. As used herein, the term xe2x80x9cdiastereomersxe2x80x9d refers to stereoisomers which are not enantiomers. In addition, two diastereomers which have a different configuration at only one chiral center are referred to herein as xe2x80x9cepimersxe2x80x9d. The terms xe2x80x9cracematexe2x80x9d, xe2x80x9cracemic mixturexe2x80x9d or xe2x80x9cracemic modificationxe2x80x9d refer to a mixture of equal parts of enantiomers.
The term xe2x80x9cenantiomeric enrichmentxe2x80x9d as used herein refers to the increase in the amount of one enantiomer as compared to the other. A convenient method of expressing the enantiomeric enrichment achieved is the concept of enantiomeric excess, or xe2x80x9ceexe2x80x9d, which is found using the following equation:   ee  =                              E          1                -                  E          2                                      E          1                +                  E          2                      xc3x97    100
wherein E1 is the amount of the first enantiomer and E2 is the amount of the second enantiomer. Thus, if the initial ratio of the two enantiomers is 50:50, such as is present in a racemic mixture, and an enantiomeric enrichment sufficient to produce a final ratio of 50:30 is achieved, the ee with respect to the first enantiomer is 25%. However, if the final ratio is 90:10, the ee with respect to the first enantiomer is 80%. An ee of greater than 90% is preferred, an ee of greater than 95% is most preferred and an ee of greater than 99% is most especially preferred. Enantiomeric enrichment is readily determined by one of ordinary skill in the art using standard techniques and procedures, such as gas or high performance liquid chromatography with a chiral column. Choice of the appropriate chiral column, eluent and conditions necessary to effect separation of the enantiomeric pair is well within the knowledge of one of ordinary skill in the art. In addition, the enantiomers of compounds of formula I can be resolved by one of ordinary skill in the art using standard techniques well known in the art, such as those described by J. Jacques, et al., xe2x80x9cEnantiomers, Racemates, and Resolutionsxe2x80x9d, John Wiley and Sons, Inc., 1981.
The compounds of the present invention have one or more chiral centers and may exist in a variety of stereoisomeric configurations. As a consequence of these chiral centers, the compounds of the present invention occur as racemates, mixtures of enantiomers and as individual enantiomers, as well as diastereomers and mixtures of diastereomers. All such racemates, enantiomers, and diastereomers are within the scope of the present invention.
The terms xe2x80x9cRxe2x80x9d and xe2x80x9cSxe2x80x9d are used herein as commonly used in organic chemistry to denote specific configuration of a chiral center. The term xe2x80x9cRxe2x80x9d (rectus) refers to that configuration of a chiral center with a clockwise relationship of group priorities (highest to second lowest) when viewed along the bond toward the lowest priority group. The term xe2x80x9cSxe2x80x9d (sinister) refers to that configuration of a chiral center with a counterclockwise relationship of group priorities (highest to second lowest) when viewed along the bond toward the lowest priority group. The priority of groups is based upon their atomic number (in order of decreasing atomic number). A partial list of priorities and a discussion of stereochemistry is contained in xe2x80x9cNomenclature of Organic Compounds: Principles and Practicexe2x80x9d, (J. H. Fletcher, et al., eds., 1974) at pages 103-120.
The specific stereoisomers and enantiomers of compounds of formula (I) can be prepared by one of ordinary skill in the art utilizing well known techniques and processes, such as those disclosed by Eliel and Wilen, xe2x80x9cStereochemistry of Organic Compoundsxe2x80x9d, John Wiley and Sons, Inc., 1994, Chapter 7, Separation of Stereoisomers. Resolution. Racemization, and by Collet and Wilen, xe2x80x9cEnantiomers, Racemates, and Resolutionsxe2x80x9d, John Wiley and Sons, Inc., 1981. For example, the specific stereoisomers and enantiomers can be prepared by stereospecific syntheses using enantiomerically and geometrically pure, or enantiomerically or geometrically enriched starting materials. In addition, the specific stereoisomers and enantiomers can be resolved and recovered by techniques such as chromatography on chiral stationary phases, enzymatic resolution or fractional recrystallization of addition salts formed by reagents used for that purpose.
The compounds of formula I can be prepared by techniques and procedures readily available to one of ordinary skill in the art. For example, various starting materials and general procedures which may be employed by one of ordinary skill in the art in the preparation of compounds of formula I are described in U.S. Pat. No. 5,446,051, issued Aug. 29, 1995, which is hereby incorporated by reference, and WO 98/45270, published Oct. 15, 1998.
More specifically, compounds of formula I can be prepared by following the procedures as set forth in Scheme I. This scheme is not intended to limit the scope of the invention in any way. All substituents, unless otherwise indicated, are previously defined. The reagents and starting materials are readily available to one of ordinary skill in the art.
In Scheme I, compound A is esterified to provide the diester of formula I under standard conditions well known in the art. For example, compound A is dissolved in a suitable organic solvent and treated with a suitable acid, such as hydrochloric acid. Examples of suitable organic solvents include, methyl alcohol, ethyl alcohol, propyl alcohol, isopropyl alcohol, n-butyl alcohol, isobutyl alcohol, t-butyl alcohol, pentyl alcohol, isopentyl alcohol, hexyl alcohol, 3-methylpentyl alcohol, 2-ethylbutyl alcohol, n-heptyl alcohol, n-octyl alcohol, and the like. The reaction is heated at about 40xc2x0 C. to about 60xc2x0 C. for about 4 hours to about 16 hours. The product is then isolated and purified using techniques well known to one of ordinary skill in the art, such as extraction techniques and chromatography.
For example, the above reaction is cooled, diluted with a suitable organic solvent, such as ethyl acetate, washed with saturated sodium bicarbonate, brine, dried over anhydrous magnesium sulfate, filtered and concentrated under vacuum to provide the compound of formula I. This material may be further purified by flash chromatography on silica gel with a suitable eluent such as ethyl acetate/hexane.
Alternatively, compound A is dissolved in a suitable organic solvent and treated with an excess of thionyl chloride. Examples of suitable organic solvents are anhydrous methyl alcohol, ethyl alcohol, propyl alcohol, isopropyl alcohol, butyl alcohol, isobutyl alcohol, t-butyl alcohol, pentyl alcohol, isopentyl alcohol, hexyl alcohol, 3-methylpentyl alcohol, 2-ethylbutyl alcohol, n-heptyl alcohol, n-octyl alcohol, and the like. The solution is stirred at reflux for about 1 to 3 hours, and at room temperature for about 8 to 16 hr. The mixture is then concentrated under vacuum, and the residue is purified in a manner analogous to the procedures described above to provide the prodrug diester of formula I.
The pharmaceutically acceptable salts of formula I are readily prepared by one of ordinary skill in the art using standard techniques and procedures. For example, the above product is suspended in diethyl ether, which has been saturated with HCl gas. The mixture is stirred for about 1 to 3 hours. The precipitate is then filtered and washed with diethyl ether under vacuum to provide the pharmaceutically acceptable salt of the prodrug diester of formula I.
The following examples illustrate the invention and represent typical syntheses of the compounds of formula I as described generally above. The reagents and starting materials are readily available to one of ordinary skill in the art. As used herein, the following terms have the meanings indicated: xe2x80x9ceqxe2x80x9d or xe2x80x9cequiv.xe2x80x9d refers to equivalents; xe2x80x9cgxe2x80x9d refers to grams; xe2x80x9cmgxe2x80x9d refers to milligrams; xe2x80x9cLxe2x80x9d refers to liters; xe2x80x9cmLxe2x80x9d refers to milliliters; xe2x80x9cxcexcLxe2x80x9d refers to microliters; xe2x80x9cmolxe2x80x9d refers to moles; xe2x80x9cmmolxe2x80x9d refers to millimoles; xe2x80x9cpsixe2x80x9d refers to pounds per square inch; xe2x80x9cminxe2x80x9d refers to minutes; xe2x80x9chxe2x80x9d refers to hours; xe2x80x9cxc2x0 C.xe2x80x9d refers to degrees Celsius; xe2x80x9cTLCxe2x80x9d refers to thin layer chromatography; xe2x80x9cHPLCxe2x80x9d refers to high performance liquid chromatography; xe2x80x9cxcex4xe2x80x9d refers to part per million down-field from tetramethylsilane; xe2x80x9cTHFxe2x80x9d refers to tetrahydrofuran; xe2x80x9cDMFxe2x80x9d refers to N,N-dimethylformamide; xe2x80x9cDMSOxe2x80x9d refers to methyl sulfoxide; xe2x80x9caqxe2x80x9d refers to aqueous; xe2x80x9cEtOAcxe2x80x9d refers to ethyl acetate; xe2x80x9ciPrOAcxe2x80x9d refers to isopropyl acetate; xe2x80x9cMeOHxe2x80x9d refers to methanol; xe2x80x9cMTBExe2x80x9d refers to tert-butyl methyl ether, and xe2x80x9cRTxe2x80x9d refers to room temperature.

Diester prodrugs of a decahydroisoquinoline-3-carboxylic acid


This invention relates to a biojoint prosthesis comprising:. a) a prosthetic comprising a first component having an outer surface comprising at least 90 mol% zirconia, and PA1 b) a second component having a surface shaped to receive the outer surface of the first component,. wherein the outer surface of the first component is received on the surface of the second component, and. wherein a) at least a portion of the surface of the second component receiving the first component comprises a ceramic having a surface roughness of no more than 100 nm, and b) the outer surface of the first component has a surface roughness of no more than 100 nm.

In surgeries requiring a total hip joint replacement, both the acetabulum and the upper portion of the femur must be replaced, and appropriate materials must be selected as the replacement components. During the 1970's, the femoral prosthetic component was typically made of a metal such as stainless steel, alloys of Cr--Co--Mo and titanium, while the mating acetabular cup was typically made of ultra high molecular weight polyethylene (UHMWPE). However, it soon became apparent that the metal-UHMWPE coupling produced significant amounts of polyethylene wear debris in vivo. This debris has been heavily implicated in the osteolytic destruction of periarticular tissues and the subsequent loosening of the hip joint prosthesis. Consequently, the medical community began to consider replacement materials for the metal heads.
Because of the wear and debris problem, standardized testing methods were also developed to help compare the wear rates of candidate materials for hip joint prosthesis components. Determining the wear-related suitability of components for use in a hip joint prosthesis typically involves performing a standard pin-on-disc wear test, such as ASTM F 732 82, and characterizing its results by a normalized wear factor, k. The wear factor, k, is defined as the wear volume V (in mm.sup.3) of a material, divided by the product of the load P (in N) and the sliding distance X (in m). According to Saikko, Wear 166 (1993) 169-178, a wear factor of 10.sup.-9 mm.sup.3 /Nm is "extremely low" while a wear factor of 10.sup.-7 mm.sup.3 /Nm is "considerable".
From these wear tests, alumina was identified as a candidate replacement material. The reported wear factors k of the UWPE.backslash.alumina couple of about 10.sup.-7 mm.sup.3 /Nm to 10.sup.-9 mm.sup.3 /Nm were found to be superior to the metal.backslash.HMWPE couple. Accordingly, modular femur components comprising an alumina head taper fit to a metal stem were developed, and these components were coupled with both UHMWPE and alumina cups. Although the alumina-UHMWPE and alumina-alumina couplings produce less wear debris, the low strength of alumina (only about 600 MPa) has hindered its widespread acceptance. Because of the unreliability associated with the low strength of alumina, other ceramic materials have been considered.
Over the past five years, artificial hip joint prostheses having zirconia heads have gained acceptance in the medical community. As the strength of partially stabilized zirconia is typically between about 900-1300 MPa and its toughness is at least about 5 MPa m.sup.1/2, it is more reliable than alumina. In fact, the superior mechanical properties of zirconia has even enabled its use in small 22 mm heads. In all hip joint prostheses using zirconia heads, UHWPE cups have been used. See, for example, U.S. Pat. No. 5,181,929, assigned to Ceramiques Techniques Desmarquest; Willmann (of Cerasiv), Biomedizinische Technik 39(4) (1994) 73-78; Saikko, Wear 166 (1993) 169-178; Derbyshire, Med. Eng. Phys. 16 (1994) 229-236; Tateishi Mat. Sci. Eng. C1 (1994) 121-125; Japanese Patent Publication (Kokoku) 5-75423; Streicher (of Sulzer) "Bioceramics, Vol. 4", (1991) 9-16; and Schwartz (of Richards), "36th Ann. Mtg. ORS" 1990 483. Since the reported production of UHWPE debris has been extremely variable in this case (a wear factor k of 10.sup.-7 mm.sup.3 /Nm according to Streicher and Derbyshire to 10.sup.-9 mm.sup.3 /Nm according to Saikko), there remains a continuing need to identify materials for use in acetabulum cups which, when coupled with zirconia heads, produce even smaller amounts of debris than a UHMWPE cup.
Researchers studying the wear of zirconia-ceramic couplings have reported extremely high wear. For example, the results reported by Ludema, in "Advanced Ceramics for Structural and tribological Applications" (1995) 37-45, yield an alumina plate-zirconia pin total wear factor of about 10.sup.-5 mm.sup.3 /Nm, and a zirconia plate-alumina pin total wear factor of over 10.sup.-5 mm.sup.3 /Nm. The results reported by Medevielle et al., in J. Eur. Cer. Soc. 15 (12) (1995) 1193-1200, yield an alumina plate-zirconia pin total wear factor of about 10.sup.-6 mm.sup.3 /Nm (assuming a test period of 30 minutes). Tucci, in Wear, 172, (1994) 111-119, reports yttria tetragonal polycrystal ("YTZP") zirconia plate-alumina pin wear factors ranging from 10.sup.-5 mm.sup.3 /Nm to 10.sup.-3 mm.sup.3 /Nm. Lastly, the results of Sudanese, in Alumina vs Zirconium Oxide: A Comparative Wear Test, in "Bioceramics 1989", pp. 237-240, Oonishi H, Aoki M, Sawai L (eds), yield a wear factor for a zirconia ring-zirconia disc coupling which was over 5000 times worse than an alumina-alumina coupling.
Because of the high wear factors associated with zirconia-ceramic couplings, the hip joint prosthesis field has considered and specifically rejected a zirconia head-ceramic cup coupling. For example, in Clarke, Clin. Orthop. 282 (1992) 19-30, the author points to the relative inferiority of zirconia in wear tests and warns that "there may be a cause for concern given the potential to mix and match alumina ceramic cups with zirconia balls". In Willmann, supra, Table 3 specifically discourages using a zirconia head and an alumina cup and bases that conclusion upon clinical and technical studies. Sudanese, supra, concludes that ". . . zirconium oxide cannot be used for ceramic-ceramic coupling prosthesis, due to its low wear resistance. It may be the bioceramic material of choice to make ceramic heads in hip prosthesis with polyethilene! sockets." Although Kyocera JP Patent Publication 4303443 discloses an alumina head coupled with a cup having either an alumina or zirconia mating surface, its reference to a zirconia cup is merely prophetic and it does not disclose a zirconia head with a cup having an alumina mating surface. Since the wear mechanisms for the head and cup are different (see e.g., Medevielle's discussion and Ludema's results when the couples are switched), Kyocera's silence with respect to the zirconia head-alumina cup combination is notable.
Accordingly, there exists a continuing need for an acetabulum cup for use with a zirconia head which produces a wear factor of less than 10.sup.-7 mm.sup.3 /Nm.

Hip joint prosthesis having a zirconia head and a ceramic cup

Saint-Gobain/Norton Industrial Ceramics Corp.


Provided is a display panel having a display area including a first display area and a second display area. The display panel includes: a substrate; an array layer; a display layer including light-emitting elements each including an anode, a light-emitting layer and a cathode that are sequentially stacked; the light-emitting elements comprises first light-emitting elements and second light-emitting elements; a state switching layer located at a side of the display layer facing away from a display surface of the display panel and located in the first display area, wherein in a direction perpendicular to the display panel, the state switching layer overlaps the first light-emitting elements; the state switching layer is switchable between a first state and a second state, and the state switching layer has a smaller light transmittance in the first state than in the second state; and an optical element.

With development of display technologies, demands on smooth use and visual experiences of an electronic product are getting higher, and a high screen occupancy ratio has become a research focus currently. For electronic products, an optical element such as a front camera inevitably occupies a certain space, thus affecting the screen occupancy ratio. In order to achieve a true full screen, the researchers have considered an implementation of the optical element under the screen.
An optical element such as a camera is disposed under a light-emitting element of the display panel, that is, the optical element is disposed in the display area, and a normal display can be achieved at a position where the optical element is disposed. When an optical element is needed, light passes through the display panel to reach the optical element and is finally utilized by the optical element. In a structure of a display panel in the related art, an optical element, when being disposed under the screen, receives little light, thereby affecting an operational performance of an optical module. Therefore, a technical problem that needs to be solved is how to increase an amount of light received by the optical element and thus improve the performance of the optical element under the screen.


The system includes a vestibule and a plurality of emergency exits interconnecting the secure area with the outside environment. The vestibule comprises a pair of security doors and the emergency exits comprise security doors having locking means and means for disabling the locking means in response to any one of several preselected egress corroborating events that are not likely to be associated with adversarial activity. The various preselected events may include non-emergency situations such as a request to leave or disable made by two persons within the secure area, a request to leave or disable made by a single person within the secure area plus security guard affirmation, and a request to leave or disable made by a single person within the secure area plus the expiration of a time delay triggered by the request. The various preselected events may also reflect emergency situations such as activation of an alarm system triggered by single, double or multiple alarms that bring into question the safety of insiders in the secure area. The emergency exits may be in the form of an environmentally-hardened portal or a single security door.

Security systems which provide some degree of control of the ingress to and egress from enclosed or secure areas are known. Generally, there are two known approaches in such security systems. One approach is to physically harden the entry doors (and their associated hardware, i.e. locks and hinges) leading into the secure area. The objective is to increase the amount of time that it takes to penetrate the entry doors at least to that of the penetrability of the surfaces adjacent to the doors, i.e. the walls, ceiling, and floor. The rationale is to insure that doors which are provided for authorized ingress do not facilitate unauthorized entry by force.
The second approach comprises using doors adapted to be locked and unlocked by a mechanism responsive to a single event. For example, the event triggering the mechanism may be the turn of a key, the entry of a code, or the actuation of a switch by one having authority to lock and unlock the door, e.g. a security guard. Security effectiveness can be increased with "anti-passback" or "anti-piggyback" enhancements in the mechanism, whereby the mechanism unlocks the door in response to its recognition of credentials personal to authorized persons, such as weight or a personal key or code. A time delay may also be included so that the personal key or code cannot be used more than once during a specific time period.
In high security applications, the second approach is typically implemented using a "Two Person Rule". The Two Person Rule is based on the principle that insider adversarial activity is usually committed alone. Thus, when the Two Person Rule is implemented, a mechanism is provided for locking and unlocking the doors that can be activated only by two persons acting together, thereby significantly reducing the likelihood that the opening of the door is for adversarial purposes.
Doors used in accordance with the latter system may be part of a vestibule through which persons must pass in order to enter the secure area. By locking the doors to the vestibule, the vestibule can operate as a man trap in the event adversarial activity is suspected. For example, the vestibule may have a time delay that provides security personnel with time to examine an individual who seeks to leave the secure area. The time delay is triggered by the opening and closing of one of the doors, indicating that the individual seeking egress has entered the vestibule. Before the expiration of the time delay, however, the security person accesses the vestibule to view the individual or individuals and, among other things, to confirm that the correct number of individuals are present. If adversarial activity is suspected, the security person actuates an emergency switch or the like which locks the individual or individuals in the vestibule. Otherwise, upon expiration of the time delay, the other vestibule door opens, enabling the individual to leave.
Regardless of the type of security system used, there are always safety concerns regarding persons within the secure area who must be able to escape in the event of catastrophic events such as fires, explosions, etc. These safety concerns typically are addressed by providing secure entry doors with emergency panic opening features so that insiders may exit in the event of an emergency. Also, either in addition to or in lieu of panic opening features on secure entry doors, one or more separate emergency "panic opening" or "crash out" doors can be provided to allow insiders to exit at any time.
Although such panic opening doors are nearly foolproof in safeguarding the emergency escape of those in secure areas, they present a serious security risk. Where such panic opening doors are provided, the security system may be entirely defeated when an adversarial insider, who presumably is authorized to be within the secure area, opens the panic opening door to make an unauthorized exit or to admit an unauthorized person. Such insiders potentially include disgruntled employees, psychotics and criminals who have obtained authorization to be present in the secure area through fraud or deceit. Prior security systems fail to satisfactorily address this problem.
Accordingly, there is a need in the art for a security system that controls the ingress to and egress from a secure area, and that also addresses the problem of insider adversarial activity, all without impairing the ability of those in the secure area to escape when an by emergency arises.

Secure area ingress/egress control system


A method for fabricating a solid-state image sensor includes the steps of forming a well of a first conductivity type in a substrate of a second conductivity type, forming a plurality of photoelectric conversion regions in the well, forming a plurality of charge coupled devices in the photoelectric conversion regions, forming a gate insulating layer over the substrate, forming a polysilicon layer over the gate insulating layer, forming a cap insulating layer over the polysilicon layer, forming a first optical shielding metal layer over the cap insulating layer, forming a first insulating layer over the first optical shielding metal layer, patterning the polysilicon layer, cap insulating layer, the first optical shielding metal layer, and the first insulating layer to form polygates, forming sidewall spacers on sides of the cap insulating layer and the polygate, forming a second optical shielding metal layer on sides of the first optical shielding metal layer and the sidewall spacers, and removing the first insulating layer.

1. Field of the Invention
The present invention relates to a method for fabricating a solid-state image sensor, and, more particularly, to a method for fabricating a solid-state image sensor using self-alignment to form an optical shielding metal (OSM) layer, thus improving its sensitivity and solving the smear problem.
2. Discussion of the Related Art
A solid-state image sensor is a device which images a subject and then outputs the imaged subject as electrical signals by using photoelectric conversion devices and charge-coupled devices (CCDs). By using potential changes in the substrate, CCDs transfer in a predetermined direction charges generated in the photoelectric conversion devices, e.g., photodiodes.
A general solid-state image sensor includes a plurality of photoelectric conversion regions, e.g. photodiodes, vertical charge coupled devices (VCCDs) formed between the photoelectric conversion regions for transferring in a vertical direction the charges generated in the photoelectric conversion regions, a horizontal charge coupled device (HCCD) for transferring in a horizontal direction the charges transferred in a vertical direction by the VCCDs, and a floating diffusion region for sensing and amplifying the charges transferred in a horizontal direction and then outputting the charges to a peripheral circuit.
A conventional solid-state image sensor will now be described with reference to the accompanying drawings.
FIG. 1 is a cross-sectional view showing a structure of a solid-state image sensor, which includes a p-type well 2 formed beneath the surface of an n-type semiconductor substrate 1. Buried charge coupled devices (BCCDs) 3 are formed in the p-type well 2 and spaced apart from one another, PD-N regions 4 are formed in the p-type well 3. Channel stop layers 5 are formed partially around the PD-N regions 4. PD-P regions 6 are formed on the PD-N regions 4. A gate insulating layer 7 is formed on the entire surface including the PD-N and PD-P regions 4 and 6 and the BCCDs 3. Polygates 8 are formed over the BCCDs 3 and above the gate insulating layer 7. An insulating layer 9 is formed to cover the polygates 8. OSM layers 10 are formed on the entire surface except over the PD-N regions 4. At this time, the BCCDs 3 stand for VCCDs.
An operation of a conventional solid-state image sensor having such a structure will now be described. Charges accumulated in photoelectric conversion regions, e.g., the PD-N regions 4 and the PD-P regions 6, which convert the image into electric signals, are transferred to BCCDs 3 by clock signals, applied to a transfer gate (not shown). Then, the charges transferred to the BCCDs 3 are transferred in a vertical direction by clock signals applied to the polygates 8. The OSM layer 10, formed on the gate insulating layer 7 and the insulating layer 9 (except over the PD-N regions 4), prevents photons from directly entering the BCCDs 3.
FIG. 2 is a cross-sectional view showing problems of the conventional solid-state image sensor. In general, the OSM layer 10 is made of a metal having a 99% reflectivity.
A process for forming an OSM layer in a conventional solid-state image sensor will now be described. First, a gate insulating layer 7 is formed on the entire surface including the photoelectric conversion regions, i.e. the PD-N and PD-P regions 4 and 6 and the BCCDs 3. Subsequently, the polygates 8 are formed on the gate insulating layer 7 and only on the BCCDs 3, and then the insulating layer 9 is formed on the entire surface of the polygates 8. Thereafter, an OSM layer 10 is formed on the insulating layer 9 and the gate insulating layer 7, except over the PD-N regions 4. To form the OSM layer 10, optical shielding metal is formed on the entire surface of the insulating layer 9 and is selectively patterned by photolithography and photo etching processes. The insulating layer 9 is selectively removed over the PD-N regions 4.
However, as the number of pixels increases in order to obtain a miniaturized device with good resolution, minimum line width is reduced, and margins for the photolithography is also reduced. Accordingly, if misalignment exists, as shown in FIG. 2, the OSM layer 10 can shift over a portion of the PD-N region 4. If so, a smear can result, where light is smeared into the CCDs (mainly into VCCDs) at one side of a light-receiving part (PD-N) where the OSM layer 10 is not formed. At this time, the smear, where carriers due to light leakage are directly transferred to adjacent CCDs, can cause a phenomenon where a trail is dragged in a vertical direction on a screen.
FIG. 3 is a cross-sectional view showing a structure of another conventional solid-state image sensor. The structure of this solid-state image sensor is similar to that of the solid-state image sensor shown in FIG. 1. The difference between these two sensors, however, is that an OSM layer 10 of FIG. 3 covers the edge portions of the PD-N region 4. The solid-state image sensor shown in FIG. 3 is designed to solve the problem generated in a solid-state image sensor shown in FIG. 2. Since the OSM layer 10 is expanded by a predetermined distance D, light is blocked from transmission through PD-N regions 4 in spite of misalignment.
However, such conventional solid-state image sensors have the following problems. First, as the number of pixels increases to obtain miniaturized devices with light weight and high resolution, process margins for photolithography decrease. Accordingly, the possibility of misalignment and smear is high, thus affecting the reliability of a solid-state image sensor.
Second, in the conventional solid-state image sensor as shown in FIG. 3, an OSM layer is formed over edges of a PD-N region in order to prevent the smear. However, total light-receiving area is decreased even though the OSM layer is precisely patterned, thereby degrading its sensitivity. If misalignment also exists, the sensitivity of the device becomes inferior, and its performance deteriorates.

Method of fabricating solid-state image sensor


A method, system and computer program product for generating and verifying the correctness of isolation logic modules in design of integrated circuits (ICs). The method disclosed generates an isolation logic module for each power domain specified by a user, instantiates the generated module in a pre-determined wakeup domain, and then simulates shutdown conditions to ensure the correctness of the generated isolation logic module. The isolation logic is generated based on user-defined voltage constraints.

1. Field of the Invention
The present invention relates generally to the design of integrated circuits (ICs) and more particularly to methods for generating and verifying isolation logic in the design of ICs.
2. Description of the Related Art
Complex electronic systems are typically designed using integrated circuits (ICs) comprising multiple functional blocks. An IC may have a wide range of power supply conditions, a number of independent power domains, and circuit performance objectives. Generally, different power domains are established between digital, analog and radio frequency (RF) functional blocks on an IC. As an example, a wireless handset chip has several power domains due to multiple modes of operation.
Referring to FIG. 1, an exemplary circuit 100 including two power domains 110 and 120 is shown. The power domains 110 and 120 are logic units serving different functions. Power domains 110 and 120 are powered by signals VC1 and VC2 supplied by a level shifter 130, which translates power signals between two voltage domains. For example, level shifter 130 may translate signals originating from a first domain operating under a lower supply voltage (e.g., 1.2V) to a second domain operating with a higher supply voltage (e.g., 2.5V). However, it should be noted that power domains do not have to be connected to a level shifter.
For power management purposes and reducing power consumption, parts of a design are usually turned off during the operation of a semiconductor device. Specifically, power domains that power IC areas not actively used in certain modes of operation are completely shut down. A correct design requires that when a power domain is shut down, its output signals will not become indeterminable so that an unknown state is transferred to the rest of the design.
Moreover, leakage power is a critical concern for design of ICs that operate in stand-by mode and are manufactured using advanced fabrication technologies, such as 90 nm and below. Turning off a supply to the regions of design in such modes of operation eliminates leakage power consumption associated with these regions completely. For isolating and enforcing stable output values at shutdown, the outputs of power domains 110 and 120 are connected to isolation logic modules 140 and 150 respectively. Isolation logic modules 140 and 150 ensure that power domains 110 and 120 are correctly isolated and none of their outputs is left indeterminable, and are therefore determinable, when the power is off. The design of isolation logic demands a designer to determine a set of shutdown constraints including steady state output values, shutdown conditions, wakeup/shutdown signals, and so on.
Prior art design tools, e.g., computer aided design (CAD) do not provide automated means for isolating power domain in the design, i.e., generating and inserting isolation logic modules in the design. Moreover, such tools generally require that the user identify all power domains in the design, define an isolation logic for each domain and check its correctness. In ICs where the number of power domains may be large, this is an inefficient, time-consuming, as well as an error prone task.
It would be, therefore, advantageous to provide a solution that automatically generates isolation logic modules for power domains and appropriately places these modules in the design. It would be further advantageous if the provided solution automatically detects isolation logic modules within the design and checks their correctness.

This patent is subject to a terminal disclaimer.

Method, system, and computer program product for generating and verifying isolation logic modules in design of integrated circuits


A wireless communication method and apparatus that produce only a small amount of transmission delay even when carrier sensing is performed. Intensity indication data indicating the radio wave intensity of a received wireless signal is generated. The intensity indication data is intermittently captured and retained. An average of the retained intensity indication data is calculated. If the average is less than or equal to a threshold, a wireless transmission operation is enabled. The average is calculated with a frequency according to the frequency of capturing of the intensity indication data. The average and the threshold are compared at a frequency corresponding to the frequency of calculation of the average.

1. Field of the Invention
The present invention relates to a wireless communication method and apparatus for performing communication by using a wireless signal.
2. Description of the Related Art
A wireless communication system including a base station and a plurality of wireless communication terminals each transmitting data retained in the own terminal (hereinafter, referred to as retained data) to the base station has been known heretofore. Examples of communication schemes employed in such a system include carrier sense multiple access/collision avoidance (CSMA/CA). According to the CSMA/CA communication scheme, when a wireless communication apparatus transmits its own retained data, the wireless communication apparatus performs so-called carrier sensing (CCA: Clear Channel Assessment) to make sure that no other wireless communication apparatus is transmitting retained data (for example, Patent Literature 1). The purpose of the CCA operation is to prevent the transmission of the own retained data from being interfered with and hindered by transmission waves of retained data from other wireless communication apparatuses. Specifically, a wireless communication terminal measures a wireless signal intensity around the own terminal for a predetermined period, and transmits retained data if an average intensity in the period is less than or equal to a predetermined value.

Wireless communication method and apparatus


A digital VCR incorporates an IC card reader/writer that cooperates with an IC card that stores therein control data corresponding to the transmission format of video signals to be recorded. The signal processing circuits with the digital VCR are controlled by the control data and are structured of digital signal processors and the operations of the circuits are controlled such that the sync block length and the like of the record data are controllable. A host interface is connected to a modem is and the modem connected to a host computer of a bank, a department store, or the like through the public phone network, so that the digital VCR can be utilized as a terminal unit for an IC card application system for home banking, home shopping, and so on.

1. Field of the Invention
The present invention relates to a digital video signal recording and reproducing apparatus such as a digital video cassette recorder (VCR) and, more particularly, to a digital video signal recording and reproducing apparatus incorporating an IC card reading/writing unit.
2. Description of the Background
There have been put on the market various types of analog VCRs for use in the home. Although a home digital VCR has not yet been marketed, there are a number of examples that underwent trial manufacture and these are identified by Y. Eto, et al. in "Digital Video Recording Technology", p. 158.
Since the above-described analog VCRs and digital VCRs have their circuits arranged to record and reproduce video signals in the existing formats, in the event that a video signal in a new format is employed, they cannot record and reproduce the signal unless additional circuits supporting the new format are attached to them. Further, such VCRs are unable to perform operations other than recording and reproducing video signals.

Recording and reproducing device for digital signal including IC card


An image lens array, from object side, comprises: a first positive meniscus plastic lens with a convex surface facing forward, a second negative meniscus plastic lens with a concave surface facing forward, a third positive meniscus plastic lens with a convex surface facing forward, and an infrared filter disposed in the lens barrel of the image lens array, the central thickness of the first and second lenses are: CT1<1.0 mm, CT2<0.6 mm. The radius of curvature of the front and back surfaces of the first lens are L1R1 and L1R2 that satisfy the condition as: |L1R1/L1R2|<0.5. The radius of curvature of the front and back surfaces of the third lens are L3R1 and L3R2 that satisfy the condition: |L3R1/L3R2|>0.3.

1. Field of the Invention
The present invention relates to an image lens array for a small image taking device, and particularly to a mid-aperture type image lens array consisted of three plastic lenses that are provided with aspherical surfaces.
2. Description of the Prior Arts
Since the image pick up lens has an increasingly wide range of application, plus the consumer electronic industrial is growing fast, the small image pick-up lens is accordingly found in great demand in different fields, particularly in photographic cell phone, digital camera, or auto's detection system for parking or other purposes.
A photosensitive element for a digital fixed focus lens array generally includes charge coupled device (CCD) type or CMOS type Complementary Metal Oxide Semiconductor, and its light sensitivity will be reduced sharply with the increase of exit angle of the lens. Therefore, the digital fixed focus lens array is usually provided with telecentric type for prevention of shading problem. However, most of the existing over Megapixel lens arrays are consisted of 3-4 lenses approximately 5.5-7 mm high, these types of lens arrays still have some technical defects as follows:
First, the exit angle of over Megapixel lens array should be reduced, considering the brightness, so that the optical system needs a large space to refract light. Since most of the aforementioned optical systems are 5.5-7 mm high (cannot be reduced further), even if the future pixel is further minimized as a result of further advancement of semi-conductor technology, the resolution of the optical systems should be high, thus causing difficulties in making a handy and light lens array.
Second, most of the conventional digital fixed focus lens array employ front aperture to correct aberration, however, the front aperture arrangement will lead to an increase both in stray light and sensitivity of the optical system, substantially complicating the design process.
U.S. Pat. No. 6,441,971B2 discloses a small image lens array with large aperture (f/2.5), the specification of the photosensitive element is ¼ inch while the total length of the image lens array is up to 5.3 mm. As for the existing small image lens array, every 0.1 mm reduction in the total height of the lens array will lead to a substantial degradation of the resolution quality.
The present invention has arisen to mitigate and/or obviate the afore-described disadvantages.


A filling paste structure and process of wafer level package is disclosed. The process comprises filling an adhesive material to fill among plurality of dice and cover the plurality of dice. The pluralities of dice are adhered to glue pattern with viscosity in common state formed on a removable substrate. A rigid substrate is coated by adhesive material to adhere the dice. Then, pluralities of dice are departed from the glue pattern by a special environment after attaching the rigid base substrate.

1. Field of the Invention
This invention relates to a filling paste structure and process of wafer level package, and more particularly to a structure and process by using the top side face down filling paste to make flatness of dice surface and without overflowing or recessing on the surface of dice, thereby improving filling paste performance and life cycle during reliability testing.
2. Description of the Prior Art
As a suitable semiconductor device for a high-pin-count package, a semiconductor device having a BGA (Ball Grid Array) structure has been developed. In this semiconductor device with a BGA structure, a semiconductor chip is mounted on a chip mount area of a main surface of a base substrate by using adhesive material and several bump electrodes are positioned in an array on the back side thereof that is opposite to said main surface of the base substrate.
The CSP has been conventionally formed by a method in which a semiconductor wafer is cut into semiconductor chips, then the semiconductor chips are mounted on a base substrate serving as a package base at predetermined positions and bonded thereto, and they are collectively sealed with a resin, thereafter the sealing resin and the base substrate are cut into pieces together at the parts between the semiconductor chips. In another conventional method, a semiconductor wafer (not being cut into semiconductor chips yet) is mounted on a base substrate and bonded thereto, then the semiconductor wafer and the base substrate are cut together, and the cut and divided semiconductor chips and package bases are sealed with a resin.
However, in the former conventional manufacturing method, a problem exists in that the method essentially includes a step of positioning and mounting the cut and divided semiconductor chips one by one on the base substrate. Like wise in the latter conventional manufacturing method, a problem exists in that the method essentially includes a step of sealing the cut and divided semiconductor chips and package bases one by one with a resin. Both conventional methods require a number of working processes equal to the number of semiconductor chips, which results in a disadvantage of low productivity.
Besides, at present, filling paste process of any type IC device package is adopted directly printing filling paste among the dice, shown as FIG. 1. The pluralities of dice 91 are formed on a glass base substrate 90. Silicone rubber 92 is formed on the glass base substrate 90 by using a printing method. In general, such filling paste technique causes an overflow filling paste on the surface of the dice in printing direction and a recess filling paste on the surface of the dice in non-printing direction, shown as FIG. 2A and FIG. 2B, respectively. The filling paste may cover the bonding pad of the die. That is to say, such filling paste process of prior art will suffer yield and reliability issues owing to poor uniformity of the filling paste on the surface of the dice.
Therefore, the present provides a new filling paste process of wafer level package to improve yield and reliability of the dice of wafer level package.

Packaging structure with coplanar filling paste and dice and with patterned glue for WL-CSP

Advanced Chip Engineering Tachnology Inc.