There is provided a piezoelectric actuator which includes a piezoelectric material layer in which, a portion sandwiched between a first electrode and a second electrode is an active portion, and a vibration plate which is arranged on a surface of the piezoelectric material layer. The piezoelectric material layer is polarized in a direction parallel to a direction of thickness thereof, and a direction of polarization of a central portion in the active portion and a direction of polarization of an edge portion excluding the central portion, in the active portion are mutually opposite. Accordingly, even when a drive voltage is low, it is possible to increase sufficiently an amount of deformation of the piezoelectric actuator.

1. Field of the Invention
The present invention relates to a piezoelectric actuator which deforms a piezoelectric material layer by applying an electric field to the piezoelectric material layer, a liquid transporting apparatus which includes the piezoelectric actuator, and a method of manufacturing the piezoelectric actuator.
2. Description of the Related Art
In US Patent Application Laid-open No. 2006082619 (corresponds to Japanese Patent Application Laid-open No. 2006-093348), an ink-jet head which transports an ink to nozzles, and jets the ink onto a paper from these nozzle has been disclosed. This ink-jet head includes a channel unit in which ink channels including pressure chambers which communicate with the nozzles are formed, and a piezoelectric actuator which causes the ink to be jetted from the nozzles by changing a volume inside the pressure chambers.
The piezoelectric actuator includes a vibration plate which covers openings of the pressure chambers, a piezoelectric material layer which is formed on a surface of the vibration plate, and subjected to a polarization process such that the piezoelectric material layer is polarized in a direction of thickness thereof, and an individual electrode which is formed on a surface of the piezoelectric material layer, on a side opposite to a side of the vibration plate, in an area slightly smaller than an area facing the pressure chamber. The vibration plate is kept at a ground electric potential, and functions as a common electrode. In other words, an active portion, of the piezoelectric material layer, sandwiched between the individual electrode and the common electrode is positioned at a central portion of the piezoelectric material layer facing the pressure chamber.
In the abovementioned piezoelectric actuator, when a predetermined driving electric potential is applied to the individual electrode, an electric field is generated in the active portion, of the piezoelectric material layer, sandwiched between the individual electrode and the common electrode; and the active portion is contracted in a direction orthogonal to a direction of thickness thereof. Moreover, due to the contraction of the operation portion of the piezoelectric material layer, a first portion, of the piezoelectric actuator, corresponding to the operation portion positioned at the central portion of the piezoelectric material layer facing the pressure chamber, is deformed spontaneously to form a projection toward the vibration plate; and a second portion, of the piezoelectric actuator, surrounding the first portion is deformed passively due to the first portion. Accordingly, an entire portion of the piezoelectric actuator, facing the pressure chambers is deformed to form a projection toward the pressure chamber. Due to the deformation, the volume inside the pressure chamber is decreased, and a jetting pressure is exerted on an ink in the pressure chamber.

Piezoelectric actuator, liquid transporting apparatus which includes piezoelectric actuator, and method of manufacturing piezoelectric actuator


Methods, control apparatus and series resonant or LLC power conversion systems are presented in which a resonant series circuit current is compared with a threshold during a portion of a modulation switching cycle following turn on of a corresponding switching device and one or more indications or remedial actions are undertaken to modify modulation control of a switching circuit in response to a determination that the resonant current is below the threshold to facilitate our promote zero voltage switching or near-zero voltage switching and provide current reversal protection.

LLC converters are a form of series resonant converters having a series resonant circuit including a transformer primary winding in which a switching circuit is used to alternately couple a switching node of a resonant circuit or tank circuit to a positive supply node or a ground node to provide an alternating resonant current flow through the transformer primary winding. A secondary circuit, such as a rectifier, provides an output voltage to drive a load, with the switching circuit operation being adjusted to regulate the output voltage. Series resonant converters can operate in a so-called inductive mode or in a capacitive mode depending on the operating frequency and impedances of the resonant circuit and the secondary circuit, with the impact of the output rectifier and any associated filter circuitry being reflected back into the primary resonant circuit through the turns ratio of the transformer, whereby the load impedance including the secondary circuitry is essentially in series with the resonant circuit. Frequency control of the switching circuit can be used to regulate an output condition (e.g., output voltage, output current, etc.) based on one or more feedback signals, where the resonant circuit impedance is minimized at a resonant frequency. LLC converters provide a resonant inductance, typically an inductor connected in series with the transformer primary winding and a resonant circuit capacitance, as well as a magnetizing inductor in the series circuit, with LLC resonant converters typically having two resonant frequencies. Operation at the higher resonant frequency advantageously facilitates regulation of a wide load range with minimal frequency adjustment.
LLC converters are preferably designed to operate in an inductive region with the resonant circuit current lagging the voltage. The lagging current operation in the inductive region facilitates zero-voltage-switching (ZVS) on the MOSFETs or other switching devices used in the series resonant converter, thereby enhancing system efficiency while mitigating switch degradation. However, certain operating conditions may change the resonant circuit operation toward the capacitive region, thereby inhibiting zero voltage or near-zero voltage switching operation. As a result, operation in the capacitive region is undesirable, and may lead to current reversal stresses on the switching components. Although operating frequency, resonant circuit component values and other system design parameters can be tailored to help prevent or minimize operation in the capacitive region, input voltage brownout or other drops in input voltage and/or output current overload conditions may cause a circuit to operate in the capacitive region, which can lead to undue stress on the switching devices. Also, certain circuit configurations may be subject to capacitive mode operation at startup before resonant circuit capacitors are fully charged to a steady state value. Thus, capacitive region operation reduces system efficiency, and may in some cases lead to degradation or damage to the switching devices. Accordingly, a need remains for improved control apparatus and techniques to promote zero voltage switching or near-zero voltage switching and mitigate operation in the capacitive region for LLC and other series resonant converters.

LLC converter and loss of inductive mode detection circuit


A new variety of carnation plant named ‘CFPC Unforgettable’ having flowers with a light to medium purple color diffused over a cream base color. The center of the flowers are cream color with a faint purple pigmentation gradually becoming darker purple toward the petal edge. The flower coloring gives the new variety a distinctive “watercolor” effect.

The present invention comprises a new and distinct cultivar of hybrid carnation botanically known as Dianthus caryophyllus, and referred to by the cultivar name 'CFPC Unforgettable'.
'CFPC Unforgettable', identified as selection no. 020135, originated from a cross made by Roy Stahlhut in a controlled breeding program in Salinas, Calif.
The female parent of the new variety is the patented variety known as 'CFPC Sari' (U.S. Plant Pat. No. 14,843) and the male parent is the unpatented variety known as selection no. 000809-6. The new variety 'CFPC Unforgettable' has been asexually reproduced by vegetative side shoot cuttings in Salinas, Calif. and the distinguishing characteristics are retained through successive generations of asexual reproduction.

Carnation plant named ‘CFPC Unforgettable’


A quick-coupling device for a milking module of a milking system for milking dairy animals that forms a releasable and re-establishable connection between the milking module and a milk pipe and includes a valve mechanism for opening and closing a feeding port and a discharge port using a number of articulated clamps.

The invention relates to a quick-coupling device for a milking module in an automated dairy animal milking system.
Milking systems, as are used for example for the automatic milking of dairy animals, for example cows, sheep or goats, may be provided with such quick-coupling devices. An automatic milking process may be carried out by means of so-called milking robots. The quick-coupling devices serve to release a milking module from a milk pipe, for example in order to change it for the purpose of cleaning or replacement. The milk pipe may conduct so-called "good" or "bad" milk.
The document EP 0 671 875 B2 describes a milk pipe valve. A valve with a hose connection part is fastened in a valve guide on a milk pipe. When attaching or removing the connector, this valve is displaced such that it either closes or opens a cross section of the milk pipe. The valve always remains fixedly connected to the system. In this case, it is perceived as a drawback that a region of the valve is not able to be reliably cleaned. After the valve is closed, this region is located directly inside the milk pipe.
However, the relevant national regulations and guidelines which apply to pipes and equipment for milking systems and milking equipment which come into contact with milk, for example the American FDA guidelines, have to be observed and maintained.
Due to the continually increasing, and in particular different, national requirements, in particular relative to high throughput rates and continuous low-maintenance operation and/or operation with long maintenance intervals, there is a need for simple and reliable devices, i.e. also conforming to specific regulations.


A novel method for producing a stereoselective epoxyketone compound is provided. A method for producing an epoxyketone compound represented by the formula (1), as represented by the following scheme, whereby it is possible to obtain an epoxyketone derivative in good yield and at high selectivity and to provide an industrially useful production method and an intermediate thereof. wherein R1 is a hydrogen atom, a linear, branched or cyclic alkyl group, an aromatic group which may have a substituent, or a heterocyclic group which may have a substituent, and R2 is a protective group for an amino group. R is a hydrogen atom or a C1-10 alkyl group, and R's may be the same or different, provided that at least one R is a C1-10 alkyl group.

Epoxyketone derivatives represented by the structural formulae (1a) and (1b) (wherein PG is a protective group, Boc is a t-butyloxycarbonyl group and Cbz is a benzyloxycarbonyl group, and hereinafter, the same applies in this specification) are important compounds as raw materials for medicines, etc. (Non-patent Document 1 and Patent Document 3). Heretofore, as methods for their production, a production method of directly epoxidizing an α,β-unsaturated ketone (2a) (Non-patent Document 1) and a synthetic method of epoxidizing an allyl alcohol (3a) or (3b) obtainable by reducing an α,β-unsaturated ketone (2a) or (2b), followed by oxidation of an epoxy alcohol (4a) or (4b) (Patent Documents 1, 2 and 3), have been known.

Method for producing stereoselective epoxyketone compound


A method for a continuation model predictive control (CMPC) of a system determines at least a part of a preconditioner using an approximate coefficient function and determines a solution vector by solving a matrix equation of the CMPC with a coefficient matrix defined by an exact coefficient function at a current time step of a control using an iterative method with the preconditioner. The approximate coefficient function applied to a vector approximates a result of an application of the exact coefficient function to the vector. A control signal for controlling the system is generated using the solution vector.

Model predictive control (MPC) is used in many applications to control complex dynamical systems. Examples of such systems include production lines, car engines, robots, other numerically controlled machining, and power generators.
The MPC is based on an iterative, finite horizon optimization of a model of a system. The MPC has the ability to anticipate future events, and to take appropriate control actions. This is achieved by optimizing the operation of the system over a future finite time-horizon subject to constraints, and only implementing the control over a current time step.
The MPC can predict the change in dependent variables of the modeled system caused by changes in independent variables. In a chemical process, for example, independent variables that can be adjusted by the controller are often pressure, flow, temperature, opening of the valves, and stiffness of dampers. Independent variables that cannot be adjusted by the controller are treated as disturbances. Dependent variables in these processes are other measurements that represent either control objectives or process constraints.
The MPC uses models of the system, the current system measurements, the current dynamic state of the process, and the process variable targets and limits to calculate future changes in the dependent variables. These changes are calculated to hold the dependent variables close to target subject to constraints on both independent and dependent variables. The MPC typically sends out only the first change in each independent variable to be implemented, and repeats the calculation when the next change is required.
The MPC numerical methods are implemented on various computational apparatus often designed specifically for a given system. Computational apparatus can range from inexpensive fixed-point precision embedded controllers to sophisticated multi-core computer processor units (CPU), graphics processing unit (GPU), field-programmable gate array (FPGA), or dedicated parallel computer clusters.
Model predictive controllers rely on dynamic models of the process, most often linear empirical models, in which case the MPC is linear. Nonlinear MPC (NMPC), which describes systems with nonlinear models, is often more realistic, compared to the linear MPC, but computationally more difficult. Similar to the linear MPC, the NMPC requires solving optimal control problems on a finite prediction horizon, generally not convex, which poses challenges for obtaining a numerical solution. The numerical solution of the NMPC optimal control problems is usually based on Newton-type optimization schemes.
Exact Newton-type optimization schemes require an analytic expression of a corresponding Jacobian matrix, which is rarely available in practice and is commonly replaced with a forward difference (FD) approximation. Such approximate Newton-type optimization schemes utilize the FD) approximation of the original nonlinear equation during every time step of the control.
In and application to the NMPC, such the approximate Newton-type optimization can be performed by a Continuation NMPC (CNMPC) numerical method described by Ohtsuka, T., "A Continuation/GMRES Method for Fast Computation of Nonlinear Receding Horizon Control," Automatica, Vol. 40, No. 4, pp. 563-574, Apr. 2004, one of the key repetitive and most computationally intensive steps in on-line calculations with CNMPC is numerical solution of a matrix equation Ax=b, where A is a coefficient matrix, x is a solution vector and b is a vector. The solution varies, from one time step of control to the next one) the coefficient matrix A and the vectorb.
The coefficient matrix A in the CNMPC is not explicitly given and available only via matrix-vector products. Specifically, a computer code is available to compute a product A*X, where A is the coefficient matrix, * is a matrix-matrix product, and X is a single column-vector, or several column-vectors assembled into a matrix. In this disclosure, the action of this computer code is referred as an application of"a coefficient function." The coefficient function applied to a vector returns a product of the coefficient matrix and the vector. Internally, the coefficient function requires, e.g., evaluation of the state and costate equations by solving a number of differential equations, as described by Ohtsuka.
Because the coefficient matrix A is only available via the coefficient function, rather than in the matrix format, direct matrix solvers, requiring access to matrix entries, are not used in the CNMPC. Instead, so-called "matrix-free" iterative methods are used, which can operate having only the coefficient function without the coefficient matrix A. One conventional matrix-free iterative method for solving the matrix equation Ax=b of the CNMPC is a generalized minimal residual (GMRES) method. The use of GMRES for the FD approximation of the nonlinear equation during every time step is commonly called FDGMRES, and can be interpreted as inexact Newton's method. In the context of CNMPC, the FDGMRES is named Continuous/GMRES (C/GMRES).
The FDGMRES requires matrix-vector multiplications involving the coefficient function. The overall cost of computations is proportional to the maximal number of FDGMRES steps. Slow convergence of the FDGMRES results in slowing down on-line computations of the control and reducing control quality obtained in real time calculations in the controller.
Accordingly, it is desired to increase an efficiency of a continuation model predictive control of a system.

Method and apparatus for preconditioned continuation model predictive control

Mitsubishi Electric Research Laboratories, Inc.


A heel holder arrangement of a safety ski binding has a sole holder which is pivotable about a first axis parallel to the surface of the ski between a position of locking the heel of a ski boot and a release position. Arranged behind the sole holder and pivotable about a second parallel axis is a retaining lever which at its upward end carries at least one retaining roller. The retaining roller co-operates both with a cam surface on the sole holder and also with a cam surface on a pivotable opening lever which is loaded by a compression spring. The cam surface on the sole holder includes a retaining recess in which the retaining roller is engaged when the sole holder is in the locking position. The spring is pivotable with the opening lever. The cam surfaces jointly determine the force-travel characteristic of the sole holder both in the event of safety release of the arrangement and also upon voluntary opening by actuation of the opening lever. A brace member is pivoted at a first end on the first axis and has its second end engaging the rear of the sole holder. At its first end the brace member also has a contact surface which can be engaged by the end of the compression spring as it is pivoted upon pivotal actuation of the opening lever. The brace member being pivoted about the first axis under the spring loading, it causes the sole holder to be pivoted into its release position after the movement of the opening lever allows the retaining roller to come out of the retaining recess of the cam surface of the sole holder.

This invention is generally concerned with a heel holder arrangement of a safety ski binding.
A safety ski binding typically comprises a front sole holding arrangement which is operable to hold the front edge of the sole of a ski boot in position, and a heel holding arrangement which similarly locates the heel of the ski boot on the ski. In a heel holding arrangement as disclosed in German laid-open application (DE-OS) No 33 22 634, a sole holder which, when in the locking position, engages over the upper edge of the sole at the heel end of the boot thereby to fix the boot on the ski, carries at its lower end a kicker or spur portion on which the skier presses with the heel of his boot in order to fit the boot into the safety ski binding, by consequentially moving the sole holder into the locking position. So that the sole holder is always held in the condition of being ready for insertion of a boot, and also for assembly reasons, it is desirable for the movement of the sole holder out of the locking position into the release position to occur substantially automatically under the effect of the force of a spring, when an opening lever for releasing the sole holder is actuated. For that purpose, the opening lever of the above-indicated known arrangement is mounted pivotably on the sole holder, with the mounting axis for the opening lever being arranged behind and below the mounting axis for the sole holder. Therefore, when the opening lever is pressed down, the sole holder is already loaded in the direction of opening of the holder arrangement, in the first phase of the movement involved. In addition, that heel holder arrangement has a retaining lever to hold the sole holder in its locking position, and the retaining lever and the opening lever are connected by a coupling member which forms a spring plate for the compression spring which urges the sole holder from the locking position towards the release position. The sole holder further comprises a cam configuration which in turn also provides a cam detent portion or notch arranged to receive a roller carried on the retaining lever to hold the sole holder in the locking position. The cam configuration is such that the sole holder can pivot into its release position under the influence of the compression spring, by way of the retaining roller, as soon as the retaining roller has moved out of the above-mentioned cam notch. The retaining lever is mounted behind the sole holder, pivotably about an axis which is parallel to the pivot axis of the sole holder, with the retaining roller being carried on the retaining lever at its upper end. The opening lever is mounted pivotably about a third axis which extends parallel to the surface of the ski on which the ski binding is used. The compression spring of the heel holder arrangement bears against the coupling member so that the retaining lever is spring-loaded thereby and the retaining roller is thus urged against the cam configuration, thereby to define the force/travel characteristic involved in the opening movement of the sole holder. As noted above, the retaining roller can engage into a notch in order for the ski boot to be held under a spring force on the ski, while the cam configuration in the region of that notch, in conjunction with the lever arm of the retaining roller and the lever arm in respect of engagement of the spring against the retaining lever define the release time in respect of safety release of the heel holder arrangement. The cam configuration outside the notch thereof determines the force required for insertion of a ski boot into the holder, being the force which the skier must overcome by standing on the above-mentioned spur portion of the sole holder in order thereby to pivot the sole holder from its release position into its locking position. When the opening lever is actuated by the skier, to release the holder arrangement, the retaining roller is lifted out of the notch in the cam configuration so that the sole holder can pivot upwardly in an unloaded condition.
The fact that the compression spring bears against the coupling member which connects the retaining lever and the opening lever, the way in which the coupling member is disposed in the assembly, and the arrangement of the compression spring in the housing beneath the opening lever, means that the arrangement requires a relatively large amount of space while in addition the structural size thereof is increased as a result.

Heel holder arrangement of a safety ski binding


A memory interface enables AC characterization under test conditions without requiring the use of Automated Test Equipment (ATE) and functional patterns. The memory controller may be configured to generate output patterns through the test interface and create a loopback path for input specification testing using an external stressed-eye random number generator and checker. As a result, the memory interface may be evaluated for electrical and timing specifications under a relatively simple test setup and test procedure through the test interface (JTAG), as opposed to a complex processor program that sets up a similar memory access pattern on Automated Test Equipment (ATE).

Semiconductor vendors are responsible for validating all specifications listed in their datasheets either through production testing or through characterization. Production testing means that all parts shipped are tested against all specifications in the product datasheet. Characterization is employed when production testing is not possible or not economically feasible. Characterization means that a collection of parts (around 10) are selected from skewed lots that represent process variation and are subjected to bench characterization of the above specs across voltage and temperature. A report is generated at the end which is typically available to customers. The report shows that all table specifications are met across PVT.

Memory interface with selectable evaluation modes


A method of manufacturing an LCD device is disclosed, which can improve yield by preventing occurrence of a contact failure between a transparent conductive film and a pad region (gate and data regions). In this method, amorphous transparent conductive films connected to a drain electrode, a gate pad and a data pad are formed of a transparent conductive material.

1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a method for manufacturing a pad region of an LCD device.
2. Discussion of the Related Art
In general, an LCD device according to a related art includes a lower substrate having a TFT and a pixel electrode, an upper substrate having a color filter film for displaying colors and a common electrode, and a liquid crystal film between the lower and upper substrates.
The LCD device according to the related art will now be described in more detail.
FIG. 1 is a layout of a TFT array region and a pad region in a lower substrate of a general LCD device.
To define a plurality of pixel regions, a plurality of gate lines 100 are formed on the lower substrate (not shown) at constant intervals, and a plurality of data lines 200 are formed perpendicular to the gate lines 100 at constant intervals. Then, a plurality of TFTs (thin film transistors) are formed at crossing points of the plurality of gate and data lines 100 and 200.
In each TFT, a gate electrode 2a projects from the gate line 100, and a semiconductor film 4 in an island shape is formed above the gate electrode 2a. A source electrode 6 projects from the data line 200 toward the semiconductor film 4, and a drain electrode 7 is formed in a portion where the source and drain electrodes 6 and 7 oppose each other. A pixel electrode 9a made of ITO is electrically connected to the drain electrode 7 of the TFT in the pixel region.
Although not shown, a plurality of black matrix films are formed, except in the pixel regions, to prevent light leakage from the upper substrate. Then, R/G/B color filter films are formed in the pixel regions between the black matrix films for displaying colors. A plurality of common electrodes are formed on the entire surface of the upper substrate including the color filter films.
Then, the lower and upper substrates are attached to each other with a certain constant distance therebetween, and then a liquid crystal is injected between the lower and upper substrates.
The above LCD device adjusts display conditions by applying a certain voltage to both ends of the lower and upper substrates. A conductive material that does not intercept light has to be deposited on the surfaces of the upper and lower (glass) substrates. Therefore, transparent electrodes are formed on the lower and upper substrates by sputtering. At this time, the common electrodes discussed above are formed on the upper substrate and the pixel electrode is formed on the lower substrate.
In the related art LCD device, the transparent electrode is formed of an indium tin oxide (ITO) film or SnO2 film The ITO film obtains high conductivity, chemical stabilization and thermal stabilization. Furthermore, the ITO is easy to pattern, so that the ITO film as the transparent electrode can be used in both segment and dot matrix. The SnO2 film obtains chemical stabilization and physical strength more than the ITO film, but its conductivity is less than that of the ITO. The SnO2 film also has a problem of forming the electrode by photolithography. As such, the SnO2 Film can not be used as the transparent electrode of a minute pattern in which a low resistance is required.
In general, the ITO film as the transparent electrode provides a low manufacturing cost, a good adhesion to the substrates and photoresists, a low resistance, a high transmittivity, and a uniformity of resistance value, transmittivity and etching ratio. The ITO film as the transparent electrode is also needed not to have an etching residue during the formation of a minute pattern, and is required not to have particles or defects on the surfaces certain layers.
FIG. 2 is a sectional view showing a structure of the related art LCD device taken along line I–I′ (TFT region) and line II–II′ (pad region) of FIG. 1.
As shown in FIG. 2, in the TFT region, a gate electrode 2a is formed on a lower glass substrate 1, and then a gate insulating film 3 is formed on the entire surface of the glass substrate 1 to cover the gate electrode 2a.
A semiconductor film 4 is formed on the gate insulating film 3 above the gate electrode 2a, and then source/drain electrodes 6 and 7 are formed at both sides of the semiconductor film 4. An ohmic contact film 5 is formed between the semiconductor film 4 and the source/drain electrodes 6 or 7.
A passivation film 8 having a contact hole 8a to expose the drain electrode 7 is formed over the glass substrate 1. A pixel electrode 9a is electrically connected with the drain electrode 7 through the contact hole 8a.
In the pad region, a gate pad 2b or a data pad 2c is formed of the same material as a gate line or a data line. As an example, FIG. 2 illustrates the gate pad 2b. The gate insulating film 3 is formed on the glass substrate 1 to cover the gate pad 2b, and then the passivation film 8 having a contact hole 8b to expose the gate pad 2b is formed on the gate insulating film 3. A pad contact film 9b is formed of the same material as the pixel electrode 9a on the gate pad 2b.
As shown in FIG. 2, in the related art LCD device, the gate insulating film 3 and the passivation film 8 are formed of a silicon nitride film. The source/drain electrodes 6 and 7, the gate electrode 2a and the gate pad 2b are formed of a conductive metal such as Cu or Ti. The pixel electrode 9a and the pad contact film 9b are formed of a transparent conductive film such as ITO.
A method for manufacturing the related art LCD device of FIG. 1 will now be described as follows.
A gate electrode material such as Al, Cr or Al alloy is deposited on the entire surface of the substrate 1 by sputtering, and a photoresist (not shown) is deposited. Then, the gate line 100, the gate electrode 2a and the gate pad 2b are formed by photolithography. A silicon nitride film SiNx or a silicon oxide film SiOx is deposited on the entire surface of the substrate 1 including the gate line 100, the gate electrode 2a and the gate pad 2b by a plasma enhanced chemical vapor deposition (PECVD), thereby forming the gate insulating film 3.
The semiconductor film 4 and the ohmic contact film 5 are sequentially deposited over the substrate 1, and then patterned to remain on the gate electrode 2a and the gate insulating film 3.
Subsequently, Al, Cr or Al alloy is deposited over the substrate 1 by sputtering and then is selectively removed to pattern the data line 200 and the source/drain electrodes 6 and 7. Then, the ohmic contact film 5 is removed between the source and drain electrodes 6 and 7.
The passivation film 8 is formed on the entire surface of the substrate including the source and drain electrodes 6 and 7. Then the passivation film 8 and the passivation/gate insulating films 8 and 3 are selectively removed to respectively expose the drain electrode 7 and the gate pad 2b of the pad region through the contact holes 8a and 8b.
A polycrystal ITO is deposited on the entire surface of the substrate including the contact holes by sputtering, and then is patterned, so that the pixel electrodes 9a connected to the drain electrode 7 is formed in the TFT region, simultaneously, the pad contact film 9b connected to the gate pad 2b is formed in the pad region. At this time, the polycrystal ITO is deposited at a thickness of 500 Å.
However, the related art LCD device has the following problems.
The pixel electrode and the pad contact film are formed of polycrystal ITO, so that a stripper diffuses and penetrates a grain boundary of the polycrystal ITO during a removal of the photoresist by patterning the pixel electrode and the pad contact film. Therefore, the stripper generates a galvanic effect with the pad, so that miniature gaps are formed at an interface between the pad contact film and the pad region, causing a contact failure indicated as reference numeral 10 in FIG. 2. It can also cause a change in TFT characteristics and a degraded yield.

Liquid crystal display device and method of manufacturing the same


A method (and apparatus) for operating a disk drive apparatus. The method includes moving a movable member about a fixed position to move a read/write head coupled to a slider to a selected track on a disk. The selected track is at least one of a plurality of tracks. The method includes adjusting a position of the read/write head using an actuating device integrated on the gimbal. The actuating step moves the read/write head relative in a manner normal to the track on the magnetic disk to align the read/write head on the track using a finer and faster alignment of the read/write head than the moveable support member.

This invention generally relates to techniques for operating a disk drive apparatus. More particularly, the present invention provides a method and apparatus for reading and writing information onto a computer disk commonly called a hard disk for storing data. Merely by way of example, the present invention is implemented using such method and apparatus with an actuating device coupled between a read/write head and support member for fine tuning the read/write head onto a data track on the hard disk, but it would be recognized that the invention has a much broader range of applicability.
Storage of information has progressed through the years. From the early days, primitive man stored information on walls of caves, as well as used writings on wood such as bamboo. Since then, people have used wood, silk, and papers as a media for writings. Paper has been bound to form books. Information is now stored electronically on disks, tape, and semiconductor devices. As merely an example, some of the early disks used magnetic technology to store bits of information in a digital manner onto the magnetic media. One of the first disk drives was discovered in the 1950's by International Business Machines of Armonk, N.Y.
Although such disks have been successful, there continues to be a demand for larger storage capacity drives. Higher storage capacity can be achieved in part by increasing an aerial density of the disk. That is, the density increases with the number of tracks per inch (TPI) and the number of bits per inch (BPI) on the disk.
As track density increases, however, the data track becomes narrower and the spacing between data tracks on the disk decreases. It becomes increasingly difficult for the motor and servo control system to quickly and accurately position the read/write head over the desired track. Conventional actuator motors, such as voice coil motors (VCM), often lack sufficient resolution and bandwidth to effectively accommodate high track-density disks. As a result, a high bandwidth and resolution second-stage microactuator is often necessary to precisely position the read/write head over a selected track of the disc. Thus, there is a need for an improved drive apparatus.

Apparatus for PZT actuation device for hard disk drives


The invention refers to switching a physical quantity, wherein the switching is performed by a switching element (SW) according to a control signal received from a control circuit (11), comprising detecting from the control signal (CS) a first number indicative of a time length, and a second number indicative of a point in time, generating a switching signal (S) comprising a switching pulse having a pulse length according to the time length and a pulse position according to the point in time, and providing the switching signal to the switching element (SW). The invention further refers to a power amplifier and to a corresponding computer program.

Pulse width or pulse length modulation (PLM), is a commonly used technique for controlling power to electrical devices. The average value of a voltage (or current) fed to a load is controlled by turning the switch between supply and load on and off at a fast pace. The longer the switch is on compared to the off periods, the higher is the power supplied to the load.
An increasing need to improve an efficiency of power amplification regarding power consumption has brought the concept of pulse length modulation (PLM) into focus using e.g. so-called switched mode Class-S power amplifiers (PA), especially in the field of mobile communication. In this approach, power transistors inside the PA are driven by rectangular pulses at the carrier frequency. The on and off times are controlled by a digital signal, wherein a certain duration of an off time might be represented by a certain number of consecutive "0" (or "low") bits, and a certain duration of an on-time might be represented by a certain number of consecutive "1" (or "high") bits, or vice versa.
The rectangular pulses e.g. driving a transistor of the power amplifier switches might be generated by means of a shift register containing the consecutive number of "1" bits where the number of these bits relates to a pulse length (or an amplitude), and their position within the register is related to a delay or phase within the carrier period.
Due to an increasing requirement with respect to the switching rate, e.g. currently about 10 GHz, transferring the switching information (PLM sequences) from the processing or controlling circuit to the power amplifier circuit requires a high demand with respect to transmission resources. E.g. for transmitting a ternary switching signal from a mobile terminal base band (BB) circuit (ASIC or the FPGA) to a switched power amplifier circuit at a data transfer rate of 2×10 Gbit/s, two high-speed (gigabit) digital data lines are required, resulting in high requirements to the transmitter, to the receiver logic and to the board layout e.g. with respect to noise suppression. Alternatively, a number of parallel signal lines at corresponding lower data rates could be applied instead, but such parallel transmission would require augmented resources e.g. with respect to space (due to a corresponding number of pins in both circuits and wires on the printed circuit board).

Transmission of pulse length modulation information


A system and method for controlling particular communication capabilities of an electronic device located within an electronic communication room (ECR) includes spreading a physical layer of a communication protocol across various (e.g. two) physical communication channels in a coordinated manner. Each physical communication channel is invoked to transmit a different portion of the control signals required for ECR admission. The electronic device is allowed particular communication capabilities if all ECR control signals from all involved physical communication channels are brought together at the device. If an expected control signal from one of the physical communication channels is missing, the particular communication capability fails.

There are often situations when it is desirable to control particular electronic communication to and/or from devices used by people who are present at a discrete (small) location, such as a room or building. The discrete location is hereinafter referred to as an electronic communication room (ECR), and the people within the location who are participating in the electronic communication, are referred to as ECR visitors.
The electronic communication within the ECR may be wireless radio communication or wireline electronic communication. For mobile devices that utilize public wireless networks such as 2G, 3G or 4G, wireless reception by those devices is generally not confined to a given (small) location. Local radio communication such as WiFi is also usually not confined to the given (small) location. For example it is very common for an electronic device to be able to connect to other open local wireless networks in the neighborhood.
One approach used to control electronic communication by a device is to use short-range radio communication such as Near Field Communication (NFC), Bluetooth, or WiFi. These are all radio protocols with protocol-dependent range, and the corresponding geographic area is just defined by the given range. These protocols do not address a situation where the geographic area in which particular electronic communication is to be allowed, is defined by a spatial structure, such as, for example, a room in a building. For example, although access to a local WiFi may be controlled by security mechanisms and explicit registration of authorized users, once registered, the users are able to connect as long as the device is capable of receiving the transmitted radio signals. The range of such reception often transcends the boundaries of a room or other designated space.
One way to control communication of an electronic device while within an ECR is to give the ECR visitors instructions to manually control the electronic device to have certain communication capabilities. For example, ECR visitors may be asked to manually re-configure their electronic communication devices to prevent particular communication of the electronic devices (e.g. manually silencing their phones so that no calls are attended to). ECR visitors may also be provided with a password or URL, and asked to manually type in the password or URL in order to access confidential data. This control mechanism, however, does not control electronic communication once the ECR visitor leaves the ECR location. That is, electronic communication may remain enabled even after leaving the ECR location.
Another option may be to disable radio communication outside of a given location using technologies such as, for example, a Faraday cage/shield. This solution, however, is expensive and has many barriers towards implementation.
Accordingly, what is desired is a system and method for controlling particular communication capabilities of electronic devices within an ECR location, where the ECR may be set up as a permanent or temporary ECR, and may be defined by any spatial boundaries such as a room or building.

System and method for communication spread across multiple physical layer channels

Genesys Telecommunications Laboratories, Inc.


A radio frequency ID tag, very small in size and with an onboard antenna, is manufactured, tested and applied cost-efficiently. The transmit frequency for the tag is set during manufacture approximately, within a selected range, in a gross tuning step. A second tuning step fine tunes each tag by RF communication to set values of capacitance, resistance, etc., and this can be at the point of application of the tags. Other aspects include burning a randomly-selected value in the RF ID chip during manufacture to impose a random time delay for tag response (rather than having a random generator on the chip itself); structural testing of a large number of tags on a wafer using on-wafer interconnects and a special onboard sequencer test die; and production of the tag so as to be tunable to different frequency ranges.

This invention concerns radio frequency identification tags to be used as identifiers and for counting and inventorying articles and containers of articles. In particular, the invention concerns a miniature RF ID tag generally of the type disclosed in U.S. Pat. No. 6,480,699, which is incorporated herein by reference.
Radio frequency ID tags have been described in various forms, and designed for various purposes. The type of ID tag to which this invention is concerned essentially comprises an integrated circuit with an antenna onboard the chip, and with an energy store which will capture a portion of the RF energy from an interrogator unit, store that energy and use it to power a responding signal transmitted from the tag, as in U.S. Pat. No. 6,480,699.
Currently, in the manufacture of semiconductor devices (for a variety of different purposes, not only ID tags) dice are tested by connecting each die individually with a tester. This typically occurs while the dice are still on the wafer and also after each die has been cut from the wafer and assembled, and it is a costly procedure.
In addition, present semiconductor devices typically are pre-tuned by automatic testing equipment (ATE) during a manufacturing test. Such devices are often tested/tuned numerous times in both the wafer stage (before packaging) and in a final test (wherein the device is packaged). To eliminate any high variation in the manufactured devices, a fairly expensive process with narrow tolerances is required for the initial tuning. Most fine tuning of semiconductor devices cannot make adjustments over a wide enough range to overcome the initial production offset, unless ATE type pre-tuning has been performed. There is a need for a less expensive regime for tuning of semiconductor devices to target values, particularly in the production of RF ID tags. ATE type testing is expensive and its avoidance is an object of the invention. It would be desirable to perform as much testing of RF ID tags as possible at the time of application of the tags, rather than during manufacturing, although an efficient parallel test for manufacturing defects would also be desirable at the time of manufacture.
In RF ID tags, of the type described in U.S. Pat. No. 6,480,699 wherein an onboard power supply stores energy from an interrogating signal, the responsive tag transmission in many applications must occur in a specific time slot which is distinct from the transmit time slots of all other tags similarly situated. This is needed for collision avoidance, that is, simultaneous responsive transmissions from multiple tags. This is true for applications in which a large number of items are to be detected, counted, tracked and/or identified, since the reader needs to detect or count or track or identify every individual item. U.S. Pat. No. 6,480,699 described a method to reduce data transmission collisions from RF ID tags by having each tag select a random time slot. This would require each of the tags to have an onboard random number generator as well as supporting digital circuitry to calculate the random time slot in which to transmit. It would further economize the production of semiconductor RF ID tags to eliminate the need for such onboard random number generators and supporting circuitry, by imposing a random time slot on each tag in a different way.
Different nations of the world have different regulations regarding frequency bands for radio frequency devices. This requires RF ID tags to be tuned differently for different jurisdictions. It would be efficient and highly desirable to be able to produce a single form of tag which is tunable to an appropriate frequency for the requirements of all applicable jurisdictions. In addition, even within a single jurisdiction, different frequencies are often needed for different applications, within the same facility, for reasons relating to interference and false readings for different products or applications. A tunable tag, tunable by the user at time of application, would allow for the production and inventorying of only one type of tag, again saving cost and increasing efficiency.
The following U.S. patents have relevance to the invention described below: U.S. Pat. Nos. 6,480,699 and 6,825,683.
It is among the objects of the invention to address the needs described above. These and other objects, advantages and features of the invention will be apparent from the following description of preferred embodiments, considered along with the accompanying drawings.


A modular post system, in some versions, includes an exterior post extending along a central axis. The exterior post may be composed of multitude of tube segments that are coupled, with each other to form the exterior post. In some cases, each tube segment may have at least four holes arranged in a ring about the central axis. The holes are configured to allow the mounting of articles, such as playground equipment, to the post system. Thus, the exterior post may have a multitude of rings with the rings being located in axial planes a fixed distance apart along the central axis. The tube segments have interior surfaces from which ribs protrude, to define an internal channel of the exterior post. An internal core post may be partly located within the internal channel. A fastening mechanism may secure the coupled tube segments to the internal core post.

Posts are often used to attach articles to. For example, a playground may have several posts to which various types of playground equipment are attached. This playground equipment may include decks, slides, climbers, traverses, monkey bars, and other equipment. Attaching articles to posts sometimes includes challenges. For example, it may be necessary to drill holes in a post for purposes of attaching an article. Also, some articles must be attached to two or more posts, preferably at the same elevation. Careful measuring when drilling holes may be necessary to assure that the article is mounted to the posts at the same elevation.
Some posts may come from the manufacturer with pre-drilled holes. But when designing a post with pre-drilled holes, various design considerations may present themselves.
One possible design consideration is optimizing the placement of holes at a given elevation on a post. That is, one design consideration is how many pre-drilled holes to provide a user at a given elevation on the post.
Another possible design consideration may be how holes at various elevations on a post are organized for ease of use by a user.
Another possible design consideration is whether a post requires assembly and how difficult that assembly is.
Yet another possible design consideration may be the structure of a post and how strong it is.

Modular post system with holes on multiple axial planes


A light-emitting device includes a light-emitting element, a phosphor layer containing a phosphor that is excited by the light emitted by the light-emitting element to emit fluorescence, a substrate with the light-emitting element and the phosphor layer on the surface, and a resin body that seals the light-emitting element and the phosphor layer. An additional member is provided on an opposite surface opposed to the light-emitting surface of the light-emitting element on the surface of the resin body. The additional member at least reflects or diffuses the light emitted by the light-emitting element and the phosphor layer.

A light-emitting device provided with a light-emitting element such as a light-emitting diode as a light source is utilized, for example, in a backlight of a liquid crystal display or the like. In the lighting device that is required to planarly irradiate light without unevenness in luminance, like a backlight, it is preferred if a light-emitting device that controls distribution characteristics by expanding the light emitted by the light-emitting element and emitting the light outward is utilized.
Examples of the light-emitting device described above are disclosed in Patent Documents 1 and 2. The structure of this light-emitting device will be described with reference to FIG. 14. FIG. 14 is a top view and cross-sectional view showing a schematic structure of a conventional light-emitting device. FIG. 14A is a top view, and FIG. 14B is a cross-sectional view showing an X-X cross section in FIG. 14A. Here, electrodes, wiring and the like are omitted in FIG. 14, for simplification of illustration.
As shown in FIG. 14, a light-emitting device 100 comprises a substrate 101 and a light-emitting element 102 provided on the surface of the substrate 101, and a resin body 103 that seals the light-emitting element. An opposite surface 103a that is opposed to a light-emitting surface (surface on the side opposite to the substrate 101) of the light-emitting element 102 in the resin body 103 is a depressed surface that is concavely depressed. Also, the depressed surface is an inclined surface of an inverted cone. Furthermore, the outer shape of the depressed surface of the resin body 103 is curved convex upward in the cross section that is perpendicular to the surface of the substrate and cut so as to pass through the center of the light-emitting surface of a light source (light-emitting element 102). In the light-emitting device 100, a part of the light emitted by the light-emitting element 102 is totally reflected on this depressed surface to return into the resin body 103, thereby expanding the light emitted by the light-emitting element 102 and emitting the light outward. As described above, since it is not necessary to separately provide a member that controls light distribution characteristics such as a lens, it is possible to reduce the number of the components of the light-emitting device 100.

Light-emitting device, lighting device, display device, and method for manufacturing light-emitting device


Two NMOS transistors and two PMOS transistors are provided on a substrate. Power supply lines VDD and VSS connected to the transistors are provided in the second wiring layer. A metal line is provided in the third wiring layer, which is the uppermost wiring layer, and the pad is connected to the metal line. Even when the width of the metal line is increased so as to increase the acceptable current capacity thereof, it is possible to keep the wiring area ratio of the first wiring layer in the I/O region at a low level. Thus, it is possible to suppress the global step between the I/O region and the central region of the chip.

The present invention relates to a semiconductor device having pads. More particularly, the present invention relates to a semiconductor device in which a global step between an I/O region along the periphery of a chip and a central region of the chip is reduced even when the width of a metal line connected to a pad is increased.
In recent years, the degree of integration of a semiconductor integrated circuit has been increasing along with the advancement of minute processing techniques. A multilayer wiring structure is typically employed in an integrated circuit that is fabricated with a 0.25 xcexcm, or subsequent, design rule. Along with the miniaturization of devices, the thickness of each wiring film and interlayer insulating film in the multilayer wiring structure has been reduced. The reduction in the thickness of each wiring film also reduces the acceptable current density thereof.
A semiconductor integrated circuit typically includes I/O cells arranged along the periphery of the chip. An I/O cell includes a protection circuit for protecting the integrated circuit from an electrostatic discharge (ESD) and an input/output circuit. The width of each I/O cell has been reduced along with a reduction in the pad pitch due to an increase in the number of pins provided in an integrated circuit. Under such circumstances, for example, the acceptable current capacity of a metal line connected to the pad of an I/O cell, through which a large current is expected to flow, is increased by increasing the width thereof as much as possible, or providing the metal line in multiple layers, so as to increase the reliability thereof against possible wire breaking due to a current flow therethrough.
FIG. 8 illustrates a layout of a conventional semiconductor integrated circuit. More specifically, FIG. 8 illustrates an I/O cell having a three-layer wiring structure. The I/O cell includes ESD protection elements, output transistors, power supply lines and a pad. The output transistors all have the same structure, and also function as the ESD protection elements. Therefore, the term xe2x80x9coutput transistorsxe2x80x9d as used herein refers to both output transistors and ESD protection elements.
FIG. 9 is a cross-sectional view taken along line 101 of FIG. 8, and FIG. 10 is a circuit diagram illustrating the semiconductor integrated circuit of FIG. 8. A gate insulating film and an interlayer insulating film for providing an insulation between wiring layers are not shown in FIG. 8 and FIG. 9.
In FIG. 8 and FIG. 9, 102 denotes a p-type semiconductor substrate, and 103 and 104 respectively denote a p-type well and an n-type well, which are provided on the semiconductor substrate 102. Two NMOS transistors N101 are provided on the p-type well 103, and two PMOS transistors P101 are provided on the n-type well 104. The transistors N101 and P101 function as output transistors, and are separated from each other by a device separation region 105. In FIG. 8 and FIG. 9, 106 and 107 denote n-type diffusion regions, which respectively serve as the drain and the source of the NMOS transistors N101, and 108 and 109 denote p-type diffusion regions, which respectively serve as the drain and the source of the PMOS transistors P101.
Moreover, in FIG. 8 and FIG. 9, VSS denotes a power supply line at a ground potential which is provided in the second wiring layer, and VDD denotes a power supply line at a predetermined potential which is also provided in the second wiring layer. The power supply line VSS is connected to the n-type diffusion region 107, serving as the source of the NMOS transistors N101, via a via hole 110, an isolated wiring region 111 which is provided in the first wiring layer, and a via hole 112 (note that the two via holes 110 and 112 appear to be a single hole in FIG. 8 because they overlap each other in the vertical direction). The power supply line VDD is connected to the p-type diffusion region 109, serving as the source of the PMOS transistors P101, via a via hole 113, an isolated wiring region 114 which is provided in the first wiring layer, and a via hole 115 (note that the two via holes 113 and 115 appear to be a single hole in FIG. 8 because they overlap each other in the vertical direction).
Moreover, 122 denotes a pad, and 116 denotes a metal line having a large width which is provided in the first wiring layer. The metal line 116 is used to connect the output transistors N101 and P101 to the pad 122. The metal line 116 is connected to the n-type diffusion region 106, serving as the drain of the NMOS transistors N101, via a via hole 117, and to the p-type diffusion region 108, serving as the drain of the PMOS transistors P101, via a via hole 118. Furthermore, the metal line 116 is connected to the pad 122 via a via hole 119, an isolated wiring region 120 which is provided in the second wiring layer, and a via hole 121 (note that the two via holes 119 and 121 appear to be a single hole in FIG. 8 because they overlap each other in the vertical direction).
However, with the conventional I/O cell illustrated in FIG. 8 and FIG. 9, when the width of the metal line 116 is increased in order to increase the acceptable current capacity thereof, the parasitic capacitance between the metal line 116 in the first wiring layer and the power supply lines VSS and VDD in the second wiring layer may increase, thereby also increasing the delay time.
Moreover, when the width of the metal line 116 in the first wiring layer is increased in an I/O region along the periphery of the chip, the wiring area ratio of the first wiring layer in the I/O region (i.e., the ratio of the total area of wiring within a unit area, e.g., 100 xcexcmxc3x97100 xcexcm, with respect to the unit area) increases with respect to the wiring area ratio of the first wiring layer in the central region of the chip. The difference between the wiring area ratio of the first wiring layer in the I/O region and that in the central region of the chip may cause a physical step or unevenness (hereinafter, referred to simply as a xe2x80x9cstepxe2x80x9d) on the surface, even if the interlayer insulating film deposited on the first wiring layer is flattened through a CMP process (a chemical mechanical polishing process for increasing the flatness of a surface). The step increases as the difference in the wiring area ratio of the first wiring layer increases. Moreover, the step which is caused by the difference in the wiring area ratio of the first wiring layer and remaining after the CMP process will not be significantly reduced even after a CMP process that is performed in preparation for the formation of lines in the third wiring layer. The steps occurring in the respective wiring layers accumulate to cause a so-called xe2x80x9cglobal stepxe2x80x9d on the surface of the chip. Therefore, when the metal line 116 is provided as a multilayer line by using two or more wiring layers in order to further increase the acceptable current capacity, the global step between the I/O region and the central region of the chip increases. Typically, a plurality of chips are fabricated in a regular arrangement on a single wafer, and the I/O region of one chip adjoins the I/O region of another adjacent chip on the wafer. FIG. 11 illustrates an arrangement of a plurality of chips on a wafer. In FIG. 11, 150 denotes a wafer, and a plurality of chips 151 are arranged on the wafer 150. Each chip 151 includes an I/O region 152 surrounding a central region 153 of the chip. When fabricating such chips 151 each having the central region 153 surrounded by the I/O region 152, as illustrated in FIG. 11, the I/O region 152 of one chip on the wafer 150 adjoins that of another adjacent chip. Therefore, when the wiring area ratio in the I/O region 152 is significantly larger than that in the central region 153, a large area defined by two I/O regions 152 adjoining each other will have a large wiring area ratio on the wafer 150. As a result, a sufficient flatness cannot be ensured across a large area on the chip even by the CMP process, thereby causing a substantial global step on the chip surface. Then, it is difficult to ensure a desirable exposure margin in the lithography process.
Where a so-called xe2x80x9cPOE (PAD on Element)xe2x80x9d structure, in which the pad is located above an element such as an output transistor, is employed, a parasitic capacitance occurs between the pad and the power supply lines. Specifically, referring to FIG. 12 illustrating a cross-sectional view of an I/O cell having a POE structure, the pad 122 is located above the two power supply lines VDD and VSS, thereby causing a parasitic capacitance between the pad 122 and the power supply lines VDD and VSS, which causes an increase in the delay time.
An object of the present invention is to reduce the global step while increasing the acceptable current amount by increasing the width of the metal line connected to the pad, even when the width of the I/O cell is reduced. In addition, another object of the present invention is to suppress the parasitic capacitance occurring between the metal line connected to the pad and the power supply lines connected to the output transistors.
In order to achieved these objects, in the present invention, the metal line connected to the pad is provided in an upper wiring layer that is higher in position than a lower wiring layer in which the power supply lines connected to the output transistors are provided so that the wiring area ratio of the lower wiring layer is lower than that of the upper wiring layer, thereby effectively suppressing the occurrence of the global difference.
Specifically, a semiconductor device of the present invention includes: a plurality of wiring layers; an output transistor provided on a substrate; a power supply line provided in a predetermined one of the wiring layers for supplying a power to the output transistor; a pad for connecting an output of the output transistor to an external unit; and a metal line for connecting the output transistor to the pad, wherein: the metal line is provided in one of the wiring layers that is higher in position than another one of the wiring layers in which the power supply line is provided; and a wiring area ratio of the other wiring layer which is provided under the wiring layer in which the power supply line is provided is less than a wiring area ratio of the wiring layer in which the power supply line is provided.
In one embodiment, the plurality of wiring layers include three or more wiring layers; and the metal line for connecting the output transistor to the pad is provided in an uppermost one of the wiring layers.
In one embodiment, the output transistor includes a first-conductivity-type transistor and a second-conductivity-type transistor; the first-conductivity-type transistor includes a first-conductivity-type diffusion region which is connected to the metal line; the second-conductivity-type transistor includes a second-conductivity-type diffusion region which is connected to the metal line; and the predetermined one of the wiring layers includes a vacant region where the power supply line is not present, the vacant region existing above the first- and second-conductivity-type diffusion regions which are connected to the metal line.
In one embodiment, the first- and second-conductivity-type transistors are provided so that a longitudinal direction thereof is parallel to a width direction of the pad.
In one embodiment, the power supply line is provided so as to extend in parallel to the longitudinal direction of the first- and second-conductivity-type transistors.
In one embodiment, a via hole of a stacked via structure is provided so as to extend from each of the first- and second-conductivity-type diffusion regions to the vacant region in the predetermined one of the wiring layers, the via hole extending between the predetermined one of the wiring layers in which the power supply line is provided and the first- and second-conductivity-type diffusion regions of the first- and second-conductivity-type transistors which are connected to the metal line.
In one embodiment, a part of the metal line provided in the uppermost one of the wiring layers is used as the pad.
In one embodiment, the pad is located above the output transistor.
In one embodiment, the metal line is provided in two or more of the wiring layers that adjoin one another in a vertical direction.
As described above, in the present invention, the wide metal line having a large acceptable current capacity which is connected to the pad is provided in an upper wiring layer that is higher in position than a lower wiring layer in which the power supply lines are provided. Therefore, as compared to the case where the metal line is provided in a wiring layer that is lower in position than the wiring layer in which the power supply lines are provided, the wiring area ratio of the lower wiring layer is reduced. Therefore, the difference between the wiring area ratio of the lower wiring layer in the I/O region including the pad and that in the central region of the chip is suppressed, thereby suppressing the occurrence of the global step.
Moreover, in the present invention, the metal line connected to the pad may be provided in the uppermost wiring layer. Typically, the thickness of an insulating film provided between adjacent wiring layers is greater than another insulating film that is lower in position than the insulating film. Therefore, when the metal line is provided in an upper wiring layer, particularly the uppermost wiring layer, the spacing between the metal line and the power supply lines is increased, thereby suppressing the parasitic capacitance occurring between the metal line and the power supply lines.
Moreover, in the present invention, a predetermined wiring layer in which the power supply lines are provided includes a vacant region, where no power supply line is present. Therefore, an output transistor can be connected to the metal line, which is connected to the pad, via a straight vertical path extending through the vacant region, thereby simplifying the structure of the connecting path.
In addition, in the present invention, a so-called xe2x80x9cstacked viaxe2x80x9d structure, including a plurality of via holes that are stacked on one another and substantially aligned with one another in the vertical direction, is employed for connecting the output transistor to the metal line, which is connected to the pad. A line in the stacked via structure can be provided so as to extend only around the via holes without having to take into consideration the acceptable current capacity thereof. Therefore, the wiring area ratio of the lower wiring layer is reduced, thereby further suppressing the global step between the I/O region and the central region of the chip.
Moreover, in the present invention, a part of the metal line in the uppermost wiring layer may be used as the pad. Therefore, it is possible to suppress the parasitic capacitance occurring between the metal line and the pad while eliminating the need for a line for connecting the metal line to the pad.
Furthermore, in the present invention, when the POE structure in which the pad is located above the output transistors is employed, any part of the metal line may be used as the pad, thereby increasing the freedom in the location of the pad.
In addition, in the present invention, the metal line connected to the pad may be provided across a large area in the form of a multilayer line. Therefore, when employing an area pad structure in which the pad is located in the central region of the chip, the connection to the pad can be made only by extending an end portion of the metal line facing the central region of the chip toward the area pad, whereby it is possible to reduce the length of the extension of the metal line to the area pad.

Matsushita Electric Industrial Co., Ltd.


In a regenerator for a regenerative cycle machine, regenerator foil is grooved on both sides, with intersections of grooves on opposite side forming holes at which separate flows of fluid interact to induce flows ancillary to the overall direction of flow in the regenerator, thereby enhancing heat transfer to and from the material of the regenerator and improving thermodynamic performance of the gas cycle machine.

1. Field of Invention
This invention relates to foil for regenerators of regenerative gas cycle machinery.
2. Description of Prior Art
Regenerative gas cycle machines are a class of machinery that includes Stirling cycle engines and Stirling cycle, Gifford-McMahon, Vuilleumier, Solvay and pulse tube refrigerators. A regenerator is a critical component of all regenerative gas-cycle machines. The regenerator acts as a thermal sponge. Fluid passing back and forth through the regenerator leaves heat in the regenerator matrix in one direction of flow and picks up that heat as it passes back through the regenerator in the opposite direction.
Stacks of wire-mesh screens, wire felt materials, and beds of packed metal powder have been widely used as regenerators in gas cycle machinery because the materials are primarily used for other purposes, are produced in quantity, and are readily available in the marketplace. However, none of those materials is specifically designed to fulfill the special function of a regenerator. Regenerators fabricated from those materials all contain random fluid flow passages in the spaces between wires or grains of powder. The flow passages are of varying width, and a significant portion of the void volume in those regenerator is in spaces in which there is little or no fluid flow and thus little opportunity for heat transfer between the fluid and the regenerator matrix material. One advantage of those prior art materials was that the regenerator permitted lateral flows as well as flows in the overall direction of flow in the regenerator. That permitted imbalances in flow at different points in each cross section of the regenerator to be equalized by natural cross-flows. However, these materials contain no means for dynamically redistributing fluid laterally relative to the overall direction of flow in the regenerator.
Spaced layers of foil have also been used as the matrix material in regenerators in gas cycle machinery. Sheets of foil can be etched to create grooves on the surface of the foil. Foil can also be shaped by crimping or dimpling it, which avoids the loss of material in the etching process, but those techniques have not been sufficiently precise to produce acceptable regenerators. Moreover, solid layers of foil prevent cross-flows necessary to rebalance overall flow distribution over a cross section of the regenerator as fluid moves through it.
Etched foil regenerators used heretofore have partially solved the problem of flow passage width; if the foil is prepared carefully, flow passages are close to the same width throughout the regenerator. Perforations in etched foil have also permitted cross-flows, as in screen, felt and packed powder regenerators. In practice, performance of prior art foil regenerators has generally been disappointing.
Laboratory work with prior art foil regenerators shows that they offer lower pressure drop than felted material, stacked screens or packed powder, the standard regenerator materials. Computer models suggest that prior art foil regenerators should also provide good heat transfer, and, overall, superior performance.
Disappointing performance of prior art foil regenerators is due in part to inadequate heat transfer between the fluid and the foil. When fluid passes straight through the regenerator from one end to the other, the time that the fluid spends in transit is minimized, limiting the time during which heat transfer can take place. Moreover, boundary layers develop as fluid flows through the regenerator, impeding heat transfer.


Disclosed herein is a method for preparing a multilayer metal complex having excellent surface properties. Specifically, the present invention relates to a method for preparing a multilayer metal complex having a low cost metal-core/noble metal-shell structure, which has a high mass fraction of noble metals and exhibits excellent surface properties and dispersity.

1. Technical Field
The present invention relates to a method for preparing a multilayer metal complex having excellent surface properties. More particularly, the present invention relates to a method for preparing a multilayer metal complex having a low cost metal-core/noble metal-shell structure, which has a high mass fraction of noble metals, and exhibits excellent surface properties and dispersity.
2. Description of the Related Art
Metal complexes having a low cost metal-core/noble metal-shell structure capable of being used as low cost conductive pastes and electromagnetic shielding substances are known in the art and exhibit excellent conductivity to provide high reliability when applied to products.
For metal complexes used in such purposes, it is important that noble metals forming a shell structure are uniformly and sufficiently adhered to a surface of a low cost metal, thereby secure a sufficient thickness.
Complexes of a copper core/silver shell structure are widely used in the art. Conventionally, a copper-silver complex is prepared by a liquid phase reduction method. All processes of the liquid phase reduction method are carried out in liquid phase. However, this method has problems in that aggregation can easily occur due to interfacial effects between a solid phase and a liquid phase and an excess of reducing agents, and separation of silver particles also occurs, thereby making it difficult to obtain a complex with a uniform surface. In addition, when a large amount of silver ions is introduced in order to increase silver content, the silver ions are uniformly dispersed on the surface of copper, making it difficult to obtain a thin silver layer, and voids are generated inside the complex due to active melting of copper.
Therefore, there is a need for a method for preparing a novel metal complex through controlled process conditions so as to solve the above problems and provide excellent surface properties.

Method for preparing multilayer metal complex having excellent surface properties


A catheter for cardiac procedures includes a generally C-shaped distal end which roughly conforms to the shape of an aortic arch. The catheter is made of a flexible material and includes a distal portion having a proximal section connected to an intermediate section at approximately 135 degrees. The distal most section attached to the intermediate section is generally perpendicular to the intermediate section and consists of a double or reverse curve. The structure allows the catheter to be utilized to enter either left or right ostia without catheter exchange by rotation of the catheter around its axis.

A. Field of the Invention PA1 B. Problems in the Art
The present invention relates to catheters, and in particular, to catheters utilized in investigative and therapeutic procedures with respect to the main coronary arteries of the heart.
The procedures involved with cardiac catheterization are well known in the art. Cardiac catheterization generally is used to investigate the condition of the main coronary arteries. The usual procedure is to utilize a long narrow flexible tubular catheter inserted into an artery either in the groin area or in the patient's arm. The catheter is moved up the artery and into the coronary arteries near the heart to inject x-ray dye (contrast media) into the coronary arteries to allow cardiologists to diagnose the existence or severity of coronary artery disease. Catheters can also be used as the conduits for guide wires for such things as dilatation balloons used in angioplasty. Other uses are possible.
The coronary arteries branch out from what is called the aortic arch. What are called ostia are the openings between the aortic arch and the left and right main coronary arteries. It is generally advantageous, and sometimes necessary, to be able to enter the ostia for these procedures.
One problem that exists with cardiac catheterization is that there are different sizes and shapes of aortic arches and different locations and distances between the aortic arch and the ostia for access to the coronary arteries. Therefore, the conventional solution in the art is to have available a number of differently sized and shaped catheters to allow the doctor to select essentially what is believed to be the best fit for a particular patient and organ configuration.
Different types of catheters are used or are preferred for different types of cardiac procedures. Furthermore, certain materials may be preferred for the catheters. Certain catheters are desired to be made of a more flexible material to allow more deformation, and therefore more flexibility as far as maneuvering and positioning the distal end of the catheter. On the other hand, more rigid, less flexible materials are desired by some to allow easier insertion through the long distance to the aortic arch. However, the less flexible materials are more difficult to conform to curves and bends, and run the risk of damage to the arteries or complications because of the nature of the material.
As can be appreciated, cardiac catheterization is not a trivial procedure. It requires the cardiologist to introduce the distal end of the catheter in an artery in the patient's limb (arm or leg) and then basically push the catheter up the artery to the aortic arch. Because of the limited ability to manipulate the tip once in the artery, the tip usually must have some sort of inherent configuration that would allow it to enter at least one coronary artery by simply pushing on the proximal but remotely located end. The inherent nature of the ostia into the coronary arteries is such that a straight ended catheter, while being fairly effective inserted through the limb arteries, does not function to effectively traverse the aortic arch and to enter the ostia.
No single catheter is known which allows easy and safe access to both ostia. Therefore, the state of the art is such that when investigation of one coronary artery is completed, the catheter has to be completely removed. A second catheter of a different shape is then inserted to investigate the second coronary artery. This is called catheter exchange. This greatly adds to the time, effort, and difficulty of these procedures, including risk associated with any such procedure.
It is therefore a principle object of the present invention to offer an improvement with respect to the problems, deficiencies, and needs in the art.
It is another object of the present invention to provide a cardiac catheter which can be used for both diagnostic and therapeutic cardiac procedures.
A further object of the present invention is to provide a cardiac catheter which can access both coronary ostia, including those with anatomically varied locations.
Another object of the present invention is to provide a cardiac catheter which may avoid the need for catheter exchange to access both ostia.
A still further object of the present invention is to provide a cardiac catheter which is stable in the sense that it can be inserted into a patient's limb artery and safely and efficiently moved to a location at or near the coronary ostia, and safely and effectively manipulated into the coronary ostia.
Another object of the present invention is to provide a catheter which is flexible enough to be manipulated as needed, and is safer than more inflexible designs.
These and other objects, features and advantages of the present invention will become more apparent with reference to the accompanying specification and claims.


A battery capable of improving cycle characteristics is provided. An anode active material layer is formed by a vapor phase method, and includes Si as an element. In the anode active material layer, a plurality of primary particles formed by growth in a thickness direction are included, and the plurality of primary particles are agglomerated to form a plurality of secondary particles. Each secondary particle is separated by a groove formed by charge and discharge, and some of primary particles are split particles split by the groove. The average number of the split particles per secondary particle in 5 or more adjacent secondary particles is 10 or more. Moreover, the primary particles and the secondary particles are inclined to the same side.

The present invention relates to a battery including an anode active material layer which includes silicon (Si) as an element, and a method of manufacturing the battery.
In recent years, as mobile devices have become more sophisticated and multifunctional, a demand for an increase in the capacity of secondary batteries as power sources for the mobile devices has been made. As a secondary battery which meets the demand, a lithium secondary battery is cited. However, in a currently typical lithium secondary battery which uses lithium cobalt oxide for a cathode and graphite for an anode, its battery capacity has reached the saturation point, so it is extremely difficult to significantly increase its capacity. Therefore, using metal lithium (Li) for an anode has been considered since a long time ago; however, in order to put the anode to practical use, it is necessary to improve lithium precipitation/dissolution efficiency and control dendritic evaporation.
On the other hand, in recent times, a study of an anode with high capacity which uses silicon, tin (Sn) or the like has been conducted vigorously. However, when charge and discharge are repeated, the anode with high capacity is broken into small pieces due to severe expansion and shrinkage of an active material, thereby a current collecting property declines, and the decomposition of an electrolyte solution is accelerated due to an increase in a surface area, so cycle characteristics are extremely poor. Therefore, an anode formed through forming an active material layer on a current collector by a vapor phase method, a liquid phase method, a firing method or the like has been studied (for example, refer to Japanese Unexamined Patent Application Publication No. H8-50922, Japanese Patent No. 2948205 and Japanese Unexamined Patent Application Publication No. H11-135115). The anode can be prevented from being broken into small pieces, compared to a coating type anode formed through applying slurry including a particulate active material, a binder and the like in a related art, and in the anode, a current collector and an active material layer can be formed as one unit. Therefore, the electronic conductivity in the anode is excellent, and higher performance in terms of capacity and cycle lifespan is expected. Moreover, an electrical conductor, a binder and voids which are present in an anode in a related art can be reduced or eliminated, so the anode can be formed into a thin film in essence. Further, it has been reported that the surface of the anode current collector is roughened so as to form microscopic asperities on the surface of the anode active material, thereby excellent characteristics can be obtained (for example, refer to Japanese Unexamined Patent Application Publication No. 2002-83594, S. Fujitani, H. Yagi, K. Sayama, T. Yoshida, H. Tarui, Sanyo Electric Co., Ltd., "The Electrochemical Society 203rd Meeting (Paris, France) Abstract 1152", (New a-Si Alloy Thin Film Anode with Self Organized Micro Columnar Structure), P. 1152, and "Summary of Autumn Meeting of the Electrochemical Society of Japan" 2002, p. 107).
However, in such an anode, for example, as described in S. Fujitani, H. Yagi, K. Sayama, T. Yoshida, H. Tarui, Sanyo Electric Co., Ltd., "The Electrochemical Society 203rd Meeting (Paris, France) Abstract 1152", (New a-Si Alloy Thin Film Anode with Self Organized Micro Columnar Structure), P. 1152, in an anode active material layer, individual primary particles which grow long and thin in a thickness direction repeatedly expands and shrinks by charge and discharge, so in the early stages of cycles, relatively good characteristics can be obtained; however, when the cycles are repeated, the anode active material layer may be damaged or fall off a current collector, thereby the characteristics decline.
Such a phenomenon often occurs in the case where the adhesion between primary particles is poor; however, when the adhesion between primary particles is strong, and thereby secondary particles become too large, the secondary particles may fall off according to charge and discharge, or a current collector may be damaged because it is difficult to release a stress by the expansion and shrinkage of the secondary particles. Therefore, it is difficult to obtain sufficient characteristics.

Battery and method of manufacturing the same


Automated methods and systems for determining and setting router QoS adjustments to control the service level of VoIP voice communications in a packet switching network supporting both voice and data communications. Network topology and service level requirements are processed to determine QoS settings for each of the routers. The QoS settings are transmitted to the routers, for example in the form of a router configuration file, to set the QoS adjustments to achieve the desired VoIP service level. The invention is applicable to packet switching networks comprising routers or equivalent electronic switches providing electronically adjustable QoS settings.

Conventional circuit-switched telephony, known in the art as the public switched telephone network (PSTN), has the well-recognized disadvantage of requiring that a physical communications line be held open throughout an entire conversation between two communicating parties. A complex infrastructure of circuits and switches exists to establish and hold such lines for every PSTN telephone call. Because only a small percentage of the available bandwidth is actually used during each call, the PSTN system is inefficient and the infrastructure costs burdensome.
Newer, packet switching telephony technology integrates telephony with digital network technology. This packet switching technology codes telephony communications into digital packets, transfers the packets using non-dedicated, dynamically established routing between network servers, and decodes the digital packets at the receiving end to recreate the communication. Each packet may take a different path through a network, the connection between the parties being virtual, i.e. a permanent virtual connection (PVC), rather than physical in nature. Because packet switching telephony does not require a dedicated line, it is generally more efficient and cost-effective than PSTN telephony. However, packet switching communications requires complex software controls and communications commands, known as protocols, to establish, use and then close the virtual network connections between parties.
With the establishment of the Internet, the largest high-speed digital communications network in the world, protocols, such as voice over Internet protocols (VoIP), were established to support telephone communications over the Internet. One early set of protocols was known as H.323, a standard created by the International Telecommunications Union (ITU). A more recent set of VoIP protocols comprises Session Initiation Protocol (SIP) developed under the auspices of the Internet Engineering Task Force (IETF). Both H.323 and SIP provide standardized protocols for VoIP telephony, with SIP considered to be somewhat simpler and more flexible than H.323.
As VoIP telephony has become more prevalent, it has concomitantly become necessary for voice to share hardware and software resources in packet switching networks with other types of data. As expected, each of the different data types has it's own service requirements. Voice service, for example, requires relatively low throughput, low delay and low packet loss. In contrast, file transfer protocol (FTP) data, operating under TCP protocols, requires relatively higher throughput but will tolerate longer delays and potentially higher packet loss. For each different service type, service requirements define the minimally acceptable network behavior for that service type. QoS parameters are derived for an Internet protocol (IP) network to meet those service requirements. As will be described in further detail below, QoS can be measured on different networks for different data types. Network operations can be adjusted to meet the QoS requirements for various data types.
For VoIP telephony, voice service standards were established by the ITU and published as ITU-T G114, the standards defined with respect to a variety of parameters including: one-way delay, jitter, throughput (dependent on coding algorithms employed), coding cycle restrictions, packet loss and service availability. In a wide area network (WAN) environment such as a typical enterprise WAN, a permanent virtual circuit is established between the transmission and receiver sources. Enterprise WANs consist of a variety of hardware components, the principal components comprising routers and switches, which are commercially available, programmable network nodes; they are capable of receiving and transmitting data packets, including VoIP data packets, in accordance with appropriate protocols. Routers and switches are programmable by the operator, each of them generally being set up in a manner to optimally handle anticipated network traffic.
Network routers inherently develop queues of data packets, the data packets processed in accordance with the programmed, controllable settings of the routers. These router settings, along with the resultant handling of the data packets, directly affect the service levels of the various data services handled by the routers. Routers are thus provided with adjustable operating parameters, the operating parameters typically set by software. Adjustable router operating parameters typically include parameters that affect QoS and thus directly affect voice and data service levels. Router QoS 'tool chests' enable operators to set these QoS parameters to control the interaction of voice and data in the network. However, adjusting router settings to meet QoS requirements is a complex effort. As noted above, different types of data services have different service requirements. As voice becomes integrated with data through VoIP telephony, QoS parameters must be set so that the service requirements for telephony are met in addition to the service requirements for other data types. Further, many geographically disperse routers handling many different data applications are required to support VoIP, making the configuration of those routers complex and difficult.
Different conceptualizations of and at least partial solutions are known to these problems in the art. For example, U.S. Pat. No. 6,430,154 to Hunt et al. shows methods and systems for supporting multiple application traffic types on networks where elastic and inelastic data are determined and handled differently. U.S. Pat. No. 6,510,219 to Wellard et al. shows an alternate network fallback solution for IP telephony wherein QoS is monitored and, if it falls below a first threshold, a connection over an alternate network is established. If the QoS falls below another predetermined threshold, the call is transferred to the alternate network connection. U.S. Pat. No. 6,515,963 to Bechtolsheim et al. shows a per-flow dynamic buffer management scheme for a data communications device.
There exists in the art a need for managing the service level of VoIP telephony in WANs operating multiple routers distributed over geographically disperse areas and supporting multiple data applications.

Methods and systems for configuring voice over internet protocol network quality of service