A method for designing a digital compensator for a switching mode power supply is provided such that the digital compensator has complex conjugated zero pair or a right hand pole to eliminate the complex conjugated pole pair or right hand zero in the transfer function of the control-to-output voltage of the switching mode power supply.

Switching mode power supplies are widely used in various electronic devices for providing stable voltages; however, non-ideal effects resulted from the switches, inductor and output capacitor in a switching mode power supply may cause the output voltage of the switching mode power supply unstable, and thus a compensator is needed to compensate these non-ideal effects. FIG. 1 shows a conventional switching mode power supply 100, which includes an output stage 102 to convert an input voltage Vi to an output voltage Vo for a load 104, a pre-filter 105 to filter the output voltage Vo to produce a voltage Vo′, an error amplifier 106 to compare the voltage Vo′ with a reference voltage Vref to generate an error signal Ve, a compensator 108 to compensate the error signal Ve to generate a signal Vd, and a pulse width modulator to generate a pulse width modulation (PWM) signal pwm_o according to the signal Vd to drive the output stage 102. In the output stage 102, a driver 112 is used to switch a pair of switches 114 and 116 connected in series between the power input Vi and ground GND according to the PWM signal pwm_o, in order to convert the input voltage Vi to the output voltage Vo.
Generally speaking, the compensator 108 for the switching mode power supply 100 is designed based on the small signal modeling of the switching mode power supply 100. The continuous-time transfer function of each circuit can be derived from the small signal analysis and Laplace transformation as shown in FIG. 2, in which the pre-filter 105 has the transfer function H(s) to transform the output voltage {circumflex over (V)}o(s) into the voltage {circumflex over (V)}o′(s)=H(s)×{circumflex over (V)}o(s), the error amplifier 106 compares the voltage {circumflex over (V)}o′(s) with a reference voltage {circumflex over (V)}ref(s) to generate the error signal {circumflex over (V)}e(s), the compensator 108 has the transfer function Gc(s) to compensate the error signal {circumflex over (V)}e(s) to generate the signal {circumflex over (V)}d(s), the pulse width modulator 110 has the transfer function 1/VM to transform the signal {circumflex over (V)}d(s) into the PWM signal pwm_o(s), and the output stage 102 has the transfer function Gvd(s) of the so-called control-to-output voltage to transform the PWM signal pwm_o(s) into the output voltage {circumflex over (V)}o(s). From the system shown in FIG. 2, the switching mode power supply 100 obviously has the open-loop gainT(s)=Gvd(s)×Gc(s)×H(s)/VM.  [Eq-1]Further, the continuous-time transfer function of the output stage 102 is
                                                                        Gvd                                                  (                  s                  )                                            =                                                V                  ^                                                                                o                                                              (                      s                      )                                                        /                  pwm_o                                                                  (                  s                  )                                                                                =                                                                    (                                          RoRcCs                      +                      Ro                                        )                                                      Vi                                                                                LC                                                                                (                                                              Rc                                +                                Ro                                                            )                                                                                s                            2                                                                          +                                                                                [                                                          L                              +                                                                                (                                                                      RoRc                                    +                                                                          RcR                                      L                                                                        +                                                                          RoR                                      L                                                                                )                                                                                C                                                                                ]                                                                              s                                                +                                                  (                                                                                R                              L                                                        +                            Ro                                                    )                                                                                =                                                (                                                                                b                        1                                                                  s                                        +                                          b                      0                                                        )                                /                                  (                                                                                a                        2                                                                                s                        2                                                              +                                                                  a                        1                                                                  s                                        +                                          a                      0                                                        )                                                                                =                                                      A                                                              [                                                                        (                                                      s                            /                                                          ω                                                              z                                                                                1                                                                                )                                                +                        1                                            ]                                                        /                                      {                                                                  [                                                                              (                                                          s                              /                                                              ω                                                                  p                                                                                1                                                                                )                                                    +                          1                                                ]                                                                                [                                                                              (                                                          s                              /                                                              ω                                                                  p                                                                                2                                                                                )                                                    +                          1                                                ]                                                              }                                                              ,                                                          [                  Eq                                -                              2                ]            where a0, a1, a2, b0, b1 and A are constants, ωp1 and ωp2 are poles, ωz1 is a zero, RL is the equivalent DC resistance of the inductor L, Rc is the equivalent serial resistance of the capacitor C, and Ro is the resistance of the load 104. From the equation Eq-2, it can be obtained the poles
                                          ω                          p                                                                                1                                =                                                                      a                  1                                                  a                  2                                            +                                                                                (                                                                        a                          1                                                                          a                          2                                                                    )                                        2                                    -                                      4                                                                                a                        0                                                                    a                        2                                                                                2                                                                    and                            [                  Eq                                -                                                                        3                ]                                                      ω                          p                                                                                2                                =                                                                      a                  1                                                  a                  2                                            -                                                                                (                                                                        a                          1                                                                          a                          2                                                                    )                                        2                                    -                                      4                                                                                a                        0                                                                    a                        2                                                                                2                          ,                            [                  Eq                                -                              4                ]            the zeroωz1=b0/b1,  [Eq-5]and the constantA=(b0a2)/(a1a0).  [Eq-6]
The compensator 108 is so designed according to the transfer function Gvd(s) of the output stage 102 for the converter 100 to provide a stable output voltage and a fast load transient response. Currently, popular analog compensators include type-I, type-II and type-III, and FIG. 3 shows a typical type-III analog compensator 108 which includes resistors R1, R2, R3, and capacitors C1, C2, C3. From the circuit of FIG. 3, the analog compensator 108 has the continuous-time transfer function
                                                                        Gc                                                  (                  s                  )                                            =                                                                    (                                          1                      +                                              sR                                                                                1                                                                                C                                                                                2                                                              )                                                                          [                                          1                      +                                                                        s                                                                                (                                                                                R                                                                                3                                                            +                                                              R                                                                                1                                                                                )                                                                                C                                                                                3                                                              ]                                                                    sR                                                                                1                                                        (                                          1                      +                                              sC                                                                                3                                                                                R                                                                                3                                                              )                                                                          (                                                                  C                                                                                1                                            +                                              C                                                                                2                                            +                                              sR                                                                                2                                                C                                                                                1                                                C                                                                                2                                                              )                                                                                =                                  Ac                                                                                (                                                  1                          +                                                      s                            /                                                          ω                                                              cz                                                                                1                                                                                )                                                                                (                                                  1                          +                                                      s                            /                                                          ω                                                              cz                                                                                2                                                                                )                                                                                s                                                                          (                                                      1                            +                                                          s                              /                                                              ω                                                                  cp                                                                                1                                                                                )                                                                                (                                                  1                          +                                                      s                            /                                                          ω                                                              cp                                                                                2                                                                                )                                                                                ,                                                          [                  Eq                                -                              7                ]            where Ac is a gain constant, ωcz1 and ωcz2 are zeros, and ωcp1 and ωcp2 are poles. In the equation Eq-7, the poles ωcp1 and ωcp2 are real poles for suppressing high-frequency noises. A good compensator 108 must eliminate the poles in the denominator of the transfer function Gvd(s) of the output stage 102. However, due to the inductor L and the output capacitor C, the transfer function Gvd(s) usually includes complex conjugated pole pair or a right hand zero (RHZ). For example, when
            (                        a          1                          a          2                    )        2    <      4                      a        0                    a        2            in the equations Eq-3 and Eq-4, the poles ωp1 and ωp2 become complex conjugated pole pair. As shown in the equation Eq-7, the poles ωcp1 and ωcp2 of the analog compensator 108 are
            1              C                                                  3                R                                                  3                                    and                                1              R                                                  2                                                  C                                                  1                C                                                  2              ,respectively. Since R2, R3, C1, C2 and C3 are all real, the poles ωp1 and ωp2 are real and thus cannot produce a complex number. As a result, the complex conjugated pole pair in the transfer function Gvd(s) of the output stage 102 will not be eliminated. In other words, the traditional compensator 108 can only eliminate the magnitude term of the complex conjugated pole pair so as to compensate the gain, but cannot compensate the phase angle correctly, which will reduce the bandwidth and the phase margin of the switching mode power supply. In addition, current digital compensators only compensate the magnitude term of the complex conjugated pole pair.
For more information of analog compensators, readers are referred to R. W. Erickon and D. Maksimoric, "Fundamentals of Power Electronics", Kluwer Academic Publisher, 2001. For more information of digital compensators, readers are referred to D. Maksimovic, R. Zane and R. Erickson, "Impact of Digital Control in Power Electronics", Proceeding of 2004 International Symposium on Power Semiconductor Devices & Ics, pp. 13-22, and Shamim Choudhury, "Designing a TMS320F280x Based Digitally Controlled DC-DC Switching Power Supply", Texas Instruments Application Report, SPRAAB3, July, 2005.
For further details, a unit gain single pole system is taken as an example which has the transfer functionI(s)=1/[1+(s/ωp)].  [Eq-8]The equation Eq-8 means that the system has a pole at the angular frequency ωp, and the poleωp=ωp0ejθ=ωp0(cos θ+j sin θ),  [Eq-9]where ωp0 is the magnitude of the pole ωp, and θ is the phase angle of the pole ωp. From the equation Eq-9, when sin θ=0, for example θ=N×180, where N is an integer, ωp is a real pole. When sin θ≠0, ωp is a complex pole. Obviously, even having a same magnitude ωp0, the complex pole ωp will have different frequency response with different phase angles θ. FIGS. 4 and 5 show the frequency response of the unit gain single pole system at different phase angles. In FIG. 4, X-axis represents the frequency, Y-axis represents the gain, curve 200 represents the gain when the phase angle θ of the system is zero, curve 202 represents the gain when the phase angle θ of the system is 45 degrees, curve 204 represents the gain when the phase angle θ of the system is 90 degrees, and curve 206 represent the gain when the phase angle θ of the system is 135 degrees. In FIG. 5, X-axis represents the frequency, Y-axis represents the phase, curve 208 represents the phase when the phase angle θ of the system is zero, curve 210 represents the phase when the phase angle θ of the system is 45 degrees, curve 212 represents the phase when the phase angle θ of the system is 90 degrees, and curve 214 represents the phase when the phase angle θ of the system is 135 degrees. Let ωp0=2π×1000 and θ=0, the unit gain single pole system has the transfer functionI(s)=1/[1+(s/(2π×1000))].  [Eq-10]This means that when the pole is at the frequency 1,000 Hz, as shown by the curve 200 in FIG. 4, the unit gain single pole system is a real pole system. When the frequency is higher than 10 KHz, the phase of the system is close to −90 degrees, as shown by the curve 208 in FIG. 5. However, if the pole ωp has a non-zero phase angle, for example 45 degrees, the transfer function of the system will become
                                                                        I                                                  (                  s                  )                                            =                              1                /                                  [                                      1                    +                                          (                                              s                        /                                                  (                                                      2                                                        π                            ×                            1000                                                                                ⅇ                                                              in                                /                                4                                                                                )                                                                    )                                                        ]                                                                                =                              1                /                                                      [                                          1                      +                                              (                                                  s                          /                                                      (                                                          2                                                            π                              ×                              1000                                                                                (                                                                  0.7071                                  +                                                                      0.7071                                                                                i                                                                                )                                                                                )                                                                          )                                                              ]                                    .                                                                                [                  Eq                                -                              11                ]            From the equation Eq-11, as the system has an imaginary number 2π×1000×0.7071i, the phase of the system is close to −45 degrees when the frequency is over 10 KHz. As shown by the curve 212 in FIG. 5, it is obvious that the phase of the system is close to −45 degrees at high frequencies, but not close to 90 degrees as the situation when the system is at a single real pole. FIGS. 6 and 7 show the difference between a perfect and an imperfect compensated system. In FIG. 6, X-axis represents the frequency, Y-axis represents the gain, curves 200 and 204 are the gain when the phase angle θ is zero and 45 degrees, respectively, curve 220 represents the gain after the pole of the system is perfect compensated, and curve 222 represents the gain after the complex pole is compensated by a real zero. In FIG. 7, X-axis represents the frequency, Y-axis represents the phase, curves 208 and 212 are the phase when the phase angle θ is zero and 45 degrees, respectively, curve 224 represents the phase after the pole of the system is perfect compensated, and curve 226 represents the phase after the complex pole is compensated by a real zero. When the system has a single pole, if there is a compensator C(s) which can provide only one real zero, for example C(s)=(1+s/(2π×1000)), this compensator will compensate a real pole system to have the ideal characteristic of the gain equal to 1 and the phase equal to 0 as indicated by the equation Eq-10, as shown by the curves 220 and 224 in FIGS. 6 and 7. However, when a system having complex conjugated pole pair as the equation Eq-11 indicates is compensated by the compensator C(s), it is obtained
                                          I                                      (              s              )                                ·                      C                                      (              s              )                                      =                                            1              +                              s                                  2                                    π                  ×                  1000                                                                    1              +                              s                                  2                                    π                  ×                  1000                                                                                ⅇ                                          ⅈπ                      4                                                                                .                                    [                  Eq                                -                              12                ]            The frequency response is shown by the curves 222 and 226 in FIGS. 6 and 7, and the system has the non-ideal characteristic of the gain not equal to 1 and the phase not equal to 0.
Therefore, there is a need of a compensator for eliminating the complex conjugated pole pair of a switching mode power supply.

Digital compensator design method and digital compensator for a switching mode power supply


An example method is provided and includes receiving a data message from a first virtual local area network; determining at an edge switch-router of a Layer-2 network whether the message should be routed; and routing the message in the Layer-2 network at the edge switch-router if the message should be routed. The method also includes switching the message at the edge switch-router if the message should not be routed.

Ethernet architectures have grown in complexity in recent years. This is due, at least in part, to diverse technologies that have emerged to accommodate a plethora of end users. For example, Data Center Ethernet (DCE) represents an extension to Classical Ethernet (CE), and it can offer a lower cost, lower latency, high-bandwidth configuration. The forwarding methodology adopted by networks is generally scalable and, further, provides forwarding paths with equal-cost multipathing with support for different forwarding topologies. Layer-2 link state routing protocols can be used in data centers to overcome the drawbacks of the Spanning Tree Protocol (STP). Transparent Interconnect of Lots of Links (TRILL) from the IETF and Fabricpath from Cisco Systems, Inc. of San Jose, Calif. are examples of such Layer-2 link state routing techniques. The link state protocols allow for better use of network resources by calculating shortest path forwarding trees to the nodes in the network. In certain network scenarios, topology information may not be current, accurate, and/or consistent. Optimally managing network topologies presents a significant challenge to system designers, network operators, and service providers alike.

System and method for layer-2 network routing


Described herein are implementations related to data communication using a frame that includes at least two data packets. In one implementation, a first of the data packets includes at least a payload with repeated payload portions to increase diversity gain. A second of the data packets includes at least a payload with repeated payload portions to increase diversity gain. The repeated payload portions of the second data packet are shuffled or rotated in relation to the repeated data payload portions of the first data packet. In one implementation, the frame is conveyed in a Power Line Communication (PLC) system.

Data packet transmission in multipoint-to-multipoint networks (e.g., ad-hoc or mesh networks) is usually arranged by sending one or more data packets. A data packet is often encoded and modulated. Also, a data packet typically includes at least one frame. Each frame is preceded by a preamble. The primary purposes of the preamble include 1) enabling the receiver of the frame to detect the frame on the transmission medium, 2) adjusting the gain of the receiver (e.g., an analog front end (AFE)) and synchronizing the clock so that frame is received when expected. The frame also has a header that carries information helping the receiver to address, demodulate, and decode the frame. The preamble and header are generally followed by a payload, which carries data for communication to one or more receivers.
Because of their ubiquitous nature, powerlines are increasing in popularity as a transmission medium for many networks that use data packet transmission techniques. For example, Power Line Communication (PLC), also called Mains Communication, Power Line Transmission (PLT), Broadband Powerline (BPL), Powerband or Power Line Networking (PLN), is a term describing several different systems for using power distribution wires for simultaneous distribution of data. PLC systems can communicate voice and data by superimposing a signal(s) over standard 50 or 60 Hz alternating current (AC). For indoor applications, PLC equipment can use household electrical power wiring as a transmission medium.
Most AC power outlets have 3 connections, phase (P), neutral (N), ground (G). A PLC system can utilize two independent channels provided by these three connections (e.g., P-N pair for one channel and N-G pair for another channel). Utilizing more than two channels is also possible. Without loss of generality, only two channels are assumed in this disclosure for the simplicity of description and illustration.
A Single-Input Single-Output (SISO) PLC system often utilizes P-N pair for its communication channel because of its ubiquitous availability. However, emerging PLC Multi-Input Multi-Output (MIMO) technology takes advantage of the remaining communication channel(s) to increase spectral efficiency and throughput.
Most deployed SISO PLC modems provide a payload repetition scheme that effectively repeats payload blocks in frequency and time to increase the robustness when the channel characteristics are unknown. However, such a SISO payload repetition does not effectively translate to MIMO PLC modems and systems, as the application of the SISO payload repetition scheme would result in undesirable correlation of payloads.
The Detailed Description references the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to reference like features and components. Also, note that any text smaller than ten point is presented merely to indict where text would appear in the depicted figures. Since such text is merely an indicator of where text might appear, the content of such text is unimportant to the understanding the implementations depicted.


A new cultivar of pelargonium particularly characterized by having brilliant, deep-purple semi-double flowers, floriferous with small, compact umbels, medium-green foliage with weak zonation, a medium sized, well-branched, spreading to trailing plant habit and a mid-season flowering response, is disclosed.

The present invention comprises a new and distinct cultivar of pelargonium, botanically known as Pelargonium peltatum, and hereinafter referred to by the cultivar name 'Fiscody'. The new cultivar is a product of a planned breeding program which had the objective of creating new varieties having bluish-purple flowers and fairly early flowering response. 'Fiscody' was discovered as a seedling resulting from the cross of the female parent 'I95-421-14' (unpatented), a proprietary pelargonium plant having pink single-type flowers, and the male parent 'Kleblue' (unpatented), a proprietary pelargonium plant having bluish-purple, double flowers.
The new cultivar was created in 2002 in Hillscheid, Germany and has been asexually reproduced repeatedly by vegetative cuttings in Galdar, Gran Canaria, Spain, and Hillscheid, Germany over a three-year period. It has been found to retain its distinctive characteristics through successive asexual propagations, 'Fiscody' reproduces true to type in successive generations of asexual reproduction.
Plant Breeder's Rights for this cultivar were applied for in Germany on Apr. 4, 2005 and Canada on Apr. 20, 2005.


A universal joint comprises a pair of yokes each formed by bending a metal plate, a single piece of cross shaft for connecting the pair of yokes to each other so as to be capable of oscillating and displacing, and a bolt for fixing each of the yokes to an end portion of a shaft. The yoke includes a joint cylindrical portion provided at a proximal end portion thereof and having a discontinuous portion at one place in a circumferential direction, first and second flange portions provided in parallel to each other at a part of the joint cylindrical portion with the discontinuous portion sandwiched in therebetween, a through-hole formed in the first flange portion thereof in such a direction as to bear a torsion positional relationship with the joint cylindrical portion, a screw hole formed in a fixing portion of the second flange portion and disposed concentrically to the through-hole. The bolt has a large-diameter head portion formed at one end of a bar portion and a male screw portion formed similarly at the other end thereof, and is fastened in such as state that the bar portion is inserted into the through-hole from a side opposite to the screw hole, the male screw portion is screwed into the screw hole, and a one-side surface of the head portion is brought into contact with a one-side surface of the first flange portion, thereby pressing an outer peripheral surface of the shaft inserted into the joint cylindrical portion without a large gap and fixing the yoke to the shaft. A length from the one-side surface to an opening edge of the screw hole is set more than 2.6 times as large as a nominal diameter of the bolt.

1. Field of the Invention
The present invention relates generally to a universal joint and, more particularly, to a universal joint incorporated into a steering apparatus of, e.g., an automobile and utilized for transmitting motions of a steering shaft to a steering gear.
2. Related Background Art
For example, Japanese Utility Model Laid-Open Publication No. 59-56424 discloses a structure as shown in FIGS. 13-14, of a universal joint, incorporated into a steering apparatus, etc. of an automobile, for transmitting rotational motion between a pair of rotary shafts which do not exist on the same straight line. This universal joint 1 includes a pair of yokes 2a, 2b, a single piece of cross or cruciform shaft 3 for connecting the pair of yokes 2a, 2b to each other so as to be capable of oscillating and displacing, and bolts which are, though not illustrated, used for fixing the respective yokes 2a, 2b to end portions of unillustrated shafts.
Proximal ends of the yokes 2a, 2b, which are manufactured by effecting press working upon a metal plate such as a steel plate exhibiting a sufficient rigidity, are respectively provided with partially cylindrical joint portions (herein after joint cylindrical portions) 4a, 4b. Each of those joint cylindrical portions 4a, 4b has a discontinuous portion 5 at one place in a circumferential direction, an inside diameter of which is elastically reducible. A rugged portion like serration grooves is formed along an inner peripheral surface of each joint cylindrical portions 4a, 4b. Further, first and second flange portions 6, 7 are, with the above discontinuous portion 5 sandwiched therebetween, provided in parallel with each other in given portions of the respective joint cylindrical portions 4a, 4b. The first and second flange portions 6, 7 are formed with through-holes 8, 9 coaxial with each other in such a direction as to bear a cross positional relationship with each of the joint cylindrical portions 4a, 4b. Moreover, a nut 10 is fixed by welding to an outer surface (a lower surface in FIGS. 13 and 14) of the second flange portion 7, and a screw hole formed in this nut 10 is disposed coaxiallly with the through-holes 8, 9. Further, a pair of joint arm members 12, 12 extend in an axial direction from two positions, opposite to each other in a diametrical direction, of one edges of the respective joint cylindrical portions 4a, 4b in the axial direction. Then, circular holes 13, 13 are formed coaxially with each other in tip portions of the joint arm members 12, 12.
Further, the cross shaft 3 has four lengths of shaft members 14, 14. These shaft members 14, 14 are provided in such a state that the shaft members 14, 14 adjacent to each other are orthogonal to each other. These shaft members 14, 14 are rotatably supported through bearings inwardly of the circular holes 13, 13 formed at the tip portions of the joint arm members 12, 12. More specifically, bearing cups 15, 15 formed in a bottomed cylindrical shape by use of a rigid metal plate such as a case hardening steel, are press-fitted and fixed inwardly of those circular holes 13, 13. The tip portions of the shaft members 14, 14 are inserted in those bearing cups 15, 15, and a plurality of needles 16, 16 are provided between inner peripheral surfaces of the bearing cups 15, 15 and outer peripheral surfaces of the tip portions of the shaft members 14, 14, thus constituting a radial needle bearing.
The thus constructed universal joint 1 has the pair of yokes 2a, 2b fixed to end portions of a pair of shafts each disposed on a non-identical straight line, and a rotating force is transmittable between the pair of shafts. In order to fixedly join the yokes 2a, 2b to the end portions of the respective shafts, a bolt 17 (see FIGS. 1-11 which will be described later penetrating the through-holes 8, 9 formed in the first and second flange portions 6, 7, is screwed into the screw hole of the nut 10 and then fastened. That is to say, the bar member 18 of the bolt 17 is inserted into the two through-holes 8, 9 from the opposite side (an upper side in FIGS. 13 and 14) to the screw hole 11, and a male screw portion 19 provided at a proximal end of the bar member 18 is screwed into the screw hole 11. At the same time, a one-side surface of the head member 20 formed at the proximal end of the bar member 18 is brought into contact with a one-side surface (an upper surface in FIGS. 13 and 14) of the first flange portion 6. Bolts 17 are fastened from this corresponding state, and inside diameters of the joint cylindrical portions 4a, 4b are thereby decreased, whereby the outer peripheral surfaces of the ends of the above shafts are pressed by the inner peripheral surfaces of the joint cylindrical portions 4a, 4b. The outer peripheral surfaces of the ends of the shafts are also formed with serration rugged portions, and therefore the yokes 2a, 2b are firmly fixedly joined to the end portions of the shafts by fastening of bolts 17.
Note that the formation of the screw hole 11 through which the male screw portion 19 of the bolt 17 is screwed to the second flange portion 7 does not necessarily involve fixing the nut 10 to the outer surface of the second flange portion 7 by welding as illustrated in FIGS. 13 and 14. In addition, as disclosed in, e.g., Japanese Patent Laid-Open Publication No. 58-193935, a cylindrical nut member is fixedly fitted inside to a through-hole 9 formed in a second flange portion. Alternatively, as disclosed in Japanese Patent Laid-Open Publication No. 3-41220 and Japanese Utility Model Laid-Open Publication No. 55-68726 that will hereinafter be described, a screw hole is formed directly in a second flange portion 7 in place of the through-hole 9.
A distance between the first and second flange portions 6, 7 is narrowed by fastening the bolt 17. If a particular measure is not taken, however, the flange portions 6, 7 become unparallel to each other so that a distance between the tip portions (left end portions in FIG. 14) of the respective flange portions 6, 7 is especially reduced, whereas a distance between proximal ends (side edge portions of the joint cylindrical portions 4a, 4b, and right end portions in FIG. 14) thereof becomes larger than between the tip portions. As a result, a force in a bending direction is applied to the bolt 17 spanning the two flange portions 6, 7, and there might be a possibility in which the bolt 17 is broken off in an extreme case such as fastening the bolt 17 with a torque largely exceeding a specified value. Such being the case, according to the structure illustrated in FIGS. 13 and 14, the tip portions of the two flange portions 6, 7 are formed with bent portions 21, 21 bent toward the face-to-face flange portions 6, 7. When the distance between the tip portions of the two flange portions 6, 7 is reduced by fastening the bolt 17, tip edges of the two bent portions 21, 21 contact each other, thereby preventing the distance between the tip portions of the two flange portions 6, 7 from being further shrunk. Accordingly, the bolt 17 is prevented from being deformed enough to cause a damage thereto by decreasing a degree to which those two flange portions 6, 7 become unparallel.
Note that Japanese Utility Model Laid-Open Publication No. 59-56424 discloses a structure for decreasing the degree to which the pair of flange portions with a distance reduced by fastening the bolt become unparallel, and, in addition, the known structures are dealt with in Japanese Patent Laid-Open Publication No. 3-41220 and Japanese Utility Model Laid-Open Publication No. 55-68726. According to the structures disclosed in those Publications, some portions, for forming the first and second flange portions 6, 7, of the metal plate are folded double at 180 degrees or formed in padding to increase a thickness.
According to the prior art structures, the degree to which the first and second flange portions 6, 7 become unparallel is decreased for preventing the bolt 17 from being broken off by fastening the bolt 17. It is troublesome to manufacture those first and second flange portions 6, 7, and further it is inevitable that the weight of the first and second flange portions 6, 7 increases.


A call management technique implemented using a call routing engine is disclosed. In the technique, local (e.g., ACD) switching resources and a public network are controlled as a single virtual switch for purposes of implementing call processing features.

1. Field of the Invention
The present invention relates generally to call management using a call routing engine in a communications system, and more specifically, to a call management technique that involves processing by the engine after an initial call connection has been established in the system.
2. Brief Description of Related Prior Art
Systems for managing and routing calls through public and/or private communications networks are known in the art. Conventional automatic call distribution (ACD) systems route calls to agents in telemarketing and service inquiry centers, and provide limited real-time call management and reporting capabilities. A typical ACD system will monitor the status of the agent and, when an incoming call is received, selects the agent to handle a particular service request. Reporting and performance data from the agents are also generated by the ACD.
One particular type of scheme for distributing calls to agents is disclosed in Frauenthal et al., U.S. Pat. No. 4,737,983. According to Frauenthal et al., data representing the present call congestion of each of the ACD systems is accumulated in a database. Using the data in the database, the percentage of calls made to the ACD systems, as a group, is determined. The information is then used to generate call routing information. When a new call is made to the central office, the routing information is queried to determine which of the ACD systems is to receive the call, so as to balance the call traffic load across the ACD systems.
Another call management and distribution scheme is provided in Gechter et al., U.S. Pat. No. 5,036,535. This patent discloses a system for automatically distributing telephone calls placed over a network to one of a plurality of agent stations connected to the network via service interfaces, and providing status messages to the network. Gechter et al.'s disclosed system includes means for receiving the agent status messages and call arrival messages from the network, which means are connected via a network service interface to the network. Routing means responsive to the receiving means is provided for generating a routing signal provided to the network to connect the incoming call to an agent station through the network. In the system disclosed in Gechter et al., when an incoming call is made to the call router, it decides which agent station should receive the call, establishes a call with that agent station, and then transfers the original call onto the second call to connect the incoming caller directly to the agent station and then drops out of the connection (See, Gechter et al., column 11, lines 45–51).
Other prior art call management, routing, and distribution techniques are disclosed in Andrews et al., U.S. Pat. No. 5,873,130, which is assigned to the assignee of the subject application. This patent discloses a communications system and method for automatically making telephone routing decisions with global authority based upon information gathered in real time from the entire communications system and global optimization criteria. The entirety of the disclosure of the Andrews et al. patent is incorporated herein by reference.
In conventional systems that implement the call processing techniques disclosed in the Andrews et al. patent, it is often desirable to facilitate certain "post-routing" call processing features. A call is considered to undergo "post-routing" processing when, after the call has already been initially routed to an initial destination, the same call is again processed such that another destination or called device becomes involved in the call. Examples of conventional "post-routing" call processing features include, e.g., the ability to transfer a call, initially routed via a public network (e.g., a public switched telephone network (PSTN)) to a first called device (e.g., an ACD and/or interactive voice response (IVR) unit-containing system), from the first called device to a second, remote called device, the ability to conference the calling device and/or the first called device with the second called device, etc. Such post-routing call processing may be initiated by the first called device, and when the called devices comprise ACD or IVR systems typically is facilitated by one or more telecommunications inter-site tie-lines connecting the first and second called devices. Unfortunately, however, the use of such inter-site tie lines undesirably increase the cost and complexity of implementing such post-routing call processing features.
Other prior art communications systems utilize conventional integrated services data network (ISDN) and American Telephone and Telegraph (AT&T) technologies to carry out such post-routing call processing features, without using such inter-site tie-lines. However, such prior art communications systems do not control public switched telephone network and local switch resources (e.g., in the called devices) as a single virtual switching resource when implementing such post-routing call processing features. Disadvantageously, this undesirably increases the cost and complexity associated with implementing such post-routing call processing features in such systems, and makes less efficient the use of the telecommunications resources of the called devices and the public network.
Thus, it would be desirable to eliminate the need to use such inter-site tie-lines to facilitate post-routing call processing features, and to provide a mechanism that reduces the cost and complexity associated with implementing post-routing call processing features and ensures that telecommunications resources of called devices and the public network are used more efficiently than in the prior art.

Call management using call routing engine


A thermal mechanical process for bonding a flip chip die to a substrate. The flip chip die includes a plurality of copper pillar bumps, each copper pillar bump of the plurality of copper pillar bumps having a copper portion attached to the die and a bonding cap attached to the copper portion. The process includes positioning the die on the substrate such that the bonding cap of each copper pillar bump of the plurality of copper pillar bumps contacts a corresponding respective one of a plurality of bonding pads on the substrate, and thermosonically bonding the die to the substrate.

1. Field of Invention
The present invention relates generally to semiconductor devices and methods for fabricating the same. More particularly, at least one embodiment is directed to a flip chip semiconductor package and die bonding process.
2. Discussion of Related Art
One semiconductor packaging technique that is widely used in the radio frequency (RF) component industry is referred to as "flip chip" packaging. Flip chip describes the method of electrically connecting the die or "chip" to the package carrier. In contrast to standard chip and wire packaging that uses bond wires to connect the die to the carrier, the interconnection between the die and the carrier in flip chip packaging is made through a conductive "bump" that is placed directly on the surface the die. The bumped die is then "flipped over" and placed face down with the bumps connecting the die to the carrier directly.
The flip chip assembly process generally includes three major steps: 1) bumping of the dies; 2) "face-down" attachment of the bumped dies to the substrate or board; and 3) under-filling, which is the process of filling the open spaces between the die and the substrate or board with a non-conductive but mechanically protective material. There are several types of bumps and bumping processes that are used for flip chip devices. For example, solder bumping includes placing an underbump metallization over the bond pad (e.g., by plating, sputtering or similar techniques), and then depositing solder over the underbump metallization. Another type of flip-chip bumping is known as "plated bumping." The bond pad is covered with a nickel layer to the desired plating thickness, forming the foundation of the bump. An immersion gold layer is then added over the nickel bump for protection. Adhesive bumping is another flip-chip bumping process that stencils electrically conductive adhesive over an underbump metallization placed over the bond pad. The stenciled adhesive serves as the bump after it has been cured.
Gold bumping is a favored bumping process, as the gold bonds provide superior bond strength because of the monolithic structure of the gold material. Gold bonds also generally have superior high frequency performance and low resistance when compared to solder or other conductive materials. Gold bumps may be formed on the flip chip die by depositing a layer of gold in the desired bump locations, or gold-plating a pad formed of another material (e.g., nickel). Flip chips with gold bumps are attached to a substrate with gold bond pads using an ultrasonic gold-to-gold interconnect (GGI) process.
GGI is a thermosonic process by which gold bumps and gold bond pads are joined together by heat and ultrasonic power under a pressure head, using a machine called a GGI bonder. The thermosonic process connection is made by solid-phase bonding between the two gold layers. Diffusion of gold (micro-welding) under load, and ultrasonic power, creates the gold-to-gold connection as a bond layer that is void-free and monolithic. The ultrasonic GGI process has a mounting accuracy of about ±10 μm and can reliably bond die with a thickness as thin as 100 μm. A disadvantage of GGI processes however, is the use of gold, an expensive material, for both the bumps and the pads.

Thermal mechanical flip chip die bonding


The present invention relates to an image processing device arranged for image stabilization of a video stream comprising image frames captured by a video camera, the image processing device comprising: an electronic image stabilization module arranged to perform electronic image stabilization to sub-sets of image frames of the image frames of the video stream to compensate for a oscillating movement of the video camera; and a masking module arranged to apply an edge mask to each sub-set of image frames, wherein each edge mask is having a fixed width, wherein the fixed width is based on a camera oscillation amplitude being specific for the sub-set of image frames to which the edge mask is applied. The present invention also relates to a method for image stabilization of a video stream.

Video streams captured by video cameras may suffer from a problem known as camera shake. For example, a video camera mounted at an area for, e.g., monitoring the area may from time to time experience shakes or vibrations due to shifting environmental factors, such as wind, vehicles (e.g. airplanes, trains, trucks, etc.) entering or leaving the area, construction work, etc. Such shakes or vibrations will induce movement of the video camera, thereby causing a captured video stream to shake.
Prior art systems for image stabilization reducing the effects of camera shake often include electronic manipulation of a video stream captured by the video camera before displaying the video stream. By doing so the viewer is presented with a stable view of the video stream despite the induced movement of the video camera. This electronic manipulation is based on determining an image shift between image frames of the video stream captured by the video camera. Depending on the image read out technique used, the image shift and hence the method of electronic manipulation of a video stream may differ. In case a global shutter is used, i.e. an entire image frame is read out simultaneously, the whole content of an image frame is shifted in order to compensate for the vibration of the video camera. In case a rolling shutter is used, i.e. an image is read out one or a few row(s) at a time, each row or a few rows in the image frames is/are shifted individually since they are exposed at different points in time. For the sake of simplicity, in the examples disclosed below, global shutter read out is used for explaining the electronic image stabilization, however, it should be understood that rolling shutter read out may as well be used for achieving the same result. Hence, the term image shift should be understood as a shift between the whole image content of two image frames or a shift between the image content of one or a few rows of two image frames.
An image shift determination may be made in various ways. One way of determining the image shift is to use sensors within the video camera to measure movement of the camera and with knowledge of the focal length of the camera lens, a corresponding image shift on a camera sensor may be calculated. Alternatively, features within the scene depicted by the video stream believed to be stationary between image frames may be tracked using image processing techniques.
Once the image shift has been measured each of a plurality of image frames of the video stream is shifted in accordance with the measured image shift to compensate for the image shift caused by camera movement. Thereby a viewer may be provided with a stable displayed view of the scene depicted by the video stream.
A prior art image stabilization system will be explained in more detail in connection with FIG. 1.
In FIG. 1(A) an example of a displayed video stream affected by video camera shake or vibration is presented. More precisely, a plurality of superimposed image frames of the video stream depicting a scene of a person 1 and a tree 2 is presented. The video camera shake or vibration induces movement of the video camera. Due to the movement of the video camera the person 1 and the tree 2 move to various positions within the displayed image frames. The superposition of image frames representative of the video stream of the scene captured at different positions of the video camera has an effect of obscuring visual information of the scene. Therefore, FIG. 1(A) presents a representation of an unstable video stream of the person 1 and the tree 2.
In FIG. 1(B) the image frames of the video stream are displayed after determining and applying image shift between the image frames. Hence, FIG. 1(B) is a representation of a video stream after electronic image stabilization according to the above has been applied to the unstable video stream presented in FIG. 1(A). In FIG. 1(B), the stabilized video stream is now centrally located and stable within the display. Hence, the image stabilization system operates to shift each image frame such that the person 1 and the tree 2 appear to be stable in the display. However, as the electronic image stabilization operates to shift entire image frames, part of the displayed video stream will not contain any displayed information and will therefore appear blank. Furthermore, as indicated in FIG. 1(B) by solid lines 3, 4, 5, 6, 7, which are representative of the edges of the displayed image frames, the edges of the video stream will continuously be moving as the image stabilization system operates to present a stable video stream of the scene. In practice, the image stabilization system, hereinbefore described, suffers a disadvantage in that although the image stabilization system operates to stabilize an image within the centre of a display, the peripheral region of the displayed video stream will be continuously moving, which is distracting to the viewer.
To alleviate this problem the prior art image stabilization systems operate to expand or zoom in the displayed view such that only the stable central part of the video stream is displayed. FIG. 1(C) presents the stabilized video stream depicting the scene of the person 1 and the tree 2, expanded to fill the display. In practice, the prior art image stabilization includes an always present digital zooming in of 10-20%. This implies that even when the image is stable, image information around the edges of the image frames is lost. Hence, peripheral image information will be lost, thereby greatly reducing the value of the image information of the video stream. The digital zooming in also implies that the video stream is displayed with a lower resolution than supplied by an image sensor of the video camera.

Method and image processing device for image stabilization of a video stream


A new structure of a capacitor for a DRAM is disclosed herein. The structure of the capacitor includes a mushroom shape first storage node, a dielectric layer and a second storage node. The mushroom shape first storage node includes a base portion that is formed of polysilicon. A plurality of mushroom neck portions located on the base portion. A plurality of roof portions are connected on the tops of the mushroom neck portions. The dielectric layer is conformally covered the surface of the mushroom shape storage node. The second storage node encloses the surface of the dielectric layer. The formation of the mushroom shape capacitor includes forming a first conductive layer over a wafer. Then, an undoped hemispherical grains silicon (HSG-silicon) is formed on the first conductive layer. The HSG-silicon is separated along the grain boundaries to expose a portion of the first conductive layer. Next, the exposed first conductive layer is etched by using the HSG-silicon layer as a mask. A dielectric layer is then deposited on the exposed surface of the first conductive layers, and the HSG-silicon. A second conductive layer is formed over the dielectric layer.

Semiconductor Dynamic Random Access Memory (DRAM) devices have been applied in integrated circuits for many years. Indeed, a memory cell is provided for each bit stored by a DRAM device. Each memory cell typically consists of a storage capacitor and an access transistor. The source of the access transistor is connected to one terminal of the capacitor. The transistor gate electrode is connected to external connection lines called a bit line and a word line, respectively. The other terminal of the capacitor is connected to a reference voltage. Therefore, the formation of a DRAM memory cell comprises the formation of a transistor, a capacitor and contacts to external circuits.
With the trend of making the semiconductor devices, the sizes of memory cells have gotten smaller and smaller. Thus, the area available for a single memory cell has become very small. This has caused a reduction in capacitor area, which in turn results in a reduction in cell capacitance. For very small memory cells, planar capacitor becomes very difficult to use reliably. Specifically, as the size of the capacitor decreases, the capacitance of the capacitor also decreases and the amount of the charge capable of being stored by the capacitor similarly decreases. This results in the capacitor being very susceptible to .alpha. particle interference. Additionally, as the capacitance decreases, the charges held by storage capacitor must be refreshed often.
Prior art approaches to overcome these problems have resulted in the development of various types of capacitor. One of the capacitors is honeycomb-shape capacitor structure. The process uses the characteristic that the oxidation rate at grain boundary is higher than that at the grain itself, and the oxide is thicker at the grain boundary. Then, an etching mask is formed over the grain boundary by etching process. Finally, the etching mask is used for generating the honeycomb-shape capacitor structure. However, the structure has a plurality of tips formed thereon, which will resulte leakage current in the structure. Please see "The Honeycomb-Shape Capacitor Structure for ULSI DRAM, S. Yu et al., IEEE Electron Device Lett., vol. 14, p.369, 1993" and "Tunnel Oxide Prepared by Thermal Oxidation of Thin Polysilicon Film on Silicon, S. L. Wu et al., IEEE Electron Device Lett., vol. 14, p.379, 1993."
Further, a capacitor over bit line (COB) cell with a hemispherical grain silicon storage node has been developed (see "Capacitor Over Bit Line Cell With Hemispherical Grain Storage Node For 64 Mb DRAMs", M. Sakao et al., microelectronics research laboratories, NEC Corporation, IEDM Tech Dig., December 1990, pp655-658). The HSG-silicon is deposited by low pressure chemical vapor deposition method at the transition temperature from amorphous silicon to polycrystalline silicon. This memory cell provides about two times capacitance by increasing the effective surface area of a simple storage node. The following art teaches a highly selective etching method between HSG-silicon and polysilicon. Please see "Selective Etching Technology of in-situ P Doped Poly-Si (SETOP) for High Density DRAM Capacitors, S. H. Woo etal., 1994, Symposium on VLSI Technology Digest of Technical Papers". The present invention will use the method to form storage node of a capacitor.

Method of making a multiple mushroom shape capacitor for high density DRAMs


A printed circuit board with vias that reduce or eliminate radio frequency interference and method of forming the same. The printed circuit board includes non-conductive layers, conductive-layers interspersed between the non-conductive layers, vias extending through the non-conductive layers and the conductive layers, radio frequency absorbing material within each of the vias, where the radio frequency absorbing material is at a conductive layer within the printed circuit board at which a conductive trace is not connected to a via, an insulating layer over each radio frequency absorbing material, and a cylindrical conductive material within via and over each insulating layer.

Non-conductive circuit boards printed with conductive traces, commonly referred to as Printed Circuit Boards (PCBs), are used extensively in commercial electronics. Electronic components are connected to a PCB, and the traces are formed to realize the desired connection there between. The first PCBs were one non-conductive layer with one layer for the conductive traces, or interconnect. To reduce the size of PCBs or to make it possible to realize a complicated circuit, multi-level PCBs were developed.
A multi-level PCB consists of multiple non-conductive layers interspersed with interconnect layers. A via through a layer of a PCB is used to connect a conductive trace on one interconnect layer with that of another. FIGS. 1A-1C illustrate the construction of a via on a multi-layered PCB.
In FIG. 1A is a cross-sectional view of a portion of a PCB 1 showing multiple layers of non-conductive material 2 and multiple layers of conductive traces (i.e., a trace on the top of the PCB, 5 layers of traces within the PCB, and one trace on the bottom of the PCB. In the example, the second 3 and fourth 4 embedded traces, counting from the top of the PCB, are desired to be connected by a via. Epoxy reinforced with fiberglass is typically used for the non-conductive layers 2. Copper is typically used for the conductive traces.
FIG. 1B is a cross-sectional view of the PCB of FIG. 1A, where a hole has been drilled through the PCB and through the second 3 and fourth 4 embedded traces.
FIG. 1C is a cross-sectional view of the PCB of FIG. 1B, where conductive material 6 has been plated in the formed in FIG. 1B. The plated material electrically connects the second 3 and fourth conductive traces, but does not connect to any other conductive trace.
The frequency at which electronic components can operate has steadily increased over the years. To realize the maximum operating frequency of an electronic component, resistance and dielectric losses of the interconnect layers connected to the component should be minimized. However, increased operating frequencies with their attendant shorter wavelengths increase the likelihood of generating radio frequency interference (RFI) on a PCB. FIG. 2 illustrates one possible way of generating RFI on a PCB.
FIG. 2 is a cross-sectional view of a portion of a PCB 21. The PCB 21 includes a first via 22 and a second via 23. The first via 22 electrically connects a first conductive trace 24 on the second embedded conductive layer of the PCB, counting from the top of the PCB, to a second conductive trace 25 on the fifth embedded conductive layer. The second via 23 connects the second conductive trace 25 to a third conductive trace 26 on the same embedded conductive layer as well as possibly to a surface mounted component. A first arrow 27 indicates the preferred path of a signal traversing the interconnection formed by the vias 22, 23, and the conductive traces 24, 25, 26. However, at a sufficiently high frequency, RFI may be created when the intended signal encounters a via. Two examples of this are indicated by the second arrow 28 and the third arrow 29. The second arrow 28 indicates RFI that traverses the PCB, guided by solid plane layers 26A and 26B, whereas the third arrow 29 indicates RFI that reflects off of the second via 23. The fourth arrow 29A indicates energy that can be resonantly amplified by the high Q via stubs associated with via 23. Since RFI can disrupt operation of electronic components on or off of the PCB, there is a need to reduce or eliminate such RFI.
U.S. Pat. Nos. 6,538,538 and 6,661,316, each entitled "HIGH FREQUENCY PRINTED CIRCUIT BOARD VIA," disclose a via that includes a conductive pad surrounding the conductor and embedded within the PCB to increase the frequency at which electronics can operate. Such a via increases the likelihood of generating RFI, not reduces or eliminates RFI as does the present invention. U.S. Pat. Nos. 6,538,538 and 6,661,316 are hereby incorporated by reference into the specification of the present invention.
U.S. Pat. No. 6,541,712 entitled "HIGH SPEED MULTI-LAYER PRINTED CIRCUIT BOARD VIA," discloses a via for eliminating or reducing RFI caused by a via by reducing the length of the via using an insulator. The present invention does not reduce the length of a via using an insulator as does U.S. Pat. No. 6,541,712. U.S. Pat. No. 6,541,712 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. No. 6,621,012, entitled "INSERTION OF ELECTRICAL COMPONENT WITHIN A VIA OF A PRINTED CIRCUIT BOARD," discloses a method of reducing impedance of a via by inserting an electrical component into the via. Reducing impedance does not necessarily eliminate RFI as does the present invention. U.S. Pat. No. 6,621,012 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. No. 6,983,535, entitled "INSERTION OF ELECTRICAL COMPONENT WITHIN A VIA OF A PRINTED CIRCUIT BOARD," discloses a method of reducing impedance of a via by inserting an electrical component into the via. Reducing impedance does not necessarily eliminate RFI as does the present invention. U.S. Pat. No. 6,983,535 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. Appl. No. 20040212972, entitled "PRINTED CIRCUIT BOARD MINIMIZING UNDESIRABLE SIGNAL REFLECTIONS IN A VIA AND METHODS THEREOF," discloses a method of minimizing signal reflectance by avoiding long conductive vias and using, instead, non-conductive vias and inserting conductive elements into the via to connect conductive traces on either side of the via, where the conductive element is only long enough to connect the conductive traces, but not long enough to cause signal reflections. The present invention does not employ non-conductive vias and conductive elements that are only large enough to make the desired connection. U.S. Pat. Appl. No. 20040212972 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. Appl. No. 20040238216, entitled "VIA SHIELDING FOR POWER/GROUND LAYERS ON PRINTED CIRCUIT BOARD," discloses a method of adding an insulating material around a conductive layer to prevent short circuits with a power or ground line if a via hole is drilled improperly. U.S. Pat. Appl. No. 20040238216 does not reduce or eliminate RFI as does the present invention. U.S. Pat. Appl. No. 20040238216 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. Appl. No. 20050230813, entitled "PRINTED CIRCUIT BOARD INCLUDING VIA CONTRIBUTING TO SUPERIOR CHARACTERISTIC IMPEDANCE," discloses a method of forming a conductive ring around a via to facilitate impedance matching and, thus, better suppress noise. The present invention does not employ a conductive ring around a via as does U.S. Pat. Appl. No. 20050230813. U.S. Pat. Appl. No. 20050230813 is hereby incorporated by reference into the specification of the present invention.

Printed circuit board via with radio frequency absorber


A device (4440), system and method may sense and/or analyze in-vivo pressure or stress, and may in addition sense other data such as for example, image data. An in-vivo device (4440) may include a stress or pressure sensor (4443), and possibly an additional sensor, such as an image sensor, a pH sensor, etc. In one example the stress or pressure sensor (4443) is connected to a shell (4444) of the device.

In vivo press can be indicative of organ's function; for example, of endo luminal conditions. The pressure in blood vessels, intra cerebral pressure or intra-gastric pressure, for example, may be indicative of the activity in these body lumens or of prevailing conditions in these lumens. The gastrointestinal (GI) tract is a typically convoluted body lumen starting from the oral cavity and proceeding through the esophagus, stomach, duodenum and small intestine and ending at the rectum; it is a long tube that folds many times to fit inside the abdomen. The small intestine is connected to the large intestine, which begins with the cecum, a small saclike evagination, then continues through the ascending colon, transverse colon, descending colon and the sigmoid (S-shaped) colon to the rectum. Portions of the GI tract are separated by muscular valves, such as the esophageal gate, separating the esophagus from the stomach, the pylorus, separating the stomach from the small intestine and the ileocecal valve separating the cecum from the colon. Such gates may be considered "motility gates" in the sense that motility of matter moving through the GI system may differ before and after passing through such gates. Matter, such as food, is passively moved through the GI tract and pushed through the valves due to the muscle action of the GI tract wall, namely, peristalsis. Thus, motility in the GI tract is achieved via pressure exerted by the GI tract walls.
Some gastrointestinal conditions or diseases, for example constipation, GERD (gastroesophageal reflux disease) and IBS (irritable bowel syndrome), are thought to be related to intestinal motility and are some times referred to as functional diseases (either the muscles of the organs or the nerves that control the organs are not working normally, and, as a result, the organs do not function normally). Whereas some gastrointestinal diseases can be seen and diagnosed with the naked eye or by microscopic examination of biopsies gastrointestinal functional diseases typically cannot be seen with the naked eye or with the microscope. In some instances, the abnormal function can be demonstrated by tests, for example, gastric emptying studies or antro-duodenal motility studies. However, these tests often are complex, are not widely available, and do not reliably detect the functional abnormalities. Accordingly, functional gastrointestinal diseases are identified, to date, by default, namely, diseases involving the abnormal function of gastrointestinal organs in which abnormalities cannot be seen in the organs with either the naked eye or the microscope.
Endo-luminal pressure, e.g., gastric pressure, may be measured by pressure sensors carried on the end of endoscopes or catheters However, these methods may cause patient discomfort and are of limited scope (for example, these methods are not useful for sensing the entire GI tact). They also, by being interventionist in nature, may distort the normal behavior thus distorting the results. Gastric pressure has been known to be measured and the information transmitted from the body by an autonomous ingestible device including, for example, a diaphragm assembly, which includes a diaphragm and elements such as coils, capacitors and a transistor. This assembly, which may be housed in a plastic cap or in a rubber sack, is inserted into the GI tract such that vibration of the gastrointestinal environment (typically containing fluids) is sensed. These measurements and measurements of pressure sensors used in other methods may be useful for indicating the hydrostatic pressure in a body lumen. The hydrostatic pressure is exerted uniformly throughout the lumen, and as such, is easily influenced by events that are unrelated to the activity or condition of the lumen itself. For example, pressure sensed in the GI tract can be affected by breathing and heart activity.
There is therefore a need for an improved system and method for sawing in vivo environments for parameters such as pressure, which might be indicative of a body lumen activity and/or of its condition.

System and method for sensing in-vivo stress and pressure


In application to a superconducting magnet which is cooled by a cryogenic refrigerator, provided is a superconducting coil which can maintain a cooled state and enables a stable operation and continuous driving even if a ramping speed is increased. First and second superconducting conductors are connected with each other. Respective tape-like superconducting multifilamentary wires are electrically connected with each other through solder, to form joint bodies. The respective joint bodies are insulated from each other by interposition of an insulating material therebetween.

1. Field of the Invention
The present invention relates to a superconducting coil, and more particularly, it relates to a superconducting coil for a superconducting magnet which is applied to a magnetic resonance diagnostic apparatus or the like and cooled by a cryogenic refrigerator, for example.
2. Description of the Background Art
In general, superconducting magnets are cooled by two types of methods including a method of dipping and cooling a superconducting magnet in a refrigerant such as liquid helium or liquid nitrogen, and a method of thermally connecting a superconducting magnet directly to a cold head of a cryogenic refrigerator.
In the latter superconducting magnet cooled by a cryogenic refrigerator, a superconducting conductor is generally wound on a coil former (bobbin) in the form of a pancake or solenoid. Japanese Patent Laying-Open No. 6-174349 (1994) proposes means of interposing a mixture of silicon grease and a powder material having excellent thermal conductivity in a connecting portion between the cryogenic refrigerator and the superconducting magnet while filling up clearances between coil wires and those between the coil and the bobbin with the mixture, in order to improve the cooling efficiency for the superconducting magnet having such a structure.
While the superconducting coil can be cooled to a prescribed very low temperature in a short time in the superconducting magnet proposed in the aforementioned gazette, however, remarkable heat generation is caused by an ac magnetic field or a shunt current to disadvantageously result in normal conducting transition of the superconducting coil when the superconducting coil is rapidly excited in the state cooled to the prescribed very low temperature. Such heat generation cannot be suppressed, and hence the superconducting magnet cannot be continuously driven and no stable operation can be attained.


A process for the manufacture of a reflective conductive film comprising: (i) a reflective polymeric substrate comprising a polymeric base layer and a polymeric binding layer, wherein the polymeric material of the base layer has a softening temperature TS-B, and the polymeric material of the binding layer has a softening temperature TS-HS; and (ii) a conductive layer comprising a plurality of nanowires, wherein said nanowires are bound by the polymeric matrix of the binding layer such that the nanowires are dispersed at least partially in the polymeric matrix of the binding layer, said process comprising the steps of providing a reflective polymeric substrate comprising a polymeric base layer and a polymeric binding layer; disposing said nanowires on the exposed surface of the binding layer; and heating the composite film to a temperature T1 wherein T1 is equal to or greater than TS−HS, and T1 is at least about 5° C. below TS-B.

There has been considerable research into the manufacture of transparent conductive films. Such films are generally multi-layer films which comprise a support which exhibits high light-transmittance and/or low haze (the degree to which light is scattered as it passes through a material), as well as high insulating properties, overlaid with a thin conductive layer containing an electro-conductive material. Such films must exhibit high surface conductivity while maintaining high optical transparency and have been used as transparent electrodes in the manufacture of photovoltaic cells, EMI shielding screens, flat liquid crystal displays, electroluminescent devices and touch screens in electronic equipment (for instance PDAs, mobile phones etc). Thin film photovoltaic (PV) cells are of particular interest and for this utility the support must exhibit high light transmittance.
The support can be a glass, ceramic or polymeric substrate, and recent developments in flexible electronic devices have focussed on the use of polymeric substrates. Flexible substrates allow manufacture of conductive films in a low-cost, high throughput process. Transparent conductive films composite films have typically been produced by vacuum deposition or sputtering techniques. Wet-coating methods have also been used to prepare conductive films, by applying to a substrate a coating composition comprising conductive particles and typically also a binder resin, which is then dried (or sintered) at high-temperature to form a conductive layer, as disclosed in for example U.S. Pat. No. 5,504,133, JP-A-8-199096, JP-A-9-109259, U.S. Pat. No. 5,908,585, U.S. Pat. No. 6,416,818, U.S. Pat. No. 6,777,477, said dried layer may be then subsequently compressed as disclosed in for example in US-2007/0145358 and US-2008/0026204.
Typically, the conductive layer comprises a conductive metal oxide such as indium tin oxide (ITO). However, metal oxide films are fragile and prone to damage during bending or other physical stresses. They also require elevated deposition temperatures and/or high annealing temperatures to achieve high conductivity levels, and this can limits the applicability of vacuum deposition techniques in the manufacture of flexible electronic devices based on polymeric substrates. In addition, vacuum deposition is a costly process and requires specialized equipment, and is not conducive to forming patterns and circuits which typically results in the need for expensive patterning processes such as photolithography. Conductive polymers have also been used as electrical conductors, but these generally have lower conductivity values and higher optical absorption (particularly at visible wavelengths) compared to the metal oxide films, and can suffer from lack of chemical and long-term stability.
More recent developments have utilised nanowires for the preparation of transparent conductive layers. The nanowires must exhibit good adhesion to the substrate and good abrasion resistance. The preparation of transparent conductive layers is disclosed in WO-A-2007/022226, WO-A-2008/046058, WO-A-2008/131304, WO-A-2008/147431, WO-A-2009/017852, WO-A-2007/114645 and WO-A-2004/069736. Typically, the nanowires are applied onto a pre-formed substrate and form a surface conductive network. The nanowire network is then typically over-coated with one or more protective or barrier layer(s), such as an abrasion-resistant or binder layer (e.g. a UV-curable resin layer) in order to impart mechanical integrity or some other characteristic to the conductive layer, while allowing high light-transmittance. The network of metal nanowires becomes partially embedded in the over-coat matrix such that some nanowires may be entirely covered by the matrix while other nanowires may protrude above the surface. Surface conductivity is ensured if enough protruding nanowires percolate above the over-coat matrix.
Thus, the conventional production of transparent conductive films comprising nanowires involves three distinct stages: (i) the preparation of the substrate; (ii) subsequent off-line coating of the nanowires; and (iii) subsequent off-line coating of the protective over-coat layer. Typically, one or both of the off-line coating steps is effected using solvent-coating techniques. It would be desirable to provide a more efficient method of manufacture, for example one which dispenses with the over-coating step, while maintaining the mechanical integrity and abrasion resistance of the conductive layer. In addition, it would be desirable to avoid the use of potentially hazardous and environmentally unfriendly organic solvents in the manufacture of transparent conductive films.
It would also be desirable to provide a reflective conductive film, particularly a diffuse reflecting film. Such films can be used in applications which require a high reflectance and a high electrical conductivity. Such conductive and reflective films may be used as elements in solar cells, liquid crystal displays, electronic display devices (including electronic-paper (e-paper) and electrochromic displays), light irradiation devices (including light-emitting diode devices and semiconductor laser devices), decorative illumination devices, or any device which may require a reflecting electrode. Conductive films which act as diffuse reflecting layers in a variety of applications are disclosed in US-2009/0176121-A. A reflective conductive film is used as the rear electrode layer in a photovoltaic cell in U.S. Pat. No. 5,348,589. Photovoltaic devices containing a reflective conductive films are also disclosed in U.S. Pat. No. 6,061,977 and U.S. Pat. No. 6,613,603. A metal layer e.g. Al, Ag, Cu, Au and a conductive oxide layer e.g. ZnO (used to impart some roughness to the extremely smooth metal surface) are successively applied onto a substrate (such as stainless steel) used as a support for the photovoltaic device. The two layers are typically deposited by expensive physical coatings methods, e.g. magnetron sputtering, which are difficult to apply to large-scale roll-to-roll production.
Reflective conductive film is disclosed in U.S. Pat. No. 6,583,919 as a layer in an electrochromic anti-glare mirror, suitable for use in the automotive industry. Electrically conductive and pigmented (white or coloured) polymer compositions are disclosed in U.S. Pat. No. 6,184,280, which further describes the formation of electrically conductive filaments, films and other articles therefrom, which are reported for use as anti-static mats, shields for electromagnetic radiation, construction materials, and other applications requiring conductive members. US-2007/0126959 and U.S. Pat. No. 6,927,818 disclose reflective conductive film layers in transflective liquid crystal display devices. U.S. Pat. No. 6,548,832 and U.S. Pat. No. 6,784,462 teach the use of reflective conductive films to improve the efficiency of light extraction in light irradiation devices containing light-emitting elements such as light-emitting diodes or semiconductor lasers.

Dupont Teijin Films U.S. Limited Partnership


A clock signal selection circuit includes a delay for delaying a switching control signal to supply a delayed switching control signal. A first selection circuit changes its state between first and second states in response to the switching control signal. A second selection circuit changes its circuit condition between third and fourth states in response to the switching control signal and the output of first selection circuit. The second selection circuit outputs a second clock signal when operated in the third state and inhibits the second clock signal in the fourth state. The first selection circuit supplies the first clock signal when operated in the first state and inhibits the first clock signal from being supplied when operated in the second state in response to the switching control signal and the output of second selection circuit. A third selection circuit transmits the switching control signal to either the first or second selection circuit in response to the delayed control signal.

1. Field of the Invention
This invention relates to a clock signal selection circuit.
2. Description of the Prior Art
A clock signal selection circuit for selecting one of first and second clock signals. FIG. 5 is a logic circuit diagram of a first prior art clock signal switching circuit. FIG. 6 shows waveforms of outputs at respective portions of the first prior art clock signal switching circuit.
The first prior art clock signal switching circuit shown in FIG. 5 comprises a first gate G11 for effecting operation of AND between a control signal and a first clock signal CLK1, a second gate G12 for effecting operation of AND between a control signal and a second clock signal CLK2, and an OR gate G13 for effecting operation of OR between outputs of the first and second gates G11 and G12.
As shown in FIG. 6, the first prior art clock signal selection circuit changes the outputting of the first clock signal CLK1 from that of the second clock signal CLK2 in response to the control signal CONT to produce a selected clock signal CLK13.
FIG. 7 is a logic circuit diagram of a second prior art clock signal selection circuit. The second prior art clock signal selection circuit comprises first and second D type flip-flops F1 and F2, first, second, and third gates G14, G15, G16, first and second delay circuits DY1 and DY2 and an inverter IV1. FIG. 8 is a time chart showing respective outputs of the second prior art clock signal selection circuit. As shown in FIG. 8, when the control signal CONT is H, an output Q2 of the second flip-flop F2 is logic H, so that the second clock signal CLK2 is selected. This causes an output Q1 of the first flip-flop F1 to be L, so that outputting of the first clock signal CLK1 is inhibited. When the control signal goes to L, the output Q2 of the flip-flop F2 goes to logic L and the output Q1 of the flip-flop F1 goes to H, so that outputting of the second clock signal CLK2 is inhibited and that of the first clock signal CLK1 is permitted.
FIG. 9 is a logic circuit diagram of a third prior art clock signal selection circuit. The third prior art clock signal selection circuit has fourth and fifth gates G17 and G18 in addition to a structure of the second prior art wherein the D type flip-flops F1 and F2 with the reset inputs are replaced with D type flip-flop F3 and F4 having no reset input.
In the first prior art clock signal selection circuit, there is a problem that it generates a short obstructive pulse Px during switching operation as shown in FIG. 8. In the second and third prior art clock signal selection circuits, delay circuits DY1 and DY2 are used to prevent hazard. However, there is a problem that hazard is not prevented sufficiently because there is two portions which judge the logic level of the control signal, so that there is a possibility that the first flip-flop and the second flip-flop F1 and F2 output different results due to time delay. Moreover, in the second and third prior arts, there is a further problem that in the manufacturing of integrated circuit including this clock signal selection circuit is difficult because there is analog type delay circuits DY1 and DY2 whose delay time should be controlled in the manufacturing processing.


Radially spaced calibration holes are drilled parallel to the exterior surface of a cylindrical shell for a dryer roll. An ultrasonic transducer is mounted in a fixture filled with a coupling medium which allows for adjustment of the spacing and angle of the transducer which traverses the shell as it is rotated. The transducer produces a signal directed to the shell. A computer calculates the time the signal takes to travel from and return to the transducer and the depth of the shell from which the signal returns. A clear signal corresponding to holes up to one inch from the surface are found by adjusting the ultrasonic transmission angle. This angle is approximately 23 degrees from a normal to the casting surface. The calibrated transducer traverses the surface of the shell. The signals are gathered and stored to create data which may be used in maintaining the shell for the dryer roll.

In the manufacture of tissue paper and paper towel a web of paper fibers is formed and pressed against a Yankee dryer. After drying the web is scraped from the surface of the Yankee dryer, giving the web a creped texture which gives the paper it's soft absorptive characteristics. Because only a single dryer is used the Yankee dryer is normally large, typically from twelve to twenty-five feet in diameter. Moreover, the Yankee dryer is heated by steam at pressures of up to 160 psig. A Yankee dryer may be 400 inches long and may have a total weight of over 100 tons. Because of its large size and high operating pressure, a Yankee dryer typically has a cylinder wall thickness of over two inches. Yankee dryers are generally formed from cast iron; a material which has good release characteristics if the surface is properly ground. Thus the surface of a Yankee dryer requires periodic regrinding to maintain the proper surface finish.
A Yankee dryer is a pressure vessel and the safety precautions typically employed with any pressure vessel or boiler must be observed. In U.S. Pat. No. 4,398,421 an apparatus for measuring the thickness of a work piece which is useful for measuring the thickness of steam boiler walls is disclosed. Determining the wall thickness of a Yankee dryer is useful but it is also desirable to detect small voids within the thickness of the dryer wall.
Existing ultrasonic inspection systems have a limited capability for detecting small voids or finding voids near the surface of cast iron parts. Ultrasonic signals in cast iron are scattered and reflected from grain boundaries present in the cast iron. This characteristic of cast iron makes detecting small discontinuities very difficult. Even measurement of thickness in cast iron can be difficult to perform. One national study has found errors of over 40 percent in thickness measurements of cast iron with some conventional techniques. Ultrasonic transducers typically have an interface zone of up to one-half inch where subsurface discontinuities can not be detected.
X-ray methods are used for the inspection of Yankee dryer rolls. X-ray methods, however, require the use of radioactive sources which are cumbersome and dangerous. In practice, x-ray images are only made of limited portions of the Yankee dryer. Furthermore, x-ray imaging is not effective at detecting hair-line cracks because such cracks do not significantly reduce the density of the material. Hair-line cracks are, however, typically detectable by ultrasonics.
In the application No. 08/690,763 filed Aug. 1, 1996, which is incorporated herein by reference, a method of ultrasonic inspection was disclosed which is capable of detecting flaws in a Yankee dryer with a high signal-to-noise ratio.
In that application it was disclosed that if an ultrasonic signal is directed at a surface to be inspected at a particular angle, about ten percent of the signal will appear as Harris waves which propagate into the test plate at ninety degrees to the surface. The signal which propagates vertically is polarized, with the result that the signal detects flaws with greatly improved signal-to-noise ratio. The particular angle is between that angle where the ultrasonic signal is refracted so as to propagate parallel to the surface of the metal plate and that angle where the ultrasonic signal is reflected by the test plate. Employing shear waves, for an incident medium of water and a refracting medium of cast iron, the specific angle is approximately 33 degrees from the vertical. For steel the specific angle is approximately 31 degrees. For brass the angle is about 50 degrees.
This particular angle while detecting flaws, produced a signal without an apparent time of flight--meaning that the depth of the flaw could not be determined with the disclosed method. Methods of finding the depth of a flaw using ultrasonic energy can be difficult to calibrate. Traditional methods require a flat bottomed hole drilled from a surface opposite the surface from which the ultrasonic interrogation is conducted. A hole with a flat bottom is difficult to drill and difficult to precisely line up parallel to the interrogation surface.
What is needed is a method for performing complete inspection of a Yankee dryer for material defects which can determine the depth of any detected flaws.