A method of manufacturing VIGUs and IGUs comprises providing a first lite; providing a second lite spaced apart from the first lite to form a cavity therebetween; and encircling the lites with a one piece band. Spacers of a metal solder alloy or other reflowable material are inserted between the band and the perimeter edges of the lites. The assembly is heated in an evacuated environment, causing the spacers to melt and hermetically bond to the lites, but not until the cavity has been substantially evacuated.

Insulating glass units (also known as insulating glazing units or "IGUs" or "IGs") and vacuum insulating glass units (also known as vacuum insulating glazing units or "VIGUs" or "VIGs") are known. They comprise two or more parallel but spaced-apart sheets, or panes, of glass attached and/or sealed to one another around their respective peripheries. The gap between each pair of sheets or panes of glass (also known as "lites") defines a cavity. In IGUs, the cavity is filled with air or other gasses such as argon, krypton or xenon, whereas in VIGUs, the gap is "filled" with or contains a reduced-pressure atmosphere or a vacuum. Spacers (also known as "stand-offs" or "suspenders") are typically disposed within the gap of IGUs and VIGUs to maintain the gap. In the case of VIGUs, spacers are particularly necessary in order to support the sheets of glass against the pressure of the outside air, which otherwise might distort or damage the glass, or cause the two panes of glass to come in contact with each other so as to produce a thermal "short circuit" (i.e., a thermally conductive path directly through the panes of glass).
Using vacuum to increase the insulating performance of window glazing components is not a new concept, and in fact many innovative approaches have been taught in the literature over the last 75 years. It is, however, readily observed by skilled practitioners of the art that the majority of the prior work relates to low-to medium-vacuum levels, i.e., vacuum levels within the range from about 760 torr (1 atmosphere of pressure at sea level) to about 10−3 torr. Note, for purposes of this application, a "higher" level of vacuum is understood to correspond to a lower absolute pressure, e.g., a vacuum level of 10−4 torr is a higher vacuum than 10−3 torr. In a few cases the literature makes reference to the measured vacuum levels in glazing components, but in many cases the maintainable vacuum level must be interpreted from careful evaluation of the materials exposed to the vacuum enclosure, the methods used to create the vacuum seal and the methods used to produce the vacuum condition in the enclosed space.
While the literature describing vacuum insulating window glazing components may not rigorously define the vacuum levels, literature from other industries, such as the electronics industry, defines different vacuum levels and the types of materials and processing methods required to achieve and maintain those specified vacuum levels. The common distinction between medium- and high-vacuum devices is a vacuum level of 10−3 torr. In other words, the range of high-vacuum levels begins at about 10−3 torr and goes higher, i.e., in the direction toward and/or past 10−4 torr. In the case of vacuum insulating glass units ("VIGUs" or "VIGs") for windows, doors and other components, where it is desirable for the VIGs to retain a prescribed minimum vacuum level for an extended operating lifetime (e.g., 25 years), a vacuum containment system capable of initially maintaining a higher level of vacuum (e.g., 10−4 torr to 10−5 torr), may be necessary.
One purpose of high vacuum insulating glass units ("HVIGUs") is to provide lower levels of conductive heat losses between temperature-controlled spaces and non-temperature-controlled spaces, or between different temperature-controlled spaces, that are separated by this glazing unit (i.e., compared to VIGUs with low or medium-vacuum levels). In such cases, providing this desired lower level of conductive heat transfer over a long period of time is desirable. Since the ambient conditions in the uncontrolled space, most commonly the external atmospheric environment, produce a variety of stresses including thermal, pressure and mechanical vibration, and since, to a lesser extent, this also happens in the conditioned space, various embodiments of the HVIGU will be more or less capable of surviving the applied stresses while maintaining the desired minimum vacuum level. Thus, the design lifetime, i.e., the period of time that the HVIGU will maintain its desired level of performance, is one of the performance features of the HVIGU.
VIGUs and HVIGUs have multiple applications in addition to their use as the glass unit (component) of windows for residential and non-residential buildings. Examples of other (non-fenestration) uses include glass windows for refrigerated supermarket display cases (supermarket refrigerators and freezers); thermally-insulating covers for active and/or passive solar collectors; windows for transportation vehicles including spacecraft, aircraft, automobiles, trains, buses and watercraft (boats, ships and submarines); and many other applications.
As previously described, IGUs, VIGUs and HVIGUs are typically constructed using at least two spaced-apart sheets or panes of glass, each of some prescribed thickness. The gap between two adjacent glass sheets or panes defines a cavity. In IGUs, the cavity is filled with air or other gasses such as argon, krypton or xenon, whereas in VIGUs and HVIGUs, the gap is "filled" with a reduced pressure atmosphere or a vacuum. Spacers (also known as "stand-offs" or "pillars") are typically disposed within the gap of IGUs, VIGUs and HVIGUs to maintain the gap. In the case of VIGUs and HVIGUs, spacers are particularly necessary in order to support the sheets against the pressure of the outside air, which otherwise might distort or damage the glass, or cause the two panes of glass to come in contact with each other so as to produce a thermal "short circuit."
These glass panes are then sealed, typically along the edges, using some arrangement of sealing elements which are intended to isolate the evacuated volume from the surrounding atmospheric pressure. Since the primary objective of the VIGU or HVIGU is to provide a low thermally-conductive barrier between environmental spaces, each of which may have a higher or lower temperature with respect to the other, it is obvious to skilled practitioners of the art that the two panes of glass may reach temperature levels which vary distinctly from each other. In fact, for a given space-to-space temperature differential, the pane-to-pane temperature differential will typically increase as a function of reduced thermal conductivity of the VIGU or HVIGU. As a result of the temperature differential between the panes of glass, the panes may expand and contract differentially. This may also introduce differential movement of the spacers relative to one or both panes of glass.
For reference purposes, in a dual pane IGU, VIGU or HVIGU, the outdoor-facing or outside-facing glass pane of an IGU/VIGU/HVIGU is typically referred to as glass lite #1, and the indoor-facing or inside-facing glass pane is typically referred to as glass lite #2. There are typically four glass surfaces of interest, denoted (in order from outside to inside) as surfaces 1, 2, 3 and 4. Surfaces 1 and 2 are, respectively, the outdoor facing and indoor facing surfaces of glass lite #1, and surfaces 3 and 4 are, respectively, the outdoor facing and indoor facing surfaces of glass lite #2. Thus, surfaces 2 and 3 are typically disposed on opposite sides of the cavity of the IGU/VIGU/HVIGU.
Similarly, in a triple pane IGU, VIGU or HVIGU, the outdoor-facing or outside-facing glass pane of an IGU/VIGU/HVIGU is typically referred to as glass lite #1, the middle glass pane is referred to as glass lite #2 and the indoor-facing or inside-facing glass pane is typically referred to as glass lite #3. There are typically six glass surfaces of interest, denoted (in order from outside to inside) as surfaces 1, 2, 3, 4, 5 and 6. Surfaces 1 and 2 are, respectively, the outdoor facing and indoor facing surfaces of glass lite #1, surfaces 3 and 4 are, respectively, the outdoor facing and indoor facing surfaces of glass lite #2 and surfaces 5 and 6 are, respectively, the outdoor facing and indoor facing surfaces of glass lite #3. Thus, surfaces 1 and 6 are typically disposed on opposite outer surfaces of the overall IGU/VIGU/HVIGU, surfaces 2 and 3 are typically disposed facing one another on opposite sides of the outer cavity between lites #1 and #2 and surfaces 4 and 5 are typically disposed facing one another on opposite sides of the inner cavity between lites #2 and #3 of the IGU/VIGU/HVIGU.
Vacuum insulated glass units (VIGUs/HVIGUs) are of interest for window applications because of their extremely high insulating properties, with center-of-glass insulating or thermal resistance R values as high as R-13 or more, expressed in US units of British Thermal Units as ft2·° F.·hr/Btu. (conductive U-Values or U-Factors of 0.07 or lower, expressed in US units of BTU/(h·° F.·ft2)).
The conversion between SI and US units of R-value is 1 h·ft2·° F./Btu=0.176110 K·m2/W, or 1 K·m2/W=5.678263 h·ft2·° F./Btu.
Creating the reduced pressure between two or more lites surrounded by a metal band hermetically bonded to the perimeter of the two lites in a two-lite VIGU or HVIGU or to three or more lites of a VIGU or HVIGU with three or more glass lites can be very difficult. Evacuation of the VIGU/HVIGU's cavity or cavities often requires evacuation times of eight hours or more when a small vacuum septum fabricated into one or more of the VIGU/HVIGU's lites is used as the evacuation port. When vacuum septums fabricated into one or more lites are used, they are usually covered and protected from damage after the evacuation process by attaching with an adhesive or epoxy a cover over the then hermetically-sealed septum. The cover is typically a stainless-steel disk.
The use of a gettering material (also know as "getter material" or "getters") is well known to those skilled in the art of hermetic packaging. Getters are designed and made of materials to have an affinity to one or more non-noble gases to have the gas or gases stick or be absorbed by the getter upon impact with the getter rather than continue to remain moving in the package's atmosphere. In some cases the atmosphere inside the package may be a partial pressure atmosphere, e.g. a vacuum.

Edge seal assemblies for hermetic insulating glass units and vacuum insulating glass units


The present application relates to communications between a partner network and a wide area network (WAN) via the Internet. The WAN advertises unicast border gateway protocol (BGP) address prefixes for a plurality of front-end devices in the WAN. An agent in the partner network measures a plurality of paths to a service within the WAN. Each of the plurality of paths is associated with one of the plurality of front-end devices and a respective unicast BGP address prefix. The agent provides measurements of the plurality of paths to the WAN. The WAN selects a path within the WAN for the service. The agent receives a routing rule specifying a unicast address prefix for a selected device of the plurality of front-end devices of the WAN. The agent forwards data packets for the service to the respective border gateway protocol address prefix of the selected device via the Internet.

Wide area networks may include computing resources spread across a geographic region and connected via communication links such as fiber optic cables. The size of wide area networks may vary greatly from a small city to a global network. For example, a WAN may connect multiple offices of an enterprise, the customers of a regional telecommunications operator, or a global enterprise. The computing resources and connections within a WAN may be owned and controlled by the WAN operator.
A partner network may obtain services from the WAN. For example, a partner network may be an enterprise network and the WAN may host services for users of the enterprise network. The partner network may be connected to the WAN via the Internet. A path between the partner network and the WAN may include one or more Internet Service Providers (ISPs). In general, traffic traversing the Internet may be routed on a lowest cost basis. Accordingly, neither the partner network nor the WAN may have significant control of routing decisions between the partner network and the WAN.
One attempt to give a network greater control over routing decisions is software defined wide area networking (SD-WAN). SD-WAN may control routing decisions within an enterprise network. An SD-WAN appliance, which may be referred to as an SD-WAN edge is a physical or virtual network function that is placed at an organization's branch/regional/central office site, data center, and in public or private cloud platforms. The SD-WAN edge may perform classification of traffic and forwarding based on availability of a route to another SD-WAN edge. In the context of cloud services hosted by the WAN operator, however, an SD-WAN may not have information or ability to select routes over the Internet to the WAN hosting a cloud service.

Network diagnostic to control path between partner network and WAN


The present invention relates to a material for hydrogen-storage constituted by Ti-Mn alloy system which has a high hydrogen-storage capacity, plateau hydrogen dissociation equilibrium pressure, hypostoichiometric composition and crystal structure of C14. Ti-Mn alloy system for hydrogen-storage of the invention which has a C14 crystal structure, is represented as: Ti.sub.u Zr.sub.v Mn.sub.w Cr.sub.x V.sub.y X.sub.z, wherein, X is at least one of element selected from the group consisting of Fe, Al and Ni; u, v, w, x, y and z are mole numbers of each components; 0.7<u<1.0; 0<v<0.3; 1.0.ltoreq.w.ltoreq.1.3; 0.1.ltoreq.x.ltoreq.0.4; 0<y<0.3; 0.ltoreq.z.ltoreq.0.2; 0.7<u+v<1.0; 1.4.ltoreq.w+x.ltoreq.1.7; and, 1.3.ltoreq.w+x+y+z<2.0.

Conventionally, hydrogen has been stored in a pressure-resistant vessel under a high pressure or stored as a cryogenic liquid, being cooled to an extremely low temperature. However, said storage methods have revealed some drawbacks that: transfer is very difficult, since the hydrogen is stored in a large-sized vessel; amount of hydrogen stored in a vessel is limited, due to low density of hydrogen; and, heat is required to release hydrogen to the outside.
On the other hand, several metals and alloys have been known to permit reversible storage and release of hydrogen. In this regard, they have been considered as a superior hydrogen-storage material, due to their high hydrogen-storage efficiency. Solid-phase metal or alloy system can store large amounts of hydrogen by absorbing hydrogen with a high density and by forming a metal hydride under a specific temperature and pressure or an electrochemical conditions, and hydrogen can be released by changing the said conditions. The metal hydride has an advantage of high-density hydrogen-storage for a long time, since it is formed by the intrusion of hydrogen atoms to the crystal lattice of a metal.
In general, hydrogen-storage alloy system must have a hydrogenation characteristics such as a proper plateau pressure, high hydrogen-storage capacity and hydriding rate, and long cycle-life. A variety of metallic materials for hydrogen-storage to meet the said requirements have been proposed in the art, e.g., Mg, Mg-Ni, Mg-Cu, Ti-Fe, Ti-Ni, R-Ni and R-Co alloy systems(wherein, R is a rare-earth metal).
Of these metals, Mg alloy system, though it can store a relatively large amounts of hydrogen per unit weight of the storage material, heat energy should be supplied to release hydrogen stored in the alloy, owing to its low hydrogen dissociation equilibrium pressure at room temperature. Moreover, release of hydrogen can be made over a long time, only under a high temperature of over 250.degree. C. along with the consumption of large amounts of energy.
On the other hand, rare-earth metal alloy, has demerits that hydrogen-storage capacity per unit weight is lower than any other hydrogen-storage material and it is very expensive, though it can efficiently absorb and release hydrogen at room temperature, grounded that it has the hydrogen dissociation equilibrium pressure in the order of several atmospheric pressures at room temperature.
Ti-Fe alloy system which has been considered as a typical and superior material of the titanium alloy systems, has the advantages that it is relatively inexpensive and the hydrogen dissociation equilibrium pressure of hydrogen is several atmospheric pressure at room temperature. However, since it requires a high temperature of about 350.degree. C. and a high pressure of over 30 atms for initial hydrogenation, the alloy system provides relatively low hydrogen absorption/desorption rate and it has a hysteresis thereof, finally to hinder the complete release of hydrogen stored therein.
Under the circumstances, a variety of approaches have been made to solve the problems of the prior art and to develop an improved material which has a high hydrogen-storage efficiency, a proper hydrogen dissociation equilibrium pressure and a high absorption/desorption rate.
In this regard, Ti-Mn alloy system has been reported to have a high hydrogen-storage efficiency and a proper hydrogen dissociation equilibrium pressure, since it has a high affinity for hydrogen and low atomic weight to allow large amounts of hydrogen-storage per unit weight.
In specific, Ti.sub.0.9 Zr.sub.0.1 Mn.sub.1.4 V.sub.0.2 Cr.sub.0.4 alloy system which has a hydrogen-storage capacity of 1.94 wt % and a dissociation pressure of 8 to 10 atm at 20.degree. C., has been suggested as a superior hydrogen-storage alloy(see: T. Gamo et al, Int. J. Hydrogen Energy, 10(1):39-47(1985)). However, said alloy system does not reach a stage of practical application in the art, since it has still low hydrogen-storage capacity.

Hydrogen-storage material employing ti-mn alloy system

Korea Advanced Institute of Science and Technology


In a method of fabricating a semiconductor device, an interlayer insulating film is selectively etched to remove a level difference at an area of the interlayer insulating film on a cell plate on cylindrical capacitors and simultaneously form a concave portion on a fuse portion. Since the etching is ended to a degree that the cell plate is not exposed, the concave portion can be formed on the fuse portion not exposed. This does not add a step of forming a protection film on the fuse portion.

1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device equipped with a fusing portion which will be cut for defect relief, and more particularly to a method of fabricating a semiconductor device which forms an opening for easily cutting the fuse portion.
2. Description of the Prior Art
Generally, semiconductor devices in which elements such as transistors are integrated on a semiconductor substrate are subjected to wafer test before packaging to test whether it can carry out a prescribed operation. In this case, even when a failure chip with poor elements is found in the test, in order that the chip can carry out a normal operation without being fabricated again, a spare element previously formed in the same chip is substituted for the poor element. Such a technique has been commonly adopted to relieve the failure chip. Further, when a poor element is found in a memory array section, another block unit in a spare memory cell array is substituted for the block unit incorporating the poor element. The spare element is substituted for the poor element in such a manner that a fuse formed as a part of wiring is physically cut. For example, the semiconductor device is provided with a spare memory array as well as a memory array section. In such a structure, when a row decoder or column decoder for selecting each block receives an address signal selecting a block incorporating a poor element, a fuse is cut. Thus, without accessing the poor block, the spare block in place of it will be accessed.
The fuse can be cut by several methods. A method which has been widely adopted is laser trimming in which the fuse is molten and cut by laser irradiation. FIGS. 17A to 17C are sectional views of a semiconductor device which show the conventional method of laser trimming. In FIG. 17A, reference numeral 1 denotes a semiconductor substrate; 2 a first inter-layer insulating film formed on the semiconductor substrate; 3 a fuse portion formed on the first inter-layer insulating film; 4 a second inter-layer insulating film formed on the fuse portion 3 and the first inter-layer insulating film 2; and 5 a wiring layer serving as an electric pad formed on the second inter-layer insulating film 4.
As seen from FIG. 17B, the second inter-layer insulating film 4 is selectively removed by etching to form an opening above the fuse portion 3. In this step, the circuit formed on the semiconductor substrate is subjected to wafer test. A test signal is supplied through the wiring layer (electrode pad) 5. When it is found as a result of test that the fuse portion 3 must be cut, the fuse portion 3 is cut by irradiation of laser light rays 7 through the opening 6. Thereafter, as seen from FIG. 17C, a passivation film 8 serving as a final protection film is formed on the entire surface of the second inter-layer insulating film 4 and in the opening 6. Further, another opening 9 is made in the passivation film 8 by etching so that the electrode pad 5 is exposed.
The opening 6 is formed in order to reduce the thickness of the insulating film on the fuse portion 3 to a degree that the fuse portion 3 can be easily cut by irradiation of the laser light rays 7. In this case, in order to form the opening 6, a step of etching a resist formed using a photomask is required. For this purpose, the second inter-layer insulating film 4 is etched so that a contact hole is formed at the portion not shown of the second inter-layer insulating film 4 and the opening 6. Thus, the normal contact hole made in the inter-layer insulating film and the opening 6 can be formed in the same step using the same mask. For example, Postexamined Japanese Patent Pubication 4-79138 discloses that as shown in FIG. 18, in the same PSG film a, a contact hole b brought into contact with the source/drain regions c of an MOS transistor and an opening d formed on the fuse portion e on a field layer f can be formed simultaneously. A protection layer q is formed on the fuse portion e.
The technique described above has the following drawbacks. Where the contact hole b and fuse portion e are formed simultaneously, the fuse portion e is exposed. Exposure of the fuse portion e may lead to its break because of an accidental cause. In order to prevent this, a protection film q is previously formed on the fuse surface as shown in FIG. 18 thereby to prevent exposure of the fuse surface. In the above reference, a protection film q having a double layer structure composed of a polysilicon layer and a molybdenum silicide layer is formed on the fuse surface. However, this requires an additional step of forming the protection film. Further, in the above reference, the protection film g is formed of the same material and in the same step as the gate electrode of an MOS transistor. However, in the multi-layered structure of a semiconductor device, the fuse portion is formed on a more upper layer so that it can be easily broken. For this reason, the protection film cannot be necessarily formed simultaneously with the gate electrode.

Method of fabricating semiconductor device with a fuse portion


The present invention provides a variable valve lift including a housing, a plurality of swing arms that are rotatably arranged at the housing, and a plurality of latching mechanisms for selectively latching the plurality of swing arms.

(a) Field of the Invention
The present invention relates to an engine of a vehicle and more particularly, a rocker arm for a variable valve lift (VVL) apparatus and a variable valve lift apparatus having the same.
(b) Description of the Related Art
An internal combustion engine generates power by burning fuel in a combustion chamber in an air media that is drawn into the chamber. Intake valves are operated by a camshaft in order to take in the air, and the air is drawn into the combustion chamber while the intake valves are open. In addition, exhaust valves are operated by the camshaft, and a combustion gas is exhausted from the combustion chamber while the exhaust valves are open.
An optimal operation of the intake valves and the exhaust valves depends on a rotation speed of the engine. That is, optimal opening/closing timing of the valves or an optimal lift depends on the rotation speed of the engine. In order to achieve such an optimal valve operation depending on the rotation speed of the engine, research has been undertaken on a variable valve lift (VVL) apparatus that enables different valve lifts depending on the engine speed.
As an example of the VVL apparatus, a hydraulic line is formed for each desired valve lift, and oil supply to the hydraulic line is controlled by an oil control valve (OCV).
According to such a scheme, in order to achieve a variety of valve lifts, the number of hydraulic lines should be increased or a greater number of OCVs should be employed even though the OCV typically occupies a large volume in the cylinder head. Considering that the cylinder head has limited space, only a limited number of OCVs can be installed in the cylinder head, and an increase of the number of the OCVs employed results in complexity of a hydraulic circuit in the cylinder head and an increase of manufacturing cost.
Therefore, if a VVL apparatus may be realized by merely redesigning a single part (e.g., a rocker arm), an improvement of performance of an engine may be expected without incurring substantial cost, and a smaller-size and higher-performance engine may be achieved.
In addition, research has been undertaken on a cylinder deactivation function in which a specific cylinder may be deactivated when the engine may be operated at a relatively low output power. This cylinder deactivation enables improvement of fuel consumption of the engine without deteriorating maximum power of the engine.
Accordingly, if an improved VVL apparatus enables such a cylinder deactivation function, performance of the engine may be improved in various aspects with minimal cost and space loss of the engine.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

Rocker arm for variable valve lift, and variable valve lift apparatus having the same


A pouch is formed from one or more webs of material that provide at least one absorbent surface. The pouch further includes an integral flap, which may be folded over the opening, or entrance, of the pouch so as to maintain the contents of the pouch in place and to help retain moisture within the pouch. The interior of the pouch is defined, at least partially, by its absorbent faces.

Traditionally, the purpose of a medical pouch has been to provide a sterile barrier for instruments and devices up to the point of use. After use, the soiled articles are sent to a washing/disinfecting facility in bags or containers which allow protein to dry on the instruments, thereby rendering them difficult to clean.
Statements of the Invention
According to the present invention there is provided a pouch formed from one or more webs of material providing at least one absorbent surface, the pouch having an integral flap which may be folded over the entrance of the pouch so as to maintain the contents of the pouch in place and help to retain moisture within the pouch, and the interior of the pouch being defined at least partly by the or each absorbent surface. In use therefore, an item, such as a medical instrument will be located within the pouch along with the absorbent surface or surfaces.
A pouch in accordance with the present invention is intended to provide a moist environment for the bag contents at and beyond the point of use. Such an environment reduces the drying of protein and other debris on the instruments, thus facilitating easier cleaning prior to sterilisation.
To achieve and maintain a moist environment within the pouch, liquid is introduced into the pouch and is allowed to permeate the absorbent surfaces prior to use. The liquid may be a sterile liquid and/or it may contain one or more additives. The liquid is preferably an aqueous liquid.
Preferably, the pouch comprises first and second substantially rectangular webs of material, at least one of which has an absorbent surface on one side thereof, the webs being of the same length but of different width and being sealed together along respective three edges of each web so that the web of greater width extends beyond the free edge of the web of lesser width to provide a flap for folding over the web of lesser width and also for facilitating ease of entry of the instruments or trays into the pouch.
Alternatively, the pouch may comprise first and second substantially rectangular webs of material and a third web located between said first and second webs and having at least one absorbent surface, the first and second webs being of the same length but of different width and being sealed together along respective three edges of each web so that the web of greater width extends beyond the free edge of the web of lesser width to provide a flap for folding over the web of lesser width and also for facilitating ease of entry of the instruments or trays into the pouch.
Preferably, the pouch is formed by at least one web of absorbent material.
Preferably, the pouch is provided with at least one web of water imperious plastics film.
One or both of the flaps and the outer surface of the web of lesser width is provided with means for securing the flap to the outer surface of the web of lesser width. Preferably, such securing means is provided on the flap.
Preferably, the securing means is double sided tape.
The first and second webs may be provided by a single piece of folded over material or alternatively by separate pieces of material.
Preferably, the webs are additionally joined together at one or more positions along the length of the pouch to provide pockets for accommodating medical instruments.
For example, the webs may be joined together at two positions along the length of the pouch to provide three pockets.
The present invention also provides a method of storing a medical instrument or component in a moist environment, the method comprising locating the instrument or component within a pouch as claimed in any of the preceding claims, the or each absorbent surface being permeated with liquid.
The pouch may be provided in "wet" condition, that is to say, with the or each absorbent surface permeated with liquid. Alternatively, it may be in "dry" form with liquid supplied in a separate container, from which it is added to the pouch. As a further alternative, the pouch may be supplied dry and the user may make up a suitable liquid for addition to the pouch.

Pouch for medical instruments and devices


A display panel and a driving method thereof, and a display device are disclosed. The display panel includes: a pixel region, including a first pixel region and a second pixel region located around the first pixel region, the first pixel region and the second pixel region each including a plurality of pixels; a photosensitive layer, located at least in the second pixel region; a cover plate, on a side of the pixel region for displaying, and the cover plate including a light transmission region and a light shielding layer surrounding the light transmission region. The light shielding layer coincides with at least a portion of the second pixel region in a direction perpendicular to the cover plate, and the photosensitive layer is configured to determine a position of the light transmission region.

In products such as existing liquid crystal display devices (LCD) and active-matrix organic light emitting diode (AMOLED) display devices, a screen of a product is getting larger and larger, the screen visibility ratio is getting higher and higher. Therefore, many manufacturers have higher and higher requirements for the narrow frame structure.

Display panel and driving method therefor, and display device

CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.


In a method for terminating a plurality of ATM lines for a base station modulator/demodulator in a mobile communication system for data communication between upper stations and a base station by a transmission method wherein ATM cells are mapped utilizing an existing leased line as a physical medium sublayer, when an increase in capacity of the base station necessitates leased line interfaces corresponding to a plurality of upper stations, processing is carried out in such a manner that leased line numbers are added to respective HEC regions of ATM cells sent from each upper station into a leased line interface section, whereby the addition of the function of the leased line interface section involved in an increase in the leased line can be minimized and the additional function can be simply designed utilizing a conventional technique. By virtue of this constitution, a method for receiving a plurality of ATM lines can be realized which can efficiently utilize VCI filters and can distinguish each upper station in a leased line interface section.

FIG. 1 is a system construction diagram showing one example of a conventional mobile communication system for data communications between an upper station and a base station by a transmission method wherein ATM calls are mapped utilizing an existing leased line.
An upper station 150 is connected to a base station 101 through a network 103 and a leased line 151, and is connected to a leased line interface 152 within the base station 101. Therefore, the upper station 150 and the leased line interface 152 are connected in a 1:1 logical relationship.
FIG. 2 is a typical diagram showing an ATM cell format. An ATM cell 110 is constituted by data of 53 bytes, and is divided into an ATM header 118 in a region of 5 bytes from the head and a payload 117 of the remaining 48 bytes. The ATM header 118 is composed of GFC (generic flow control) 111, VPI (a virtual path identifier) 112, VCI (a virtual channel identifier) 113, PT (a pay load type) 114, CLP (cell loss priority) 115, and HEC (header error control) 116.
VPI 112 is utilized for setting a virtual path between the upper station and the base station. VCI 113 is utilized for identification in the case of the communication of a plurality of data through the set VP (a virtual path).
HEC 116 detects a bit error in the ATM header 118, and is the result of 8-bit CRC coding for 4 bytes of the portion other than HEC 116 in the ATM header 118. The payload 117 is a communication data storage region.
FIG. 3 is a typical diagram showing a leased line (secondary group) frame format which is an example of a leased line frame format.
FIG. 4 is a typical diagram showing the construction of ATM cell termination processing means in the leased line interface 152 in the prior art technique. Data received from the leased line 151 is synchronized in a frame format as shown in FIG. 3 at a leased line frame trailer 120 in the leased line interface 152. After the establishment of the frame synchronization, cell synchronization for establishing the cell boundary position is carried out in an ATM cell synchronization detector 121 to identify the ATM cell 110 which has bean mapped within the frame.
FIG. 5 is a typical diagram illustrating an ATM cell synchronization method in the ATM cell synchronization detector 121 shown in FIG. 4. The ATM cell 110 is fixed in 53 bytes and mapped within the frame. Therefore, from the state wherein cell synchronization has not been established, the ATM cell synchronization detector 121 performs HEC processing 126 of the received signal one bit by one bit, and recognizes a position, at which data free from an HEC error has been detected, as an ATM header 118. Since the ATM header 118 is continuously received in a cycle of 53 bytes, the processing is continued based on the assumption that the next ATM header 118 is present at a position located 48 bytes after HEC-detected position. Stable HEC detection is the point of cell synchronization completion 128.
Upon the cell synchronization completion 128, the ATM cell synchronization detector 121 can extract ATM cells within the frame.
The ATM HEC error detector 122 shown in FIG. 4 performs error detection of HEC 116 in the restored ATM cell 110, and an ATM cell 110, in which an error has been found, is discarded in this functional section because there is a possibility that the error has taken place during data transmission.
In the protocol error detector 124 shown in FIG. 4, upon the receipt of an ATM cell 110 free from the HEC error, confirmation is made on whether or not VPI/VCI is an expected value. When data communication takes place between the upper station 150 and the base station 101, VPI/VCI is set and functions as a parameter at the time of communication with the upper station 150. Therefore, upon the receipt of an ATM cell having an value other than the set value, this ATM cell should be discarded as a protocol error.
FIG. 6 is a typical diagram showing an example of the construction of CCH connection in the prior art technique. In the example shown in FIG. 6, CCH (control channel) is a signal provided for the control of the base station 101, and three CCH signals are provided per base station 101. The upper station uses the CCH signal to control the base station, for example, at the time of connection to a terminal.
In CCH_A 129, VCI 113 is set at "20." CCH_B 130 has a VCI 113 value of "21," and CCH_C 131 a VCI 113 value of "22." Further, DCHs (data channels) also have respective different VCIs 113. All the signals including DCHs have identical VPI 112 "0." DCHs represent voice data, and are respectively identified by VC.
Since the type of CCH/DCH is identified by VCI 113, the base station 101 should provide the same number of VCI filters 132 as the number of VCIs connected by the leased line 151 to detect an protocol error.
In the VCI filter 132, VPI/VCI does not have a fixed value. Therefore, the value is set at the time of connection to the upper station 150, and comparison is performed for the set value.
FIG. 7 is a typical construction diagram of the protocol error detector 124 shown in FIG. 4. For the ATM cell 110 sent from the ATM HEC error detector 122, VPI/VCI is confirmed by the VPI/VCI detector 134. ATM Cells 110 other than the set VPI/VCI are discarded. CPU 125 receives ATM cells 110, which have not been discarded in the protocol error detector 124, and detects data in the payload 117.
This prior art technique, however has the following problems.
The first problem is that, when a plurality of connections to upper stations 150 have become necessary due to an increase in capacity of the base station 101, the base station 101 should provide the same number of leased line interfaces 152 as the number of upper stations (connected leased lines). FIG. 8 is a typical system construction diagram at the time of the connection of a plurality of upper stations to the base station in a conventional mobile communication system for data communication between upper stations and a base station by a transmission method wherein ATM cells are mapped using an existing leased line.
In signals provided between the upper stations 150 and the base stations 101, like CCH, the number of supports in the base station 101 is fixed. For example, the base station is controlled by an upper station A. On the other hand, data comes from upper station A/upper station B/upper station C. Therefore, the number of CCHs in the base station is limited. In this signal, the upper station connected by the leased line 151, from which the connection of VCI is carried out, is not determined. This is because a redundancy is considered such that, for example, when the upper station A 150a has had trouble, the upper station B 150b as an alternative station connects CCH to prevent breakdown of the system.
FIG. 9 is a typical diagram showing the construction of CCH connection through a plurality of upper stations in the prior art technique. In the conventional protocol error detector 124, filters of VPI/VCI set as shown in FIG. 6 should be provided. Therefore, as shown in FIG. 8, a leased line interface section A 152a, a leased line interface section B 152b, and a leased line interface section C 152c should be provided for respective leased lines.
As shown in FIG. 9, when CCH is connected from each upper station 1 VCI by 1 VCI, however, the VIC filter 132 of CCH not supported by the protocol error detector 124 of the leased line interface sections 152a/152b/152c is not used.
Thus, in the conventional construction, a larger number of VIC filters 132 than necessary should be provided in the protocol error detector 124. This is disadvantageous from the viewpoints of a reduction in size of hardware and a reduction in cost.
The second problem is that, with respect to VPI/VCI set between upper stations, a value falling within a specified range can be independently set for each upper station and, thus, an identical value can be used in each upper station. In FIG. 9, CCH_A 129, CCH_B 130, and CCH_C 131 are different from each other in VCI 113. In fact, however, in all the upper stations, the VCI 113 can be set at "20."
Thus, since identical VPI/VCI can be used in each upper station, the leased line interface sections 152a/152b/152c cannot identify the upper stations through VPI/VCI.

Filtering using communication line identification


Circuitry for preventing slow erasing and slow programming in non-volatile semiconductor memories is disclosed. This circuitry establishes the potential on the source regions of cells in blocks not currently being programming so as to substantially prevent the occurrences of slow erasing and slow programming which can alter the state or condition of the cells.

Metal-Oxide-Semiconductor (MOS) electrically programmable read-only memories (EPROMS) frequently use memory cells that have electrically isolated gates (floating gates). These floating gates are typically completely surrounded by insulation and formed from a polycrystalline silicon (polysilicon) layer. Information is stored in the memory cells or devices in the form of charge on the floating gates. Charge is transported to the floating gates by a variety of mechanisms such as avalanche injection, channel injection, tunnelling, etc., depending upon the construction of the cells. The cells are erased generally by exposing the array to ultraviolet radiation. An example of these cells can be found in U.S. Pat. Nos. 3,500,142; 3,660,819; 3,755,721; and 4,099,196. In some cases these cells are electrically erasable (EEPROM) cells. An example of such a cell is shown in U.S. Pat. No. 4,203,158.
The invention of the present application is used with an EPROM cell, particularly one which is electrically erasable, commonly referred to as a "flash" EPROM cell.
Due to the nature and design of a typical flash memory device, the entire device must be erased in order to erase any one cell in that device. Flash memory array blocking allows segregating different portions or types of data. In this way, when one portion needs to be erased, the other portion(s) do not have to be erased.
However, whenever any cells in a given block are programmed, even cells in another block may be affected by such effects as slow programming due to the combination of potentials necessarily applied to the cells.
Prior attempts at controlling these combination of potentials have met with limited success and have revealed such effects as slow erasing, again due to the combination of potentials then applied to the cells.
Proper control of all of the potentials applied to all of the cells in all of the blocks of a flash memory array, as discussed herein, substantially eliminates the problems of both slow programming and slow erasing.


A method and apparatus for obtaining content with reduces round trip times is provided. The method may comprise transmitting, from a device, a primary content item request to a proxy server to obtain a primary content item using a first protocol, receiving the primary content item from the remote proxy using the first protocol, generating one or more secondary content item requests for one or more secondary content items associated with the primary content item, transmitting the one or more secondary content item requests to the proxy server using a second protocol, wherein the second protocol decouples the one or more secondary content item requests from an acknowledgement of receipt of the one or more secondary content item requests, and receiving at least one of the one or more secondary content items from the proxy server using the second protocol.

1. Field
The disclosed aspects relate to communications between a device and a network to obtained web content.
2. Background
Advances in technology have resulted in smaller and more powerful personal computing devices. For example, there currently exist a variety of portable personal computing devices, including wireless computing devices, such as portable wireless telephones, personal digital assistants (PDAs) and paging devices that are each small, lightweight, and can be easily carried by users. More specifically, the portable wireless telephones, for example, further include cellular telephones that communicate voice and data packets over wireless networks. Further, many such cellular telephones are being manufactured with relatively large increases in computing capabilities, and as such, are becoming tantamount to small personal computers and hand-held PDAs.
Still further, users of such device are interested in using the devices to access more web based content. Currently, a device may obtain web content relying on sequential transmission and acknowledgement protocols. As applied to a wired communications network, such protocols have not been found to be overly limiting, as the round trip times have been found to be relatively small. However, unlike in wired communications network, communications through wireless network may be unfavorably delayed through sequential transmission and acknowledgement protocols thereby increasing the time it takes to access web content.
Thus, improved apparatus and methods for obtaining content with access times are desired.

Methods and apparatus for obtaining content with reduced access times


Methods for code protection are disclosed. A method includes using a security processing component to access an encrypted portion of an application program that is encrypted by an on-line server, after a license for use of the application program is authenticated by the on-line server. The security processing component is used to decrypt the encrypted portion of the application program using an encryption key that is stored in the security processing component. The decrypted portion of the application program is executed based on stored state data. Results are provided to the application program that is executing on a second processing component.

Code Protection (CP) technologies encompass a class of access control technologies that are used by hardware manufacturers, publishers, copyright holders and individuals as a means of controlling the use of digital content and devices. CP technologies include technologies that inhibit uses of digital content that are not desired or intended by the content provider.
CP technologies seek to provide control of digital content or devices to a content provider or device seller after it has been purchased by a consumer. As it relates to digital content, such control can include preventing access to content, preventing content copying and preventing the conversion of content to other formats. As it relates to devices, such control can include restricting the hardware and software that can be used with a device.
Some conventional CP technologies are susceptible to specific types of attack. For example, software based CP technologies can be susceptible to attacks that are based on information that is contained by the software itself because the software can include information that can enable the decryption of content (e.g., decryption keys). Consequently, an attacker may be able to extract this information and decrypt and copy the content directly, and thereby bypass the restrictions imposed by the CP system
Hardware based CP technologies have susceptibilities as well. Some of these technologies require the use of purpose built hardware to hear and/or to see content. This approach attempts to ensure that only licensed users (those with the hardware) can access the content. In addition, it seeks to deny system users access to the secret decryption key.
However, although hardware based CP technologies can provide robust protection, it can be very difficult to build hardware that is sufficiently robust to protect a secret key against a sufficiently determined adversary. Moreover, once the secret key is known, building a version of the hardware that can be used to hear and/or see content can be relatively straightforward. Accordingly, conventional technologies can lack a level of protection that is sufficient to deter determined adversaries.

Code protection using online authentication and encrypted code execution


Ball limited metallurgy is used in conjunction with defining a solder deposit volume using an aperture in a resist layer and reflow of electroplated solder materials deposited in that aperture, possibly with planarization after deposition to enhance volume accuracy, to develop solder deposits extending up to 10 .mu.m or more above the surface on which solder is deposited. Such deposits can be made at fine pitch and provide solder connections of high reliability even when the distance which must be bridged by the solder connection is not easily or reliably regulated.

1. Field of the Invention
The present invention generally relates to the fabrication of electronic circuit devices and, more particularly, to the in-situ formation of solder deposits especially of a size appropriate to solder connections between carriers or substrates and chips or other substrates or carriers where a significant gap may exist.
2. Description of the Prior Art
Formation of electrical and mechanical connections between elements of an electronic device has long been known, particularly for attachment of discrete components and integrated circuits to carriers such as printed circuit boards. As component sizes have been reduced and in the course of production runs of particular electronics devices and portions thereof, many sophisticated techniques for forming such connections by soldering have been developed, particularly for forming numerous connections concurrently and at close spacing.
In particular, in modular circuit packaging, in which numerous connections are formed in layers on lamina which are later stacked and sintered or otherwise fused to provide a complex interconnection structure for the interconnection of numerous integrated circuit chips which may be mounted thereon, soldering techniques have been developed by which the chips can be mechanically mounted and also form potentially thousands of connections to each chip in a very closely spaced array. For this purpose, the technique of application of solder materials and flux has become quite critical, particularly as to volume of solder materials. If too much solder is used, the solder material may form unwanted bridges between closely spaced conductors and/or connection pads. If too little solder is used, the mechanical and/or electrical integrity of the connection may be severely compromised, if a solder connection can be formed at all.
Generally the amount of solder required for a particular connection depends on the area of the connection and the physical proximity of the surfaces which are to be connected. Solder can successfully bridge relatively small gaps and, by adjustment of solder-wettability of surface surrounding the connection, solder flow can generally be well-controlled within the boundaries of the surfaces to be connected and which must necessarily be solder wettable. However, the volume of solder, if too great for a given area and surface separation, may be sufficient to cause solder flow across surfaces which are not solder wettable. Conversely, if the separation of surfaces is too great to be bridged by the volume of solder available, the solder will merely form bumps on the solder wettable surfaces to the limit of the solder volume without making a connection therebetween.
Generally, the surfaces to be connected by solder can be placed in sufficiently close proximity for connections to be made with very small volumes of solder materials. Such volumes of solder materials have been dispensed as a paste, containing particles of solder as a fine powder in a binder, by screening techniques, often using masks, as solder preforms such as the so-called C4 preform which may be appropriately placed and then caused to collapse in a controlled fashion upon application of heat. Production, use and rework of C4 solder deposits are discussed in detail on pages 366-391 of "Microelectronics Packaging Handbook" edited by R. R. Tummala et al., Van Nostrand Reinhold, N.Y., 1989.
More recently, solder materials have been deposited by evaporation or electroplating of solder materials. Electroplating is rapidly becoming a technique of choice for extremely close connection spacings possible at the present state of the art principally because lithographic techniques can assure that solder is placed at all desired locations while closely limiting the possibility that any solder materials at all will be placed at any other location.
As is known in the art, electroplating of solder materials requires the formation of common connections to all locations which are to be electroplated with solder materials with specific locations to which solder is to be electroplated exposed with a dielectric resist mask. The volume and height of the solder materials deposited is generally limited by the thickness of the resist used. Currently available resists can provide solder bump height of about 4 to 5 mils which is sufficient for most application. However, thicker resists are not readily available and, in any event, cause difficulty in lithographic exposure and patterning since the energy of exposures sufficient to expose a greater thickness of resist is also scattered within the resist, causing inaccuracy of the outline of the exposure pattern and the shape of the profile of the resist at apertures which adversely affects the accuracy of the solder volume deposited. Further, the masking and patterning may be compromised by inaccuracy of registration of the exposure for patterning the resist; causing inaccuracy of position of the deposited solder materials, particularly near the maximum resist thickness available.
Recently, some technologies have been developed which, while providing distinct and substantial advantages in circuit performance and package capacity (in terms of the number of circuits which may be included therein) as well as in chip integration density, present substantial new difficulties in formation of solder connections. In particular, circuit packages having connections made to edges of chips have become known in which solder bumps on a chip edge are pushed onto pins attached to the substrate. The so-called Single Inline Memory Module (SIMM) is exemplary of this type of package. However, in this and other types of edge connection packaging, due to difficulties of alignment and irregularities of chip edge geometry, particularly where several chips may be joined together prior to connection to a carrier, a maximum spacing of 4 -5 mils between a contact surface thereof and a connection surface of a substrate to which it is to be electrically and mechanically attached cannot be maintained. A solder bump height of 10 mils is considered to be required for formation of reliable solder connections having such geometries.
Nevertheless, the pitch of connections thereto must approach the pitch of connections to integrated circuits formed and or mounted in accordance with other technologies in order to exploit the potential integration density available in those technologies. Accordingly, forming solder deposits by electroplating has not been feasible since greater volumes of solder, higher dimensional extent above the carrier and higher geometrical accuracy of solder bumps is required to form connections than can be accommodated by thicknesses of currently available resists. At the same time, the pitch of connection pads closely approaches the limits at which solder connections can be reliably formed using preforms or by screening of solder materials and at which additional and unintended amounts of solder material can severely compromise manufacturing yield.
Accordingly, a need exists for accurate deposition of larger volumes of solder and with a greater dimensional extent above a surface than is available with currently available processes.

Method of forming oversized solder bumps

International Business Machines Corporation


A method and system of forming large-diameter SiC single crystals suitable for fabricating high crystal quality SiC substrates of 100, 125, 150 and 200 mm in diameter are described. The SiC single crystals are grown by a seeded sublimation technique in the presence of a shallow radial temperature gradient. During SiC sublimation growth, a flux of SiC bearing vapors filtered from carbon particulates is substantially restricted to a central area of the surface of the seed crystal by a separation plate disposed between the seed crystal and a source of the SiC bearing vapors. The separation plate includes a first, substantially vapor-permeable part surrounded by a second, substantially non vapor-permeable part. The grown crystals have a flat or slightly convex growth interface. Large-diameter SiC wafers fabricated from the grown crystals exhibit low lattice curvature and low densities of crystal defects, such as stacking faults, inclusions, micropipes and dislocations.

1. Field of Invention
The invention relates to high-quality, large-diameter silicon carbide (SiC) single crystals of 4H and 6H polytype and the sublimation growth process thereof. The SiC single crystals of invention can be used in semiconductor, electronic and optoelectronic devices, such as high power and high frequency diodes and transistors, ultra-fast semiconductor optical switches, detectors working in harsh environments and many others.
The invention is an improved process of SiC sublimation crystal growth. The main novel aspect of the invention is in control of the vapor transport and temperature gradients, wherein said transport is restricted to the central area of the growing crystal, while the crystal and its environs are under conditions of near-zero radial temperature gradients. This leads to the advantageously shaped growth interface, such as flat or slightly convex towards the source, reduced crystal stress and reduced densities of crystal defects.
Other novel aspects of the invention include in-situ densification of the SiC source by sublimation and filtration of the vapor from particulates originating from the SiC source. As an optional feature, the invention comprises a step of in-situ synthesis of the SiC source from elemental components.
The SiC single crystals grown by the growth process of invention are suitable for the fabrication of large-diameter, high-quality SiC single crystal substrates of 4H and 6H polytype, n-type and semi-insulating, including substrates of 100 mm, 125 mm, 150 mm and 200 mm in diameter.
2. Description of Related Art
Over the last decade, significant progress has been achieved in SiC crystal growth and substrate manufacturing. Currently, the largest SiC substrates available commercially are 4H and 6H SiC wafers of 100 mm in diameter. 150 mm substrates have been under development, and, recently, limited quantities of 150 mm n-type substrates became available on trial or sampling basis. Broad implementation of 150 mm diameter SiC substrates and, in the future, 200 mm substrates will enable significant cost reduction of SiC- and GaN-based semiconductor devices.
Development-grade 150 mm n-type wafers are known in the art. However, progress in SiC-based devices is still hampered by the scarcity of commercially available, high-quality 150 mm SiC substrates and by the absence of 200 mm substrates.
Harmful defects in SiC substrates include: dislocations, micropipes, stacking faults, inclusions of foreign polytypes and carbon inclusions. Stress in the SiC substrate is another factor detrimental to the device performance and technology.
Dislocations and Micropipes
The main dislocation types in hexagonal SiC are: Threading Screw Dislocations (TSD), Threading Edge Dislocations (TED) and Basal Plane Dislocations (BPD). The term 'threading' means that the dislocation line is approximately parallel to the hexagonal <0001> axis. The term 'basal' means that the dislocation line lies in the basal hexagonal (0001) plane. TSDs cause leakage and device degradation, while BPDs lead to the generation of stacking faults under bias and, subsequently, to the terminal device failure. TEDs are viewed as relatively benign defects.
Micropipes (MP) are hollow-core TSDs with the Burgers vector exceeding 3c, where c is the lattice parameter. 4H SiC homoepitaxial layers are commonly grown on 4° off-cut substrates, whereupon at least a fraction of dislocations and micropipes present extends into the epilayer from the substrate. MPs are "device killers" causing severe charge leakage even at low bias voltages.
Etching in KOH-based fluxes is commonly used to reveal etch pits due to dislocations and MPs—each dislocation type produces etch pits of characteristic geometry. In addition to etching, MP density (MPD) can be determined optically, by studying polished SiC wafers under a polarizing microscope. Upon etching on-axis SiC wafers (i.e. oriented parallel to the hexagonal c-plane) or wafers oriented several degrees off-axis, each threading dislocation and MP produces one etch pit on the wafer surface. Therefore, MP, TSD and TED densities are measured as the number of corresponding etch pits per 1 cm2 of the wafer surface.
The terms 'dislocation density', 'total dislocation density' and 'wafer-average dislocation density' used in the SiC related literature and in the present disclosure are understood as the density of etch pits per 1 cm2 of the wafer surface and, therefore, signify the density of threading dislocations.
BPD lines are in the basal plane, and the number of etch pits BPDs produce depends on the wafer off-cut angle. For instance, BPDs do not produce etch pits in on-axis wafers. The best way to reveal BPDs is by x-ray topography, where they are visible as a plurality of curved lines. Accordingly, the BPD density is calculated as the total length of the BPD lines (cm) per total analyzed volume of the substrate (cm3), i.e. in the units of cm/cm3.
Micropipes are hollow-core TSDs with the Burgers vector exceeding 3c, where c is the lattice parameter. Micropipes are stress concentrators triggering generation of BPD loops around the micropipe. Micropipes are "device killers" causing severe charge leakage even at low bias voltages. In addition to etching, micropipe density (MPD) can be determined optically, by studying polished SiC wafers under a polarizing microscope.
3″ and 100 mm SiC substrates with MPD=0 have been demonstrated by several commercial manufacturers. However, average MPD values in commercial substrates are, typically, higher than 0.1-0.2 cm2.
Stacking Faults
For 4H and 6H polytypes, the normal stacking sequences in the <0001> direction are 'ABCB' and 'ABCACB', respectively. Stacking faults (SFs) are two-dimensional defects violating the ideal stacking sequence and emerging as a result of non-optimized growth conditions. During homoepitaxial growth on 4° off-cut 4H SiC substrates, SFs propagate from the substrate into the epilayer. The presence of SFs can be detected by x-ray topography and photoluminescence. Based on the x-ray topography, the SF density can be expressed as percentage of the substrate area occupied by SFs. SFs are terminal for the devices.
Inclusions of Foreign Polytypes
Free energies of various SiC polytypes are close, and polytype inclusions, such as 15R, are frequently observed in 4H and 6H crystals, especially when the growth conditions are non-optimized or unstable. The lattice of 15R is rhombohedral, and 15R inclusions in hexagonal 4H and 6H lead to crude defects, such as dislocation walls and clusters of micropipes.
Carbon Inclusions
Carbon inclusions are common in SiC crystals, and their origin is usually assigned to the spent, carbonized SiC source. Evaporation of SiC is incongruent, with the vapor enriched with silicon. As a result, gradual accumulation of the carbon residue, which is a light and flaky substance, takes place during growth. Carbon particles from the residue become airborne and, transported by the vapor flux, incorporate into the growing crystal. Carbon inclusions, which can be from a fraction of a millimeter to several microns in size, are often visible in a polished wafer as light-scattering clouds. Large carbon inclusions lead to micropipes, while clouds of small-size inclusions increase the dislocation density.
X-Ray Quality
The method of x-ray rocking curves provides quantitative information on the lattice curvature and broadening of the x-ray reflection. The lattice curvature is expressed as ΔΩ, which is a variation of the sample angle Ω between different points on the wafer surface (ΔΩ=ΩMAX−ΩMIN). High values of ΔΩ are indicative of strong lattice deformation. In highest quality SiC substrates, ΔΩ is below 0.1°, while in present-day commercial SiC substrates, ΔΩ values as high as 0.2-0.3° are often observed.
X-ray reflection broadening is expressed as Full Width at Half Maximum (FWHM) of the reflection peak. High FWHM values are a consequence of lattice disorder, such as high density of dislocations and low-angle grains. For highest quality 4H SiC substrates, the value of FWHM is on the order of 10-12 arc-seconds and comparable to the angular divergence of the incident monochromatic x-ray beam. In the present-day commercial SiC wafers, the values of FWHM are, typically, above 15 arc-seconds and up to 75-100 arc-seconds. A FWHM value above 25-30 arc-seconds is a sign of inferior crystal quality.
Stress
In a SiC wafer, one can distinguish global, wafer-size stress and local stress. The magnitude of stress can be quantified by Raman spectroscopy or by special x-ray methods. However, a much simpler, qualitative technique is routinely applied to SiC wafers—visual inspection under crossed polarizers. Based on the cross-polarizer contrast, the level of stress and its uniformity can be assessed qualitatively, and various macroscopic defects, such as dislocation clusters, polytype inclusions, grain boundaries, etc. can be found. The cross-polarizer contrast is usually classified qualitatively as 'low', 'medium' or 'high'.
SiC Sublimation Growth of Prior Art
The sublimation technique of Physical Vapor Transport (PVT) is widely used for the growth of commercial-size SiC single crystals. A conventional SiC sublimation growth cell of Prior Art is shown schematically in FIG. 1. The process is carried out in a gas-tight chamber 10, which is usually made of fused silica. The chamber 10 includes a growth crucible 11 and thermal insulation 12 which surrounds the crucible 11. The growth crucible 11 is generally made of dense, fine-grain graphite, while the thermal insulation 12 is made from lightweight, fibrous graphite. Most commonly, heating is provided by a single RF coil 16, which couples electromagnetically to the crucible 11. However, the use of resistive heating is envisioned.
The crucible 11 includes SiC sublimation source 14 and a SiC single crystal seed 15. Most commonly, the source 14 (polycrystalline SiC grain) is disposed at the bottom of the crucible 11, while the seed 15 at the top, for instance, is attached to crucible lid 11a.
At growth temperatures (typically, between 2000° C. and 2400° C.), the SiC source 14 vaporizes and fills the crucible with vapors of Si2C, SiC2 and Si molecules. During growth, the temperature of the source 14 is maintained higher than that of the seed 15, leading to temperature gradients in the growth crucible, both axial and radial, on the order of 10-30° C./cm. The vapors migrate to the seed 15 and precipitate on said seed causing growth of a SiC single crystal 17 on the seed 15. The vapor transport in the crucible is signified by arrows 19 in FIG. 1. In order to control the growth rate and ensure crystal quality, sublimation growth is carried out under a small pressure of inert gas, generally, between several and 100 Torr.
As one of ordinary skill in the art of SiC sublimation growth would recognize, two technological factors are crucial to the crystal quality: the magnitude of radial temperature gradients within the growing SiC single crystal 17 and the shape of the crystal growth interface 20. Steep radial gradients cause stress and appearance of stress-related crystal defects, such as BPDs. A strongly curved growth interface, convex or concave, leads to the appearance of crude macrosteps on the interface, stacking faults, inclusions of foreign polytypes and other defects. A concave toward the source (hereafter 'concave') interface leads to the generation and rapid accumulation of various defects during growth. It is generally believed that a flat or slightly convex toward the source (hereafter 'convex') growth interface is the most conducive to high crystal quality.
It is commonly believed that the growth interface follows closely the isotherm shape: concave isotherms result in a concave interface 20, while convex isotherms yield a convex interface 20. Radial temperature gradients are positive when the temperature increases in the radial direction from the crucible axis toward the crucible wall. Positive radial temperature gradients produce convex isotherms. Radial temperature gradients are negative when the temperature decreases in the radial direction from the crucible axis toward the crucible wall. Negative radial temperature gradients produce concave isotherms. A zero radial gradient produces flat isotherms.
The conventional, single-coil SiC sublimation growth arrangement from FIG. 1 suffers from poorly controllable radial temperature gradients, especially when the crystal diameter is large. With increase in the diameter of the crucible 11 and the RF coil 16, electromagnetic coupling between crucible 11 and RF coil 16 becomes less efficient, thermal fields less uniform and radial gradients steeper. A SiC sublimation growth method aimed at reduction of the harmful radial gradients is disclosed in U.S. Pat. No. 6,800,136 (hereinafter "the '136 patent").
The SiC sublimation growth system disclosed in the '136 patent utilizes two independent flat heaters, namely, a source heater and a boule heater, which can be either inductive or resistive. The heaters are positioned coaxially with the crucible—the source heater is disposed below the source material, while the boule heater is disposed above the growing crystal. In order to reduce the radial heat losses, desirably to zero, the growth apparatus of the '136 patent comprises thick cylindrical thermal insulation with an option of an additional cylindrical heater disposed around the growth cell. Disadvantages of the growth system disclosed in the '136 patent include poor coupling of the flat coils to the cylindrical crucible, while disk-shaped resistive heaters obstruct heat dissipation in the axial direction, leading to strongly negative radial gradients.
An improved SiC sublimation growth method disclosed in US 2010/0139552 is shown in FIG. 2A. The growth apparatus includes cylindrical growth crucible 20 30 including SiC source material 21, a SiC seed 22 and a SiC single crystal 23 growing on the seed 22. The crucible 20 30 is positioned between two resistive heaters, top heater 28 and bottom heater 29, disposed coaxially with the crucible 20 30. The growth crucible 20 30 and heaters 28 and 29 are surrounded by thermal insulation (not shown).
The top heater 28 is ring-shaped with through hole 28a at the center. The bottom, cup-shaped heater 29 comprises two sections: ring-shaped section 29a with central hole 29b and cylindrically-shaped section 29c. The bottom heater 29 is disposed below and around the source material 21 included in the growth crucible 20 30.
FIG. 2B shows results of modeling of the growth cell from FIG. 2A. The isotherms 25 and the contour of a 3 inch diameter SiC crystal 23 were obtained by finite element simulation. The thermal field in the crucible 20 30 can be tuned by adjusting the current supplied to the heaters 29 and 28 to produce positive and shallow radial gradients within the crystal 23. Still, when this improved technique was applied to the growth of larger-diameter boules, such as 150 mm diameter boules, the growth interface was concave or wavy, such as concave at the center and convex at the periphery.
This is illustrated in FIG. 3, which depicts a growth cell similar to that of FIG. 2A, but scaled up for the growth of 150 mm crystals. The isotherms 35 and the contour of a 150 mm SiC crystal 33 growing on a SiC seed crystal 34 were obtained by finite element simulation. One can see that in spite of the isotherm convexity, the growth interface at the center of crystal 33 is concave.
A common practical approach to achieving the convex growth interface is in further increase of the isotherm convexity. However, strongly convex isotherms and associated with them steep radial gradients cause stress and crystal defects. It is postulated herein that the common perception of the growth interface following closely the shape of the isotherms is inaccurate, and that the interface shape is determined not only by the isotherms, but by the geometry of the vapor transport as well.
Generally, the temperature distribution within the SiC source material 31 is spatially nonuniform with the highest temperatures reached in the areas 36 adjacent to the crucible walls. During growth, the source vaporizes from these hotter areas 36, leaving carbon residue behind, while a denser SiC body 37 is formed in the colder top area of the source material 31. As a result, vapors from the source material 31 arrive predominantly at the periphery of the growing SiC crystal 33, as shown by arrows 34 34′ in FIG. 3. The vapor molecules adsorb on the growth interface and diffuse in the adsorbed state towards the colder center of the SiC single crystal 33 boule. With this geometry of vapor transport, the growth interface at the center of the growing SiC crystal 33 has a tendency to be concave, especially, when the boule diameter is large. Reference numbers 38 and 39 in FIG. 3 correspond to heaters 28 and 29, respectively, in FIGS. 2A and 2B.
The effect of the vapor transport geometry on the crystal shape is illustrated in FIGS. 4A and 4B, which show two 150 mm boule contours produced by finite element modeling of heat and mass transport. The thermal boundary conditions were chosen to produce zero radial gradients, that is, flat isotherms. In the case shown in FIG. 4A, the vapors were supplied to the SiC single crystal boule periphery, yielding a concave interface at the center of the boule. In the case shown in FIG. 4B the vapors were supplied to the SiC single crystal boule center, yielding a convex interface at the center of the boule.
Another common problem of SiC sublimation growth is carbon inclusions originating from the spent (carbonized) source.
While the prior art of SiC sublimation growth is broad and numerous, there is still a need for a process that can reproducibly yield high-quality SiC single crystals suitable for the fabrication of high-quality, large-diameter SiC substrates, such as 100 mm, 125 mm, 150 mm and 200 mm in diameter.

Large diameter, high quality SiC single crystals, method and apparatus


Various embodiments include memory devices and related methods. An embodiment includes circuitry including: a first inverter having a first inverter storage node, the first inverter cross-coupled to a second inverter having a second inverter storage node, wherein each of the first inverter and the second inverter has a reverse bit line controlled feedback transistor coupled between an pull-down transistor and a pull-up transistor, and wherein each pull-down transistor is further coupled to a ground; a first signal line coupled with the reverse bit line controlled feedback transistor of the second inverter; a second signal line coupled with the reverse bit line controlled feedback transistor of the first inverter; a first access transistor coupled with the first inverter storage node, the first signal line, and a third signal line; and a second access transistor coupled with the second inverter storage node, the second signal line, and the third signal line.

Aspects of the invention relate generally to the field of data processing. More particularly, various aspects of the invention relate to static random-access memory (SRAM) circuitry and read and write functions thereon.
Semiconductor memory devices retain data bits in memory and are useful in the fields of industrial and scientific subsystems. Compared with dynamic RAM devices (DRAM), containing at least a capacitor and a transistor, conventional SRAM device structure includes a six-transistor (6-T) cell having six metal-oxide-semiconductors-field-effect-transistors (MOSFETs). Wherein DRAM devices must be periodically refreshed, SRAM devices exhibit data remanence, where data is retained as long as power is being supplied.
Conventional 6-T SRAM devices store bits on four transistors that form two cross-coupled inverters. Storage cells have two stable states, denoted by a 0 and 1. Two access transistors coupled with each of the inverters serve to control access to a storage cell during read and write functions. Typically, a word line enables access to the cell. The word line controls the two access transistors, which in turn, control the connection to a bit line. Furthermore, SRAM cells have three different states: hold (the circuit is idle), read (data has been requested), and write (updating the contents of the cell).
While conventional SRAM devices provide benefits over DRAM devices, namely static memory and improved speed, conventional SRAM devices still face many challenges. The traditional 6-T SRAM cell faces limitations in read disturb, write margins, leakage, process variation, area, and half selection. For instance, a potential difference between the bit line and a storage cell during read functions can increase the threshold voltage (Vth) of the storage cell and flip the value in the storage cell. In another example, read functions on 6-T SRAM cells can cause nearby cells in the same memory block to change over time (known as a read disturb). If reading continually from the same cell, that cell will not fail, but other surrounding cells on subsequent reads will fail.

International Business Machines Corporation


An image forming apparatus comprises a fusing device for heating and fixing an unfixed image on a recording material while feeding the recording material, reversing device for reversing the recording material after passing the fusing device. The image forming apparatus operates in a first mode in which the recording material which passed the fusing device is ejected to an ejection section directly without being reversed, and a second mode in which the recording material which passed said fusing device is ejected to an ejection section after being reversed by the reversing device. A throughput of the recording material fed and/or the fusing temperature of the fusing device in the first mode being smaller or lower during at least part of an image forming process than in the second mode. With this image forming apparatus, the recording materials can be stacked in the ejection portion with improved quality and an excessive rise of temperature in the vicinity of the ejection portion can be avoided.

1. Field of the Invention
The present invention relates to an image forming apparatus utilizing electrophotographic techniques or electrostatic recording techniques, such as a copying machine, a facsimile and a laser printer provided with a heating type fuser.
2. Description of the Related Art
It has been customary in an image forming apparatus utilizing electrophotographic techniques, such as a laser printer, that commands related to printing and coded character and pictorial image information are received from external image processing equipment such as a computer, and when the coded information is converted into image information by a formatter or the like, pictorial images having density information, such as photographs, are binary-coded through known image processing, e.g., the dither matrix process or the error diffusion process, for conversion into the image information. After that, the image information is printed in an electrophotographic engine.
In one of the known electrophotographic engines, an electrostatic latent image is formed by writing an electrostatic image, based on the image information, on an electrophotographic photosensitive member or an electrostatic recording dielectric member which is uniformly charged beforehand; e.g., optically scanning over a photosensitive surface by a semiconductor laser. Also, one of the known developing devices for developing the electrostatic latent image performs development in such a manner, for example, that in a developing region where an electrostatic latent image carrier and a developer carrier are positioned to face each other with a small gap therebetween, a developer is moved from the developer carrier onto the surface of the electrostatic latent image carrier to form a developer (toner) image corresponding to the electrostatic latent image. The toner image thus developed is transferred onto a sheet of recording paper (material) by transfer means.
Subsequently, the recording paper onto which the toner image has been transferred is separated from the electrostatic latent image carrier and sent to fusing means, e.g., a known heating type fuser, where the toner image is fused and fixed to the recording paper.
As heating type fusers, hot-roller fusers have been widely used in the past, and film heating fusers have been used recently. In film heating fusers, particularly, no power is supplied to the fusers in the standby state and power consumption is held as low as possible. More specifically, a heat-fusing method using the film heating technique that a toner image is fused and fixed to a sheet of recording paper through a film interposed between a heater and a press roller, is proposed in Japanese Patent Laid-Open No. 63-313182, No. 2-157878, No. 4-44075, No. 4-204980, etc.
FIG. 7 schematically shows the principal part of a film heating fuser as one example of such heating type fusers. In FIG. 7, the fuser comprises a heating member (referred to as a heater hereinafter) 101 fixedly supported by a stay holder (support) 102, and an elastic press roller 110 held in pressure contact with the heater 101 while a fusing nip portion N is formed in a predetermined nip width, with a heat-resistant, thin film (referred to as a fusing film) 103 sandwiched therebetween. The heater 101 is heated and adjusted to a predetermined temperature upon supply of electric power. The fusing film 103 is a member in the form of a cylinder, an endless belt or a rolled web having ends, and is moved in the direction of an arrow a by the rotating force of not-shown driving means or the press roller 110 while closely contacting with and sliding over the surface of the heater 101 in the fusing nip portion N.
Under the condition where the heater 101 is heated and adjusted to the predetermined temperature and the fusing film 103 is moved in the direction of the arrow, when a sheet of recording paper P having a not-yet-fused toner image t formed and carried thereon as an object to be heated is introduced between the fusing film 103 and the press roller 110 in the fusing nip portion N, the recording paper P is brought into close contact with the surface of the fusing film 103 and transported through the fusing nip portion N along with the fusing film 103 while being held in sandwiched relation. In the fusing nip portion N, the recording paper P and the toner image t are heated by the heater 101 through the fusing film 103 so that the toner image t on the recording paper P is fused and fixed under heating. A part of the recording paper P having passed the fusing nip portion N is peeled off from the surface of the fusing film 103 and then further transported.
FIG. 8 shows the background art of the present invention and is a partial view of an image forming apparatus provided with the heating type fuser mentioned above.
In the image forming apparatus provided with the heating type fuser mentioned above, as the printing speed increases, ejected sheets of recording paper are stacked one above another in a paper ejection tray under the condition where the paper temperature still remains high and the charged static electricity is not yet attenuated.
Particularly, in the F/U (faceup) paper ejection mode in which the sheets of recording paper P are each ejected and stacked with the surface including the toner image t (i.e., the printed surface) facing up, as shown in FIG. 8A, the above tendency is more remarkable because the feed path of the recording paper is shorter and the recording paper is stacked more immediately after being fed out of the fuser than in the F/D (facedown) paper ejection mode in which the sheets of recording paper P are each ejected and stacked with the printed surface facing down, as shown in FIG. 8B. Therefore, when sheets of recording paper having relatively small thermal capacity and high volume resistivity, such as OHP sheets, are fed in the F/U paper ejection mode, the sheets of recording paper ejected to a paper ejection tray 130 still remain at such a high temperature that the sheets lack firmness and the toner is not solidified sufficiently, and still have the charged static electricity not yet attenuated. This may result in the OHP sheets not being stacked one above another satisfactorily because the adhesive force of the toner, the force of returned static electricity, etc. cause the sheets to stick to each other or curl.
Further, in the F/U paper ejection mode, because the sheets of recording paper are generally stacked on the tray 130 which is disposed downstream of a fuser 100 in the direction of pass of the recording paper and is opened as shown in FIG. 8A, paper ejection members 131 (131a, 131b) (such as paper ejection guides) of the fuser are exposed to the exterior such that the user may easily touch them. Nevertheless the paper ejection members are often heated excessively; hence the user feels unpleasant upon touching those members in such a condition.


A packaging unit includes a body delimited by a peripheral edge, and defining inside the peripheral edge at least one hollow compartment containing at least one liquid or semi-liquid product, and having an opening. A removable element is provided for obturating the opening in a leakproof manner. A groove forming a gutter is arranged substantially all around the opening of at least one of the compartments. The gutter is capable of receiving a quantity of the product which can escape from the compartment during its opening or during the manipulation of the packaging unit after it has been opened.

1. Field of the Invention
The invention concerns a packaging unit for a liquid or semiliquid product, preferably one capable of flowing under gravity. The invention is particularly suitable for readily oxidizable products of the type used in the field of hair care, such as reducing agents or coloring products.
2. Description of the Related Art
Such products are typically packaged in thermoplastic boat-shaped receptacles, having one or several compartments containing the product. The compartments are obturated in a leakproof manner by a removable cover which is generally heat sealed. Because of the highly oxidizable nature of certain products, such as those used in the field of hair care, it is necessary to fill the compartment (or compartments) to the top so that there is substantially no space between the free surface of the product and the cover. One of the problems associated with such packaging units relates to the fact that when tearing off the cover to allow access to the product, a portion of the product escapes from the compartment which, apart from the wastage of the product, produces stains, in particular on the hands of the user. Such a packaging unit is described for example in European Patent No. 206 583. The packaging unit there described takes the form of a compartmentalized container in which each compartment is closed by an individual sealing foil.
French Patent No. 2 451 322 describes a boat-shaped food receptacle with a rolled edge, having several compartments closed by a single stretched foil fixed to the rolled edge and forming a cover. The separating partitions between two contiguous compartments progressively rise from one edge in an arc in order to increase the tension of the foil forming the cover. A groove-shaped fillet is disposed in the zones between two contiguous compartments so as to retain the product particles which pass under the cover, in particular during transport, thus forming a leakproof seal between two contiguous compartments once they have been filled. Because of the localized disposition of the fillet or fillets (which is limited to the zones separating the edges common to two contiguous compartments), this arrangement does not resolve the problem mentioned above to the extent that the spattering of the product is not limited to these zones between two contiguous compartments. Moreover, the fillet is not separated from the product inside the compartments, so the groove can be completely filled during transport of the packaging unit, which renders it ineffectual when the tensioned foil is opened. In fact, once filled, the groove can no longer recover in any substantial way the product which may escape when the foil forming the cover is torn away. Moreover, after opening, the product contained in the groove situated between two contiguous compartments remains there, which poses problems when the consumer wishes to recover it. In practice, the product is "lost."
French Patent No. 2 447 322 describes a boat-shaped receptacle for food products, having several compartments covered by a single film. To increase the rigidity of the unit, a stamped recess is made in each of the corners of the receptacle. As in the preceding document, in the closed position of the receptacle, the recesses are not separated from the product (or products) contained in the various compartments.
German Patent No. 3 843 861 describes a thermoformed container fitted with a spout delimited by two hollows situated on either side of the spout, and whose presence only seems justified by the constraints of making the spout by thermoforming.
U.S. Pat. No. 4,863,036 describes a tub for a small dose of cream or milk, on the edge of which there has been provided a small raised tube situated above the filling level and communicating with the container. The combination in two stages of this small tube and an opening of a heat-sealed cover mainly allows the easy dispensing of the product via a small opening. Such a device is particularly unsuitable for the packaging of hair care products such as those mentioned above.
WO-94/27868 and U.S. Pat. No. 2,745,752 describe packaging units of the boat-shaped type with one or several compartments, used for the packaging of meat, butter or other food products of the same type. According to some embodiments, the compartment or compartments are surrounded by a channel whose function is to allow the cover to be cut all around the receptacle when a blade is inserted in the channel at the time of cutting the cover. The teachings of these documents do not resolve the problem of collecting the product which can escape from the compartments, either at the time of their opening or during the manipulation of the packaging unit after opening. Because of the nature of the packaged products, the above problem does not arise. Moreover, to permit the cutting described in these documents, a groove only slightly wider than the width of the blade and of an adequate depth is sufficient.

Packaging unit for a liquid to semi-liquid product


Embodiments are provided to simulate a quantum circuit. A system receives a quantum circuit (or its representation), generates a graph, and adds edges for each n-qubit of fusion to be applied. Costs are estimated or calculated for various paths of gate fusion between endpoints in the graph. One or more paths are selected, for example, the lowest cost path based on a Dijkstra algorithm evaluation. A unitary matrix for each gate fusion is then generated for simulating the quantum circuit. A simulation is performed locally or remotely based on the gate fusions along the selected one or more paths, and thus, improving the memory and processor performance of the simulation.

Simulation of quantum circuits and quantum computation is an important part of researching quantum computing algorithms, architectures, and devices. However, simulating quantum circuits of any significant breadth (i.e., qubit count) requires substantial memory and central processing unit (CPU) resources. For example, in a quantum computing simulation, all the quantum states must be loaded, updated, and stored for each gate being simulated. A state of n-qubits requires 2n complex values. Simulation of a quantum computing device typically load, update, and store all the complex values using a unitary matrix for each gate operation. The calculations and operations to perform the computations on such a broad array of unitary matrices requires significant memory and processing resources. Accordingly, the memory requirements and the time required to simulate an elementary circuit operation, grow exponentially with the number of qubits. For example, the simulation of a 26-qubit quantum circuit, using double-precision arithmetic, requires 1 gigabyte (GB) of memory. Indeed, the memory requirements follow an exponential curve, doubling with each additional qubit. Significant CPU resources are also required to perform the required computations and to manipulate the large data structures involved in simulating a quantum circuit. Accordingly, simulation of quantum circuits and computations can be challenging to simulate due to the size of the quantum computing systems, even with the use of powerful computers or computing systems.
When simulating quantum circuits of many qubits, known quantum simulators enable gate fusion. Gate fusion is where a simulator will rewrite a quantum circuit by combining operations on adjacent qubits before applying them. For example, instead of applying a Hadamard gate to 5 qubits, the simulator calculates a product of the 1-qubit gate unitary matrices and then applies one 5-qubit gate, e.g., using a nested loop and cache blocking. By fusing these operations, the simulator avoids having to iterate through the state vector operations multiple times This increases the operational intensity of the simulation, especially when running on a classical computer.
Known simulators rely on a user to manually specify when a simulator can use gate fusion. This is because gate fusion can be harmful to the simulation depending on the system's processing resources and memory and the number of threads available on the processor running the simulation. In addition, it can be difficult to determine how many operations and qubits should be combined when gate fusion is enabled. For example, employing gate fusion can cause a simulator to spend significant time evaluating futile optimizations for the gate fusion. Accordingly, the known simulation systems remain inefficient, for example, regarding how to implement gate fusion, memory utilization (e.g., cache hits and misses) and execution time (e.g., the time needed to perform the simulated computation).

Scheduling fusion for quantum computing simulation

INTERNATIONAL BUSINESS MACHINES CORPORATION


According to one embodiment, at demodulation of an A-phase burst pattern and a B-phase burst pattern arranged in a down-track direction so as to be different from each other in phase in a cross-track direction, the demodulated position of a magnetic head is calculated based on a sin component and a cos component in the A-phase burst pattern and a sin component and a cos component in the B-phase burst pattern.

At a magnetic disk device, burst data indicative of position information on a track is retrieved together with sector and cylinder numbers in servo data, and a magnetic head is positioned based on the information. Typical burst patterns include a null-type burst pattern and a phase pattern. The null-type burst pattern can be defined as "ns=2, Δφ=180°". The phase pattern can be generally defined as "ns=arbitrary number, Δφ<180°" and can be practically defined as "ns=1 or 2, Δφ≦90°, and a value which is a result of having divided 360° by a integer, where ns denotes an interval of magnetization change counted in STW step and Δφ denotes an adjacent phase difference. The phase pattern is demodulated mainly using an a tan(arctangent) demodulation technique. The null-type burst pattern is not demodulated using an a tan demodulation technique because of insufficient linearity, and thus is demodulated using a polynomial demodulation technique or the like so as to improve linearity.

Head position demodulation method and magnetic disk device