A method and device for transmission of wide beam in ultrasonic diagnostic systems is disclosed. The method comprises: dividing an aperture of an ultrasonic probe into N sub-apertures; laterally dividing a focus into N sub-focuses, wherein the N sub-apertures correspond to the N sub-focuses respectively, each sub-aperture has M array elements which all focus on a sub-focus corresponding to said sub-aperture; and N and M are integers larger than 2; exciting the N sub-apertures by a pulse generator, so as to obtain a laterally stretched transmit acoustic filed, wherein the transmit acoustic fields of the N sub-apertures focus on the corresponding sub-focuses respectively; and accumulating the acoustic fields of the sub-apertures to form an acoustic field of a wide beam covering acoustic fields of all receive lines. The present invention makes it possible for the system to transmit wide beams covering all receive lines, by dividing the aperture of the probe into a plurality of sub-apertures and accumulating the acoustic fields of the sub-apertures.

Fast imaging plays an important role in an ultrasonic diagnostic system in that it helps to provide a basis for more advanced techniques, i.e. a high data rate. With more information collected within a unit time, it becomes possible to perform finer image analysis and implement various techniques well. In particular, its advantages are as follows:
1. Improvement on 3D/4D Imaging
Both 3D and 4D imaging are on the basis of processing an extremely large amount of data. The imaging rate may be limited by the relatively low frame rate, which in turn poses limitations on 3D image speed.
2. Improvement on Blood Flow Imaging
The frame rate and image quality of blood flow imaging both have a direct influence on the interaction between a user and the system, which is an important criterion on the system level. In some systems, the frame rate of flow imaging is under that of C mode in some advanced systems. Thus the fast imaging is very important. To make it simple, the principle of fast imaging lies in generating the data of a plurality of scan-lines with the data received during one transmission, which helps to obtain the data of scan-lines in parallel. As a result, the frame rate of flow imaging can be increased significantly.
3. Improvement on Cardiac Imaging
For a heart moving fast, the frame rate is sometimes even more important than image quality.
4. Improvement on Image Quality
Many prior arts may be summed up as coming under different tradeoffs between image quality and frame rate, e.g.:
i) Synthesis aperture uses two transmissions to synthesize one scan-line with high signal to noise ratio.
ii) Composite imaging improves the image quality and reduces speckles by repeatedly transmitting composite scan-lines at different angles.
iii) It takes several transmissions to reduce the effect of longitudinal side lobes during the transmission of Golay code in coded excitation.
iv) In B mode imaging of heart, high frame rate is achieved by using low-density scan.
In the above-described examples, i)-iii) improve image quality at the expenses of frame rate, while iv) increases frame rate at the expenses of image quality. This contradiction between image quality and frame rate can be relieved by the fast imaging, which helps to implement these techniques in a better way.
5. Improvement on Heart-Related Techniques
In prior arts, many advanced systems are related to clinical techniques of heart, such as anatomic M-mode and the related analysis on the movement of heart. These techniques use the variation over time of the location of a certain part of heart in the image to conduct clinical evaluation and indicator calculation, in order to get a continuous image and a precise result. This imposes a critical requirement on the time resolution of the heart image, while the time resolution is actually the frame rate of image.
Multi-beam reception has become the focus of study for the purpose of improving frame rate. In multi-beam reception, a plurality of scan-lines is received during one transmission so as to reduce the time needed to generate one image frame, and thereby improve the frame rate significantly. A main problem associated with this technique is distortion, i.e., obtained scan-lines will be distorted if the transmit beam does not cover all the scan-lines. Therefore, an important issue concerned with multi-beam techniques is to make the transmit beam to cover a range of received scan-lines, i.e., a technique for transmission of wide beam.
A method of transmission of wide beam is disclosed in U.S. Pat. No. 6,585,648, titled "System, method and machine readable program for performing ultrasonic fat beam transmission and multilane receive imaging", wherein the transmit waveforms of a plurality of transmissions are accumulated to obtain a wide transmit beam. According to this patent, for a single beam, the transmission of each beam corresponds to different delayed transmit waveforms of a plurality of array elements; for various scan-lines, delays of transmit waveforms are different from each other. As a result, incorporating a plurality of transmission into one will accumulate a plurality of transmit waveforms of one array element and a composite waveform of the wide beam of the array element is obtained. Since the delays are different from each other, the transmit waveforms obtained at each array element are different from each other as well. The transmission result of such a waveform can be actually regarded as an accumulation of acoustic fields generated by single beam transmissions, thereby a wide beam is obtained.
A method for optimization of ultrasonic beam is disclosed in U.S. Pat. No. 6,282,963, titled "Numerical optimization of ultrasound beam path". The main principle of the patent is to obtain a wide beam by optimizing the transmit apodizing curves. This method mathematically models the transmit beam (taking into account the effect of the apodizing curves) and proposes criterions on evaluation of wide beam. An optimized transmit apodizing curve is obtained by optimizing math equations.
The above-discussed techniques have the disadvantages that wide beam is obtained by transmitting any waveform (U.S. Pat. No. 6,585,648) or by controlling the transmit apodizing curve (U.S. Pat. No. 6,282,963). However, the premise for implementing these methods is that a front end of an ultrasonic system can transmit arbitrary waveform, which is impossible for lots of ultrasonic systems that can transmit only excitation waveform of unipolar or bipolar levels.

Method and device for transmission of a wide-beam in an ultrasonic diagnostic system

Shenzhen Mindray Bio-Medical Electronics Co., Ltd.


A pressure testing apparatus can pressure test separately a first object having a width and a height and a second object having a width and a height. The first object can be, for example, a fiber optic repeater; the second object can be, for example, a fiber optic branch unit. The pressure testing apparatus has a testing vessel and an adaptor. The testing vessel has a chamber with an inner width corresponding to the width of the first object and a first gap. The adaptor can be selectably insertable into the chamber of the testing vessel and has an inner width and an outer width. The outer width of the adaptor corresponds to the inner width of the chamber of the testing vessel and a second gap. The inner width of the adaptor corresponds to the width of the second object and a third gap.

The present invention generally is related to pressure testing. More specifically, the present invention is related to an apparatus and method for pressure testing fiber optic systems that are to be used in high pressure environments, such as undersea.
Pressure testing of a container is typically performed by pressurizing the inside of the container with, for example, a liquid such as water or a gas and then detecting any leaks outside the container. This type of testing replicates an environment where the inside of the container is at a higher pressure than the pressure of the environment where the container is typically located.
For example, U.S. Pat. No. 4,577,487 issued to Dooley, describes a pressure testing system where a container is immersed in water and then the inside of the container is pressurized. Acoustic events are recorded by sensors fixed either to the wall of the container or to the walls of the water-holding vessel. Acoustic event measurements indicate the position of the leak in the pressurized container.
Where a container is typically located in an environment having a higher pressure than the pressure inside the container, however, pressure testing can more effectively replicate the environment by pressurizing the outside of the container and detecting any leaks inside the container. For example, a container located in an undersea environment will be subject to substantially higher pressure than the pressure inside the container where the container was sealed at a typical atmospheric pressure.
Known systems for pressure testing at high pressures are typically dimensioned to correspond to the object to be tested. If the pressure testing system does not correspond to the dimensions of the object to be tested, an excessive amount of time (e.g., hours) can be required to obtain the high pressures needed to perform the pressure testing. Because various object sizes may need to be tested, difficulty exists in using a pressure testing system dimensioned for one object to test objects of other dimensions.

Pressure vessel adaptor for testing of undersea fiber optic systems


A control valve includes an elastomeric flow tube, a plunger having first and second ends, and a pinch member connected to the first end of the plunger. The pinch member is situated adjacent the flow tube. A reference surface is positioned generally opposite the pinch member such that the elastomeric tube is squeezable between the pinch member and the reference surface to control fluid flow through the flow tube. A first guide spring is situated between the pinch member and the first end of the plunger, and a second guide spring is situated adjacent the second end of the plunger. A damper may be connected to the plunger. Further, a pressure containing member may situated about at least a portion of the flow tube.

1. Field of the Disclosure
The present invention relates generally to fluid flow and control, and more particularly, to a pinch valve having a reduced-friction guide mechanism.
2. Description of Related Art
A fluid flow control system generally consists of three components: a flow sensor, a control valve and a controller such as a proportional-integral-derivative (PID) controller. A typical fluid flow control system functions by changing the amount of opening of the control valve until the flow sensed by the flow sensor matches the desired, or set point flow. Often, the control valve must be adjusted by very small amounts to achieve the desired closeness of control.
Many industries such as semiconductor, pharmaceutical, and bio-technology experience fluid control problems due to the typically low flow rates, the use of abrasive chemical fluids, the use of corrosive chemical fluids, and the need for contaminant free, accurate, compact, and real-time fluid control and delivery systems.
For example, Chemical-Mechanical Planarization (CMP) is a critical process in the semiconductor industry that involves a process to flatten the wafer surface of a semiconductor by applying an ultra-pure fluid containing suspended solid particles and a reactive agent between the wafer surface and a polishing pad. In most applications, the polishing pad rotates at a controlled speed against the semiconductor to flatten the surface. Over-polishing the wafer can result in altering or removing critical wafer structures. Conversely, under-polishing of the wafer can result in unacceptable wafers. The polishing rate of the wafer is highly dependent upon the delivery rate of the fluid and the total amount of fluid delivered during a polishing operation.
Another process used in the semiconductor industry requiring accurate control of fluid flows and a contaminant free environment is the photolithography process. As is known in the art, photolithography is a process that applies a light sensitive polymer, known as resist, or photo resist, to the wafer surface. A photomask containing a pattern of the structures to be fabricated on the wafer surface is placed between the resist covered wafer and a light source. The light reacts with the resist by either weakening or strengthening the resist polymer. After the resist is exposed to light the wafer is developed with the application of fluid chemicals that remove the weakened resist. Accurate and repeatable resist delivery is essential to properly transfer the pattern. The resist must be contamination free as any dirt on the surface will cause a defect in the final pattern.
A modification of this process applies a host of new liquids to the wafer surface to create films that will become an integral part of the final semiconductor. The primary function of these films is to act as an insulator between electrical conducting wires. A variety of spin-on materials are being evaluated with a wide variety of chemical compositions and physical properties. The key difference between the lithography process and the spin-on deposition is that any defect in the film (such as a void, bubble or particle) is now permanently embedded in the structure of the semiconductor and could result in non-functioning devices and a financial loss for the semiconductor producer.
Both of these processes take place in a tool called a track. The purpose of the track is to apply a precise volume of fluid to the surface of a stationary or slowly spinning wafer. Additional chemical processing steps may be used to convert the liquid to the proper structure. After the liquid application, the wafer rotation speed is rapidly increased and the liquid on the wafer surface is spun off the edge. A very thin, consistent thickness of liquid remains from the center of the wafer to the edge. Some of the variables that affect liquid thickness include the resist or dielectric viscosity, solvent concentration in the resist or dielectric, the amount of resist/dielectric dispensed, speed of dispense, etc.
The track will also provide additional processing steps after liquid application that changes the liquid to a polymer using a bake process that also removes any solvent in the film. The track also controls the environment around the wafer to prevent changes in humidity or temperature and chemical contaminants from affecting the performance of the film. Track system performance is determined by the accuracy and repeatability of liquid delivered to the wafer surface in addition to minimizing defects in the film caused by voids, bubbles and particles.
The fluid control element is thus a critical component of such systems to insure proper delivery of the process fluids. A pinch valve may be used for the fluid control valve in such systems to provide an efficient, compact and high purity fluid control device. In particular, a solenoid-actuated pinch valve provides a cost-effective means for providing fine fluid control. Such valves typically have a guide mechanism that incorporates parts that slide against each other. With any sliding mechanism there is a finite amount of friction. Even if the sliding parts are made up of low friction materials, there will still be some friction. This friction can result in a stick-slip motion of the pinch valve, impacting the precision of flow control.
The present application addresses shortcomings associated with the prior art.


A combined toy capable of permitting a user to enjoy play full of unexpectedness and/or novelty. The combined toy includes a toy body constituted by a trunk, and attachments including a head, arms and legs detachably combined with the trunk. Combining between the trunk and the attachments is carried out using magnetic force. Also, a sound producing unit and a light emitting unit are provided in the toy body and/or attachments so as to be actuated when the attachments each are combined with the toy body.

This invention relates to a combined toy, and more particularly to a combined toy which includes a toy body and at least one attachment detachably combined with the toy body and is adapted to actuate a stimulus producing means for producing at least one predetermined stimulus appealing to the sense such as at least one of a sound producing unit and a light emitting unit arranged in at least one of the toy body and attachment when the attachment is combined with the toy body.
A conventional combined toy generally includes a toy body and a plurality of attachments, wherein a user combines the attachments with the toy body to assemble the combined toy into a predetermined configuration, to thereby enjoy play. Unfortunately, the combined toy is merely constructed so as to permit a user to assemble the combined toy, therefore, it fails to provide the user with play full of unexpectedness and novelty. Thus, the conventional combined toy readily loses its popularity with time.

Magnetically jointed toy for emitting stimuli


A photoresponsive device and a method of fabricating same, wherein the device includes semiconductor material, such as a cap region (14a), comprised of elements selected from Group IIB-VIA. A molybdenum contact pad (16) is formed upon a surface of the cap region, and a molybdenum ground contact pad is formed on a surface of a base region (12). A wide bandgap semiconductor passivation layer (20) overlies the surface of cap region and also partially overlies the molybdenum contact pad. A dielectric layer (22) overlies the passivation layer, and an indium bump (24) is formed upon the molybdenum contact pad. The indium bump extends upwardly from the molybdenum contact pad and through the dielectric layer. The dielectric layer is in intimate contact with side surfaces of the indium bump such that no portion of the molybdenum contact pad can be physically contacted from a top surface of the dielectric layer. The method eliminates the possibility of unwanted chemical reactions occurring between the In and the underlying contact pad metal. The method also deposits the contact metal before the deposition of the passivation and before a high temperature anneal, with windows to the contact being opened after the anneal so as to reduce localized stresses at the edges of the windows.

Known types of contact metals used for photovoltaic (PV) mercury-cadmium-telluride (HgCdTe) IR sensors include gold (Au) with a nickel (Ni) overcoat, for individual p-type contacts, and palladium (Pd) with a Ni overcoat for n-type ground (common) contacts. However, during high temperature storage both Au and Pd are known to diffuse into HgCdTe, causing a high density of dislocations, in the case of Pd, and shorting out the p-n junction, in the case of Au. Both of these unwanted diffusions result in degraded device performance and poor high temperature (bake) stability. Furthermore, the use of Au/Ni contacts for the p-type material and Pd/Ni for the n-type material requires two separate photolithographic and deposition processes. Also, the Au/Ni and Pd/Ni metal systems each have a coefficient of thermal expansion (CTE) that differs significantly from the CTE of HgCdTe. As a result, stress is applied to the HgCdTe during thermal cycling.
It is also known to employ an annealed, wide bandgap semiconductor passivation layer comprised of, by example, cadmium-telluride (CdTe) with the aforementioned contact metals. In that an as-deposited CdTe film contains residual crystal lattice stress, thermal annealing reduces the stress in the CdTe to approximately 10% of its as-deposited value. Annealing of the CdTe passivation is conventionally performed prior to depositing the contact metalization, and requires openings, or windows, to be etched through the passivation film before annealing. However, etching openings in the passivation film results in undesirable stress concentrations at the edges of the openings, thereby degrading the underlying HgCdTe material.
As a result, Dewar bake-out temperatures are typically limited to 100.degree. C. or less because of the instabilities in the surface passivation and/or the undesired diffusion of contact metal.
Furthermore, in that Hg is known to diffuse through a CdTe passivation layer during high temperature storage, a desired stoichiometric ratio of Group IIB-VIA material is not preserved within the radiation sensor device, over a prolonged period of high temperature storage.
A further problem that arises during the processing of conventional IR detector arrays relates to two unwanted chemical reactions that occur during an etch process that is used to remove oxide from indium (In) bumps, in preparation for hybridization of the array with other circuitry. By example, one suitable etch process is described in commonly assigned U.S. Pat. No. 4,865,245, issued to E.F. Schulte et al..
More specifically, it has been discovered that during the etch an electrochemical cell is formed between the In bump and the contact metal upon which the bump is deposited. The etchant, for example HCl, acts as the electrolyte. The result is that the etch rate of the In is increased in proportion to (a) the surface area of exposed contact metal, and (b) the difference in electronegativity between the contact metal and the In. As a result, the amount of In removed during the etch may vary over the surface of an array. The greatest In removal has been found to occur around the periphery of the array, where large amounts of ground contact metal are typically exposed. The degradation of the In bumps is especially troublesome for those In bumps around the outer periphery of the array, as these bumps are most prone to failure after prolonged thermal cycling of the hybrid assembly.
The second unwanted chemical reaction results in the formation of electrically conductive In-Te whiskers on the surface of the CdTe passivation layer.
The following patents are cited as relating to Group IIB-VIA photodetector fabrication techniques.
U.S. Pat. No. 4,439,912 (Pollard et al.) teaches the use of a molybdenum (Mo) layer that is overcoated with an Au/Ge layer to form connecting leads to a HgCdTe epitaxial detector array that is formed on a CdTe substrate. The leads are said to have excellent matches for the CTEs of HgCdTe and CdTe. Portions of the leads are masked prior to depositing a ZnS passivation layer. JP 60-3165(A) (Takeda) discloses, in the Abstract, the deposition, after a heat treatment, of a Mo electrode upon a (CdZnTe)(InTe) photoconductor layer. U.S. Pat. No. 4,766,084 (Bory et al.) teaches the deposition and etching of Cr and Au to form conductive pads. FIG. 2 illustrates a HgCdTe diode having an insulating layer that may be SiO.sub.2 and Si.sub.3 N.sub.4, SiO.sub.2 and ZnS, or CdTe and ZnS. In U.S. Pat. No. 4,206,003 T. Koehler describes a HgCdTe diode having a ZnS encapsulation layer that overlies an anodic oxide passivation layer. U.S. Pat. No. 4,132,999 (Maille, et al.) describes a PV detector having a HgCdTe substrate, a CdTe transition layer, and a masking layer comprised of ZnS, SiO.sub.2, SiO, or Si.sub.3 N.sub.4. After a heat treatment a window is opened to enable a doping impurity to be diffused into the HgCdTe. A protective layer of CdTe is then deposited over the masking layer and the window, Hg is diffused in through the window, an aperture is opened through the protective layer, and Cr or Au contacts are formed. U.S. Pat. No. 3,988,774 (Cohen-Solal et al.) describes a body of HgCdTe having an intermediate layer of HgCdTe or CdTe deposited thereon. Following a heat treatment windows are opened, dopants are diffused into the HgCdTe body, and Cr and Au contacts are formed. In U.S. Pat. No. 3,845,494, J. Ameurlaine et al. describe a HgCd-CdTe PV detector having Au electrodes formed on opposite faces. After forming the electrodes a Hg-impervious layer of ZnS is applied. In GB-2100927 A. Dean et al. describe a CdHgTe photodiode having a CdTe passivating layer. After a heat treatment, an Au electrode is formed through apertures in the CdTe.
What is not taught by these various U.S. and foreign Patents, and what is thus one object of this invention to provide, is a radiation sensor fabrication method, and a radiation sensor formed thereby, that deposits contact metal before the deposition of a wide bandgap semiconductor passivation layer or film, with windows to the contact metal being opened in the film after a thermal annealing step so as to significantly minimize localized stresses at the edges of the windows.
A further object of this invention is to provide a fabrication process that employs a contact metal selected to have a CTE that more closely equals that of HgCdTe, and to apply the selected contact metal prior to the deposition of a semiconductor passivation layer and a subsequent thermal anneal.
A still further object of this invention is to provide a fabrication process that significantly reduces or eliminates the possibility of unwanted chemical reactions degrading In bump interconnects during a hybridization process, thereby increasing the reliability of a resulting radiation detector hybrid assembly.

Bake-stable HgCdTe photodetector and method for fabricating same


In an embodiment, a system may include an aircraft clevis comprising two opposite sides and a longitudinal axis located between the two opposite sides. The longitudinal axis may be parallel to the two opposite sides. The system may include a slider positioned within the aircraft clevis and along the longitudinal axis. The system may include a clip configured to prevent the slider from rotating about the longitudinal axis by having at least a first portion of the clip coupled to one of the two opposite sides of the aircraft clevis and at least a second portion of the clip in contact with the slider.

Mechanical systems, such as an aircraft, automobile, or watercraft, often have components that are free to rotate Due to various forces occurring during operation of those systems, a component may rotate into another structural component of the system. The rotating component may damage or wear itself or the other structural component. As a result, the damaged or worn components must be replaced at a cost to the operator of the system. Moreover, workers must spend significant time inspecting for damage in areas known to have rotating components.

Apparatus and system for preventing wear to a component


Disclosed is a communications network for peripherals in a digital loop carrier transmission system. A broadcast STAR network is employed so that all peripherals receive any message which is broadcast by any of the peripherals. No peripheral broadcasts without clearance from the active communications hub. Two hubs can be provided to alternatively act as the active hub. Each peripheral includes a controller which transmits a request to send signal, multiplexes the request to send signal with an outgoing message, receives clear to send signals, and demultiplexes the clear to send signals from an incoming message.

This invention relates to digital loop carrier transmission systems and, in particular, to communication among common equipment peripherals within a remote and/or distant terminal.
In digital loop carrier transmission systems, peripherals within a remote or distant terminal are designated in terms of their function, and each may comprise a single circuit pack, a portion of a circuit pack, or several circuit packs within an equipment shelf or in different equipment shelves. For example, in the Subscriber Loop Carrier (SLC.RTM.) 2000 System, a metallic distribution controller (MDC) is located within a remote terminal and combines the functions of a transmit-receive unit (TRU) and a bank controller unit (BCU) in order to multiplex/demultiplex data and to control the other components of the remote terminal. Other peripherals which are part of the common equipment of the remote terminal include the system timing unit (STU) which handles the timing of the system, the virtual tributary unit (VTU) which acts as an interface to the optical portion of the network, and the provisioning and display control unit (PDC) which drives the display panel. These peripherals must be able to communicate with each other for the system to operate.
Typical communications systems for local area networks utilize a STAR configuration where each peripheral is coupled to a hub which controls transmission between the peripherals. Each peripheral could have a dedicated slot in which to send its messages, and these messages would be broadcast to all the peripherals (see, e.g., N. Abramson, "The Throughput of Packet Broadcasting Channels," IEEE Transactions on Communications, Vol. COM-25, No. 1 (Jan. 77), pp. 117-128). Such an approach was inefficient for a SLC.RTM. carrier system since a single central processing unit (CPU) at each peripheral would have to continually monitor incoming messages to see which messages were meant for that peripheral. Further, in many prior art STAR systems, it was necessary to detect collisions among messages from different peripherals and retransmit any messages that collided (see, e.g. R. M. Metcalfe et al., "Ethernet: Distributed Packet Switching for Local Computer Networks," Communications of the ACM, Vol. 19, No. 7 (July 1976), pp. 395-404 and U.S. Pat. No. 4,347,498 issued to Lee et al.). This requirement made the system unduly complex.
Other STAR network proposals have included the use of an alternate hub to take over communications in the event of a failure in the main hub (see, e.g., U.S. Pat. No. 4,701,756 issued to Burr).

Parsippany-Troy Hills Township, Morris County


When performing writing on a substrate applied with a resist by rapidly vibrating electron beam in a direction orthogonal to a radial direction of the substrate and X-Y deflecting the electron beam while rotating the substrate in one direction, a long element is written by scanning the electron beam with the middle position of a 2-bit signal length as the center position of the electron beam so as to completely fill the area of the writing length reduced by a predetermined ratio and an unwritten portion of predetermined width remaining on each side of the long element with respect to a final 2-bit signal length on a magnetic disk medium.

1. Field of the Invention
The present invention relates to an electron beam writing method and a fine pattern writing system for writing a fine pattern according to a desired uneven pattern when manufacturing an imprint mold, magnetic transfer master substrate, or the like for a high density magnetic recording medium, such as a discrete track medium, bit pattern medium, or the like.
The invention also relates to a method for manufacturing an uneven pattern carrying substrate, including an imprint mold, magnetic transfer master substrate or the like, having an uneven pattern surface formed through a writing step performed by the electron beam writing method described above. The invention further relates to a method for manufacturing a magnetic disk medium having an uneven pattern transferred thereto from the uneven pattern carrying substrate or imprint mold, and a method for manufacturing a magnetic disk medium having a magnetic pattern transferred thereto from the magnetic transfer master substrate.
2. Description of the Related Art
A magnetic disk medium is provided with a fine pattern corresponding to servo signal, address signal, and the like by an uneven pattern, a magnetic pattern, or the like. As for the method for forming such fine patterns, an electron beam writing method in which a pattern is written on a substrate applied with a resist by irradiating an electron beam thereon while rotating the substrate is proposed as described, for example, in U.S. Pat. No. 7,026,098 and Japanese Unexamined Patent Publication No. 2003-248981.
The electron beam writing method described in U.S. Pat. No. 7,026,098 is a method in which when, for example, writing a rectangular or parallelogram element constituting a servo pattern extending in a track width direction, the electron beam is deflected in a radial direction while being vibrated rapidly in a circumferential direction, thereby scanning the beam so as to completely fill the area of the element.
The electron beam writing method described in Japanese Unexamined Patent Publication No. 2003-248981 is a method in which when, for example, writing elements of a recording bit string with a constant length in a track width direction and different lengths in a track direction, the electron beam is rapidly vibrated in a radial direction with the amplitude thereof being adjusted as the substrate is rotated.
Further, as on/off writing method, a method in which pattern writing is performed by on/off irradiating an electron beam on a substrate applied with a resist according to the shape of a pattern while rotating the substrate, and shifting the substrate or electron beam irradiation unit by one beam width every rotation of the substrate in a radial direction is also known.
FIG. 6 shows an example fine pattern to be recorded on a magnetic disk medium, such as a hard disk. The concentric tracks in an annular region of disk-shaped disk 1 excluding outer circumferential portion 1a and inner circumferential portion 1b are made up of a plurality of sectors, each including preformatted area 2 and data area 5. Preformatted area 2 includes, for example, preamble, address signal, burst signal, and the like recorded typically by a magnetic pattern (fine pattern) or the like. Preformatted areas 2 are formed in elongated areas extending substantially radially in each sector from the center at regular intervals with respect to concentric tracks of disk 1. Note that preformatted areas 2 in this example are formed in curved radial continued in radial directions.
A portion of preformatted area 2 recorded on disk 1 includes address information recorded by a fine pattern (magnetic pattern) like that shown, as an example, in FIG. 7. The address information is formed of a fine pattern that includes short rectangular elements 3 and long rectangular elements 4 disposed on concentric tracks T1 to T4 in a mixed fashion.
As illustrated in FIG. 8A in an enlarged form, short element 3 in preformatted area 2 (magnetic pattern) recorded on a magnetic disk medium corresponds to 1-bit signal length "T", and long element 4 has a track direction length corresponding to 2-bit signal length "2T".
FIG. 8B illustrates fine pattern 12 to be written on substrate 10 of the present invention, to be described later, by an electron beam when, for example, producing a master substrate for performing magnetic transfer recording on the magnetic disk medium described above. Writing lengths of short element 13 and long element 14 formed on the master substrate for magnetically transferring short element 3 and long element 4 to the magnetic disk medium are reduced by a predetermined ratio with respect to 1-bit signal length "T" and 2-bit signal length "2T" on the disk medium respectively, resulting in "kT" for short element 13 and "2kT" for long element 14. This is influenced by magnetization characteristic at the time of magnetic transfer (transfer bleeding) and size variation at the time of etching, and reduction ratio k varies depending on various conditions.
For a 2-bit signal, long writing element 14 of the present invention is written as an integrated rectangular element having a length of 2kT centered on the middle position of 2-bit signal length 2T.
That is, the following have been found out. When long element 14 is formed by writing short elements 13 in adjacent 1-bit signal areas, an unwritten gap (T-kT) will present between adjacent elements 13. Then, if a magnetic transfer master substrate is produced with this element and magnetic transfer is performed on a magnetic disk medium using the master substrate, an area having a different magnetic pole according to the gap will present in the middle portion of long element 4 shown in FIG. 8A in a magnetic pattern formed on the magnetic disk medium after the magnetic transfer, which poses a problem of address information readout error. In order to record long element 4 with 2-bit length 2T on a magnetic disk medium as an integrated signal, it is necessary to write long element 14 as one element with reduced writing length 2kT like that shown in FIG. 8B.
The fine pattern representing an address signal shown in FIG. 7 is an example of address information in a hard disk pattern after Manchester conversion. The Manchester conversion converts binary numbers "0" and "1" to "01" and "10" respectively, thus having always "1". Whereas, in dibit conversion, binary numbers "0" and "1" are converted to "00" and "01" respectively. That is, "1" does not appear in the second digit, and instead "0" appears more.
When address information in a hard disk pattern is converted by the dibit conversion and formed in an uneven pattern on a magnetic transfer master substrate, flat portions corresponding to "0" appears more than convex portions corresponding to "1" because "0" appears more. Consequently, if magnetic transfer is performing by bringing the master substrate and a magnetic disk medium into close contact with each other and applying a transfer magnetic field, flat portions other than convex portions of the master substrate, which normally do not brought into close contact with the magnetic disk medium, are brought into close contact with the surface of the medium, causing a problem that an erroneous signal is magnetically transferred to the disk medium. In view of this, it is proposed that information including address information be converted by Manchester conversion, which causes more convex portions to appear in an uneven pattern on a master substrate, for pre-formatting a magnetic disk medium by magnetic transfer.
In a signal train converted by Manchester conversion, a binary number "01" is converted to "0110", resulting in that "1" corresponding to a convex portion of a fine pattern appears in succession. Thus, when writing such a portion in the fine pattern, the adjacent short elements must be written as one long element as described above.
In the mean time, exposure bleeding occurs in electron beam exposure writing on a resist in which a portion wider than the portion actually scanned by the electron beam reacts and is exposed. Therefore, it is also necessary to reduce the exposure width scanned by the electron beam shorter than the actual signal length on the magnetic disk medium.
The electron beam writing methods disclosed in U.S. Pat. No. 7,026,098 and Japanese Unexamined Patent Publication No. 2003-248981 do not mention about a method for writing a long element like that described above, and there is a demand for a method capable of writing such a long element on a predetermined position accurately and rapidly.
In particular, writing of a fine pattern having short elements and long elements in a mixed fashion as described above has a problem that a long element representing "11", which should be written integrally, is written separately, having a gap in the middle, thereby causing faulty transfer or erroneous signal.
In view of the circumstances described above, it is an object of the present invention to provide an electron beam writing method capable of writing a reduced element having a predetermined exposure width in a track direction without a gap in the middle thereof for a fine pattern having short elements and long elements in a mixed fashion.
It is a further object of the present invention to provide a method for manufacturing an uneven pattern carrying substrate, such as an imprint mold or a magnetic transfer master substrate, having a fine pattern accurately written by an electron beam, and a method for manufacturing a magnetic disk medium using the uneven pattern carrying substrate in which an uneven pattern or a magnetic pattern is transferred from the uneven pattern carrying substrate to the magnetic disk medium.

Electron beam writing method for magnetic recording medium


A cellular communication device including a housing having a front section and a rear section complementary to the front section such that the front and rear section align and mate together. A cavity is formed by mating of the front and rear section of the housing. An electronic circuit board having a microprocessor is located within the cavity. At least one of an accelerometer, a tilt sensor and a thermal sensor is operably connected to the microprocessor for detecting displacement of the cellular communication device from the ear of the user during communication.

1. Field of Invention
This invention relates in general to cellular communication devices, and in particular, to a cellular phone having usage mode detection and automatic speakerphone toggling.
2. Description of Background
Normal usage of a cellular phone requires the user of the cellular phone to hold the device to their ear. This provides quick access, private conversation, and for the most part, comfort. However, there are many reasons why a user may temporarily remove the cellular phone from their ear during the conversation, but not want to break the conversation. For example, a temporary need to use both hands may arise. Additionally, as cellular phones gain more functionality, a cellular phone user may wish to check their e-mail or find a file on their phone that is appropriate for the conversation or snap a picture to send to the other caller, etc.
Currently, there are alternatives for allowing the cellular phone user to perform other actions mid-conversation, however, these alternatives have drawbacks. For instance, headsets and earpieces are available for usage with cellular phones. Yet, many people do not use these devices since they require an additional attachment and additional setup time. Many people do not want to tote around an earpiece, nor do they want to plug it in and insert it into their ear for each call. Also, many people find these devices to be quite inconvenient.
Alternatively, many cellular phones possess speakerphone capability but this does not provide privacy for the user of the cellular phone. Most people located within the vicinity of the cellular phone user can hear the complete conversation of the cellular phone user and speakerphone usage is not appropriate in many situations.
Thus, it would be desirable to have a cellular phone that detects whether the cellular phone is being held to the ear of the user or removed from the ear of the user temporarily during conversation and, temporarily toggles between normal usage and louder speakerphone functionality.

Cellphone usage and mode detection and automatic speakerphone toggle

International Business Machines Corporation


A fabrication process includes a step of providing a substrate to be fabricated. A multi-layer antireflective layer is then formed on the substrate. A patterned resist having a thickness less than 850 nanometers is formed on the multi-layer antireflective layer and the substrate is fabricated using the patterned resist as a mask.

1. Technical Field
The present invention generally relates to a fabrication process and, more particularly, to a fabrication process using a thin resist. The fabrication process is usable, for example, in manufacturing processes for manufacturing semiconductor integrated circuits such as semiconductor memory devices.
2. Description of Related Art
In the fabrication of semiconductor integrated circuits such as semiconductor memory devices, optical photofabrication techniques may be used to provide desired patterns for circuit features. These techniques typically involve the controlled projection of actinic light (e.g., ultraviolet (UV) radiation) in order to transfer a pattern from a photolithographic mask onto a layer of light-sensitive material such as a resist deposited on a semiconductor wafer. The mask typically embodies a light transmissive substrate with a layer of light blocking material defining the patterns of circuit features to be transferred to the resist coated wafer. If a negative resist is used, then the projected exposure light passing through the mask will cause the exposed areas of the resist layer to undergo polymerization and cross-linking, resulting in an increased molecular weight. In a subsequent development step, unexposed portions of the resist layer will wash off with the developer, leaving a pattern of resist material constituting a reverse or negative image of the mask pattern. Alternatively, if a positive resist is used, the exposure light passing through the mask will cause the exposed portions of the resist layer to become soluble to the developer, such that the exposed resist layer portions will wash away in the development step, leaving a pattern of resist material corresponding directly to the mask pattern. In both cases, the remaining resist will serve to define a pattern of exposed material that will undergo subsequent processing steps (e.g., etching and deposition) for forming the desired semiconductor devices. The exposed material may, for example, be an insulator, a conductor, or a semiconductor.
Two important parameters of a lithography system are resolution and depth of focus. Resolution is a measure of the ability of the system to form separate images of closely spaced objects. Using a quarter micron (0.25.mu.) ground rule, the minimum resolution may be expressed using the conventional Rayleigh equation as: ##EQU1## where R is the minimum resolution; .lambda. is the wavelength of the exposure light (e.g., .lambda.=248 nanometers); NA is the numerical aperture (a lens design parameter) (e.g., NA=0.5); and K.sub.1 is a first empirical process parameter (e.g., K.sub.1 =0.5). K.sub.1 is a system process parameter which takes into account factors such as a finite resist thickness, partial coherency .sigma. (condenser lens NA/projection lens NA) of the optics, and pattern structures. In general, K.sub.1 is equal to about 0.5 to about 0.6 for deep ultraviolet (DUV) (.lambda.=248 nanometers) lithography.
An optical image degrades as the system is defocused, and the amount of defocusing that can be tolerated is called depth of focus (DOF). Increased DOF will minimize the adverse effects of slight deviations of the exposure tool from a best focus condition. The DOF may be expressed using the conventional Rayleigh equation as: ##EQU2## where DOF is the depth of focus; .lambda. is the wavelength of the exposure light (e.g., .lambda.=248 nanometers); NA is the numerical aperture (a lens design parameter) (e.g., NA=0.5); and K.sub.2 is a second empirical process parameter (e.g., K.sub.2 =0.7). To take into account a finite resist thickness d, the DOF may be expressed as: ##EQU3## where DOF is the depth of focus; .lambda. is the wavelength of the exposure light (e.g., .lambda.=248 nanometers); NA is the numerical aperture (a lens design parameter) (e.g., NA=0.5); d is the thickness of the resist; n is the refractive index of the resist at the wavelength of the exposure light (i.e., 248 nanometers); and K.sub.2 is a second empirical process parameter (e.g., K.sub.2 =0.7). See, for example, Arnold et al., Proc. SPIE 772, 21 (1987) and Boettiger et al., Microelectronics Engineering 23, 159(1994).
In advanced lithography processes such as DUV lithography processes, the reduction of ground rules to quarter-micron or below requires a methodology for achieving higher resolution capability. However, improved resolution is obtained at the expense of depth of focus. Thus, for example, the higher the NA of the lens being used, the more difficult it is to keep the whole wafer properly focused. Accordingly, it would be desirable to provide a methodology for achieving higher resolution capability without sacrificing or degrading any process windows such as depth of focus.

Fabrication process using a multi-layer antireflective layer


In a power supply device, the bridge circuit including a plurality of switching arms which is an inverse-parallel circuit of a semiconductor switch and a diode. The power supply device includes a control unit. The control unit switches the semiconductor switch such that a voltage v between AC terminals becomes a positive-negative voltage whose peak value is the voltage Vo between the DC terminals only during prescribed time periods before and after a point that has deviated from each zero crossing point ZCP of a current i by a prescribed compensation period φ and such that the voltage v between the AC terminals becomes a zero voltage during the other time periods, and sets the compensation period φ such that a time period during which the voltage v between the AC terminals becomes a zero voltage is the shortest.

1. Field of the Invention
The present invention relates to a power supply device that supplies power to a load by utilizing a magnetic coupling between coils.
2. Description of the Related Art
Methods to supply power to a load utilizing a magnetic coupling mutually between coils by electromagnetic induction include, for example, non-contact power supply. The principle thereof is forming a so-called transformer by magnetically coupling a plurality of coils through a space, and utilizing the electromagnetic induction between the coils, thereby exchanging power.
For example, the method includes arranging a primary side coil that corresponds to a power supply source as a power supply line in a rail shape, integrating a secondary side coil with a power receiving circuit to form a mobile object, and at the same time, making the primary side coil and the secondary side coil be opposed to each other. With this, it is possible to conduct a non-contact power supply to a mobile object that moves along the power supply line.
Here, FIG. 8 illustrates a non-contact power supply device described in Japanese Laid-open Patent Publication No. 2002-354711. In FIG. 8, to both ends of a high-frequency power source 100, a primary side power supply line 110 is connected as a coil. To the primary side power supply line 110, a power receiving coil 120 is coupled magnetically, and the primary side power supply line 110 and the power receiving coil 120 form a sort of a transformer.
Both ends of the power receiving coil 120 are connected to a pair of AC (alternating-current) terminals of a full-wave rectifier circuit 10 through a resonance capacitor Cr. The power receiving coil 120 and the resonance capacitor Cr form a serial resonance circuit.
The full-wave rectifier circuit 10 is formed by bridge-connecting diodes Du, Dv, Dx, and Dy. To a pair of DC (direct-current) terminals of the full-wave rectifier circuit 10, a constant voltage control circuit 20 is connected that controls a DC output voltage of the full-wave rectifier circuit 10 to be a reference voltage value. The constant voltage control circuit 20 is formed of a step-up chopper circuit that is formed, for example, of a reactor L1, a diode D1, a smoothing capacitor C0, and a semiconductor switch SW1. Further, to both ends of the smoothing capacitor C0, a load R is connected.
In FIG. 8, a control device that switches a semiconductor switch SW1 is omitted.
In the conventional technology disclosed in FIG. 8, a high-frequency current is applied to the primary side power supply line 110 by the high frequency power source 100 and the high-frequency power supplied through the power receiving coil 120 is input into the full-wave rectifier circuit 10 to convert it into DC power.
Generally, in this type of a non-contact power supply device, due to a change in a gap length between the primary side power supply line 110 and the power receiving coil 120, or a position gap of both, a voltage induced in the power receiving coil 120 changes. As a result of this, the DC output voltage of the full-wave rectifier circuit 10 changes. Further, characteristics of the load R also cause the DC output voltage of the full-wave rectifier circuit 10 to change. Accordingly, in FIG. 8, the DC output voltage of the full-wave rectifier circuit 10 is controlled to have a constant value by the constant voltage control circuit 20.
In the non-contact power supply device, the higher the frequency of the current supplied through a coil, the smaller an excitation inductance needed for transmitting a power, and a size of a coil or a core arranged at a periphery of the coil may be made to be small. However, in a power converter which forms a high frequency power source device or a power receiving circuit, the higher the frequency of the current flowing through the circuit, the larger an increase in a switching loss of a semiconductor switch, and a power supply efficiency lowers. Accordingly, it is common to set the frequency of the power supplied in a non-contact state to several [kHz] to several tens of [kHz].
In the non-contact power supply device illustrated in FIG. 8, in particular, a power receiving circuit in a subsequent stage of the resonance capacitor Cr has the following problems.
(1) Since the power receiving circuit is configured by the full-wave rectifier circuit 10 and the constant voltage control circuit 20, a size of an entire circuit becomes large and it causes an increase in installation space or cost.
(2) Since losses occur not only in the diodes Du, Dv, Dx, and Dy of the full-wave rectifier circuit 10 but also in the reactor L1, the semiconductor switch SW1, and the diode D1 of the constant voltage control circuit 20, these losses cause a reduction in a power supply efficiency.
As a conventional technology that solves the problems above, inventors have proposed a non-contact power supply device and a method for controlling the same as described in Japanese Laid-open Patent Publication No. 2012-125138.
FIG. 9 illustrates a non-contact power supply device described in Japanese Laid-open Patent Publication No. 2012-125138. In FIG. 9, 310 is a power receiving circuit. The power receiving circuit 310 includes semiconductor switches Qu, Qx, Qv, and Qy, diodes Du, Dx, Dv, and Dy, and a smoothing capacitor C0. The semiconductor switches Qu, Qx, Qv, and Qy are bridge-connected. The diodes Du, Dx, Dv, and Dy are connected in inverse-parallel to the switches Qu, Qx, Qv, and Qy, respectively. The capacitors Cx and Cy are respectively connected in parallel to the switches Qx and Qy of a lower arm. The smoothing capacitor C0 is connected between DC terminals of a bridge circuit being formed of these elements. A series circuit of a resonance capacitor Cr and a power receiving coil 120 is connected between AC terminals of the bridge circuit, and a load R is connected to both ends of the smoothing capacitor C0.
200 is a control device that generates a driving signal for switching the semiconductor switches Qu, Qx, Qv, and Qy. The control device 200 generates the above mentioned driving signal on the basis of a current i of the power receiving coil 120 detected by a current detection unit CT and a voltage Vo between DC terminals (DC output voltage) of the power receiving circuit 310.
In the non-contact power supply device, by controlling the semiconductor switches Qu, Qx, Qv, and Qy, a voltage v between the AC terminals of the bridge circuit is controlled to be a positive-negative voltage whose peak value is the voltage Vo between the DC terminals. A power supplied from a primary side power supply line 110 to the power receiving circuit 310 is a product of the current i of the power receiving coil 120 and the voltage v between the AC terminals. The control device 200 adjusts a phase of driving signals of the semiconductor switches Qu, Qx, Qv, and Qy on the basis of the voltage Vo between the DC terminals such that a control of the supplied power, that is, a constant control of the voltage Vo between the DC terminals, becomes available. Further, by configuring the power receiving circuit 310 using the bridge circuit which is formed of the switches Qu, Qx, Qv, and Qy and the diodes Du, Dx, Dv, and Dy, an operation of keeping the power constant is available even when the load R is a regenerative load.
According to this non-contact power supply device, the voltage Vo between the DC terminals may be controlled in a constant state by a phase control of the driving signals of the semiconductor switches Qu, Qx, Qv, and Qy without using a constant voltage control circuit, as illustrated in FIG. 8. In addition, the power receiving circuit 310 may be configured only of the bridge circuit and the smoothing capacitor C0. Therefore, a circuit configuration may be simplified, the size and the cost thereof may be reduced, and further, losses may be reduced by reducing the number of component parts, and consequently, a highly efficient and stable non-contact power supply may become available. In addition, by a charging/discharging action of the capacitors Cx and Cy, a so-called soft-switching is performed so as to reduce switching losses and further improve an efficiency.
However, in the conventional technology described in Japanese Laid-open Patent Publication No. 2012-125138, the current i of the power receiving coil 120 becomes a leading phase to a fundamental wave component of the voltage v between the AC terminals. Therefore, there is a problem that the input power factor of the power receiving circuit 310 reduces, and the problem invites an increase in a loss throughout the entire device and causes obstructions in further downsizing of the entire device.
In view of the foregoing, the applicant has proposed a non-contact power supply device in which an input power factor of a power receiving circuit has been improved (hereinafter referred to as a "first prior application invention") as described in Japanese Laid-open Patent Publication No. 2013-071432.
FIG. 10 is a circuit diagram of the first prior application invention. In FIG. 10, a power receiving circuit 320 includes semiconductor switches Qu, Qx, Qv, and Qy, diodes Du, Dx, Dv, and Dy, and a smoothing capacitor C0. The semiconductor switches Qu, Qx, Qv, and Qy are bridge-connected. The diodes Du, Dx, Dv, and Dy are respectively connected in inverse-parallel to the switches Qu, Qx, Qv, and Qy. The smoothing capacitor C0 is connected between a pair of DC terminals of abridge circuit being formed of these elements. A series circuit of a resonance capacitor Cr and a power receiving coil 120 is connected between a pair of AC terminals of the bridge circuit, and a load R is connected to both ends of the smoothing capacitor C0. Here, 100 is a high frequency power source, and 110 is a primary side power supply line.
On the other hand, a control device 200 generates driving signals of the switches Qu, Qx, Qv, and Qy on the basis of a voltage Vo between the DC terminals and a current i of the power receiving coil 120 detected by a current detection unit CT and outputs the driving signals. Although it is not illustrated, the voltage Vo between the DC terminals is detected by a well-known voltage detection unit such as a DC voltage detector.
Described next is an operation when power is supplied from the power receiving coil 120 to the load R in FIG. 10.
FIG. 11 illustrates a current i that flows through the power receiving coil 120, a voltage v between the AC terminals of the bridge circuit, a fundamental wave component v′ of the voltage v, and driving signals of the switches Qu, Qx, Qv, and Qy. The switches Qu, Qx, Qv, and Qy perform a switching operation with a constant frequency synchronized with the current i. In FIG. 11, a ZCP′ represents a zero crossing point of the current i. Described below is an operation in each time period (1) to (4) of FIG. 11.    (1) Time period (1) (switches Qu and Qy are turned on): The current i flows with a route of a receiving coil 120→a resonance capacitor Cr→a diode Du→a smoothing capacitor C0→a diode Dy→the power receiving coil 120. The voltage v between the AC terminals becomes a positive voltage whose peak value is a voltage Vo between DC terminals. During this time period, a smoothing capacitor C0 is charged by the current i.    (2) Time period (2) (switches Qx and Qy are turned on): The current i flows with a route of a receiving coil 120→a resonance capacitor Cr→a switch Qx→a diode Dy→the power receiving coil 120. The voltage v between the AC terminals becomes a zero voltage.    (3) Time period (3) (switches Qu and Qv are turned on): The current i flows with a route of a resonance capacitor Cr→a power receiving coil 120→a diode Dv→a switch Qu→the resonance capacitor Cr. The voltage v between the AC terminals becomes a zero voltage.    (4) Time period (4) (switches Qx and Qv are turned on): The current i flows with a route of a resonance capacitor Cr→a power receiving coil 120→a diode Dv→a smoothing capacitor C0→a diode Dx→the resonance capacitor Cr. The voltage v between the AC terminals becomes a negative voltage whose peak value is the voltage Vo between the DC terminals. During this time period, the smoothing capacitor C0 is charged by the current i.
Hereafter, operations are transitioned to a switching mode of the time period (1), and similar operations are repeated.
As is clear from FIG. 11, the control device 200 performs a switching control of the semiconductor switches Qu, Qx, Qv, and Qy. Consequently, the voltage v between the AC terminals is controlled such that the voltage v becomes a zero voltage only during time periods α before and after one of two zero crossing points ZCP′ of the current i that flows through the power receiving coil 120 and such that the voltage v becomes a positive-negative voltage whose peak value is the voltage Vo between the DC terminals during the other time periods. A power supplied from the primary side power supply line 110 to the power receiving circuit 320 is a product of the current i and the voltage v. Accordingly, the control device 200 adjusts the driving signals of the switches Qu, Qx, Qv, and Qy on the basis of a detected value of the voltage Vo between the DC terminals such that a control of the supplied power, that is, a constant control of the voltage Vo between the DC terminals, becomes available.
When this happens, as illustrated in FIG. 11, since a phase difference between the current i and the fundamental wave component v′ of the voltage v between the AC terminals becomes 0°, an input power factor of the power receiving circuit 320 may be set to 1.
Here, in the first prior application invention, when resonance frequency of the power receiving coil 120 and the resonance capacitor Cr completely coincides with a power source frequency, the input power factor of the power receiving circuit 320 becomes 1, but when the resonance frequency deviates from the power source frequency, the input power factor of the power receiving circuit 320 is decreased. The reason for that is described below.
FIG. 12 illustrates an input side equivalent circuit of the power receiving circuit 320 in a case in which the resonance frequency of the power receiving coil 120 and the resonance capacitor Cr deviates from the power source frequency. In FIG. 12, a voltage vin induced in the power receiving coil 120 is represented as an AC power source, and the reference numeral 400 denotes an impedance that corresponds to the power receiving circuit 320 and the load R. Generally, the other impedance to the load R can be ignored, and therefore the reference numeral 400 may be regarded as a pure resistance that corresponds to the load R.
Further, FIG. 13 illustrates operating waveforms of a current i that flows through the power receiving coil 120, an induced voltage vin of the power receiving coil 120, a voltage v between AC terminals of the bridge circuit, a fundamental wave component v′ of the voltage v, and driving signals of the switches Qu, Qx, Qv, and Qy.
As illustrated in FIG. 12, inductance of the power receiving coil 120 is assumed to be L[H], and capacitance of the resonance capacitor Cr is assumed to be Cr[F] similarly to a reference numeral of the component. Further, when the power source frequency is assumed to be fs[Hz], combined inductance Ls[H] of the inductance L and the resonance conductor Cr is defined by the expression φ.
                              2                                                              π                                                                          f            s                                          L            s                          =                              2                                                                          π                                                                                f              s                                    L                    -                      1                          2                                                                                π                                                                                f                s                                                          C                r                                                                        (        1        )
On the other hand, a resonance frequency of a resonance circuit being formed of the power receiving coil 120 and the resonance capacitor Cr is represented by the expression (2).
                              f          c                =                  1                      2                                                                          π                                                      LC                r                                                                        (        2        )
Accordingly, when fc=fs, Ls=0 is established, and when fc≠fs, Ls≠0 is established.
In addition, according to the control method illustrated in FIG. 11, a phase of v′ coincides with that of i. Therefore, when the current i of the power receiving coil 120 is represented as I sin ωt, v′ is represented as V′ sin ωt.
On the other hand, vin is represented by the sum of the fundamental wave component v′ of v and vL by the circuit illustrated in FIG. 12 so as to be represented by the expression (3).
                                                                                V                    in                                                                          (                                          ω                                                                                t                                        )                                                  =                                                                                v                      ′                                                                                (                                              ω                                                                                t                                            )                                                        +                                                            v                      L                                                                                (                                              ω                                                                                t                                            )                                                                                =                                                                                V                      ′                                                                                sin                                                                    (                                                  ω                                                                                t                                                )                                                                              +                                                            j                                                                    (                                                  2                                                                                π                                                                                f                            s                                                                          )                                                                                L                      s                                                            I                                                                                sin                                                                    (                                                  ω                                                                                t                                                )                                                                                =                                                                                V                      ′                                                                                sin                                                                    (                                                  ω                                                                                t                                                )                                                                              +                                      2                                                                                π                                                                                f                      s                                                                                L                      s                                                            I                                                                                cos                                                                    (                                                  ω                                                                                t                                                )                                                                                =                                                                                V                    a                                                                          sin                                                              (                                                                        ω                                                                                t                                                +                        θ                                            )                                                                                (                                                    V                a                            =                                                                    V                                          ′                                                                                2                                                        +                                                            (                                              2                                                                                π                                                                                f                          s                                                                                L                          s                                                                        I                                            )                                        2                                                                        ,                          θ              =                              arc                                                                                sin                                                        (                                          2                                                                                π                                                                                f                        s                                                                                L                        s                                                                                I                        /                                                  V                          a                                                                                )                                                                                )                                    (        3        )
When Ls=0, vin=V′ sin ωt is established, and a phase difference θ between vin and i(=I sin ωt) becomes zero, and an input power factor of the power receiving circuit 320 becomes 1. However, when Ls≠0, vin and i has a phase difference θ as illustrated in FIG. 13, and the input power factor is decreased.
In view of the foregoing, the applicant has proposed a non-contact power supply device described in Japanese Patent Application No. 2013-123810 (hereinafter referred to as a "second prior application invention"). The second prior application invention aims at improving an input power factor of a power receiving circuit even when Ls≠0, namely, when a resonance frequency of a resonance circuit being formed of a power receiving coil and a resonance capacitor does not coincide with a power source frequency.
A configuration of a circuit in the second prior application invention is similar to that of the circuit illustrated in FIG. 10, and described below is a power factor improvement operation according to the second prior application invention.
FIG. 14 illustrates operating waveforms of a current i that flows through the power receiving coil 120 in FIG. 10, an induced voltage vin of the power receiving coil 120, a voltage v between AC terminals of the bridge circuit, and a fundamental wave component v′ of the voltage v between the AC terminals of the bridge circuit, and driving signals of the switches Qu, Qx, Qv, and Qy.
In addition, FIG. 15 illustrates an input side equivalent circuit of a power receiving circuit 320 in this case, and the reference numeral 400 denotes an impedance that corresponds to the power receiving circuit 320 and a load R. Generally, the other impedance can be ignored for the load R, and therefore the reference numeral 400 can be regarded as a pure resistance that corresponds to the load R. The reference numeral 401 denotes a capacitive reactance component of v′.
In the second prior application invention, the control device 200 provides driving signals to the switches Qu, Qx, Qv, and Qy such that a middle point of a time period during which a peak value of v is 0 deviates from one zero crossing point ZCP in one cycle of the current i by a compensation period (angle) β. As a result, the input power factor of the power receiving circuit 320 is improved. According to these driving signals, the voltage v between the AC terminals has a waveform that is asymmetric with respect to the zero crossing point ZCP of i in which the voltage v is a zero voltage during time periods before and after the middle point (respectively referred to as "α") and the voltage v is a positive-negative voltage whose peak value is a voltage V0 between DC terminals during the other periods. Accordingly, a phase of v′ deviates from a phase of i. Here, when a time period β is given such that a voltage drop caused by the capacitive reactance component 401 of v′ illustrated in FIG. 15 compensates for a voltage drop vL in Ls, the impedance of the circuit apparently becomes a pure resistance. Accordingly, as the phase of i coincides with a phase of vin, the input power factor of the power receiving circuit 320 is set to 1.
Described next is a method for obtaining the time period β for setting the input power factor to 1. First, v′ is expanded by fourier series, and is represented by the expression (4).v′(ωt)=a1 cos(ωt)+b1 sin(ωt)  (4)
From FIG. 14, a1 and b1 in the expression (4) are obtained by the expressions (5) and (6), respectively.
                                                                        a                1                            =                                                                            1                  π                                                                                ∫                    0                                          2                                                                                π                                                                                v                                                                    (                                                  ω                                                                                t                                                )                                                                                cos                                                                    (                                                  ω                                                                                t                                                )                                                                                ⅆ                      ω                                                                                t                                                                                =                                                                                1                    π                                                                                ∫                      0                                              π                        -                                                  (                                                      α                            -                            β                                                    )                                                                                V                                                                                cos                                                                          (                                                      ω                                                                                t                                                    )                                                                                ⅆ                        ω                                                                                t                                                                      +                                                      1                    π                                                                                ∫                                              π                        +                                                  (                                                      α                            +                            β                                                    )                                                                                2                                                                                π                                                                                (                                                  -                          V                                                )                                                                                cos                                                                          (                                                      ω                                                                                t                                                    )                                                                                ⅆ                        ω                                                                                t                                                                                =                                                                            V                  π                                                                  {                                                            sin                                                                    (                                                  α                          -                          β                                                )                                                              -                                          sin                                                                    (                                                  α                          +                          β                                                )                                                                              }                                                                                =                                                                            -                                                            2                                                                                V                                        π                                                                  cos                                                                                α                                                                                sin                                                                                β                                                                        (        5        )                                                                                b                1                            =                                                                            1                  π                                                                                ∫                    0                                          2                                                                                π                                                                                V                                                                    (                                                  ω                                                                                t                                                )                                                                                sin                                                                    (                                                  ω                                                                                t                                                )                                                                                ⅆ                      ω                                                                                t                                                                                =                                                                                1                    π                                                                                ∫                      0                                              π                        -                                                  (                                                      α                            -                            β                                                    )                                                                                V                                                                                cos                                                                          (                                                      ω                                                                                t                                                    )                                                                                ⅆ                        ω                                                                                t                                                                      +                                                      1                    π                                                                                ∫                                              π                        +                                                  (                                                      α                            +                            β                                                    )                                                                                2                                                                                π                                                                                (                                                  -                          V                                                )                                                                                cos                                                                          (                                                      ω                                                                                t                                                    )                                                                                ⅆ                        ω                                                                                t                                                                                =                                                                            V                  π                                                                  {                                      2                    +                                          cos                                                                    (                                                  α                          -                          β                                                )                                                              +                                          cos                                                                    (                                                  α                          +                          β                                                )                                                                              }                                                                                =                                                                                2                                                                                V                                    π                                                                  (                                      1                    +                                          cos                                                                                α                                                                                cos                                                                                β                                                        )                                                                                (        6        )
On the other hand, from FIG. 15, v′ may be represented by the expression (7).v′(ωt)=vin(ωt)−vL(ωt)  (7)
When the input power factor is set to 1, the phase of i coincides with the phase of vin, and therefore when iin(ωt)=Iin sin(ωt) is assumed, vin(ωt)=Vin sin(ωt) is established. Accordingly, the expression (7) may be represented by the expression (8).
                                                                                v                  ′                                                                  (                                      ω                                                                                t                                    )                                            =                                                                                V                    in                                                                          sin                                                              (                                              ω                                                                                t                                            )                                                                      -                                  j                                                                                ω                                                                                L                    s                                                      I                                                                                sin                                                              (                                              ω                                                                                t                                            )                                                                                =                                                                                -                    ω                                                                                L                    s                                                      I                                                                                cos                                                              (                                              ω                                                                                t                                            )                                                                      +                                                      V                    in                                                                          sin                                                              (                                              ω                                                                                t                                            )                                                                                (        8        )
When putting VL=ωLsI, the expressions (9) and (10) are established by the expressions (4)-(6) and (8).
                              a          1                =                                            -                                                2                                                                                V                                π                                                  cos                                                                          α                                                                          sin                                                                          β                    =                      -                          V              L                                                          (        9        )                                          b          1                =                                                            2                                                                                V                            π                                                  (                              1                +                                  cos                                                                                α                                                                                cos                                                                                β                                            )                                =                      V            in                                              (        10        )
Accordingly, β and α at the time of setting the input power factor to 1 are obtained by the expressions (11) and (12), respectively.
                    β        =                              tan                          -              1                                (                      -                                          V                L                                                                                2                                                                                V                                    π                                -                                  V                  in                                                              )                                    (        11        )                                α        =                              cos                          -              1                                                      (                                          π                                                                                V                  L                                                            2                                                                                V                                                                                sin                                                                                β                                      )                                              (        12        )
Namely, even when the power source frequency does not coincide with the resonance frequency and Ls≠0, the control device 200 provides driving signals that have been calculated by using a and R obtained by the expressions (11) and (12) so as to drive the switches Qu, Qx, Qv, and Qy. As a result of driving the switches Qu, Qx, Qv, and Qy by these driving signals, the input power factor of the power receiving circuit 320 is controlled to be 1.
When other impedances have a great influence, for example due to a high wiring inductance, and the reference numeral 400 in FIG. 15 cannot be regarded as a pure resistance, a time period β is provided such that a reactance component included in the reference numeral 400 is also compensated for. As a result, the input power factor is set to 1.
In addition, when a waveform of v is the same as that in FIG. 14, the driving signals of the switches Qu, Qx, Qv, and Qy may be, for example, signals as illustrated in FIG. 16. Also in this case, by driving the switches Qu, Qx, Qv, and Qy by applying α and β obtained by the expressions (11) and (12), the input power factor of the power receiving circuit 320 can be set to 1.
However, the second prior application invention has the following problem.
Namely, in the second prior application invention, an induced voltage vin cannot be detected during the switching of the switches Qu, Qx, Qv, and Qy, and it is also difficult to calculate the induced voltage vin. Therefore, it is difficult to obtain a compensation period β for setting the input power factor to 1 from the theoretical expressions described above during the operation of a power supply device.

Power supply device with a resonant bridge circuit control unit