A dietary supplement for animals, comprising safflower oil, sunflower oil, olive oil, soya oil, cod liver oil, lecithin, natural flavors, herbs, garlic, and zinc. When fed to a dog or cat daily in a proper dosage, the supplement reduces or eliminates non-seasonal shedding and promotes healthy skin and a glossy, silky coat, without affecting the dog's or cat's natural shedding cycle and without causing any harmful effects. The composition also may be administered topically.

The present invention relates generally to compositions for keeping animals' skins and coats healthy. More specifically, the present invention relates to a dietary supplement for dogs and cats that prevents shedding out of season and promotes healthy skin and silky, glossy coats.
There are over 54 million domesticated dogs and over 63 million domesticated cats in the United States. The owners of these pets and other animals have had to cope with the problems associated with keeping the animals indoors and coming into frequent contact with the animals. Additionally, these pet owners deeply care for their pets and want to keep them as healthy and as beautiful as possible.
One of the problems pet owners often encounter is excessive amounts of pet hair clinging to clothes and fabrics and covering surfaces, including floors, carpets, and furniture. This is a result of shedding, the process by which many animals routinely lose their hair. New hair grows to replace that which is lost, so that the animals maintain a full coat.
Shedding is a normal process for certain animals and breeds, and should take place in those animals every spring. However, many individual animals shed throughout the year, not just during their natural shedding cycle. It is this unwanted, non-seasonal shedding that creates the year-round covering of pet hair found in the homes and on the clothes of pet owners.
Pet owners also are interested in keeping their pets healthy, and one aspect of that is healthy skin. Animals may be subject to myriad problems and diseases of the skin, including fungus infections and seasonal dry skin. Additionally, most pet owners want their pets to have a coat that is pleasing to the eye and to the touch. This is especially true for owners of show dogs, but is equally important to owners of household pets. It is desirable that pets have coats that look and feel healthy, glossy, and silky.
In view of the above mentioned problems and considerations, the present invention contemplates a liquid composition that supplements a dog's or cat's food daily, prevents or reduces non-seasonal shedding and promotes healthy skin and a silky, glossy coat. Prior products on the market have partially met this need but have not fully achieved the objective. As described below, the present composition solves the problems and is safe and all-natural, does not interfere with an animal's natural shedding cycle, and is highly palatable to dogs and cats.

Dietary supplement for preventing or reducing shedding by animals


An outline detection apparatus which detects an outline of a tooth in a dental image, including: a rectangular range specification device for estimating portions in the dental image as a tooth, gum, and background respectively, and specifying rectangular ranges with predetermined pixels in the positions estimated as the tooth, gum, and background; and a site estimation device for acquiring a characteristic quantity based on color information of the pixels in the rectangular ranges, finding a classification vector which maximizes the Fischer ratio based on the characteristic quantity, and estimating which of the tooth range, the gum range, and the background range, pixels other than the pixels in the rectangular ranges are positioned in according to comparison between a predetermined threshold value and an inner product between the classification vector and a pixel value vector based on color information on pixels other than the pixels in the rectangular ranges.

1. Field of the Invention
The present invention relates to an outline detection apparatus, an outline detection method, and a program thereof.
Priority is claimed on Japanese Patent Application No. 2007-069227, filed on Mar. 16, 2007, the content of which is incorporated herein by reference.
2. Description of Related Art
In the field of dentistry, medical treatments by the ceramic crown method and the like are performed. In this ceramic crown method, a crown (a prosthetic crown made of ceramics) with a color similar to that of the original tooth of a patient is fabricated, and then is placed on the tooth of the patient. In the medical treatment by the ceramic crown method, fabrication of a crown as a prosthesis is indispensable.
Here, to fabricate a crown, an application software for taking an image of a tooth of a patient to allow a dentist or a dental technician to correctly examine the color and shape of the tooth is required.
In such an application, a technology for correctly detecting the outline of a tooth is required. As a technology relevant to the present invention, there is disclosed a technology for detecting a boundary of a surface of biological mucosae in an image taken by an endoscope to detect the presence of biological mucosae with different descriptions. (see Japanese Unexamined Patent Application, First Publication No. 2006-166990)

Outline detection apparatus, outline detection method, and program thereof


A coherent optical receiver that receives an optical PSK-modulated signal includes optical elements that combine the optical PSK-modulated signal and an optical local-oscillating (LO) signal and splits the combined optical signals into multiple parts that have a predefined phase offset relative to one another. The receiver further includes at least one thyristor and control circuitry operably coupled to terminals of the at least one thyristor. The control circuitry is configured to receive the multiple parts of the combined optical signals and controls switching operation of the at least one thyristor according to phase offset of optical PSK-modulated signal relative to the optical LO signal.

1. Field
The present disclosure relates to optical communication systems and, in particular, to receivers of optical communication signals as well as optical and electro-optical components thereof.
2. State of the Art
Phase-shift keying (PSK) is a digital modulation scheme used in optical communication that conveys data by changing, or modulating, the phase of a reference optical signal (the optical carrier wave). PSK uses a finite number of phases, each assigned a unique pattern of binary digits. Usually, each phase encodes an equal number of bits. Each pattern of bits forms the symbol that is represented by the particular phase. The demodulator (or receiver), which is designed specifically for the symbol-set used by the modulator (or transmitter), determines the phase of the received optical signal and maps it back to the symbol it represents, thus recovering the original data. One form of demodulation requires that the receiver be able to compare the phase of the received optical signal to an optical local oscillating signal whose phase tracks the phase of the reference optical signal. Such a receiver is commonly referred to as a coherent PSK optical receiver. The coherent PSK optical receiver typically employs an optical phase lock loop to synchronize the phase of the optical local oscillating signal to the phase of the reference optical signal used by the transmitter.
Constellation diagrams are commonly used to represent PSK schemes. The constellation diagram shows points in the complex plane where, in this context, the real and imaginary axes are termed the in-phase and quadrature axes respectively due to their 90° separation. Such a representation on perpendicular axes lends itself to straightforward implementation. Specifically, the constellation points are typically selected with uniform angular spacing around a circle. This gives maximum phase-separation between adjacent points and thus the best immunity to corruption. They are positioned on a circle so that they can all be transmitted with the same energy. In this way, the moduli of the complex numbers they represent will be the same and the amplitude of the phase-modulated carrier wave does not change.
Two common PSK schemes are binary phase-shift keying (BPSK or 2-PSK) which uses two phases separated by 180 degrees, and quadrature phase-shift keying (QPSK or 4-PSK) or which uses four phases separated by 90 degrees, although any number of phases may be used. Since the data to be conveyed are usually binary (or digital) in nature, the PSK scheme is usually designed with the number of constellation points being a power of 2. The higher-order PSK schemes are typically labeled with the number of phases used for the respective scheme. Thus, a PSK scheme employing 8 phases separated by 45 degrees is commonly referred to as 8-PSK, a PSK scheme employing 16 phases separated by 22.5 degrees is commonly referred to 16-PSK, and a generic PSK employing M phases separated by (360/M) degrees is commonly referred to as M-PSK or M-ary PSK.
For the coherent BPSK optical receiver, the phase-aligned local oscillating signal can be split and mixed in the optical domain by a network of 3-dB fiber couplers for supply to corresponding photodetectors as shown in FIG. 1. This configuration converts the received optical signal to baseband electrical signals that represents the in-phase component and quadrature component of the received optical signal. These two component signals can be processed in the electrical domain by a signal processor in order to determine the phase of the received optical signal and map it back to the symbol it represents, thus recovering the original data.


The present invention relates, e.g., to in vitro method, using isolated protein reagents, for joining two double stranded (ds) DNA molecules of interest, wherein the distal region of the first DNA molecule and the proximal region of the second DNA molecule share a region of sequence identity, comprising contacting the two DNA molecules in a reaction mixture with (a) a non-processive 5′ exonculease; (b) a single stranded DNA binding protein (SSB) which accelerates nucleic acid annealing; (c) a non strand-displacing DNA polymerase; and (d) a ligase, under conditions effective to join the two DNA molecules to form an intact double stranded DNA molecule, in which a single copy of the region of sequence identity is retained. The method allows the joining of a number of DNA fragments, in a predetermined order and orientation, without the use of restriction enzymes.

Homologous recombination of linear double stranded DNA has long been known to be crucial for the repair of double stranded DNA breaks. In most organisms, the initiation of homologous recombination requires the action of an exodeoxyribonuclease. The single stranded DNA fragment generated can then pair with homologous sequence on other DNA molecules to complete the recombination. Although homologous recombination has been intensely studied, the mechanism involved is still not fully understood. The most efficient homologous recombination system has been discovered in Deinococcus radiodurans, which can survive 15,000 Gy of ionizing radiation, while doses below 10 Gy are lethal to almost all other organisms (Daly et al. (1996) J. of Bacteriology 178, 4461-4471). However, due to the complexity of the D. radiodurans genome, it is extremely difficult to pinpoint the proteins involved in the homologous recombination process.
Homologous recombination has also been demonstrated in the enterobacteria phage T7 system, the efficiency of which can be more than 50% (Lai et al. (1998) J. of Bacteriology 180, 6193-6202). T7 phage contain only 56 genes which encode 59 proteins, and therefore would be a more suitable system to isolate proteins involved in homologous recombination. In the T7 genome, genes that are involved in similar functions are normally clustered together. It has been reported that the early genes from gene 1.3 ligase to gene 6 exonuclease may be important in recombination (Lee et al. (1983) J. of Virology 48, 647-653; Lai et al. (1998), supra; Lai et al. (2000) Molecular Microbiology 36, 437-466; Yu et al (2001) J. of Bacteriology 183, 1862-1869). However, it is not known whether host proteins are also important in this process.


A DRAM or VRAM integrated circuit memory of the divided bit line design includes a bit line pair extending from a column decoder to a SAM. An N-sense amplifier divides the bit line pair into two pairs of bit halves. The N-sense amplifier is connected to each of the bit line halves through an isolation transistor. A P-sense amplifier is connected across each pair of the bit line halves. Since a P-sense amplifier is associated with each pair of bit line halves, the P-sense amplifier never has to pull through isolation transistors, and thus the isolation transistors can be high threshold transistors, eliminating the natural threshold mask step in fabrication. The two P-sense amplifiers separate the bit line voltages faster, thereby decreasing crossing current and saving power, and pull the bit lines to full high voltage levels.

1. Field of the Invention
The invention in general relates to integrated circuit memories and more particularly with the architecture of the sensing and write back circuits connected to the memory cells.
2. Statement of the Problem
Integrated circuit memories generally contain a two dimensional array of storage cells arranged in rows and columns. A common architecture is to connect all cells in a row to a common row line, often referred to as the "word line" and all cells in a column to a common column line often called the "bit line" or "digit line". In this architecture, the row line provides a signal which enables cells to receive or output a data signal and the column line provides the input or output line on which the signal is transferred. An individual cell is addressed via a row decoder that selects a row to be addressed and a column decoder which selects a column to be addressed, thereby selecting one particular cell at the corresponding row and column location. The cell is accessed by placing an enable signal on the row line in the row associated with the cell and reading or writing a signal on the column line associated with the cell.
Integrated circuit memories are also generally binary logic circuits in which information is stored and transferred as voltages representing complementary logic values that are alternately referred to as "true and false", "logic 1 and logic 0", or "logic high and logic low". Typically a voltage of 5 volts may represent the logic 1 state while a voltage of zero volts represents the logic 0 state. Because of the constraints of resistance, capacitance etc. the individual voltages input to or output on the column. lines by individual cells are usually at some intermediate voltage. Thus subcircuits are associated with the column lines of integrated circuit memories to pull the high voltage values up to, or as close as possible to, the full logic 1 voltage, for example 5 volts, and to pull the low voltages down to as close to the logic 0 voltage, for example 0 volts, as possible. These subcircuits are commonly referred to as sense amplifiers. A common architecture utilizes a separate pull down subcircuit, referred to as an N-sense amplifier, to pull the low signals down to the logic 0 voltage, and a separate pull up subcircuit, referred to as a P-sense amplifier, to pull the high voltages up to the logic 1 voltage.
The invention to be disclosed herein is particularly applicable to an architecture used in dynamic random access memories (DRAM) and video random access memories (VRAM). In this architecture the individual memory cell comprises a transistor and a capacitor connected in series. One side of the capacitor is connected to a reference voltage, and the other side is connected to the column line through the transistor. The gate of the transistor is connected to the row line. Information is stored in the form of charge on the capacitor, which charge is input and output via the column line and gated by the row line acting on the transistor gate. There are tens or even hundreds of such cells connected to each column line. The column lines are organized into pairs with one N-sense amplifier and one P-sense amplifier associated with each pair. The N-sense amplifiers and P-sense amplifiers are connected across the pairs, with one column line going low and the other going high when one of the pairs of lines is addressed. The attachment of the transistor gates to row lines is staggered with the cells associated with adjacent pairs of column lines belonging to different rows so that the transistor which gates one of each associated pair will be off when a cell On the other of the pair is being addressed. That is, when a particular cell is addressed, the column line it is attached to will go high or low, depending on the cells content; the other column line of the pair will go to the opposite logic value. When the read or write cycle is over, the pairs are shorted together, which quickly brings them to a mid-voltage level, resetting them for the next cycle. In this way the pairing of the lines results in faster cycling of the circuit as a whole. Since the connection of the cells to the row lines are staggered, the transistor gates associated with the one of the line pair that is not being addressed are always off and the information in the cells is not affected by the column line of the non-addressed cells going high or low. This architecture is referred to as "divided bit line sensing". A common arrangement of the various parts of the circuit in the divided bit line sensing approach is to locate the column decoder and DRAM input and output terminals at one end of the column lines, the P-sense amplifiers at the other end of the column lines, and the N-sense amplifiers at the center of the column lines thereby dividing each the column lines into two halves, one half of the line extending between the N-sense amplifier and the column decoder and the other half extending between the N-sense amplifier and the P-sense amplifier. In VRAM a sequential-access memory (SAM) port is connected to the column lines on the side of the P-sense amplifier away from the column decoder.
As is well-known, integrated circuit memories are generally mass produced by fabricating hundreds of identical circuit patterns on a single semiconducting wafer, which wafer is subsequently sawed into hundreds of identical dies or chips. The advantages of building integrated circuits with smaller individual circuit elements so that more and more circuitry may be packed on a single chip are well-known: electronic equipment becomes less bulky, reliability is improved by reducing the number of solder or plug connections, assembly and packaging costs are minimized, and improved circuit performance, in particular higher clock speeds. However, the smaller the size of the individual cell, the smaller the size of the individual electrical components in the cell, and the smaller the electrical signals associated with them. As more and more individual storage cells are placed onto a single chip, the length of the column lines connecting the individual cells to the amplifiers becomes longer and longer as compared to the individual cell size, and the capacitance associated with the lines becomes larger. This means that the signal transferred to the column line from an individual cell will become even smaller as the capacitance of the line absorbs the charge, and further that the time for developing a useful signal level on the line will increase. As is well known, speed is an important factor in such memories, since the faster the cells can be read, the faster is the computer of which the memory is a part, and the more operations the computer can do. Thus a number of enhancements have been made to DRAM and VRAM architecture to increase the signal level and amplifier response time. Several such enhancements are described in U.S. Pat. Nos. 4,748,349 and 4,636,987. The former patent describes a circuit which boosts the voltage on the row line and thus the gate of the gating transistors to a value above the high logic voltage of the circuit. This permits the full high logic voltage to be placed on the cell capacitor, since the threshold voltage drop across the gating transistor is eliminated. The latter patent describes an architecture in which each N-Sense amplifier is connected to each of the four column line pair halves associated with it through an isolation transistor. The gates of the isolation transistors are connected to a timing signal which isolates the N-sense amplifier from the column line pair halves on the opposite side of the N-sense amplifier from the row that is being addressed. That is, when the row being addressed is on, say, the left side of the N-sense amplifier, the isolating transistors connecting the N-sense amplifier to the left halves of the column line pair are on while the isolating transistors on connecting the N-sense amplifier to the halves on the right side of the N-sense amplifier are off. Thus the N-sense amplifier is connected to only half of the full column line during the time the N-sense amplifier signal is developing, which doubles the signal that the addressed cell develops at the N-sense amplifier. However, this architecture creates several disadvantages. First, for the cells on the opposite side of the N-sense amplifier from the P-sense amplifier, i.e., the cells between the N-sense amplifier and the column decoder, the voltage developed at the P-sense amplifier must pull through the two isolation transistors, thus the voltage for these accesses can never be pulled to the full logic 1 voltage, but is down V.sub.T, the threshold voltage of the isolation transistors. Further, in order to prevent the voltage drop V.sub.T from being too large, the isolation transistors have to be natural threshold N-channel transistors. Since all the transistors in the DRAM or VRAM integrated circuit except these are high impedance transistors, this architecture requires an additional mask step in fabrication process, i.e. a natural threshold transistor mask step. Thus there is a need for a DRAM and VRAM architecture that allows the voltage doubling at the N-sense amplifiers but does not decrease the voltage that can be developed on the opposite side of the N-sense amplifier near the column decoder, and can tolerate high impedance N-sense amplifier isolation transistors.
For many applications of integrated circuit memories, such as for portable computers and other battery powered intelligent devices, the amount of power available is limited. Thus it is important that sense amplifiers not only are fast and small, but also consume a minimum of power. During the period when the N-sense and P-sense amplifiers are separating the voltages on the column line pairs, the sense amplifiers pass through an intermediate state in which current flows through them from Vcc to ground. This current is called crossing current. The faster the column line pairs separate, the less crossing current. In sum, it would be highly desirable to have an integrated circuit memory architecture that not only increases the voltage developed at the P-sense. amplifiers and permits high impedance N-sense amplifier isolation transistors, but also pulls the column line pairs apart faster, resulting in less crossing current and more efficient use of power.
3. Solution to the problem
The present invention solves the above problems by employing dual P-sense amplifiers in the memory architecture. One P-sense amplifier is located on either side of each N-sense amplifier.
Two P-sense amplifiers are associated with each column line pair, one P-sense amplifier being associated with each pair of column line halves. Preferably, one P-sense amplifier is located at the SAM end of the column line pair and another P-sense amplifier is located at the column decoder end of the column line pair.
With the above arrangement of P-sense amplifiers, the P-sense amplifiers never have to pull through the isolation transistors. Therefore these transistors can be high impedance transistors just as the other transistors in the integrated circuit, and a fabrication step can be eliminated.
Moreover, since the invention provides independent control of the high voltage on both sides of the N-sense amplifier, both halves of the column lines can be charged all the way to the full logic 1 voltage. This full voltage can then be written to all the storage cells, on both sides of the sense amplifier, providing substantially improved performance over the previous art.
With the additional P-sense amplifier the separation of the voltages on the column lines is faster resulting in a higher speed of operation, and therefore a faster memory.
The faster separation of the column lines means that the sense amplifiers spend less time in the intermediate states in which crossing current flows, and thus there is less crossing current and more efficient use of power.

Integrated circuit memory with dual P-sense amplifiers associated with each column line


The present invention provides a method for notifying a primary wireless unit in a group calling plan that a wireless unit in the group calling plan has call activity. An MSC determines if there is call activity on a wireless phone. The MSC determines if the wireless phone is a member of a call monitoring group. If so, the MSC records call information related to the call activity and sends the call information to the primary wireless unit.

Wireless phones, sometimes referred to as cellular phones or mobile phones, allow users to make calls without being tied into a fixed location. Cellular calling plans give users access to a wireless communication network, and are customizable to provide various features and options to users.
One feature that has been provided by cellular service providers is group calling plans. Group calling plans allow multiple wireless phones to be associated with a single subscriber account. This simplifies billing and accounting, and allows the owner of the account to monitor phone usage.
One problem with current group calling plans is that the information is only provided on a periodic basis, typically monthly. This wait can lead to a significant response time delay when dealing with issues or problems with wireless phones that are part of the group calling plan.
Therefore, a need exists for a method that allows a primary user to receive information about usage of other members of the group calling plan without having to wait for the monthly detailed billing statement to arrive.

Method for notifying a primary wireless unit of group calling plan activity


A method of forming a tire (1) inside a forming mold (2) having an inner surface negatively reproducing the outer surface of the finished tire (1). The method provides for forming a second stage tread assembly (13) of the tire (1) in an annular housing (3b) defined by an annular body (3) constituting an outer portion of the forming mold (2), and by two auxiliary outer rings (47) fitted in releasable manner to the opposite axial ends of the annular body (3). The two auxiliary rings (47) are subsequently removed from the annular body for fitting the annular body (3), in place of the auxiliary rings (47), with two annular lateral plates (6) defining respective lateral portions of the forming mold (2).

1. Technical Field
The present invention relates to a tire forming method. In particular, the present invention relates to a method of forming a tire inside a forming mold, the inner surface of which negatively reproduces the outer surface of the finished tire, the tire comprising an inner carcass and a second stage tread assembly.

Method of forming a tire inside a forming mold


A method of mounting precious stones in an article of jewelry, typically an earring, which includes the steps of punching a recess in the article of jewelry which is hollow, positioning the stone in the recess, and heading over the edge of the recess to retain the stone.

This invention relates generally to the field of jewelry manufacture, and more particularly to an improved method for setting a cut stone in secure engagement within an article of jewelry.
In the prior art, it is known to position in a mold, and cast the article of jewelry around the periphery of the stone. This method results in a heavy solid casting, and additional soldering of an attaching post or ring.
A second known method is to form a hollow casting, and drill a passage corresponding to the diameter of the stone, inserting a hollow tube in the passage, and positioning the stone on the end of the tube prior to heading over the hollow casting. Subsequently, the posts or ring are soldered into position.


For automatic wiring of terminals of electrical apparatus, for example fluorescent lamp luminaires, a line or wire-laying tool is used which has a finger (31) on which a pressure element (37), movable between three positions I, II, III with respect to the finger, and the terminal, respectively, is retained. The pressure element presses a wire (20) in an insertion slit (12) of a slit blade insulation piercing connector SBIPC (11). The pressure element (37) has a cutter blade at an end surface, and further has two pressure sections (46, 47). One section (46) is used to effect a connection at the beginning of a wire run, or for through-wiring, and the other (47) is used to terminate the end of a wire line, and to cut the wire. The finger (21) is always outside of a contacting zone (3), thus permitting miniaturization of the terminal to a degree limited only by insulation requirements of air or creep paths between adjacent SBIPCs. The terminals can thus be fitted into a raster, and are formed with grooved extensions (16) to form wire retention and introduction slots.

U.S. Pat. No. 5,515,606, Albeck et al., assigned to the assignee of the present application, and the disclosure of which is hereby incorporated by reference, describes a method to wire electrical terminals of electrical devices, aggregates or assembled units or systems, which is particularly adapted to achieve high efficiency, reliable operation, and avoidance of erroneous wiring, or errors. The method can be used in general, but is especially suitable for wiring luminaires, especially fluorescent light fixtures, which have within the luminaire separate accessory apparatus, such as ballasts. The patent describes a method which permits complete automation of the wiring of such luminaires or, in general, electrical apparatus, aggregates, assemblies and systems. It permits elimination of preassembled, or precut lines, as well as wiring harnesses, since it permits direct association of the required wires with the device, or terminals the wires are to serve.
The method is carried out, by means of a position controlled mechanical wire placement element, hereinafter and for brevity, a wiring finger, in such a way that, first, the electrical device or system has terminal blocks or the like preassembled therein. The location of the fixture, as well as of the terminals, is fixed and determined in accordance with a positioning raster. By relative movement between the preassembled device, or system, and the wiring finger, a first connection terminal is brought in the operating region of the finger and is positioned with respect thereto in proper wire-laying orientation. The wiring finger then introduces one end of an electrical wire supplied, for example, from an external wiring supply, such as a supply spool, into a contacting zone of the first terminal. It is fixed in position at the same time when an electrical contact is effected. Further relative movement between the preassembled electrical device or system and the finger, along a predetermined path, results in positioning of the line, sequentially, to further terminals all within the operating range of the wiring finger, and properly oriented positioning of the finger relative to the next terminal. During this relative movement, the line is supplied to the finger with a suitable length corresponding to the line positioning path. The continuously supplied line is introduced, at any terminal, into a contacting zone. An electrical contact is made, and the position of the wire is fixed at the terminal. The wire may be cut or not; if not, a through-wired contact is made.
The line, which is so positioned, is cut at the final end in the region of the last terminal. The cut end of the line, as well as the terminal, are so constructed that the cut end is safely received in the terminal and protected against accidental contact. The line positioning element, that is for short, the finger, is so constructed that it has a positioning finger element projecting from a housing. A conductor duct is located within the finger element. A controlled feed for the wire is provided. The finger is controlled, for example, by an industrial robot, or automatic positioning system in accordance with a preprogrammed wiring path, which places the finger adjacent the respective terminal to be contacted. The contacting zone of the terminal is formed as a Slit Blade Insulation Piercing Connector—hereinafter for short SBIPC—and the line which is to make contact at the terminal is pressed into the slit of the slit blade connector.
To place the wire into the SBIPC, a pressure element is provided movably secured on the finger and movable transverse to the axial orientation of the terminal end of a wire guide duct in the finger. The pressure element can be moved between two positions, one being a quiescent or rest position, remote from the terminal end of the wire duct, and the other a working position in which it projects over a line extending from the wire duct at one side, or at least is in approximate alignment with the upper side of the exit opening of the wire duct.
A separately controllable knife blade is located between the pressure element and the finger element as such, which cooperate with the opening surface of the wire exit opening of the wire duct, to permit cutting off the wire at the last terminal end when the positioning path of the wire has been run through.
The terminals are so constructed that they retain all the terminals within a contacting zone, and are surrounded within a housing of insulating material. The housing is formed with at least one introduction slot, open at an end, to receive the line, and further includes the SBIPC, which has its insulation piercing slit oriented to the introduction slot. The upper end of the slit is open. The SBIPC is retained in the insulating housing part in a manner to ensure that accidental contact therewith is not possible.
The housing, at least in one side thereof, and adjacent the introduction slot has an extension in form of a groove-like recess or depression, the width of which is larger than the width of the introduction slot, and the dimensions of which are so determined that a free end of a line which made contact to the SBIPC can be received in this slot, or groove-like extension. The slot or groove-like extension, as well as the housing, is generally matched to the dimensions of the wire-positioning finger and of the pressure element thereof, so that this extension can carry out a dual function:
(1) It receives a cut end of the wire at the last terminal of the wire positioning path in such a manner that it is safely retained against accidental contact. This means that the blank end of the wire cannot be reached from the outside in accordance with standard testing procedures, or at standard testing probe.
(2) The extension functions as a guide groove for the positioning finger of the positioning tool as the finger is moved over the terminal connection, and upon pressing the wire into the SBIPC by the pressure element.
The second function of the groove-like extension or depression at the terminal requires a predetermined minimum width of the depression which is substantially larger than the diameter of the wire, including its insulation. This is due to the size of the positioning finger which engages into the extension. The walls adjacent this extension duct or groove are thicker than the outer diameter of the wire insulation of the wire which is placed by the finger and located in the guide groove. This thickness dimension must also be extended to permit for slight shifting of the wire in the guide groove.
If multi-pole terminals are used, a terminal block will have a substantial width, due to the width of the slit or groove-like extension or depression of the housing at any one terminal, which is of substantially greater width than that of the wire, including insulation, itself. Some minimum dimension could not be decreased below that which is given by the width of the positioning finger and the required wall thicknesses, which are established in view of the air and surface creep path necessary for effective insulation between poles or terminals.
There are many applications where it is necessary, for example, due to space reasons, to closely move together terminals of a terminal block, or, otherwise, to make the individual terminals narrower than it was possible while retaining the groove-like depressions or extensions of the housing to permit the positioning finger to engage therein. In actual practice, it is desirable that such a device or assembly might have connection terminals of the well-known type which have grooves or extensions capable of receiving the width or thickness of the positioning finger, but which also have narrower connection points. If such narrower connection points, for space reasons, are also required, it was not possible to completely automatically wire a luminaire, or other device independently and without change in tools or wiring apparatus, in other words, to completely automate wiring of such devices or apparatus, entirely independently of the special construction of the terminals.

Electrical terminal used for wiring fluorescent light fixtures, and the like


Methods and Apparatus including a packet selector are disclosed herein. The packet selector is configured to select and provide to a transmitter two or more packets, wherein at the time the two or more packets are provided to the transmitter, at least one of the provided packets is not definitely to be transmitted by the transmitter. Other embodiments are also disclosed and claimed.

Wireless communication systems such as, for example, wireless local area networks (WLAN's), often involve the transferring of data in packets from one point to another. The transmission of packets may be done by a packet selector that identified the next packet to transmit based on the priorities associated with the packets waiting to be transferred. The packet selector may then provide the packet to a transmitter which, in turn, attempts to transmit the packet. The packet selector then waits for an acknowledgement signal (i.e. a success or fail indicator) from the transmitter and identifies the next packet to transmit based on the result of the last attempted transmission.
However, the use of this feedback mechanism may introduce delay in transmitting packets and reduce the overall transmission data rate within a wireless network. That is, the overall transmission data rate within the wireless network may be sacrificed because the packet selector has to wait for an acknowledgement signal to be received or not received before being able to identify and send to the transmitter the next packet for transmission. Thus, there is a continuing need for better ways to transfer packets within a wireless network.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements.

Apparatus to speculatively identify packets for transmission and method therefor


A solar module has a plurality of solar panels framed within a frame member having side frame members connected to end frame members. Each side frame member and end frame member have a groove and a channel, and side frame members also have an elongated flange that raises up the solar panel a distance to allow cooling air to pass under the solar panel. Framed solar panels are connected to lengthwise support members having top, bottom and side channels, such as T-slots. These channels allow for easy adjustment and compensates for variability in the installation process. Each solar panel is connected to the lengthwise support members by way of legs. To connect adjacent solar panels to the lengthwise support members, a pair of legs, one long leg and one short leg, are stacked on top of one another and fastened to the lengthwise support member.

Solar panels (also known as solar modules, photovoltaic modules or photovoltaic panels) are a packaged, connected assembly of photovoltaic cells (also known as solar cells). Solar panels use light energy (photons) from the sun to generate electricity through the photovoltaic effect. Conventional solar panels are comprised of a substrate, and a superstrate with a plurality of solar cells laminated or sealed between the substrate and the superstrate. Often, the substrate and the superstrate are formed of a plane of glass, ceramic, plastic, composite or the like.
To achieve economies of scale and improve efficiencies, often a plurality of solar panels are used in an array. To further improve efficiencies in residential and commercial applications, a micro inverter is used in association with each solar panel. One challenge to using micro inverters is to achieve the greatest efficiency, the micro inverter should be positioned as close as possible to its associated solar panel.
To produce energy, solar panels are positioned where they are exposed to sunlight. A convenient place to mount solar panels is on the roof of structures. However, due to the angles of various roofing structures mounting solar panels is difficult and complex. In addition as the number of solar panels increases, so does the complexity of the installation. When micro inverters are used in association with each solar panel, this substantially complicates the installation. Furthermore, due to the nature of being positioned on the roof of a structure, the mounting structure must be rigid and durable enough to sustain high winds, such as in a hurricane or thunderstorm, without damage to either the solar panel or the roof.
While mounting a plurality of solar panels together increases the amount of energy that can be generated, mounting solar panels in tight proximity to one another has the unintended negative effect of limiting the air movement around the solar panels which causes the solar panels to heat up. As the temperature of the solar panels increases, the solar panels become less efficient. In addition, excessive heat can also reduce the useful life of the solar panels and cause premature failure. Furthermore, excessive heat is also damaging to micro inverters.
While there are a plurality of mounting structures for solar panels on the market, they tend to be heavy, expensive, complex, and difficult to install, among suffering from countless other deficiencies.
Therefore, despite the advances in solar panel technology, problems still remain. In particular, problems remain in mounting an array of solar panels on the roof of structures in an inexpensive, fast, simple and durable manner.
Thus, it is a primary object of the invention to provide a mounting structure and system for solar panels that resolves the problems of and improves upon the prior art.
Another object of the invention to provide a mounting structure and system for solar panels that is efficient to install.
Yet another object of the invention is to provide a mounting structure and system for solar panels that is inexpensive.
Another object of the invention is to provide a mounting structure and system for solar panels that is easy to use.
Yet another object of the invention is to provide a mounting structure and system for solar panels that is durable while being light weight.
Another object of the invention is to provide a mounting structure and system for solar panels that provides a secure and rugged attachment.
Yet another object of the invention is to provide a mounting structure and system for solar panels that improves and maximizes the efficiency and longevity of solar panels.
Another object of the present invention is to provide a mounting structure and system which allows for increased air to flow through and around the mounting structure and the solar panels mounted therein.
Yet another object of the invention is to provide a mounting structure and system that is convenient and efficient to assemble, install, adjust and use.
Another object of the present invention is to provide a mounting structure and system uses a minimum number of parts.
Yet another object of the invention is to provide a mounting structure and system that allows for easy removal and replacement of solar panels in an array.
Another object of the present invention is to provide a mounting structure and system that allows for adjustment between solar panels in an array.
These and other objects, features, or advantages will become apparent from the specification, drawings and claims.


There is provided a new and useful alarm system for use on a school bus having an ignition switch, a master switch, a rear door switch, the alarm system comprises a plurality of electromechanical circuits arranged so as to effect a resting state in which the system is inoperable, a stand-by state activated by actuating the ignition switch, a latching state from which the system may be armed, an armed state in which the system is operable, alarm means to indicate an alarm state, and a disarmed state in which the system is deactivated. There is also provided deactivation means positioned at a rear of the bus to deactivate the alarm system while in the armed state or the alarm state, wherein the alarm system is integral with the ignition switch, the master switch and the door switch of the bus.

In order to ensure that no children are left on a bus, such as a school bus, drivers are trained to walk to the back of the bus to look for children who may still be on the bus before locking it up at the end of a run. This can be done at the school bus yard, or en route to the yard, so long as it is done at a time when the driver believes that all of the children are off of the bus. It can even be done while the bus is running. For example, if the driver wished to pull off on the side of the road on the way to the yard and do the check at that point, the requirement would be met. The timing or location of the check is not crucial, so long as the check is done.
However, driving a school bus is a demanding task and at the end of a shift, the driver is often tired and anxious to get home. Thus, even the best drivers can sometimes forget to perform the crucial check for children left on the bus. In those unlikely circumstances, the trauma suffered by a child that was left on the bus after the bus has been parked at the school bus yard and locked up for the night would be immeasurable. The bus company would likely then face negligence lawsuits from the child's parents and the driver would more than likely be fired.
There thus exists a need for a system on the bus to remind the driver to walk to the back of the bus to perform the check. An audible or visual alarm system which sounds when the bus ignition is turned off would be sufficient, as long as it required the driver to walk to the back of the bus to deactivate the system. In consultation with bus drivers, however, it was found that it is not necessary to have a system which could only be deactivated when the alarm was actually sounding. Such a system would not permit the driver to perform the check at any point along the route with the ignition running. It was also found that the bus owners desired a system which could be tied in with the existing wiring of the bus to eliminate the need for time-consuming and costly modifications to the bus.
Another pressing concern to school bus operators in particular is to ensure that the rear door and any other emergency exits of the vehicle are in proper working condition. A recent coroner's inquest into the death of children trapped in a burning in the Province of Ontario found that the deaths were attributable in part to the fact that the rear door of the bus could not be opened. Consequently, one of the recommendations from the inquest was to require a regular inspection of the rear door of the bus. Of course, such an inspection requires the driver to walk to the back of the bus and manually operate the door. This is a third aspect of the existing need for safety systems on buses.
Attempts in the prior art to design such a system have failed on the two key points outlined above and would not satisfy the third aspect of the rear door inspection. Reference may be had for example to U.S. Pat. No. 5,128,651 of Heckart, issued Jul. 7, 1992, and U.S. Pat. No. 5,243,323 of Rogers, issued Sep. 7, 1993. Neither of these references provides a means to deactivate the system with the ignition running and Heckart in particular would require significant modifications to the existing wiring of the bus to be installed. Rogers is similarly deficient in that it is only activated by the ignition switch and not any of the other switches or existing systems on the bus.


In the method of producing smaller, sheet glass plates having a predetermined geometry and lateral dimensions in the millimeter range from a larger sheet glass plate, a joining material is imprinted on one side of the larger sheet glass plate in accordance with a joining zone geometry of the smaller, sheet glass plates. Dividing lines along which the smaller, sheet glass plates are separated are specified on the larger sheet glass plate. Then the smaller, sheet glass plates are separated along the dividing lines together with the imprinted joining material into individual sheet glass plates.

The invention concerns a method for producing small, sheet glass plates having a specified geometric structure and lateral expansions in the millimeter range by removing them from a larger sheet glass plate.
The invention further concerns such a larger sheet glass plate having dimensions in the centimeter range as a semifinished product for producing the small, sheet glass plates having lateral expansions in the millimeter range.
Small, sheet glass plates of the aforementioned type are needed in certain technical fields, in particular for the production of electronic components.
For example, small containers, among other things, that are closed completely or partially on at least one side by a sheet glass plate are used to house micro-and optoelectronic components such as vibrating quartz crystals, SAW filters, CCD components, the "electronic packaging". Housing covers made of sheet glass are also used frequently in the housing of micro-and optoelectronic components. The thickness s of these small sheet glass plates is typically in the range of 10 μm≦s≦500 μm. Sheet glass plates having the most diverse geometry (rectangular, circular, etc.) are used in this application. The edge length and/or diameter of such plates made of sheet glass typically measure only a few millimeters in size.
Small sheet glass plates are also used as structural components in the production of microelectronic and micromechanical components. It is made known in DE 196 49 332, for example, that a vibrating quartz crystal is positioned directly between two sheet glass plates and interconnected with them. Bonded structures of this type have a minimal height and are capable of being placed and contacted on a printed-circuit board or a base plate.
In this application of sheet glass as an element for closing a housing for micro-and optoelectronic components, as well as a structural element of microelectronic or micromechanical components, the bond is typically formed by means of adhesive bonding or soldering. In the case of soldering, metal or glass solder is used as the joining material. Glass solder is used in the majority of applications.
The production of small, sheet glass plates of this type is typically carried out according to the related art (Derwent abstract of JP 62-070241) by removing them from larger sheet glass plates. The separating procedure is carried out by means of abrasive cutting or boring using rotating diamond tools. At the same time, higher requirements are placed on the quality of the edges, since they have a decisive influence on the strength of the sheet glass plate.
The sheet glass plates are typically divided initially in the manner described previously and then subjected to the subsequent further processing steps (assembly and joining process). In the case of the joining technique currently used in many housing applications, the sheet glass plates are bonded with the housing by means of a soldering process. In the majority of applications, the soldering material is applied to the glass using a dispenser. The soldering material is typically applied in the edge region of the sheet glass plates and therefore usually forms a thin, closed, frame-shaped contour. Glass or metal solder is typically used. Another method of applying the soldering material to the joining zone that is also used to a certain extent in common practice is the use of presintered solder frames. In this application, the sheet glass plates and a free and likewise very thin, presintered solder frame made of glass solder must be positioned and partially fixed in position relative to each other and relative to the housing with which the sheet glass plates are to be bonded.
In the case of this further processing method, problems occur with handling and positioning due to the minimal lateral expansion, thickness and mass of the sheet glass plates, as well as the solder frame used. This handling problem occurs to a greater extent, in particular, when thin, free solder frames are used. On the one hand, the thin glass plates are comparably susceptible to breakage and, on the other, the ratio of gravitational force to the adhesive forces occuring during handling is low. In particular, lifting the individual sheet glass plates and the solder frame in defined fashion is difficult, so that the individual components must be handled manually in the majority of cases. This manual handling is time-consuming and personnel-intensive, which makes it cost-intensive. Moreover, waste due to breakage and contamination increases when this type of handling is used and during transport of the individual sheet glass plates.

Method for producing small, sheet glass plates and larger sheet glass plates as semifinished products for producing the former


A method of maintaining patient registration in surgical navigation includes: obtaining a patient position in a tracking system frame of reference, based on a fiducial marker array affixed in a first position relative to the patient; receiving an initial surface scan depicting the patient and the fiducial array; responsive to receiving an intraoperative image depicting the patient: obtaining a position, in the tracking system frame of reference, of the fiducial array affixed in a second position relative to the patient; receiving a secondary surface scan depicting the patient and the fiducial array; detecting a deviation in a position of the fiducial marker array relative to the patient between the initial and secondary surface scans; and applying the deviation to the position of the patient to generate an updated position of the patient in the tracking system frame of reference, based on the fiducial array affixed in the second position.

Navigation systems are employed in various surgical contexts, permitting surgical tools to be tracked during a procedure and displayed alongside both preoperative and intraoperative patient images, surgical planning data, and the like.
Such systems generally require that a patient's position be registered with a tracking system, permitting the patient to be depicted alongside tracked surgical tools, for example. Registration may be accomplished, for example, by affixing fiducial markers in a known position relative to the patient. However, the markers may need to be removed—for example, when repositioning the patient to obtain an intraoperative (e.g. magnetic resonance imaging, MRI) image of the patient, as well as when repositioning the patient for further surgical intervention after the intraoperative image is captured. Removal of the fiducial markers results in loss of patient registration, which can reduce the accuracy of intraoperative image capture, and may necessitate a time-consuming repetition of the patient registration process after the intraoperative image is captured.
Additionally, positioning the patient within an imaging device such as an MRI scanner typically requires manual verification and adjustment of imaging configuration to account for the patient's orientation within the imaging device. Such verification and adjustment can be time-consuming procedures.

Method, system and apparatus for maintaining patient registration in a surgical navigation system


A PLL circuit arrangement includes a first frequency divider connected to a reference frequency source, a second frequency divider connected to the output of an oscillator controlled by the output of a loop filter, a phase/frequency detector that detects phase/frequency differences between the two divider outputs, a charge pump between the detector and the loop filter, a controller providing a changeable divider ratio to the first and/or second frequency divider, and a regulating signal generator that changes the output voltage of the loop filter applied to the oscillator in a controlled manner in response to a change of the divider ratio. The signal generator preferably has inputs connected to outputs of the controller and the frequency dividers, and an output connected to the charge pump and/or the loop filter to accelerate the recharging thereof in response to a change of the divider ratio.

The circuit and method of the above mentioned general type forming the field of this invention are known from the published European Patent application EP 0 993 122 A1. To generate a control voltage for controlling the voltage controlled oscillator (VCO), this European publication provides an adder circuit, which adds a predetermined frequency-dependent voltage to the output voltage of the loop filter. Those measures aim to reduce the transient settling time or frequency pull-in time of the circuit in connection with a change of the frequency.
Phase regulating circuits, and particularly phase locked loops (PLLs) are utilized, for example, to generate defined signals with frequency synthesizers for mixers. For this purpose in transceiver systems, it is necessary that the rated or nominal frequency of the PLL output signal can be sharply varied within a short time. Thus, for example, in the context of the GPRS (Global Packet Radio Services) standard, it is required that a frequency jump of about 150 MHz at an average or mid-frequency of about 2 to 2.4 GHz is carried out within about 150 to 200 μs. This time in which the frequency is switched to a new frequency (allowing for a transient to settle out to the new frequency) is referred to as the settling time. The accuracy with which the new nominal selected or desired frequency must be established within this settling time amounts to a few kHz.
The basic function of a phase regulating circuit and particularly a phase locked loop (PLL) involves dividing a reference frequency of, for example, 13 MHz by a factor R (typically 65) in a frequency divider. As a result, a frequency of about 200 kHz will be established at the output of the frequency divider. In the assumed example case of a GSM application, this frequency defines the channel raster prescribed by the system. Moreover, a second signal FVCO is generated by a voltage controlled oscillator (VCO) at a frequency of about 2 GHz. This second frequency signal is divided by a divisor N in a second frequency divider. By means of the regulating loop of the PLL including the charge pump and the loop filter, the flank of the divided signal of the VCO is regulated in such a manner so that the two input signals of the PLL have the same frequency and a fixed phase relationship. The two frequency dividers can be programmed via a serial interface, so that the frequency of the VCO can be adjusted, for example in 200 kHz steps, through an adjustment or variation of the divisor N by which the output signal of the VCO is divided.
With a comparison frequency of 200 kHz, a respective comparison is carried out every 5 μs. The loop filter must ensure that this 200 kHz interference only leads to a small or minor modulation of the voltage at the input of the voltage controlled oscillator (VCO). If this is not the case, spurious signals at a spacing of 200 kHz from the carrier frequency arise in the output spectrum of the VCO. It is typically required that these spurious signals are damped at greater than 60 dBc (decibels below carrier). The result thereof is that the bandwidth of the loop filter is normally limited to about 10 to 15% of the comparison frequency. For GSM applications, this means that the bandwidth is limited to about 20 to 30 kHz.
Simultaneously with limiting the bandwidth, the above damping of spurious signals also determines the settling time that is determinative of the transient frequency settling or pull-in of the PLL after a programmed frequency change. For frequency changes in the range from 100 MHz to 150 MHz, this means that a transient frequency settling or pull-in cannot be achieved within 200 μs if the bandwidth of the loop filter is about 20 kHz. This problem cannot be solved by increasing the filter bandwidth, because then the spurious signals can no longer be adequately and reliably suppressed.
In this context it is known to use a fractional PLL instead of an integer or integral PLL. However, a concept, e.g. a circuit arrangement and a method, with a fractional PLL requires special circuit measures for compensating so-called "fractional spurs". In order to be able to further utilize the relatively simple concept of an integer PLL rather than a fractional PLL, National Semiconductor developed a so-called "FASTLOCK" architecture (LMX2330) in which the filter time constants are reduced at the beginning of the transient frequency settling or pull-in process of the PLL, in that a second resistor is temporarily connected parallel to a first resistor. In the final condition, the parallel resistor is again clamped off, so that the PLL once again operates with the normal small bandwidth.

Circuit and method for faster frequency switching in a phase locked loop


A dielectric enhancement fluid composition having at least one organoalkoxysilane and an acid catalyst having a pKA less than about 2.1 and a method for using the composition to enhance the dielectric properties of an electrical cable having a central stranded conductor encased in a polymeric insulation and having an interstitial void volume in the region of the conductor, the method comprising at least partially filling the interstitial void volume of the cable with the composition. The fluid composition may further include an organometallic catalyst and a corrosion inhibitor.

Restoration of the dielectric properties of in-service electrical power cables is well known. The general method comprises injecting a dielectric enhancement fluid into the interstitial void space associated with the conductor geometry of the cable. Typically, the injected fluid is an organoalkoxysilane monomer which subsequently diffuses radially outward through the polymeric insulation jacket to fill the deleterious micro-voids ("trees") which form therein as a result of exposure to high electric fields and/or adventitious water. The organoalkoxysilane can oligomerize within the insulation, the shields, and the interstitial void volume of the cable by first reacting with adventitious water. In the case of in-service cables, as defined below, water can be present in the conductor strands as well as the intermolecular spaces of the polymeric components and fillers associated therewith (e.g., carbon black for most conductor and insulation shields; clay for most rubber insulation formulations). Water can also reside in micro-voids formed during manufacture of the cable and those formed during aging (e.g. water trees and halo). Furthermore, water can also diffuse into the cable from the environment. Oligomerization of the organoalkoxysilane retards the exudation of fluid from the insulation and micro-voids of the cable. An early method of this type, wherein the dielectric enhancement fluid was an aromatic alkoxysilane, was described by Vincent et al. in U.S. Pat. No. 4,766,011. This disclosure teaches the optional inclusion of a "hydrolysis condensation catalyst" as a part of the treatment fluid formulation to promote the above-mentioned oligomerization. A variation of the '011 patent method, which employs a mixture of an antitreeing agent, such as an organoalkoxysilane, and a rapidly diffusing water-reactive component as the dielectric enhancement fluid, also teaches the inclusion of such a catalyst, albeit with less emphasis. This method has enjoyed commercial success for more than a decade (see U.S. Pat. No. 5,372,841).
However, even though the above patent references recognized the benefit of including a catalyst and the importance of preventing the exudation of the dielectric property-enhancing fluid from the cable, they only disclose the use of certain organometallic catalysts.

Acid-catalyzed dielectric enhancement fluid and cable restoration method employing same


Methods and apparatus are disclosed for assembling an electric machine. The electric machine includes a plurality of stator segment assemblies that are mounted inside of a housing of an electric machine. The stator segment assemblies are positioned around an outer surface of an assembly fixture. The stator segment assemblies are held to the assembly fixture using a magnetic field that is generated by the assembly fixture. The housing is press fit or hot dropped over the stator segment assemblies. If the housing is hot dropped, the housing is heated to cause the housing to expand. The housing is positioned over the stator segment assemblies while the housing is hot. The housing cools and contracts around the stator segment assemblies to form an interference fit with the stator segment assemblies and then the stator and the housing are removed from the assembly fixture.

This invention relates to electric machines and, more particularly to methods and apparatus for assembling a segmented stator for an electric machine.
Electric machines, such as motors and generators, generally include the same basic component parts. A motor housing encloses a stator and a rotor. Endbells position the rotor relative to the stator. The stator includes salient poles and slots between the salient poles. Winding wire is wound around the stator poles. A drive circuit is connected to the windings and generates a rotating magnetic field in the windings. The rotor includes rotor poles and rotates relative to the housing, the endbells and the stator due to the rotating magnetic field.
Improvements to the design of electric machines have led to more compact machines for a given torque output at reduced assembly costs. If the product is equipped with a motor that does not require additional torque, the outer dimensions of the motor and the product can be reduced without impacting performance. Alternately, the dimensions of the product can be kept the same with a motor providing increased torque and improved performance.
The torque density of machines has been improved through the use of improved magnets on the rotors, stators including segmented stator assemblies, increased slot fill, improved placement of the windings on the segmented stator, and optimized thermal dissipation. In addition to the design and material changes, the assembly processes have also improved.
Part of the assembly process for electric machines having a segmented stator involves securing stator segment assemblies to an inner wall of the housing. In the xe2x80x9chot dropxe2x80x9d process, the housing is heated and expands slightly. Expansion of the housing provides sufficient clearance to position the stator segment assemblies inside of the housing. After the housing is placed over the stator segment assemblies, the housing cools and contracts to establish an interference fit between the stator segment assemblies and the housing. In an alternate assembly process, the stator segment assemblies are press fit into the housing. Since the segmented stator typically includes several stator segment assemblies, it is difficult to hold the stator segment assemblies in position while the housing is hot dropped.
Complex assembly fixtures have been devised to locate and hold the stator segment assemblies while the housing is installed. The assembly fixture is often located on the radially outer surface of the stator segment assemblies and obstructs the placement of the housing during assembly. Other assembly techniques employ wires and/or springs to hold the individual stator segment assemblies together while the housing is installed. Oftentimes, the wire and springs fall off during this process which slows the assembly process and adversely impacts quality.
To decrease the time and cost that is required to assemble the electric machines, it is desirable to further improve the assembly process of segmented stator assemblies for electric machines.
A method of assembling a stator including a plurality of stator segment assemblies inside a housing of an electric machine according to the invention includes the step of positioning the stator segment assemblies around an outer surface of an assembly fixture. The stator segment assemblies are held against the assembly fixture using a magnetic field. The housing is then positioned over the stator segment assemblies. Thereafter, the housing with the stator secured thereto is removed from the assembly fixture.
In other features of the invention, the housing is heated to cause the housing to expand before the housing is positioned over the stator segment assemblies. Afterwards, the housing is allowed to cool and contract around the stator segment assemblies.
According to another feature of the invention, the assembly fixture has a generally cylindrical outer surface. The assembly fixture includes a magnet positioner and a plurality of permanent magnets that are held by the magnet positioner. The assembly fixture generates a magnetic field that has a radial magnetic field component that is higher than an axial magnetic field component. The higher radial magnetic field component holds the stator segments during assembly and the lower axial magnetic field component allow easy removal.
An assembly system for manufacturing a stator with a plurality of stator segment assemblies inside a housing of electric machine includes an assembly fixture that generates a magnetic field. A heater heats and expands the housing. The stator segment assemblies are positioned and held in place around the assembly fixture by the magnetic field while the heated and expanded housing is hot dropped over the stator segment assemblies. The housing cools and contracts to provide an interference fit between the stator segment assemblies and the housing.
In other features of the invention, the assembly fixture includes a cylindrical portion that is connected to a base. A sleeve is positioned on an outer surface of the cylindrical portion of the assembly fixture. The cylindrical portion includes a plurality of circular stacked laminations. Each of the stacked laminations includes a plurality of radial slots. The radial slots of the laminations are aligned and receive permanent magnets. Alternately, the assembly fixture includes an electromagnet that generates the magnetic field.
Other objects, features and advantages will be apparent from the specification, the drawings and the following claims.

Method and apparatus for constructing a segmented stator


An elevated feeder or framework holds the round bales of feedstock off the ground while providing a convenient height for the livestock to feed from. The bale feeder is made by rigidly connecting tubular elements, of the same or different diameters together, at any angle, without the use of special fasteners. The elevated feeder holds the bales with the flat ends in a position that is the most convenient for the livestock to consume the feedstock. The elevated feeder keeps the feedstock bales off the ground by supporting the feedstock on an adjustable, flexible mesh bale support, with openings to permit rain and water to drain away from the feedstock. The mesh bale support length is adjusted by moving the mesh support clamping bars closer to or farther away from the ends of the mesh raises or lowers the bale to accommodate the feeding height of the livestock being fed.

Hay that was once formed into relatively small rectangular bales is now typically formed into larger round bales typically weighing 800 to over 1000 pounds. On a farm, these bales are lying in the field where they were harvested, with their axis horizontal (parallel to the ground). Typically they are moved with a farm tractor having a front end loader attachment fitted with a spike which enters one of the flat ends of the bale, so it can be lifted off the ground before moving it to another location.
Several types of round bale feeders which surround a bale either on the ground or on a raised platform are also available from suppliers. These are used to contain the bale during the feeding of animals such as horses, cattle or sheep. Many of these are designed to accept a round bale that has been flipped from the horizontal axis onto one of its flat ends so that the axis is now perpendicular to the ground. This not an easy task and requires the hydraulics of a tractor or other apparatus to grasp the horizontal bale and rotate it 90 degrees, before depositing it onto a feeder.
A round bale feeder for horses is described in U.S. Pat. No. 6,789,504 B1 of O'Neill. It is formed of several rings spaced apart by straight members and welded into a stand with a horizontal axis and raised on a base which spaces it from the ground. It accepts round bales from either end after a door is opened. It does eliminate the need to rotate the round bale 90 degrees prior to loading into the feeder. The chore of loading the feeder of O'Neill must be performed precisely by an experienced person since the alignment of a spiked round bale on a front loader requires skill in guiding it into the enclosure formed by the several rings. This is especially problematic considering that round bales can be more than five feet in diameter, and may not be perfectly round due to the settling of the heavy round bale. The situation is further hampered by poor visibility around the bale, for the equipment operator moving the suspended hay bale. Only larger diameter rings on the feeder, which add material bulk and weight to the feeder, ameliorate some of the loading problems.


A training apparatus 1000 using a method of decoding nerve activity includes: a brain activity detecting device 108 for detecting brain activity at a prescribed area within a brain of a subject; and an output device 130 for presenting neurofeedback information (presentation information) to the subject. A processing device 102 decodes a pattern of cranial nerve activity, generates a reward value based on a degree of similarity of the decoded pattern with respect to a target activation pattern obtained in advance for the event as the object of training, and generates presentation information corresponding to the reward value.

Recently, training systems for training subjects/trainees utilizing the technology of computer graphics (CG) such as virtual reality (VR) are available. Among such systems, some conduct training while measuring biological reaction of a subject. A training supporting apparatus disclosed in Patent Literature 1 detects, as the biological reaction of the subject, an active region of his/her brain using near infrared light, to assist rehabilitation and image training of a subject with disabilities. Patent Literature 1 is hereby incorporated by reference in its entirety. The training supporting apparatus measures an active region or regions of the subject's brain while the subject is working on a calculation problem or a memory task imposed as a training material; after the end of training, the response of the subject in the training and the record of measured brain activities are studied together to confirm the effectiveness of the training. Patent Literature 2 discloses a training system that always keeps an optimal training scenario in accordance with the biological reaction of a subject during training. Patent Literature 2 is hereby incorporated by reference in its entirety. Patterns of active parts of the brain measured by fNIR (Functional Near Infrared Spectroscopy), fMRI (Functional Magnetic Resonance Imaging), PET (Positron Emission Tomography) or the like are described as the means for measuring biological reaction.
Such a technique of scientifically grasping physiological indexes that would not otherwise be sensed and feeding these back to enable perception by the subject is referred to as "bio-feedback."
Though conventional bio-feedback sometimes utilize biological information such as pulse and breath, it mainly involves human brain wave outputs, converted to visible image or audible sound and output to humans. Through bio-feedback as such, a subject can grasp the state of his/her brain waves on real-time basis. Therefore, bio-feedback is helpful for the subject to control the state of his/her own brain waves.
By way of example, bio-feedback is utilized for treating abnormal cardiac rhythm, headache, autonomic dysregulation and high blood pressure and, in addition, it is utilized for mental training in sports.
As a technique of applying bio-feedback to rehabilitation, Patent Literature 3 discloses a rehabilitation assisting apparatus. The apparatus is for patients suffering from functional impairment or brain dysfunction. The apparatus measures conditions of a rehabilitating patient, and evaluates training contents. The apparatus detects the state of patient's feet using a force sensor or a position sensor, drives thighs, knees and feet joint driving portions to enable coordinated operations of two lower limbs. The apparatus presents the timing of motion of the healthy foot or impaired foot as an image, sound or vibration to the subject, and thereby supports effective gait training.
Operating a switch or a remote controller of electric appliances, for example, is not easy for a physically disabled person. As a solution to this problem, Patent Literature 4 discloses a technique of controlling devices using human brain potential. Patent Literature 4 is hereby incorporated by reference. According to the technique, a control signal for controlling a device is output based on the brain wave obtained from human brain potential. According to the technique, the brain wave is consciously changed using bio-feedback method, and the resulting brain wave is subjected to frequency analysis and arithmetic comparison to obtain the control signal. Another example is disclosed in Patent Literature 5, which is incorporated herein by reference in its entirety. The apparatus disclosed in this reference includes: a detecting unit detecting brain potentials at different portions of a human skull and outputting brain potential data; a pattern generating unit comparing respective detected brain potentials with a prescribed threshold value and generating an activity pattern in accordance with the result of comparison; a pattern database storing in advance the activity patterns representing the state of activation of the brain and control signals for controlling a device in mutually associated manner; and a pattern processing unit comparing the generated activity pattern with the activity patterns in the pattern database, extracting a control signal corresponding to the activity pattern matching the generated activity pattern, and transmitting the control signal to the device. Using this apparatus, it is possible to control the device by brain potential.
Human sensation and perception are ever-changing in accordance with the surrounding environment. Most of the changes occur in a certain early period of human developmental stage, or the period referred to as "critical period." Adults, however, still keep sufficient degree of plasticity of sensory and perceptual systems to adapt to significant changes in surrounding environment. By way of example, Non-Patent Literature 1 reports that adults subjected to a training using specific perceptual stimulus or exposed to specific perceptual stimulus came to have improved performance for the training task or improved sensitivity to the perceptual stimulus, and such results of training were maintained for a few month to a few years. Non-Patent Literature 1 is hereby incorporated by reference in its entirety. Such a change is referred to as perceptual learning, and it has been confirmed that such change occurs in every sensory organ, that is, visual perception, auditory perception, sense of smell, sense of taste, and tactile perception.
The perceptual learning has various specificities, which are believed to come from involvement of lower order visual cortex with the perceptual learning. Further, as reported in Non-Patent Literature 2, there is an unsettled controversy regarding at which stage of visual processing the perceptive learning takes place. Non-Patent Literature 2 is hereby incorporated by reference in its entirety. Thus, it has been unclear what method is effective to support perceptual learning.
Bio-feedback used for perceptual learning needs measurement of brain activity. Various methods therefor have been known, including the following.                A method of measuring electrocorticogram using electrodes placed directly on cerebral cortex.        Non-invasive method of measuring electroencephalogram (EEG), in which small currents generated by activities of neurons in the brain are picked up by electrodes placed on one's skull, amplified and recorded.        Functional MRI (fMRI) visualizing hemodynamic responses related to human and animal brain activities, utilizing Magnetic Resonance Imaging (MRI).        Magnetoencephalography (MEG), which is an imaging technique of measuring with high sensitivity magnetic field generated by electric activities of the brain, using Superconducting Quantum Interference Device (SQUID).        Near-Infrared Spectroscopy (NIRS) measuring increase/decrease of hemoglobin (Hb) or indexes accompanying oxygen exchange information, using infrared light in a non-invasive manner through one's scalp and thereby mapping brain functions.
Conventional studies using fMRI have positively mapped sensory stimulation to humans and brain activities generated in relation therewith. When nerve activities are considered to be codes, the conventional methods try to find how stimuli are represented by the brain, or how the nerve activities encode stimuli.
In contrast, reading what stimuli have been applied from the nerve activities may be called decoding of nerve activities. Decoding of nerve activities is reported in Non-Patent Literature 3, which is hereby incorporated by reference in its entirety.
Besides, Patent Literatures 6 and 7 and Non-Patent Literatures 4 and 5 also report non-invasive measuring methods enabling direct measurement of in-brain nerve activities with high temporal and spatial resolutions from MEG data or EEG data, by utilizing fMRI data. These references are hereby incorporated by reference in their entireties.
Further, Non-Patent Literature 6 reports decoding of brain activities using measurements by electroencephalogram or magnetoencephalography to find that motion activity to a certain orientation among a plurality of orientations is activated, and utilizing the findings to brain-machine interface (BMI, hereinafter "interface" will be denoted as "I/F"). Non-Patent Literature 6 is hereby incorporated by reference.

Apparatus and method for supporting brain function enhancement

ADVANCED TELECOMMUNICATIONS RESEARCH INSTITUTE INTERNATIONAL


A power rectifier having low on resistance, fast recovery time and low forward voltage drop. In a preferred embodiment, the present invention provides a power rectifier device employing a vertical device structure, i.e., with current flow between the major surfaces of the discrete device. The device employs a large number of parallel connected cells, each comprising a MOSFET structure with a gate to drain short via a common conductive layer. This provides a low Vf path through the channel regions of the MOSFET cells to the contact metallization on the other side of the integrated circuit. A thin gate structure is formed annularly around pedestal regions on the upper surface of the device and a precisely controlled body implant defines the channel region and allows controllable device characteristics, including gate threshold voltage and Vf.

1. Field of the Invention
The present invention relates to discrete semiconductor devices and in particular power semiconductor devices. More particularly, the present invention relates to power semiconductor rectifiers including semiconductor diodes, Schoftky diodes and synchronous rectifiers.
2. Background of the Invention
Power semiconductor rectifiers have a variety of applications including applications in power supplies and voltage converters. For example, an important application of such rectifiers is in DC to DC voltage converters and power supplies for personal computers and other electronic devices and systems. In such applications, it is important to provide both a fast recovery time for the semiconductor rectifier and a low forward voltage drop across the rectifier (Vf). In particular, DC to DC voltage converter applications employ switched inputs and the recovery time of the rectifier used in the voltage converter will affect the dynamic losses for a given frequency of operation of the input. Also, a fast recovery time is needed for rectification of high frequency signals which are present in computers and many other electronic devices.
A low Vf in turn is needed in low voltage applications including power supplies for computers and other low voltage (e.g., 12 volt and lower) electronics applications. In particular, computer applications will typically require both a five volt power supply and a 3.5 volt power supply and in the future it may be as low as a one volt power supply. In converting the input five volt power supply to a 3.5 volt power supply, the voltage converter will inevitably introduce a loss due to the Vf drop across the rectifier in the converter circuit. In typical fast recovery semiconductor diodes employed in such devices, the voltage drop Vf may be approximately 0.7-0.8 volts. This results in a significant percentage of available power being wasted due to the voltage drop across the rectifier. For example, as much as 40% of the available power may be wasted in a two step voltage conversion from a 5 volt input to a one volt output. As a result, a significant portion of the available power may be simply dissipated in the device due to the relatively high Vf. This wasted power is obviously significant in laptop and notebook computers and other portable devices relying on battery power. However, such wasted power is also a significant problem in desktop computers and other devices due to heat generation.
While it is possible to adjust the properties of the diode junction to increase the recovery speed of the diode or to reduce the Vf of the diode, it is typically impossible to simultaneously lower both the voltage drop across the diode and at the same time decrease the recovery time of the diode. In computer applications the compromise is usually made in favor of fast recovery times.
Schottky diodes provide some advantages since Schottky diodes have a lower Vf for a given recovery time than semiconductor diodes. Nonetheless, such Schottky diode rectifiers suffer from problems such as high leakage current and reverse power dissipation. Also, these problems increase with temperature causing reliability problems for power supply applications. Therefore, the design of voltage converters using Schottky barrier diodes can cause design problems for many applications. Also, Schottky diodes are typically more expensive than semiconductor junction diodes due to yield problems.
As an alternate approach, synchronous rectifiers have been designed which avoid some of the problems associated with both Schottky diodes and PN junction diodes for high speed low voltage applications. Conventional power MOSFETs are typically employed for such synchronous rectifiers, and gate controller ICs have been used for driving the discrete MOSFET devices in order to provide synchronous rectifiers with the desired device characteristics. The current state of such approaches to synchronous rectifiers for high performance rectifier applications is described, for example, in Bob Christiansen, et al. xe2x80x9cSynchronous Rectificationxe2x80x9d, PCIM, August 1998. The need for a driver IC, however, adds additional complexity and costs over simpler rectifiers.
A different approach to the problem that addresses most of the shortcomings of the Schottky diodes can be derived from an observation that the subthreshold current of a MOSFET as a function of drain voltage exhibits rectifying properties, which may be appreciated from the following equation (1):                                           (                          1              -                              ⅇ                                                      -                    k                                                                          xe2x80x83                                                                          T                    q                                                                          V                    d                                                                        )                                          I            s                          =                  I          d                                    (        1        )
(See, for example, S. M. Sze, Physics of Semiconductor Devices, Chapter xe2x80x9cMOSFETxe2x80x9d, paragraph xe2x80x9cSubthreshold Regionxe2x80x9d.) In the above expression, Id is the Drain Current; Vd is the Drain Voltage and Is is an equivalent saturation current which value is mainly determined by the surface potential "psgr"s and the gate voltage VG. Fixing VG (e.g., by shorting it to Drain) will lead to the rectifying Volt Ampere characteristic with the equivalent xe2x80x9cbarrier heightxe2x80x9d determined by the internal device parameters (gate oxide thickness, doping concentrations, surface states, etc.; e.g., reference S. M. Sze above).
An example of such approach directed to providing a power rectifier suitable for low voltage applications is described in U.S. Pat. No. 5,825,079 to Metzler, et al., issued Oct. 20, 1998. In the ""079 patent, a rectifier device is described which may be viewed as a vertical MOSFET structure having a gate to drain short. This device is thus a type of a rectifier as described above. There are several attributes of the teaching of the ""079 patent, which significantly undermine its practical usefulness. For example, the proposed procedure of formation of a P type body region (denoted by reference numeral 56 in FIG. 3 of the ""079 patent) introduces serious yield problems in the manufacture of the device. This arises since the characteristics of the carrier concentrations in the channel region are highly susceptible to uncontrollable process variations.
This severe manufacturing problem may be appreciated by consideration of FIGS. 7A and 7B which illustrate the implantation of a P type body region 1 below an N type region 2 using a spacer 3 which serves to define the channel 4. The ideal situation is illustrated in FIG. 7A corresponding to a perfectly vertical sidewall of spacer 3 with the P layer 1 situated below the N type layer 2 with a peak concentration indicated by the horizontal dashed line. (The vertical profile of the P implant will typically have a Gaussian distribution with the dashed line in FIG. 7A corresponding to the peak of the Gaussian curve.) This perfectly vertical sidewall of spacer 3 is never achieved in practice, however, and instead a sloped sidewall is inevitably produced. This situation is illustrated in FIG. 7B. As may be appreciated by inspection of FIG. 7B, the sloped sidewall of the spacer 3 inevitably affects the penetration of the implant at the edge of the spacer region pulling the peak P dopant concentration up toward the surface as illustrated by the dashed line in FIG. 7B. As may be seen, this pulls the P region into the N type channel region affecting the threshold voltage and Vf of the device.
It will be appreciated from FIG. 7B that a variation in the slope of the sidewall spacer 3 will horizontally move the region where the peak P concentration reaches the surface. Since the degree of verticality of the sidewall spacer 3 cannot be precisely controlled, this creates uncontrollable variations in the device characteristics. Furthermore, increasing the N type concentration in the contact region to reduce the on resistance of the device exacerbates the variability of the doping concentrations in the channel due to the interaction of the N++ contact region and the P concentration which has been pulled to the surface in the unpredictable manner illustrated in FIG. 7B. Accordingly, the problems of the high on resistance and the unpredictability of the dopant concentrations in the channel region adjacent the contact region, render the device of the ""079 patent commercially nonviable.
In view of the foregoing, it will be appreciated that none of the existing power rectifiers provide all the desirable characteristics needed for computer power supplies and voltage converters, and other applications where both low Vf and fast recovery are needed. Therefore, a need presently exists for a power rectifier device having low on resistance, low Vf, high speed switching capabilities as well as having controllable device characteristics. Furthermore, it will be appreciated that a need presently exists for such a device which is not unduly complex and which is readily compatible with available integrated circuit processing techniques and which may be produced at low cost.
The present invention provides a power rectifier device having low on resistance, fast recovery time and low forward voltage drop. The present invention further provides a method for manufacturing such a rectifier device which is compatible with existing semiconductor technology, which provides a high degree of reliability in device characteristics and which can provide such devices at reduced cost.
In a preferred embodiment, the present invention provides a power rectifier device employing a vertical device structure, i.e., with current flow between the major surfaces of the discrete device. The device employs a large number of parallel connected cells, each comprising a MOSFET structure with a gate to drain short via a common metallization. This provides a low Vf path through the channel regions of the MOSFET cells to the source region on the other side of the integrated circuit. A precisely controlled body implant defines the channel region and allows controllable device characteristics, including gate threshold voltage and Vf.
In a first aspect, the present invention provides a discrete integrated circuit rectifier device, comprising a semiconductor substrate doped with a first conductivity type dopant and having a first major surface and a second major surface and a plurality of active cells on the first major surface. First and second electrical contacts on the first and second major surfaces, respectively, define a current flow path vertically between the major surfaces through the plurality of active cells. The active cells each comprise a gate oxide, a gate over the gate oxide, a highly doped contact region of the first conductivity type, a body region of a second conductivity type underlying the contact region and the gate oxide, and a channel region. The channel region comprises a portion of the body region underlying substantially all of the gate oxide. The current flow through the active cells flows through the plurality of channel regions under control of an electrical potential applied to the gates via the first electrical contact.
In another aspect the present invention provides a discrete integrated circuit rectifier device, comprising a semiconductor substrate having first and second surfaces and a plurality of pedestals formed on the first surface. A MOSFET comprising a plurality of parallel connected MOSFET cells is formed on the semiconductor substrate, the MOSFET cells controlling current flow between the two surfaces of the substrate. Each MOSFET cell comprises a spacer formed adjacent the side of a pedestal, the spacer defining the location of the MOSFET cell relative to the pedestal, a gate, a gate oxide, a contact region of a first conductivity type, a body region of a second conductivity type underlying the gate oxide and contact region, and a channel region comprising a portion of the body region underlying substantially all of the gate oxide. A common electrically conductive layer shorts the gate and contact regions of the plurality of cells to provide a two terminal rectifier device.
Further features and advantages of the present invention will be appreciated by review of the following detailed description of the invention.

Discrete integrated circuit rectifier device