A device for transferring items to a transport system or to a storage unit has a feed unit for conveying a plurality of items in at least one feeding line. Further, it has a transfer station for receiving the items from the feed unit and for transferring the items to the transport system or to the storage device. The transfer station includes two temporary storage lines arranged in parallel. The items are provided by the feed unit in a manner that the items in the first temporary storage line are arranged offset from the items in the second temporary storage line. The temporary storage surfaces in the first temporary storage line have at least one flap to be opened. A pusher in the transfer station is adapted to push the items from the second temporary storage line to the first temporary storage line.

1. Field of the Invention
The present invention pertains to a device for transferring items to a transport system or to a storage device.
2. Description of the Related Art
Devices for transferring items are used, for example, to transfer blister packs to the transfer chain of a cartoning machine. U.S. Pat. No. 6,092,979 describes a device for transferring blister packs to a moving blister pack transfer chain, in which two parallel lines of blister packs are transported by two separate conveyor belts. A pickup unit picks up the blister packs, which are initially arranged in parallel rows, and forms a stack of two blister packs, one on top of the other, on each of the two conveyor belts, wherein the individual stacks are arranged a certain distance apart from each other, and the stacks of one conveyor belt are offset from the stacks of the other conveyor belt. Finally, the stacks of blister packs are pushed together by a pusher transversely to the transport direction of the conveyor belts to form a line, so that a row of closely spaced blister pack stacks can be carried onward on a transport belt. A device of this type is subject to considerable limitations with respect to the further processing of the blister stacks, because they can be transported only in the conveying direction of the two conveyor belts. Finally, a device such as this occupies a relatively large amount of space.
A similar device is also known from WO 00/68086, in which individual blister packs, which are arranged in parallel rows, are again deposited with an offset from each other on two conveyor belts by a pickup unit. The conveyor belts work in cycles, and the blister packs are pushed out from the their cassettes toward a transport device located between the two conveyor belts, as a result of which a line of closely spaced blister packs is formed on this transport device. Here, too, however, the blister packs can be conveyed onward only in the transport direction of the conveyor belts, and the device again occupies a relatively large amount of space.
A device in which the individual blister packs are brought up into position one by one by a vacuum belt in a direction parallel to that in which the transport system moves is known from EP 1,602,584 A1. The blister packs are delivered in stacks to the cassette module of a transfer unit. The cassette module can be moved in synchrony with the packaging material transport system, wherein, during the parallel movement, the stacks of blister packs are pushed by pushers into the individual receptacles of the transport system. The cassette module then travels back to its starting position, where it is refilled with blister packs by the vacuum belt. The device is complicated mechanically, occupies a large amount of space because of the movement of the cassette module, and makes it possible to fill only special types of transport devices.

Device for transferring packaged material to a packaged material transport system or to a storage device


Described is a multi-modal binary pixel sampling system incorporating a configurable sampler. The system includes an imaging pixel that outputs a series of reset and measurement values. The configurable sampler can extract image data from these values using correlated double sampling (CDS), non-correlated double sampling (NCDS), direct comparison sampling (DS), or a combination of these sampling modes. The configurable sampler is agile and may transition among modes during an exposure interval. Additional switches, storage elements, and reference nodes may be added to store additional measurements or calibration values.

In a conventional CMOS image sensor, an integrated circuit contains an array of pixel sensors, or "pixels," each pixel including a photodetector that develops an analog voltage change proportional to a number of photons striking the detector during an exposure interval. At the conclusion of the exposure interval, a voltage developed on the photodetector is typically amplified and delivered to an analog-to-digital converter (ADC), which digitizes the amplified voltage.
Pixel geometries have scaled downward as CMOS processing has improved, resulting in performance rivaling that of larger and more power-consumptive Charge Coupled Devices (CCD), which have been widely applied in imaging devices such as digital single lens reflex (DSLR) cameras and camcorders. CMOS devices, having lower cost and performance equivalent to CCDs, now enjoy widespread adoption in modern imaging devices including smart phones, web cameras, and DSLR cameras. Despite the widespread adoption of CMOS imaging sensors however, limitations in performance exist due to various noise sources and dynamic range constraints.

Methods and circuitries for pixel sampling


A T-fitting such as for use inside a containment box for connecting a primary pipeline to a gasoline dispenser has two flanges which connect to the pipeline and a main T-element sealed to each flange by a sealing element such as a gasket. The flanges thread onto each end of the primary pipeline. The main T-element has a stem which is threaded to a pipe leading to a gasoline dispenser. The flanges of the T-element are bolted to the main body of the T-element with the rubber gasket in between to seal the primary pipeline to the T-element.

1. Field of the Invention
The present invention relates to a T-fitting with quick release flanges for gasoline handling equipment, and more particularly, to a T-fitting with quick release flanges for a primary pipeline connection to a gasoline dispenser for service stations with secondary containment pipes and a method for installing the T-fitting.
2. Background of the Invention
For some time now, gasoline handling equipment, such as gasoline dispensers, and the piping connecting such dispensers with underground gasoline tanks and pumps has been made with secondary containment. That is, due to environmental concerns favoring prevention of leaking gasoline from entering the ground, the pipes have a second pipe around them, and the dispensers and underground pump have a box-like structure below them. An example of such a box and secondary containment is shown in U.S. Pat. Nos. 5,285,829 and 5,341,857, both to the present inventor. Typically, for each product line, such as 87 octane, there is a separate pipeline. At the dispenser, there is an impact valve which will shut off the flow of gasoline to the dispenser in the event of a vehicle colliding with the gasoline dispenser or other disaster. The above-mentioned patents show that the impact valve may also be connected to a float mechanism for detecting leaking gasoline that is collected within the containment box. The lifting of the float mechanism will shut off the impact valve. In addition, in such systems, it is common to provide a light, bell, or other warning signal, including the shutting off of the dispenser itself, to alert the station attendant that there is a problem with that dispenser. The float system will also detect water and will operate in the same manner as in response to gasoline.
In such systems, it is customary to install the containment box. The box surrounds an impact valve which leads to the gasoline dispenser below which the box is installed. A primary pipeline (product line) will pass through the box carrying fuel from an underground storage tank to the gasoline dispenser above the box, and also to be carried to an additional dispenser. Accordingly, a T element is needed within the box to connect an input line of the primary pipeline to the line leading to the impact valve and dispenser (gasoline dispenser input line), while allowing product to continue on to the next dispenser through a product output line.
Once the box is installed, a T is connected to the line leading to the impact valve. The T must also be connected to the primary pipeline. This is a cumbersome connection to make and to remove and replace in the event of repairs. What is needed is a way to simplify installation of the T element and surrounding piping, and to simplify repair of the piping and/or T element after installation.

Removable penetration fittings using T-fitting and flexible pipe combination


A method to drive a display with grid array pixels is comprised of writing image data containing a range of grayscale code into multiple pixels; at least a time of a pixel row being divided into frame time and black picture time; each code in the grayscale range being mapped to that in and adjusted range to drive the display without changing gamma voltage or with increased gamma voltage of the greatest grayscale code to present the luminance desired; pixel response time being shorter than frame time; and black picture data being written into the pixel row during the black picture time.

(a) Field of the Invention
The present invention is related to a method to drive a display of grid array pixels, and more particularly to one that has grayscale code range of each light color mapped to an adjusted range and to overdrive pixels to present the luminance desired for the response time of the pixel to be shorter than the frame time, thus to solve the problem of residual image.
(b) Description of the Prior Art
Reason for LCD to get popular is that in comparison with the conventional CRT display, LCD provides advantage of low power consumption, compact, radiation free and absence of glittering to make it applicable to TV, notebook or PC screen and gradually becomes the mainstream in the manufacturing industry of display. Furthermore, with the advancing process technology of display and the introduction of large size LCD, LCDs become even more comprehensively applied in daily life and A/V entertainment. Meanwhile, more demands are particularly put on the visual angle, response speed and number of colors of the display to pursue even higher quality presentation of image of the display.
Conventional CRT display works on having electronic beams to irradiate from the terminal of a vacuum tube to a screen coated with light emitting material; the irradiated screen produces momentary colors, meaning they will disappear before the irradiation of the image data of the next picture. That type of display refers to impulse type, and there will be no residual image between pictures; however, glittering does exist if the scanning frequency of the CRT display is not fast enough.
On the contrary, there will be no problem of glittering in case of a LCD because LCD contains a liquid crystal capacitor CLC and storage capacity (CS) so that the voltage to drive liquid crystal molecules is stored in a fully charged capacitor to be held for the next updated picture. This type of display is referred to as a hold type. However, if the response rate of liquid crystal molecules when driven by the voltage is not fast enough, i.e., the response time is greater than the frame time, the picture will become blur or produce residual image to significantly affect the viewing quality.
As illustrated in FIGS. 1, 2A, and 2B, generally the response time is divided into two parts: (1) Rising response time (Tr): i.e., with the applied voltage, the time raising taken for the luminance of the liquid crystal box of the LCD to change from the level of 10% up to 90%; and (2) Falling response time (Tf), i.e., without the applied voltage, the time falling taken for the luminance of the liquid crystal box to change from the level of 90% down to 10%. If the curve of the variation of the normal luminance is indicated as "10" for a display to receive the image of code A during the first frame time I and the image of code B during the second frame time II, the expected luminance of code B may be achieved only upon entering into the firth frame time III in case of a display with the response rate of its liquid crystal molecules. Furthermore, if the display relates to a hold type, problems of deferred or residual image will appear as illustrated in FIG. 2B, wherein, the arrow points out the scanning direction of the display. If overdrive method is used to have the second frame time II of the display to drive with and OD voltage higher than that of code B and the response rate of the liquid crystal molecules is fast enough, the luminance variation may reach the expected luminance with that frame time with its luminance curve as that marked by 10′. Even so, certain residual image problem remains in case of a hold type display with its scanning picture as illustrated in FIG. 2B.
To solve the problem of residual image, the impulse type of CRT display is usually borrowed in the following two approaches: (1) Data of black color or black pictures are inserted into pictures of continuous images; and (2) Signals of black picture are inserted into back light source to control the light source for producing flaring effects so to glitter the back light source. As illustrated in FIGS. 3A when the first approach is applied to insert black pictures into picture of image, the grayscale code of the image of the first frame time I is code A, data of black picture are received upon entering into the first black picture time I′ for the luminance variation curve 20 to indicate as an impulse curve. Upon entering into the second frame time II, the third frame time III and the fourth frame time IV, code B with a luminance higher than that of code A is received while data of black pictures will immediately following after each grayscale code B, e.g., the second black picture time II′, the third black picture time III′ and the fourth black picture time IV′. Theoretically, any pixel driven by code B shall give the same luminance performance, i.e., the highest points of the luminance curve shall be at the same level. However, lab test shows that the luminance is gradually rising with the luminance of any frame time higher than that of the immediately preceding one, a phenomenon so far not yet explained by any theory in the field of liquid crystal. As projected, the sticking characteristic of liquid crystal molecules might be attributable to such phenomenon. Nonetheless, the problem should be solved to avoid poor picture quality or insufficient luminance of the picture to indicate the delay as illustrated in FIG. 3B.

Drive method for display of grid array pixels


Part of a first oxide film formed by thermal oxidation is removed by etching. A second oxide film is formed in the part of substrate from which the first oxide film has been removed using heated nitric acid. The two oxide films are nitrided by a nitrogen plasma having a low energy so as to be first and second gate insulating films, i.e., oxynitride films, respectively.

The present invention relates to a method for fabricating a semiconductor device and a semiconductor device, and particularly relates to a method for fabricating a semiconductor device including an oxide film which is formed by solution oxidation and, furthermore, into which nitrogen is introduced and the semiconductor device.
Among a plurality of transistors formed on a semiconductor substrate, for example, a transistor in a CMOS (complementary metal oxide semiconductor) device has a gate insulating film having a more and more reduced thickness for the purpose of improving the driving ability of a semiconductor device. In recent years, a gate insulating film having a thickness of 1–3 nm is required for such a transistor. On the other hand, in another transistor which is not required to perform a high speed operation but is required to use a relatively high voltage such as an input/output signal, a gate insulating film has to have a relatively great thickness in order to suppress a leakage current in the gate insulating film. In this case, a desired thickness of the gate insulating film is 7–10 nm. Since these transistors described above are formed in the semiconductor device, two or more different gate insulating films having different thicknesses have to be formed on the same substrate.
Conventionally, thermal oxidation (e.g., see S. M. Sze, VLSI technology, McGraw-Hill, 1984, pp.131–168) which allows formation of an oxide film with excellent properties as a gate insulating film has been mainly used in oxidizing a semiconductor device to form a gate insulating film. To form two different gate insulating films having different thicknesses on a semiconductor substrate, a method is used in which after a first gate insulating film has been formed by thermal oxidation, part of the first gate insulating film is removed by patterning and then a second gate insulating film is formed by thermal oxidation in a region of the semiconductor substrate from which the first gate insulating film has been removed. Moreover, besides thermal oxidation, use of various other methods for forming a gate insulating film has been examined (e.g., see Japanese Patent Publication No. 2937817, Japanese Unexamined Patent Publication No. 10-50701, Japanese Unexamined Patent Publication No. 10-223629, Japanese Unexamined Patent Publication No. 11-214386, and Japanese Unexamined Patent Publication No. 2002-64093).
As a technique for reducing the thickness of a gate insulating film for the purpose of improvement of the driving ability of a semiconductor device, a method in which nitrogen is introduced into a gate insulating film by annealing in nitrogen monoxide so as to reduce an electrical film thickness has been used. An electrical film thickness is a thickness measured in terms of electrostatic capacity. Even with the same physical thickness, the larger dielectric constant a film has, the smaller the thickness of the film is indicated. Oxynitride into which nitrogen is introduced has a larger dielectric constant than that of silicon dioxide. Therefore, by introducing nitrogen, an electrical film thickness is reduced, so that the driving ability of a transistor is improved. As a method for introducing nitrogen into a gate insulating film, i.e., a silicon dioxide film, a method using a plasma is known (e.g., Japanese Unexamined Patent Publication No. 10-79509).
Moreover, when nitrogen is introduced into a gate insulating film, as described in Japanese Unexamined Patent No. 10-79509, a dopant with which a gate electrode has been doped is prevented from reaching a substrate through the gate insulating film. This will be described further in detail.
In a CMOS transistor, a dual gate structure in which boron is introduced as a dopant into a gate electrode of a p-channel transistor and phosphorous is introduced as a dopant into a gate electrode of an n-channel transistor is used. Boron has a larger diffusion constant than that of phosphorous and thus is diffused in a gate insulating film through thermal treatment performed after the transistor has been formed. Thus, boron easily reaches a channel region. This phenomenon is called boron leakage and causes a large change in a threshold voltage, reduction in the driving ability of a transistor and the like. Especially, the smaller thickness a gate insulating film has, the larger the boron leakage becomes. However, if nitrogen is introduced into a gate insulating film, the boron leakage can be suppressed.
Problems that the Invention is to Solve
In a method for forming a plurality of gate insulating films according to the known method, a first gate insulating film is etched through wafer cleaning performed after a photoresist has been removed, so that the thickness of the first gate insulating film is once reduced. Then, when a second gate oxide film is formed, the thickness of the first insulating film is increased this time. This causes reduction in controllability of the thickness of the first gate insulating film, and also, in terms of film quality, it is very difficult to control the film quality of the first insulating film which has undergone through etching and additional oxidation.
Furthermore, assume that three different gate insulating films having different thicknesses (e.g., 7 nm, 3 nm and 1.5 nm) are formed. A second gate insulating film has a relatively small thickness, i.e., 3 nm. Thus, the second gate insulating film is more largely influenced by reduction and increase in a film thickness caused in forming a third gate insulating film having a thickness of 1.5 nm than a first gate insulating film having a thickness of 7 nm. That is to say, it is very difficult to control the thickness of the second gate insulating film so that the second gate insulating film has a constant thickness at any time. Accordingly, the ratio of an additional portion formed through additional oxidation to the entire thickness of the second gate insulating film is increased. Therefore, the quality of the entire second gate insulating film is largely reduced.
Moreover, assume that the thickness of a gate insulating film is reduced. When an oxynitride film is obtained as a gate insulating film according to a method described in Japanese Unexamined Patent Publication No. 10-79509, the electron energy of a nitrogen plasma is very high, i.e., about 50–1000 eV and this becomes a problem. For example, assume that a gate insulating film into which nitrogen is to be introduced has a thickness of 1.5 nm. Even when a nitrogen plasma has an energy of the lower limit of the energy range described in Japanese Unexamined Patent Publication No. 10-79509, i.e., 50 eV, the nitrogen plasma easily goes through the gate insulating film to nitride a silicon substrate as well. As a result, even though the thickness of the gate insulating film was about 1.5 nm before an exposure to the nitrogen plasma, the silicon substrate has been nitrided after the exposure to the nitrogen plasma, so that the total thickness of part of the gate insulating film which has been nitrided is over 2 nm. Thus, even though an oxide film having a thickness of 1.5 nm is formed, an oxynitride film having a small thickness can not be obtained. As a matter of course, the known method can not be used with a gate insulating film having a thickness of about 1 nm. Furthermore, when a nitrogen plasma has a higher energy than 50 eV, use of the known method is out of question. Nnitriding of a silicon substrate causes not only increase in a film thickness but also reduction in a driving force resulting from reduction in mobility or reduction in reliability.
The present invention has been devised in view of the above-described problems. It is therefore an object of the present invention is to provide a method for a fabricating a semiconductor device in which a gate insulating film having a small thickness allowing a high-speed operation can be formed with excellent film thickness control and furthermore, nitriding can be performed so as not to reach a semiconductor substrate, and a semiconductor device which includes a gate insulating film having a small thickness and excellent quality and in which a semiconductor substrate is hardly nitrided.

Method for fabricating semiconductor device and semiconductor device

Matsushita Electric Industrial Co., Ltd.


An electrical connector for a medical instrument has a plug containing a plurality of pins in electrical communication with wires emanating from a shielded cable that is connected to a medical sensor detecting physiological data. The plug portion of the electrical connector substantially surrounds the connection of the pins with the cable in a plastic housing. When the plug is inserted in to a socket portion of the connector mounted to a medical instrument housing, the pins electrically communicate with a plurality of tubular sockets to communicate the signals to electronic devices in a medical instrument. Surface coatings on the connector are provided to shield the wire connections with the pins and tubular sockets from electromagnetic interference (EMI). A tubular shield is also provided in the medical instrument to shield the electrical connection between the internal cable and the tubular receptacles from EMI. The EMI shields on the connector and the EMI shielding on the connecting cables are all connected to a common ground. A significant reduction in EMI distortion of the sensor signals is achieved.

In hospitals it is common to have sensors monitoring patients by sensing a variety of parameters. These sensors monitor, among other things, heart rate, breathing rate, and various blood gases, including the oxygen content in the blood. The medical instruments that analyze and display the data from these sensors are typically located some distance from the patient and the sensors. A variety of cables connect these sensors to the instruments and often transmit electrical signals containing the sensor data from the patient to the instruments. Because these sensors are connected to, or used near patients, very low electrical currents and voltages are preferably used in these sensors and cables. As a result, the signals from the sensors are subject to electromagnetic interference ("EMI") from a variety of sources, including room lights, electric wall outlets, and other electrical devices. Radio Frequency interference, or RF interference also presents a concern, but all types of interference will be referred to as EMI for convenience in this application.
One medical device subject to this EMI is a blood oximeter. The sensor cables connect to this oximeter through a cable that connects to an instrument casing containing the electronic analysis equipment. The cable connects to the instrument through a widely used plastic coupling or connector made by Hypertronics, with the connector comprising a plurality of male pins that are inserted into a corresponding socket connected to the oximeter instrument housing. A resilient lever hook holds the two parts together. To reduce EMI disruption of the signals, the sensor cable is shielded. Further, the instrument housing is also shielded, as is the cable inside the instrument. Similar shielding steps are used in the cables on other medical instruments where these cable connectors are used.
But despite the shielding in the instrument casing and cable, sensor signals from this oximeter are subject to interference from even the 60 Hz florescent lights commonly used in hospitals. There is thus a need for improved performance of medical devices in general, and from this oximeter in particular. Further, there is a need for a way to reduce or eliminate EMI disruption and distortion of the signals from these medical instruments in general, and for medical equipment using this particular Hypertronics connector in particular.


A massage device includes an outer casing, a driving mechanism and at least one massage module. The massage module includes an inclined rotary plate coupled to a main gear seat having central massage balls. When the inclined rotary plate rotates, the main gear seat and the central massage ball are driven to rotate. The main gear seat engages with a plurality of planetary gears, each of which is coupled with a massage arm. An upper end of the massage arm has a peripheral massage ball disposed thereon and a lower end of the massage arm contacts with the inclined rotary plate. A rotation of the inclined rotary plate drives massage arms and the peripheral massage balls thereon to rotate via the planetary gear as well as to move the massage arms up and down, thereby providing a massage of kneading and acupressure.

1. Field of the Invention
The present invention relates generally to a massage device, and more particularly to a massage device that provides massage with heat setting.
2. Description of the Related Art
A conventional massage device, such as a foot, back or neck massage device, comprises an outer casing in which a driving mechanism is received to drive the rotation of massage balls. When the massage device is put in contact with the human body, the rotation of the massage balls provides a massage action. The driving mechanism usually includes a motor coupled with a worm shaft. The worm shaft drives intermediary gears and the intermediary gears drive a follower gear, thereby rotating the massage balls associated with the follower gear.
The massage device mentioned above can offer only one single kneading movement. Therefore, the massage device has a limited massage effect only at the skin surface level, and fails to provide a deep tissue massage for penetrating relief or improving blood circulation.


The present invention provides for a circuit comprising: an input operable to receive a bit pattern; a bit-operator configured to selectively transpose the bit pattern; a shifter configured to shift the bit pattern following the transposition of the bit pattern; and the bit-operator being configured to transpose the bit pattern following the shift of the bit pattern. The present invention additionally provides a barrel shifter and a method for manipulating a bit pattern.

Barrel shifters are conventional circuits which may be utilized to shift the contents of a data path of an integrated circuit, such as a microprocessor or digital signal processor. The output bit pattern of the barrel shifter may be applied to an arithmetic logic unit which provides arithmetic and logic operations thereto. A variable-length shift of a bit on the data path requires the possibility of connecting the selected bit to any one of several other bit paths.
The circuit shown in FIG. 1 comprises a classical 8-bit barrel shifter. The barrel shifter generally receives data via an input 6. The data may be shifted or rotated within the barrel shifter. An array containing passgates may be utilized to perform the shift function. The classical barrel shifter includes 2*d lines of m+1 passgates (d=signed shift value; m=number of bits in input and output data path). Each line includes m+1 passgates (opposed to only m) to account for the carry over bit.
A decoding section 7 may be utilized to generate a plurality of select signals from control signals received via input 6. The select signals may be applied via lines 4 to the passgate array 8. The classical barrel shifter generates 2*d select signals for providing shifting operations. In particular, the select signals enable an appropriate column of passgates to provide the desired shift of the bit pattern
It is often desired to optimize the area occupied by components implemented within an integrated circuit to enable the formation of additional components thereupon. Providing additional components enables additional processing of data, faster processing of the data, as well as larger amounts of data to be processed.
Improvements in integrated circuit materials, mechanical equipment and photolithography have enabled close tolerances and small geometries to be attained. Such improvements permit the formation of additional components upon a processor.
In addition, space upon the integrated circuit may be conserved by providing components which require less surface area for implementation. Reducing the surface area required for implementing components provides additional space for providing additional components on the integrated circuit.
Therefore, there exists a need for reducing the surface area required for the implementation of a barrel shifter on an integrated circuit.

Barrel shifter, circuit and method of manipulating a bit pattern


An FPGA is laid out as a plurality of repeatable tiles, wherein the tiles are disposed in columns that extend from one side of the die to another side of the die, and wherein each column includes tiles primarily of one type. Because substantially all die area of a column is due to tiles of a single type, the width of the tiles of each column can be optimized and is largely independent of the size of the other types of tiles on the die. The confines of each type of tile can therefore be set to match the size of the circuitry of the tile. Rather than providing a ring of input/output blocks (IOBs) around the die periphery, IOB tiles are disposed in columns only. Where more than two columns worth of IOBs is required, more than two columns of IOB tiles can be provided.

Programmable logic devices (PLDs), such as field-programmable gate arrays (FPGAs), are user-programmable integrated circuits that can be programmed to implement user-defined logic circuits. In a typical FPGA architecture, an array of configurable logic blocks (CLBs) and a programmable interconnect structure are surrounded by a ring of programmable input/output blocks (IOBs). Configurable logic blocks can also be referred to using other names such as, for example, a logic array block (LAB) or a logic module.
In one SRAM-based FPGA, each of the CLBs, each of the IOBs, and the programmable interconnect structure includes configuration memory cells, the contents of which determine how the CLB, the programmable interconnect structure, or the IOB is configured. To realize a user-defined circuit, configuration data is loaded into the configuration memory cells such that the CLBs and IOBs are configured to realize particular circuit components used in the user-defined circuit. Configuration data is also loaded into the configuration memory cells of the programmable interconnect structure such that the programmable interconnect structure connects the various configured CLBs and IOBs in a desired manner to realize the user-defined circuit.
In addition to CLBs and IOBs, other more specialized circuits may be provided on an FPGA integrated circuit for use in user-specific designs. Examples of such other circuits include, but are not limited to, block random access memory (BRAM), multiplier circuits, processors, clock management circuitry, and high-speed transceivers.
The cost of an integrated circuit die is directly related to its size. If all other cost factors involved in the manufacture of an integrated circuit are equal, then making the integrated circuit larger will make the integrated circuit more expensive to produce. It is therefore generally an objective in FPGA integrated circuit design to lay out the circuitry of the CLBs, IOBs, and programmable interconnect using as little integrated circuit die surface area as is realistically possible. Because the layout of an integrated circuit die includes considerable engineering effort and therefore cost, FPGA integrated circuits are often laid out as a set of repeatable "tiles". The various tiles are laid out adjacent to one another such that adjacent tiles couple together at their boundaries to form the larger FPGA integrated circuit. The particular way the tiles are laid out across the surface of the FPGA die is called a floorplan.
FIG. 1 (Prior Art) is a simplified diagram showing one way that various CLB, IOB, BRAM/multiplier tiles could be laid out to form an FPGA integrated circuit 1. The CLB tiles 2 are laid out in column-like two-dimensional arrays. In this example, each CLB tile includes a portion of the configurable interconnect structure such that the entire interconnect structure is formed by the various portions of the many CLBs when the CLB tiles are placed together on the FPGA. There are also BRAM/multiplier tiles 3. The BRAM/multiplier tiles, which are not required in as great of numbers as the CLB tiles, are laid out in columns of uniform width. For more information on the various types of tiles shown in FIG. 1, see the data sheet for the Virtex II Pro FPGA. The data sheet is available on-line in PDF form on the Xilinx, Inc. web site, www.Xilinx.com.
In order to provide a large amount of input/output circuitry for interfacing the FPGA 1 to external logic, IOB tiles 6 are provided along each of the four sides (top, bottom, left, right) of the die. In this particular design, an input/output interconnect tile (IOI tile) is used to couple each pair of IOB tiles to a CLB tile in the central core of the die. One such IOI tile is therefore disposed between each pair of IOB tiles and the central core. Reference numeral 7 points to one such IOI tile. IOI tile 7 is disposed between the two IOB tiles to its right and the CLB tile to its left.
FIG. 2 (Prior Art) is a simplified perspective view of an IOB tile 6 of the die of FIG. 1. In this example, input/output circuitry 8 within the IOB tile is connected by conductive traces 9 to both a bond pad 10 as well as to a solder bump 11. A solder bump is sometimes called a bond bump or a microbump. The solder bump may be formed of metal in the upper metalization layers above the IOB tile itself or may be disposed outside the lateral boundary of the IOB tile as illustrated in FIG. 2. The bond pad 10 is provided so that the FPGA die can be wire bonded to an integrated circuit package. The solder bump 11 is provided so that the FPGA die can be packaged in flip-chip fashion. Providing both bond pads and solder bumps for the IOB tile makes the resulting FPGA die more versatile in that the same type die layout can used in wire bond packages and in flip-chip packages.
Providing an IOB tile with both a bond bump and a wire bond pad, however, increases total capacitive loading on input/output trace 9. This additional capacitive loading is undesirable. In addition to an undesirable increase in capacitive loading, providing both a bond bump and a wire bond pad also has the drawback of consuming additional die surface area. Wire bond pads cannot generally be disposed directly over areas of circuitry. During wire bonding, physical forces are placed on the bond pad by an external wire bonding device. The physical forces imposed on the wire bond pad may damage any circuitry that might be disposed under the wire bond pad. Consequently, providing a wire bond pad for an IOB tile generally involves consuming die surface area in addition to the amount of die surface area occupied by the circuitry of the IOB tile. If the bond pad could be eliminated from the FPGA design, then the amount of die area required to realize the IOB tiles could be reduced.
For additional information on a tile FPGA floorplan and on the general operation of an FPGA integrated circuit, see: 1) U.S. Pat. No. 5,914,616 by Young et al.; 2) the Advance Product Specification entitled "Virtex-II Pro Platform FPGAs: Functional Description", Sep. 27, 2002; 3) Published U.S. Patent Application US2001/0030555A1 by Witting et al.; and 4) U.S. Pat. No. 6,396,302, by New et al. (the subject matter of these four documents is incorporated herein by reference).
Although the tile layout technique illustrated in FIG. 1 has significant efficiencies and benefits, the tile layout technique also has certain drawbacks. For example, the four corner regions 12–15 of the die cannot accommodate the same IOB tile and IOB tile structure as is present elsewhere along the periphery of the die. As set forth above, the architecture of FIG. 3 requires that an IOI tile be disposed between a pair of IOB tiles on the die edge and a corresponding CLB tile on the edge of the central core of the die. As can be seen in FIG. 3, the CLB tile nearest to a corner is bounded by an IOI tile, and yet additional die area in the corner region. If an additional IOI tile and a corresponding pair of IOB tiles were to be placed in the available space in the corner region, then there would be no CLB tile edge to which the added IOI tile could be abutted. Accordingly, the IOI tile mechanism for interfacing IOB tiles to the central core cannot easily be used in the four corner areas of the die.
In addition to the limited utility of corner regions 12–15, the tiles and layout technique of FIG. 1 also results in areas above and below the columns of BRAM/multiplier tiles having limited utility. As set forth above, the repeatable IOB tiles interface to CLB tiles through intervening IOI tiles. In the areas 16–27 above and below the BRAM/multiplier tile columns, there are no CLB tiles to interface to. IOB tiles and IOI tiles are therefore not placed in these areas. The result is an area along the periphery of the die that either is wasted or must have a tile that differs in structure from the IOB and interconnect and CLB tile structure used elsewhere on the periphery of the die.
FIG. 3 (Prior Art) is a diagram that shows one way that these corner regions 12–15 and areas 16–27 above and below the BRAM/multiplier tile columns are used in one conventional FPGA. In the example of FIG. 3, clock management circuitry is fitted into the areas 16, 21, 22 and 27 above and below the leftmost and rightmost columns of BRAM/multiplier tiles. Although these areas 16, 21, 22 and 27 are used, it is not necessarily the case that the amount of circuitry required by the clock management circuitry is the precise amount of area of regions 16–21, 22 and 27. A clock management circuit may, for example, occupy a smaller area than is available in one of these areas such that some of the area is left unused in the final die layout and is wasted. Alternatively, the amount of area that is desired for the functionality of the clock management circuit exceeds the amount of area that happens to have been left above and below the BRAM/multiplier tiles. In such case, some clock management functionality that is desired cannot be provided in the ultimate FPGA.
There is also an amount of area left above and below the center four columns of BRAM/multiplier tiles. These areas are designated in FIG. 1 by reference numbers 17–20 and 23–26. These areas are, in one specific design, used to provide high speed transceivers. Each transceiver, however, requires more die area than is left in one of the areas. Accordingly, the available area is expanded in the horizontal dimension one pair of IOB tile spaces to the left and one pair of IOB tile spaces to the right. The result is T-shaped transceiver tiles 28–35 as illustrated FIG. 3. Although this solution provides the extra space required to implement the desired transceiver circuitry, expanding the available die area by four IOB tile spaces might not provide the exact additional amount of extra space desired. More space than is desired may be provided resulting in wasted die area, or too little space may be provided resulting in less transceiver functionality being provided than is desired. The resulting T-shaped region puts a greater burden on design and layout to conform to the odd shaped hole which adds to development costs.
There is also an amount of area left in the corner areas 12–15 of the die. These areas are, in one specific case, used to accommodate other miscellaneous circuitry. This miscellaneous circuitry may, for example, include configuration logic, encryption/decryption logic, global clock driver circuitry, a performance monitor, and boundary scan circuitry. Again, as was the case with the areas above and below the columns of BRAM/multiplier tiles, these areas may provide more space or less space than is desired for the miscellaneous circuitry. The result is either wasted die area and/or less functionality than is desired. This circuitry must be divided between the four corners which can adversely impact performance, required area, and design/layout effort.
In addition to the problems set forth above, there is also another problem with the tile layout technique of FIG. 1. It is often the case that a particular circuit is most efficiently laid out in a particular shape. That shape is often not a square. In the case of the SRAM-based CLB design used in the FPGA integrated circuit of FIG. 1, for example, the CLB circuitry is most efficiently laid out as a rectangle. Because there are a great many CLB tiles in the FPGA integrated circuit of FIG. 1, the layout of the CLB tiles is optimized such that the size of the overall integrated circuit is reduced. Consequently, the CLB tile has a rectangular shape. Using this rectangular CLB tile shape, however, gives rise to a layout inefficiency.
FIG. 4 (Prior Art) is a diagram that illustrates this layout inefficiency. The tiles within dashed line 36 represent tiles disposed along the leftmost side of FPGA integrated circuit 1. The tiles include a CLB tile 37, two IOB tiles 38 and 39, and an associated interconnection tile 40 disposed between the CLB tile and the IOB tiles. The IOB tiles are made of such a height that the combined height of the two stacked IOB tiles 38 and 39 is the same as the height 41 of CLB tile 37.
When the IOB tile is reoriented ninety degrees so that a pair of IOB tiles 42 and 43 is disposed along the upper side of FPGA die 1, however, the IOB tiles 42 and 43 do not have a combined width that is the same as the width of a CLB tile. The CLB tile is wider than it is tall. The combined width 44 of the vertically oriented IOB tiles 42 and 43 is therefore less than the width 45 of the associated CLB tile 46. Moreover, the IOI tile 47 disposed between CLB tile 46 and the two IOB tiles 42 and 43 is also reoriented ninety degrees and therefore also has a width 44 that is narrower than the width of the CLB tile. In one design, the same IOB tile layout is maintained for simplicity purposes and to provide identical performance on all four sides of the FPGA die. As a result, there is an extra amount of wasted space 48 associated with each CLB tile disposed along the top and bottom sides of FPGA die 1.
A solution is desired that minimizes and/or eliminates the above-described problems.


Embodiments of photoconductors and methods of making photoconductors for electrophotography are described, each embodiment comprising a complex between metal oxide phthalocyanine compound(s) and hydroxy compound(s) or amine compound(s). A metal oxide phthalocyanine pigment exhibits extended photoresponse between 850 nm and 1000 nm when it is milled with hydroxy binders or amine binders. The preferred hydroxy or amine binders include a modified poly-vinyl butyral binder unit containing a --CH.sub.2 CH.sub.2 OH unit, a cyclohexanol unit, a --CH.sub.2 CH.sub.2 NH.sub.2 unit, a --CH.sub.2 C.sub.6 H.sub.10 --NH.sub.2 unit, a --CH.sub.2 C.sub.6 H.sub.10 --CH.sub.2 NH.sub.2 unit, a --CH.sub.2 C.sub.6 H.sub.4 --NH.sub.2 unit, or other hydroxy or amine units. Optionally, hydroxy solvents or other hydroxy additives may also be included. Preferably, the pigment is dehydrated or hydroxy-starved before milling with the binder and solvents. The metal oxide phthalocyanine pigments and the hydroxy or amine groups form a complex which extends the photo-response of an OPC to wavelengths beyond about 850 nm, in order to achieve higher xerographic speed with higher resolution.

Electrophotography
The present invention is related to the photoconductor materials suitable for electrophotography. In the conventional electrophotographic process, electrostatic charge is utilized as the key component for recording information and reading out information. The recording process involves a photoconductive material that must be capable of: a) holding an electrostatic charge in darkness, and b) dissipating this electrostatic charge when exposed to a suitable light source of a wavelength that is strongly absorbed by the photoconductive material. The requirement of holding electrostatic charge can be realized if the photoconductor can exhibit a surface resistivity greater than 10.sup.13 ohm-cm in darkness, i.e. the photoconductor must be a good insulator in the dark. The requirement of releasing the electrostatic charge under light exposure is related to the significant decrease of the surface and the bulk resistivity during the process of light exposure. Thus, the requirements for the xerographic or electrophotographic photoconductor are different from that of photoconductors utilized in opto-electronic devices, such as photodiodes, solar cells, photodetectors, etc.
Electrophotographic processes have been successfully utilized in reprographic, copier, and duplicating products from low speed print-out, in the range of 1-3 pages per minute (ppm), to high speed print-out in the range of above 100 pages per minute.
Electronic Printing Using Electrophotography
Recently, electrophotography has become important in the design of electronic printers. Generally speaking, the electronic printing process utilizing electrophotography is mainly based on synchronizing of the light source, controlled by electrical signal output from a computing device such as computer. The electrical signal turns on or off the light source in order to produce many small dots, which can be developed into visible dots by electrophotographic ink or toner. The selection and collection of these dots form a halftone image.
It should be noted that the basic difference between copying machines and electronic printers, in this case, can be identified by the position at which the toner is deposited. In the copying machine, due to the reflection of the light source from the original image being copied, the toner is attached to the non-exposed area of the photoconductor, which leaves behind the light-exposed area as white background. On the other hand, in electronic printing using electrophotography, toner is attached to the light-exposed area, and thus the light source performs as a writing head or a print head.
Laser Printing Technology Components: Laser, Infrared (IR) Photoconductor
Recently, significant progress in electronic printing has been made, and solid-state opto-electronic devices such as a laser diode or a light emitting diode (LED) have become popular as the optical print head. The laser print head provides much smaller beam diameter than LED, and it is considered a key component for high resolution print-out.
Most laser printer products in the market today utilize single-beam laser scanners. These scanners typically utilize 780 nm wavelength edge-emitting laser diodes and, therefore, there is a lot of effort in development of electrophotographic photoconductors having a suitable response at 780 nm. These conventional photoconductors, typically called infrared or "IR" photoconductors, may include inorganic compounds such as amorphous silicone, dye-sensitized CdS, ZnO, TiO.sub.2 and As.sub.2 Se.sub.3. However, progress in development of organic materials has shown organic photoconductors to have some advantages over inorganic photoconductors in terms of photo-response, cost and ecological concerns.
High-resolution, High-speed Laser Printing Technology Components:
Even though the edge-emitting laser diode exhibits productivity and excellent performance in conventional laser printers products, its applications are limited in the area of higher speed and higher resolution printing. For higher speed printing above 600 DPI, for example, at 1200 DPI, 2400 DPI, or 4800 DPI, a multi-beam scanner is effective. Such multi-beam scanners use laser diodes that are surface-emitting lasers (SEL) instead of edge-emitting diodes. Thus far, the best-performing SEL is one that emits wavelengths longer than 780 nm, for example, wavelengths above 830 nm and preferably in the range of 850 nm-1000 nm.
Therefore, it is an important goal to develop an organic photoconductor (OPC) compatible with long wavelength multi-beam scanners. Such OPC's should be capable of very high speed in the wavelength range between about 850 and 1000 nm.

Photoconductor comprising a complex between metal oxide phthalocyanine compounds and hydroxy or amine compounds


A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a layer (215) of a first material in a fixed position relative to the wafer. The first material has a dielectric constant less than 3.6. The method also forms a photoresist layer in (216) a fixed position relative to the layer of the first material. The method also forms at least one void (220) through the layer of the first material in response to the photoresist layer. Further, the method subjects (106) the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen so as to remove the photoresist layer.

The present embodiments relate to semiconductor device fabrication and are more particularly directed to clean-up processing following photoresist patterning and etching of a low-dielectric constant material.
Integrated circuit technology continues to advance at a rapid pace, with many circuit technologies being implemented using semiconductor fabrication processes. With the advancement of semiconductor circuit fabrication, consideration is given to various aspects, including maximizing efficiency, lowering manufacturing cost, and increasing performance. With these goals in mind, low dielectric constant materials are now being considered as favorable for various insulating layers, sometimes referred to as interlevel dielectrics, used in a semiconductor circuit. In the past, such insulating layers were implemented using silicon dioxide (i.e., SiO2). Silicon dioxide has a dielectric constant, sometimes referred to in the art by the value k, on the order of 4.0. However, relatively lower dielectric constant values, such as on the order of 2.7 or 2.8, are now achieved by incorporating carbon within the silicon dioxide, thereby creating what is referred to in this document as a carbon-containing oxide. Carbon-containing oxides are sold under various trade names, such as organo-silicon glass ("OSG") commercially available from Novellus and black diamond commercially available from Applied Materials. Carbon-containing oxides may contain a considerable amount of carbon, such as on the order of 20 to 30 atomic percent (i.e., amount of carbon per atomic volume). The inclusion of the carbon drives down the dielectric constant which is a highly desirable goal. Specifically, by reducing the dielectric constant, such as is achieved by these carbon-containing oxides, semiconductor devices may be constructed using thinner films for insulating layers. This approach decreases device size and cost. Performance is also increased, such as by way of example where metal lines (e.g., copper) are formed closer together due to the thinness of the low-dielectric constant carbon-containing oxide which separates the metal from other layers/regions/devices.
While carbon-containing oxides have advanced various goals in the formation of semiconductor circuits, the present inventors have observed a considerable drawback in the use of such low dielectric constant (known as low k) materials. Specifically, during the formation of semiconductor circuits, and as also detailed later, it is known in the art to use photoresist materials as a mask for etching through an insulating layer, such as a silicon dioxide layer, to provide for example, vias, trenches, or other areas through which electrical contact may be made to various points covered by the insulating layer. Once the photoresist has served its masking purpose, it along with any related residue is removed. This process is sometimes referred to as a clean-up or a strip, and such removal has been achieved in the art by various different processes. However, the present inventors have observed that these traditional photoresist-removal processes, while effective for ordinary silicon dioxide, negatively affect a lower dielectric constant material such as a carbon-containing oxide. For example, one prior art photoresist-removal process uses an oxygen-based plasma at high temperature, that is, on the order of 250° C. However, when used with a carbon-containing oxide, the prior art use of an oxygen-based plasma causes the oxygen in the plasma to react with the carbon-containing oxide; in other words, rather than being inert with the carbon-containing oxide as is desired, the oxygen may cause the carbon-containing oxide to convert (lose carbon) in part and/or to diminish in width and/or in depth. Further complicating this issue is that manufacturers provide carbon-containing oxides that contain different percentages of carbon. As a result, the present inventors have observed a corresponding difference in the rate of carbon loss and width and/or depth loss of the carbon-containing oxide when the film is exposed to oxygen-containing plasma. For example, in the past rates of degradation were observed on the order of 25 Angstroms per minute exposure to oxygen-containing plasmas while more recently rates of degradation on the order of 100 Angstroms per minute have been observed. Thus, there is a need to reduce this degradation, and indeed such a need will continue should low k materials continue to show degradation on reaction with standard (e.g., O2, 250° C.) photoresist removal processes.
In view of the above, there arises a need to address the drawbacks of the prior art and to provide a method for effectively removing post-etch polymers and photoresist from low dielectric constant materials, as is achieved by the preferred embodiments described below.

Hydrogen plasma photoresist strip and polymeric residue cleanup process for low dielectric constant materials


An anti-splash device for use in a cup or other container can help prevent or minimize sloshing, splashing and other undesirable movement of fluids. In some embodiments, the device includes a main body portion having a plurality of openings. The device can also include one or more features that are configured to engage an interior wall of the cup or other container. In other embodiments, the anti-splash device can attach to the brim of a cup or to a lid. In other embodiments, an anti-splash device, a cup lid or any other components related to a beverage or food container comprises one or more finger guides that provide targeted points of contact when manipulating such a device.

1. Field of the Invention
This application relates in general to barrier members for containers, and in particular to anti-splash devices and lids incorporating same for cups and other beverage containers.
2. Description of the Related Art
Different types of lids for cups are known in the beverage container industry. Further, various types of lids exist for disposable cups or other containers (e.g., paper coffee cups, polystyrene, plastic or paper soft drink cups, etc.). Typically, such lids engage an upper rim of a cup to prevent the spillage of liquid or other substances contained within the cup. Some lids include an opening which is configured to provide access to the interior of the cup. However, a need exists for a device that minimizes sloshing, splashing and other undesirable movement of a liquid contained within a cup.

Anti-splash device for a beverage container


A processing system and associated method for vacuum evaporation of material onto a substrate. The processing system includes a loading chamber, a transfer chamber, and a thermal processing chamber arranged together to form a cluster tool. The cluster tool arrangement provides the system a continuous processing capability. The system also includes an evacuation system arrangement for evacuating the processing system to adequate processing pressure levels. The evacuation system arrangement includes a series of pumps, which are capable of maintaining the selected processing pressure levels for continuous thermal evaporation processing without the need for lowering the pressure to deep vacuum pressure levels.

1. Field of the Invention
The invention relates to vacuum deposition, and more particularly to a system and method for vacuum deposition in a cluster tool.
2. Description of the Related Art
Vacuum evaporation systems are well known in the art. FIG. 1A illustrates a typical vacuum evaporations system 10, which has magnetron sputtering and/or electron beam gun deposition capabilities. Magnetron sputtering and electron beam gun deposition are well established technologies for the coating of objects, such as semiconductor substrates. For example, sputtering is accomplished by bombardment with high-energy ions, usually ions of the rare gas argon (sputter gas), which is initiated by gas discharge processes. The ions of the sputter gas are subjected to controlled acceleration in the direction of the target at high kinetic energies, such that individual atoms can be knocked out of the target.
As illustrated in FIG. 1A, vacuum deposition system 10 includes a single closed chamber 12 operatively coupled to a roughing pump (not shown) and a diffusion type pump (not shown) through a series of valves 18a-18d. The sputter process is typically carried out in closed chamber 12 under conditions of deep vacuum pressures to ensure a long to mean free path length of the vapor particles (i.e., sputtered particles) as possible.
FIG. 1B illustrates a representative Pressure-Time profile for system 10. As shown, valves 18a-18d are closed to maintain the pressure in chamber 12 initially at atmospheric pressure. Valve 18a is opened to allow the roughing pump to lower the pressure in chamber 12 to a first pressure P0. Once the pressure is lowered to a level where the roughing pump is no longer effective, valve 18a is closed while valves 18b and 18c are opened to allow the diffusion pump to evacuate chamber 12 down to deep vacuum pressure P1. Since in most evaporation processes the process is not controlled, the deep vacuum pressure supplied by the diffusion pump is necessary to compensate for the increase in pressure that occurs at time T3, when the evaporation process begins. Also, since the mean free path of the sputtered particles is longest at pressures below pressure P0, the deep pressure is necessary to increases the length of time that the sputtered particles can be effectively deposited.
Unfortunately, because of the rapid increase in pressure during the evaporation process, the mean free path of the sputtered particles is changing from long to short very quickly, which can create a relatively non-uniform deposition. Another drawback of vacuum deposition system 10 is the inefficient use of the vacuum pumps. For example, the roughing vacuum pump is effective to evacuate chamber 12 up to pressure levels of from 0.7 Torrxe2x88x920.5 Torr. At pressure levels of 0.7 Torrxe2x88x920.5 Torr the efficiency of the mechanical pump is reduced dramatically because the movement of the remaining atmosphere in chamber 12 begins to take on molecular flow characteristics. This results in a substantial reduction in pumping speed as chamber 12 continues to be evacuated to about 0.2 Torr. The diffusion pump can then be used to further evacuate chamber 12 to the desired deep vacuum pressure levels. Unfortunately, since diffusion pumps, such as oil diffusion pumps, are ineffective when operated at pressures over 0.2 Torr microns, chamber 12 has had to be mechanically evacuated to the effective operating range of the diffusion pumps. The time taken to reduce the pressure in chamber 12 from 0.5 Torrxe2x88x920.2 Torr can be significant and can reduces production rates appreciably. In addition, once the evaporation process has begun, the pressure in chamber 12 rises significantly, which is usually above the operating range of the diffusion pump. This prevents the ability to continuously process substitutes.
In addition to the length of time required to evacuate chamber 12 to its effective operating levels, chamber 12 is opened to atmosphere between operations. The evacuation time is further extended since water and oxygen molecules, as well as other contaminants, are introduced into chamber 12. The presence of these contaminants can adversely effect the quality of the thin film layers. Purging chamber 12 of such molecules is possible, however, this further extends the production time.
What is needed is a vacuum deposition system that provides a continuous processing capability, reduces processing cycle times, and increases throughput per cycle.
The present invention provides a processing system and associated method for vacuum evaporation of material onto a substrate. In accordance with the present invention, the system includes an evacuation system arrangement for evacuating the processing system to adequate processing pressure levels. Advantageously, the evacuation system arrangement includes pumps, which are capable of substantially maintaining the processing pressure levels for continuous thermal evaporation processing without the need for lowering the pressure to deep vacuum pressure levels. The processing system further includes a loading chamber, a transfer chamber, and a thermal evaporation processing chamber arranged together to form a cluster tool. The cluster tool arrangement provides the system a continuous processing capability.
In one aspect of the present invention, a system is provided for vacuum depositing a thin film on a semiconductor substrate. The system includes a wafer processing chamber for receiving a substrate. The wafer processing chamber defines a transfer section and a processing section. The transfer section provides the system with the capability to insert and remove substrates on a continuous cycle. The processing section provides the system with a thermal evaporation processing capability in which the thin film is deposited on the substrate. A first evacuation device is provided in the system for evacuating the wafer processing chamber to an operating pressure. A second evacuation device is also provided for evacuating the wafer processing chamber to sustain the operating pressure throughout the wafer processing cycle. Once the processing of the substrate has occurred, the substrate can be transported between the transfer section and the processing section while the chamber is maintained at or near the operating pressure.
In another aspect of the present invention, a method is provided for vacuum depositing a thin film on a substrate. The method includes providing a wafer processing chamber for receiving a substrate. The chamber is substantially and continuously evacuated to sustain a selected operating pressure level during a thermal evaporation process, which may be conducted in the wafer processing chamber.
The present invention has many advantages over typical vacuum deposition systems and methods. For example, sputtered particles that emanate from the evaporated material during the evaporation process have a more average and consistent mean free path. Thus, the sputtered particles can be more uniformly deposited on the wafer. Because the present invention does not require deep vacuum pressure levels, the process chamber structure can be made smaller and more economically. By avoiding the need for deep vacuum pressures, the system of the present invention can be arranged in conjunction with a loading station and a transfer station to provide continuous cycling of substrates within a closed vacuum environment. Thus, exposure of the substrates to contamination is minimized and processing cycle times are reduced. The time needed to reduce the chamber pressure to deep vacuum levels and the need to backfill the chamber between processing cycles is removed, thus throughput of processed substrates can be increased.
These and other features and advantages of the present invention will be more readily apparent from the detailed description of the embodiments set forth below taken in conjunction with the accompanying drawings.


An image processing apparatus includes a first extraction section extracting first feature quantities from image data of an image of a subject captured in a first period; a first estimation section estimating a first average value of the first feature quantities on the basis of second feature quantities extracted from image data of an image of a registered subject captured in a second period and third feature quantities extracted from image data of an image of the registered subject captured in a third period; a second estimation section estimating a first distribution width indicating the width of dispersion of the first feature quantities with respect to the first average value on the basis of the second and third feature quantities; and a determination section determining whether or not the first feature quantities are within a predetermined range based on the first average value and the first distribution width.

1. Field of the Invention
The present invention relates to image processing apparatuses and methods, and programs, and more particularly, to an image processing apparatus and method, and a program, which are suitably used for personal authentication.
2. Description of the Related Art
Face image authentication in which personal authentication is performed using an image of the face of a person (hereinafter, also referred to as a face image) is known.
In known face image authentication, as shown in FIG. 1, a plurality of face images 11-1 to 11-3 of a person (a registered person) that have been previously captured and recorded in advance are compared with a face image 12 of a person to be identified that is newly captured for face image authentication, and it is determined whether or not the person to be identified is equal to the registered person.
Face image data of the previously captured face images 11-1 to 11-3 and face image data of the newly captured face image 12 are subjected to predetermined conversion processing, and the feature quantities of features of the faces of the persons are extracted from the individual sets of image data. Then, it is determined whether or not the feature quantity extracted from the face image data of the face image 12 is located within an area (hereinafter, referred to as an authentication area), which is constituted by the feature quantities extracted from the face image data of the face images 11-1 to 11-3, in a feature space.
If it is determined that the feature quantity extracted from the face image data of the face image 12 is located within the authentication area, the person to which the newly captured face image 12 belongs is authenticated as the registered person. In contrast, if it is determined that the feature quantity extracted from the face image data of the face image 12 is not located within the authentication area, the person to which the newly captured face image 12 belongs is identified as not being the registered person, and the subsequent processing is thus not carried out.
In addition, for face image authentication, since a plurality of previously captured face images are recorded in advance, the average of the feature quantities of the plurality of face images can be acquired, the average of the face images of a registered person can be estimated, and the width of dispersion of feature quantities can be estimated for each face image. Thus, the accuracy of face image authentication can be further improved.
In addition, an authentication apparatus is available in which statistical data representing general time-lapse changes in regions of faces and image data of a previously captured face image of a registered person are stored in advance and in which authentication is performed by transforming each region of the stored face image of the registered person on the basis of the statistical data (see, for example, Japanese Unexamined Patent Application Publication No. 09-134428). In this authentication apparatus, authentication is performed by comparing the previously captured face image of the registered person that has been transformed on the basis of the statistical data with a face image of a person to be identified newly captured for authentication.

Image processing apparatus and method, and program


An article having anti-microbial properties which includes a low temperature melt injected film containing an interconnected network of resolidified photosemiconductor and conductor particles. The anti-microbial film also may include adsorbent particles for adsorbing microorganisms. Methods of manufacture of such articles, methods for treating infections, and methods for sterilizing fluids, also are provided.

The sterilization of various bacteria, viruses and other microorganisms and the growth suppression of plants and algae is essential for many medical treatments, preventive hygiene, food processing and preservation, and industrial and domestic applications. Known sterilization techniques employ heat, electricity, microwaves, radiation, chemicals, toxicants, antibiotics, cold, ultraviolet and far-infrared rays, and high magnetic fields. Such sterilization techniques, however, generally require large equipment and/or facilities, and may damage the object being sterilized or become toxic to the patient undergoing treatment.
It has been proposed to employ photocatalytic materials (also referred to as photosemiconductors), such as titania (TiO.sub.2), as membranes and filters to eliminate organic pollutants and other impurities from a fluid source such as water. UV irradiation of the photocatalytic material in water at an appropriate wavelength (less than 400 nm for titania) generates excess electrons in the conduction band leaving behind positively charged holes in the valence band. It is suggested in U.S. Pat. Nos. 5,126,111 and 5,118,422 that the oxidizing holes generated in the valence band react with adsorbed H.sub.2 O or surface OH.sup.- groups to form extremely reactive OH radicals. The electrons react with molecular oxygen to form superoxide ions (O.sub.2 --) which subsequently leads to the formation of additional OH radicals. The OH radicals are considered essential to purification of the contaminated fluid.
The apparent choice of the prior art has been to form such photoreactive ceramic membranes in a sol-gel process which involves precipitation of a sol containing titania in solution (typically water or alcohol), removal of the solvent to create a semisolid gel and then calcination of the gel until a rigid porous membrane is formed. The ceramic membrane may be self-supporting or coated onto a mesh substrate prior to gellation. U.S. Pat. Nos. 5,227,342, 5,192,452, 5,035,784 and 4,892,712 are representative of conventional sol-gel formed photosemiconductor membranes. The sol-gel process suffers from several deficiencies. It is complicated, time consuming and expensive. The sol-gel process is not believed to be indicated for use with substrates made of paper, low melting point plastic mesh or other heat susceptible or liquid absorbable material which may be weakened, damaged or destroyed by the soaking, evaporating and firing steps required in sol-gel formation. The fired sol-gel membranes are likely to be brittle and susceptible to flaking and other deterioration of the photosemiconductive material, particularly after prolonged contact with the fluid being purified. Further, it would appear to be difficult to provide a porous membrane, necessary for filtration, having the required mechanical strength. Although sintering will stabilize the ceramic, the downside is a reduction in porosity due to grain growth.
An alternative and more advantageous approach for forming photocatalytic materials is generally described by Sakurada in Japanese patent nos. H3-60911, H3-65430 and H3-8448. Low temperature melt injection (LMI) is employed to create a thin, porous and flexible film of a particulate photosemiconductor on a heat susceptible substrate such as cloth, paper or plastic, previously electroless plated with a conductive metal such as nickel, without thermally damaging the substrate. The excited conduction band electrons, upon irradiation of the photosemiconductor film, migrate to the conductive metal where they act as a reducing agent. The positively charged holes in the photosemiconductor operate as an oxidizing agent. Organic materials, such as bacteria and viruses, which come into contact with the cloth are eliminated. When the film is immersed in water, the active species generated on the surface of the photosemiconductor particles and the electroless silver plated cloth migrate in the water to attack spatially separated microorganisms which are not within the intimate reach of the reactive surfaces. The photosemiconductor film and electroless plated substrate provide an improved sterilizing efficiency as compared to the photosemiconductor film alone. The metal conductor is believed to act as an electron attractor, delaying recombination of the conduction band electrons and valence band holes which are essential to destruction of the offending substances. Alternatively, the Sakurada references proposed coating the photosemiconductor particles with platinum or ruthenium oxide and then melt spraying the particles onto a mesh substrate.
The LMI technique involves entraining the fine photosemiconductor particles in a fast moving combustible carrier gas, igniting the gas to form a flame which melts the fine particles and carries the molten mist at high speed onto a cloth or other heat susceptible substrate. A cold accelerating gas injected from side ports jettisons the molten particles toward the substrate. The fine molten particles penetrate into and coat the mesh fibers of the substrate and then solidify very quickly, forming a binderless, flexible and porous photocatalytic film. Despite the fact that the ultrafine particles are melted at temperatures in excess of 1000.degree. C., and sometimes as high as 3000.degree. C., a heat susceptible substrate such as cloth or paper does not become damaged. LMI is simpler, faster and less expensive than the sol-gel process described in the aforementioned prior art, and results in a flexible, yet durable, photocatalytic film which can be coated onto thermally frail materials without adverse consequences. The high porosity of the LMI film enhances catalysis which is surface area dependent.
Investigation of the LMI process has revealed that the ability to adsorb microorganisms from a fluid to allow sufficient time for sterilization of the antimicrobial film would be beneficial. It also has been discovered by applicants that the reactive ability of the anti-microbial film can be enhanced by ensuring that an aqueous environment is maintained around the sterilizing material. The versatility and efficiency of the prior art LMI anti-microbial films also were believed to be enhanceable. It was not apparent from the prior art how to accomplish these newly discovered goals, which are achieved by the present invention as delineated below.

Low temperature melt injected anti-microbial films, articles containing such films and methods of manufacture and use thereof


A detector for detecting a characteristic and a speed of a vehicle includes a first magnetic field sensor. The first magnetic field sensor includes a magnetically variable resistor that changes resistance in response to being exposed to a magnetic field. A bias is applied to the magnetically variable resistor and a change in the resistance thereof in response to an applied magnetic field is detected by an amplifier. The amplifier generates a first analog signal indicative of changes in the resistance of the magnetically variable resistor. A differentiating circuit differentiates the first analog signal and produces a first output that changes binary state in response to detecting a predetermined change in the differentiated first analog signal. A counter accumulates values at a predetermined rate and a microprocessor stores values of the counter corresponding to each change in the binary state of the first output of the differentiating circuit. The microprocessor converts the stored counter values into a first time series profile corresponding to changes in the first output of the differentiating circuit and accumulates and stores a count of a characteristic of the passing vehicle based on the first time series profile. A second time series profile is produced from counter values accumulated in response to the differentiating circuit producing a second output.

1. Field of the Invention
This invention relates to an apparatus and method for detecting vehicles or other magnetically permeable masses and measuring according to number, classification and speed and/or length.
2. Prior Art
Prior art traffic counters utilize road tube detection and magnetic loop sensing to detect the presence and/or movement of vehicles. The road tube counter comprises a flexible length of pressure tubing laid across the roadway. At one end of the tube, a pressure sensor is positioned to detect changes in the air pressure as wheels compress the tube. Disadvantages of road tubes are their susceptibility to damage and wear and their inability to count low speed vehicles. Magnetic loop sensors comprise a loop or coil of wire buried in a shallow trough in the roadway. The inductance of the coil due to the disturbance of the earth's magnetic field changes when a vehicle passes by. The change in inductance can be measured electronically. Disadvantages of the magnetic loop detector include installation requires tearing up the road, the detectors are susceptible to damage upon thermal expansion of the highway and they are unable to discriminate between closely passing vehicles.
Still another type of magnetic permeable sensor is described in U.S. Pat. No. 5,408,179 to Sampey et al. In this sensor, a ferromagnetic strip has a conductive winding wrapped about it. A small permanent magnet is positioned adjacent one end of the ferromagnetic strip. The magnet biases the ferromagnetic strip in a linear portion of its BH curve where the slope is substantially linear. An electronic circuit generates an analog signal indicative of the inductance of the winding as the earth's magnetic field is disturbed. Another electronic circuit digitizes the analog signal at spaced time intervals to produce a series of digitized values. A microprocessor processes the digitized values to produce a first time series profile that characterizes the presence and/or motion of the magnetic permeable mass. Another sensor, similar to the above-described sensor, is spaced apart from the above-described sensor a fixed distance in the direction of the travel of the magnetically permeable mass. The output of the second sensor is also digitized by the electronic circuit to produce another series of digitized values. The microprocessor processes these digitized values to produce a second time series profile and determines equivalent positions in the first time series profile and second time series profile.
A disadvantage of this sensor is that a 100 Khz excitation signal utilized to stimulate the conductive winding also produces undesirable noise in other components of the electronic circuitry.
It is, therefore, an object of the present invention to provide a new apparatus and method for detecting characteristics of a magnetically permeable mass and detecting a speed of a magnetically permeable mass that avoids the above disadvantages and others. Still other objects of the invention will become apparent to one of ordinary skill in the art upon reading and understanding the ensuing detailed description.

Method and apparatus for analyzing traffic and a sensor therefor


A backside-illuminated imaging device is provided and includes: a plurality of charge accumulating areas in the semiconductor substrate which accumulate the electric charges; and a plurality of filters above a backside surface of the semiconductor substrate corresponding to the respective charge accumulating areas. The plurality of filters includes different color filters which transmit different color components of the light from one another and luminance filters each having a spectral characteristic correlated with a luminance component of the light, the plurality of charge accumulating areas includes first charge accumulating areas corresponding to the respective color filters, and second charge accumulating areas corresponding to the respective luminance filters, and the second charge accumulating areas includes a third charge accumulating area having a size larger than those of the first accumulating areas.

1. Field of the Invention
The present invention is related to a backside-illuminated imaging device that performs imaging by illuminating light from a back side of a semiconductor substrate to generate electric charges in the semiconductor substrate based on the light and reading out the electric charges from a front side of the semiconductor substrate.
2. Description of Related Art
Various kinds of backside-illuminated imaging devices are proposed, each of which performs preformed imaging by illuminating light from a back side of a semiconductor substrate to generate electric charges in the semiconductor substrate based on the light, accumulating the electric charges in the charge accumulating areas formed on a front side of the semiconductor substrate, and output signals in accordance with the electric charges accumulated in the charge accumulating areas to the outside of the device by CCD or CMOS circuit or the like formed on the front side of semiconductor substrate (e.g., JP-A-2005-142221).
Also, JP-A-11-355790 discloses an imaging device in which a first photosensitive element group including photosensitive elements arrayed in a square lattice pattern for detecting luminescent components of light and a second photosensitive element group including photosensitive elements arrayed in a square lattice pattern for detecting hue components of the light are arranged on a silicon substrate in such a manner that the first and second photosensitive element groups are shifted from each other at adjacent positions so as to form a so-called honeycomb array pattern.
The backside-illuminated imaging device disclosed in JP-A-2005-142221 is a CMOS type imaging device. If the backside-illuminated imaging device is a CCD type imaging device, light receiving areas can be made larger since it is not necessary to provide CCD on the back side of the semiconductor substrate. However, if the light receiving areas become large, the distance between the charge accumulating areas located adjacent to each other becomes short. As a result, there are many possibilities that mixed colors may readily occur in peripheral portions of the backside-illuminated imaging device, in which incident angles of light are steep.
When a color filter array capable of realizing the device characteristics disclosed in JP-A-11-355790 is used as a color filter array provided above the backside surface of the semiconductor substrate, there is a probability that at the peripheral portion of the imaging device, light passing through the filter provided above a photosensitive element for detecting a hue component may be entered into a photosensitive element for detecting a luminance component and also light passing through the filter provided above the photosensitive element for detecting a luminance component may be entered into the photosensitive element for detecting a hue component. If light to be originally entered into a photosensitive element enters into its adjoining photosensitive element that is for detecting a luminance component, this is not any major problems, since the sensitivity of the photosensitive element for detecting a luminance component is high. However, if light to be originally entered to a photosensitive element for detecting a luminance component enters into a photosensitive element for detecting a hue component, S/N of signals acquired from the photosensitive element for detecting a hue component is deteriorated and adverse influences given to image qualities are increased.


An apparatus and a method for enhancing decision-making using left to right to left hemisphere guidance includes a housing, two buttons which are coupled to the housing and four recording media with their respective instructions to a user. The first instruction is to think about a subject until an issue related to the subject comes to his mind, then to make a choice from alternatives of the issue and thereafter the user presses one of the two buttons to designate his choice of one of the alternatives of the issue. The second instruction is to look inside his head and ask himself if he is right while he is inclined to a new discovery. The third instruction is to see a picture of the subject in his head and while he is daydreaming the picture to listen for thoughts in his mind about how he is right, then to listen for thoughts in his mind about the other side of the issue, with both sides of the issue in his mind to listen for changes over a period of time. The fourth instruction is to verbalize his conclusions.

The field of the invention is psychological devices for enhancing the making of decisions.
U.S. Pat. No. 4,900,256 teaches an object-directed emotional resolution apparatus which uses speech and electronics technology coupled with psychological techniques to further emotional development and stress reduction.
U.S. Pat. No. 4,923,428 teaches an interactive, articulated talking toy which talks and moves certain of its body parts under microprocessor control on the basis of the program material selected from a tape storage device incorporated in the body of the toy. The material selected is determined by a human's response to questions asked by the toy. The material stored on tape contains both audio and data. The processor chooses a particular one of a possible three audio tracks stored on tape on the basis of the specific response or nonresponse made by a human.
U.S. Pat. No. 4,300,763 teaches a psychological game device having a small box-like housing which has cabinet with a panel facing a player called the SPEAKER and another panel facing a player called the LISTENER. The SPEAKER panel mounts two push buttons labeled TRUTH and ALMOST TRUTH. The LISTENER panel mounts two push buttons labeled BELIEVE and ALMOST BELIEVE. The bottom of the cabinet includes a recessed panel with scoring indicators labeled CREDIBLE consisting of three light emitting diodes (LEDs) and FORGET-IT consisting of three LEDs. A reset button is also provided. The top surface of the cabinet contains an on/off switch, a START push-button, and an LED indicator. A timer circuit, started by the START button, illuminates the indicator LED for either a preselected time period or a sequence of random duration time periods. Logic circuits contained within the cabinet are controlled by the SPEAKER and LISTENER push buttons to provide a basic game sequence of three periods. The device may be used with a wide variety of games limited only by the imagination of the players.
U.S. Pat. No. 4,717,343 teaches a method of conditioning a person's unconscious mind in order to effect desired change in the person's behavior which does not require the services of a trained therapist. The program as viewed by the person's unconscious mind acts to condition the person's thought patterns in a manner which alters that person's behavior in a positive way.
U.S. Pat. No. 4,762,494 teaches a psychotherapy 9 device which includes a body member, a pair of arms, legs, and a head connected to the body member. The pyschotherapy device is in the general configuration of a child-like human figure. The head includes a pair of expressionless eyes and nose which are permanently affixed to the face and means are connected to the face adjacent to and generally below each of the permanent eyes for releasably receiving indicia of tears. During pyschotherapy of a child patient, the patient may be invited to apply or remove tears to reflect a current or past mental state.
U.S. Pat. No. 4,812,126 teaches a new method of learning by use of a machine which interacts with the user to guide the user through a programmed series of questions. The system is based on finding trouble spots in the users logic or feelings by observing the users skin response to questions. The computer will ask the user a question. The computer selects the next question based on his answer to the previous question and guides the use through a
U.S. Pat. No. 4,931,934 teaches a system and method for measuring the emotional response of a subject to a chosen focus in order to reliably produce objective data representing that emotional response. The subject is put in contact with the chosen focus and the emotional response of that subject to the chosen focus is determined in order to provide initial response emotions and the intensities of these emotions. Utilizing the initial response emotion intensities and the baseline emotion intensities, clarified emotion intensities are determined for use in a variety of decision making applications.
U.S. Pat. No. 4,734,038 teaches a method which includes selecting the particular ideal behavior to be achieved, defining the steps to be taken to effectuate the modification, assigning a mnemonic device for each step to promote mental identification of the step and providing a visual image of a role model for behavioral emulation. The role model acts out the defined steps.

Apparatus and method for enhancing decision-making


A first motion vector is estimated by using a first frame and a second frame that follows the first frame. A support frame is generated from at least either the first or the second frame by using the first motion vector. The support frame is divided into a plurality of small blocks. Motion vector candidates are estimated by using the first and second frames, in relation to each of the small blocks. A small block on the first frame, a small block on the second frame and the small blocks on the support frame are examined. The small block on the first frame and the small block on the second frame correspond to each of the motion vector candidates. A second motion vector is selected from the motion vector candidates, and points the small block on the first frame and the small block on the second frame which have the highest correlation with each of the small blocks on the support frame. An interpolated frame is generated from at least either the first or the second frame by using the second motion vector.

1. Field of Art
The present invention relates to a method of frame interpolation and an apparatus using the method of frame interpolation, for efficiently interpolating frames between successive frames of a reproduced moving-picture signal to increase the number of frames to be displayed per unit of time in reproduction of a moving-picture signal.
2. Related Art
In general, frame interpolation efficiently interpolates an additional frame between frames in a moving-picture signal carrying a plurality of frames, to increase the number of frames to be displayed per unit of time.
A recent frame interpolation technique is to produce a frame to be interpolated based on motion vectors obtained by block matching, one of fundamental technique in motion estimation.
Block matching is to detect motion vectors from a block in an image of a reference frame, the block having the highest correlation with small blocks of a base frame.
Such a frame interpolation technique is disclosed, for example, in Japanese Patent Laid-Open Publication 2000-224593.
The publication discloses intra-block area division based on block matching to aim at further accurate frame interpolation.
The known motion-compensated frame interpolation techniques perform motion compensation to image data pointed by a fixed terminal of a motion vector with respect to an initial point of the motion vector. The location of the initial point is, however, different from its original location due to motion-vector operations in interpolation. This causes a gap or superimposition in a frame to be interpolated.
Such a disadvantage is overcome by a technique disclosed in the Japanese Patent No. 2528103.
Disclosed in this patent is frame interpolation based on correlation between an anterior first frame and a posterior second frame. The correlation is geometrically found with a specific block of a frame to be interpolated as the center between the first and the second frame.
This frame interpolation technique requires no operations after obtaining motion vectors, different from the several known techniques described above, thus directly producing frames to be interpolated.
In addition, imaginary square grids on each frame to be interpolated in this frame interpolation technique do not cause a gap or superimposition in the frame to be interpolated, which otherwise occur like the above technique.
Nevertheless, this frame interpolation technique could assign an error motion vector in a still background, different from a motion vector to be assigned, due to relatively not so high correlation between objects in a first frame and a second frame.
This erroneous motion-vector assignment results in displaying the background on an image area on which the object should be displayed.
As discussed, one known motion-compensated frame interpolation technique is disadvantageous in causing a gap or superimposition in a frame to be interpolated.
The other known interpolation technique solving this problem is still disadvantageous in displaying a background on an image area on which an object should be displayed.
The known interpolation techniques therefore have difficulty in producing high-quality frames to be interpolated.

Frame interpolation and apparatus using frame interpolation