A resistive memory device includes a lower electrode disposed on a substrate, first and second resistance layers respectively disposed on opposite sides of the lower electrode and exhibiting resistance variation at different voltages, respectively, and an upper electrode disposed on and the first and second resistance layers.

1. Technical Field
The present invention relates to a non-volatile memory device and, more particularly, to a resistive memory device, a system including the same and a method for fabricating the same.
2. Description of the Related Art
With rapid development of digital telecommunication and electronic appliance technologies, conventional memory devices such as a dynamic random access memory (DRAM) or a flash memory ill soon reach their physical limits in obtaining higher integration and higher device performance. For example, a flash memory representing a non-volatile memory uses a high voltage in programming and erase operations and has physical limits due to interference between adjacent cells in being scaled down. Moreover, the flash memory suffers from a low operating speed and high power consumption. As an alternative to conventional memory devices, different types of memory devices are being developed to store data based on different characteristics such as phase transition, magnetic field variation, and the like as follows. As an example, a phase-change memory device may store information by varying resistance of a material by causing a phase change thereof.
A ferroelectric RAM (FeRAM) has been developed but raises a concern with respect to its material stability. A magnetic RAM (MRAM) has also been developed, but it has a complicated fabrication process, a multilayer structure, and a small reading/writing margin. As an alternative to the above-discussed memory devices, a resistive random access memory (ReRAM) has been developed to store data based on resistance variation of a thin film according to voltage applied to the thin film. Theoretically, the ReRAM does not suffer from deterioration even after numerous writing and erasing operations and exhibits normal operation characteristics even at a high temperature. In addition, the ReRAM exhibits non-volatile properties and provides excellent data stability. Furthermore, the ReRAM operates at a high operation speed of 10 to 20 ns in varying resistance variation of 1000 times or more upon application of an input pulse thereto.
Since a variable resistance layer of the ReRAM device is generally a single layer, the ReRAM can be highly integrated and operate at a high speed. Further, typical integration technologies for complementary metal oxide semiconductor (CMOS) can be applied to the ReRAM. Here, the variable resistance layer is generally formed of an oxide. Specifically, the oxide includes a binary oxide and a perovskite oxide. Recently, the variable resistance layer of the ReRAM is often made of a metal-doped perovskite oxide.
As an example of ReRAM devices, Korean Patent Publication No. 2006-106035 discloses a ReRAM device that includes a resistance layer formed of a Cr-doped perovskite oxide of SrZr3.
Korean Patent Publication No. 2004-63600 discloses a ReRAM device which includes an iridium (Ir) substrate, a barrier layer of Ta, TaN, Ti, TiN, TaAlN, TiSiN, TaSiN, TiAl or TiAlN formed on the substrate, and a Pr0.7Ca0.3MnO3 (PCMO) thin film formed as a resistance layer on the barrier layer.
However, since these memory devices are single level devices which allow a device formed at an intersection of an upper data line and a lower data line to store single on/off information, such memory devices have lower data storage capacity per unit area than multi-level devices.
Therefore, it is useful to have a memory device which may be fabricated through a simple fabrication process without surface contamination, is applicable to various memory devices including non-volatile memory devices, and permits adjustment of various resistance states through control of an operating voltage.


Various methods and apparatuses associated with the serving of data from a wireless mobile phone, including a wireless mobile phone, are described herein.

Advances in semiconductor, processor, telecommunication, networking and related technologies have led to the ubiquitous availability of a wide range of general and special purpose computing devices. In particular, wireless mobile phones are now widely available and employed for voice communication. In some cases, wireless mobile phones have replaced desktop phones as the primary voice communication devices for many users.
At the same time, as the capabilities and functionality of wireless mobile phones continue to grow, wireless mobile phones have become the major repositories of the users' data. Today, very often, not only contacts and calendar data are stored on the wireless mobile phones, increasingly, word documents, presentations, including the viewers of the corresponding applications are stored thereon. In other words, increasingly, wireless mobile phones are also being employed to perform data processing functions that were once performed on traditional data processing devices, such as laptop or desktop computers.
However, by virtue of the portability characteristic, which inherently means small display screens and small keypads, wireless mobile phones, when used as data processing/computing devices, remain relatively user-unfriendly.
The term "wireless mobile phone" as used herein refers to the class of telephony devices equipped to make and receive calls wirelessly, notwithstanding movement, as long as the device is within the communication reach of a service or base station of a wireless network service provider. Unless specifically excluded, these terms are to include the analog subclass as well as the digital subclass (of all signaling protocols).

This patent is subject to a terminal disclaimer.

Serving data/applications from a wireless mobile phone


An apparatus for identifying differences in the visual and recorded appearance of colors and gray tones illuminated by light sources having different spectral distribution and having: a first image with illumination, with separate and different color elements and with gray scale elements, apertures in the first image adjacent to the elements, a second image with illumination having a plurality of separate elements of color and gray scale, corresponding to the elements of the first image so that the elements on the second image are viewable through the apertures in the first image, with corresponding color and gray scale elements adjacent to one another in the first and second images, and a method of comparing light quality using such apparatus.

Since man started using fire as a light source, whether this was a wood fire, candlelight, oil lamps or gaslight, these sources of illumination produced relatively smooth distribution of spectral energy across the human visible spectrum (400 to 700 nm). Even when Edison invented the incandescent light bulb, the tungsten element, glowing with heat, produced light having a similarly smooth, full distribution of energy. Consequently, when colored objects were illuminated by any of these light sources the colors looked essentially similar to the average viewer, whose vision compensated for changes in color temperature, i.e. the excessive blue of daylight and lower levels of blue in heat generated illuminants.
With the invention of illuminants having discontinuous spectral distribution such as fluorescent tubes, differences in the appearance of certain colors became very noticeable when viewed under such discontinuous sources. This became particularly relevant with the introduction of color film and television in the 1940s, but was not initially a problem because the prime artificial light sources were full spectrum arc lamps and quartz halogen, the latter a more efficient use of tungsten.
In the 1970's, to reduce air-conditioning loads, studios started using fluorescent and HMI lighting. Since 2010, LED light sources have become increasingly popular in cinema and TV production, because they are lightweight, very efficient and generate even less heat than other types. The downsides are that the light emitted by LED illuminants is discontinuous, there are few if any standards and that LEDs deteriorate with age.

Light source comparator and calibration apparatus


An emitter switching configuration having at least one bipolar transistor and a MOS transistor having a common conduction terminal and a Zener diode inserted between a control terminal of the bipolar transistor and the common conduction terminal. A monolithic structure is also provided that is effective in implementing the emitter switching configuration.

1. Field of the Invention
The present invention relates to an emitter switching configuration and, more specifically, the invention relates to an emitter switching configuration comprising at least a bipolar transistor and a MOS transistor having a common conduction terminal and to an integrated structure effective to implement the emitter switching configuration to be integrated on a single chip.
2. Description of the Related Art
As it is well known, in applications requiring a high switching speed of a switch implemented by means of a bipolar transistor, this bipolar transistor is associated with a MOS transistor, inserted in series with an emitter terminal of the bipolar transistor in the configuration commonly known as emitter switching, schematically shown in FIG. 1 and globally indicated with 1.
The emitter switching configuration 1 essentially has a bipolar transistor T1 with a collector terminal C1, an emitter terminal E1, and a control or base terminal B1. The emitter terminal E1 of transistor T1 is connected to a drain terminal D1 of a MOS transistor M1 having also a source terminal S1 and a control or gate terminal G1.
Advantageously, by using the emitter switching configuration 1, the lock of the MOS transistor M1 allows transistor T1 to be rapidly turned off since it cuts the emitter current thereof.
Moreover the emitter switching configuration 1 can be integrated in a single chip, forming the MOS transistor M1 in a diffusion related to the emitter terminal E1 of the bipolar transistor T1. The MOS transistor M1 will be N or P-channel according to whether the emitter terminal E1 is of the N or P type.
The MOS transistor drain terminal D1 therefore corresponds to the emitter terminal E1 of the bipolar transistor T1. The so-formed MOS transistor M1 is particularly a VDMOS transistor, i.e., a double-diffusion vertical MOS transistor.
Being the emitter terminal region of a bipolar transistor an heavily doped semiconductor region, in order to integrate a MOS transistor therein a particular monolithic structure is to be used, such as the one shown in FIG. 2.
Particularly, the monolithic structure 2 has a semiconductor substrate 21 of a first conductivity type, for example of the N type, effective to form the collector terminal C1 of the bipolar transistor T1.
A first buried layer 22 of a second conductivity type, for example of the P type, is formed on the substrate 21 and a second buried layer 23 of the first conductivity type.
The monolithic structure 2 thus has an epitaxial layer 24 of the first conductivity type covering the first 22 and second 23 buried layers.
A double-diffusion region of the second conductivity type 25 is formed in the epitaxial layer 24, corresponding to body or bulk regions of the MOS transistor M1, wherein a high-concentration double-diffusion region 26 of the first conductivity type is formed, corresponding to the source region S1 of the MOS transistor M1. The monolithic structure 2 also includes polysilicon structures 27 effective to form the gate terminal G1 of the MOS transistor M1.
The monolithic structure 2 is completed by a contact structure 28A effective to form the source terminal S1 of the MOS transistor M1, as well as a contact structure 28B effective to form the base terminal B1 of the bipolar transistor T1 and in contact with the first buried layer 22 by means of convenient wells 29 of the second conductivity type.
It is worth noting that in the monolithic structure 2 the buried layers 22 and 23 form the emitter and base regions of the bipolar transistor T1, these regions being buried by means of a higher-resistivity epitaxial layer 24 wherein the body regions 25 of the MOS transistor M1 are diffused. Moreover, the epitaxial layer 24 is the drain region of the MOS transistor M1.
The emitter switching configuration 1 being integrated by means of the monolithic structure 2 is driven as an insulated gate device, essentially of the power MOS type. However, the emitter switching configuration 1 has advantageously a lower resistance in conduction conditions than known power MOS devices. This advantage is further increased if the inverse voltage value to be undergone by the device increases, i.e., the voltage rating.
Particularly, the monolithically-integrated emitter switching configuration 1 has a low-voltage MOS transistor M1, and it has thus a low conduction resistance value Ron. Besides, in lock conditions, the entire inverse voltage applied to the emitter switching configuration 1 is supported by the base-collector junction of the bipolar transistor T1 without affecting thus the body-drain junction of the MOS transistor M1.
The body-drain junction of the MOS transistor M1 is stressed only in the turn-off step. In fact, in the turn-off step, the entire current of the bipolar transistor T1 collector terminal C1, being no more allowed to flow through the emitter terminal E1 thereof which is locked by the MOS transistor M1 turn-off, is obliged to leave the base terminal B1 of the bipolar transistor T1 by passing thus through the first buried layer 22 and wells 29. The body-drain junction of the MOS transistor M1 thus undergoes an inverse voltage VMOS given by:VMOS=Ic*RB
where RB is the resistance of the second buried layer 22 and of the wells 29 and Ic is the current to be switched.
It is thus evident that, if the value of the current Ic to be switched is too high, the body-drain junction of the MOS transistor M1 can breakdown, interrupting thus the bipolar transistor T1 turn-off step. The latter, undergoing high inverse voltages with simultaneous high current flowing, can be thus seriously damaged or even destroyed.
Definitely, the highest current Ic value, or current capability, which can be switched by the bipolar transistor T1 in the emitter switching configuration depends on the breakdown voltage value of the MOS transistor M1.
In other words, the increase in the "current capability" of the bipolar transistor T1 is obtained at the detriment of the conduction resistance Ron of the MOS transistor M1 and thus of the whole monolithic structure 2 in the emitter switching configuration.

Emitter switching configuration and corresponding integrated structure


Conductive electronic device structures such as a conductive housing member that forms part of an antenna may be tested during manufacturing. A test system may be provided that has a capacitive coupling probe. The probe may have electrodes. The electrodes may be formed from patterned metal structures in a dielectric substrate. A test unit may provide radio-frequency test signals in a range of frequencies. The radio-frequency test signals may be applied to the conductive housing member or other conductive structures under test using the electrodes. Complex impedance data, forward transfer coefficient data, or other data may be used to determine whether the structures are faulty. A fixture may be used to hold the capacitive coupling probe in place against the conductive electronic device structures during testing.

This relates generally to testing, and more particularly, to testing electronic device structures for manufacturing faults.
Electronic devices such as portable computers and cellular telephones are often provided with wireless communications capabilities. For example, electronic devices may use long-range wireless communications circuitry such as cellular telephone circuitry and short-range wireless communications circuitry such as wireless local area network circuitry.
In some devices, conductive housing structures may form part of an electronic device antenna. The performance of this type of antenna may depend on how accurately the conductive housing structures are manufactured. Excessive variations in the size and shape of conductive electronic device housing structures may have a negative impact on the performance of antennas formed using the structures. Variations in conductive electronic device structures of other types may also impact device performance.
It would therefore be desirable to be able to provide ways to test electronic device structures such as conductive electronic device structures that form parts of antennas and other structures.

Testing system with capacitively coupled probe for evaluating electronic device structures


A system for transporting and unloading dry chemicals in a container including a removable bulk head and a liner. The bulk head has a top and a bottom. The bulk head is tilted when installed in the container such that the top of the bulk head is at the back of the container and the bottom of the bulk head is recessed into the container. The bulk head has an opening at a bottom center portion thereof. The liner has an opening and fits within the container. The liner has a funnel extension fitting through the opening in the bulk head. The funnel extension has a diameter which decreases toward the opening in the liner, with increasing distance from the bulk head. The funnel extension extends across substantially the entire width of the container. The container has a height, and the removable bulk head has a length extending between the top and the bottom, which length is greater than the height of the container. The system also has an adapter which attaches to the liner. The adapter has a hollow main body having an input and an output and a hollow interior. The opening in the liner fits inside the input of the main body. The adapter has an access door attached to the main body between the input and the output for allowing access to the interior of the main body.

1. Field of the Invention
The present invention relates in general to shipment of dry chemicals. More particularly, the present invention relates to an improved system for unloading dry chemicals from a liner within an intermodal container.
2. Description of the Related Art
Dry chemicals are sometimes shipped in intermodal containers. The containers are referred to as "intermodal" because they can be shipped via different modes, such as truck, rail car and ocean liner. More particularly, the intermodal containers may be placed on a chassis to form a trailer which can be pulled behind a tractor. That is, the container plus the chassis form the trailer. Of course, when the container is shipped on sea, the chassis is not attached. To ship the dry chemicals in the container, a liner bag is inserted into the container. The liner bag may be a polymer liner and formed of a material such as polyethylene. The liner can be recycled. The dry chemicals may be in the form of a powder or pellets. An example of a powderous chemical is purified terephthalic acid (PTA). An example of a pellet form chemical is polyethylene terephthalate (PET). To fill the container, there are two openings at the top and back of the liner. Dry chemical is blown into the liner through one of the openings in the liner. Dry chemical may be blown with an inert (perhaps nitrogen) gas. The inert gas is vented from the container through the other opening in the liner. Any residual dry chemical is then filtered from the inert gas before venting.
Hereinafter, the end of the container which would be positioned away from the driver, toward the doors is referred to as the "back" of the container. The dry chemical is loaded and unloaded from the container with the doors of the container open. With the doors open, the liner must be supported by some means, from the back of the container. Conventionally, wood on metal supports were built into the container every time a new liner was to be installed. The supports were in the form of a framed bulk head. To remove the liner, the supports were completely dismantled. Building the bulk head was time consuming and the strength of the bulk head could vary.
To unload the chemical from the container, an outlet is located at the back bottom of the liner. The outlet may be attached to a conduit leading to unloading equipment. Various make-shift approaches, some more successful than others, were used to attach the outlet to the unloading equipment. The container was then tilted, either on its own power or by tilting a ramp on which the trailer was parked. The container could be tilted up to about 45.degree.. The dry chemical may weigh up to 50,000 pounds. For safety reasons, it may be important that a substantial amount of the dry chemical be removed from the liner before the container reaches the 45.degree. tilt. The weight may be too great to be supported by the hand-made bulk head.
One characteristic of dry chemical powders, and all powders for that matter, is the "angle of repose." The "angle of repose" is the steepest angle which the material can form under a given set of conditions. For example, if a powder is poured onto a flat surface, one angle of repose is the angle the resulting mound on the flat surface makes with the flat surface. Generally speaking, the larger the angle of repose, the more difficult it is to achieve flow. For example, if a powder is poured onto a flat surface, next to a ledge and the powder has a small angle of repose, the powder will simply flow off of the ledge. On the other hand, if the powder has a large angle of repose, the powder may form a steep mound next to the ledge, and will not flow off of the ledge. The angle of repose varies from powder to powder. Moreover, in a single powdered chemical, such as PTA, the angle of repose varies from manufacturer to manufacturer.
In the conventional system for transporting and unloading powdered chemicals, the liner conformed to the shape of the container and thus was substantially box-shaped. FIG. 1 is a cross-sectional view of a conventional liner, taken from a plane parallel to and below a top of the liner. The conventional liner had an outlet 2 for unloading the chemical. The outlet is at the bottom middle of the back of the container. Even when the container was completely tilted (FIG. 1 represents a tilted container), powder remained in the liner, extending from ledges 2a of the outlet 2 to the trailer wall 4. The height H to which the powder remains on the wall (depth in a horizontal container) is determined by the angle repose.
Furthermore, in the conventional system, there was not an immediate drop-off after the outlet. That is, when the container was horizontal, the outlet emptied into a conduit which was horizontal for a short distance d before becoming vertical to drop off the back of the container. FIG. 2 is a cross-sectional view of the conventional liner, taken through line II--II of FIG. 1. FIG. 1 shows the liner as being substantially empty and tilted, whereas FIG. 2 shows the liner as being substantially full and horizontal. As can be seen from FIG. 2, when the container was horizontal and the powder had a relatively large angle of repose, there was no discharge of powder. As discussed above, the powder must flow before the container is fully tilted. FIG. 3 is the same view as FIG. 2, but with the container and the liner inclined at an angle with a horizontal to show how the powder flows. As can be seen in FIG. 3, after tilting, powder began to flow. However, a portion P of the outlet was not being used. Thus, the effective diameter of the outlet was reduced by the portion P and discharge of powdered chemical was slow. The buyer of the powdered chemical may require large quantities of the chemical. However, with the conventional transporting and unloading system, unloading the chemical from the liner could require up to six hours. This time increased receiving costs, limited the rate at which the buyer could receive the chemical and thus limited production in the buyer's plant.

System for transporting and unloading dry chemicals


A fast transient simulator of SOI MOS circuits uses fast and accurate SOI transistor table models. The simulator uses a representation of a circuit with partitions. Each of partitions is simulated separately for a short time step by numerically solving differential equations describing its transient behavior. Behavior of the whole circuit is simulated in an event driven way where each event corresponds to an integration time step for each partition. Instead of body voltage, the simulator implements a transformation and uses body charge as an independent variable in order to obtain high accuracy and high speed of simulation. Construction of SOI transistor table models results in speed and accuracy enhancements. This transformation allows the reduction of the number of table dimensions exploiting the fact that SOI transistor backgate capacitance is approximately constant.

Fast transient transistor simulation programs are important aids in computer aided design (CAD) of very large scale integrated (VLSI) circuits. A fast transient simulator differs from accurate circuit simulators like SPICE in its ability to simulate very large circuits at significantly higher speed, at the expense of some accuracy. Fast transient simulators provide the ability to simulate at transistor level circuits containing hundreds of thousands of transistors with high speed on the orders of hundreds time faster than accurate circuit simulators such as SPICE. The goal of fast transient simulators is to compute waveforms of voltages at circuit nodes and currents through circuit elements. Fast transient simulators are used when it is required to simulate circuits at an accuracy higher than that can be achieved by gate and switch level simulators, and with a speed higher than SPICE-like simulators.
Fast transient simulation of a Metal Oxide Semiconductor (MOS) transistor circuit usually partitions the given circuit into D.C. connected components (DCCC). Each MOSFET model is cut across its transistor gate. The interaction between partitions is simplified by considering only the dependence of MOSFET channel current on its gate voltage. Each partition is simulated independently for a short time interval called the time step. During this time interval, it is assumed that all voltages at the boundary nodes of the partition are known. Usually they are computed through linear approximation, by interpolation and extrapolation. Based on such simplifications, the behavior of each partition is simulated independently for some short time interval called a time step. Time steps can be different for different partitions and they can vary during simulation for getting the desired trade-off between speed and accuracy. The partitions that do not change their state or change it slowly are evaluated with much longer time steps. This technique improves simulation speed as compared to traditional transistor level circuit simulators like SPICE. Because of the partition mechanism and the use of different time steps, the time points at which the simulator recomputes the states of the partitions are different for each partition. The simulator arranges reevaluation of partition states in an event driven manner. The simulator plans reevaluations of partition states according to its internal processes and changes of voltages at the partition boundary. For this purpose, it uses an event queue where it schedules partitions for reevaluation. From this queue, the simulator gets partitions for reevaluation according to their time schedule.
The accurate behavior of each partition is described by a system of non-linear differential equations. One of the most accurate techniques to simulate the behavior of non-linear circuits is to use a modified nodal analysis for computing the system of equations, trapezoidal or backward Euler integration algorithm for their numerical integration, and Newton-Raphson iterations for computing voltage and current values at each time point. Such an approach is common for implementing accurate circuit simulators like SPICE. In order to get higher simulation speed, this technique is simplified in many ways. For example, the forward Euler integration algorithm can be applied, or the Newton-Raphson iterations can be substituted by approximate linearization of non-linear elements at each time point. Any type of simplification is at the cost of accuracy of the simulation results. Fast simulators differ among themselves in their selection of trade-off between speed and accuracy.
For simulating partitions, fast circuit simulators similar to traditional SPICE-like circuit simulators require a model of MOS transistors. For SPICE simulators, an accurate transistor model is specified by very complex formulae for computing currents and charges of each transistor terminal as a function of terminal voltages. Computation of these complex formulae significantly slows down circuit simulation. In order to have high simulation speed, fast transient circuit simulators usually use a simplified transistor model. The simplified transistor model can be either analytical or table-based. Analytical models are usually not accurate enough for submicron short channel MOS transistors. Table models usually are able to provide much higher accuracy with higher computation speed. In the simplest straight forward approach, a table model is a collection of tables, each of which provides values of transistor terminal currents or charges as functions of terminal voltages. The tables are usually computed by using an accurate transistor level simulator like SPICE.
The structure of a conventional bulk MOS transistor 10 is shown in FIG. 1. Transistor 10 has a substrate 12, a gate oxide 14, a gate 16, a drain 17 and a source 18. The electrical model 34 of transistor 10 is shown in FIG. 2 and has four terminals: a drain 37, a source 38, a gate 36 and a substrate 39. Therefore, a straight-forward model approach results in four charge tables and four current tables. Each of the tables has four arguments or inputs, viz. the four terminal voltages. Unfortunately, tables organized in such a manner are too large to use efficiently in any simulator. Therefore, fast transient simulators use different techniques to simplify their table models. The first simplification comes from the fact that transistor behavior does not change if we change all terminal voltages by the same value. In other words, transistor behavior is invariant to voltage shift. This simplification allows a reduction in the number of table arguments by one as one of the four terminals can be treated as a reference terminal. Other facts that are used for model simplification are charge and current conservation laws. The conservation laws make it sufficient to have models only for three terminal currents and charges and allow computation of the current and charge of the fourth terminal so that total charge and current ate zero. Unfortunately, these simplifications are not enough to make transistor models sufficiently efficient. Therefore, fast transient circuit simulators often use additional approximations for simplifying a transistor table model. For bulk MOS transistors, it is common to assume that transistor terminal capacitances are linear, meaning that they do not depend on transistor terminal voltages. This assumption permits using just average values of transistor terminal capacitances instead of a table of terminal charges as functions of terminal voltages. Currents of bulk MOS transistor table models can be simplified by ignoring substrate and gate currents as they are orders of magnitude less than transistor channel current and do not affect circuit behavior drastically. Simulators can simplify the model of bulk transistor channel current by considering the channel current as a function of two variables: (1) the voltage between drain and source and (2) the effective gate voltage. The effective gate voltage is defined as a difference between gate-to-source voltage and a threshold voltage, predetermined for each transistor. Threshold voltage is considered as a function of body voltage and may be modeled by a separate one-dimensional table. This approach follows from the simple analytical model of a bulk MOS transistor. Thus, instead of one three-dimension table for channel current, two smaller tables are used: one two-dimensional table and one single-dimensional table. Such table reduction costs some accuracy of the model. For pure digital MOS circuits, especially for CMOS circuits, the foresaid reduction still retains sufficient accuracy and allows the simulator to compute good approximation of circuit delays and power consumption. However, this model is not accurate enough for many circuits, for example circuits using many pass gates, circuits having very large D.C. connected components, and circuits that are very sensitive to accuracy, such as the PLL (Phase Locked Loop) circuits.
Additional challenge and problem for fast circuit simulation are SOI circuits that are becoming more and more popular in high speed and low power VLSI designs. The structure of an SOI MOS transistor 20 is shown in FIG. 3. An SOI transistor is similar to a bulk transistor but it is manufactured on an insulator layer and completely isolated from one to another by the same insulator. SOI transistor 20 has a substrate (backgate) 22, a buried oxide 24, a body 26, a gate oxide 27, a gate 28, a source 29, a drain 30 and a shallow trench isolation 32 around the perimeter. Because of the SOI structure, transistor capacitances are much smaller than the ones in a comparable size bulk transistor. The reduced capacitances make an SOI transistor significantly faster and reduce power consumption. Thus SOI transistors are very attractive for high performance and low power circuits. SOI transistors also have other benefits like latch-up immunity, lower radiation susceptibility, etc. Unfortunately, designing VLSI circuits with SOI transistors is more difficult than with bulk transistors because SOI transistors have more complicated behavior than bulk transistors. In bulk transistors, the fourth terminal is a VLSI substrate that is permanently connected to ground or a supply voltage VDD. The counterpart terminal in an SOI transistor is a body that has very small capacitance and usually is not connected to any other circuit node. Because of that, the body potential (voltage) varies significantly during circuit operation due to such effects like capacitive coupling with other circuit nodes, leakage, and impact ionization currents. These effects significantly influence SOI transistor behavior by changing its threshold voltage.
Another complication with the SOI transistor model arises due to its usage with different types of body connections. The most common case, and also the most difficult to simulate, is the floating body configuration wherein the transistor body is not connected to any other circuit node. The floating body type SOI transistor configuration provides the smallest transistor area but makes its behavior less predictable. The potential of a floating body can vary due to variation in the switching frequency, thus giving rise to an effect known as the history effect. This effect makes logic gate delay depend on gate switching history. Another type of SOI MOSFET configuration has its body and source connected together that makes its behavior similar to a bulk MOS transistor. An example of this configuration is illustrated in FIG. 4 wherein a structure 50 has an SOI transistor having an n+ drain 52, a gate 54, an n+ source 56 and a p+ tie 58 to tie the body with the source 56. The third type of SOI transistor configuration has a separate body contact that can be connected to any node of the circuit. An example of this configuration is illustrated in FIG. 5 wherein a structure 60 has an SOI transistor having an n+ drain 62, an n+ source 64, a gate 66 and a p+ body contact 68. Thus, transient simulators of SOI circuits should handle all these three types of transistors.
The electrical model of an SOI transistor is shown in FIG. 6. SOI transistor 40 has five terminals as compared to four terminals of a bulk MOS transistor. Transistor 40 has a gate 42, a drain 44, a source 45, a body 46 and a backgate (substrate) 48. The additional terminal makes an SOI model significantly more complex and results in significant increase in model's table size.
Simulation of SOI circuits is more sensitive to numerical errors because the history effect has a very large characteristic time constant as compared to logic gates' switching time. Even small numerical errors in body charge computation are accumulated resulting in prediction of wrong circuit delays. Because of that, accurate transient circuit simulators simulate SOI circuits much slower than bulk circuits that makes circuit design with SOI transistors even more difficult.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.

Fast simulation of circuitry having SOI transistors


Preparation of highly monodispersed polymeric hydrophilic nanoparticles having a size of up to 100 nm (in which may have drug substances encapsulated therein. The process comprises subjecting a mixture of an aqueous solution of a monomer or preformed polymer reverse micelles, a cross linking agent, initiator, and optionally, a drug or target substance to polymerization. The polymerized reaction product is dried for removal of solvent to obtain dried nanoparticles and surfactant employed in the process of preparing reverse micelles. The dry mass is dispersed in aqueous buffer and the surfactant and other toxic material are removed therefrom.

1. Field of the Invention
This invention relates to a process for the preparation of highly monodispersed polymeric hydrophilic nanoparticles with or without target molecules encapsulated therein and having sizes of up to 100 nm and a high monodispersity.
2. Description of the Related Art
Following an administration of a drug in a living system the active substance is distributed throughout the body as a function of its physicochemical properties and molecular structure. The final amount of drug reaching its target site may only be a small fraction of the administered dose. Accumulation of drug at the non-targeted site may lead to adverse effect and undesirable side reactions. Therefore, targeting of drug to specific body sites is necessary.
One way of modifying the biodistribution of drugs in the body is to entrap them in ultrafine drug carriers. Among these carriers, liposomes, nanoparticles and pharmacosomes have been extensively studied. The use of liposomes as drug targeting agents is found to be limited due mainly to the problems of low entrapment efficiency, drug instability, rapid drug leakage and poor storage stability. With the aim of overcoming these problems, the production of polymeric nanoparticles has been investigated since the last two decades. Nanoparticles are defined as solid colloidal particles ranging in size from about 10 nm to 1000 nm.
A large number of studies have been reported on recent advances in drug targeting possibilities and sustain release action with nanoparticles encapsulating drugs. In vivo studies have also been reported with special attention to the reticuloendothelial system (RES). Some in vivo studies concerning nanoparticles administration by oral and ocular routes have also been reported in the literature with respect to the possible improvements of bioavailability. These polymeric nanoparticles should be non antigenic, biocompatible and biodegradable.
The important characteristics of the particles used for targeting at specific body sites were found to be influenced mainly by two factors: (i) the size of the nanoparticles and (ii) the surface characteristics of the nanoparticles. Particles smaller than 7 .mu.m and specially nanoparticles are not filtered in the lung and their biodistribution is dependent on their interaction with reticuloendothelial system (RES). Biodegradable nanoparticles are mainly taken up by the Kupffer cells in the liver while small amount of these particles go to macrophages in spleen and bone marrow. Bone marrow uptake and targeting at other sites can be modified drastically by reducing the particle size. Nanoparticles of 200 nm diameter and above have biodistribution dependent on their interaction with RES. The distribution, however, can be reversed if the particle size is made much smaller (i.e. below 100 nm) and particle surfaces are made hydrophilic. As an example, it has been found that if these particles are separated into three size ranges -60 nm, 150 nm and 250 nm and their surfaces are rendered hydrophilic by adsorbing poloxamer type of surfactants, then the small sized particles with maximum surface hydrophilicity are mostly taken up by cells other than Kupffer cells and as shown in FIG. 1 of the accompanying drawings. Specifically FIG. 1 shows size dependant uptake of nanoparticles, uncoated and coated with poloxamer surfactant by bone marrow. These small particles in the blood serum do not adsorb serum protein through opsonisation and as a result, their circulation time in blood is considerably increased. Hydrophobic particles are removed from the circulation very rapidly due to opsonisation. Nanometer sized particles with hydrophilic surface remain in blood for longer period of time so that targeting at specific sites may be facilitated.
At present, nanoparticles for drug encapsulation are prepared by methods involving either polymerisation of dispersed monomers or a dispersion of preformed polymers in emulsion in presence of desired drug. The methods known in the art for the preparation of nanoparticles are (i) dispersion polymerisation method, (ii) emulsion polymerisation method, (iii) dispersion of synthetic polymer nanospheres in emulsion, and (iv) interfacial polymerisation technique. In all these methods emulsions of oil-in-water are used and the polymer is formed or dissolved in the oil phase. As a result, the polymeric materials are always hydrophobic because they are to be soluble in oil and the particles formed are nanoparticles of larger size (i.e., above 100 nm) because the average size of the emulsion droplets is mostly 100 nm and above diameter. More over, since the emulsion droplets are highly polydispersed, the nanoparticles formed have broad spectrum size range and these are also highly polydispersed. Thus, in such known processes (i) one cannot prepare nanoparticles of subcolloidal size and (ii) the emulsion medium demands that the polymeric materials should be hydrophobic.

Process for the preparation of highly monodispersed polymeric hydrophilic nanoparticles


An image forming device has image forming units 3-6, a transfer belt 7, a position detection unit 19, a concentration sensor 23, and an adjustment unit. A toner image is formed on the surfaces of the image forming units 3-6, and transferred onto the transfer belt 7. The position detection unit 19 detects a predetermined position on the surface of the transfer belt 7. On the predetermined position, the concentration sensor 23 detects first information relating to the color of the surface of the transfer belt 7. The concentration sensor 23 detects second information relating to the color of the pattern image that is formed on the predetermined position. The adjustment unit adjusts toner concentration at the time of forming an image based on the first information and the second information detected by the concentration sensor 23.

1. Field of the Invention
The present invention generally relates to an image forming device. More specifically, the present invention relates to an image forming device, such as a copying machine, a printer, a facsimile machine, and the like.
2. Background Information
Conventionally, in color image forming devices, the method used in transferring a toner image onto a sheet of paper is by respectively superimposing the black, yellow, magenta, and cyan color toner images onto the transfer belt before combining the toner images thereof onto the sheet of paper.
In this type of image forming device, the toner concentration is adjusted because sometimes due to a degradation of toner or the like, the intended color concentration of an image may not be produced.
A method of adjusting toner concentration is disclosed in Japan Patent Application Publication JP-11-258872, for example. In this method, first, a pattern image is formed using the image forming unit, which is adjusted in order to maintain the intended color concentration. Then, the difference between the color concentration of the pattern image that is actually formed and the intended color concentration is investigated. In the toner concentration information of an image that is formed by the image forming unit, this difference is reflected in order to form images with the intended toner color concentration. The adjustment of the toner concentration of an image to be formed is made by adjusting the bias of the transfer roller, and the like, that is included in the image forming unit.
However, in the conventional method for adjusting the toner concentration, the color concentration on the surface of the transfer belt is not taken into consideration. Therefore, for example, when the color concentration on the surface of the transfer belt changes due to a stain or toner that is attached thereon, proper adjustment of the toner concentration cannot be made.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved image forming device. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.

Image forming device, method for adjusting toner concentration, programs, and recording media of the same


The present disclosure discloses a method for identifying a cell, including: determining, for a cell under test during a charge and discharge process, a number N of measured values of OCV and a number N of net cumulative throughputs corresponding to the number N of measured values of OCV; for an ith target cell, obtaining a number N of calculated values of OCV corresponding to the number N of measured values of OCV, and obtaining an OCV mean square error between the number N of measured values of OCV and the number N of calculated values of OCV; and determining that the cell under test is the ith target cell, when the OCV mean square error between the cell under test and the ith target cell is a minimum mean square error among a number M of OCV mean square errors.

During the use of a battery or a cell, the state of charge (SOC) is an important index, which indicates the proportion of the electric quantity that can be provided actually in the current state to that can be provided in a fully charged state. Through this parameter, the remaining capacity of the battery in the current state can be known, and thus it is convenient for the battery management system (BMS) to issue various instructions to the battery. The OCV-SOC curve for a cell is an important reference curve for the cell, and the remaining capacity of the cell can be known by measuring the open circuit voltage (OCV).
With the rapid development and replacement of batteries such as automotive batteries, more and more batteries have entered a phrase of recycling and echelon use. In the process of the recycling and echelon use of cells, there is a situation where basic information, such as the material, architecture and OCV-SOC curve for some cells, is lost or not recorded, and for cells with such basic information lost or not recorded, it is impossible or difficult to determine information such as the type of these cells.

Method, apparatus, and computer storage medium for identifying cell

Contemporary Amperex Technology Co., Limited


This invention relates generally to a unitized heavy duty axle suspension and steering system for self powered chassis. The steerable suspension system embodied in this invention takes advantage of the unique location and connection of the steering gear to the Pitman arm and its location and connection by the primary drag link to the bell crank assembly below and in-between the frame rails and above the axle. The primary drag link is the same length as the suspension arms and is located in a parallel plane to them when the vehicle is moving forward in a straight line. This unique arrangement virtually eliminates the phenomenon known as bump steer and allows the wheels to turn at a high degree of steer, dramatically increasing maneuverability for long wheel base chassis. The assembly with all of the steering controls and components between the rails and above the axle allow for unitized assembly and very straightforward installation.

1. Field of the Invention
This invention relates generally to a heavy duty axle unitized suspension and steering system for self powered chassis. The system embodied in this invention takes advantage of the unique location and connection of the steering gear to the Pitman arm and its location and connection by the primary drag link to the bell crank assembly, below and in-between the frame rails and above the axle. The primary drag link is located in a parallel plane and is the same length as the suspension arms when the trailer is moving forward in a straight line. This unique arrangement virtually eliminates the phenomenon known as bump steer and allows the wheels to turn at a high degree of steer, dramatically increasing maneuverability for long wheel base chassis.
Bump-steer is a change in toe angle caused by the suspension moving up or down. The effect of bump-steer is for the wheel to toe-in or toe-out when the suspension moves up or down. This toe change or "steering" occurs any time the suspension moves, whether it is from body roll, brake-dive, or hitting a bump in the road. Bump steer is undesirable because the suspension is steering the vehicle instead of the driver.
2. Prior Art
U.S. Pat. No. 5,220,972 Proia 1993 modifies existing self-tracking suspension systems that utilize toque rods to maintain the perpendicular orientation of the axle with respect to the center-line of the vehicle. Rubber bushings are installed on the ends of these torque rods to permit very limited angular movement as the vehicle turns. Multiple axle vehicles mount torque rods parallel to the longitudinal center-line of the vehicle body. This invention angles the forward ends of the torque rods inwardly towards the vehicle's center-line. Such angling of the torque rods allows the wheels to pivot as the trailer turns reducing wear on the drive tires and the road surface.
U.S. Pat. No. 5,234,067 Simard 1993 attempts to resolve long standing instability problems when dual axles are connected with leaf spring assemblies which are conventionally solved by the addition of torque rods as described in Proia above. His invention uses front and rear leaf-springs on each side that are aligned with each other and positioned forwardly and rearwardly of an equalizer beam. The front leaf-spring assembly has a front end pivotally attached by a pin to the vehicle frame and a rear end connected by a shackle to the front end of the equalizer beam. The rear leaf-spring assembly has a front end pivotally attached by a pin to the rear end of the equalizer beam and a rear end connected by a shackle to the frame of the vehicle. This allows road irregularity forces to be efficiently transmitted and stable without the use of torque rods.


In a warewashing machine, a power wash zone is adapted to function either in a pot washing mode or in a warewashing mode. A valve controls the flow of water into an upper manifold. In the pot washing mode when the flow of water into the upper manifold is decreased, the flow into a lower manifold is correspondingly increased. This results in an increase flow rate and pressure striking a pot.

Description of Related Art
In commercial warewashing (dishwashing systems such as sold to hotels, resorts, universities and the like) there are typically several zones through which passes dishes, glasses, flatware, etcetera to be cleaned. For example, there may be circulating pre-wash, high power pre-wash, power wash, power pre-rinse and final rinse. Typically, in commercial establishments, pots are either washed by hand or, more likely, in a separate pot washing machine. For cleaning pots in a machine, a much higher pressure is needed to properly clean or scour the inside of the pot compared to lower pressure that is used for dishes. Therefore, in a commercial establishment, a separate pot washing machine must be utilized.
U.S. Pat. No. 5,131,419, Roberts, recognized this problem, namely that a single washing apparatus should be able to function in multiple modes and particularly be interchangeable between a warewashing mode and a pot washing mode. However, as disclosed in Roberts, a relatively complex control system was necessary to achieve this result.


Devices and methods are disclosed for managing and/or treating body tissues obstructing a hollow body lumen, such as the prostatic lobe tissues obstructing the urethra. A scaffolding may be provided with opposing tissue-engaging portions and at least one expansion member configured to transition between a compressed configuration having a reduced distance between the tissue-engaging portions and a deployed configuration having an increased distance between the tissue-engaging portions.

Benign prostatic hyperplasia (BPH) is a common disease that affects 50-60% of men over age 50 and 80-90% of men over age 70. Oral medications have been used as the first-line therapy in the U.S. and many European nations. However, prostate size generally continues to increase with time in most men, leading to further urethral obstruction. Correspondingly, procedural intervention usually becomes necessary at some point during the pharmacologic management of BPH. Current procedural intervention includes transurethral resection of the prostate and targeted removal of tissue by the application of directed energy, such as ablation with laser, microwave or radio frequency energy or other vaporization techniques. However, such procedures which have been associated with complications such as bladder neck contracture, impotence, retrograde ejaculation and others. In addition, most of these procedures require general or regional anesthesia use and may require hospitalization. As a less-invasive alternative, the use of long-term urethral stents for management of BPH has been attempted but has been found to suffer from encrustation and pose difficulty in removal, making the practice unpopular among urologists. Other alternatives such as an indwelling urinary catheter or intermittent self-catheterization have been associated with significant patient discomfort and inconvenience, as well as raising the risk of urinary tract infection and hematuria. Thus, such techniques may be considered unappealing to many patients and are generally unsuitable for long-term BPH management. As a consequence, patients may have a difficult time in deciding among the conventional choices of procedural management. Furthermore, many patients may experience an overactive bladder and/or exhibit clinical voiding symptoms that are not clearly consistent with BPH, making the diagnosis of BPH (and subsequent management) challenging to the urologists. With the lack of suitable treatment options, elaborate urodynamic evaluation or testing may often be necessary.
In view of the above, it would be desirable to provide devices and methods that provide adequate management of BPH without the complications and problems of the current procedural modalities noted above, including the removal of the obstructing prostate tissues, the placement of stents, the use of an indwelling urinary catheter or intermittent self-catheterization. Likewise, it would be desirable to provide management of BPH in an outpatient or office-based setting while reducing the need for anesthesia. Further, it would be desirable to provide techniques for managing BPH with reversible clinical effects. Still further, it would be desirable to provide BPH management in clinically challenging diagnostic situations without the need for elaborate urodynamic evaluation. The present disclosure details methods and devices that satisfy these and other needs, as well as being simple and inexpensive to manufacture, simple to use and robust in use, and that be used with a variety of hollow body structures such as the pro static urethra to restore or increase patency.

System and method for increasing a cross-sectional area of a body lumen


A multistage space-efficient electrostatic collector cleans a gas flowing therethrough along a gas flow path having a first stage provided by a first corona discharge zone along the gas flow path, and a second stage provided by a second corona discharge zone along the gas flow path and spaced along the gas flow path from the first corona discharge zone. A method is provided for increasing residence time within the corona discharge zone of gas flowing through an electrostatic collector.

The invention relates to electrostatic collectors or precipitators, including for diesel engine electrostatic crankcase ventilation systems for blowby gas for removing suspended particulate matter including oil droplets from the blowby gas.
Electrostatic collectors or precipitators, including for diesel engine electrostatic crankcase ventilation systems, are known in the prior art. In its simplest form, a high voltage corona discharge electrode is placed in the center of a grounded tube or canister forming an annular ground plane providing a collector electrode around the discharge electrode. A high DC voltage, such as several thousands volts, e.g. 15 kV, on the center discharge electrode causes a corona discharge to develop near the electrode due to high electric field intensity. This creates charge carriers that cause the ionization of the gas in the gap between the high voltage electrode and the ground electrode. As the gas containing suspended particles flows through this region, the particles are electrically charged by the ions. The charged particles are then precipitated electrostatically by the electric field onto the interior surface of the collecting tube or canister.
Electrostatic collectors have been used in diesel engine crankcase ventilation systems for removing suspended particulate matter including oil droplets from the blowby gas, for example so that the blowby gas can be returned to the atmosphere, or to the fresh air intake side of the diesel engine for further combustion thus providing a blowby gas recirculation system.
The corona discharge electrode assembly commonly used in the prior art has a holder or bobbin with a 0.006 inch diameter wire strung in a diagonal direction. The bobbin is provided by a central drum extending along an axis and having a pair of flanges axially spaced along the drum and extending radially outwardly therefrom. The wire is a continuous member strung from back and forth between the annular flanges to provide a plurality of segments supported by and extending between the annular flanges and strung axially and partially spirally diagonally between the flanges. The inside of the drum is hollow.
The present invention provides a compact, multistage, space-efficient electrostatic collector. The present construction improves utilization of space within a package allowing for a reduction in package size or an increase in flow rating for the same package size. Effective residence time is increased by incorporating corona generation and particle collection in an inner annular passage by using the formerly unused hollow inside of the drum.
Customer requirements continue favoring smaller packaging in underhood components in internal combustion engine applications. These customer demands can be better met if all available space is used to maximum extent. The present invention not only provides better utilization of available space but also provides improved performance including within a small space-efficient package size. The improved performance is provided by increasing charged particle residence time. In one aspect, collecting zones are provided both inside and outside of the electrode drum, increasing residence time without lengthening the electrode, thus providing longer residence time, higher corona discharge efficiency, and better space efficiency. The use of both inner and outer charging and collection stages effectively increases residence time by increasing the effective length of the electrode and corona discharge zone.

Multistage space-efficient electrostatic collector


A semiconductor device includes a first n-type source/drain region 48a and a second p-type source/drain region 48b formed on a semiconductor substrate 20 away from side surfaces of first and second gate electrodes 39a, 39b at a first interval W4 respectively, a second n-type source/drain region 48c and a first p-type source/drain region 48d formed on the semiconductor substrate 20 away from side surfaces of third and fourth gate electrodes 39c, 39d at a second interval W3, which is wider than the first interval W4, respectively, and third and fourth insulating sidewalls 43c, 43d extended onto source/drain extensions 42c, 42d on both sides of third and fourth gate electrodes 39c, 39d from edges of upper surfaces of the third and fourth gate electrodes 39c, 39d respectively.

1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Description of the Related Art
In recent years, as the result of a reduction in power consumption of the mobile equipment, and the like, a demand for lower power consumption in semiconductor devices such as LSIs, and so on, which are incorporated into the equipment, is increasing. As the semiconductor device capable of meeting such demand, there is the MOS transistor having the dual gate structure. The dual gate structure is a MOS transistor having such a structure that an n-type impurity is introduced into a gate electrode of an n-type MOS transistor and a p-type impurity is introduced into a gate electrode of a p-type MOS transistor. A threshold voltage of the transistor can be lowered if the same impurity as the conductivity type of the channel is introduced into the gate electrode in this manner, and thus the power consumption of the transistor can be suppressed.
However, only a single kind of dual gate transistor of the identical driving voltage is rarely integrated in an actual semiconductor device. Commonly, the transistor having the dual gate structure is employed as the normal transistor for the logic circuit whose driving voltage is low, and this normal transistor is embedded with a high-voltage transistor. For instance, in the driver IC in the liquid crystal panel, the high-voltage driving transistor used to apply a voltage to alignment electrodes of the liquid crystal panel is formed together with the normal transistor for the logic circuit.
The semiconductor device in which the normal transistor having such dual gate structure and the high-voltage transistor are integrated together is disclosed in FIG. 32 in Patent Literature 1.
FIG. 1 to FIG. 4 are sectional views showing the essential part of processes in a method of manufacturing a semiconductor device disclosed in Patent Literature 1.
First, as shown in FIG. 1A, element isolation insulating films 2 are buried in element isolation trenches 1a of a silicon substrate 1, and then a thermal oxide film 3 and an undoped polysilicon film 4 are formed sequentially on the silicon substrate 1.
A normal transistor forming region I and a high-voltage transistor forming region II are defined on the silicon substrate 1. The thermal oxide film 3 in the high-voltage transistor forming region II is formed thicker than that in the normal transistor forming region I.
Then, as shown in FIG. 1B, first to fourth gate electrodes 4a to 4d are formed by patterning the polysilicon film 4.
Then, as shown in FIG. 1C, first to fourth n-type source/drain extensions 5a to 5d and first to fourth p-type source/drain extensions 5e to 5h are formed by the ion implantation using the first to fourth gate electrodes 4a to 4d as a mask. In this case, individual implantations of the p-type impurity and the n-type impurity in this ion implantation are executed by using resist patterns (not shown), and then the resist patterns are removed after the ion implantation is ended.
Then, as shown in FIG. 1D, an insulating film 6 is formed on the overall surface, and then a resist pattern 7 is formed on the insulating film 6 in the high-voltage transistor forming region II. The resist pattern 7 has first and second windows 7c, 7d on the gate electrodes 4c, 4d respectively. In contrast, the normal transistor forming region I is not covered with the resist pattern 7 and is exposed.
Then, as shown in FIG. 1E, the insulating film 6 is etched back while using the resist pattern 7 as a mask. Thus, the insulating film 6 is shaped into an insulating sidewall 6a positioned besides the first to fourth gate electrodes 4a to 4d respectively, and also the thermal oxide film 3 located under the gate electrodes 4a to 4d is shaped into first to fourth gate insulating films 3a to 3d respectively. Also, the insulating film 6 under the first and second windows 7c, 7d is etched by the etching-back. Thus, first and second openings 6c, 6d are formed in the insulating sidewall 6a and thus upper surfaces of the third and fourth gate electrodes 4c, 4d are exposed from these openings 6c, 6d.
Also, out of the gate electrodes 4a to 4d, an extended portion 6b that corresponds to the resist pattern 7 is formed to extend from the insulating sidewall 6a positioned besides the third and fourth gate electrodes 4c, 4d in the high-voltage transistor forming region II respectively.
Meanwhile, prior to this step, the thermal oxide film 3 is formed in the high-voltage transistor forming region II to have a thickness that is thicker than that in the normal transistor forming region I. For this reason, in the etching-back step, even if an etching time is set to remove completely the thermal oxide film 3 and the insulating film 6 from the normal transistor forming region I, it is possible that the etching is not completed owing to the etching residue of the thick thermal oxide film 3 in the high-voltage transistor forming region II and the thermal oxide film 3 still remains on the silicon substrate 1.
Therefore, in order not to leave the thermal oxide film 3 in the high-voltage transistor forming region II, an etching time is set in the etching-back step such that the thermal oxide film 3 and the insulating film 6 can be removed completely from the high-voltage transistor forming region II.
However, the over-etching is caused by such etching time in the normal transistor forming region I in which the thermal oxide film 3 is formed thin. Thus, as shown in FIG. 1E, upper surfaces of the element isolation insulating films 2 are etched and their height is lowered than that of the silicon substrate 1.
Then, as shown in FIG. 1F, a resist pattern (not shown) having windows from which n-type MOS transistor forming regions are exposed is formed. Then, the n-type impurity is ion-implanted simultaneously into the silicon substrate 1 and the first and third gate electrodes 4a, 4c through the windows. As a result, first to fourth n-type source/drain region 8a to 8d are formed in the silicon substrate 1 on the side of the gate electrodes 4a, 4c, and also the conductivity type of the gate electrodes 4a, 4c is set to the n type. Also, according to the same processes as above, first to fourth p-type source/drain regions 8e to 8h are formed and at the same time the conductivity type of the gate electrodes 4b, 4d is set to the p type.
In this ion implantation, since the impurity is blocked by the insulating sidewalls 6a, the source/drain regions 8a to 8h are not formed in the silicon substrate 1 under the insulating sidewalls 6a, and thus the source/drain extensions 5a to 5h are still extended thereunder. The source/drain extensions 5a to 5h in the area in which the source/drain regions 8a to 8h are not formed are called the offset.
Then, as described above, since the extended portion 6b is provided to the insulating sidewall 6a in the high-voltage transistor forming region II, an offset W2 in the high-voltage transistor forming region II becomes longer than an offset W1 in the normal transistor forming region I.
According to the steps applied up to now, basic structures of an n-type MOS transistor TRn and a p-type MOS transistor TRp having the dual gate structure are completed in the normal transistor forming region I respectively. In contrast, basic structures of an n-type high-voltage MOS transistor TR(high)n and a p-type high-voltage MOS transistor TR(high)p are completed in the high-voltage transistor forming region II. In the high-voltage MOS transistors TR(high)n and TR(high)p, since a source-drain interval is prolonged by the offset W2 that is longer than the offset W1 of the normal transistor, a source-drain withstand voltage can be enhanced. Also, since the gate insulating films 3c, 3d are formed thicker than the gate insulating films 3a, 3b of the normal transistor, a gate-source withstand voltage can be enhanced.
Then, as shown in FIG. 1G, a refractory metal layer is formed on the overall surface and then the refractory metal layer is caused to react with the silicon by the annealing. Thus, a silicide layer 9 is formed on the source/drain regions 8a to 8h and the gate electrodes 4a to 4d. Then, the unreacted refractory metal layer is removed by the etching.
Then, as shown in FIG. 1H, an interlayer insulating film 10 is formed on the overall surface and is patterned. Thus, first to eighth holes 10a to 10h are formed on the source/drain region 8a to 8h, and also first to eighth conductive plugs 11a to 11h are buried in the holes 10a to 10h.
With the above, a basic structure of the semiconductor device in the prior art is completed.
According to the above prior art, as explained with reference to FIG. 1E, due to a difference in the thermal oxide films 3 in respective regions I and II, the element isolation insulating films 2 in the normal transistor forming region I are etched at the time of forming the sidewall insulating films 6a, and thus their height is lowered than the upper surface of the silicon substrate 1.
However, when the element isolation insulating films 2 are etched in this manner, the silicide layer 9 is also formed on the silicon substrate 1 exposed on the side surface of the element isolation trench 1a, as shown in FIG. 2. Thus, the first n-type source/drain region 8a and the silicon substrate 1 are short-circuited by the silicide layer 9. As a result, it is impossible to control an electric potential of the first n-type source/drain region 8a via the first conductive plug 11a.
Also, in the ion-implantation step shown in FIG. 1F, as shown in an enlarged sectional view of FIG. 3, the n-type impurity is injected into the third gate electrode 4c through the first opening 6c in the insulating sidewall 6a, and thus a resistance of the third gate electrode 4c is lowered.
In this case, it is only a doped portion 4e of the third gate electrode 4c in the first opening 7c indicated by the hatching that the n-type impurity is injected into. Thus, the n-type impurity is not injected into the portions covered with the insulating sidewalls 6a, and these portions are left as undoped portions 4f.
However, when viewed from the carriers flowing through a channel 13, the carriers are influenced by the voltage of the third gate electrode 4c under the doped portion 4e whereas the influence of the gate electrode is reduced under the undoped portion 4f. Thus, the same effect as the case where the gate insulating film 3c only under the undoped portion 4f is made locally thick appears. According to this, a threshold voltage under the undoped portion 4f is increased higher than that under the doped portion 4e and therefore a channel resistance is increased and also a driving ability of the transistor TR(high)n is lowered.
In addition, the channel resistance depends on a shape and a size of the undoped portion 4f. Therefore, the channel resistance is changed depending upon a positional displacement between the first opening 7c and the third gate electrode 4c and thus there is a possibility that the driving ability is varied among a plurality of transistors.
Further, in the silicide step shown in FIG. 1G, as shown in an enlarged sectional view of FIG. 4, it is only in the portion under the first opening 7c of the insulating sidewall 6a that the silicide layer 9 is formed on the upper surface of the third gate electrode 4c. Thus, the silicide layer 9 is not formed in the portion covered with the insulating sidewall 6a, and the resistance of the third gate electrode 4c cannot be sufficiently lowered.
The high-voltage transistors are also disclosed in Patent Literatures 2, 3.
In Patent Literature 2, the structure capable of extending the offset of the source/drain extension by employing the dual sidewall in which two sidewalls are stacked is proposed. However, a width of the inner sidewall constituting the dual sidewall is almost 100 nm roughly, and only a width of 0.2 fÊm is given at most by the dual sidewall. For this reason, the width of the source/drain extension cannot be sufficiently expanded by the structure in Patent Literature 2 and thus it becomes difficult to increase sufficiently the source-drain withstand voltage of the high-voltage transistor.
Also, in Patent Literature 3, the process of forming the thermal oxide film on side walls and the upper surface of the gate electrode and then removing the thermal oxide film only from the upper surface to form the silicide layer therein is proposed. However, the thick thermal oxide film cannot be formed on the side surfaces of the gate electrode. Therefore, like Patent Literature 2, the width of the source/drain extension cannot be sufficiently expanded and thus the source-drain withstand voltage cannot be enhanced.
In addition to the above, the technology to integrate together the normal transistor and the high-voltage transistor is also disclosed in Patent Literatures 4 to 10.                [Patent Literature 1] Patent Application Publication (KOKAI) 2000-196037        [Patent Literature 2] Patent Application Publication (KOKAI) 2001-93984        [Patent Literature 3] Patent Application Publication (KOKAI) 2002-26139        [Patent Literature 4] Patent Application Publication (KOKAI) Hei 10-242414        [Patent Literature 5] Patent Application Publication (KOKAI) 2000-299390        [Patent Literature 6] Patent Application Publication (KOKAI) Sho 55-63873        [Patent Literature 7] Patent Application Publication (KOKAI) Hei 3-242977        [Patent Literature 8] Patent Application Publication (KOKAI) Hei 7-263705
[Patent Literature 9] Patent Application Publication (KOKAI) Hei 5-175228
[Patent Literature 10] Patent Application Publication (KOKAI) Hei 4-279033

Semiconductor device and method of manufacturing the same


A method and a system for a location determination (a) acquire a first positioning signal; (b) analyze the first positioning signal to provide an estimate of a clock signal acceleration; (c) acquire additional positioning signals based on the estimate of the clock signal acceleration; and (d) perform the location determination using the first positioning signal and the additional positioning signals. The additional positioning signals may be acquired using a stacking technique. The first positioning signal may be acquired based on a signal-to-noise ratio exceeding a predetermined threshold. Clock signal acceleration may be estimated using a constant clock signal acceleration parametric model, which may be parabolic model based on a function that depends on the clock signal acceleration, a clock Doppler and an initial phase value. Alternatively, grids of various granularity may be searched clock signal acceleration space and a clock Doppler space in the vicinity of a clock Doppler value measured in the acquisition of the first positioning signal.

1. Field of the Invention
This invention relates to a system and a method for processing positioning signals to estimate an acceleration of an embedded timing signal, so as to improve the performance of a positioning function.
2. Discussion of the Related Art
Changes in frequency can reduce the signal-to-noise ratio in a measured positioning signal, typically acquired by calculating a correlation between the positioning signal and a locally generated replica. This reduction in signal-to-noise ratio is particularly relevant in a system in which a coherent correlation is calculated over a long time period. Hence, there is a need for a method and a system to estimate the variations of the clock's frequency. In addition, there is a need for a method and a system that uses these estimated variations to improve processing of the positioning signals.
The following co-pending U.S. patent applications ("Co-pending Patent Applications") assigned to the Assignee of the present patent application disclose relevant signal processing techniques:                1. Signal Acquisition using Data Bit Information, Ser. No. 09/888,228, filed Jun. 22, 2001, now U.S. Pat. No. 6,512,479, issued Jan. 28, 2003 (hereafter, "Application 228");        2. Synthesizing Coherent Correlation Sums at One or Multiple Carrier Frequencies Using Correlation Sums Calculated at a Coarse Set of Frequencies, Ser. No. 09/888,227, filed Jun. 22, 2001 (hereafter, "Application 227");        3. Extracting Fine-Tuned Estimates from Correlation Functions Evaluated at Limited Number of Values, Ser. No. 09/888,338, filed Jun. 22, 2001, (hereafter, "Application 338");        4. Determining the Spatio-Temporal and Kinematic Parameters of a Signal Receiver and its Clock by Information Fusion, Ser. No. 09/888,229, filed Jun. 22, 2001 now U.S. Pat. No. 6,542,116, issued Apr. 1, 2003 (hereafter, "Application 229");        5. Determining Location Information Using Sampled Data Containing Location-Determining Signals And Noise, Ser. No. 09/888,337, filed Jun. 22, 2001, now U.S. Pat. No. 6,535,163, issued Mar. 18, 2003 (hereafter, "Application 337");        6. System and method to estimate the location of a receiver in a multi-path environment, Ser. No. 10/237,556, filed on Sep. 6, 2002 (hereafter, "Application 556"); and        7. System and method estimate the location of a receiver, Ser. No. 10/237,557, filed on Sep. 6, 2002 (hereafter, "Application 557").
The Copending Patent Applications are hereby incorporated by reference in their entireties.

System and method for estimating clock acceleration and location determination


A hand-operated dual joystick for a motor grader is disclosed. The dual joystick comprises a first joystick having a ledge and a switch, and a second joystick that is significantly smaller than the first joystick. The second joystick is mounted to the ledge of the first joystick. The first joystick is moveable along a first axis and a second axis that are perpendicular to each other. In addition, the first joystick is rotatable about a third axis that is perpendicular to the first axis and to the second axis. The second joystick is moveable along the first axis and the second axis. Movement of the first joystick and the second joystick is used to control a plurality of motor grader functions. The dual function joystick permits an operator to control a plurality of the motor grader functions from a single location thus reducing operator fatigue.

This invention relates generally to a miniature joystick mounted on a regular joystick for controlling a variety of functions of the motor grader.
Motor graders include many hand-operated controls to perform functions such as steering the grader, positioning an implement or a blade in several orientations, and articulating the frame of the grader.
Current motor graders require numerous hand-operated controls because typically each hand-operated control is used to control only one or two functions. Often, the operator of the motor grader must steer the grader while performing many other functions, such as adjusting the blade tip, adjusting the blade angle relative to the frame, and adjusting the articulation of the grader frame. Because the typical hand-operated controls are spaced apart, performing all of these functions simultaneously is difficult, inefficient, and fatiguing for the operator. To reduce difficulty, increase efficiency, and reduce operator fatigue, it is desirable to provide an apparatus that permits an operator to rapidly and easily control a plurality of functions from a single hand location. Also it is desirable to provide an apparatus that is ergonomically advantageous for controlling this plurality of functions.

Miniature joystick mounted on a joystick


A control circuit module for a power factor corrector is provided to convert the operation mode of the inductor current from the boundary conduction mode (BCM) to the discontinuous conduction mode (DCM) when a transistor element is operated under the valley inductor current, thus reducing the switching frequency and increasing system efficiency, also to maintain the operation mode of the inductor current in the BCM when the transistor element is operated under the peak inductor current, thus maintaining system efficiency.

1. Technical Field
The present disclosure relates generally to a control circuit module, and more particularly to a control circuit module is applied to a power factor corrector.
2. Description of Related Art
With the development of technology and economy, the demand of switch converters is increased. In recent years, most of electronic devices and power converters thereof will be developed toward the trend of light-weight, thin, small in size. Accordingly, the switching power converter will gradually replace the conventional linear converter to become a mainstream power converter due to smaller size, lighter weight, higher efficiency, and better quality of the switching power converter.
The power factor corrector can be operated in a continuous conduction mode (CCM), a discontinuous conduction mode (DCM), and a boundary conduction mode (BCM) according to the required applications.
In general, the high-switching losses are increased to reduce system efficiency when the inductor current of the PFC is operated under the BCM.

Control circuit module for power factor corrector


The objective of the present invention is the efficient analyzation of the structure of an array. By performing the prev(S) calculation for a character string S, if in S, a like variable is present upstream of a second variable, the second variable is changed to a numerical value that indicates the distance to the upstream like variable. But if in S, a like variable is not present upstream of a variable, that variable is changed to “0” to obtain a character string S1. Further, by performing the compl(S) calculation for S, if in the character string S a complementary variable is present upstream of a second variable, the second variable is changed to a numerical value that indicates the distance to the complementary variable. But if in S, a complementary variable is not present upstream of a variable, that variable is changed to “0” to obtain a character string S2.

1. Technical Field
The present invention relates to a method for changing an array, and a method, an apparatus, a storage medium and a transmission medium for analyzing a structure. In particular, the present invention relates to a method for changing an array in order to analyze its structure, a method for employing the array changing method to perform the analyzation of the structure of the array, an array structure analyzation apparatus specifically provided for the employment of the array structure analyzation method, a storage medium on which is stored a program that permits a computer to implement and apply the array structure analyzation method, and a transmission medium for transmitting the program that permits a computer to implement and apply the array structure analyzation method.
2. Prior Art
Recently, the deciphering of genetic information has been completed for a variety of organisms other than human beings, and it is now anticipated that the same process of explication can be performed for the human genome. For DNA, which is the main component of chromosomes and which is represented by an array of four bases consisting of adenine (A), thymine (T), cytosine (C) and guanine (G), and for RNA, which is transcribed from DNA and which is represented by an array of four bases, in which the T in DNA is replaced by uracil (U), the analyzation of the genetic information is performed by replacing an array of the bases of a single standard DNA or RNA base array with a character string for convenience, extracting from the obtained character string the pattern of a character string that frequently appears, and analyzing the extraction results.
Conventionally, as a technique, a suffix tree (a data structure) is well known that is effective for performing a rapid search of character strings to extract a character string that appears frequently, or a character string that is common to two or more character strings. The suffix tree represents all the suffixes in a character string wherein the character "$," which does not exist in a string that is currently being processed, is added at the end of the pertinent character string. An example is the character string "mississippi$" that, as is shown in FIG. 7, is obtained by adding the character "$" at the end of "mississippi," the character string that is currently being processed.
As is shown in FIG. 7, a label that corresponds to the character string is provided for each edge of the suffix tree. The first character of each label that is provided for each outgoing edge of one node (including a root node) differs from the others, and the edges are sorted in accordance with the first characters of the labels (for example, in FIG. 7, the edges are arranged in the English alphabetic order from left to right). In the suffix tree, the array of the labels that are provided for the individual edges from the root node to a specific leaf node (a node at the distal end of an edge to which no other edge is connected) is used as a suffix that corresponds to the specific leaf node (for example,"issippi$" is the suffix that corresponds to the leaf node of the array extending from the edges with labels "ppi$," "ssi" and "i" to the root node, and "ssissippi$" is the suffix that corresponds to the leaf node of the array extending from the edges with labels "ssippi$," "si" and "s" to the root node.
An algorithm is well known whereby the data structure of a suffix tree can be constructed within the time that corresponds to O(n Log s) where n denotes the length (character count) of the original character string, and s denotes the number of types of alphabetic characters that form the original character string). In particular, when the alphabet is an integer alphabet (numerals from 1 to n), the data structure of a suffix tree can be constructed within the time that corresponds to O(n). Therefore, even when a target character string is enormously long, like a character string that represents a DNA or an RNA base array, the data structure of a suffix tree for the pertinent character string can be completed within a short period of time (more specifically, a linear time relative to the length of the original character string). Further, if the suffix tree is employed, a character string having a length (character count) m can be found in the target character string within a time that corresponds to O(m log s), so that a character string used in common or a frequently appearing character string can be listed within a short period of time (a linear time relative to the length of the original character string).
In addition, when the label provided for each edge is replaced with information that represents the locations of the first character and the last character (character preceding "$") of the label in the original character string (e.g., "mississippi$" is replaced with [1●11]), the length of the character string that represents the suffix tree can be fitted to the constant times for the length of the original character string. The suffix array is also well known as a technique by which the length of the character string that represents a suffix tree can be reduced.
As was previously described, leaf nodes of a suffix tree correspond respectively to the suffixes of an original string. When the individual suffixes are arranged beginning with the suffix that corresponds to the leaf node at one end of the suffix tree (the left end in FIG. 7), an array wherein all the suffixes of an original string are arranged in dictionary order is obtained. When the suffixes that are elements of the array are replaced with data that represent the locations of the first characters of the suffixes in the original string (e.g., "ippi$" is replaced with "8"), an array (called a suffix array) having the same length as the original character string is obtained. For example, the suffix array for "mississippi" in FIG. 7 is "8 5 2 11 1 10 9 7 4 6 3."
When the above suffix array is employed, the memory capacity required for a search for a character string can be reduced compared with when a suffix tree is employed.
However, the time required for searching for the character string is O(m log n), where n denotes the length of a target character string and m denotes the length of a character string that is to be searched for.
A parameterized suffix tree is also well known as a technique (a data structure) for searching for a character string that frequently appears or a character string used in common when the character string includes a variable. For a gene sequence, such as a DNA or RNA base array, a specific element in the array may be exchanged with another specific element (for example, the A and T or the G and C of DNA complement each other and can be exchanged). Thus, in a parameterized suffix tree, when replaceable elements of an array are employed as variables, and when by replacing these variables in character strings (the character strings that include the variables) the character strings can be altered so that they are the same, the character strings are regarded as being the same.
For example, when x, y and z are defined as variables and a, b and c are defined as fixed characters, "axbycxaza" and "azbxczaya" are regarded as being the same character string (called a p-string (Parameterized String)) because by exchanging the variables x, y and z the same character array can be obtained. Encoding that is expressed as prev( ) is used to detect a p-string. This encoding is used to replace variables in a character string with a numerical value (the first variable that appears is 0) that represents the distance from the same variable that appeared immediately before. When the encoding prev( ) is performed for the two previously mentioned character strings, prev(axbycxaza)=prev(azbxczaya)=a0b0c4a0a is obtained.
The parameterized suffix tree represents the result that is obtained by performing the prev( ) encoding for all the suffixes of a character string to which the character $, which is not present in a target character string, is added (this differs from a normal suffix tree that is prepared while an array obtained by performing the prev( ) encoding, for a character string to which the character $ has been added, is regarded as a normal character string). In a parameterized suffix tree, as well as a suffix tree, leaf nodes correspond to the respective suffixes. Each edge has a label that corresponds to a partial character string, and the arrangement of labels that are provided for edges from the root node to a specific leaf node represents the result obtained by the prev( ) encoding for a suffix that corresponds to the specific leaf node.
Further, in the same manner as for the suffix tree, the first character of each label, which is provided for each edge extending from a node (including the root node), differs the others, and the labels are sorted in accordance with the first character. In addition, since the labels of each of the individual edges are represented by the first and the last positions of the original character string, the data structure has the size of the constant times of length of the character string.
For a gene sequence, such as a DNA or RNA base array, it is well known that although arrays that have the same structure may have different appearances they tend to have the same functions or properties. For a DNA base array, for example, when either or both of the complementary A and T, and the complementary G and C components are exchanged with each other, or when the non-complementary A and C components are exchanged and the non-complementary T and G components are exchanged, the structure of the array (the relationship of the elements of the array) tends to be unchanged, even though the array differs from the original array, and the functions and the properties obtained by effecting the exchange tend to be similar to those of the original array. Therefore, when analyzing a gene sequence, it is extremely important that arrays having the same structure be defined as the same array, regardless of whether the array themselves are identical, and that a frequently appearing array be extracted or that a partial array commonly included in two arrays be searched for.
On the other hand, with the conventional technique for employing a suffix tree or a suffix array, a character string other than an identical one can not be defined as being the same character string, so that even though an array may have the same structure, if it has a different element arrangement it can not be treated as the same array. Further, in a parameterized suffix tree, a character string wherein variables are simply replaced is defined as being the same character string. Thus, when, for example, only A and C are exchanged in the DNA base array, or only T and G are exchanged, or when A is exchanged with C and T with A, an array having a different structure from the original array can not be distinguished from an array having the same structure as the original array. Therefore, even when any of the above conventional techniques is employed, it is difficult to efficiently analyze a gene sequence.
To resolve the above shortcomings, it is one object of the present invention to provide a method for changing an array in order to efficiently analyze the structure of the array.
It is another object of the present invention to provide a method, an apparatus, a storage medium and a transmission medium for efficiently analyzing the structure of an array.

Method for changing a target array, a method for analyzing a structure, and an apparatus, a storage medium and a transmission medium therefor

International Business Machines Corporation


A vessel such as a dairy pasteuriser having a path B for product and a separate path A for coolant in intimate relationship is tested for leaks by circulating a donor fluid under pressure in path A whilst a recipient fluid such as clean tap water is circulated in path B. If the donor fluid is an electrolyte, a probe (12) is placed in path B to measure the conductivity of the recipient fluid. A rise in conductivity over a period indicates leakage between the two paths, the rate of change indicating the size of the leak. Alternatively, the donor fluid can be a gas, and leakage detected using an untrasound probe.

Pasteurisers used in the dairy process industry typically include a product path in which the milk is placed for treatment. A heating and/or cooling medium is passed through a separate circuit in close heat-exchange relationship with the product path via a number of heat exchange plates. Modern pasteurisers of this kind are known as HTST (High Temperature, Short Time) pasteurisers.
From time to time, leaks can develop between the heating/cooling circuit and the product path. Such leaks can be very costly, not only because the contaminated product must be discarded but also due to the cost of finding and rectifying the leak. Present preventive maintenance techniques involve shut down of the plant, dismantling of the pasteuriser,. detailed examination and testing of the individual heat exchange plates using mechanical and/or chemical tests, careful cleaning of the components, re-assembly with new seals, pressure and leak testing, and recommission of the re-assembled pasteuriser. Such a procedure results in considerable lost production time whilst the equipment is out of commission, is extremely labour intensive, and involves the cost of new seals. In addition, there is a substantial risk that further leaks can inadvertently be introduced during the re-building process.
An aim of the present invention may be viewed as being to overcome these problems.

Method of testing a plate heat exchanger for leakage