An impact printer and method of printing having a plurality of hammers in side-by-side relationship with pairs of pole pieces in associated relationship with each hammer with a hammer contact end and a distal end removed from the hammer contact. A pair of elongated magnets span the pole pieces at their distal ends and a magnet connection connects the magnets for creating a magnetic circuit through the pole pieces. The pole pieces have reduced adjacent facing areas at their distal ends, and are reduced in cross-section intermediately between their ends. The reduction in area between pole pieces directly reduces the permeance and mutual induction thereby creating greater accuracy of printing by the hammers.

1. Field of the Invention
The field of this invention lies within the field of dot matrix printers. More particularly, the field lies within the art of dot matrix printers which are characterized as line printers having a series of hammers that are released from a hammerbank. The hammerbank has permanent magnets for retention of the hammers, and electrical coils to overcome the magnetic retention by reversing the polarity for releasing the hammers. It particularly relates to that aspect of the magnetics which permanently retain the hammers and interact with adjacent magnetic forces including those of the pole pieces.
2. Prior Art
The prior art of line printers with permanent magnets incorporates numerous magnetic orientations. Oftentimes, these magnetic orientations are such where an elongated bar magnet is used to cause a pair of pole pieces to retract a hammerspring. The pole pieces are such wherein they receive a permanent magnet between them.
The pole pieces can be oriented so as to have shunts and air gaps for modifying the action of the permanent magnets. However, by in large, such permanent magnetism is provided by a magnet which is placed in a notch, space, or slot between pairs of pole pieces. The magnetism flows from the permanent magnet through the pair of pole pieces for retracting the hammer against the pole pieces.
Coils are wrapped around the pole pieces and overcome the permanent magnetism of the magnetic circuit so that a release of the sprung hammers of the hammerbank can be effected. This is when the permanent magnetism is counteracted so that the hammers are released and move away by their spring action from the ends of the pole pieces. During this release action, the permanent magnetism and the reverse flux provided by the coils creates a dynamic within the interaction of the hammers and the interfacing adjacent pole pieces. This interaction within the hammers is such that magnetic phenomena dynamically changes between the hammers, the pole pieces, and the magnetic circuit.
The dynamic interaction is extremely critical to the phases of printing. When the hammers are released, the relative phases of printing, as the hammers each respectively strike the print ribbon and the underlying media, can vary depending on the magnetic interaction between adjacent hammers and pole pieces. As can be appreciated, if the hammers are released too slowly, too quickly, or magnetically retracted in a particularly variable manner without consistency, the dots in a line matrix printing or other dot matrix printer are not accurate and do not present clear print. This is most critical with regard to such items today as bar codes that are printed onto an underlying media for bar code reading.
The position of a hammerspring in contact or when away from a pole piece affects the magnetics, and magnetic forces are imposed on the other hammerspring magnetic circuits. These interactive changes during the operation of the hammerspring is a major problem. When such interaction takes place, it tends to occlude and change the desired operating characteristics of the magnetics and attendant hammersprings. Such interaction, can create a cascading effect. The magnetic effects of one hammerspring and magnetic circuit of the pole pieces can be transferred to another one. Likewise, down the line of a plurality of hammersprings and magnetic pole pieces, a cascading effect is created in a line printer thereby affecting them on a cascading basis.
The foregoing cascading effect can vary depending upon the dynamics of operation. For instance, if one particular series of adjacent springs are releasing and retracting, they can effectively create a cascade effect in an adjacent relationship. To this extent, they can change the magnetic effects on a constantly shifting basis. As a consequence, if this problem can be resolved or reduced it is eminently helpful to the accuracy and functions of a printer, especially a printer printing bar codes.
When viewing the hammers and the pole pieces, it can be determined that permeance exists between them. In effect, the magnetic flux can transit or leap from one pole piece to a neighboring pole piece or pole pin. This permeance is inversely proportional to the distance between the pole pieces. In other words the farther they are away in spacing, the less the permeance and effect of mutual inductance has on the magnetic circuits. Further to this extent, the permeance is directly proportional to the adjacent or facing areas of neighboring pole pins or pole pieces. In other words, as the adjoining or adjacent area of the pole pieces increases, there is a directly proportional increase of magnetic permeance between the pole pieces or pins.
In order to overcome these deficiencies a decrease in the adjacent areas is utilized to resolve the problem. This is effected by removing a portion of the pole pieces or pole pins having areas in adjacent relationship to each other. By doing this, the characteristics of the permeance between the adjacent pole pieces is diminished. In effect, the connection of the magnetic flux of the permanent magnets to the pole pieces is diminished and more discrete and precise printing operations can be effected.
In order to provide for this decrease in permeance through reduced adjacent areas, the surface areas are diminished. Also the magnetics provided by the permanent magnet are split. The split magnet is interconnected by a keeper in order to provide for connected magnetic functions through the magnetic circuit.
The reduced permeance of the pole pieces to neighboring pole pieces results in reduced mutual and self inductance. Thus, the changes in forces on a hammerspring in the released and retracted positions or during the dynamic movement as well as in the static position upon return is reduced as to neighboring pole pieces.
The changes in dynamic magnetic pull back forces in the hammers and pole pieces because of the positions of neighboring hammersprings is one of the worst case conditions. This is particularly true when the hammerspring spacing between them is reduced which in turn creates greater permeance. To solve this, this invention specifically reduces the geometry of the pole pins as to their mutual facing areas, and reduces self and mutual inductance through the reduction of permeance. In this manner, faster circuits are achieved that are better matched for the timing and voltage levels to allow for less energy per stroke to be consumed from the power supply and more accurate printing. As a consequence, this invention is a broad step over the prior art by increasing speed and accuracy of printing as well as reducing the power requirements.

Line printer with reduced magnetic permeance


Embodiments of the present invention are directed to a method and apparatus for the identification or discovery for properties of MPLS networks through a modeling technique. Aspects of the present invention provide for discovering or identifying the Label Switched Paths in MPLS networks. The method comprises the steps of representing a network by a model comprising a plurality of configuration non-specific first object classes that are representations of types of components associated with the network components, and a plurality of configuration non-specific second object classes that are representations of relationships among the representation of types of component, identifying instances of a first one and a second one of the types of components object class, and identifying the label switch path by traversing the instances of the first and second types of components object classes through select ones of the relationship object classes associated with the first and second type of components object classes.

The concepts, terms, and acronyms of MPLS networks are well-known in the art. For example, the memorandum entitled RFC 3031-Multiprotocol Label Switching Architecture, E. Rosen, A. Viswanathan, and R. Callon, RFC 3031, January 2001, Internet Engineering Task Force (IETF), is an example of the literature regarding MPLS networks.
The ability to analyze MPLS networks has been limited by the network models that have been employed. For example, one model uses a Common Information Model (CIM) that defined objects and relationships. (see Common Information Model: Implementing the Object Model for Enterprise Management, Bumpus, et al., John Wiley & Sons, December 1999, ISBN: B00007FY8X). This model is limited by the pre-defined and standard objects and relationships defined in the Common Information Model (CIM). For example, one cannot easily capture the relationship between a Label-Switched Path (LSP) and LSPHop.
In a second model, the definition of MPLS Management Information Bases (MIBs) are established. (See, for example, SNMP, SNMPv2, SNMPv3, and RMON 1 and 2 (3rd Edition, William Stallings, Addison-Wesley Pub Co, December 1998, pages 71-162, ISBN: 0201485346). However, MIBs typically do not capture relationships between objects. For example the MPLS end-to-end Label-Switched Path (LSP) is difficult to represent explicitly in an MIB.
The lack of a systematic model specifically suited for the MPLS objects and relationships limits several forms of important analysis. Hence there is a need in the industry for a method and system that overcomes known deficiencies in identifying Label-Switched Paths in MPLS systems.

Model-based method and apparatus for determining MPLS network properties


An apparatus and method for duplicating tag addresses to maintain addresses of central processing unit (CPU) data stored in write buffers external to a cache are disclosed. Advance notification of write transactions is issued to allow a subsystem that maintains duplicate cache tags to know in advance which write transactions are present in the CPU's buffers. Such information is used to keep duplicate tags for both the cache and any buffers that contain writes that are to be removed from the cache. The cache is preferably a direct mapped cache and the CPU preferably resides within a multiprocessor architecture. In the preferred embodiment, all write transactions are indirectly caused by a read transaction that is about to bring a line into the cache. Thus, a read transaction is issued by the CPU before the write transaction is issued. A field is added to the read transaction that indicates whether or not the read transaction has a corresponding line that must be written out of the cache and into a buffer, such that the duplicate tags duplicate both the CPU cache and the CPU write buffers.

1. Technical Field
The invention relates to a computer architecture, including a uniprocessor architecture having a cache and a multiprocessor architecture. More particularly, the invention relates to maintaining cache coherency in a uniprocessor or multiprocessor computer architecture.
2. Description Of The Prior Art
Caches can be classified either as write-through or write-back. A write-through cache is always written to along with system memory, such that system memory and cache each maintain a current copy of the information that is written, and the possibility of stale data is avoided. Information input in computer architecture using a write-through cache requires significant system overhead. For example, the system must guarantee that none of the blocks of the input/output (I/O) buffer that have been designated for input are in the cache.
Write-back caches keep modified data until the data are cast out and written back to memory to make room for new data. Because a write-back cache may have the only copy of modified data, special care must be taken in the cache coherency protocol between multiple caches such that the cache data can be quickly accessed and never lost.
The protocols that are used to maintain coherency for multiple processors are referred to as cache coherency protocols. There are two classes of cache coherency protocols:
1. Directory based: The information about one block of physical memory is kept in just one location. This information usually includes which cache(s) has a copy of the block and whether that copy is marked exclusive for future modification. An access to a particular block first queries the directory to see if the memory data is stale and the real data resides in some other cache. If it is, then the cache containing the modified block is forced to return its data to memory. Then the memory forwards the data to the new requester, updating the directory with the new location of that block. This protocol minimizes inter-bus module (or inter-cache) disturbance, but typically suffers from high latency and is expensive to build due to the large directory size required.
2. Snooping: Every cache that has a copy of the data from a block of physical memory also has a copy of the information about the data block. Each cache is typically located on a shared memory bus, and all cache controllers monitor or snoop on the bus to determine whether or not they have a copy of the shared block.
Snooping protocols are well suited for multiprocessor system architectures that use caches and shared memory because they operate in the context of the preexisting physical connection usually provided between the bus and the memory. Snooping is preferred over directory protocols because the amount of coherency information is proportional to the number of blocks in a cache, rather than the number of blocks in main memory.
The coherency problem arises in a multiprocessor architectures when a processor must have exclusive access to write a block of memory or object, and/or must have the most recent copy when reading an object. A snooping protocol must locate all caches that share the object to be written. The consequences of a write to shared data are either to invalidate all other copies of the data, or to broadcast the write to all of the shared copies. Because of the use of write back caches, coherency protocols must also cause checks on all caches during memory reads to determine which processor has the most up to date copy of the information.
Data concerning information that is shared among the processors is added to status bits that are provided in a cache block to implement snooping protocols. This information is used when monitoring bus activities. On a read miss, all caches check to see if they have a copy of the requested block of information and take the appropriate action, such as supplying the information to the cache that missed. Similarly, on a write, all caches check to see if they have a copy of the data, and then act, for example by invalidating their copy of the data, or by changing their copy of the data to the most recent value.
Because every coherent bus transaction causes the caches to check their address tags, snooping interferes with the central processing unit (CPU)'s access to its cache regardless of the snoop result. For example, even when snooping returns a miss, the CPU is prevented from cache access because the cache is unavailable, i.e. the cache is busy checking tags to match against the snoop address. Thus, the CPU stalls or locks if it needs to access the cache while the cache is busy with a coherency check.
Snooping protocols are of two types:
Write invalidate: The writing processor causes all copies in other caches to be invalidated before changing its local copy. The processor is then free to update the data until such time as another processor asks for the data. The writing processor issues an invalidation signal over the bus, and all caches check to see if they have a copy of the data. If so, they must invalidate the block containing the data. This scheme allows multiple readers but only a single writer.
Write broadcast: Rather than invalidate every block that is shared, the writing processor broadcasts the new data over the bus. All copies are then updated with the new value. This scheme continuously broadcasts writes to shared data, while the write invalidate scheme discussed above deletes all other copies so that there is only one local copy for subsequent writes. Write broadcast protocols usually allow data to be tagged as shared (broadcast), or the data may be tagged as private (local). For further information on coherency, see J. Hennessy, D. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, Inc. (1990).
In a snoopy coherence multiprocessor system architecture, each coherent transaction on the system bus is forwarded to each processor's cache subsystem to perform a coherency check. This check usually disturbs the processor's pipeline because the cache cannot be accessed by the processor while the coherency check is taking place.
In a traditional, single ported cache without duplicate cache tags, the processor pipeline is stalled on cache access instructions when the cache controller is busy processing cache coherency checks for other processors. For each snoop, the cache controller must first check the cache tags for the snoop address, and then modify the cache state if there is a hit. Allocating cache bandwidth for an atomic (unseparable) tag read and write (for possible modification) locks the cache from the processor longer than needed if the snoop does not require a tag write. For example, 80% to 90% of the cache queries are misses, i.e. a tag write is not required.
It is possible to eliminate contention between the processor pipeline and the bus snoops by implementing a dual ported cache. However, this solution requires additional hardware and interconnect, and is therefore difficult and expensive to implement.
In multi-processor systems, duplicate tags (which are also referred to as "tag caches") may be used to minimize the number of coherence checks performed on a processor. For such duplicate tags to function, it is important that the duplicate tags each include all cache lines owned by an associated CPU. One challenge of maintaining duplicate tags is to make sure that they include not only the CPU caches, but also any buffers that may be temporarily holding cache lines about to be written out by the CPU.
Prior art solutions to this problem include forcing out the write of a cache line before it is replaced by another cache line. For example, a CPU "A" must issue a write for a line "X" before it is allowed to cache a line "Y." One disadvantage of this solution is that it can decrease system performance. CPUs must process cache misses as quickly as possible to optimize performance. The amount of time required to write out dirty cache lines is not critical to overall system performance. By forcing the CPU to wait until the write has been issued before it can complete the cache miss, this prior art approach adds latency to the cache miss penalty which, in turn, slows down overall CPU performance.
A system implementing a mechanism that maintains duplicate tags to make sure that they include not only the CPU caches, but also any buffers that may be temporarily holding cache lines about to be written out by the CPU, in a simple and inexpensive way would be a significant advance in multiprocessor architecture design.

Method and apparatus for duplicating tag systems to maintain addresses of CPU data stored in write buffers external to a cache


A network device implements a control node that receives an indication of a session associated with a user equipment (UE), wherein the network device is connected to a Long Term Evolution (LTE) network, and the LTE network is interconnected with a Next Generation (Next Gen) Network. The control node determines one or more parameters associated with at least one of: a relative traffic loading of the LTE network and the Next Gen Network, a quantity of first cells within the LTE network and a quantity of second cells within the Next Gen Network, a movement status of the UE, a quantity of data associated with the session, or a latency sensitivity of the session. The control node causes the session to be selectively routed to the UE via either the LTE network or the Next Gen Network, or via both the LTE network and the Next Gen Network, based on the one or more determined parameters.

Long Term Evolution (LTE) is a mobile telecommunications standard for wireless communication involving mobile user equipment, such as mobile devices and data terminals. LTE networks include existing Fourth Generation (4G), and 4.5 Generation (4.5G) wireless networks.
Next Generation mobile networks, such as Fifth Generation (5G) mobile networks, have been proposed as the next evolution of mobile wireless networks. Next Generation mobile networks are designed to increase data transfer rates, increase spectral efficiency, improve coverage, improve capacity, and reduce latency. The proposed 5G mobile telecommunications standard, among other features, operates in the millimeter wave bands (e.g., 28, 38, and 60 GigaHertz (GHz)), and supports more reliable, massive machine communications (e.g., machine-to-machine (M2M), Internet of Things (IoT)).

Resource management for interworking between LTE and next generation mobile networks


A decoding device for decoding an LDPC (Low Density Parity Check) code. The decoding device may include a first operation unit for performing a check node operation for decoding the LDPC code, the operation including an operation of a nonlinear function and an operation of an inverse function of the nonlinear function; and a second operation unit for performing a variable node operation for decoding the LDPC code. The first operation unit includes a first converting unit for converting a first quantization value assigned to a numerical value into a second quantization value representing a numerical value with a higher precision than the first quantization value, and a second converting unit for converting the second quantization value into the first quantization value.

The present invention relates to a decoding device and a decoding method, and particularly to a decoding device and a decoding method that make it possible to decode a code resulting from encoding by a low density parity check code (LDPC code) with a high precision while preventing an increase in scale of the device.
Recently, researches in a field of communications such as mobile communications and deep space communications and in a field of broadcasting such as terrestrial broadcasting and satellite digital broadcasting, for example, have been advanced considerably. As such researches have been advanced, researches into coding theories have also been actively pursued for purposes of improvement in efficiency of error correction coding and decoding.
A so-called Shannon (C. E. Shannon) limit given by Shannon's channel coding theorem is known as a theoretical limit of code performance. Researches into coding theories are pursued with an objective of developing a code that offers performance close to the Shannon limit. Recently, methods referred to as turbo coding such as PCCCs (Parallel Concatenated Convolutional Codes) and SCCCs (Serially Concatenated Convolutional Codes), for example, have been developed as encoding methods that offer performance close to the Shannon limit. While these turbo codes have been developed, low density parity check codes (hereinafter referred to as LDPC codes) as an encoding method that has been known for a long time are drawing attention.
LDPC codes were first proposed by R. G. Gallager in "Low Density Parity Check Codes", Cambridge, Mass.: M. I. T. Press, 1963. Thereafter LDPC codes were rediscovered in D. J. C. MacKay, "Good error correcting codes based on very sparse matrices", submitted to IEEE Trans. Inf. Theory, IT-45, pp. 399-431, 1999, M. G. Luby, M. Mitzenmacher, M. A. Shokrollahi, and D. A. Spielman, "Analysis of low density codes and improved designs using irregular graphs", in Proceedings of ACM Symposium on Theory of Computing, pp. 249-258, 1998, and the like.
Recent researches have found that, as with turbo codes and the like, LDPC codes offer performance that approaches the Shannon limit as code length is increased. Since LDPC codes have a characteristic in that minimum distance is in proportion to the code length, the LDPC code has advantages, as features thereof, of good block error probability characteristics and substantially no occurrence of a so-called error floor phenomenon, which is observed in characteristics of decoding of turbo codes and the like.
Such LDPC codes will be described concretely in the following. Incidentally, LDPC codes are linear codes, and are not necessarily binary codes; however, the following description will be made supposing that LDPC codes are binary codes.
LDPC codes have a principal characteristic in that a parity check matrix defining the LDPC codes is a sparse check matrix. A sparse matrix has a very small number of "1s" as components of the matrix. Supposing that a sparse check matrix is represented by H, such check matrices H include for example a check matrix H as shown in FIG. 1 in which the Hamming weight (the number of 1s) of each column is three and the Hamming weight of each row is six.
An LDPC code defined by such a check matrix H in which the Hamming weights of each row and each column are constant is referred to as a regular LDPC code. On the other hand, an LDPC code defined by a check matrix H in which the Hamming weights of each row and each column are not constant is referred to as an irregular LDPC code.
Encoding by such an LDPC code is implemented by generating a generator matrix G based on the check matrix H and multiplying the generator matrix G by a binary information message to generate a codeword. Specifically, an encoding device for performing encoding by an LDPC code first calculates a generator matrix G which satisfies an equation GHT=0 between a transposed matrix HT of the check matrix H and the generator matrix G. When the generator matrix G is a k×n matrix (a matrix of k rows and n columns), the check matrix H is a matrix of n−k rows and n columns.
The encoding device multiplies the generator matrix G by an information message (vector) u of k bits to generate a codeword (LDPC code) c (=uG) of n bits. The codeword c generated by the encoding device is mapped such that a code bit having a value "0" is converted into "+1" and a code bit having a value "1" is converted into "−1" for transmission. The transmitted codeword is received on a receiving side via a predetermined communication channel.
In a case where the codeword c of n bits is a systematic code that coincides with a bit string obtained by arranging n−k parity bits following the information message u of k bits, supposing that a part of n−k rows and k columns in the check matrix H of n−k rows and n columns which part corresponds to the information message u of k bits in the codeword c of n bits is referred to as an information part and that a part of n−k rows and n−k columns which part corresponds to n−k parity bits is referred to as a parity part, the information message u can be encoded into an LDPC code by using the check matrix H when the parity part forms a lower triangular matrix or an upper triangular matrix.
Specifically, for example, when the check matrix H is formed by the information part and the parity part of a lower triangular matrix as shown in FIG. 2, and elements in the lower triangular part of the parity part all have a value of one, a first bit of the parity bits of the codeword c has a value obtained by calculating an EXOR (exclusive disjunction) of bits of the information message u which bits correspond to elements having a value of one in a first row in the information part of the check matrix H.
A second bit of the parity bits of the codeword c has a value obtained by calculating an EXOR of bits of the information message u which bits correspond to elements having a value of one in a second row in the information part of the check matrix H and the first bit of the parity bits.
A third bit of the parity bits of the codeword c has a value obtained by calculating an EXOR of bits of the information message u which bits correspond to elements having a value of one in a third row in the information part of the check matrix H and the first and second bits of the parity bits.
Similarly, a subsequent ith bit of the parity bits of the codeword c has a value obtained by calculating an EXOR of bits of the information message u which bits correspond to elements having a value of one in an ith row in the information part of the check matrix H and the first to (i−1)th bits of the parity bits.
Thus, the codeword c of n bits can be obtained by determining the n−k parity bits and arranging the n−k parity bits following the information message u of k bits.
LDPC codes can be decoded by a probabilistic decoding algorithm proposed by Gallager, which is a message-passing algorithm based on belief propagation on a so-called Tanner graph including variable nodes (referred to also as message nodes) and check nodes. Variable nodes and check nodes will hereinafter be also referred to simply as nodes as appropriate.
In the probabilistic decoding, however, messages exchanged among nodes are real numbers, and it is therefore necessary to monitor the probability distribution itself of the messages assuming sequential numbers in order to analytically solve the messages. Thus, very difficult analysis is required. Therefore, Gallager has proposed algorithm A or algorithm B as an algorithm for decoding LDPC codes.
LDPC codes are generally decoded according to a procedure as represented in FIG. 3. In this case, suppose that an LDPC code (codeword c) received value is U0, that a message output from a check node (hereinafter referred to as a check node message as appropriate) is uj, and that a message output from a variable node (hereinafter referred to as a variable node message as appropriate) is vi. A message is a real number that expresses the likelihood of zero by a so-called log likelihood ratio. Further, the log likelihood ratio of the likelihood of zero of the received value U0 will be represented as received data u0i.
In the decoding of an LDPC code, as shown in FIG. 3, in first step S11, the received value U0 (received data u0i) is received, the message uj is initialized to "0", and a variable k of an iterative processing counter which variable assumes an integer is initialized to "0". The process proceeds to step S12. In step S12, the variable node message vi is obtained by performing an operation represented by Equation (1) on the basis of the received data u0i, and the check node message uj is obtained by performing an operation represented by Equation (2) on the basis of the variable node message vi.
                    [                  Equation                                                              1                ]                                                                                v            i                    =                                    u                              0                                i                                      +                                          ∑                                  j                  =                  1                                                                      d                    v                                    -                  1                                                                          u                j                                                                        (        1        )                                [                  Equation                                                              2                ]                                                                                tanh                                      (                                                u                  j                                2                            )                                =                                    ∏                              i                =                1                                                              d                  c                                -                1                                                                                tanh                                            (                                                      v                    i                                    2                                )                                                                        (        2        )
In Equations (1) and (2), dv and dc are arbitrarily selectable parameters representing the number of 1s in a vertical direction (row direction) and a horizontal direction (column direction), respectively, of the check matrix H. For example, in a case of a (3, 6) code, dv=3 and dc=6.
Incidentally, in the operation of Equation (1) or (2), a message input from an edge from which to output a message is not used as a product or sum operation parameter, and therefore a product or sum operation range is a range of one to dv−1 or one to dc−1. In practice, the operation represented by Equation (2) is performed by preparing in advance a table of a function R(v1, v2) represented by Equation (3), which is defined by one output with respect to two inputs v1 and v2, and sequentially (recursively) using the function R as shown in Equation (4).
[Equation 3]x=2 tan h−1{tan h(v1/2)tan h(v2/2)}=R(v1, v2)  (3)[Equation 4]uj=R(v1, R(v2, R(v3, . . . R(vdc−2, vdc−1))))  (4)
Further, in step S12, the variable k is incremented by one. The process proceeds to step S13. In step S13, whether the variable k is equal to or greater than predetermined iterative decoding times N is determined. When it is determined in step S13 that the variable k is not equal to or greater than N, the process returns to step S12 to thereafter repeat the same processing.
When it is determined in step S13 that the variable k is equal to or greater than N, the process proceeds to step S14, where a message v as a decoding result to be finally output is obtained by performing an operation represented by Equation (5), and the message v is output. Then the LDPC code decoding process is ended.
                    [                  Equation                                                              5                ]                                                                                v          =                                    u                              0                                i                                      +                                          ∑                                  j                  =                  1                                                  d                  v                                                                          u                j                                                                        (        5        )
Unlike the operation of Equation (1), the operation of Equation (5) is performed using messages from all edges connected to the variable node.
In such decoding of an LDPC code, in the case of a (3, 6) code, for example, messages are exchanged between nodes as shown in FIG. 4. The operation represented by Equation (1) is performed at the nodes indicated by "=" (variable nodes) in FIG. 4, and the operation represented by Equation (2) is performed at the nodes indicated by "+" (check nodes). In particular, in the algorithm A, messages are binarized, and at a node indicated by "+", an exclusive OR of dc−1 messages input to the node are calculated, and at a node indicated by "=", when all of dv−1 messages input to the node have bit values different from the received data R (u0i), the code is inverted and then output.
On the other hand, researches into a method for implementing the decoding of LDPC codes have recently been pursued. Prior to the description of the implementing method, description will first be made of the decoding of an LDPC code in schematic form.
FIG. 5 shows an example of the parity check matrix of a (3, 6) LDPC code (an encoding rate of 1/2 and a code length of 12). The check matrix H of an LDPC code can be written by using a Tanner graph as in FIG. 6. In FIG. 6, a check node is denoted by "+", and a variable node is denoted by "=". A check node and a variable node correspond to a row and a column, respectively, of the check matrix H. A connection between a check node and a variable node is an edge, and corresponds to "1" in the check matrix. Specifically, when a component in a jth row and an ith column in the check matrix H is one, an ith variable node from the top (a "=" node) and a jth check node from the top (a "+" node) in FIG. 6 are connected to each other by an edge. The edge indicates that an LDPC code bit corresponding to the variable node has a constraint condition corresponding to the check node. Incidentally, FIG. 6 is a Tanner graph of the check matrix H of FIG. 5.
A sum-product algorithm as an LDPC code decoding method repeatedly performs a variable node operation and a check node operation.
The operation of Equation (1) is performed at a variable node as shown in FIG. 7. Specifically, in FIG. 7, a variable node message vi corresponding to an edge for which to calculate the variable node message vi is calculated using received information u0i and check node messages u1 and u2 from other edges connected to the variable node. Variable node messages corresponding to other edges are calculated in a similar manner.
Prior to the description of the check node operation, Equation (2) is rewritten as Equation (6) using the relation of an equation a×b=exp{ln(|a|)+ln(|b|)}×sign(a)×sign(b), where sign(x) is 1 when x≧0, and is −1 when x<0.
                    [                  Equation                                                              6                ]                                                                                u                  j                                =                                  2                                                                              tanh                                              -                        1                                                                                (                                                                        ∏                                                      i                            =                            1                                                                                d                              c                                                        -                            1                                                                                tanh                                                                                (                                                                                v                                i                                                            2                                                        )                                                                                )                                                                                =                              2                                                                      tanh                                          -                      1                                                                                [                                          exp                                                                    {                                                                              ∑                                                          i                              =                              1                                                                                d                                c                                                            -                              1                                                                                ln                                                                                (                                                                                                                                tanh                                                                                (                                                                                v                                        i                                                                            2                                                                        )                                                                                                                                            )                                                                                }                                            ×                                                                        ∏                                                      i                            =                            1                                                                                d                              c                                                        -                            1                                                                                sign                                                                                (                                                          tanh                                                                                (                                                                                v                                    i                                                                    2                                                                )                                                                                )                                                                                ]                                                                                =                              2                                                                      tanh                                          -                      1                                                                                [                                          exp                                                                    {                                                  -                                                      (                                                                                ∑                                                                  i                                  =                                  1                                                                                d                                    c                                                                    -                                  1                                                                                -                                                                  ln                                                                                (                                                                          tanh                                                                                (                                                                                                                                                                v                                              i                                                                                                                                                                2                                                                                )                                                                                )                                                                                )                                                                          }                                                              ]                                                  ×                                                      ∏                                          i                      =                      1                                                                                d                        c                                            -                      1                                                                                sign                                                                                (                                              v                        i                                            )                                                                                (        6        )
Further, when a nonlinear function φ(x) is defined as an equation φ(x)=ln(tan h(x/2)) (ln( ) is a natural logarithmic function) with x≧0, the inverse function φ−1(x) of the nonlinear function φ(x) is expressed by an equation φ−1(x)=2tan h−1(e−x). Therefore Equation (6) can be written as Equation (7).
                    [                  Equation                                                              7                ]                                                                                u            j                    =                                                    ϕ                                  -                  1                                                                          (                                                      ∑                                          i                      =                      1                                                                                d                        c                                            -                      1                                                                                ϕ                                                              (                                                                                                v                          i                                                                                            )                                                                      )                                      ×                                          ∏                                  i                  =                  1                                                                      d                    c                                    -                  1                                                                                sign                                                                                (                                      v                    i                                    )                                                                                (        7        )
The operation of Equation (7) is performed at a check node as shown in FIG. 8. Specifically, in FIG. 8, a check node message uj corresponding to an edge for which to calculate the check node message uj is calculated using variable messages v1, v2, v3, v4, and v5 from other edges connected to the check node. Check node messages corresponding to other edges are calculated in a similar manner.
Incidentally, the function φ(x) can also be expressed as φ(x)=ln((ex+1)/(ex−1)), and φ(x)=φ−1(x) when x>0. When the functions φ(x) and φ−1(x) are implemented in hardware, the functions φ(x) and φ−1(x) may be implemented by using a LUT (Look Up Table), and in such a case, an identical LUT is used for both of the functions φ(x) and φ−1(x).
The LDPC code decoding method is referred to not only as the sum-product algorithm but also as belief propagation, for example; however, operations performed in either case are the same.
An implementing method in a case of performing decoding by sequentially performing operations at nodes one by one (full serial decoding) will be described as an example of implementation of the sum-product algorithm in a decoding device.
Incidentally, when implementing the sum-product algorithm in hardware, it is necessary to perform the variable node operation represented by Equation (1) and the check node operation represented by Equation (7) repeatedly with an appropriate circuit scale and an appropriate operating frequency.
Suppose in this case that a code (an encoding rate of 2/3 and a code length of 108) represented by a check matrix H of 36 (rows)×108 (columns) in FIG. 9 is decoded, for example. The number of 1s in the check matrix H of FIG. 9 is 323, and therefore the number of edges in the Tanner graph is 323. In the check matrix of FIG. 9, zero is represented by ".".
FIG. 10 shows an example of configuration of a decoding device that performs one-time decoding of an LDPC code.
The decoding device of FIG. 10 calculates a message corresponding to one edge for each clock for operation of the decoding device.
Specifically, the decoding device in FIG. 10 includes two edge memories 100 and 102, one check node calculator 101, one variable node calculator 103, one receiver memory 104, and one controlling unit 105.
In the decoding device of FIG. 10, messages are read from the edge memory 100 or 102 one by one, and a message corresponding to a desired edge is calculated using the messages. Messages obtained by the calculation are stored one by one in the edge memory 102 or 100 in a subsequent stage. Iterative decoding is achieved by serially connecting a plurality of decoding devices of FIG. 10 that perform the one-time decoding, or repeatedly using the decoding device of FIG. 10. Incidentally, suppose in this case that a plurality of decoding devices of FIG. 10 are connected to each other.
The edge memory 100 stores messages (variable node messages) D100 supplied from the variable node calculator 103 of a decoding device in a preceding stage (not shown) in order in which the check node calculator 101 reads the messages D100. Then, in a phase of check node calculation, the edge memory 100 supplies the check node calculator 101 with the messages D100 as messages D101 in the order in which the messages D100 are stored.
According to a control signal D106 supplied from the controlling unit 105, the check node calculator 101 performs an operation (check node operation) according to Equation (7) using the messages D101 (variable node messages vi) supplied from the edge memory 100. The check node calculator 101 supplies a message D102 (check node message uj) obtained by the operation to the edge memory 102 in a subsequent stage.
The edge memory 102 stores messages D102 supplied from the check node calculator 101 in a preceding stage in order in which the variable node calculator 103 in a subsequent stage reads the messages D102. Then, in a phase of variable node calculation, the edge memory 102 supplies the variable node calculator 103 with the messages D102 as messages D103 in the order in which the messages D102 are stored.
Further, the variable node calculator 103 is supplied with a control signal D107 from the controlling unit 105, and supplied with received data D104 from the receiver memory 104. According to the control signal D107, the variable node calculator 103 performs an operation (variable node operation) according to Equation (1) using the messages D103 (check node messages uj) supplied from the edge memory 102 and the received data D104 (received data u0i) supplied from the receiver memory 104. The variable node calculator 103 supplies a message D105 (variable node message vi) obtained as a result of the operation to the edge memory 100 of a decoding device in a subsequent stage not shown in the figure.
The receiver memory 104 stores the received data u0i of the LDPC code. The controlling unit 105 supplies the control signal D106 for controlling the check node operation and the control signal D107 for controlling the variable node operation to the check node calculator 101 and the variable node calculator 103, respectively. The controlling unit 105 supplies the control signal D106 to the check node calculator 101 when the messages of all edges are stored in the edge memory 100, and supplies the control signal D107 to the variable node calculator 103 when the messages of all edges are stored in the edge memory 102.
FIG. 11 shows an example of configuration of the check node calculator 101 in FIG. 10 that performs the check node operation on a one-by-one basis.
Incidentally, FIG. 11 shows the check node calculator 101 supposing that each message is quantized into a total of six bits including a sign bit (a bit representing a positive sign or a negative sign). That is, a message is represented by a six-bit quantization value assigned to each numerical value for uniformly dividing a predetermined numerical range into 64 values that can be represented by six bits including a sign bit.
In FIG. 11, the check node operation on the LDPC code represented by the check matrix H of FIG. 9 is performed. Further, the check node calculator 101 in FIG. 11 is supplied with a clock ck. The clock ck is supplied to necessary blocks. The blocks perform processing in synchronism with the clock ck.
According to a one-bit control signal D106, for example, supplied from the controlling unit 105, the check node calculator 101 in FIG. 11 performs the operation according to Equation (7) using the messages D101 (variable node messages vi) read one by one from the edge memory 100.
Specifically, a six-bit message D101 (variable node message vi) from a variable node corresponding to each column in the check matrix H is input one by one to the check node calculator 101. An absolute value D122 (|vi|), which is five less significant bits of the message D101, is supplied to a LUT 121, and a sign bit D121, which is the most significant bit of the message D101, is supplied to an EXOR circuit 129 and a FIFO (First In First Out) memory 133. The check node calculator 101 is also supplied with the control signal D106 from the controlling unit 105. The control signal D106 is supplied to a selector 124 and a selector 131.
The LUT 121 reads a five-bit operation result D123 (φ(|vi|)) obtained by performing the operation of the nonlinear function φ(|vi|) in Equation (7) in response to the absolute value D122 (|vi|). The LUT 121 supplies the five-bit result D123 (φ(|vi|)) to an arithmetic unit 122 and a FIFO memory 127.
The arithmetic unit 122 integrates the five-bit operation result D123 (φ(|vi|)) by adding the operation result D123 to a nine-bit value D124 stored in a register 123. The arithmetic unit 122 re-stores a resulting nine-bit integrated value in the register 123. Incidentally, when results D123 of operation on the absolute values D122 (|vi|) of messages D101 from all edges over one row of the check matrix H are integrated, the register 123 is reset.
The arithmetic unit 122 and the register 123 integrate the five-bit operation result D123 (φ(|vi|)) supplied from the LUT 121 a number of times that, at a maximum, corresponds to a maximum number of delays in the FIFO memory 127, that is, a maximum row weight of the check matrix H. The maximum row weight of the check matrix H in FIG. 9 is nine. Hence, the arithmetic unit 122 and the register 123 integrate the five-bit operation result D123 (φ(|vi|)) nine times at a maximum (perform integration for nine five-bit values). Thus, in order to be able to represent a value obtained by integrating the five-bit value nine times, the number of quantization bits in the output of the arithmetic unit 122 and subsequent outputs is nine, which is larger by four (a minimum number of bits that can represent nine (times)) than that of the five-bit operation result D123 (φ(|vi|)) output by the LUT 121.
When the messages D101 (variable node messages vi) over one row of the check matrix are read one by one, and an integrated value obtained by integrating operation results D123 for one row is stored in the register 123, the control signal D106 supplied from the controlling unit 105 is changed from zero to one. For example, in a case where the row weight of the check matrix is "9", the control signal D106 is "0" for a first to an eighth clock, and is "1" for a ninth clock.
When the control signal D106 is "1", the selector 124 selects the value stored in the register 123, that is, the nine-bit integrated value D124 (Σφ(|vi|) from i=1 to i=dc) obtained by integrating φ(|vi|) obtained from the messages D101 (variable node messages vi) from all the edges over one row of the check matrix H, and then outputs the value as a value D125 to the register 125 to store the value D125 in the register 125. The register 125 supplies the value D125 stored therein as a nine-bit value D126 to the selector 124 and an arithmetic unit 126. When the control signal D106 is "0", the selector 124 selects the value D126 supplied from the register 125, and then outputs the value D126 to the register 125 to re-store the value D126 in the register 125. That is, until φ(|vi|) obtained from the messages D101 (variable node messages vi) from all the edges over one row of the check matrix H is integrated, the register 125 supplies previously integrated φ(|vi|) to the selector 124 and the arithmetic unit 126.
Meanwhile, the FIFO memory 127 delays the five-bit operation result D123 (φ(|vi|)) output by the LUT 121 until the new value D126 (Σφ(|vi|) from i=1 to i=dc) is output from the register 125, and then supplies the five-bit operation result D123 (φ(|vi|)) as a five-bit value D127 to the arithmetic unit 126. The arithmetic unit 126 subtracts the value D127 supplied from the FIFO memory 127 from the value D126 supplied from the register 125. The arithmetic unit 126 supplies a result of the subtraction as a five-bit subtraction value D128 to a LUT 128. That is, the arithmetic unit 126 subtracts φ(|vi|) obtained from a message D101 (variable node message vi) from an edge for which a check node message uj is desired to be obtained from the integrated value of φ(|vi|) obtained from the messages D101 (variable node messages vi) from all the edges over one row of the check matrix H. The arithmetic unit 126 supplies the subtraction value (Σφ(|vi|) from i=1 to i=dc−1) as the subtraction value D128 to the LUT 128.
Incidentally, since the arithmetic unit 126 subtracts the five-bit value D127 supplied from the FIFO memory 127 from the nine-bit value D126 supplied from the register 125, the result of the subtraction can be nine bits at a maximum, whereas the arithmetic unit 126 outputs the five-bit subtraction value D128. Therefore, when the result of the subtraction of the five-bit value D127 supplied from the FIFO memory 127 from the nine-bit value D126 supplied from the register 125 cannot be represented by five bits, that is, when the result of the subtraction exceeds a maximum value (31 (11111 as a binary number) that can be represented by five bits, the arithmetic unit 126 clips the result of the subtraction to the maximum value that can be represented by five bits, and then outputs the five-bit subtraction value D128.
The LUT 128 outputs a five-bit operation result D129 (φ−1(Σφ(|vi|))) obtained by performing the operation of the inverse function φ−1(Σφ(|vi|)) in Equation (7) in response to the subtraction value D128 (Σφ(|vi|) from i=1 to i=dc−1).
In parallel with the above processing, an EXOR circuit 129 calculates an exclusive OR of a one-bit value D131 stored in a register 130 and the sign bit D121, and thereby multiplies the sign bits together. The EXOR circuit 129 re-stores a one-bit multiplication result D130 in the register 130. Incidentally, when the sign bits D121 of messages D101 (variable node messages vi) from all edges over one row of the check matrix H are multiplied together, the register 130 is reset.
When a multiplication result D130 (Πsign(vi) from i=1 to dc) obtained by multiplying together the sign bits D121 of the messages D101 from all the edges over one row of the check matrix H is stored in the register 130, the control signal D106 supplied from the controlling unit 105 is changed from zero to one.
When the control signal D106 is "1", the selector 131 selects the value stored in the register 130, that is, the value D131 (Πsign(vi) from i=1 to i=dc) obtained by multiplying together the sign bits D121 of the messages D101 from all the edges over one row of the check matrix H, and then outputs the value D131 as a one-bit value D132 to a register 132 to store the value D132 in the register 132. The register 132 supplies the value D132 stored therein as a one-bit value D133 to the selector 131 and an EXOR circuit 134. When the control signal D106 is "0", the selector 131 selects the value D133 supplied from the register 132, and then outputs the value D133 to the register 132 to re-store the value D133 in the register 132. That is, until the sign bits D121 of the messages D101 (variable node messages vi) from all the edges over one row of the check matrix H are multiplied together, the register 132 supplies a previously stored value to the selector 131 and the EXOR circuit 134.
Meanwhile, the FIFO memory 133 delays the sign bit D121 until the new value D133 (Πsign(vi) from i=1 to i=dc) is output from the register 132 to the EXOR circuit 134, and then supplies the sign bit D121 as a one-bit value D134 to the EXOR circuit 134. The EXOR circuit 134 calculates an exclusive OR of the value D133 supplied from the register 132 and the value D134 supplied from the FIFO memory 133, and thereby divides the value D133 by the value D134. The EXOR circuit 134 then outputs a one-bit division result as a divided value D135. That is, the EXOR circuit 134 divides the value obtained by multiplying together the sign bits D121 (sign(|vi|) of the messages D101 from all the edges over one row of the check matrix H by a sign bit D121 (sign (vi)) of a message D101 from an edge for which a check node message uj is desired to be obtained. The EXOR circuit 134 supplies the divided value (Πsign(vi) from i=1 to i=dc−1) as the divided value D135.
The check node calculator 101 then outputs, as a message D102 (check node message uj), a total of six bits with the five-bit operation result D129 output from the LUT 128 as five less significant bits and the one-bit divided value D135 output from the EXOR circuit 134 as a most significant bit (sign bit).
As described above, the check node calculator 101 performs the operations of Equation (7), and thereby obtains the check node message uj.
Incidentally, since the maximum row weight of the check matrix H of FIG. 9 is nine, that is, since the maximum number of variable node messages vi supplied to the check node is nine, the check node calculator 101 has the FIFO memory 127 for delaying results (φ(|vi|)) of the operation of the nonlinear function on nine variable node messages vi and the FIFO memory 133. When a check node message uj for a row with a row weight of less than nine is to be calculated, an amount of delay in the FIFO memory 127 and the FIFO memory 133 is reduced to the value of the row weight.
FIG. 12 shows an example of configuration of the variable node calculator 103 in FIG. 10 that performs the variable node operation on a one-by-one basis.
Incidentally, as with FIG. 11, FIG. 12 shows the variable node calculator 103 supposing that each message is quantized into a total of six bits including a sign bit. Also in FIG. 12, the variable node operation on the LDPC code represented by the check matrix H of FIG. 9 is performed. The variable node calculator 103 in FIG. 12 is supplied with a clock ck. The clock ck is supplied to necessary blocks. The blocks perform processing in synchronism with the clock ck.
According to a one-bit control signal D107, for example, supplied from the controlling unit 105, the variable node calculator 103 in FIG. 12 performs the operation (variable node operation) according to Equation (1) using messages D103 read one by one from the edge memory 102 and received data D104 (u0i) read from the receiver memory 104.
Specifically, a six-bit message D103 (check node message uj) from a check node corresponding to each row in the check matrix H is input one by one to the variable node calculator 103. The message D103 is supplied to an arithmetic unit 151 and a FIFO memory 155. In addition, in the variable node calculator 103, six-bit received data D104 (u0i) read from the receiver memory 104 on a one-by-one basis is supplied to an arithmetic unit 156. Further, the variable node calculator 103 is supplied with the control signal D107 from the controlling unit 105. The control signal D107 is supplied to a selector 153.
The arithmetic unit 151 integrates the six-bit message D103 (check node message uj) by adding the six-bit message D103 to a nine-bit value D151 stored in a register 152. The arithmetic unit 151 re-stores a resulting nine-bit integrated value in the register 152. Incidentally, when messages D103 from all edges over one column of the check matrix H are integrated, the register 152 is reset.
The arithmetic unit 151 and the register 152 integrate the six-bit message D103 a number of times that, at a maximum, corresponds to a maximum number of delays in the FIFO memory 155, that is, a maximum column weight of the check matrix H. The maximum column weight of the check matrix H in FIG. 9 is five. Hence, the arithmetic unit 151 and the register 152 integrate the six-bit message D103 five times at a maximum (perform integration for five six-bit values). Thus, in order to be able to represent a value obtained by integrating the six-bit value five times, the number of quantization bits in the output of the arithmetic unit 151 and subsequent outputs is nine, which is larger by three (a minimum number of bits that can represent five [times]) than that of the six-bit message D103.
When the messages D103 over one column of the check matrix H are read one by one, and an integrated value obtained by integrating the message D103 for one column is stored in the register 152, the control signal D107 supplied from the controlling unit 105 is changed from zero to one. For example, in a case where the column weight of the check matrix is "5", the control signal D107 is "0" for a first to a fourth clock, and is "1" for a fifth clock.
When the control signal D107 is "1", the selector 153 selects the value stored in the register 152, that is, the nine-bit value D151 (Σuj from j=1 to dV) obtained by integrating the messages D103 (check node messages uj) from all the edges over one column of the check matrix H, and then outputs the value D151 to a register 154 to store the value D151 in the register 154. The register 154 supplies the value D151 stored therein as a nine-bit value D152 to the selector 153 and the arithmetic unit 156. When the control signal D107 is "0", the selector 153 selects the value D152 supplied from the register 154, and then outputs the value D152 to the register 154 to re-store the value D152 in the register 154. That is, until the messages D103 (check node messages uj) from all the edges over one column of the check matrix H are integrated, the register 154 supplies a previously integrated value to the selector 153 and the arithmetic unit 156.
Meanwhile, the FIFO memory 155 delays the message D103 from the check node until the new value D152 (Σuj from j=1 to dV) is output from the register 154, and then supplies the message D103 as a six-bit value D153 to the arithmetic unit 156. The arithmetic unit 156 subtracts the value D153 supplied from the FIFO memory 155 from the value D152 supplied from the register 154. That is, the arithmetic unit 156 subtracts a check node message uj from an edge for which a variable node message vi is desired to be obtained from the integrated value of the messages D103 (check node messages uj) from all the edges over one column of the check matrix H. The arithmetic unit 156 thereby obtains the subtraction value (Σuj from j=1 to dV−1). Further, the arithmetic unit 156 adds the subtraction value (Σuj from j=1 to dV−1) to the received data D104 (u0i) supplied from the receiver memory 104. The arithmetic unit 156 supplies a resulting six-bit value as a message D105 (variable node message vi).
As described above, the variable node calculator 103 performs the operations of Equation (1), and thereby obtains the variable node message vi.
Incidentally, since the maximum column weight of the check matrix H of FIG. 9 is five, that is, since the maximum number of check node messages uj supplied to the variable node is five, the variable node calculator 103 has the FIFO memory 155 for delaying five check node messages uj. When a variable node message vi for a column with a column weight of less than five is to be calculated, an amount of delay in the FIFO memory 155 is reduced to the value of the column weight.
The arithmetic unit 156 performs the operations of subtracting the six-bit value D153 supplied from the FIFO memory 155 from the nine-bit value D152 supplied from the register 154, and adding the value obtained by the subtraction to the six-bit received data D104 supplied from the receiver memory 104. A result of the operations may be less than a minimum value that can be represented by the six-bit message D105, or may exceed a maximum value that can be represented by the six-bit message D105. When the operation result is less than the minimum value that can be represented by the six-bit message D105, the arithmetic unit 156 clips the operation result to the minimum value. When the operation result exceeds the maximum value that can be represented by the six-bit message D105, the arithmetic unit 156 clips the operation result to the maximum value.
In the decoding device of FIG. 10, the control signals are supplied from the controlling unit 105 according to the weights of the check matrix H. The decoding device of FIG. 10 can decode the LDPC codes of various check matrices H by changing only the control signals as long as the edge memories 100 and 102 and the FIFO memories 127, 133, and 155 in the check node calculator 101 and the variable node calculator 103 have sufficient capacities.
Though not shown in the figures, the decoding device of FIG. 10 performs the operation of Equation (5) in place of the variable node operation of Equation (1) in a final decoding stage, and outputs a result of the operation as a final decoding result.
When an LDPC code is decoded by using the decoding device of FIG. 10 repeatedly, the check node operation and the variable node operation are performed alternately. Specifically, in the decoding device of FIG. 10, the variable node calculator 103 performs the variable node operation using a result of the check node operation by the check node calculator 101, and the check node calculator 101 performs the check node operation using a result of the variable node operation by the variable node calculator 103.
Incidentally, while FIG. 10 shows a full serial decoding device that decodes an LDPC code by sequentially performing operations at nodes one by one as an example of implementation of a decoding device, other decoding devices have been proposed in C. Howland and A. Blanksby, "Parallel Decoding Architectures for Low Density Parity Check Codes", Symposium on Circuits and Systems, 2001 [Non-Patent Literature 1] and E. Yeo, P. Pakzad, B. Nikolic, and V. Anantharam, "VLSI Architectures for Iterative Decoders in Magnetic Recording Channels", IEEE Transactions on Magnetics, Vol. 37, No. 2, March 2001 [Non-Patent Literature 2]. The Non-Patent Literature 1 is a full parallel decoding device that performs decoding by performing operations at all nodes simultaneously. The Non-Patent Literature 2 is a partly parallel decoding device that simultaneously performs operations at a certain number of nodes rather than one node or all nodes.
For example, in the decoding device of FIG. 10, the number of bits at least equal to a value obtained by multiplying the code length of the LDPC code by the number of bits of quantization values representing the received data D104 (the number of quantization bits) is required as a storage capacity of the receiver memory 104 for storing the received data D104. The number of bits at least equal to a value obtained by multiplying a total number of edges by the number of bits of quantization values representing messages is required as storage capacities of the edge memories 100 and 102 for storing the messages.
Hence, when the code length is 108, the number of bits of the quantization values representing the messages (including the received data D104) is six, and the number of edges is 323, as described above, the receiver memory 104 having a storage capacity of at least 648 (=108×6) bits and the edge memories 100 and 102 having a storage capacity of at least 1938 (=323×6) bits are required.
Incidentally, in this case, the code length is 108 for simplicity of the description; in practice, however, a few thousand is used as the code length of an LDPC code.
On the other hand, when considered simply, to improve accuracy of decoding of an LDPC code requires quantization values of a certain number of bits as the quantization values representing the messages (including the received data D104).
However, as described above, the storage capacities of the edge memories 100 and 102 and the receiver memory 104 are proportional to the number of bits of the quantization values representing the messages. Therefore, when the messages are represented by a quantization value of a large number of bits, high-capacity memories are required as memories forming the decoding device, thus increasing the scale of the device.


An industrial machine startup control system for controlling startup of an industrial machine, the industrial machine startup control system including: a vital data measurement device that measures vital data of a worker; a health state analysis device that acquires the vital data of the worker measured by the vital data measurement device, and that determines a health state of the worker based on the acquired vital data; and a startup control device that controls whether or not to allow startup of the industrial machine based on the determination result from the health state analysis device.

Generally, when starting industrial machines including construction machines, agricultural machines, machine tools, woodworking machines, and the like, it is necessary for conditions, such as all of the actuators being at their origin positions, no one being within the machine driving range, sufficient raw materials being loaded, and the like, to be met.
For example, Patent Document 1 proposes technology wherein a plurality of light emitters and a plurality of light receivers are arranged to form a curtain comprising a plurality of light beams, the presence or absence of workers or materials is detected on the basis of whether the curtain of light beams is blocked, the working state of a worker is determined by counting the number of times, after the curtain of light beams has been blocked, that the blocked light enters a restored state, and an industrial machine is controlled so as to be able to start at a correct timing in accordance with the determination result.
When a worker having a health problem operates an industrial machine, there is a possibility that the health state of the worker will deteriorate during the operating work, and the worker cannot continue to perform the operations. As technology for monitoring the health state of a worker, Patent Document 2 proposes, for example, technology wherein the worker wears a biosensor device that is in a wearable form, and when the biosensor device detects an abnormality in the worker, a warning is displayed in accordance with the type of abnormality.

Industrial machine startup control system, startup control method, and program


The invention is directed to a process for the preparation of thiocarboxylate silane comprising reacting an aqueous solution of a salt of a thiocarboxylic acid with a haloalkylalkoxysilane in the presence of a solid supported catalyst. The invention is also directed to a process for the preparation of an aqueous solution of a salt of a thiocarboxylic acid which comprises reacting an aqueous solution of a sulfide and/or hydrosulfide with a carboxylic acid halide and/or acid anhydride.

Thiocarboxylate-functional silanes are coupling agents which are used extensively in rubber applications such as tires and tire components. Several batch processes of making thiocarboxylate-functional silane are known. The batch processes include the reactions of alkali metal salts of mercapto-functional silanes with carboxylic acid chlorides or the reactions of alkali metal salts of alkylthioic acids with halo alkyl-containing silanes. The later process, the reactions of alkali metal salts of alkylthioic acids with halo alkyl-containing silanes, are advantageously carried out in a two-phase batch process in which an aqueous phase of the alkali metal salts of alkylthioic acids is reacted with a non-aqueous phase of the halo alkyl-containing silane, often in the presence of phase transfer catalyst. The two-phase batch process eliminates the need to handle solid alkali halide salts, which are a byproduct of the reaction, because these salts are soluble in the aqueous phase.
However, the two-phase batch process has the disadvantages of having to conduct washing of the non-aqueous phase, requiring long reaction times and forming meta-stable rag layers. The washing is needed to remove the phase transfer catalyst from the non-aqueous phase containing the reaction product. The phase transfer catalyst is an undesirable impurity in the product which may affect the curing of the rubber compositions in which the thiocarboxylate-functional silanes are used. The long reaction times results from the diffusion control transport of the alkali metal salts into the non-aqueous phase, and the need to carry out the reaction to completion before the next batch can be started. The meta-stable rag layer, which is an emulsified mixture of water, the reaction products and the phase transfer catalyst, make the separation of the two-phases difficult, often resulting in loss of reaction product.
The use of the two-phase batch process results in the process having the problems of being expensive, long and of limited capacity. Thus, there still exists a need for a process of making thiocarboxylate-functional silane that provides for efficient reaction of a two-phase reaction mixture, reduction of rag layers and very low amounts and advantageously, absence of phase transfer catalysts in the final product.

Continuous process for the preparation of thiocarboxylate silane


The present invention provides a computer implemented method for placing feathers on a surface. The method includes providing a surface having a plurality of vertices and establishing a growing direction for each of the plurality of vertices on the surface. Feathers are placed on the surface based on the plurality of vertices and the growing direction.

The present invention relates to computer generated graphics, in particular, the modeling and rendering of feathers using a computer.
Computer graphics are used in many different applications including computer games, movies and web pages. Graphically modeling and rendering of feathers for a realistic simulation of birds and other feather objects is a difficult task. In general, graphical feathers are generated on an ad hoc basis that consumes a significant amount of an artist's time to study and draw feathers. Thus, a systematic method for rendering feathers is useful.


The distance between a discrete or passive electrical component and an electrical semiconductor device and substrate or carrier is minimized by shortening the lead length connections of the passive component. One or more passive electronic components are mounted within the body of a carrier or board by creating a cavity in the substrate or carrier that is directly below a semiconductor device. The passive component is electrically connected to the substrate and device using solder bump technology resulting in much shorter lead length connections to and from the passive component.

1. Field of the Invention
The present invention relates generally to integrated circuit packaging, and in particular to a structure and method for minimizing the lead length between a passive electronic device and an integrated circuit.
2. Description of Related Art
Semiconductor devices having high and dense lead counts and operating at high speeds require very short leads to ensure noiseless signal propagation. Noise can be introduced onto a lead by other nearby signal leads. Additionally, passive devices or components, such as resistors, capacitors, inductors and filters, add to the length of signal leads within an assembly. As used herein, the term xe2x80x9csemiconductor devicexe2x80x9d or xe2x80x9cdevicexe2x80x9d refers to an integrated circuit chip or die containing circuitry. The xe2x80x9ccarrierxe2x80x9d refers to the substrate material upon which the device is attached and contains internal circuitry that is used to interface the device with other electronic components. The xe2x80x9csemiconductor device assemblyxe2x80x9d or xe2x80x9cassemblyxe2x80x9d refers to the semiconductor device plus associated carrier containing the device. The xe2x80x9cpassivexe2x80x9d refers to resistors, inductors, filters, capacitors and any combination attached to the carrier and/or device as a component of the assembly. A xe2x80x9cboardxe2x80x9d is a structure that is used to hold a plurality of carriers.
The lead length effect is highly affected by the capacitor type passive component. It is highly desirable to locate the capacitors as close to the semiconductor device as possible. It is a common practice to mount capacitors external to the semiconductor device. In some carriers, the capacitors may be mounted on the same plane as the device but off to one side or another. Another carrier structure might attach the capacitor within a socket or cavity on the carrier. In either case, the capacitor is xe2x80x9cremotelyxe2x80x9d located away from the semiconductor device. As the distance from the capacitor to the semiconductor device increases, the capacitor""s efficiency and effectiveness are adversely affected. Problems that can occur include stray inductances, ground plane bounce, and voltage surges.
Attempts in the prior art to reduce lead lengths has not resolved these problems. For example, U.S. Pat. No. 5,210,683 discloses an assembly for mounting a capacitor, external to a semiconductor device, within a well or cavity that is formed in the assembly in close proximity to the device such that it is located within the assembly and thereby somewhat reducing the lead or via length. However, the major problem of connectivity to the device, without electrical noise still exists with this structure.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a structure and method for minimizing the lead length between a passive electronic component, a carrier or board, and an electronic device.
It is another object of the present invention to provide a structure and method to minimize the distance between a passive electronic device and a semiconductor device.
A further object of the invention is to provide a method and structure to minimize the length of signal leads within a semiconductor device assembly.
It is yet another object of the present invention to provide a method and structure to minimize the ability of electrical noise to be induced onto nearby signal leads.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one skilled in the art, are achieved in the present invention which is directed to, in a first aspect, a method of electrically connecting a passive electronic component to a semiconductor substrate and a semiconductor device whereby the lead lengths between the passive electrical component, the substrate and the device are minimized. In the preferred embodiment, the method comprises forming a first cavity in a layer of a semiconductor substrate. The first cavity has at least one electrical termination pad on one of its surfaces. A first passive electrical component is electrically connected in the first cavity, the electrical connection being made between at least one electrical connection point on a surface of the first component and the electrical termination pad of the cavity. A semiconductor device is placed over the first cavity and first component such that an electrical termination pad on the semiconductor device makes an electrical connection with a second connection point on the first component.
In the preferred embodiment, a second cavity having at least one electrical termination pad is also formed in the substrate and a second passive electrical component is electrically connected to an electrical connection point in the second cavity. In the most preferred embodiment, a number of cavities are formed in the substrate surface, each one being adapted to have a passive electrical component mounted therein with an electrical connection being made between termination pads in the cavity and electrical connection points on the component.
In the preferred embodiment, the electrical connection points on the passive component are solder bumps and the electrical connections are made using controlled collapse chip connection technology. In the most preferred embodiment, the electrical connection points are located on opposing sides of the component.
In another aspect, the method may include forming a multilevel cavity adapted to hold a plurality of passive electrical components.
In the preferred embodiment, the substrate includes a plurality of layers including at least one layer of internal circuitry used to interface the passive components with at least one other electrical device. It is also preferred that the method include electrically connecting the substrate to at least one passive electrical component mounted in a cavity formed in an electronic circuit board.
In another aspect, the present invention is directed to a structure for electrically connecting a discrete electrical component between a semiconductor substrate and an electronic semiconductor device whereby the lead length of the discrete electrical device is minimized. The structure comprises at least one cavity formed in a semiconductor substrate, and at least one discrete electrical component located in the cavity. The electronic component is electrically connected to the substrate and a semiconductor device positioned over the cavity. In the preferred embodiment, the cavity includes at least one electrical termination pad on a surface of the cavity which is electrically connected to an electrical connection point on the electrical component. In the preferred embodiment, the electrical connection points on the component are located on opposing sides of the component. It is preferred that the electrical connection points are solder bumps.
In the preferred embodiment, the component is electrically connected to the substrate and the semiconductor device, most preferably using solder connection technology. It is also preferred that the solder connection technology is controlled collapse connection technology.
The cavity may also comprise a multilevel cavity adapted to contain a plurality of discrete components electrically connected to the substrate semiconductor device. In the preferred embodiment, the substrate layer includes at least one layer of internal circuitry used to interface the discrete electrical component with at least one other electrical device. In the preferred embodiment, the electronic circuit board may have at least one cavity formed therein adapted to contain at least one discrete electrical component electrically connected to the circuit board and the substrate.

Multi-cavity substrate structure for discrete devices

International Business Machines Corporation


An iron (Fe)-based austenitic heat-resistant cast steel includes, based on a total of 100 mass % (indicated below simply as “%”): 0.4 to 0.8% of carbon (C), 3.0% or less of silicon (Si), 0.5 to 2.0% of manganese (Mn), 0.05% or less of phosphorus (P), 0.03 to 0.2% of sulfur (S), 18 to 23% of chromium (Cr), 3.0 to 8.0% of nickel (Ni) and 0.05 to 0.4% of nitrogen (N). A ratio of chromium (Cr) to carbon (C) is in a range of 22.5≦Cr/C≦57.5. The cast steel includes one or two or more of vanadium (V), molybdenum (Mo), tungsten (W) and niobium (Nb) in a total amount of less than 0.2%.

1. Field of the Invention
The invention relates to austenitic heat-resistant cast steels, and more particularly to austenitic heat-resistant cast steels having excellent thermal fatigue characteristics.
2. Description of the Related Art
In order for austenitic heat-resistant cast steels to have excellent thermal fatigue characteristics at 950° C. or more, for example, they must have excellent high-temperature strength properties and excellent toughness from room temperature to elevated temperatures. Temperature-resistant cast steels for resolving such a challenge are described in Japanese Patent Application Publication No. 2004-269979 (JP-A-2004-269979) and Japanese Patent Application Publication No. 2002-194511 (JP-A-2002-194511). JP-A-2004-269979 discloses temperature-resistant cast steels which, based on a total of 100 mass %, include 0.5 to 1.5% of carbon (C), 0.01 to 2% of silicon (Si), 3 to 20% of manganese (Mn), 0.03 to 0.2% of phosphorus (P), 3 to 20% of nickel (Ni), 10 to 25% of chromium (Cr), 0.5 to 4% of niobium (Nb) and 0.1% or less of aluminum (Al), and which also include a total of 1.5 to 6% of one or both of molybdenum (Mo) and tungsten (W), with the balance being primarily iron (Fe).
In iron-based austenitic heat-resistant cast steels, carbon is effective for increasing high-temperature strength and improving castability, and acts as an austenite phase-stabilizing element. Chromium is effective for improving the high-temperature strength, but lowers the toughness when added in a large amount. Moreover, the presence of nickel together with chromium helps increase the high-temperature strength, stabilizing the austenite phase. In light of the above, among iron-based austenitic heat-resistant cast steels according to the related art, use is frequently made of steels containing about 0.3 to 0.8% of carbon, about 10 to 25% of chromium and about 10 to 21% of nickel. In the Japanese industrial Standards (JIS), such steels are designated as, for example, SCH12 and SCH22.
In recent years, nickel has become an increasingly scarce element, in addition to which the cost has skyrocketed. For these reasons, even in austenitic heat-resistant cast steels, the tendency has been to seek lower nickel levels. However, at a low nickel content, the matrix structure is unable to achieve a uniform austenite phase, as a result of which the high-temperature strength decreases. Hence, it is not easy to lower the nickel level while maintaining high-temperature strength characteristics. Adding elements such as vanadium, molybdenum, tungsten and niobium is effective for enhancing the strength. However, these elements have a tendency to lower the toughness, thus making it difficult to achieve both high-temperature strength and toughness.