The present invention discloses a continuous process and the associated system for upstaging liquid epoxy resins to produce resins with higher molecular weight. The process comprises passing continuously (i) a liquid epoxy resin having a first molecular weight, (ii) a catalyst and (iii) a compound having at least one active hydrogen or reactive functional group capable of reacting with the liquid epoxy resin in the presence of the catalyst, flow through one or more reaction chambers and under conditions effective to produce a stream comprising an upstaged epoxy resin product having a second molecular weight. The second molecular weight is higher than the first molecular weight.

The present invention relates to an integrated continuous process and the associated system for upstaging lower molecular weight liquid epoxy resins in one or more reactor chambers with one or more reaction zones in each chamber to produce a stream comprising a higher molecular weight product of resinous polyepoxides, hydroxy-terminated polyethers or phenolic terminated polyethers.
Epoxy resins have been known for many years. In combination with a suitable curing agent, such thermosetting resinous polyepoxides, have produced thermosetting polymers useful for many applications, providing a combination of superior toughness, flexibility, adhesion and electrical properties and chemical resistance in the finished products. The terms xe2x80x9cpolyepoxide,xe2x80x9d xe2x80x9cresinous polyepoxide,xe2x80x9d xe2x80x9cpolyethersxe2x80x9d and xe2x80x9cepoxy resinxe2x80x9d are used herein interchangeably.
The most common types of resinous polyepoxides are produced by reacting monomeric epoxy compounds, such as epichlorohydrin, with polyhydric (including dihydric) phenols, such as bisphenol-A (BPA), to give diglycidyl ethers. Depending primarily upon their molecular weights, resinous polyepoxides may vary from a viscous liquid to a high melting solid.
Higher molecular weight solid or semi-solid resinous polyepoxides, hydroxy- or phenolic-terminated polyethers are often made by a process known as xe2x80x9cupstaging,xe2x80x9d xe2x80x9cupgrading,xe2x80x9d xe2x80x9cfusionxe2x80x9d or xe2x80x9cadvancementxe2x80x9d. In such an upstaging or advancement process, a lower molecular weight liquid resinous polyepoxide is reacted with a polyhydric, most often dihydric, phenol in the presence of a catalyst until enough of the phenol is incorporated into the epoxy polymer chain, terminally and/or as a crosslinking agent, to increase the molecular weight of the upstaged epoxy resin product to the desired level. If the molecular weight is high enough, the product is in the solid form at room temperature. Other than using polyhydric phenols, it also is known that such an upstaging process may be carried out using carboxyl- or other hydroxyl-containing compounds or mixtures thereof.
The upstaging processes have in the past been carried out in both a batch process or a continuous process. See, for example, U.S. Pat. Nos. 3,547,881, 3,919,169 and 4,612,156. Typically in these known batch and continuous upstaging processes, the dihydric phenols and liquid polyepoxide are admixed or otherwise contacted with a catalyst at a relatively low temperature and then heated up to the reaction temperature and held at a desired reaction temperature and other conditions for a time sufficient to produce the resinous polyepoxide or hydroxy-terminated polyether of a higher molecular weight. Sometimes, the catalyst is added after the reactants have already been mixed and heated up to a higher temperature.
The cycle times are relatively long in typical batch upstaging processes. This cycle time includes charging of the raw materials, the upstaging reaction itself, discharging and solidification/packaging of the product. For example, a batch process involving bisphenol-A or tetrabromobisphenol A (TBBPA) and a liquid polyepoxide consisting essentially of the diglycidyl ether of bisphenol-A can take from about 8 to about 12 hours of cycle time to complete. It would be advantageous to shorten the cycle time needed in a batch process as well as the residence time in a continuous process to increase productivity and/or to reduce capital investment.
Furthermore, it is difficult to maintain the homogeneity of temperature in a large batch reaction vessel. Since the upstaging reaction is exothermic and the viscosity of the reaction mixture is usually quite high, there may be heat-transfer problems, localized hot spots and/or substantial temperature gradients inside the vessel. Unintended and adverse gelling, non-uniform upstaging, over- or under-crosslinking, localized side-reactions or byproduct formation also may take place as a result of non-uniform reaction conditions. All of these problems can lead to non-uniform inhomogeneous product compositions and/or product properties. For example, the product may exhibit broad molecular weight distributions, broad softening points or glass transition temperatures, inconsistent chemical compositions and others. In addition to such problems within a given batch, it is also not unusual to have significant batch-to-batch differences. These differences may cause additional problems in various applications due to varying molecular weight distributions and the associated changes in viscosity and other properties such as softening point or glass transition temperatures.
As mentioned earlier, certain continuous reaction systems have been proposed or disclosed to upstage epoxy resins using, for example, a long tubular (pipe) reactor (length/diameter=900) and a long tubular post-heat zone (I/d=1020) as disclosed in U.S. Pat. No. 3,919,169; or using a twin-screw extruder reactor as disclosed in U.S. Pat. No. 4,612,156. Long tubular or pipe reactors are generally known to subject to fouling problems due to heavies buildup and the upstaged products tend to show broad molecular weight distributions (so-called polydispersion or MW/Mn, the ratio of weight averaged molecular weight and number averaged molecular weight). The extruder reactor is an expensive piece of equipment for commercial scale productions. While these two patents might have disclosed certain general concepts with respect to continuous upstaging of epoxy resins, they disclose neither the use of a solvent in the system, nor the advantages of using non-tubular/non-extruder type reactors and/or the importance of particular modes of flow or flow directions of feeds.

Integrated continuous process for upstaging epoxy resins


A system and method creates multiple, symmetric spanning trees within a network. Bridges within the network generate, send and process Spanning Tree Protocol (STP) control messages that are updated as they are propagated across the network to reflect the paths followed by the messages. The bridges, moreover, utilize the path indication value of received STP control messages to compute the spanning trees. The path indication values are preferably derived from the sum of Bridge Identifiers (IDs) corresponding to the bridges through which the STP control message has passed from the root bridge to the current bridge processing the STP control message. Each bridge also tags newly received messages with the Virtual Local Area Network (VLAN) identifier (VID) associated with the spanning tree for which the bridge is the root, thereby causing the messages to follow more optimal paths through the network.

1. Field of the Invention
The present invention relates generally to computer networks, and more specifically, to a method and apparatus for efficiently transmitting messages across the network.
2. Background Information
Many organizations, including businesses, governments and educational institutions, utilize computer networks so that employees and others may share and exchange information and/or resources. A computer network typically comprises a plurality of entities interconnected by means of one or more communications media. An entity may consist of any device, such as a computer, that "sources" (i.e., transmits) or "sinks" (i.e., receives) data frames over the communications media. A common type of computer network is a local area network ("LAN") which typically refers to a privately owned network within a single building or campus. LANs typically employ a data communication protocol (LAN standard), such as Ethernet, or a wireless protocol, that defines the functions performed by data link and physical layers of a communications architecture (i.e., a protocol stack).
One or more intermediate network devices are often used to couple LANs together and allow the corresponding entities to exchange information. For example, a bridge may be used to provide a "switching" function between two or more LANs or end stations. Typically, the bridge is a computer and includes a plurality of ports that are coupled via LANs either to other bridges, or to end stations such as routers or host computers. Ports used to couple bridges to each other are generally referred to as a trunk ports, whereas ports used to couple bridges to end stations are generally referred to as access ports. The bridging function includes receiving data from a sending entity at a source port and transferring that data to at least one destination port for forwarding to one or more receiving entities.
Spanning Tree Algorithm
Most computer networks include redundant communications paths so that a failure of any given link does not isolate any portion of the network. Such networks are typically referred to as meshed or partially meshed networks. The existence of redundant links, however, may cause the formation of circuitous paths or "loops" within the network. Loops are highly undesirable because data frames may traverse the loops indefinitely.
Furthermore, some devices, such as bridges or switches, replicate frames whose destination is not known resulting in a proliferation of data frames along loops. The resulting traffic can overwhelm the network. Other intermediate devices, such as routers, that operate at higher layers within the protocol stack, such as the Internetwork Layer of the Transmission Control Protocol/Internet Protocol ("TCP/IP") reference model, deliver data frames and learn the addresses of entities on the network differently than most bridges or switches, such that routers are generally not susceptible to sustained looping problems.
To avoid the formation of loops, most bridges and switches execute a spanning tree protocol which allows them to calculate an active network topology that is loop-free (i.e., a tree) and yet connects every pair of LANs within the network (i.e., the tree is spanning). The IEEE promulgated a standard (IEEE Std. 802.1D-1998™) that defines a spanning tree protocol to be executed by 802.1D compatible devices. In general, by executing the 802.1D spanning tree protocol, bridges elect a single bridge within the bridged network to be the "Root Bridge". The 802.1D standard takes advantage of the fact that each bridge has a unique numerical identifier (bridge ID) by specifying that the Root Bridge is the bridge with the lowest bridge ID. In addition, for each LAN coupled to any bridge, exactly one port (the "Designated Port") on one bridge (the "Designated Bridge") is elected. The Designated Bridge is typically the one closest to the Root Bridge. All ports on the Root Bridge are Designated Ports, and the Root Bridge is the Designated Bridge on all the LANs to which it has ports.
Each non-Root Bridge also selects one port from among its non-Designated Ports (its "Root Port") which gives the lowest cost path to the Root Bridge. The Root Ports and Designated Ports are selected for inclusion in the active topology and are placed in a forwarding state so that data frames may be forwarded to and from these ports and thus onto the LANs interconnecting the bridges and end stations of the network. Ports not included within the active topology are placed in a blocking state. When a port is in the blocking state, data frames will not be forwarded to or received from the port. A network administrator may also exclude a port from the spanning tree by placing it in a disabled state.
To obtain the information necessary to run the spanning tree protocol, bridges exchange special messages called configuration bridge protocol data unit (BPDU) messages or simply BPDUs. BPDUs carry information, such as assumed root and lowest root path cost, used in computing the active topology. More specifically, upon start-up, each bridge initially assumes itself to be the Root Bridge and transmits BPDUs accordingly. Upon receipt of a BPDU from a neighboring device, its contents are examined and compared with similar information (e.g., assumed root and lowest root path cost) stored by the receiving bridge in memory. If the information from the received BPDU is "better" than the stored information, the bridge adopts the better information and uses it in the BPDUs that it sends (adding the cost associated with the receiving port to the root path cost) from its ports, other than the port on which the "better" information was received. Although BPDUs are not forwarded by bridges, the identifier of the Root Bridge is eventually propagated to and adopted by all bridges as described above, allowing them to select their Root Port and any Designated Port(s).
In order to adapt the active topology to changes and failures, the Root Bridge periodically (e.g., every hello time) transmits BPDUs. In response to receiving BPDUs on their Root Ports, bridges transmit their own BPDUs from their Designated Ports, if any. Thus, BPDUs are periodically propagated throughout the bridged network, confirming the active topology. As BPDU information is updated and/or timed-out and the active topology is re-calculated, ports may transition from the blocking state to the forwarding state and vice versa. That is, as a result of new BPDU information, a previously blocked port may learn that it should be in the forwarding state (e.g., it is now the Root Port or a Designated Port).
Rapid Spanning Tree Protocol
Recently, the IEEE issued a new version of the 802.1D standard, known as IEEE Std. 802.1D-2004, that describes a rapid spanning tree protocol (RSTP) to be executed by otherwise 802.1D compatible devices. The RSTP similarly selects one bridge of a bridged network to be the root bridge and defines an active topology that provides complete connectivity among the LANs while severing any loops. Each individual port of each bridge is assigned a port role according to whether the port is to be part of the active topology. The port roles defined by the 802.1D-2004 standard include Root, Designated, Alternate and Backup. The bridge port offering the best, e.g., lowest cost, path to the root is assigned the Root Port Role. Each bridge port offering an alternative, e.g., higher cost, path to the root is assigned the Alternate Port Role. Each bridge port providing the lowest cost path from a given LAN is assigned the Designated Port Role, while all other ports coupled to the given LAN in loop-back fashion are assigned the Backup Port Role.
Those ports that have been assigned the Root Port and Designated Port Roles are placed in the forwarding state, while ports assigned the Alternate and Backup Roles are placed in a state. A port assigned the Root Port Role can be rapidly transitioned to the forwarding state provided that all of the ports assigned the Alternate Port Role are placed in the blocking state. Similarly, if a failure occurs on the port currently assigned the Root Port Role, a port assigned the Alternate Port Role can be reassigned to the Root Port Role and rapidly transitioned to the forwarding state, provided that the previous Root Port has been transitioned to the discarding or blocking state. A port assigned the Designated Port Role or a Backup Port that is to be reassigned to the Designated Port Role can be rapidly transitioned to the forwarding state, provided that the roles of the ports of the downstream bridge are consistent with this port being assigned the Designated Port Role. The RSTP provides an explicit handshake to be used by neighboring bridges to confirm that a new Designated Port can rapidly transition to the forwarding state.
Like the STP described in the 1998 version of the 802.1D specification standard, bridges running RSTP also exchange BPDUs in order to determine which roles to assign to the bridge's ports. The BPDUs are also utilized in the handshake employed to rapidly transition Designated Ports to the forwarding state.
Virtual Local Area Networks
A computer network may also be segmented into a series of logical networks. For example, U.S. Pat. No. 5,394,402, issued Feb. 28, 1995 to Ross (the "'402 Patent"), discloses an arrangement for associating any port of a switch with any particular network segment. Specifically, according to the '402 Patent, any number of physical ports of a particular switch may be associated with any number of groups within the switch by using a virtual local area network (VLAN) arrangement that virtually associates the port with a particular VLAN designation. More specifically, the switch or hub associates VLAN designations with its ports and further associates those VLAN designations with messages transmitted from any of the ports to which the VLAN designation has been assigned.
The VLAN designation for each port is stored in a memory portion of the switch such that every time a message is received on a given access port the VLAN designation for that port is associated with the message. Association is accomplished by a flow processing element which looks up the VLAN designation in the memory portion based on the particular access port at which the message was received. In many cases, it may be desirable to interconnect a plurality of these switches in order to extend the VLAN associations of ports in the network. Those entities having the same VLAN designation function as if they are all part of the same LAN. VLAN-configured bridges are specifically configured to prevent message exchanges between parts of the network having different VLAN designations in order to preserve the boundaries of each VLAN. Nonetheless, intermediate network devices operating above L2, such as routers, can relay messages between different VLAN segments.
In addition to the '402 Patent, the IEEE promulgated the 802.1Q specification standard for Virtual Bridged Local Area Networks. To preserve VLAN associations of messages transported across trunks or links in VLAN-aware networks, both Ross and the IEEE Std. 802.1Q-2003 specification standard disclose appending a VLAN identifier (VID) field to the corresponding frames. In addition, U.S. Pat. No. 5,742,604 to Edsall et al. (the "'604 patent"), which is commonly owned with the present application, discloses an Interswitch Link (ISL) encapsulation mechanism for efficiently transporting packets or frames, including VLAN-modified frames, between switches while maintaining the VLAN association of the frames. In particular, an ISL link, which may utilize the Fast Ethernet standard, connects ISL interface circuitry disposed at each switch. The transmitting ISL circuitry encapsulates the frame being transported within an ISL header and ISL error detection information, while the ISL receiving circuitry strips off this information and recovers the original frame.
Multiple Spanning Tree Protocol
Within the IEEE Std. 802.1Q-2003, the IEEE also included a specification standard for a Spanning Tree Protocol that is specifically designed for use with networks that support VLANs. The Multiple Spanning Tree Protocol (MSTP), which is described in the IEEE 802.1s supplement to IEEE Std. 802.1Q-2003, organizes a bridged network into regions. Within each region, MSTP establishes an Internal Spanning Tree (IST) which provides connectivity to all bridges within the respective region and to the ISTs established within other regions. The IST established within each MSTP Region also provides connectivity to the one Common Spanning Tree (CST) established outside of the MSTP regions by IEEE Std. 802.1Q-1998 compatible bridges running STP or RSTP. The IST of a given MST Region receives and sends BPDUs to the CST. Accordingly, all bridges of the bridged network are connected by a single Common and Internal Spanning Tree (CIST). From the point of view of the legacy or IEEE Std. 802.1Q-1998 bridges, moreover, each MST Region appears as a single virtual bridge on the CST.
Within each MST Region, the MSTP compatible bridges establish a plurality of active topologies, each of which is called a Multiple Spanning Tree Instance (MSTI). The MSTP bridges also assign or map each VLAN to one and only one of the MSTIs. Because VLANs may be assigned to different MSTIs, frames associated with different VLANs can take different paths through an MSTP Region. The bridges may, but typically do not, compute a separate topology for every single VLAN, thereby conserving processor and memory resources. Each MSTI is basically a simple RSTP instance that exists only inside the respective Region, and the MSTIs do not interact outside of the Region.
MSTP, like the other spanning tree protocols, uses BPDUs to establish the ISTs and MSTIs as well as to define the boundaries of the different MSTP Regions. The bridges do not send separate BPDUs for each MSTI. Instead, every MSTP BPDU carries the information needed to compute the active topology for all of the MSTIs defined within the respective Region. Each MSTI, moreover, has a corresponding Identifier (ID) and the MSTI IDs are encoded into the bridge IDs. That is, each bridge has a unique ID, as described above, and this ID is made up of a fixed portion and a settable portion. With MSTP, the settable portion of a bridge's ID is further organized to include both a settable priority component and a system ID extension. The system ID extension corresponds to the CIST or one of the MSTI IDs. The MSTP compatible bridges within a given Region will thus have a different bridge ID for the CIST and each MSTI. For a given MSTI, the bridge having the lowest bridge ID for that instance is elected the root. Thus, an MSTP compatible bridge may be the root for one MSTI but not another within a given MSTP Region.
Each bridge running MSTP also has a single MST Configuration Identifier (ID) that consists of three attributes: an alphanumeric configuration name, a revision level and a VLAN mapping table that associates each of the potential 4096 VLANs to a corresponding MSTI. Each bridge, moreover loads its MST Configuration ID into the BPDUs sourced by the bridge. Because bridges only need to know whether or not they are in the same MST Region, they do not propagate the actual VLAN to MSTI tables in their BPDUs. Instead, the MST BPDUs carry only a digest of the VLAN to MSTI table or mappings. The digest is generated by applying the well-know MD-5 algorithm to the VLAN to MSTI table. When a bridge receives an MST BPDU, it extracts the MST Configuration ID contained therein, including the digest, and compares it to its own MST Configuration ID to determine whether it is in the same MST Region as the bridge that sent the MST BPDU. If the two MST Configuration IDs are the same, then the two bridges are in the same MST Region. If, however, the two MST Configuration IDs have at least one non-matching attribute, i.e., either different configuration names, different revision levels and/or different computed digests, then the bridge that received the BPDU concludes that it is in a different MST Region than the bridge that sourced the BPDU. A port of an MST bridge, moreover, is considered to be at the boundary of an MST Region if the Designated Bridge is in a different MST Region or if the port receives legacy BPDUs.
FIG. 1 is a highly schematic block diagram of an MST BPDU 100 in accordance with IEEE Std. 802.1Q-2003. The MST BPDU 100 includes a header 102 compatible with the Media Access Control (MAC) layer of the respective LAN standard, e.g., Ethernet. The header 102 comprises a destination address (DA) field, a source address (SA) field, a Destination Service Access Point (DSAP) field, and a Source Service Access Point (SSAP), among others. The DA field carries a unique bridge multicast destination address assigned to the spanning tree protocol, and the DSAP and SSAP fields carry standardized identifiers assigned to the spanning tree protocol. Appended to header 102 is a BPDU message area that includes an "outer" part 104 and an "inner" part 106. The outer part 104 has the same format as an RSTP BPDU message and is recognized as a valid RSTP BPDU message by bridges that do not implement MSTP. The "inner" part 106 is utilized by bridges executing MSTP to establish the IST and the MSTIs. The inner part 106 has a set of spanning tree parameters, e.g., spanning tree priority vectors, for the IST, and a set of parameters for each MSTI supported by the bridge sourcing the MSTP BPDU 100.
Outer part 104, also referred to as the CIST priority vector, has a plurality of fields, including a protocol identifier (ID) field 108, a protocol version ID field 110, a BPDU type field 112, a CIST flags field 114, a CIST root ID field 116, a CIST external path cost field 118, a CIST regional root ID field 120, a CIST port ID field 122, a message age field 124, a maximum (MAX) age field 126, a hello time field 128, and a forward delay field 130. The CIST root identifier field 116 contains the identifier of the bridge assumed to be the root of the Common and Internal Spanning Tree, which may be in the same MSTP Region as the bridge sourcing the BPDU message 100, in another MSTP Region or in part of the bridged network that is not running MSTP. The CIST external path cost field 118 contains a value representing the lowest cost from the bridge sourcing the BPDU 100 to the CIST root identified in field 116 without passing through any other bridge in the same region as the bridge that is sourcing the BPDU message 100.
Inner part 106, also referred to as an MSTI priority vector, similarly has a plurality of fields, including a version 1 length field 132, which is typically set to null, a version 3 length field 136, an MST configuration ID field 138, a CIST internal root path cost field 140, a CIST bridge ID field 144, and a CIST remaining hops field 150. Inner part 106 may further include one or more optional MSTI configuration messages 152, each of which constitutes another MSTI priority vector or M-record.
Because version 2 of the RSTP does not specify any additional fields beyond those already specified by version 1, the MST BPDU does not have a version 2 length field.
As mentioned above, the MST configuration ID field 138 is made up of three subfields: a configuration name sub-field 154, a revision level sub-field 156 and an MD-5 checksum sub-field 158. The configuration name sub-field 154 carries a variable length text string encoded within a fixed size, e.g., 32-octets. The revision level sub-field 156 carries an integer encoded within a fixed field of two octets. The MD-5 checksum sub-field 158 carries a 16-octet signature created by applying the MD-5 algorithm to the bridge's VLAN to MSTI table, which contains 4096 consecutive two octet elements.
Each MSTI Configuration Message 152 consists of a plurality of fields including a MSTI flags field 160, a MSTI regional root ID field 162, a MSTI internal root path cost field 164, a MSTI bridge priority field 166, a MSTI port priority field 168, and a MSTI remaining hops field 170. MST bridges utilize the STP parameters contained in fields 140-150 of inner part 106 and in each MSTI configuration message 152 to compute an active topology for each MSTI configured in the respective region.
Although the STP prevents the formation of loops within a bridged network, it can result in the creation of less than ideal paths. FIG. 2 is a highly schematic illustration of a bridged network 200. Network 200 includes six bridges 202a-f, each having a plurality of ports (not shown). The bridges 202a-f are interconnected by network segments 204, such as shared media or point-to-point links. Suppose that bridge 202a is elected the root of the network 200. Execution of the STP will cause bridge 202b to block one of its ports to prevent the formation of a loop in network 200. Suppose bridge 202b determines that its port coupled to bridge 202f is to be blocked as indicated by the "X" on FIG. 2. Execution of the STP thus prevented the formation of a loop in network 200. The path utilized by data messages going from bridge 202b to bridge 202f, however, is far from optimal. In particular, data messages received at bridge 202b, e.g., from a Local Area Network (LAN) connected thereto (not shown) that are to be delivered to bridge 202f are routed through bridges 202e, 202d, 202a and 202c. Given that bridges 202b and 202f are neighbors, this roundabout path is obviously not ideal. Indeed, such a situation results in delays and wasted bandwidth.

System and method for generating symmetrical spanning trees


A method and system for providing a twin well in a semiconductor device is described. The method and system include masking a first portion of the device such that a second portion of the device is exposed. A sacrificial layer has a first portion on the first portion of the device and a second portion on the second portion of the device. In one aspect, an oxidation stop layer may be below the sacrificial layer. The method and system include implanting a first well in the second portion of the device, exposing the first portion of the device after the first well is implanted, and oxidizing the second portion of sacrificial layer after the exposing. The method and system further include implanting the second well in the first portion of the device after the oxidizing and planarizing the device after the second well is implanted.

Certain semiconductor devices include twin wells. A twin well includes a P well and an adjacent N well. FIG. 1 depicts a conventional method 10 for providing a conventional twin well semiconductor device. The portion of the conventional twin well semiconductor device in which the P well is to be formed is masked, via step 12. Step 12 includes forming a pad oxide over the surface of the wafer for the conventional twin well semiconductor device. Step 12 also includes depositing a nitride layer on the pad oxide over the surface of the wafer and providing a photoresist mask covering regions which are not to be implanted during formation of an N-well. Step 12 further includes removing the exposed portion of the nitride layer in regions in which the N-well is to be implanted. Consequently, the pad oxide is exposed in the regions in which the N-well is to be implanted, while the remaining nitride covers regions in which the P-well is to be formed. The photoresist mask may also be removed in step 12. The N-well is provided, via step 14. Step 14 thus includes implanting with phosphorus, arsenic or another N-type dopant. The silicon nitride layer is sufficiently thick to prevent the N-type dopant from passing through the nitride in regions in which the P-well is to be formed. In addition, a photoresist mask, which is virtually congruent to the remaining nitride underneath, may optionally be retained as present in step 12 and used as mask in conjunction with the remaining nitride. Consequently, step 14 allows the N-well to be provided.
After implantation of the N well, a LOCOS oxide is grown typically using a high temperature oxidizing ambient, via step 16. Prior to growing the LOCOS oxide, remaining photoresist is removed. The remaining nitride precludes the LOCOS oxide from being grown underneath, in the regions in which the P-well is to be formed. The remaining nitride is then removed typically using a hot phosphoric etch bath, via step 18. A P well is implanted typically using boron or another P-type dopant, via step 20. Because of the presence of the LOCOS oxide, the P-type dopant does not penetrate the N-well. The LOCOS oxide is then removed and the P implant activated, via step 22.
FIG. 2 depicts a conventional twin well semiconductor device 50. For clarity, the conventional semiconductor device 50 is not drawn to scale. The semiconductor device 50 is fabricated using the conventional method 10. The conventional semiconductor device 50 includes an N-well 52 and a P-well 56. Because the conventional method 10 is used, the N-well 52 and the P-well 56 are adjacent.
Although the method 10 can provide the conventional semiconductor device 50, one of ordinary skill in the art will readily recognize that the conventional semiconductor device 50 has serious drawbacks. In particular, the surfaces of the N-well 52 and P-well 56 are not coplanar. A step 60 exists between the surfaces of the N-well 52 and P-well 56. The step 60 adversely affects subsequent processing. For example, the step 60 may elevate electric fields and are associated with failures and defects, such as dielectric failure of a gate oxide that passes over a step. The step 60 may also cause out-of-focus conditions, which degrades imaging and reduces control over the properties of the conventional semiconductor device 50. The step 60 may also reduce the current carrying capacity of conductors which pass over the step 60 and reduce the mobility of charge carriers (electrons and/or holes) passing in the vicinity of the step 60. In addition, the step 60 may reduce the process window for chemical mechanical polishing (CMP). Moreover, the presence of the step 60 can result in the formation of stringers or unwanted pockets of material adjacent to them. Thus, utility of the conventional semiconductor device 50 may be limited.
Accordingly, what is needed is a method and system for providing an improved twin well device. The present invention addresses such a need.

LOCOS self-aligned twin well with a co-planar silicon surface


A set of grounded and isolated duplex electrical receptacle assemblies includes interchangeable dual female bodies, interchangeable socket bases, interchangeable right, left and middle contact members, and interchangeable support bridges for assembling either a grounded or an isolated receptacle assembly. In the isolated assembly, an insulator plate is fitted between the support bridge and the middle contact member to electrically isolate one from another to thereby prevent electrical engagement therewith.

1. Field of the Invention
The present invention generally relates to electrical receptacles and, more particularly, is concerned with grounded and isolated electrical receptacle assemblies employing interchangeable receptacle body and base components and right, left and middle contact members as well as one-piece contact members.
2. Description of the Prior Art
Grounded and isolated (or non-grounded) duplex electrical receptacle assemblies heretofore manufactured and marketed by Hubbell Incorporated of Orange, Connecticut, the assignee of the subject application, are respectively illustrated in FIGS. 1 and 2. The grounded and isolated receptacle assemblies A, B employ a first group of components that are substantially the same and thereby interchangeable, and a second group of components that are not the same and thereby not interchangeable. The first group of components in each grounded and isolated assembly A, B includes a receptacle body C and right and left contact members D, E (also commonly referred to in the industry as "line" contacts). The second group of components includes a receptacle base F, a support bridge G, a pair of middle contact elements H (also commonly referred to in the industry as "center" contacts) and a ground tab I of the grounded receptacle assembly A, and a receptacle base J, insulator plate K, middle contact member L and support bridge M of the isolated receptacle assembly B. Neither the respective receptacle bases F, J nor the respective support bridges G, M of the grounded and isolated receptacle assemblies A, B are interchangeable with one another. This means that three interchangeable and eight non-interchangeable, or a total of eleven, components, must be manufactured, inventoried, handled and assembled to provide the grounded and isolated receptacle assemblies A, B.
Furthermore, referring to FIGS. 1-6, even though the right and left contact members D, E of one receptacle assembly A, B are interchangeable with the right and left contact members D, E of the other receptacle assembly A, B, the right and left contact members D, E are each made up of multiple parts which must be manufactured, inventoried, handled and assembled to provide the respective right and left contact members D, E. The same is true with respect to the non-interchangeable middle contacts. For example, the middle contact elements H and the ground tab I of the grounded receptacle assembly A which are mounted on the support bridge G require rivets N to attach them to the support bridge G, while the middle contact member L of the isolated receptacle assembly B includes contact elements O and rivets P to mount them on a binding plate R.
Consequently, a need exists for improvements in the design and construction of grounded and isolated electrical receptacle assemblies that will overcome the aforementioned drawbacks without introducing new drawbacks in their place.

Grounded and isolated electrical receptacle assemblies with interchangeable components


An electrically conductive hexagonal patch element for a patch antenna. The hexagonal patch element comprising a hexagonal shape with a first angle and a second angle opposite the first angle, a third angle and a fourth angle opposite the third angle, a fifth angle and a sixth angle opposite the fifth angle, the first, third, and fifth angles each measuring approximately 150 degrees and the second, forth, and sixth angles each measuring approximately 90 degrees, wherein the first angle is positioned in between the fourth angle and the sixth angle.

The present invention relates to a microstrip antenna and, more particularly but not exclusively, to a microstrip antenna having a hexagonal patch.
In its simplest form, a microstrip patch antenna consists of a radiating patch positioned on a dielectric substrate which overlays a ground plane. Microstrip patch antennas have been used widely as microwave circuit elements such as transmission lines, filters, resonators, and antennas. The rapid miniaturization of complex electronic circuits has vastly increased the demand for small size antennas. Hand-held computers, aerospace applications, mobile telephones, pagers and other portable wireless equipment now comprise microstrip antennas. The desirability of microstrip antennas results from their structure, particularly in view of their compactness, conformability, aerodynamic structure and general ease of fabrication.
A microstrip antenna which is used as an extension for a microstrip transmission line radiates primarily due to the fringing electromagnetic fields between the patch edge and the ground plane. It is known that providing an antenna patch which overlays a thick dielectric substrate having a low dielectric constant improves the antenna performance since this provides better efficiency, larger bandwidth and better radiation. However, such a configuration leads to a larger antenna size. In order to design a compact microstrip patch antenna, higher dielectric constants have to be used, limiting the antenna performance to a narrower bandwidth. Another method to improve the antenna performance is to introduce parasitic elements of varying size above and/or below the driven element. The addition of parasitic elements stacked above and/or below the driven element to increase the bandwidth is less desirable in some cases because of the physical structure that is required.
A known factor that influences the performance of an antenna is the structural design of the patch. The commonly known patches are generally made of a conducting material such as copper or gold, which can be structured to form different shapes. Known shapes for the radiating patch are square, rectangular, circular, triangular, and elliptical shapes. U.S. Pat. No. 6,664,926, issued on Dec. 16, 2003, discloses a compact planar antenna wherein a radiating element in the shape of a right triangle is formed on a substrate. A ground plane may be positioned on one or both sides of the substrate. In one embodiment, the radiating elements are positioned on the substrate in groups of two or more in close proximity to one another. In another embodiment, the radiating elements are arranged in an array.
Another example of a microstrip antenna is disclosed in U.S. Pat. No. 7,015,868, issued on Mar. 21, 2006. This patent discloses an antenna in which the corresponding radiative element contains at least one multilevel structure formed by a set of similar geometric patch elements (polygons or polyhedrons) electromagnetically coupled and grouped such that each of the basic component elements can be identified in the structure of the antenna. The design is such that it provides two important advantages: the antenna may operate simultaneously in several frequencies, and/or its size can be substantially reduced.
However, both patents and other known structures for patches of microstrip antenna do not provide optimum geometrical structures that allow transmission at a wide range of frequencies, while maintaining a high antenna gain level.
There is thus a widely recognized need for a compact microstrip antenna having a patch with an optimum geometrical structure which is easy to fabricate and is devoid of the above limitations.

Microstrip antenna having a hexagonal patch and a method of radiating electromagnetic energy over a wide predetermined frequency range


A novel and improved method and apparatus for providing an interface to a digital wireless telephone system compatible with standard analog wire line telephones and analog wire line fax machines is disclosed. During a telephone call, a fax detector monitors the incoming data for fax signals. If a fax is detected, the data processor switches from processing the data as if it were voice to processing it as fax. In addition, the remote station is sent a signal notifying it to process the data as fax rather than voice. The fax detector operates by detecting the preamble of a V.21 message, present at the beginning of every fax call. Energy is measured in both frequencies of the BFSK signals. A decision is made by analyzing these energies and locating a specific pattern which repeats itself a sufficient number of times.

I. Field of the Invention
The present invention relates to communications systems. More particularly, the present invention relates to a novel and improved method for automatically detecting a fax call and providing the correct service option based on that detection.
II. Description of the Related Art
Digital wireless telephone systems allow information to be exchanged more efficiently than analog wireless telephone systems. This increased efficiency allows a greater number of telephone calls or other communications to be conducted over digital wireless telephone systems using a given amount of radio frequency (RF) bandwidth. A prominent example of an analog wireless telephone system is the AMPS cellular telephone system employed extensively throughout the United States.
In some instances, the increased efficiency provided by digital wireless telephone systems is so substantial that digital wireless telephone service becomes economically competitive with the traditional analog wire line telephone service. Analog wire line telephone service is the telephone service provided using the conventional wire based telephone system, often referred to as the public switched telephone network (PSTN). Analog wireline telephone systems typically process data in analog format directly, or in a digital representation of the analog data referred to as pulse code modulated (PCM) format. Analog wire line telephone service has traditionally been far less expensive than wireless telephone service.
To provide a complete replacement for traditional analog wire line telephone service, wireless digital telephone systems must be able to accommodate all the services and functions that are currently supported by analog wire line telephone service. One such service is fax transmission.
Although digital wireless telephone systems typically do provide fax transmission service, the interface to the fax service is generally different than that of analog telephone systems. In particular, digital wireless telephone systems process the digital data directly, rather than in the form of tones, as practiced for analog communication systems.
Because of the different interface methods, some analog telecommunication equipment can not be used with the digital wireless telephone systems. In particular, fax machines designed for use with an analog telephone system typically cannot be used with a digital wireless telephone system. Therefore, a user converting from analog wire based telephone service to digital wireless telephone service will have to consider the capital investment made in such equipment when determining the cost benefit of switching to digital wireless telephone service.
Therefore, to reduce the cost of transitioning from wire based telephone service to a digital wireless telephone service, it is desirable to provide interface to a digital wireless telephone system that works with analog based wire line telecommunication equipment. In particular, it would be desirable to provide an interface to a digital wireless telephone system that works with standard telephones and fax machines.

Method and apparatus for detecting facsimile transmission


An impedance calibration circuit and a semiconductor device including the same are provided. An embodiment of the invention provides an impedance calibration circuit with a variable reference voltage generation unit. The impedance calibration circuit maximizes the number of semiconductor devices that can be tested in test equipment at one time and permits the operation of an impedance matching unit (e.g., an on-die-termination (ODT) circuit and/or an off-chip-driver (OCD)) to be tested for a variety of reference resistor values.

1. Field of the Invention
The present invention relates to semiconductor devices and, more particularly, but not by way of limitation, to an impedance calibration circuit having an adjustable reference voltage generation unit.
2. Description of Related Art
In recent years, operating frequencies of semiconductor devices are showing a tendency to increase. Also, alternating-current (AC) characteristics associated with input and output signals, such as a data signal, are very important to high-frequency semiconductor devices. The AC characteristics are affected by the characteristics of a channel that connects two or more devices rather than a semiconductor device or a controller for controlling the semiconductor device. Thus, it is essential that semiconductor devices should be designed to improve channel characteristics.
In order to improve the channel characteristics, impedance matching is typically performed in a channel using an on-die-termination (ODT) circuit and an off-chip-driver (OCD) circuit. Specifically, in order to improve the channel characteristics, in a semiconductor device, an output signal is output through a data input/output terminal after passing through an OCD circuit having an output impedance that is adjusted to a predetermined impedance, while an input signal is input through the data input/output terminal after passing through an ODT circuit having an input impedance that is adjusted to a predetermined impedance.
The semiconductor device includes an impedance calibration circuit, which calibrates the impedance of an ODT circuit or an OCD circuit using an external reference resistor, in order to further improve the channel characteristics. The reference resistor used for impedance calibration may have various resistances according to systems or other circumstances in which the semiconductor device is used. An impedance calibration circuit for the ODT circuit or the OCD circuit may calibrate impedance therein in proportion to a reference resistance. Each of the ODT circuit and the OCD circuit receives information on the calibrated impedance from the impedance calibration circuit and adjusts impedance therein. Also, the operation of the impedance calibration circuit and the operation of the ODT circuit or the OCD circuit are necessarily tested in testing the semiconductor device.
FIG. 1 is a block diagram of a conventional impedance calibration circuit.
Referring to FIG. 1, the conventional impedance calibration circuit includes an impedance calibration unit 10, a comparison unit 20, a reference voltage generation unit 30, and an impedance matching unit 40. The impedance calibration unit 10 includes a variable impedance circuit 11 and a control code generator 13. The reference voltage generation unit 30 includes resistors R10 and R20 that are connected in series between a power supply voltage Vdd and a ground voltage. The impedance matching unit 40 includes two variable impedance circuits 41 and 43. In FIG. 1, reference character ZQ refers to an additional terminal used for impedance calibration, RQ refers to a reference resistor, and DQ1 refers to a data input/output terminal.
Functions of the respective blocks shown in FIG. 1 will now be described.
The impedance calibration unit 10 calibrates the calibration impedance therein (i.e., the impedance of the variable impedance circuit 11) in response to a control signal "con" output from the comparison unit 20 and outputs an impedance control code "code". The variable impedance circuit 11, which is connected between the power supply voltage Vdd and the terminal ZQ, may include a MOS array and has an impedance value corresponding to the impedance control code "code". The control code generator 13 varies the impedance control code "code" in response to the control signal "con" and outputs the varied code to the variable impedance circuit 11. After the impedance calibration operation is finished, the control code generator 13 outputs the impedance control code "code" to the impedance matching unit 40. The comparison unit 20 compares a voltage VZQ at the terminal ZQ with a reference voltage Vref and outputs the control signal "con" based on the comparison result. The reference voltage generation unit 30 outputs a predetermined reference voltage Vref. The impedance matching unit 40, which may be an ODT circuit or an OCD circuit, adjusts input/output impedance (i.e., the impedance of the variable impedance circuits 41 and 43) in response to the impedance control code "code". That is, when the impedance matching unit 40 is an ODT circuit, the ODT circuit terminates a signal input to the data input/output terminal DQ1 as the input/output impedance. Also, when the impedance matching unit 40 is an OCD circuit, the output impedance of the OCD circuit is adjusted as the input/output impedance. The variable impedance circuits 41 and 43 of the impedance matching unit 40 function as a pull-up portion and a pull-down portion, respectively. Also, each of the variable impedance circuits 41 and 43 of the impedance matching unit 40 has the same configuration as the variable impedance circuit 11 of the impedance calibration unit 10 and has an impedance value corresponding to the impedance control code "code".
The operation of the conventional impedance calibration circuit shown in FIG. 1 will now be described.
In general, the resistors R10 and R20 of the reference voltage generation unit 30 have the same resistance. Thus, the reference voltage generation unit 30 outputs a reference voltage Vref having a half level of the power supply voltage Vdd. The comparison unit 20 compares the voltage VZQ at the terminal ZQ with the reference voltage Vref and outputs a control signal "con". When calibration impedance (i.e., the impedance of the variable impedance circuit 11 of the impedance calibration unit 10) is higher than the impedance of the reference resistor RQ, the voltage VZQ at the terminal ZQ becomes lower than the reference voltage Vref, so that the comparison unit 20 outputs a low-level control signal "con".
When the calibration impedance is lower than the impedance of the reference resistor RQ, the voltage VZQ at the terminal ZQ becomes higher than the reference voltage Vref, so that the comparison unit 20 outputs a high-level control signal "con". The control code generator 13 of the impedance calibration unit 10 varies the impedance control code "code" in response to the control signal "con" and outputs the varied code to the variable impedance circuit 11. That is, the control code generator 13 of the impedance calibration unit 10 decreases the impedance control code "code" in response to the low-level control signal "con", while the control code generator 13 of the impedance calibration unit 10 increases the impedance control code "code" in response to the high-level control signal "con".
As described above, the variable impedance circuit 11 has an impedance value corresponding to the impedance control code "code". Accordingly, when the low-level control signal "con" is input, the impedance control code "code" decreases, and thus the calibration impedance (i.e., the impedance of the variable impedance circuit 11) becomes low. Also, when the high-level control signal "con" is input, the impedance control code "code" increases, and thus the calibration impedance becomes high.
When the above-described operation is performed until the voltage VZQ at the terminal ZQ is equal to the reference voltage Vref, the calibration impedance becomes the same as the impedance of the reference resistor RQ. The control code generator 13 outputs the impedance control code "code" allowing the calibration impedance to be the same as the impedance of the reference resistor RQ to the impedance matching unit 40. For example, the control code generator 13 may initially output an impedance control code "code" with a small value, continuously vary impedance control codes "code", and output an impedance control code "code" with the greatest value among the continuously varied impedance control codes "code" to the impedance matching unit 40.
Each of the variable impedance circuits 41 and 43 of the impedance matching unit 40 has the same configuration as the variable impedance circuit 11 of the impedance calibration unit 10. Thus, when the same code as the impedance control code "code" input to the variable impedance circuit 11 is input to the variable impedance circuits 41 and 43, input/output impedance (i.e., the impedance of the variable impedance circuits 41 and 43) becomes the same as the calibration impedance (i.e., the impedance of the variable impedance circuit 11). The number of variable impedance circuits of the impedance matching unit 40 depends on the number of data input/output terminals DQ1.
However, in the conventional impedance calibration circuit shown in FIG. 1, there is no problem with the operation of the impedance calibration circuit, but there are some problems in testing a semiconductor device including the impedance calibration circuit.
Specifically, when testing a semiconductor device including the conventional impedance calibration circuit for reference resistors having different reference resistances, a plurality of reference resistors having different resistances should be installed at test equipment and a relay switch should be installed between the semiconductor device and each of the reference resistors. As a result, a large amount of testing space is required, and the number of semiconductor devices that can be tested at one time is reduced. In turn, it is difficult to mass-produce semiconductor devices at high efficiency. Consequently, even though semiconductor memory devices may use a reference resistance ranging from 120Ω to 360Ω, semiconductor memory devices are typically tested using a single reference resistance of 240Ω.

Impedance calibration circuit and semiconductor device including the same


A method for actively determining a steering stop angle for tires associated with a front axle of a work vehicle may generally include receiving an input associated with a tire parameter for the tires, monitoring a suspension travel distance of the front axle and monitoring an oscillation angle of the front axle. In addition, the method may include determining a maximum allowable steering angle for the tires based on both the suspension travel distance and the oscillation angle of the front axle, wherein the maximum allowable steering angle corresponds to a steering angle at which clearance is maintained between the tires and at least one hood-related component of the work vehicle when the tires are moved to the maximum steering angle.

Work vehicles, such as tractors and other agricultural vehicles, typically include a suspension system configured to damp vibrations caused by uneven field conditions. The suspension system often includes an axle configured to support one or more wheels on each of its ends and an axle carrier extending between the axle and a frame or chassis of the work vehicle. The axle carrier may generally be configured to rotate relative to the frame about a lateral axis to facilitate vertical movement of the axle. In addition, the axle may be configured to pivot about the axle carrier to enable the axle to oscillate about a substantially longitudinal axis. Moreover, the suspension system may also include actuating cylinders coupled to the axle that are configured to damp vertical and oscillatory movement of the axle, thereby enhancing ride quality, reducing operator fatigue and reducing wear on certain work vehicle components.
Certain work vehicles also include a steering assembly configured to rotate each wheel and, thus, each associated tire relative to the axle across a range of steering angles. To prevent contact and/or damage to the various components positioned adjacent to the tires (e.g., hood, engine, frame, etc.) while the tires are being rotated, conventional steering assemblies typically include mechanical stops that limit both the steering angle of the tires as well as the oscillatory movement of the axle. As a result, the steering performance of work vehicles including such mechanical stops is often quite limited. Moreover, the mechanical stops must be manually adjusted by the operator to accommodate changes in the front-end configuration of the work vehicle (e.g., when larger tires are installed onto the vehicle and/or when the tire tread width of the vehicle is adjusted). Unfortunately, the manner in which the stops must be adjusted can be confusing, which leads to incorrect adjustments resulting in damage to adjacent vehicle components when the tires contact and/or rub against such components while the vehicle is being steered. In addition, the failure to properly adjust the positioning of the stops may also lead to inefficient vehicle operation.
Accordingly, an improved system and method for actively determining a steering stop angle for a work vehicle that allows for the steering performance of the vehicle to be optimized while preventing damage to adjacent vehicle components would be welcomed in the technology.

System and method for actively determining a steering stop angle for a work vehicle


A data communication method and apparatus is presented that allows communication in a distributed heterogeneous network. Communications managers reside in local processing environments and are responsible for interfacing local end users with the remainder of the heterogeneous network. Each communications manager receives distribution units from end users, the distribution units being assigned various priority levels and levels of assurance. Within each communications manager, an adjacent communications manager is determined in accordance with a communications path to a destination for the distribution unit. The distribution unit is then configured according to a network protocol stack existing between the communications manager and the adjacent communications manager, and the distribution units are transmitted according to priority. Each communications manager can have any number of adjacent communications managers each communicating through different network protocol stacks. Also described is load distribution among a complex of processors that share common functions, as well as control of information flow between adjacent communications managers.

The invention relates to a method and apparatus for managing and facilitating communications in a distributed heterogeneous network.
Information system planners are faced with a wealth of new technology including powerful processes at every level of the system. Such processes include, for example, desktop systems, main frame systems, cooperative processing, graphical user interfaces, distributed data bases and so-called "open" operating systems, which are just a few of the technological advances that promise to propel computing even more fully into the daily activities of people in organizations. The proliferation of communication networks to connect these processes over the past several years has increased the potential for users of the information systems to share information.
Such computer networking resulted in gains in productivity and efficiency, and networked computer systems provide access to a vast information repository. Every major hardware and software vendor in the world has created networked platforms and applications. With such proliferation, connecting these disparate communication networks and operating platforms so that they can cooperate and interoperate to allow information in physically separate networks to be integrated seamlessly has been a problem.
Corporations are moving rapidly toward implementing large scale strategic computing systems that integrate all components of an enterprise. These complex computer systems will be based on networks capable of supporting large numbers of personal computers, file servers, and multiple links to disparate main frame systems. Data and processing will be distributed throughout the network in cooperative processing applications. In addition, such distributive cooperative processing will allow enterprises to keep pace with rapid technological change while protecting past investment in information structure. Enterprise connectivity, transparent seamless data transfer, and increased transaction processing are just some of the growing requirements facing modern enterprises.
In conjunction with the increased demand for distributed environments, there has been an increase in on-line transaction processing. With the advent of high performance hardware and improved operating systems, on-line, mission critical applications are being developed and implemented outside of the main frame environment. It has been projected by the Vertical Systems Group that local area network originated messages across Wide Area Network Systems will increase in size 690% (21K to 145K) by 1994 with a corresponding 30% reduction in transport time (1.5 seconds to 1.05 seconds).
In addition to these factors, there is an increasing requirement for interoperability among various vendor hardware platforms and across unlike networks. The desire for vendor independence without the associated costs (both in development and productivity), is driving the support of open systems and common communication interfaces.
In a traditional environment, applications are forced to perform the activities that are not only germane to the business needs, but also to the communications network needs. If an application were viewed as a column with the user interface at the top of the column, the interface development at the bottom of the column becomes a customization process specific to the communications network environment. This customization inhibits the movement of the application to other environments, and it limits change to the communications network or operating environment without impact to the application. Typically, this impact is two-fold, first the cost of the application rewrite, and second, the cost of supporting two applications performing the same tasks during cut-over. For a single platform change in a reasonably-sized environment, hundreds of applications may be affected, significantly impacting development and computing resources.
In order to avoid such customization of application, it would be desirable to have a standard communications network interface independent of the different types of communications networks used in the system.

Method and apparatus for managing and facilitating communications in a distributed hetergeneous network


Apparatus comprising a thin film transistor having passivation layer disposed adjacent to a second surface of said channel layer, wherein said passivation layer comprises one or more wide-bandgap dielectric materials.

Electronic devices, such as integrated circuits, solar cells, and/or electronic displays, for example, may be comprised of one or more electrical components, such as one or more thin film transistors. Thin film transistors may be formed from one or more layers, which may be stacked, for example. In at least one type of electronic device, multiple thin film transistors may be coupled to form circuitry, such as a circuitry comprising a plurality of thin film transistors. When forming circuitry such as this, varying techniques may be utilized to isolate, separate and/or insulate one or more transistors and/or layers from one another, for example. Although particular techniques may vary, one or more techniques may have particular disadvantages. For example, such techniques may be time-consuming and/or expensive, may not allow for the use of particular materials, and/or may not produce the desired results.

Thin film transistor with a passivation layer

Hewlett-Packard Development Company, L.P.


A magazine supporting multiple bone grafts in chambers is coupled to a housing including a barrel. A plunger selectively passes through one of the chambers and along the barrel. A trigger mechanism advances the plunger along the barrel. A selector knob is movable into a plurality of positions, wherein each position employs one of a plurality of stops. One stop prevents the end of plunger from advancing past a predetermined ready position short of the end of the barrel when selected. Another stop prevents the plunger from advancing past a predetermined dispensing position substantially aligned with the end of the barrel when selected. Another stop prevents the plunger from advancing past a predetermined manipulating position beyond the end of the barrel when selected. In the manipulating position, the distal end of the plunger can be used to reposition the bone graft within the spinal disc cavity. Related methods are also provided.

This section provides background information related to the present disclosure which is not necessarily prior art.
The human musculoskeletal system is composed of a variety of tissues including bone, ligaments, cartilage, muscle, and tendons. Tissue damage or deformity stemming from trauma, pathological degeneration, or congenital conditions often necessitates surgical intervention to restore function. Surgical intervention can include any surgical procedure that can restore function to the damaged tissue or correct the deformity, which can require the use of one or more implants such as bone grafts.
In one example, in order to restore function to or correct a deformity of the spinal column, posterior lumbar interbody fusion (PLIF) surgery can be performed through the posterior part of the spine. This technique can also be used through other lumbar approaches, such as anterior, posterolateral, as well as through various approaches in the thoracic and cervical spinal regions. During such surgery, hardware such as pedicle screws and rods can be attached to the back of the vertebra to stabilize the spine and to enhance the fusion rate. One or more intervertebral implants or spacers can also be used to further stabilize the spine. Bone grafts are inserted into the disc space from one side of the spine. Delivering and positioning the bone grafts into and within the disc space can be problematic.


The inventive method for optically measuring a sample consists in temporarily repeatedly transmitting an electromagnetic signal (2) to the sample in such a way that a substance contained in the sample is transferred from a first electronic state (1) into a second electronic state (3), wherein at least one part of said substance in the second state (3) emits photons which are used for carrying out the optical measurement of the sample, the signal (2) is transmitted to the same sample area at a certain repetition interval and said repetition interval of the signal (2) is adjusted with a lifetime of the second state (3) of the substance having an order of magnitude of 1 ns on a value of at least 0.1 μs which is optimized with respect to photon yield from the substance.

A method of optically measuring a sample which is called STED microscopy is known from U.S. Pat. No. 7,253,893 B2. To the end of fluorescence microscopically examining a sample, a fluorescent dye or fluorophore in the sample is first transferred into an excited energetic state by means of excitation light. In this optical excitation, the usual limit for spatial resolution in optical methods of λ/2n applies, λ being the wavelength of the light used and n being the diffraction index of the sample. To get below this limit, the optically excited state of the fluorophore is de-excited with de-excitation light except of a desired measuring point in which the intensity distribution of the de-excitation light has a zero point; i.e. the fluorophore is forced to stimulated emission everywhere outside the actual measuring point by means of the de-excitation light. The dimensions of the resulting fluorescent measuring point, i.e. the spatial resolution of the remaining fluorescence, can significantly be lowered below the usual optical resolution limit in that the de-excitation light is applied to the sample outside of the desired measuring point at such a high intensity that saturation is achieved in de-excitation by means of stimulated emission. Thus, the fluorophore in the sample remains in its fluorescent state in a very narrowly delimited area about the zero point of the intensity distribution of the de-excitation light only. To cope with a limited average intensity of the de-excitation light, the de-excitation light and also the excitation light are pulsed. A further reason for using pulsed light in STED microscopy is to avoid that the intensive de-excitation light stresses the sample, even if the dye is not excited. Regarding a same area of the sample, irradiation with both the excitation and the de-excitation light is repeated multiple times at a short repetition interval which is sufficiently above the half-life of the fluorescent state of the fluorophore of typically 1 ns and has an order of magnitude of 10 ns to have a measurement signal sufficiently standing out of the background noise even with only few fluorophore molecules within a measuring point. Pulses of the excitation light and of the de-excitation light incident in the same areas of the sample comprise a typical repetition rate of 80 MHz.
With a high intensity of the de-excitation light which is necessary for saturation of the de-excitation outside the actual measuring point, there is a considerable probability that the dye in the sample bleaches, i.e. that it is chemically changed in such a way that it does no longer emit fluorescence light. Thus, the lifetime of the dye, i.e. the number of times at which fluorescence light from it may be registered from the fluorophore, is considerably reduced. This delimits the yield of fluorescence light from an actual sample in which naturally only a limited number of fluorophore molecules is available.
Similar problems with regard to the yield of photons in optically measuring a sample also occur with other fluorescence microscopic methods working with pulsed light, i.e. if high light intensities are employed, such as in multi-photon excitation, and also in other methods of optically measuring a sample, like for example in the lifetime measurement of fluorophores (life-time-imaging).
To enhance the yield of registered photons in methods of optically measuring a sample, high efforts have been spent to enhance the responsiveness of detectors to incident photons by which the photons from a sample are registered. An increase in responsiveness of high value detectors from about 20% up to 40 to 60% has been achieved within the previous 10 to 15 years. The associated increase of the yield of registered photons by a maximum factor of 3 was, however, accompanied by an extreme increase in cost of these detectors.
Despite the improvements with regard to the responsiveness of the detectors used, it is still the limited total yield of photons emitted by the fluorophore which sets the limits to most fluorescence-based measuring methods. In fluorescence microscopy, the limited number of photons emitted by a fluorophore in total, i.e. up to bleaching, nearly always is the main problem. Each considerable increase in the absolute signal by means of increasing the number of fluorescence light emissions prior to bleaching is of general importance for fluorescence microscopy.
A further method of optically measuring a sample which is called confocal two-photon microscopy is known from U.S. Pat. 2002/0027202 A1. In two-photon microscopy a quadratic dependency of the transition probability on the intensity distribution of the excitation light, which the fluorophore displays with regard to a transition out of its ground state into its excited fluorescent state upon taking up energy of two photons, is used for resolution enhancement. The excitation light is concentrated to pulses of high intensity to obtain an as high as possible yield of fluorescent light here. Due to the quadratic dependency of the transition probability of the fluorescence dye on the intensity of the excitation light, these pulses of high intensity result in more fluorescence light with a same average power of the excitation light as compared to a higher number of pulses of lower intensity. U.S. Pat. 2002/0027202 A1 additionally considers a negative effect on the fluorescence light yield which may result from a saturation of the excitation of the fluorescent state during each single pulse, and proposes to adjust the intensity of the pulses by means of keeping their repetition rate at a constant power of the excitation light so high that the negative influence on the fluorescence light yield does just not yet occur. The danger of bleaching of the fluorescence dye is not considered. As principally possible with regard to the repetition rate of the excitation light pulses U.S. Pat. 2002/0027202 A1 indicates a range of kHz to GHz, the repetition rate being to be adapted to the lifetime of the fluorescence dye; no numerical example, however, being given for this adaptation.
From EP 0666 473 B1 it is known to achieve a comparatively high yield of fluorescence light in two-photon microscopy despite the use of excitation light of comparatively low power in that very special fluorescence dyes, like for example lanthanide chelates, which have a long average lifetime of at least 0.1 μs (1×10−7 s), are subjected to comparatively long pulses of excitation light adapted to these lifetimes. The repetition rate of these long pulses is lower than 10 MHz (1×107 Hz) which corresponds to the indicated lifetime in the usual way.
The lifetime of the fluorescent state of fluorescence dyes usually used in fluorescence microscopy, however, is in the order of magnitude of 1 ns, i.e. shorter than 10 ns.
There is the need of a method of optically measuring a sample by which a considerable increase in the yield of registered photons can be achieved without a further expensive increase of the responsiveness of the detectors used.

Method and device for optically measuring a sample

Max-Planck-Gesellschaft zur Förderung der Wissenschaften e.V.


A test device for testing for the presence of voltage on an electrical power cable has a manually graspable handle and a probe mounted on the handle for projecting forwardly for engaging the power cable. The housing contains an electronic detection circuit responsive to signals from the probe for detecting presence of voltage on the cable and an indicator light for providing a warning indication in response to the detection of a voltage. The probe has a v-shaped mouth for surrounding the cable and a central rod for engaging into the cable. The mouth is retracted by pressure to expose the rod. The rod engages between the exposed neutral wires of one type of cable or into a punched hole in a cable of the type having a jacket.

Electrical utility service distribution and the increasing use of underground cables provides a convenience, safety factor, and cost saving to the public and electrical utility companies. Disrupted service and scheduled maintenance requires the investigation, diagnosis and repair of the cables plus their associated connection points, such as sub stations, distribution centers and pad mounted transformers.
For any maintenance work to be conducted on underground cables, requires some method of indication to the service personnel as to whether the cable has any electrical potential on it. That is, whether the cable in question is "live or dead". Existing instruments are difficult to use and often the indication is inconclusive. The final step prior to cutting a primary cable, is to spike it. This requires a spiking tool that is to be used only after the cable is proven "dead" and grounded at both ends.


The present invention relates to a method, system, and non-transitory computer-readable recording medium for calculating a motion trajectory of a subject. According to one aspect of the invention, there is provided a method for calculating a motion trajectory of a subject, the method comprising the steps of: acquiring at least three images of a subject using one imaging module; and calculating a motion trajectory of the subject with reference to the at least three acquired images, on the basis of each of at least three positions determined by a projection from a viewpoint of the imaging module to the subject on a background, and at least three virtual lines passing through a position where the imaging module is disposed.

Virtual golf systems are widely spreading which allow golfers to virtually play golf at low cost in downtown areas and the like. The basic concept of such virtual golf systems is to acquire a plurality of images in which a golf ball is photographed after the golf ball is hit by a golfer, measure physical quantities of the golf ball on the basis of a trajectory, interval, size, and the like thereof, perform a simulation of movement of the golf ball, and show a result of the simulation on a display.
Conventionally, in order to identify the above physical quantities of the golf ball (particularly, the direction or speed of the movement of the golf ball), a technique has been employed which causes a plurality of synchronized cameras to simultaneously photograph the golf ball, and uses information on the absolute or relative positions of the photographed golf ball images or the sizes of the golf ball images.
However, according to the above conventional technique, it is possible to accurately identify the physical quantities of the golf ball only when the plurality of cameras are perfectly synchronized. In practice, synchronization failure has frequently occurred due to a variety of variables such as communication delays, and a problem of cost increase has been caused depending on the number of cameras since two or more cameras are inevitably required. Further, although some conventional techniques using only one camera have been introduced, they have a problem of causing large measurement errors in physical quantities of a golf ball.
In this connection, the inventor(s) present herein a novel and inventive technique for easily and accurately calculating a motion trajectory of a golf ball using only one camera.

Method, system and non-transitory computer-readable recording medium for calculating a motion locus of a subject


The present invention relates to an airbag apparatus for a vehicle. In order to attain the purpose, the airbag apparatus for a vehicle according to the present invention comprises: a mounting board positioned in front of a rider; and an airbag module which is installed on the mounting board and, when a vehicle collides, restrains and protects the rider by means of inflating and expanding an airbag cushion toward the rider. Therefore, when the vehicle collides, the airbag cushion is inflated and expanded from the mounting board and thus the rider can safely be protected.

In general, an airbag apparatus for a vehicle is a safety device that protects the rider by rapidly inflating an airbag by injecting a gas into the airbag according to a signal of an impact detection sensor upon vehicle collision.
Such an airbag apparatus is installed in a steering wheel, a dashboard, a seat, a sidewall, etc. provided in a vehicle, and is inflated toward the front or side of a rider upon collision of a vehicle, and protects the rider.
That is, a vehicle may be provided with a frontal airbag expanded in front of a driver seat and a passenger seat, a curtain airbag and a side airbag expanded from the side of a rider to protect the rider, and a knee airbag to protect the rider's knees.
Recently, autonomous vehicles moving by themselves without drivers' driving are developing.
The autonomous vehicle detects states of respective devices provided in the vehicle and the surroundings of the vehicle by using a high-tech sensor for recognizing objects around the vehicle and a high-performance graphic processing device, and travels while controlling driving of the respective devices provided in the vehicle according to the result of the detection.
The high-tech sensor measures the distance between objects like a human, and detects danger and helps a driver view all areas without a blind spot. In addition, the graphic processing device recognizes a surrounding environment of the vehicle through various cameras, and analyzes the images and helps the vehicle drive safely.
For example, a LiDAR device, a sound wave device, a 3D camera, a radar device, and etc. may be mounted in the autonomous vehicle.
As the autonomous vehicles configured as described above do not require drivers to drive, all seats including a driver seat can freely rotate and an angle of a back of a seat can be adjusted to be horizontal by a tilting operation.
A rider can adjust the angle of the back of the seat variously, and may rotate the seat to have a meeting facing a rider on a back seat.
Accordingly, it is impossible to apply a normal airbag apparatus which is designed with reference to a posture of a rider sitting on a seat facing forward to the autonomous vehicles.
Patent Document 1 and Patent Document 2 presented below disclose a passenger protection system configuration for vehicles.


A circuit for refreshing memory cells of a dynamic memory contains a refresh control circuit for driving a memory cell array for accessing memory cells of the dynamic memory for a refresh process. Furthermore, a storage circuit is provided, which is assigned to at least one of the memory cells, for storing a time information item with regard to a last previous access to the assigned memory cell during the operation of the memory, a register bit being set in a manner dependent on the stored time information item and being able to be evaluated for controlling a refresh process. The refresh control circuit calls up the time information item stored in the storage circuit during operation of the memory and accesses the memory cell array in such a way that the memory cell assigned to the storage circuit is refreshed in a manner dependent on the time information item.

In integrated dynamic memories in the form of DRAMs, a so-called refresh operation is necessary in operating times in which memory cells are not accessed externally, in order to refresh the memory cell content, which can volatilize for example due to leakage currents of the storage capacitor or selection transistor, and thus to permanently retain said memory cell content. During the refresh operation, the assessed and amplified data signals from selected memory cells are written back directly to the relevant memory cells. This is generally controlled by a controller circuit, which additionally defines a refresh frequency with which a respective refresh of the memory cell content is effected.
There are a number of possibilities for refreshing the content of memory cells. Firstly, during a normal operation of the memory for carrying out read or write operations, as early as with the activation of a wordline of the memory and which the subsequent closing of the wordline, the information read from the relevant memory cells is assessed and amplified in sense amplifiers, the assessed and amplified information being written back to the memory cells and refreshed in this way (normal so-called activate-precharge cycle).
Furthermore, the memory controller sends so-called autorefresh commands to the memory, which in each case initiate a command sequence for activating a row due for refreshing. By way of example, a so-called refresh counter defines which of the rows is due for refreshing, the refresh counter successively addressing the rows of the dynamic memory for example in a sequential sequence of their addresses. Such a refresh process is often effected in parallel in all the memory banks of the memory in that a row is in each case activated and closed again simultaneously in each memory bank. If a memory bank has 4096 rows, for example, the memory controller that drives the memory sends an autorefresh command to the memory every 64 ms/4096 (the date retention time is 64 ms), for example.
For the purpose of data retention, the memory may enter a so-called self-refresh mode, in which a refresh counter periodically internally initiates a command sequence for activation and for closing of a row of the memory, similarly to an autorefresh command described previously. The data of memory cells can thus be refreshed regularly even without an external autorefresh command of a memory controller.
A memory controller which controls the accesses to the dynamic memory has the task, inter alia, of ensuring that none of the rows of the memory is in the non-activated state for longer than the maximum specified data retention time, for example 64 ms. In the simplest case, the memory controller intersperses an autorefresh command between the normal read and write operations on average every 15.6 μs (=64 ms/4096). The term used in this case is distributed refreshes, which can be implemented only when the memory is not in a read or write mode.
What is disadvantageous about this type of distributed refresh is, in particular, that it is not possible to define when a distributed refresh is to be effected, since the points in time depend on the access capacity utilization. A high access capacity utilization during read and write operations of the memory would on the other hand mean, however, that a multiplicity of rows are opened and closed again anyway during active operation, so that the information items are already refreshed during the customary read and write operations. In this case, the autorefresh commands are sent to the memory as a precaution in a regular sequence in a supporting manner, in which case a data stream interruption of normal read and write operations also occurs.

Circuit and method for refreshing memory cells of a dynamic memory


Systems and methods for booting a host device(s) from a peripheral device(s), via an interface, such as an MMC/SD interface, with power terminals, a data bus with data bus terminals, a clock line with a clock terminal and a command line with command terminal. Power is provided to the power terminals, and the command terminal of the MMC/SD or analogous interface is set during power-up to low. The data bus is monitored for a start bit of data transmission.

A short specification of the MMC-specification may be downloaded from the Internet site "http://www.mmca.org/compliance/buy_spec/MMCA_System_SummaryV41.pdf".
Boot definitions for existing embedded mass memory components having a different electrical interface are already known. These known components are e.g. NAND, OneNAND and MDOC mass memories. Common to all of these is that they are using some signal state (e.g. separate pin reserved for booting) during certain stage of power up to indicate to the memory component that it should fetch the first sector (typically 512 B) of data to the IO buffers. The technical data sheet of M-systems DiskOnChip (DOC) being cited as state of the art may be retrieved from the Internet at the address http://www.m-systems.com/NR/rdonlyres/85A96312-0130-47AD-A22C-CB533E28EE7A/0/DOC_G3—512Mb—1Gb_Rev20.pdf.
There are other known boot definitions for the other existing embedded mass memory components which has different electrical interface. These kinds of components are e.g. NAND (see: http://www.samsung.com/Products/Semiconductor/NANDFlash/index.htm), OneNAND (see: http://www.samsung.com/Products/Semiconductor/OneNAND/index.htm) and MDOC (see: http://www.m-systems.com/site/en-US/Products/DiskOnChip/DiskOnChip/) mass memories. Common to all of these is that they are using some signal state (e.g. separate pin reserved for booting) during certain stage of power up to indicate to the memory component that it should fetch the first sector (typically 512 B) of data to the IO buffers.
Present MMC- and SD-memory cards can provide capabilities of performing e.g. hot-swap operations, but it is also desirable to extend the capabilities of these memory cards to be able to provide a broader functionality.
To improve the usability of memory cards it would be desirable to enable a user to use memory cards as bootable media. This feature would enable a broader use of e.g. MMC (Multi-Media Card) and SD (Secure Digital) cards not only in self booting devices such as mobile cellular phones or cameras but also as a bootable storage medium for e.g. laptop and palmtop computers.
Presently, in the field of MMC-cards and SD-cards, the only way to access the first (sector) data during boot up of a host device is to follow the whole procedure of initializing the card, reading/writing the registers and performing a normal read access to known address.
The issue with existing MMC- and SD memory card interface protocols is that there is no efficient booting mechanism defined. The only way to access the first (sector) data during boot up of a host device is to follow the whole procedure of initializing the card, reading/writing the registers and performing a normal read access to known address. That means it is actually impossible to perform a boot procedure with a device not being configured to perform automatically a normal read access to a boot address (as e.g. the address of the boot data to be read is not known).
It is also desirable to achieve a broader usability without a necessity to change the electrical interface or the form factor, i.e. without using the signal state of an additional separate pin reserved for booting during certain stage of power up to indicate to the memory component that it should fetch a certain sector of data to the I/O buffers.
Therefore, a problem addressed by the invention involves extending the capabilities of existing MMC- and SD-cards without changing to many properties of the memory cards and to also be able to guarantee full down-compatibility.

Method for booting a host device from an MMC/SD device, a host device bootable from an MMC/SD device and an MMC/SD device method a host device may booted from


Systems, methods, and computer products that efficiently present large amounts of entity information with a graphical display that retains all or most of the relevant contextual information. More particularly, the preferred embodiment of the present invention enables efficient analysis of data with a graphical display that minimizes distortion of the text in the graphical display, that retains contextual information associated with data objects in the graphical display, and that positions the objects to optimally represent relational database associations.

1. Field of the Invention
The present invention is directed to the field of graphical displays of database information. It is more particularly directed to efficiently modifying the graphical display of a typically large number of data objects.
2. Description of the Background Art
A computer-implemented database is a collection of data, organized in the form of tables. A table typically consists of columns that represent data of the same nature, and records that represent specific instances of data associated with the table. A relational database is a database that may be a set of tables containing information that is manipulated in accordance with the relational model associated with the data. The product marketed under the trademarks IBM DB2 stores the data associated with the database in tables, and each table has a name.
On-Line Analytical Processing (OLAP) is a computing technique for summarizing, consolidating, viewing, analyzing, applying formulae to, and synthesizing data according to multiple dimensions. OLAP software enables users, such as analysts, managers, and executives, to gain insight into performance of an enterprise, such as a corporation, through rapid access to a wide variety of data dimensions that are organized to reflect the multidimensional nature of enterprise data, typically by means of hypotheses about possible trends in the data. More particularly, OLAP techniques may be used to analyze data from different viewpoints by identifying interesting associations in the information in a database. Therefore, OLAP is a decision support technique used in data management for the purpose of modeling and analyzing business information.
An increasingly popular data model for OLAP applications is the multidimensional database (MDDB). Often, data analysts use MDDBs during interactive exploration of business data for finding regions of anomalies in the data. Before this data can be explored, modeling needs to be enabled for the business. Modeling a business for an OLAP application may require typically large amounts of metadata including data entities.
In the past graphics tools have used objects, such as rectangle displays, to represent data entities, such as relational database tables and OLAP data. The objects are displayed so that they present the relationships between the data contained in the relational database tables and between the OLAP data. It is useful to represent these data entities with as much contextual information as possible to enhance the presentation of the data for use in data modeling and analysis. Given the large amount of OLAP data associated with databases, such as multidimensional databases and relational databases, there may be many objects in the graphical representation. Further, the objects may be manipulated by techniques such as enlarging, minimizing, and moving the objects within the graphical display during creation and manipulation of the business data model. Some of the problems caused by object manipulation during the analysis of the data entities in a graphical display are that representations of the objects may be obscured or difficult to read, and that the contextual reference of the objects may be lost.
For example, scrolling of the graphical display windows typically associated with the presentation of the objects allows other objects to be viewed but has the disadvantage of losing the contextual reference for some of the objects. That is, during scrolling some of the objects may not be visible to the user, thereby losing the contextual reference of those objects. Also, zooming out operations to enable viewing of more objects in the graphical display typically results in the indiscriminate reduction in the size of individual objects. This has the disadvantage that the text within the individual objects is typically rendered too small to read so that the user must repeatedly zoom in to see details of the objects and zoom out to view the contextual relationship of the objects.
Yet another example of the difficulty of managing the graphical display of a large number of data entities occurs when the user is allowed to move the objects thereby enabling flexibility in graphical display but having the disadvantage that the user must constantly reposition the objects as they are expanded and minimized. For example, when a large number of objects are moved, typically one or more of the moved objects obscures the display of other objects thereby reducing contextual information on the graphical display. This type of operation also may require the user to iteratively expand and minimize objects to maintain the information about the contextual relationship of the moved objects.
It would therefore be useful to be able to efficiently analyze typically large amounts of entity information with a graphical display that retains all or most of the relevant contextual information and minimizes distortion of the graphical display. More particularly, when employing OLAP processing techniques that manipulate objects it would be useful to be able to efficiently analyze multidimensional data with a graphical display that minimizes the disadvantages associated with current graphical displays. From the foregoing it will be apparent that there is still a need to improve the graphical display of a typically large number of objects to retain contextual information and minimize graphical display distortion thereby enhancing analysis of the objects and the associated data by techniques such as data mining of relational database information and OLAP data.

Modifying the graphical display of data entities and relational database structures

International Business Machines Corporation