HNF-4 (hepatocyte nuclear factor 4) is a protein enriched in liver extracts that binds to sites required for the transcription of the transthyretin (TTR) and apolipoprotein CIII (apoCIII) genes (Costa et al., 1989; Costa et al., 1990; Leff et al., 1989). We have purified HNF-4 protein (54 kD) and isolated a cDNA clone encoding the protein. HNF-4 is a member of the steroid hormone receptor superfamily with an unusual amino acid in the conserved “knuckle” of the first zinc finger (DGCKG). This and the fact that HNF-4 does not bind significantly to estrogen, thyroid hormone or glucocorticoid response elements indicate that HNF-4 may represent a new subfamily. HNF-4 binds to its recognition site as a dimer and activates transcription in a sequence-specific fashion in nonhepatic (HeLa) cells. HNF-4 mRNA is present in kidney and intestine as well as liver but is absent in other tissues. DNA binding data suggest that HNF-4 could be identical to liver factor A1 (LF-A1), a factor previously shown to regulate the transcription of the α-1 antitrypsin, apolipoprotein A1 and pyruvate kinase genes.

Cell type specificity is based on differential gene expression which is in turn determined, at least in part, by the particular set of transcription factors present and active in a given cell at a given time. Many such factors have been identified and characterized, particularly in the liver where there is a wide range of transcriptionally controlled genes (McKnight & Palmiter, 1979; Derman et al., 1981). Some transcription factors, such as AP-1 and Sp-1, seem to be present in all cells at all times but other factors have a more limited distribution. Whether there is a discernible logic that explains the distribution of the many factors has yet to be determined. Two aspects of this problem are particularly important. The first aspect is to determine whether the distribution of factors in different issues is controlled at the level of transcription. If so, then a cascade of transcriptional regulation that ultimately results in cell specificity is indicated. The second issue is whether any particular factor is central to the accomplishment of a particular metabolic or physiologic goal. Such a goal might be suggested by factors acting on an interrelated set of genes.
These issues have begun to be addressed by the dissection and analysis of the promoter/enhancer regions of genes expressed primarily in hepatocytes by the present applicants and others (Johnson, 1990). The DNA elements that confer cell specific expression have been defined by transient transfection into cultured cells (e.g., hepatoma vs. HeLa cells) and/or in vitro transcription assays, and the proteins that bind to these elements have been identified by DNA binding assays using crude liver nuclear extracts. In this way, at least four distinct protein factors that are abundant in liver have been found thus far: HNF1 (LF-B1) (Courtois et al., 1987; Monaci et al., 1988), C/EBP (Johnson et al., 1987), HNF-3 and HNF-4 (Costa et al., 1989). HNF1, a homeo domain protein (Frain et al., 1989; Baumhueter et al., 1990), C/EBP, the original leucine zipper protein (Landschulz et al., 1988), and most recently HNF-3A, a DNA binding protein that has no similarity to known transcription factor families (Lai et al., 1990) have all been purified and cloned so that distribution and regulation of each can be determined.
The following publications are cited in the body of the patent application. Each of the publications is incorporated herein by reference:
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This patent is subject to a terminal disclaimer.


A grinding machine includes a bed, structure for supporting a camshaft on the bed, a carriage displaceably mounted on the bed to permit movement relative to the camshaft in a radial direction of the camshaft, first and second grinding spindles respectively having a rough-grinding disc and a finish-grinding disc, a headstock having the first and second grinding spindles mounted therein and the first and second grinding spindles respectively having first and second spindle axes aligned to intersect each other at an angle. The second grinding spindle also has a third grinding which has a third diameter smaller than a first diameter of the rough-grinding disc, greater than a second diameter of the finish-grinding disc and equal to substantially twice a concavity radius and of a cam to be ground and a width narrower than a cam width. A method of grinding the cam includes first rough grinding the cam from an untreated configuration using the rough-grinding disc to an intermediate configuration using the rough-grinding disc, then rough grinding the cam to a modified intermediate configuration using the third grinding disc, wherein the modified intermediate configuration defines a concave side of the cam, by pivoting the headstock and advancing the third grinding disc against the cam in a longitudinal direction corresponding to the camshaft axis with the third grinding disc set at a depth substantially corresponding to a depth of the concavity, and finally finish grinding the cam by grinding the cam using the finish-grinding disc.

The invention relates to a method and an apparatus for grinding cams of a camshaft, which cams comprise concave sides.
A method for grinding cams is described in DE 41 37 924 C1. In this method, a cam is initially rough-ground in a first step from an untreated configuration to an intermediate configuration with a first, large grinding disc. Subsequently, in a plunge-cut grinding method, a modified intermediate configuration, corresponding to the concave sides, is produced by a second grinding disc of smaller diameter. The cam is then finish-ground with the same grinding disc and thereby brought to its final configuration. The use of a small grinding disc, which is wider than the cam, to produce the modified intermediate configuration means that optimum cooling cannot occur because the grinding disc is engaged in the whole three-dimensional region of the concave side and, hence, in the grinding zone.

Method and apparatus for grinding cams with concave sides


Long term weight loss can be achieved and maintained with a formulation of over-the-counter life-enhancing dietary supplements. One or more supplements stimulate the release of serotonin within the brain and one or more supplements stimulate the release of cholecystokinin into the bloodstream. The combined potentiating effect of these two mechanisms on satiety enables greater weight loss than that previously achieved by the individual mechanisms acting alone. A third weight loss mechanism can be achieved with the addition of phenylethylamine. Even more effective weight loss formulations can be achieved with the addition of a blue-green algae, such as aphanizomenon flos aqua, to provide a longer lasting weight loss mechanism.

Being overweight or obese puts one at serious risk for developing many obesity-related illnesses including heart attack, stroke, type II diabetes and hypertension. Gall bladder disease, breast cancer, prostate cancer, colon cancer, sleep apnea, osteoarthritis and respiratory problems also pose a greater risk for those who are obese.
There are numerous products available on the market, both over-the-counter ("OTC") and by prescription for controlling appetite and reducing body weight. A review of OTC products finds that many are based upon a predominance of empirical information. These OTC products typically contain caffeine, herbs of varying source and purity, and so-called fat blockers and carbohydrate blockers.
Weight control prescription formulations such as the amphetamine class can be dangerous and addictive. Newer advances of the serotonin reuptake variety and scientifically developed fat blockers are expensive and typically available only by prescription.
As detailed below, new compositions and formulations have been developed to provide a pair of weight loss mechanisms using proven weight loss technologies. This dual action approach to weight loss produces results beyond what an arithmetic summation of the individual technologies would produce. Little has been found in the literature about combining known mechanisms of weight loss, and nothing has been found using the formulations set forth below.


The present invention provides structures for an integrated antifuse that incorporates an integrated sensing transistor with an integrated heater. Two terminals connected to the upper plate allow the heating of the upper plate, accelerating the breakdown of the antifuse dielectric at a lower bias voltage. Part of the upper plate also serves as the gate of the integrated sensing transistor. The antifuse dielectric serves as the gate dielectric of the integrated transistor. The lower plate comprises a channel, a drain, and a source of a transistor. While intact, the integrated sensing transistor allows a passage of transistor current through the drain. When programmed, the antifuse dielectric, which is the gate of the integrated transistor, is subjected to a gate breakdown, shorting the gate to the channel and resulting in a decreased drain current. The integrated antifuse structure can also be wired in an array to provide a compact OTP memory array.

Electrical antifuses and fuses are used in the semiconductor industry to store non-erasable information. Once programmed, the programmed state of a fuse or an antifuse does not revert to the original state on its own; that is, the programmed state of the fuse or the antifuse is not reversible. For this reason, electrical fuses and antifuses are called One-Time-Programmable (OTP) memory elements. Thus, fuses and antifuses are conducive to the manufacture of a programmable read only memory (PROM). Programming or lack of programming constitutes one bit of stored information in a fuse or an antifuse. The difference between a fuse and an antifuse is the way the resistance of the memory element is changed during the programming process. A semiconductor fuse has a low initial resistance state that may be changed to a higher resistance state through programming, i.e., through electrical bias conditions applied to the fuse. In contrast, a semiconductor antifuse has a high initial resistance state that may be changed to a low resistance state through programming.
Various methods of implementing an antifuse in a semiconductor structure have been known in the prior art. In general, an antifuse includes one insulating layer sandwiched between two electrically conducting plates. In some cases, the insulating layer is a dielectric layer such as silicon dioxide or silicon nitride. In some other cases, the insulating layer comprises a stack of multiple layers including at least one silicon nitride layer and at least one silicon dioxide layer such as an oxide/nitride/oxide (ONO) stack. In a typical antifuse, the three components of the antifuse, i.e., the first electrically conducting plate, the insulating layer, and the second conducting plate, are built in a vertical stack. By supplying a large voltage difference across the two electrically conducting plates, a dielectric breakdown is induced and a current path between the two electrically conducting plates is formed, whereby the high resistance state of the antifuse changes to a low resistance state. Various materials may be used for each of the two electrically conducting plates. Improvements upon the basic structure are also known in the prior art. In one example, U.S. Pat. No. 6,853,049 utilizes a silicide for one electrically conducting plate and polysilicon for the other electrically conducting plate. In another example, U.S. Pat. No. 6,750,530 provides a mechanism for lowering the antifuse programming voltage by providing a resistive heating element adjacent to, but not in contact with the antifuse.
Incorporation of electrical antifuses or fuses into a semiconductor chip requires an external sensing circuitry located outside an array of OTP memory elements for detecting the status of each of the OTP memory elements, i.e., electrical antifuses or electrical fuses. Typically, such circuitry needs to supply a high enough voltage to differentiate the voltage output from each OTP memory element in an array. However, such a circuit design requires that the supplied voltage does not droop substantially across the array as well as requiring that the sense output voltage from each of the OTP memory elements does not droop significantly beyond the noise margin of the sense circuitry. In addition, typical external sensing circuitry requires transistors of substantial size to deliver a large current through the wiring of the array and to insure sufficient signal development during sensing operations.
Incorporating a sensing mechanism into the antifuse structure can reduce the current and noise margin requirements for the external sensing circuitry. However, adding sensing transistors to each antifuse element typically increases the size of the OTP memory element significantly as exemplified in U.S. Pat. No. 6,927,997 to Lee et al, wherein three transistors are required to constitute one antifuse memory element.
Therefore, an antifuse structure with a compact layout area and a built-in sensing mechanism is desired.
Furthermore, an antifuse structure with a wide built-in sense margin within such a built-in sensing mechanism is also desired.
Also, a general challenge in the incorporation of electrical antifuses into semiconductor chips is a relatively high voltage required to program the dielectric material within an electrical antifuse. This is especially important since semiconductor chips provide only a relatively low supply voltage in many applications such as communication and mobile computing. An electrical antifuse with a low programming voltage is therefore desired.

Transistor based antifuse with integrated heating element

International Business Machines Corporation


An inverter control circuit controls transistors based on comparison of a voltage command wave with a carrier wave, when a magnitude of a voltage vector is equal to or less than a peak value of the carrier wave. The voltage command wave is a wave, which is offset to a maximum value side from a reference potential of the carrier wave so that a maximum value of the voltage command wave equals a peak value of the carrier wave. The inverter control circuit makes an on-period of the transistor on a positive bus side longer than that of the transistor on a negative bus side by using the command voltage. The amount of electricity charged in a capacitor is reduced in comparison with a case in which the voltage command wave is used. Thus, thermal loss of a stator coil and a diode on the positive bus side is reduced.

A conventional driving apparatus for a three-phase alternating current (AC) synchronous motor has, as disclosed in JP 3223842 (U.S. Pat. No. 6,137,704 and U.S. Pat. No. 6,320,775) for example, an inverter circuit for outputting three-phase AC currents of the motor and an inverter control circuit for controlling the inverter circuit.
In the inverter circuit, three sets of paired transistors, which are connected in series in each phase, are connected in parallel one another between a positive bus line and a negative bus line. A diode is connected to each transistor in parallel and in reverse bias direction in the inverter circuit.
A direct current (DC) power source is connected between the neutral point of the stator coil and the negative bus line of the inverter circuit. A capacitor is connected between the positive bus line and the negative bus line of the inverter circuit.
The inverter control circuit is configured to drive the six transistors to perform switching operation, so that the three-phase AC currents are supplied to the motor based on a voltage difference between the positive bus line and the negative bus line.
When the transistor is turned on, a current flows from the DC power source to the stator coil so that the stator coil stores energy based on the current.
When the transistor is turned off, the stored energy is discharged as a current, which flows from the stator coil to the positive electrode of the capacitor through the diode provided and the positive bus line. Thus, by the switching operation of the six transistors, the three-phase currents are supplied to the stator coil and the capacitor is charged.
When the capacitor is charged with the current, which flows from the stator coil, thermal loss is generated in the stator coil.
As the charge to be stored in the capacitor by the switching operation of the transistors increases, the thermal loss of the stator coil increases. As a result, efficiency in driving the motor is degraded.

Driving apparatus for multi-phase AC synchronous motor


An apparatus for a lifelike, automated, heavy punching bag that can parry punches using robotic arms able to rotate to right and left, and sense and record the weight and accuracy of punches delivered to it. The boxing buddy system may be used by aspiring boxers and other martial artists to deliver punches to various strategic points of their opponent's anatomy.

The following includes information that may be useful in understanding the present invention(s). It is not an admission that any of the information provided herein is prior art, or material, to the presently described or claimed inventions, or that any publication or document that is specifically or implicitly referenced is prior art.
1. Field of the Invention
The present invention relates generally to the field of boxing training aids and more specifically relates to a boxing buddy system.
2. Description of the Related Art
Training devices are used by boxers and other practitioners of the various martial arts (MMA or mixed martial arts, kick-boxing, and so forth) where blows are delivered to an opponent by hand, fist, or feet. The training device frequently used is a heavy punching bag. Heavy bags may be suspended from above or free-standing with a weighted base; but either way, they present the training fighter not with an anatomically accurate "opponent" against whom to deliver blows, but only with a heavy cylinder. Considering this situation, it would be desirable to work out with a punching bag having characteristics of a real fighter including features to allow defensive actions. This would make a heavy-bag workout far more challenging, enjoyable, and effective in terms of developing accuracy in punches and kicks. A suitable solution is desirable.
Various attempts have been made to solve the above-mentioned problems such as those found in U.S. Pat. No. 7,909,749 to Richard Sheedy; U.S. Publication Number 2012/0053016 to Michael Williamson; and U.S. Pat. No. 5,803,877 to Thomas Franey. This art is representative of boxing training aids. None of the above inventions and patents, taken either singly or in combination, is seen to describe the invention as claimed.
Ideally, a boxing buddy system should provide a lifelike, automated, heavy punching bag that can parry punches with robotic arms, rotate to right and left, and sense and record the weight and accuracy of punches delivered to it for training aspiring boxers and other martial artists to deliver punches to various strategic points of their opponent's anatomy, while replicating the defensive moves of an actual human opponent; and, yet would operate reliably and be manufactured at a modest expense. Thus, a need exists for a reliable boxing buddy system to avoid the above-mentioned problems.


The invention relates to a parallel-serial converter for converting parallel data into serial data, in particular for or in a DDR semiconductor memory, having at least n input terminals at which n data signals are present in parallel, an output terminal for outputting a serial data signal, a controllable latch connected to the input terminals on the input side, a common storage node, which is connected to outputs of the latch and which holds a data signal of the controllable latch present last, a controllable bypass device, which has an input, which is coupled to the storage node on the output side and which has a control terminal, via which a predeterminable state present at the input of the bypass device can be switched onto the storage node. The invention furthermore relates to a semiconductor memory having such a parallel-serial converter and to a method for operating such a parallel-serial converter.

In modern computer and software applications there is increasingly a demand for ever larger volumes of data to be processed in an ever shorter time. Large scale integrated memories, such as DRAM memories for example, are used for storing the data. In order, then, to meet the aforementioned demand for an ever higher speed when processing data, it is necessary, in the case of such a semiconductor memory, for said data to be written to the memory and read out from said memory again appropriately rapidly.
As development advances in the field of integrated circuits, the operating frequency thereof rises, too, so that the data can be processed appropriately rapidly.
What is more, semiconductor memories also exist which are specially designed for high data rates. One representative of such a semiconductor memory is the so-called DDR-DRAM memory, where DDR stands for "double data rate". Whereas in conventional semiconductor memories write and read operations are performed only upon the rising edge or the falling edge of a clock signal, in DDR semiconductor memories data are read out from the semiconductor memory and written to the semiconductor memory again both upon the rising edge and upon the falling edge of the clock signal. A double data rate is thus realized.
In the case of these DDR-DRAM semiconductor memories, the double data rate present externally at the semiconductor memory is converted internally into a single data rate and written in parallel to the semiconductor memory. In the case of a read access, however, the data present in parallel internally in the semiconductor memory have to be converted into a serial data stream again. For this purpose, the semiconductor memory or the interface circuit thereof is equipped with a parallel-to-serial converter—referred to hereinafter just as parallel-serial converter for short. An integrated circuit with an interface circuit having such a parallel-serial converter is described in U.S. Pat. No. 6,317,372.
In the simplest case, a parallel-serial converter is designed as a controllable shift register. A parallel-serial converter has a number of cascade-connected flip-flops corresponding to the number of input terminals. Furthermore, a control signal generated by means of a multiplexer may be provided for controlling the shift register. The construction and the method of operation of such a parallel-serial converter designed as a controllable shift register are known in many instances and described for example in Kories, Schmidt-Walter, Taschenbuch der Elekrotechnik, [Pocketbook of electrical engineering], Wissenschaftlicher Verlag Harri Deutsch GmbH, 5th corrected edition, 2003.
FIG. 1 uses a simple block diagram to show a simplified illustration of a generally known parallel-serial converter. The parallel-serial converter has four input terminals 1–4 and a single output terminal 5. Furthermore, four controllable inverters 7–10 arranged in parallel with one another are provided, which can respectively be controlled by means of control signals RI0, FA0, RI1, FA1. Data D0–D3 are present in parallel at the respective input terminals 1–4 and are read into a respective inverter 7–10 successively by means of control signals RI0, FA0, RI1, FA1 and applied to the common storage node 11. Two further inverters 12, 13 are connected downstream of the storage node 11. Furthermore, a feedback inverter 14 is provided, which is connected back-to-back with respect to the inverter 12 and is intended to hold the last state of the inverter 12 and thus the last state at the storage node 11.
FIG. 2 shows a signal timing diagram illustrating the sequence of the clock signal CLK, the control signals RI0, FA0, RA1, FI1 and the serial data signal Dout at the output 5 of the known circuit arrangement from FIG. 1. By means of latching the data D0–D3, the parallel-serial converter serializes the data signals D0–D3 present in parallel on the input side. The last state, that is to say the state assigned to the data packet D3, is held after the process of reading out the data signals D0–D3 has ended, that is to say at the instant t3. The storage node 11 then has said last state even when a read access does not actually take place and, consequently, no data actually have to be converted in the parallel-serial converter. The state is then held until a renewed memory access takes place, that is to say at the instant t4 in the present example.
Distortions of the data read out may occur during the conversion of the data, as well as during the driving of the data via the read line. The parallel-serial converter is arranged in the read part of the data path as the last circuit part directly upstream of the output driver. A distortion caused in whatever manner would have a serious effect on the data transmission since said distortion is equally concomitantly transmitted via the output driver. The arrangement of the parallel-serial converter directly upstream of the output driver thus makes it indispensable for the signal shape provided on the output side to be distorted as little as possible by the parallel-serial converter since otherwise a high quality of the data transmitted via the read part of the data path to the microcontroller is no longer ensured.
Large distortions in the data to be transmitted and thus a reduced quality furthermore has the effect of greatly restricting the maximum operating frequency as a result since the temporal width of an individual data eye 6 to be transmitted is blurred to a greater or lesser extent in the case of such distortions. A defined transition from one data eye 6 to the next is then no longer discernible as such, or is discernible as such only with very great difficulty, by the microcontroller that processes the data read out, with the result that, overall, a read-out of serial data present in dedicated fashion is no longer ensured.
The abovementioned distortions are undesirable but can never be entirely avoided. Said distortions should nonetheless be kept as low as possible. In the case of known parallel-serial converters in accordance with FIG. 1, the feedback inverter 14 makes the principal contribution to the corruption of the serially transmitted data signals and thus to the aforementioned distortions. In order to be able to hold the last state, said feedback inverter 14 must be "exaggerated" as it were, that is to say it must be made smaller than the inverter 12. However, this inevitably leads to the distortions.
The abovementioned distortions are dependent in particular on process fluctuations, that is to say that the greater the process fluctuations in the production of the feedback inverter 14, the more distortions in the transmitted data signals are to be reckoned with. However, said process fluctuations will have a more and more serious effect primarily in the case of future memory technologies in which the trend is toward ever smaller feature sizes, so that ever greater distortions in the data to be transmitted are to be reckoned with in this case.
This is a state which, understandably, is to be avoided.


An aqueous polyurethane resin is obtained by allowing at least a polyol compound, an active hydrogen group-containing compound having anionic group, an active hydrogen group-containing acrylate compound and an alkoxysilyl group-containing polyamine compound to react with a polyisocyanate compound.

Polyurethane resins have conventionally been used as primers in various industrial fields.
For example, in the field of optical plastic lenses, when a hard-coat layer is formed on a surface of a lens substrate, polyurethane resin is used as a primer for improving adhesion between the surface of the lens substrate and the hard-coat layer.
In recent years, in the field of optical plastic lenses, a method for manufacturing a photochromic lens which colors outdoors to function as sunglasses and discolors indoors to function as a transparent glasses, by forming a photochromic coat layer on a surface of a lens substrate has been known, and it is studied that polyurethane resin is used as a primer in order to improve adhesion between the surface of the lens substrate and the photochromic coat layer.
It has been proposed, for example, to use a moisture-curing polyurethane resin as a primer between the surface of the lens substrate and the photochromic coat layer (see, for example, the following Patent Document 1).    Patent Document 1: International Publication No. WO 2004/078476 A1


The invention provides a method of operating a cache memory so that operation is optimized. Instead of fetching data immediately upon a cache miss, the present invention continues with subsequent cache accesses. Decoupled from cache access, cache misses are fetched to cache. During operation, for each request in a sequence of data requests, it is determined if the requested data can be found in cache memory. If the data is not found in the cache, the next request in the sequence is processed without first retrieving the data pending from the earlier request. A miss list is generated for each of the requests in the sequence of requests whose data is not found in the cache. The data that is associated with the requests in the miss list is obtained from DRAM and used to satisfy the requests. Some cache lines may have one or more pending hits to data associated with the cache line. Those requests are kept in a pending hits list and processed in order as required. There may also be pending misses kept in a pending misses list where the list contains one or more pending misses to data associated with the cache line. A flag or indicator is set for a cache line when there are misses associated with the cache line.

1. Field of the Invention
This invention relates to the field of information storage and retrieval, and, more specifically, to a technique for improving cache memory performance.
Portions of the disclosure of this patent document contain material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office file or records, but otherwise reserves all copyright rights whatsoever. ArtX, and all ArtX-based trademarks and logos are trademarks or registered trademarks of ArtX, Inc. in the United States and other countries.
2. Background Art
In a computer system there may be two types of memories, a large memory that is relatively slow, and a smaller memory called a xe2x80x9ccachexe2x80x9d memory that is relatively fast. Some portion of the larger memory is stored in the cache memory. When the computer system needs data, it first checks the cache to see if the data is already there (a cache xe2x80x9chitxe2x80x9d). If the data is there, the computer gets it quickly (because the cache is fast) and can move on to some other step. If the data is not already in the cache, (a cache xe2x80x9cmissxe2x80x9d), the computer retrieves the data from the large memory. This slows computer operation down. Prior art cache memory environments have a disadvantage of very slow operation when data is not in the cache memory. The disadvantages of prior art cache environments can be understood by reviewing computer operation, particularly with respect to the storage and display of graphical information.
Storing and Displaying Graphical Data
Computers are often used to display graphical information. In some instances, graphical data is xe2x80x9crenderedxe2x80x9d by executing instructions from an application that is drawing data to a display. A displayed image may be made up of a plurality of graphical objects. Examples of graphical objects include points, lines, polygons, and three dimensional solid objects.
If you looked closely at a television screen, computer display, magazine page, etc., you would see that an image is made up of hundreds or thousands of tiny dots, where each dot is a different color. These dots are known as picture elements, or xe2x80x9cpixelsxe2x80x9d for short when they are on a computer display and as dots when printed on a page. The color of each pixel is represented by a number value. To store an image in a computer memory, the number value of each pixel of the picture is stored. The number value represents the color and intensity of the pixel.
The accuracy with which a document can be reproduced is dependent on the xe2x80x9cresolutionxe2x80x9d of the pixels that make up the document. The resolution of a pixel is the size of the number value used to describe that pixel. The size of the number value is limited by the number of xe2x80x9cbitsxe2x80x9d in the memory available to describe each pixel (a bit is a binary number having a value of 1 or 0). The greater the number of bits available per pixel, the greater the resolution of the document. For example, when only one bit per pixel is available for storage, only two values are available for the pixel. If two bits are available, four levels of color or intensity are available. While greater resolution is desirable, it can lead to greater use of data storage. For example, if each pixel is represented by a 32-bit binary number, 320,000 bits of information would be required to represent a 100 X 100 pixel image. Such information is stored in what is referred to as a xe2x80x9cFrame Bufferxe2x80x9d (or xe2x80x9cG arrayxe2x80x9d).
Pixel Rendering and Texture Mapping
The process of converting graphics data and instructions into a display image is known as xe2x80x9cpixel rendering.xe2x80x9d During pixel rendering, color and other details can be applied to areas and surfaces of these objects using xe2x80x9ctexture mappingxe2x80x9d techniques. In texture mapping, a texture image (also referred to as a texture map, or simply as a texture) is mapped to an area or surface of a graphical object to produce a visually modified object with the added detail of the texture image. A texture image may contain, for example, an array of RGB (red, green, blue) color values, intensity values, or opacity values.
As an example of texture mapping, given a featureless graphical object in the form of a cube and a texture image defining a wood grain pattern,.the wood grain pattern of the texture image may be mapped onto one or more surfaces of the cube such that the cube appears to be made out of wood. Other examples of texture mapping include mapping of product logo texture images to computer-modeled products, or mapping of texture images containing vegetation and trees to a barren computer-modeled landscape. Textures mapped onto geometric surfaces may also be used to provide additional motion and spatial cues that surface shading alone might not be capable of providing. For example, a featureless sphere rotating about an axis appears static until an irregular texture image or pattern is mapped to its surface.
Texture mapping involves using a texture image having a function defined in texture space. Typically, the texture space is represented as a two dimensional space, with xe2x80x9cSxe2x80x9d and xe2x80x9cTxe2x80x9d indices defining orthogonal axes (e.g., horizontal and vertical). A texture image is represented in texture space as an array in S and T of discrete texture elements or values called xe2x80x9ctexels.xe2x80x9d The texture image is warped or mapped from the texture space into an image space having an array of picture elements called xe2x80x9cpixels.xe2x80x9d The pixels are associated with orthogonal axis coordinates xe2x80x9cXxe2x80x9d and xe2x80x9cYxe2x80x9d in the image space which define a viewing plane for display. Based on the particular mapping function, a correspondence is generated between pixels representing an object or primitive in the image space and texels representing a texture image in the texture space.
Typically, a two-dimensional texture or pattern image is mapped onto a two or three-dimensional surface. For a two-dimensional surface, X and Y coordinates may be sufficient for defining a mapping function between pixels forming the surface and texels forming the texture image. For a three-dimensional surface, a perspective coordinate or other depth cueing mechanism may be provided to indicate distance from the viewing plane defined by the X and Y axes. The perspective coordinate may then be applied to the mapping function. For example, as the perspective coordinate value for a surface region increases (i.e., the surface region is further from the viewing plane), the mapping of the texture image may be darkened and/or compressed (i.e., neighboring pixels in the surface region may span an increased number of texels in the texture image), or otherwise warped, relative to surface regions having a lower perspective coordinate value. Through the application of depth cueing, the viewer is provided with a sense of distance or depth when viewing the rendered pixels.
FIGS 1A-1C illustrate a mapping of a brick-pattern texture image in texture space to a triangle primitive (100) in image space. FIG. 1A illustrates triangle primitive 100 in image space prior to texture mapping. FIG. 1B illustrates the brick-pattern texture image in texture space. FIGS. 1C illustrates triangle primitive 100 in image space after texture mapping has completed.
In FIG. 1A, triangle primitive 100 is defined by vertices at X,Y coordinate pixel locations PA(XA,YA), PB(XB,YB) and PC(XC,YC), where X is the horizontal axis and Y is the vertical axis. Pixels defining the perimeter of triangle primitive 100 may be explicitly stored in memory, or, to reduce storage requirements for individual primitives, the perimeter pixels may be linearly interpolated from the vertices defined by pixel locations PA(XA,YA), PB(XB,YB) and PC(XC,YC). The interior of triangle primitive 100 is formed by those pixel locations that lie within the defined perimeter. The surface of triangle primitive 100 in this example comprises the union of the perimeter pixels (including the vertices) and the interior pixels.
In FIG. 1B, a brick pattern is stored as a texture image referenced by S and T coordinates. The brick pattern may be mapped to pixels in image space by accessing texels at integer S and T coordinates. In accordance with a particular mapping function, pixel vertices PA, PB and PC of the triangle primitive correspond to S and T coordinates (SA,TA), (SB,TB) and (SC,TC), respectively. The orientation of the mapped vertices indicates rotation and scaling of triangle primitive 100 with respect to the S and T texture space.
FIG. 1C shows triangle primitive 100 having pixel vertices with corresponding X,Y coordinates for the image space, as well as texture space S,T coordinates for extracting texel values. The pixel vertices are PA(XA,YA; SA,TA), PB(XB,YB; SB,TB) and PC(XC,YC; SC,TC). The brick pattern of the texture image of FIG. 1B appears within triangle primitive 100 at slightly reduced scale, and at an approximately forty-five degree rotational offset from the X-axis. Other texture images may be similarly texture mapped to surfaces in render operations.
As the pixels defining a surface are rendered, S and T coordinate values are generated for each pixel based on the mapping function. The generated S and T coordinate values are then used to obtain a texel value for each rendered pixel in the image space. However, the generated S and T coordinate values are generally fractional values (i.e., not integer values). Consequently, the generated S and T coordinate values often correspond to a location in the texture space that falls between the texels of the texture image array.
Several options exist for selecting a texture value, given real S and T coordinate values. One of the simplest options is to round the S and T coordinate values to the nearest integers, and then select the texel corresponding to the rounded integer coordinate values. A more accurate representation is produced by interpolating between the four nearest samples that surround the real (S,T) location. For example, a bilinear interpolation algorithm (i.e., bilinear filtering), or higher-order interpolation algorithm, may be used to interpolate texel values for fractional S and T coordinates. Bilinear interpolation is illustrated in FIG. 2.
In FIG. 2, a pixel PN is mapped to S and T coordinates (L+xcex1,M+xcex2). The four nearest texels in texture space are TXL(L,M), TXL(L+1,M), TXL(L,M+1) and TXL(L+1,M+1). To perform bilinear interpolation (or filtering), a linear interpolation is performed between the texel pairs [TXL(L,M), TXL(L+1,M)] and [TXL(L,M+1), TXL(L+1,M+1)] to determine intermediate pixel values PNxe2x80x2(L+xcex1,M) and PNxe2x80x3(L+xcex1,M+1), respectively. These linear interpolation functions are performed to implement equations (1) and (2) below.
Pxe2x80x2N(L+xcex1,M)=(1xe2x88x92xcex1)TXL(L,M)+xcex1TXL(L+1,M)xe2x80x83xe2x80x83(1)
Pxe2x80x3N(L+xcex1,M+1)=(1xe2x88x92xcex1)TXL(L,M+1)+xcex1TXL(L+1,M+1)xe2x80x83xe2x80x83(2)
A third linear interpolation operation is performed on intermediate pixel values Pxe2x80x2N(L+xcex1,M) and Pxe2x80x3N(L+xcex1,M+1) to obtain PN(L+xcex1,M+xcex2) in accordance with the following equation (3). The linear interpolation operations for the intermediate pixels may be performed along the opposite axis as well, or the linear interpolation operations may be combined to implement a form of equation (4) below.                                                                                P                  N                                                                  (                                                            L                      +                      α                                        ,                                          M                      +                      β                                                        )                                            =                              xe2x80x83                                                                                (                                          1                      -                      β                                        )                                                                                P                      N                      xe2x80x2                                                                                (                                                                        L                          +                          α                                                ,                        M                                            )                                                                      +                                                                                xe2x80x83                                                          β                                                  xe2x80x83                                                                                P                    N                    xe2x80x3                                                                          (                                                                  L                        +                        α                                            ,                                              M                        +                        1                                                              )                                                                                (        3        )                                                                                xe2x80x83                                                          =                                  xe2x80x83                                                                  [                                      1                    -                                                                  (                                                  α                          +                          β                                                )                                                                                TXL                                                                          (                                                      L                            ,                            M                                                    )                                                                                +                                                                                xe2x80x83                                                          [                                                                            α                                                                    (                                                  1                          -                          β                                                )                                                                                TXL                                                                    (                                                                              L                            +                            1                                                    ,                          M                                                )                                                                              +                                                                                xe2x80x83                                                          [                                                                            β                                                                    (                                                  1                          -                          α                                                )                                                                                TXL                                                                    (                                                  L                          ,                                                      M                            +                            1                                                                          )                                                                              +                                                                                xe2x80x83                                                          α                                                  xe2x80x83                                                β                                                  xe2x80x83                                                                  TXL                                                        (                                                                  L                        +                        1                                            ,                                              M                        +                        1                                                              )                                                                                (        4        )
The above equations (1)-(4) may be implemented in any equivalent form, or the equations may be approximated, to optimize the calculation apparatus for speed and/or complexity.
Using the texel selection processes described above, severe aliasing of the texture may occur if the surface being texture-mapped is far from the viewing plane. This aliasing is caused when the reduced pixel resolution provides insufficient sampling of texture images that have higher frequency components (e.g., fast transitioning color or intensity values). The interpolated (S,T) values may skip over large areas of the texture. A technique known as MIP-mapping is often performed to prevent aliasing by precomputing multiple, filtered copies of the texture at successively lower resolutions. For example, a texture image comprising a 256xc3x97256 texel array would be filtered and resampled to obtain further texel arrays (or maps) at 128xc3x97128, 64xc3x9764, 32xc3x9732, 16xc3x9716, 8xc3x978, 4xc3x974, and 2xc3x972 resolutions. The cost of storing the additional texel arrays is an increase of approximately thirty percent in memory size.
The particular size of the texel array that is used during pixel rendering is chosen based on a computer parameter known as the xe2x80x9clevel of detail.xe2x80x9d The level of detail represents the relative distance between the interpolated S and T values. Each texel array size represents an integer level of detail, and the computed level of detail values are real numbers. High quality texture mapping is obtained by performing bilinear interpolation in the texel array representing the integer level of detail immediately above and below the computed level of detail of each pixel. Next, a linear interpolation is performed between the integer levels of detail to obtain the texture value at the non-integer level of detail. This process is known as trilinear MIP-mapping.
Texture Map Storage
To facilitate texture mapping, a texture image may be stored in a dynamic random access memory (DRAM) device. The texel values of the texture image are accessed from the DRAM as needed to determine pixel values for a rendered image in the frame buffer. Unfortunately, DRAM devices are inefficient when performing data transfer operations (e.g., data reads) for individual data values. Peak efficiency is achieved when transferring multiple data values, especially data values that are in adjacent memory locations. For example, for a burst transfer of data in consecutive locations, a DRAM device may support a transfer rate of eight bytes per clock cycle. The same DRAM device may have a transfer rate of one byte per nine clock cycles for arbitrary single byte transfers. These performance characteristics are not well-suited to texture mapping.
In texture mapping operations, pixel values for a frame buffer are often determined in a particular scan order, such as by scanning in the direction of the X axis. However, texels associated with consecutive pixels are rarely in a predictable scan order with respect to texture space. For example, in the texture mapping process of FIGS 1A-1C, a scan along the X axis in image space results in a scan pattern in the texture space that includes multiple passes from the left edge (T axis) of the texture image towards the upper right of the texture image. FIG. 3 illustrates the scan direction in texture space for the texture mapping of FIGS. 1A-1C. As shown, each scan arrow represents texel accesses that frequently traverse, or xe2x80x9cskipxe2x80x9d, rows, including large skips between the ending of one scan arrow and the beginning of the next scan arrow based on the boundaries defined by the primitive in image space.
For a linearly configured DRAM, for example, because the texels in a texture image are not typically scanned in a linear path along the S axis, consecutive pixels will access texels that are widely dispersed across memory. For a 1024xc3x971024 texture image in which each texel is one byte wide, a traversal of one integer T coordinate may translate to a skip of 1024 bytes in DRAM. These memory skips are not easily predictable because the skips are dependent upon the size of the image, the width of a texel, the rotational angle between the S,T axes and the X,Y axes, etc. Texture mapping may also be nonlinear for irregular surfaces, further dispersing memory access operations.
FIG. 4 illustrates an example pixel scan line progressing through a portion of a texel array. The texel array shown encompasses the range [L, L+5] in the S direction and [M,M+4] in the T direction. The pixels that form the scan line comprise PN, PN+1, PN+2, PN+3, PN+4, PN+5 and PN+6. PN lies within the texel neighborhood formed by texels at (L,M+1), (L+1,M+1), (L,M+2) and (L+1,M+2). Pixel PN+1 has a texel neighborhood of texels at (L+1,M), (L+2,M), (L+1,M+1), and (L+2,M+1). Each of pixels PN+2, PN+3, PN+4, PN+5 and PN+6 have a similar texel neighborhood. These texels may be used to determine the nearest neighbor for approximating the desired texel value. Also, as described above, interpolation may be performed on the texel neighborhood of each pixel. Assuming a linear memory in S, and memory access of a texel neighborhood in the order of (top-left, top-right, bottom-left, bottom-right), the memory transfers for the texels associated with pixels PN, PN+1, PN+2, PN+3, PN+4, PN+5 and PN+6 may occur as shown in the following table (where the texture image size is W(width)xc3x97H(height), and the base address xe2x80x9cBxe2x80x9d of the texel array is at (L,M)):
Associated with each of the pixels above (PN-PN+6) is a skip in the DRAM texel access of approximately the width of the texture image which is caused by the two-dimensional nature of the texel neighborhood. Even larger skips are introduced when the scan pattern crosses multiple integer coordinates in T for consecutive pixels. The speed of the texture mapping process may be significantly reduced by the performance of DRAM data transfers with frequent address skips of this nature.
Prior Art Buffer Memory
Prior art texture mapping schemes attempt to overcome the limitations of DRAM data transfer characteristics by using a smaller, faster buffer memory to hold data between DRAM transfers. Buffering consists of loading a block of contiguous data into buffer memory for use by the processor performing the texel processing. A new block of data is loaded from DRAM into the buffer when it is needed.
FIG. 5 illustrates buffering applied to a texture image. In FIG. 5, texture image 500 has dimensions Wxc3x97H, and base address 502. An N-byte buffer is used to hold N-byte buffered block 501 of texture image data having starting address M. Buffered block 501 is loaded as a linear block of texture image data from memory, or as a multidimensional tile of contiguous texture image data.
Buffering apparatus are illustrated in FIG. 6. DRAM 600 is coupled to N-byte buffer 601 to receive address information 604, and to transfer read data block 603 into the buffer memory. The data transferred from DRAM 600 comprises DRAM locations M through M+N, where M is supplied as read address 604. The N-byte contiguous block of data in buffer 601 is available via bus 605 for texel processing component 602 to access the texture image data in buffer 601. The texture image data is used to produce output 606, such as rendered pixels for display. When the texture image data required by the texel processing component 602 is not located in buffer 601, a new contiguous buffered block of texture image data is retrieved from DRAM 600 and placed in buffer 601.
Rather than performing the transfer of data as a single block to the buffer, the data may be streamed through the buffer, for example, in a FIFO (first in, first out) arrangement. The streaming data has an accessibility lifetime in the buffer based on the time required to shift a data element through the buffer and out. This lifetime is directly related to the size of the buffer itself.
If the buffered block 501 is configured as a contiguous one-dimensional (or linear) block of data, the buffered data is strongly biased along the S axis direction. Therefore, for two-dimensional graphics applications such as texel processing, buffered block 501 in buffer 601 requires frequent transfers from DRAM 600 to track texels when scan patterns produced by a particular mapping have a strong T component that causes frequent skips. Any performance gain achieved by storing a contiguous memory block in buffer 601 is countered by the need to make frequent data transfers of different blocks from DRAM 600 to buffer 601. Due to the contiguous nature of a buffer, a buffer needs to be very large to encompass large skips within the buffer, particularly for large images.
In the prior art, U.S. Pat. No. 5,548,709, issued to Hannah et al. on Aug. 20, 1996, discloses a semiconductor chip, referred to as TRAM (texture random access memory), that integrates texture memory, interpolation and resampling logic on the same substrate. Textures are input to the chip and stored in a main memory. The interpolator produces an output texel by interpolating from the textures stored in memory.
The invention provides a method of operating a cache memory so that operation is optimized. Instead of fetching data immediately upon a cache miss, the present invention continues with subsequent cache accesses. Decoupled from cache access, cache misses are fetched to cache. During operation, for each request in a sequence of data requests, it is determined if the requested data can be found in cache memory. If the data is not found in the cache, the next request in the sequence is processed without first retrieving the data pending from the earlier request. A miss list is generated for each of the requests in the sequence of requests whose data is not found in the cache. The data that is associated with the requests in the miss list is obtained from DRAM and used to satisfy the requests. Some cache lines may have one or more pending hits to data associated with the cache line. Those requests are kept in a pending hits list and processed in order as required. There may also be pending misses kept in a pending misses list where the list contains one or more pending misses to data associated with the cache line. A flag or indicator is set for a cache line when there are misses associated with the cache line.

Method and apparatus for decoupled retrieval of cache miss data


A display panel includes multiple pixel units that are arranged regularly. A pixel circuit is connected with a scanning signal line and a data signal line. The pixel circuit receives a data voltage transmitted by the data signal line and outputs a corresponding current to a light emitting device under a control of the scanning signal line. When a first light emitting unit is in a black state, the data signal line provides a reference black state voltage to a pixel circuit of the first light emitting unit. The driving method of the display panel includes: providing, by the data signal line, a first black state voltage to a pixel circuit of a second light emitting unit when the first light emitting unit emits light and the second light emitting unit is in the black state. The first black state voltage is less than the reference black state voltage.

An Organic Light Emitting Diode (OLED) is an active light emitting display device, which has advantages including self-emission, a wide viewing angle, high contrast, low power consumption and a high response speed, etc. It has been widely applied in display products such as mobile phones, tablet computers and digital cameras, etc. Display of the OLED is driven by a current, and needs a pixel circuit to output a current to the OLED in order to drive the OLED to emit light.

Display panel, driving method thereof and display apparatus

Chengdu BOE Optoelectronics Technology Co., Ltd.


A lightguide module having a linear collimator produced from optically transparent material, a toroidal lens produced from optically transparent material, and a light source, wherein the toroidal lens is disposed between the linear collimator and the light source, at the exit of the linear collimator are found scattering elements, and wherein a light-emitting part of the light source is directed toward an entry surface of the toroidal lens and an exit surface of the toroidal lens is directed toward entry surfaces of the linear collimator. The light source may be a light-emitting diode and the toroidal lens may be a Fresnel type lens.

Signal lights contain various kinds of optical systems which collimate a light beam emitted by a light source and then distribute the light in a direction required by international regulations. Among the widely used collimation techniques is collimation by means of a parabolic reflector, collimation by means of a converging lens and collimation by means of a Fresnel type converging lens. Recently, in connection with the use of light-emitting diodes (LEDs), a rotational collimator has also been used for the collimation of light, in which the light beam is collimated by a central entry surface created by a converging lens and outermost entry surfaces working on the principle of total reflection of light. Rotational collimators are part of optical modules which contain, besides the mentioned collimator, also scattering elements necessary for the distribution of the collimated light beam in the directions required by international regulations. Rotational collimators are used in combination with light-emitting diodes, which have a broad radiation characteristic.
In order to achieve the required efficiency needed to achieve the luminous intensity values as required by international regulations, it is necessary for the body of the rotational collimator to have a greater thickness (much greater than 2-3 mm, which is the standard thickness for plastic moldings used in light engineering for automobiles). The greater thickness of the collimator consequently leads to a high price of the molding, a high price of the mold, and also manufacturing problems that are connected with the making of thick-wall plastic moldings. When it is necessary for production reasons to reduce the thickness of the molding, this is achieved by removing part of the collimation surface of the collimator, which necessarily leads to lower efficiency of the optical module.
For a use in signal lights, it is advisable for design and production reasons that the dimension of the collimator is substantially larger in one direction than in another direction perpendicular to it.


To provide an optical disc device 1, and similar, equipped with a new mechanism to reduce laser light noise due to optical feedback.

In optical devices which use laser diodes, a high frequency current is sometimes modulated on the laser diode driving current as a countermeasure for optical feedback; but in the prior art an optical signal processing device has been proposed which modulates a high frequency current so as to traverse across the threshold current of the laser diode, causing multiple longitudinal oscillation modes. In this optical signal processing device, by bringing the frequency of the high frequency modulation signals close to the laser resonance frequency (relaxation oscillation frequency), each of the spectral line widths Δλ of the multimode laser light is increased, and coherence is reduced. By means of such an optical signal processing device, noise arising from optical feedback from an optical system can be reduced, without taking into consideration the optical path lengths of the optical system and laser or the relation to the laser oscillation frequency (Patent Reference 1: Japanese Patent Laid-open No. S60-35344).

Abstract: In an optical disc device 1 in which a laser diode is driven by a high frequency modulation method, optical feedback is returned to the laser diode at a timing at which the phase of the injected carrier density is within one of the following ranges: (1) equal to or greater than the peak phase of the injected carrier density of the laser diode, and equal to or less than the peak phase of the injected carrier density of the laser diode plus 3π/8 (radians); or (2) equal to or greater than the peak phase of the injected carrier density of the laser diode plus 9π/8 (radians), and equal to or less than the peak phase of the injected carrier density of the laser diode plus 2π (radians).


In detecting a displacement of a cantilever (2) by a displacement detecting mechanism (5) and allowing a probe (1) and a sample (8) to approach each other by at least one of a coarse-movement mechanism (13) and a vertical direction fine-movement mechanism (11) at the same time, an excitation mechanism (4) excites the cantilever (2) with a first excitation condition and the probe (1) and the sample (8) are allowed to approach each other with a first stop condition, and then the cantilever (2) is excited with a second excitation condition different from the first excitation condition, a second stop condition is set, and the probe (1) and the sample (8) are allowed to approach each other by the at least one of the vertical direction fine-movement mechanism (11) and the coarse-movement mechanism (13) until the second stop condition is satisfied.

1. Technical Field
The present invention relates to an approach method for a probe and a sample in a scanning probe microscope for relatively scanning the probe and the sample to measure a shape and a physical property of a surface of the sample, process the surface of the sample, or move a substance on the surface of the sample by the probe while controlling a distance by detecting an interaction between a cantilever including the probe at its distal end and the surface of the sample in the atmosphere, a vacuum, or a solution.
2. Description of the Related Art
Referring to FIGS. 5 and 6, a configuration of a conventional scanning probe microscope is described (see JP 2007-33321 A).
FIG. 5 is a configuration diagram of the conventional scanning probe microscope. In the conventional scanning probe microscope, a sample 101 is placed on a distal end of a three-axis fine-movement mechanism 102 including a cylindrical piezoelectric element, the three-axis fine-movement mechanism being fixed on a coarse-movement mechanism 103 used for allowing the sample 101 and a probe 106b provided at a distal end of a cantilever 106a to be described below to approach each other. On the other hand, the cantilever 106a including the probe 106b at its distal end is placed immediately above the sample 101, the cantilever 106a including a piezoelectric element 105 for exciting the cantilever at its proximal portion. A displacement of the cantilever 106a is detected by a displacement detecting mechanism including a laser diode (LD) 104 and a photodetector (PD) 107. The displacement detecting mechanism generally employs a method called optical lever method to reflect a laser beam from the LD 104 on a back surface of the cantilever 106a and cause the reflected beam to enter a detection surface of the PD 107. When the cantilever is deflected, a laser spot on the detection surface of the PD 107 moves. The displacement of the cantilever 106a may be detected by the spot position on the detection surface at this time.
A case where an apparatus having the above-mentioned configuration is used for measurement by an oscillating mode atomic force microscope, which is one type of the scanning probe microscope, is described. An amplitude and a phase of the cantilever are measured by the displacement detecting mechanism while exciting the cantilever 106a in the vicinity of a first-order resonant frequency by the piezoelectric element 105, the sample 101 is allowed to approach the probe 106b by the coarse-movement mechanism 103, and thereafter the probe 106b and the sample 101 are allowed to further approach each other by the three-axis fine-movement mechanism 102. Then, a physical force such as an atomic force acts between the sample and the probe 106b. When the sample and the probe 106b further approach each other, the sample and the probe 106b intermittently contact each other in accordance with the oscillation of the cantilever 106a and a contact force acts between the sample and the probe 106b. The atomic force and the contact force change the amplitude and the phase or the resonant frequency of the cantilever 106a. The amount of change depends on the distance between the probe 106b and the sample 101. Therefore, in order to ensure that the amount of change in amplitude and phase or resonant frequency of the cantilever 106a is always constant, the distance between the probe 106b and the sample 101 is controlled by the three-axis fine-movement mechanism 102 to control the distance in a height direction. Further, a topographic image of a sample surface may be measured by scanning the probe 106b within a plane of the sample 101 by the three-axis fine-movement mechanism 102.
In addition to the oscillating mode atomic force microscope, there is also known a method called contact mode. In this method, the probe and the sample are brought closer to each other by the coarse-movement mechanism while detecting the displacement by the displacement detecting mechanism without exciting the cantilever, and thereafter the distance in the height direction is controlled by the three-axis fine-movement mechanism. At this time, the physical force such as the atomic force acts on a tip of the probe, and the probe experiences an attractive force at first and experiences a repulsive force when the probe and the sample further approach each other. The attractive force and the repulsive force deflect the cantilever. The physical force such as the atomic force depends on the distance between the probe and the sample. Therefore, the probe and the sample are allowed to approach each other within an area in which the atomic force acts on the probe, the probe is scanned within a two-dimensional plane by the three-axis fine-movement mechanism, and the distance between the probe and the sample is controlled so that the amount of deflection of the cantilever becomes constant, to thereby form the topographic image of the sample surface.
In the case of the oscillating mode atomic force microscope, there is also known a method of performing a measurement while exciting the cantilever in the vicinity of a second- or higher-order resonant frequency, in addition to the method of exciting the cantilever in the vicinity of the first-order resonant frequency as described above. In this case, in addition to the oscillating mode in which the tip of the probe oscillates perpendicularly to a long axis direction of the cantilever and in a vertical direction with respect to the sample surface, the cantilever is oscillated in various oscillating modes. A representative oscillating mode includes an oscillating mode in which the probe oscillates torsionally around the long axis of the cantilever.
Further, as an application of the oscillating mode or contact mode atomic force microscope, a physical property such as electrical, magnetical, or optical property, or a mechanical property of the sample is also measured by detecting the physical action at the tip of the probe and the sample surface.
The oscillating mode atomic force microscope using the first-order resonant mode has a merit of causing less damage on the probe and the sample compared to the contact mode atomic force microscope. Further, a signal of the physical property is also detected in synchronization with the oscillation of the cantilever.
On the other hand, the contact mode atomic force microscope has merits of simpler configuration and higher scanning speed compared to the oscillating mode atomic force microscope. Further, the contact mode atomic force microscope may ensure that the cantilever is brought into contact with the sample, and hence is also used for measuring the electrical property of the sample surface.
Further, higher-order oscillating modes are applied to measurements that take advantage of features of the respective oscillating modes. For example, the oscillating mode of the torsional oscillation around the long axis has a feature that the distance between the sample and the probe may be maintained substantially constant during the measurement.
Many measurements by the scanning probe microscope are performed in the atmosphere. However, the cantilever and the sample are placed in a vacuum for measurement when it is desired to eliminate the effect of adsorbed water on the sample surface, vary the temperature of the sample surface, or avoid alteration of the sample surface.
Further, when an organic sample such as a polymer, a cell, a chromosome, a deoxyribonucleic acid (DNA), a protein, or the like, or a biological sample is used, there are cases where the sample and the cantilever are immersed in a solution such as a culture for measurement because the sample is altered when exposed to the atmosphere. The measurement in the solution is applied to in situ observation of a biological sample, an organic polymer sample, and the like, a measurement combined with an electrochemical reaction in the solution, or the like.
Next, referring to FIGS. 5 and 6, a method of controlling the distance between the probe and the sample is described for the oscillating mode atomic force microscope. A current signal generated in the PD 107 in accordance with the oscillation displacement of the cantilever 106a is amplified and converted to a voltage signal by a preamplifier 108. An output from the preamplifier 108, which is an alternate current (AC) signal, is sent to a root mean squared value to direct current (RMS-DC) converter 109 to be converted to a direct current (DC) signal, which corresponds to a root mean squared value.
FIG. 6 is a graph illustrating a relationship between an amplitude amount of the cantilever 106a and the distance between the probe 106b and the sample 101 as the probe 106b and the sample 101 are brought closer to each other from a distance. In FIG. 6, the abscissa represents time in which the probe 106b and the sample 101 are brought closer to each other by the coarse-movement mechanism 103, and the time is converted to the distance between the probe 106b and the sample 101 by being multiplied by a speed of the coarse-movement mechanism 103. The ordinate represents the voltage signal converted by the RMS-DC converter 109, and the voltage signal is converted to the amplitude amount of the cantilever 106a. The change of the signal on the ordinate to the positive side indicates a direction in which the amplitude of the cantilever 106a is reduced. In the scanning probe microscope, a reference signal for measurement is set using the amount of change in amplitude as a parameter in advance in a reference value generating section 111. In the case of bringing the probe 106b and the sample 101 closer to each other, the conventional practice is to bring the probe 106b and the sample 101 closer to each other to a certain extent through manual adjustment by the coarse-movement mechanism 103 while observing by an optical microscope or the like, and thereafter, to further bring the probe 106b and the sample 101 closer to each other by the coarse-movement mechanism 103 until the RMS-DC converted signal reaches the reference signal set in the reference value generating section 111. Note that in bringing the probe 106b and the sample 101 closer to each other, not only the coarse-movement mechanism 103 but also a vertical direction fine-movement mechanism of the three-axis fine-movement mechanism 102 may be used in combination.
As an alternative to the case where the RMS-DC converted voltage is used as the reference signal, there is also a case where a phase difference signal between the voltage applied to the piezoelectric element 105 for exciting the cantilever and the signal detected by the PD 107 may be set as the reference signal in a frequency modulation (FM) demodulator 115.
Further, there is also a mode in which, after a first step of bringing the probe 106b and the sample 101 closer to each other using the phase difference signal as the reference signal, the probe 106b and the sample 101 are retracted once by the vertical direction fine-movement mechanism of the three-axis fine-movement mechanism 102, and the probe 106b and the sample 101 are brought closer to each other up to a measurement area under the same excitation condition by coordinating the vertical direction fine-movement mechanism of the three-axis fine-movement mechanism 102 and the coarse-movement mechanism 103 using the RMS-DC converted voltage signal based on the displacement signal as the reference signal. The phase difference signal starts changing earlier than the RMS-DC converted signal from when the distance between the probe 106b and the sample 101 is still large. Therefore, this mode allows the probe 106b and the sample 101 to approach each other up to the measurement area by bringing the probe 106b and the sample 101 closer to each other at high speed and stopping the probe 106b and the sample 101 reliably at a position at which the probe 106b and the sample 101 do not collide with each other in the first step, and then switching the reference signal to the RMS-DC converted signal.
After bringing the probe 106b and the sample 101 close to each other up to the measurement area, the distance between the probe 106b and the sample 101 is controlled to be constant by feeding back the distance between the probe 106b and the sample 101 so that the amplitude amount of the cantilever 106a is adjusted to the reference signal set in the reference value generating section 111. Specifically, the signal from the RMS-DC converter 109 and the reference signal of the reference value generating section 111 are compared in an error amplifier 110, a signal corresponding to an error is generated in a feedback circuit 112, and a voltage for the height corresponding to the error is applied to the vertical direction fine-movement mechanism of the three-axis fine-movement mechanism 102 through a high voltage amplifier 117. The output from the feedback circuit 112, which is an analog signal, is also converted to a digital signal by an analog/digital (A/D) converter 113, sent to a personal computer for control 114, and imaged as height information. Further, a raster scan signal generated in a scan generator 118 and amplified in the high voltage amplifier 119 is applied to a horizontal direction fine-movement mechanism of the three-axis fine-movement mechanism 102. The raster scan signal and the height information are imaged in the personal computer 114, with the result that the topographic image of the sample 101 may be obtained.
In the scanning probe microscope configured as above, the approach technology for the probe and the sample is very important. Specifically, if the probe and the sample collide with each other when the probe and the sample approach each other, the tip of the probe and the sample surface are broken, to thereby lead to reduced resolution in measuring the topographic image and the damage to the sample. Alternatively, when the speed of the coarse-movement mechanism is lowered to allow the probe and the sample to approach each other more carefully, it takes a long time for the probe and the sample to approach each other, to thereby reduce the measurement efficiency.
Further, in the case of allowing the probe and the sample to approach each other, when the probe and the sample are brought close to each other up to about several tens of μm, the amplitude of the cantilever is gradually reduced by viscous damping due to air that exists in a region between the sample surface and the cantilever. On the other hand, especially when the measurement is performed in the vacuum, the damping due to the air hardly occurs until near the measurement area, and the amplitude hardly changes until the sample and the probe are brought close to each other up to several tens of nm. Therefore, it is difficult to stop the coarse-movement mechanism before causing the collision, and it is more challenging to allow the probe and the sample to approach each other without causing the collision.
In order to reduce the damage to the probe and the sample during the approach as well as to reduce the time it takes for the approach, it is desired to allow the probe and the sample to approach each other at high speed by the coarse-movement mechanism in an area where the probe and the sample do not collide with each other until near the collision, thereafter allow further approach through coordinated operation of the coarse-movement mechanism and the vertical direction fine-movement mechanism, and finally stop the coarse-movement mechanism and operate only the vertical direction fine-movement mechanism when the probe and the sample are brought into contact with each other.
In the conventional method, when the coarse-movement mechanism is operated at high speed, the coarse-movement mechanism may be stopped so late that the probe and the sample may collide with each other. Therefore, in order to reduce the impact in case of the collision or to ensure enough processing time for comparing the RMS-DC converted signal and the reference signal and stopping the coarse-movement mechanism, it has been necessary to lower the speed of the coarse-movement mechanism. As a result, the approach has taken a long time.
In the method including the first step of allowing the probe and the sample to approach each other using the phase difference signal as the reference signal, and a second step of allowing the probe and the sample to further approach each other using the RMS-DC converted signal as the reference signal, the probe and the sample may be allowed to approach each other at high speed without colliding with each other in the first step. However, a special electric circuit such as the FM demodulator is required to perform the measurement using the phase difference signal as the reference signal, and processing for the approach becomes complicated.
Also, it has been impossible to change the excitation condition for the second step because the excitation condition has been the same for the first step and the second step. Especially in the higher-order oscillating modes, it has often been the case that the amplitude or the phase of the cantilever hardly changes until the probe and the sample are brought close to each other up to near the measurement area, which often leads to the collision between the probe and the sample.
Further, in the case of measuring in the contact mode, the probe and the sample often collide with each other to generate a larger impact than in the oscillating mode upon the collision, and hence there has been no choice but to lower the speed of the coarse-movement mechanism.

Approach method for probe and sample in scanning probe microscope