A process control system including a method of suppressing overshoot of a process variable beyond the process value setpoint by predicting the overshoot by observing a waveform associated with the process variable, observing the waveform associated with the process variable, without regard to time scale or to amplitude scale, taking corrective action to reduce or eliminate said overshoot by utilizing a fuzzy logic module with a proportional integral derivative control to take corrective action of the process variable.

1. Field of the Invention
The present invention relates to industrial process control systems, and, more particularly, to a method of suppressing overshoot, i.e., passing through or exceeding a controller setpoint.
2. Background Art
The so-called usage of fuzzy logic has been described in the periodical "Plastic Technology"--June 1996 issue, wherein it is noted that "fuzzy logic tends to make controls think like you do".
Fuzzy logic has been utilized extensively in the area of industrial process control. It has been utilized in place of conventional controls because it is able to overcome some of the problems inherent in typical solutions. It is particularly concerned with the overshooting or undershooting of setpoints or process limits by improving response time. Process control installations have found extensive utilization of fuzzy logic inasmuch as it becomes useful in the areas of temperature or pressure control by dealing with events or characteristics that disturb the normal stability of the usual industrial control structure. When a change occurs during process, because of some extraneous source, it is necessary to take some form of corrective action.
It has been determined that if operational limits are set too loosely in order to control overshoot or undershoot characteristics, a system typically will he slow to react. On the other hand, if tighter standards are included, the system may respond more quickly and subsequently cause more considerable overshoot. Thus, fuzzy logic addresses these concerns by adapting to so-called "human language", such as "too hot", "too cold", "too slow", or "too fast". Simply speaking, fuzzy logic defines process limits with typical linguistic terms other than strict mathematical terms. Effectively processed values are compared to one another and with various degrees of importance assigned to each value with decisions made upon such comparisons. If speed, for example, is excessive, then it would be desirable, for example, to set the speed to "slow".
Single loop controller systems with an included overshoot suppression feature have been disclosed by several manufacturers. One of these is disclosed in a paper entitled "A Proportional Integral Derivative (PID) Controller with Overshoot Suppression Algorithm" by Yasuda, Mano, Mori, Azegami and Crotty from the Proceedings of the ISA90 International Conference and Exhibition--pp 1849-1857. This paper teaches a method to suppress process overshoot using a fuzzy logic control technique.
Overshoot suppression is embedded in a proportional integral derivative controller as a set of knowledge-based fuzzy rules which function to modify the controller internal setpoint so the controlled variable stays on a would-be or proposed response curve without oversshoot in the presence of process changes. This design requires prior setting of a parameter, "the effective process dead time", which is set by the controller's auto tuner. This design works for systems having a relative slow dynamic response. It is reported that if the loop has a very fast overshoot, suppression does not work and could even make the loop unstable.
A fuzzy temperature controller by Omron is disclosed as a fuzzy temperature controller in their Model E5AF. This one-quarter DIN controller combines fuzzy and proportional integral derivative control for fast response to process disturbances. In the disclosed system, advanced PID control with feed-forward circuitry provides optimal response during start-up and steady-state operation. The included fuzzy and PID control work together to correct a process upset quickly with minimal overshot. The arrangement allows fuzzy parameters to be changed to adjust the fuzzy control's impact on the process. Accuracy to .+-.0.3% of set value is claimed. Omron's design indicates that the system requires prior setting of three parameters: fuzzy intensity, fuzzy scale 1 and fuzzy scale 2 by the user. Should these be incorrectly set, or when the system dynamic response is too slow, the system may become unstable.
Accordingly, it is the object of the present invention to describe a method of predicting overshoot in an industrial process control system to enable the control system to take the necessary corrective act ion to reduce or eliminate such overshoot.

Method of predicting overshoot in a control system response


A power amplifying device includes a stabilizing circuit between an input terminal and an amplifier. The stabilizing circuit has a first line, a second line, and a third line. The first line is connected to the ground. The length of the first line is equal to or longer than three fourths of the wavelength of the operating frequency.

1. Field of the Invention
The present invention relates to power amplifying device, and in particular, to power amplifying device for millimeter and micrometer wave bands.
2. Background Art
In Japanese Unexamined Patent Publication No. 2002-353745, a radio frequency power amplifying device for millimeter and micrometer wave bands is described, which comprises a stabilizing circuit disposed near the transistor in order to allow stable operation.
When the stabilization circuit is disposed in the power amplifying device, there is a possibility not to be able to stabilize enough if the change of the characteristic of the transistor is not considered. That is, to attain satisfactory stabilization, it is necessary to take into consideration the changes of characteristics of the transistor. However, there exists a trade-off relation between the stability and the amplifying capability. Particularly, in the millimeter wave band, if no characteristics margin is given to the transistor, designing the stabilizing circuit so as to secure stability regardless of changes of the characteristics of the transistor is likely to make useless much of its potential as an amplifying device.

Power amplifying device comprising a stabilizing circuit


An integrated circuit having enhanced testing capabilities and a method of testing an integrated circuit are provided. The integrated circuit preferably includes a substrate and a memory block on the substrate. The memory block preferably has a plurality of memory cells arranged in a plurality of rows and a plurality of columns within a defined area on the substrate, at least one bit line connected to each of the plurality of memory cells and defining a column, at least one word line connected to each of the plurality of memory cells and defining a row, and sense amplifying means connected to the at least one bit line for sensing a state of an addressed memory cell in at least one of the plurality of columns. The integrated circuit also includes a selectable stress tester on the substrate and connected to the memory block for selectively stress testing only portions of the memory block and not other portions so as to determine whether to accept or reject a memory block.

Integrated circuits are widely used in many electronic applications. A typical integrated circuit may include logic or processor portions along with one or more accessible memory portions on the same integrated circuit die. For example, an application specific integrated circuit ("ASIC") may include one or more random access memory ("RAM") blocks. The RAM blocks typically include arrays or memory cells arranged in rows and columns. A portion of the memory address selects one or more of the memory cells in the selected row and column for access, either for reading data or writing data to the addressed location.
Memory circuits such as RAMs are especially subject to having significant test costs not only because of the necessity of both writing data to and reading data from each of the bits in the memory, but also because RAMs are often subject to failures due to pattern sensitivity. Pattern sensitivity failures arise because the ability of a bit to retain its stored data state may depend upon the data states stored in, and the operations upon bits which are physically adjacent to a particular bit being tested. This causes the test item for RAMs to be not only linearly dependant upon its density (i.e., the number of bits available for storage) but, for some pattern sensitivity tests, dependant upon the square (or 3/2 power) of the number of bits. Accordingly, the density of RAM devices increases, generally by a factor of four from generation to generation. The time required to test each bit of each device in production increases at a rapid rate.
Since the RAM blocks may be embedded with other circuit portions, direct access to the memory blocks also can be very difficult for testing. Memory circuits are typically tested by addressing test patterns to the memory requiring multiple periods of vectors for each test cycle, and millions of test cycles are required to superficially access all bits.
A solution which has been used in the past to reduce the time and equipment required for the testing of memories, such as RAMs, is the use of special test modes, where the memory enters a special operation different from its normal operation. In such test modes, the operation of the memory can be quite different from that of normal operation, as the normal operation of internal testing can be done without being subject to the constraints of normal operation.
An example of a special test mode is an internal parallel or multi-bit test mode. Conventional parallel test modes allow access to more than one memory location in a single cycle, with common data written to and read from the multiple locations simultaneously. For memories which have multiple input/output terminals, multiple bits can be accessed in such a mode for each of the input/output terminals, in order to achieve the parallel operation. Such parallel testing is preferably done in such a way that the multiple bits accessed in each cycle are physically separated from one another so that there is little likelihood of pattern sensitivity integration among the simultaneously accessed bits. Some conventional parallel test operations may be done in different way, but these test operations often require extensive external equipment, e.g., automated test equipment, which often needs to be customized for particular operations. These parallel test operations also can continue to take extensive amounts of time to accomplish the testing results.
Another example of a parallel test operation can be seen in U.S. Pat. No. 5,265,100 by McClure et al. which describes a semiconductor memory with an improved test mode and a method of parallel testing a plurality of memory locations. This method involves selecting the plurality of memory locations, comparing the contents of the selected memory locations, and communicating the contents of a first one of the selected memory locations to an output buffer of the integrated circuit during the comparing step. The output buffer of the memory circuit is then disabled so as not to be able to present the communicated contents of the first memory locations responsive to the result of the comparing step indicating that the contents of the selected memory locations do not all match one another. This parallel test operation, however, can still take extensive amounts of time to accomplish the testing results. Because testing memory of an integrated circuit can continue to take hundreds or thousands of hours and the compaction of circuitry in the same small area continues to increase, these conventional methods and devices are becoming inadequate.

Method of stress testing integrated circuit having memory and integrated circuit having stress tester for memory thereof


Disclosed are mesoporous silica particles and a preparation method thereof, particularly, a method of preparing mesoporous silica particles, including mixing a silica precursor, an alkylamine-based surfactant, and a phosphoric acid-based cosurfactant, thus preparing a mixture solution (a mother liquor); adding or not adding the mixture solution with an acid solution, and conducting stirring, thus providing mesoporous silica particles; and thermally treating the mesoporous silica particles. These mesoporous silica particles are prepared using a phosphoric acid-based cosurfactant for stabilizing the surface of the particles to prevent the aggregation thereof, thereby uniformly distributing the particles. Through a hydrothermal reaction, the mesoporous silica particles have various pore sizes, a large surface area, and a high pore volume, and thus are widely used in catalysts, adsorbents, low dielectrics, and separation and purification processes, and are useful as templates for the preparation of novel porous materials, including porous carbon.

1. Field of the Invention
The present invention relates to mesoporous silica particles having various sizes and a method of preparing the same.
2. Description of the Related Art
Mesoporous silica is one kind of mesoporous molecular sieve. This is a mesoporous molecular sieve in which pores having a uniform size are regularly arranged. A new family of mesoporous molecular sieve materials, designated as M41S, which were synthesized using an ionic surfactant as a structure-directing agent by researchers at Mobil in 1991, are disclosed in U.S. Pat. Nos. 5,057,296 and 5,102,643. Ever since, the mesoporous molecular sieve materials have been used in various application fields, and thorough research thereon is being conducted all over the world.
Unlike the synthesis of conventional molecular sieves, the mesoporous molecular sieves are synthesized through a liquid-crystal templating mechanism, which is advantageous because the types of surfactant serving as a templating material or the synthesis conditions in the synthesis route are controlled, thereby making it possible to adjust the pore size to 1.6˜10 nm.
U.S. Pat. Nos. 6,027,706 and 6,054,111 disclose mesoporous materials prepared using amphiphilic block copolymers as nonionic surfactants. In the case of zeolite, a monomolecular inorganic or organic material generally acts as a templating material for inducing a pore structure, while, in the case of a mesoporous material, a micelle structure, in which multiple surfactant molecules are assembled, is used to induce pores, instead of the monomolecular material. The surfactant, consisting generally of a hydrophilic head portion and a hydrophobic tail portion, is known to constitute various self-assembled micelle and liquid-crystal structures in the presence of an aqueous solution. Located at the surface of the micelle or liquid-crystal structure, the hydrophilic portion interacts with an inorganic precursor to form an organic/inorganic nanocomposite, from which the surfactant is then removed, thus attaining the mesoporous material. The mesoporous material may have a pore size increased to the mesopore range (2˜10 nm), compared to conventional microporous materials having a pore size of 1.5 nm or less, such as zeolite or AlPO-based materials, thereby enabling the application of molecular sieve materials to fields in which the application thereof has been limited until now, for example, adsorption and separation of molecules having a larger pore size than microporous materials, and catalytic conversion reactions. The mesoporous material having regular pores has a very large surface area (>700 m2/g) and thus exhibits superior properties that are able to adsorb atoms or molecules. Further, because the mesoporous material has a uniform pore size, it is used as the carrier of catalyst activators, such as transition metal compounds or amine-based oxides. Furthermore, the mesoporous material is expected to be applied as conductive materials, optical display materials, chemical sensors, fine chemicals and bio-powders, novel insulators having mechanical or thermal properties, and packaging materials, and to have many applications.
To date, research into the synthesis of spherical mesoporous silica nanoparticles smaller than 1 μm and control of the morphology thereof has been extensively conducted to elucidate special physical and chemical properties. However, mesoporous silica particles having a particle size of 10 μm or more are almost impossible to synthesize through the method based on the Stöber process, which is used to synthesize conventional mesoporous particles. On the other hand, few study results on synthesis of mesoporous silica particles larger than 100 μm have been reported [H.-P. Lin and C.-Y. Mou, Acc. Chem. Res., 2002, 35, 927; C.-P. Kao, H.-P. Lin and C.-Y. Mou, J. Phys. Chem. Solids. 2001, 62, 1555].
Further, methods of synthesizing mesoporous silica particles having a size of 30˜50 μm have recently been reported [K. Kosuge and P. S. Singh, Chem. Mater., 2001, 13, 2476]. However, because the synthesized mesoporous silica has a mesopore diameter smaller than 4 nm, many problems may occur when active materials are introduced from the outside.
Although various synthesis methods for adjusting the pore size through the introduction of an organic additive, such as a hydrocarbon, alcohol, or ether, as a swelling agent are known, it is still difficult to prepare silica having mesopores larger than 10 nm using an organic template. Hence, studies on methods of increasing the mesopore size are urgently required.
These days, mesoporous silica, MCM-41, having a very large pore size, is synthesized by introducing N,N-dimethyldecylamine as a swelling agent for increasing pore size [A. Sayari, S. Hamoudi and Y. Yang, Chem. Mater., 2005, 17, 212]. However, the above synthesis method suffers because it has a complicated preparation process and cannot increase the pore size beyond 30 nm.

Mesoporous silica particles and preparation method thereof


A driving mechanism of music snow drop ball, which provides waterproof effect for avoiding rusting of the mechanism. The driving mechanism includes a water ball and a base disposed under the water ball for containing a seat member, an upper and a lower silicone gaskets, a central shaft rod, a fastening plate and a propeller. Each of the gaskets is formed with an inner and an outer rings defining an annular groove, whereby when assembled with the shaft rod, in the case that the water infiltrates back, the water will accumulate in the annular groove to create a fastening pressure which makes the gasket to bind the shaft rod. Therefore, the water is prevented from infiltrating back into the driving mechanism so as to avoid rusting of the driving mechanism.

The present invention relates to a driving mechanism of music snow drop ball, which provides waterproof effect for avoiding rusting of the mechanism.
The conventional music snow drop ball includes a driving mechanism for rotating a propeller placed in the water ball. The propeller rotates to drive up the snow drops in the water in accordance with the music emitted from a music bell. A shaft rod is passed through a shaft hole of a rotary tray of a base of the decoration. A clearance exists between the shaft rod and the shaft hole. Therefore, after a period of use, the water in the water ball tends to infiltrate back through the clearance into the driving mechanism. This will lead to rusting of the driving mechanism and affect the operation thereof. Moreover, in the conventional snow drop ball, the power of the driving motor is transmitted through the shaft rod to the base for rotating the propeller. In the case of rusting mechanism, the stirring force of the driving motor is weakened so that the snow drops can be hardly driven up evenly. Furthermore, the rusting mechanism may lead to clogging of the motor.

Driving mechanism of music snow drop ball


A refrigerant system 1D comprises a heat insulating housing 3 provided with an accommodating space inside and a refrigeration unit 9 attached to a lower portion of the heat insulating housing 3, in which a compressor 5, a gas cooler 6, an internal heat exchanger 10, a restriction means 16 and an evaporator 8 accommodated in a heat insulating case 7A are disposed on a unit base 4. The gas cooler 6 and the heat insulating case 7A are disposed so that air heat-exchanged by the gas cooler 6 moves toward the heat insulating case 7A, an air passage T is provided between the unit base 4 and the heat insulating case 7A, the air heat-exchanged by the gas cooler 6 is passed through the air passage T to be discharged outside, and the internal heat exchanger 10 is disposed in such a manner that it is embedded in a heat insulating material layer 7C provided around the heat insulating case 7A to be provided with a heat insulation property. Accordingly, exhaust heat-exchanged by the gas cooler is discharged outside without stagnation, and increases in an overload and operation power of the compressor are suppressed and the durability of the compressor can be improved. Further, the heat-exchanging efficiency of the internal heat exchanger can be improved and the generation of condensation on a surface of an outer side tube of the internal heat exchanger can be prevented.

1. Technical Field
The present invention relates to a refrigerant system applicable to a vending machine, a showcase or the like, and more specifically relates to a refrigerant system comprising a heat insulating housing provided with an accommodating space, and a refrigeration unit, attached to a lower portion of said heat insulating housing and in which a compressor, a gas cooler, an internal heat exchanger, a restriction means and an evaporator are disposed on a unit base.
2. Related Art
FIG. 8 is an explanatory cross-sectional view of one example of a conventional refrigerant system. The conventional refrigerant system 1A (an example of a showcase) comprises a heat insulating housing 3 provided with an accommodating space 2 inside, and a refrigeration unit 9 attached to a lower portion of the heat insulating housing 3, and in which a compressor 5, a gas cooler 6, a restriction means not shown are disposed on a unit base 4, and an evaporator 8 is accommodated in a heat insulating case 7 attached onto the unit base 4, and the compressor 5, the gas cooler 6, the restriction means not shown, and the evaporator 8 are sequentially connected to form a refrigeration circuit (see for example, Japanese Patent Laid-Open Publication No. H10-96532, No. 2003-56969 and No. 2003-65651). In FIG. 8, the reference numeral 17 denotes a fan for the gas cooler 6, the reference numeral 18 denotes a fan for the evaporator 8, the reference numeral 19 denotes a accommodating shelf for accommodating articles and the reference numeral 9A denotes an exhaust outlet.
When the refrigerant system 1A is operated, refrigerant gas compressed and discharged with the compressor 5 flows into the gas cooler 6. Then outside air is introduced by the fan 17 as shown by an arrow and is heat-dissipated by an air-cooling system. The heat-dissipated refrigerant passes through an internal heat exchanger not shown, and the refrigerant gas is heat-lost by a low-pressure side refrigerant to be further cooled. Then the cooled high-pressure side refrigerant gas reaches an expansion valve (restriction means) and the pressure is controlled to lower pressure so that the refrigerant gas has a two-phase mixture of gas/liquid. The mixture flows into the evaporator 8 as it is and the refrigerant is evaporated there to exhibit a cooling action by heat absorption from air. Then cooled air is introduced into the accommodating space 2 of the heat insulating housing 3 by the fan 18 as shown in an arrow (or in the opposite direction to the arrow) and is circulated.
After that the refrigerant flows out of the evaporator 8 and passes through an internal heat exchanger not shown to take heat from the high-pressure side refrigerant while receiving the heating action. Then the obtained refrigerant is perfectly gasified and the gasified refrigerant repeats cycles to be sucked into the compressor 5.
FIG. 9 is an explanatory cross-sectional view of another example of a conventional refrigerant system. The conventional refrigerant system 1E (an example of a showcase) comprises a heat insulating housing 3 provided with an accommodating space 2 inside, and a refrigeration unit 9, attached to a lower portion of the heat insulating housing 3, and in which a compressor 5, a gas cooler 6, a restriction means not shown are disposed on a unit base 4, a plurality of supporting columns 7B is fixedly provided on the unit base 4, a heat insulating case 7 is set on the column supports 7B and an evaporator 8 is accommodated in the heat insulating case 7, and the compressor 5, the gas cooler 6, the internal heat exchanger 10, the restriction means not shown, and the evaporator 8 are sequentially connected to form a refrigeration circuit (see for example, Japanese Patent Laid-Open Publication No. H10-96532, No. 2003-56969 and No. 2003-65651).
In FIG. 9, the reference numeral 17 denotes a fan for the gas cooler 6, the reference numeral 18 denotes a fan for the evaporator 8, the reference numeral 9A denotes an exhaust outlet and the reference numeral 19 denotes a accommodating shelf for accommodating articles.
When the refrigerant system 1E is operated, refrigerant gas compressed and discharged with the compressor 5 flows into the gas cooler 6. Then outside air is introduced by the fan 17 as shown by an arrow (or in the opposite direction to the arrow) and is heat-dissipated by an air-cooling system. The heat-dissipated refrigerant passes through an inner side tube of the internal heat exchanger 10 composed of a, double pipe and refrigerant gas heat exchanges there with a low pressure side refrigerant, which passes through an outer side tube of the internal heat exchanger 10 to be further cooled by being heat lost. Then the cooled high-pressure side refrigerant gas reaches an expansion valve (restriction means) and the pressure is controlled to lower pressure so that the refrigerant gas has a two-phase mixture of gas/liquid. The mixture flows into the evaporator 8 as it is and the refrigerant is evaporated there to exhibit a cooling action by heat absorption from air. Then cooled air is introduced into the accommodating space 2 of the heat insulating housing 3 by the fan 18 as shown in an arrow (or in the opposite direction to the arrow) and is circulated.
After that the refrigerant flows out of the evaporator 8 and passes through the outer side tube of the internal heat exchanger 10 to take heat from the high-pressure side refrigerant, which passes through the inner side tube of the internal heat exchanger 10 while receiving the heating action. Then the obtained refrigerant is perfectly gasified and the gasified refrigerant repeats cycles to be sucked into the compressor 5.
In the refrigeration cycle, fluorocarbon (R11, R12, R134a or the like) has been generally used as a refrigerant. However, when fluorocarbon is emitted into the atmosphere it has significant problems of the earth-warming effect, the ozone layer breakage and the like in large scale. Thus a study using other natural refrigerants having small influence on the environment, for example oxygen (O2), carbon dioxide (CO2), hydrocarbon (HC), ammonia (NH3), and water (H2O) as a refrigerant has been performed. Among these natural refrigerants, oxygen and water are low in pressure and it is difficult to use them as refrigerants in refrigeration cycles. Since ammonia and hydrocarbon are flammable, there is a problem that their handling is difficult. Thus a device using a transitional critical refrigerant cycles, to be operated on the high pressure side at super critical pressure, where carbon dioxide (CO2) is used as a refrigerant, has been developed (see Japanese Patent Laid-Open Publication No. H10-19401 and No. No. H07-18602).
However, in the conventional refrigerant system 1A, exhaust heat-exchanged by the gas cooler 6 moves in the direction of the heat insulating case 7, and after running against the heat insulating case 7 the exhaust moves around the heat insulating case 7 to flow toward the rear of the heat insulating case 7 so that it is discharged from the exhaust outlet 9A provided on a rear portion of the refrigeration unit 9 to the outside. Accordingly, airflow of the exhaust heat-exchanged by the gas cooler 6 is blocked by the heat insulating case 7 and airflow stagnates around the gas cooler 6 so that heat does not escape. Thus, air cooling of refrigerant gas in the gas cooler 6 becomes insufficient, resulting in an increase in the operation pressure. As a result the compressor 5 reaches an overload state and problems arise that an operation power is increased, a protection device is actuated to stop the compressor and the durability of the compressor 5 is adversely affected whereby its useful life of is shortened.
Alternatively, in the conventional refrigerant system 1E, exhaust heat-exchanged by the gas cooler 6 moves in the direction of the internal heat exchanger 10, and after running against the heat insulating case 7 and the internal heat exchanger 10, the exhaust moves around the heat insulating case 7 and internal heat exchanger 10 to flow toward the rear of the heat insulating case 7 and internal heat exchanger 10 so that it is discharged from the exhaust outlet 9A provided on a rear portion of the refrigeration unit 9 to the outside. As a result, airflow of the exhaust heat-exchanged by the gas cooler 6 is blocked by the heat insulating case 7 and the internal heat exchanger 10, and airflow stagnates around the gas cooler 6 so that heat does not escape. Thus, air cooling of refrigerant gas in the gas cooler 6 becomes insufficient, resulting in an increase in the operation pressure. As a result the compressor 5 reaches an overload state and problems arise that an operation power is increased, a protection device is actuated to stop the compressor and the durability of the compressor 5 is adversely affected whereby its useful life of is shortened. Further, since exhaust heat-exchanged by the gas cooler 6 flows around the internal heat exchanger 10, there are problems that the heat-exchanging efficiency of the internal heat exchanger 10 is lowered and condensation occurs on a surface of the outer side tube (the low pressure side refrigerant, which flows out of the evaporator 8, flows) of the internal heat exchanger 10.
Further, in a case where carbon dioxide is used as a refrigerant, the refrigerant pressure reaches about 150 kg/cm2 G on the high pressure side. On the other hand, in a refrigeration cycle using carbon dioxide as a refrigerant so that the refrigerant pressure reaches about 30 to 40 kg/cm2 G on the low pressure side, the refrigerant pressure becomes higher and the refrigerant temperature also becomes higher as compared with fluorocarbon. Particularly, when single-stage compressing compressor is used, portions, which adjoin between the high pressure side portion and the low pressure side portion are formed in the respective sliding members. Thus there is a problem that since the differential pressure easily generates sliding loss or leak loss and the refrigerant temperature is increased, the air cooling of the refrigerant gas in the gas cooler becomes more insufficient.


A readback apparatus (a) calculates a variance value of a signal read by a head from a disc medium, (b) estimates a degree of offtracking of the head from a target track to an adjacent track, and interference power from the adjacent track using the variance value of the signal, (c) calculates a soft decision likelihood value for the signal using the degree of offtracking and the interference power, and (d) performs error correcting decoding using the soft decision likelihood value.

1. Field of the Invention
The invention relates to a readback apparatus which plays back a recording signal from a disc medium.
2. Description of the Related Art
For example, in a magnetic recording and readback apparatus, the signal-to-noise ratio (SNR) considerably deteriorates due to the contact of a recording and read head (to be simply referred to as a head hereinafter) to a disc medium, loss of magnetic substances on the disc medium, and poor alignment precision of the head, recorded data causes burst errors, and its readback becomes impossible.
Of these burst errors, a burst error caused when the head has contacted the disc medium has a feature in that large DC components are superposed on a readback signal when the head has contacted the disc medium, compared to normal readback. By exploiting this feature, a conventional magnetic recording and readback apparatus digitizes a signal read from the disc medium by the head, and detects the DC components of the digitized signal, thus detecting the position of occurrence of that burst error. As a result, a compensation using error correction processing can be applied to certain burst errors.
In the conventional magnetic recording and readback apparatus, an analog readback signal read from a disc medium (magnetic recording medium) by the head is input to an analog-to-digital converter and digitized. At this time, when the head contacts the disc medium and large DC components are superposed on the signal, if an analog signal output from the head in correspondence with a sample value after digitization exceeds a maximum input value to the analog-to-digital converter, the digital output after analog-to-digital conversion is saturated at a maximum output value of the analog-to-digital converter, and a readback waveform is lost.
A burst detector detects if the waveform of the digital readback signal output from the analog-to-digital converter is saturated at the predetermined maximum output value of the analog-to-digital converter. When the burst detector detects burst interference in which the readback signal after digitization is saturated at the maximum output value, a burst position detector detects the position of occurrence of an error due to the burst interference.
The readback waveform which is lost due to the burst interference is input to a finite impulse response (FIR) equalizer, which equalizes the waveform to an arbitrary partial response (PR) target (e.g., a PR target such as PR(1, 2, 2, 2, 1) or the like). Furthermore, when a Viterbi equalizer having a state transition of the PR target executes equalization processing again, readback data which is hard-decided to "0" and "1" and has suffered the burst error is obtained. The Viterbi equalizer executes Viterbi equalization using, as likelihood information, the distances between the readback signal equalized to the PR target and signal points defined by the PR target, thus obtaining readback data which is hard-decided to "0" and "1".
An error correcting decoder executes error correcting decoding processing using the hard-decided data which is obtained from the Viterbi equalizer and includes the burst error, and the burst position information detected from the readback signal by the burst position detector.
The error correcting decoder corrects the error included in the data after Viterbi equalization using error correcting codes such as Reed-Solomon (RS) codes or the like that requires hard-decided data upon decoding with respect to the hard-decided data obtained by Viterbi equalization, thereby obtaining user data.
With the aforementioned processing operations, even when a readback signal includes burst errors/losses caused when the head has contacted the disc medium, errors in readback data can be corrected. However, the aforementioned burst position detection method detects interference from an adjacent track, and appropriate processing cannot be applied.
In a magnetic recording and readback apparatus which plays back recorded data from a disc medium having neighboring data tracks, when a recording signal for an adjacent track is overwritten on that on a target track due to any offtracking of the head, or when the head position is displaced to an adjacent track upon readback to simultaneously readback signals on the target track and the adjacent track, the signal on the adjacent track becomes burst interference noise with respect to the signal obtained by reading back the target track, but no DC components are generated unlike in the aforementioned case. Therefore, since the signal after analog-to-digital conversion does not have any distinctive feature, and a burst error position cannot be detected, the error rate characteristics upon readback deteriorate considerably.
At this time, when error correcting codes using likelihood information are used upon error correcting decoding, the reliability of likelihood information of a part that has suffered burst interference from the adjacent track in the readback data becomes considerably low. For this reason, the potential correction capability of error correcting codes cannot be exploited, and the error rate of readback data after error correction deteriorates undesirably.
A reference (JP-A 2005-166089 (KOKAI)) discloses a technique for improving the decoding function for burst errors caused when the head has contacted the disc medium. However, the technique disclosed in this reference does not consider any burst error from an adjacent track. This reference cannot improve an error rate upon occurrence of interference from an adjacent track.
Since the conventional magnetic recording and readback apparatus cannot detect any interference noise from an adjacent track due to a offtracking of the head, it cannot accurately calculate likelihood information in a part that has suffered interference in the readback data. For this reason, when error correcting codes using likelihood information are used upon error correcting decoding, sufficient error correction capability cannot be exploited under the influence of likelihood information with low reliability of the interference part.


A toner supply device attachable to a developing device is provided with a toner cartridge mount portion on which a toner cartridge is mounted, a toner outlet in communication with the developing device, a conveyance path which connects the toner cartridge mount portion with the toner outlet, a conveying device for conveying a specified amount of toner in the toner cartridge from the toner cartridge mount portion to a position in the vicinity of the toner outlet, and discharging the toner through the toner outlet immediately when the toner is needed in the developing device. Accordingly, the toner can be supplied to the developing device immediately after the toner density in the developing device decreases below a proper level.

This invention relates to a toner supply device provided with a conveyance path extending from a mount position of a toner cartridge to an outlet in communication with a developing device, and adapted for supplying toner from the toner cartridge to the developing device through the conveyance path.
There have been available image forming apparatuses such as copying machines and printers in which an electrostatic latent image formed on a photosensitive member is developed with two-component developer including toner and carriers. In these image forming apparatuses, a space is defined between a frame of a main body and a cover so as to provide an operation lever or the like for maintenance. In some image forming apparatuses, a toner cartridge is provided in this space so as to make the size of the apparatus smaller.
In these image forming apparatuses, there are provided a toner conveyance path extending from the toner cartridge to a developing device, and a conveying member in the form of a spiral. The conveying member is disposed in the toner conveyance path and is drivingly rotated by a drive motor. The toner from the toner cartridge is designed to fall onto the toner conveyance path spontaneously, and the fallen toner is conveyed by the conveying member up to a toner outlet provided at a downstream side of the conveyance path. The toner is discharged to the developing device through the toner outlet.
After the existing image forming apparatus is installed at a specified place, the developing device is filled with developer having a suitable toner density. Further, a toner cartridge for supplying toner to the developing device when the toner density of the developer decreases below a given level is mounted at a toner cartridge mount portion. At this time, the toner falls onto the toner conveyance path spontaneously and is accumulated at a portion of the conveyance path right below the mount portion.
Thereafter, the toner density decreases as the toner in the developing device is consumed after the start of an image forming operation. The toner density is detected by a toner sensor, and the drive motor is driven in accordance with a sensor signal output from the toner sensor. Thereby, the toner accumulated on the conveyance path right below the cartridge mount portion is conveyed to the toner outlet by the conveying member.
However, the toner density in the developing device remains in the low level until the toner reaches the toner outlet and is supplied to the developing device. Thus, the image forming operation is obliged to continue in a state where the toner density is low until the toner density increases up to an appropriate level, and accordingly images cannot be formed properly.
Further, if the image forming operation is conducted continuously while the toner is conveyed to the toner outlet, the toner density in the developing device decreases further. When the toner density decreases as low as a toner empty level, a toner empty indication is displayed despite the fact that there still remains toner in the toner cartridge.

Toner supply device mounted with a replaceable toner cartridge


A new and distinct cultivar of Gomphrena plant named ‘Balboa’, characterized by its tall and upright plant habit; vigorous growth habit; freely branching habit; large grey green-colored leaves; and purple-colored flowers with a white lanulose-colored reverse giving a bi-color appearance to the flower.

The present invention relates to a new and distinct cultivar of Gomphrena plant, botanically known as Gomphrena leontopodioides and hereinafter referred to by the name 'Balboa'.
The new Gomphrena plant is a product of a breeding program that is focused on creating new upright and freely branching Gomphrena plants that propagate easily and have numerous attractive flowers.
The new Gomphrena plant was discovered and selected by the Inventors as a single flowering plant from within the progeny of a cross-pollination of two unidentified selections of Gomphrena leontopodioides, not patented, in a controlled environment in Gatton, Queensland, Australia on Apr. 19, 2007. The new Gomphrena plant was selected on the basis of its tall upright plant form, grey green-colored leaves and purple and white-colored flowers.
Asexual reproduction of the new Gomphrena plant by terminal cuttings in a controlled environment in Gatton, Queensland, Australia since Jul. 6, 2007, has shown that the unique features of this new Gomphrena plant are stable and reproduced true to type in successive generations.


In one aspect, an adjustment system includes a first gage part adjustably engaged (e.g., mated and/or threaded) with a second gage part. The gage parts may be employed in a (e.g., pressing) process of direct installation of bearings (e.g., tapered roller bearings) on a final assembly spindle (e.g., a motor, pump and/or speed reducer shaft). Also, the gage part(s) may be employed in providing adjustment(s) (e.g., a preload and/or an endplay setting) for an adjustable spacer during the same process of direct installation of the bearings. The gage parts may have various interface(s) with the bearing(s), retainer(s), and/or housing portion(s), rotationally supported with respect to the spindle with the bearings. Further, the gage part(s) may serve to protect the bearing(s) from path(s) of compression employed in the adjustment(s). In another aspect, the gage part(s) may be employed in providing a desired adjustment for a gear mounted on the spindle. For the desired gear adjustment (e.g., an engagement, a clearance, and/or a backlash), gage part(s) may be employed to provide a desired relation between the gear and another gear (e.g., a worm and/or a bevel gear).

Anti-friction bearings serve to decrease friction between, for example, a stator and a rotor. For instance, such bearings may allow relative rotation between the housing and a shaft, spindle or axle extending therethrough. The bearings may comprise roller bearings, for example, tapered roller bearings. In one example, the tapered roller bearings may be employed in wheel hub and axle assemblies. In another example, the tapered roller bearings may be employed in devices such as motors, pumps, or speed reducers.
A typical tapered roller bearing includes a cone having an inner race for mounting on a spindle, a cup having an outer race for mounting in a housing, and a plurality of roller elements within a roller cage positioned between the inner and outer races. Commonly, a pair of such tapered roller bearings are mounted on a shaft for rotation relative to or within a housing. Cooperating bearings, such as a pair of tapered roller bearings, may be included in a bearing assembly, of a motor, pump, speed reducer or transmission assembly.
In order to properly secure bearings in motor, pump, speed reducer, and/or transmission assemblies, it is necessary to retain the bearings tightly under a pre-determined axial tolerance or load on the shaft or axle, so that they will maintain the proper running clearance of the roller elements under the influence of the combined axial and radial forces which they are designed to support. It is often the practice of manufacturers of such assemblies to carefully measure the space between the bearing inner races, and provide a spacer of precisely the correct dimension and load requirements to fit therebetween. The spacer is often made of ground steel tubing to a length tolerance of plus or minus one half of one thousandths of an inch. If the bearings are not maintained at a proper tolerance and/or load the bearings may not roll properly or may prematurely wear, particularly if the bearings are maintained at too high of a load, or may, if maintained under too low of a load, have excessive play causing failure of the bearings.
Certain assemblies including pumps, motors, reducer shafts, bevel gear or worm gear transmission, and other types of transmissions may employ an adjustable spacer or load ring which is typically fitted by means of loading without the assembly. The adjustable spacer may then be mounted, after it has been crushed to a preselected distance, on the bearing assembly. In assemblies which are subject to high loading during service, it may be required that the spacer have a very high capacity to resist being deformed. It may also be desirable to crush or size the adjustable spacer while mounted or on, a partially or fully assembled bearing assembly. In such situations the spacers are typically crushed on the assemblies but the axial load is transmitted through the spacer onto the bearings.
Thus, a need exists for improving ease, accuracy, performance and control of adjustment to an adjustable spacer employed with a bearing assembly of, for example, a pump, motor, or transmission. A need also exists for decreasing dimensional measurements required to properly prepare a spacer and bearing assembly. An additional need exists for a configuration allowing adjustment to an adjustable spacer of a partially or fully assembled bearing assembly of a pump, motor or transmission. A further need exists for providing such adjustment without transmitting the axial load through the bearings prior to final assembly.

Bearing assembly adjustment gaging system


A memory system and a memory controller are disclosed. By determining whether an error has occurred in target data stored in a predetermined target memory area of the memory device and determining, in response to whether an error has occurred in the target data, the magnitude of the supplied power based on a first operation parameter selected among predetermined candidate operation parameters in connection with the magnitude of the supplied power, the memory controller may stably drive a firmware, and may handle an operation error of the firmware due to a change in external environment.

Storage devices refer to electronic components that are used to store data on a permanent or temporary basis. Each storage device may include one or more storage medium to store data and operate based on a request of a host. Examples of the host include a computer, a mobile terminal such as a smartphone and a tablet, or other various electronic devices. The storage device can be classified based on the type of storage medium. For example, a hard disk drive (HDD) uses a magnetic disk as the storage medium, and a solid state drive (SDD), a universal flash storage (UFS) device and an embedded MMC (eMMC) device use, as the storage medium, semiconductor devices such as a volatile memory device and a nonvolatile memory device.
A memory system may include a memory controller for controlling a memory device. The memory controller may receive a command from the host, and may perform or control an operation for reading, writing or erasing data with respect to a volatile memory or a nonvolatile memory included in the memory system, based on the received command. The memory controller may drive a firmware for performing logical calculations to execute or control these operations.
The memory controller is supplied with power from an external power source to drive the firmware through an internal processor. In certain type of memory devices, whether the memory controller stably drives the firmware may depend on a state of power supplied from the external power source.

Memory system and memory controller determining a magnitude of a power supplied to the memory controller when error has occurred in target data


Novel IL-1-R intracellular ligand proteins are disclosed. Polynucleotides encoding the IL-1-R intracellular ligand protein are also disclosed, along with vectors, host cells, and methods of making the IL-1-R intracellular ligand protein. Pharmaceutical compositions containing the IL-1-R intracellular ligand protein, methods of treating inflammatory conditions, and methods of inhibiting IL-1-R intracellular domain binding are also disclosed. Methods of identifying inhibitors of IL-1-R intracellular domain binding and inhibitors identified by such methods are also disclosed.

The present invention relates to the field of anti-inflammatory substances and other substances which act by inhibiting binding to the intracellular domain of an interleukin-1 receptor (hereinafter "IL-1-R"), such as, for example, the p80, type I IL-1 receptor. More particularly, the present invention is directed to novel ligands which bind to the IL-1-R intracellular domain and to inhibition or modulation of signal transduction by this receptor.
Interleukin-1-.alpha. and interleukin-1-.beta. (herein collectively "IL-1") are cytokines which produce a wide range of cellular activities. IL-1 causes an inflammatory response, which can be beneficial, such as in mounting an immune response to a pathogen, or when overexpressed can lead to other detrimental effects of inflammation.
The cellular effects of IL-1 are initiated by the binding of IL-1 to its receptors (IL-1-Rs) on the surface of target cells. The isolation of polynucleotides encoding IL-1-Rs and variant forms of such receptors has been described in U.S. Pat. Nos. 4,968,607, 5,081,228, 5,180,812, in PCT Publication No. WO91/18982, and by Sims et al., PNAS, 86, 8946 (1989) (disclosing the p80, type I IL-1 receptor). Processes for purification of IL-1-Rs have also been disclosed in U.S. Pat. No. 5,296,592.
Native IL-1-Rs are characterized by distinct extracellular, transmembrane and intracellular domains. The primary purpose of the extracellular domain is to present a binding site for IL-1 on the outside of the cell. When IL-1 is bound to the binding site, a "signal" is transmitted to the inside of the cell through the transmembrane and intracellular domains, indicating that binding has occurred. Transmission or "transduction" of the signal to the inside of the cell occurs by a change in conformation of the transmembrane and/or intracellular domains of the receptor. This signal is "received" by the binding of proteins and other molecules to the intracellular domain of the receptor, resulting in the effects seen upon IL-1 stimulation.
While IL-1 binding by IL-1-Rs results in beneficial cellular effects, it is often desirable to prevent or deter IL-1 binding from causing other detrimental cellular effects. Although substantial effort has been expended investigating inhibition of IL-1 binding to the extracellular domain of IL-1-Rs, examination of binding of proteins and other molecules to the intracellular domain of IL-1-Rs has received much less attention.
However, ligands which bind to the IL-1-R intracellular domain have yet to be identified. It would be desirable to identify and isolate such ligands to examine their effects upon IL-1-R signal transduction and their use as therapeutic agents for treatment of IL-1-induced conditions. Furthermore, identification of such ligands would provide a means for screening for inhibitors of IL-1-R/intracellular ligand binding, which will also be useful as anti-inflammatory agents.

Interleukin-1 receptor intracellular ligand proteins


A capacitor structure includes a substrate with a plurality of dielectric layers sequentially formed thereon, a trench formed in the dielectric layers, wherein the trench is composed of at least two interconnected dual damascene recesses, each dual damascene recess formed in one dielectric layer; and a capacitor multilayer disposed on the sidewall of the trench.

1. Field of the Invention
The present invention generally relates to a capacitor structure, and more particularly, to a capacitor structure with interconnected dual damascene profiles made from preformed dual damascene structures and a method of manufacturing the same.
2. Description of the Prior Art
For several decades, the miniaturization of CMOS technology has been the most important technology requirements for increasing developing microprocessor performance and Dynamic Random Access Memories (DRAMs) density. Embedded DRAM (eDRAM), thanks to its native high integration density, allows bringing large memory volume close to computing cores and is widely used as a data buffer or cache at system-on-chip (SOC). With a 2× to 3× higher density than standard Static Random Access Memory (SRAM), it provides a competitive solution for many system design challenges: high performance computing, video processing, server applications, gaming, etc.
A DRAM generally includes an array of bit cells, each cell capable of storing a bit of information. A typical cell configuration consists of a capacitor for storing a charge (i.e., the bit of information) and an access transistor that provides access to the capacitor during read and write operations. The access transistor is connected between a bit line and the capacitor, and is gated (turned on or off) by a word line signal. During a read operation, the stored bit of information is read from the cell via the associated bit line. During a write operation, a bit of information is stored into the cell from the bit line via the transistor. The cells are dynamic in nature due to leakage, and therefore must be periodically refreshed.
Though DRAM is a competitive solution for system design, the performance of the high-density DRAM has not kept pace with the high-performance microprocessor speed, thereby hindering a system performance improvement. For example, with the migration of process node from 45 nm, 32 nm, 22 nm to even 16 nm node, the necessary capacity volume of the capacitor in DRAM cell must be kept to maintain the performance. The current approach in industry to keep the capacity volume of the capacitor is generally to: 1) increase the capacitor depth; 2) increase the dielectric k value (dielectric constant); or 3) thin down the dielectric thickness. Since the approaches 2) and 3) are susceptible to leakage issue, the best way to keeping capacity volume is by increasing the capacitor depth.
However, either for deep-trench type or stack type eDRAM, the depth of trench for accommodating the capacitor can not go deeper due to the physical limitation of etch process, thus it is difficult to keep the necessary capacity volume while the advanced process node keeps migrating and improving.

Capacitor structure and method of manufacturing the same


A bipolar junction transistor includes a substrate, a first layer, a second layer, and a third layer. The first layer comprises non-single-crystalline semiconductor material having a first conductivity type deposited on the substrate. The second layer comprises non-single-crystalline semiconductor material having a second conductivity type deposited on at least a portion of the first layer. The third layer comprises non-single-crystalline semiconductor material having a conductivity type different than the second conductivity type deposited on at least a portion of the second layer. The first, second, and third layers form a collector, base, and emitter of the bipolar junction transistor.

This invention relates in general to the field of integrated circuits, and more particularly to bipolar thin-film transistors and method for forming same.
Thin-film transistors are used in a variety of electronic devices such as high performance active matrix liquid crystal displays, two dimensional medical imagers, sensors, artificial retinas, ring oscillators, and high energy particle detectors. Conventional thin-film transistors are field-effect transistors. Field effect transistors contain three electrodes, source, a drain, and a gate. During transistor operation, current flows from the source to the drain, and the magnitude of that current is controlled by a voltage applied to the gate. The thin-film transistor performance is significantly influenced by characteristics of the interface between the semiconductor and an adjacent dielectric.
These thin-film transistors are generally made from amorphous silicon or polycrystalline silicon. An amorphous silicon thin-film transistor can be fabricated in an array form on large substrates (such as 600 mm by 720 mm glass) at low temperature (such as less than 350xc2x0 C.) with high throughputs. A polycrystalline silicon thin-film transistor generally utilizes a high temperature crystallization, or deposition step, which restricts the number of suitable substrates. Although there are low temperature polycrystalline silicon thin film processes, such as excimer laser crystallization and solid phase crystallization methods, processing time for such methods is usually excessive as compared to the requirements for mass production on very large substrates.
There are two major drawbacks with conventional amorphous silicon thin-film transistors: high photoleakage and low field-effect mobility. The high photoleakage problem has been addressed by the addition of a light blocking layer, such as a metal or a black polymer film, above the thin-film transistors. Conventional thin-film transistors have a maximum mobility of less than about 1.5 cm2/Vs. This level of mobility is proper for some simple local operations such as the pixel switching of a LCD; however, the low mobility greatly restricts the application of thin-film transistors to many advanced products. For example, amorphous silicon thin-film transistors generally cannot be used to build driving circuits of a LCD. Further, many electronic designs require a higher mobility, such as greater than 10 cm2/Vs.
A bipolar transistor may have a higher operating speed than a conventional field-effect transistor (FET), such as a metal-oxide-semiconductor (MOS) transistor. Conventional bipolar transistors are fabricated based on a single crystal silicon wafer. One of the major yield loss factors is the shortening of the emitter and collector regions (also known as piping) due to base-region crystal defect caused by contamination or other factors. Conventional bipolar transistors are prepared on an epitaxy film that is deposited at a high temperature, e.g., above 950xc2x0 C. The out diffusion of the dopant from the collector region greatly limits the minimum base region thickness. Therefore, due to the high temperature, the base and collector concentration profiles are not abrupt.
In accordance with the present invention, a bipolar thin-film transistor and method for forming same is provided that addresses disadvantages and problems associated with conventional transistors.
According to one embodiment of the invention, a bipolar transistor includes a substrate, a first layer, a second layer, and a third layer. The first layer comprises non-single-crystalline semiconductor material having a first conductivity type deposited on the substrate. The second layer comprises non-single-crystalline semiconductor material having a second conductivity type deposited on at least a portion of the first layer. The third layer comprises non-single-crystalline semiconductor material having a conductivity type different than the second conductivity type deposited on at least a portion of the second layer. The first, second, and third layers form a collector, base, and emitter of the bipolar junction transistor.
According to another embodiment of the invention, a method for fabricating a bipolar transistor includes depositing a first layer of semiconductor materials to form a first transistor region, depositing a second layer of semiconductor material over at least a portion of the first layer to form a base of the transistor, and depositing a third layer of semiconductor material over at least a portion of the second layer to form a third transistor region.
The present invention provides various technical advantages over current thin film transistors including higher mobility, higher yield and greater flexibility in transistor structure. In addition, the present invention also has advantages over conventional silicon wafer based thin film transistors including higher yield, lower process temperatures, and less restrictions on size and material of substrates.
Other advantages may be readily ascertainable by those skilled in the art and the following figures, description, and claims.

Bipolar thin-film transistors and method for forming


A system (100) for integrating a driving light (120) with a vehicle's external rear viewing mirror assembly (10) is provided. The driving light system (100) includes a lamp housing (110) having a pair of open opposing ends (104, 106) formed by a wall (102) having a tubular contour. The lamp housing (110) is mountable to an external rear viewing mirror assembly (10) by means of a tab (112) having a portion (116) thereof engageable within a recess portion (16) of the vehicle's rear viewing mirror frame assembly (14), and a fastener (108) which extends through a through opening (117) formed in the tubular wall (102) for engagement with a through opening (18) formed in a portion of the frame assembly (14) of the rear viewing mirror assembly (10). A lamp assembly (120) is disposed in the open end (104) of tubular housing (110), and coupled to the tubular wall (102) for displacement in two orthogonal directions, independent of an adjustable mirror (12) of the rear viewing mirror assembly (10). The system further includes a vertical adjustment assembly (130) rotatively coupled to the tubular wall (102) for displacing the lamp assembly to adjust the light output therefrom in a vertical direction. Additionally, the system includes a horizontal adjustment assembly (150) rotatively coupled to the tubular wall (102) for displacing the lamp assembly to adjust the light output therefrom in a horizontal direction.

1. Field of the Invention
This invention directs itself to vehicle lighting systems. In particular, this invention directs itself to a modular light system fabricated for retrofit to a vehicle's mirror assembly. Still further, this invention directs itself to an integrated driving light system wherein the lamp assembly is coupled to a tubular housing by a multi-axis mounting assembly. More in particular, this invention is directed to an integrated driving light system wherein the lamp assembly is displaceable in either of two orthogonal directions by means of individual controls extending through the system's housing.
2. Prior Art
Vehicle lighting systems are well known in the art. Some prior art vehicle lighting systems include mirror units incorporated therewith, however, such systems do not have provisions for adjusting the light beam direction independent of any mirror adjustment. In particular, no prior art systems are known for providing adaptability to motorcycle mirror assemblies to provide an increase in the focused light distance in front of the motorcycle.


A system and method for transferring messages securely over a computer network which includes the steps of inputting the message to be transmitted at a first device and then encrypting the message at the first device. An address for a dynamically addressed server is obtained and the first device is connected to the dynamically addressed server. The encrypted message is transmitted from the first device to the server and the message is received at the dynamically addressed server. The message is transmitted from the server to a second device and then the message is decrypted at the second device.

This application is not referenced in any microfiche appendix.
1. Field of the Invention
The present invention is directed to an apparatus and method for a secure electronic mail communication system. More particularly, the invention is directed for use in communicating over networks where secure information exchange is required. The invention has utility in applications such as person-to-person communication over network systems, communications over the Internet, interbusiness network communications where security is required, and the like.
2. Prior Art
The use of keys for secure communications is well known. Secure communication systems, as well as key systems, are shown in U.S. Pat. No. 4,182,933, issued to Rosenblum on Jan. 8, 1980, entitled xe2x80x9cSecure Communication System With Remote Key Settingxe2x80x9d; U.S. Pat. No. 4,310,720, issued to Check, Jr. on Jan. 12, 1982; entitled xe2x80x9cComputer Accessing Systemxe2x80x9d; U.S. Pat. No. 4,578,531, issued to Everhart et al., on Mar. 25, 1986, entitled xe2x80x9cEncryption System Key Distribution Method and Apparatusxe2x80x9d; U.S. Pat. No. 4,965,804, issued to Trbovich et al. on Oct. 23, 1990, entitled xe2x80x9cKey Management for Encrypted Packet-Based Networksxe2x80x9d; U.S. Pat. No. 5,204,961, issued to Barlow on Apr. 20, 1993, entitled xe2x80x9cComputer Network Operating With Multi-Level Hierarchial Security With Selectable Common Trust Realms and Corresponding Security Protocolsxe2x80x9d; and U.S. Pat. No. 5,416,842, issued to Aziz on May 16, 1995 entitled xe2x80x9cMethod and Apparatus For Key-Management Scheme For Use With Internet Protocols At Site Firewallsxe2x80x9d.
U.S. Pat. No. 4,182,933, issued to Rosenblum on Jan. 8, 1980, discusses a xe2x80x9cSecure Communication System With Remote Key Settingxe2x80x9d. The Rosenblum ""933 patent describes a system wherein a first subscriber communicates with a key distribution center to get an updated key to initiate secure communications with a second subscriber. An overview of the system shows that the user dials a telephone number into the first subscribing unit. The first subscribing unit then places the telephone number into temporary memory storage. The first subscriber then retrieves its initial caller variable from memory and places it into a key generator. The first subscriber then retrieves the number of the key distribution center (KDC) from its memory and dials the number. Once a connection has been established the first subscriber sends its caller ID as well as the caller ID of the telephone number being called to the KDC. This information is not yet transmitted in a secure manner.
Once the KDC has received the information from the first subscriber, the KDC looks up the caller variable for both the first subscriber and for the telephone number being called. The KDC then generates a new caller variable for the first telephone number. The KDC then transmits the caller variable for the number being called, a new caller variable for the first subscriber, using a secure transmission controlled by the initial caller variable. If this transmission is successful, then the KDC will replace the old caller variable in its table format with a new caller variable and break the connection.
Once the first subscriber has received and deciphered the caller variable for the number to be called and its new key caller variable, it will replace the old and used initial caller variable key with the new caller variable key. The first subscriber will then send the key for the number to be called to the key generator, retrieve the telephone number to be called, and dial the telephone number. The first subscriber will then transmit any information input by the user to the second subscriber using the second subscriber key. The second subscriber will receive information that has been encoded with the second subscriber key and will decode the information and transfer it on to the second user. In an alternative embodiment, after the phone call between the first subscriber and second subscriber, the second subscriber will call and get a new key from the KDC. In this alternative embodiment, both the key for the first subscriber and for the second subscriber will be changed out on every telephone call.
U.S. Pat. No. 4,310,720, issued to Check, Jr. on Jan. 12, 1982 discloses a xe2x80x9cComputer Accessing Systemxe2x80x9d. The specification discloses a method for communicating between an access unit and a computer. The user enters his password into an input device which is connected to an access unit. The access unit generates a pseudo random access key from the password that is entered. The access unit then sends the access unit number and the generated access key to the computer controller for access to the computer system. The computer controller receives the access unit number and access key. The computer controller then verifies the access unit number. If the access unit number is properly verified, the computer controller will then compare the access code to the expected access code listed in a table in the computer""s memory. This expected access code is generated using a congruent pseudo-random decoding algorthym. If the access key code and the expected code match, then the computer controller will establish a link between the access unit and the computer.
The access unit and the computer will talk through an encoded communication system. Both the access unit and the computer will use a randomly generated encryption key for encoding and decoding the communication. This key is independently generated by both the access unit and the computer and is not transmitted over the access unit to computer link. After the termination of the call between the access unit and the computer, the computer will generate and store the next access key number for that particular access unit.
U.S. Pat. No. 4,578,531 issued to Everhart et al. on Mar. 25, 1986 discloses an xe2x80x9cEncryption System Key Distribution Method and Apparatusxe2x80x9d. This system allows the secure method for communication between a terminal xe2x80x9cAxe2x80x9d and terminal xe2x80x9cBxe2x80x9d by using a remote key distribution center. An initial signal is sent from terminal xe2x80x9cAxe2x80x9d to terminal xe2x80x9cBxe2x80x9d to initiate the process of generating a secure communication line. Terminal xe2x80x9cAxe2x80x9d then generates a new call set up key in preparation for communication with the key distribution center, and a partial session key which will be transmitted through the key distribution center to terminal xe2x80x9cBxe2x80x9d. Terminal xe2x80x9cAxe2x80x9d then updates its verification information in preparation for communication with the key distribution center. Terminal xe2x80x9cAxe2x80x9d then initiates the connection with the key distribution center to which it sends its terminal address and the terminal xe2x80x9cBxe2x80x9d address and an encrypted message including the two generated keys and the verification information. At this point, terminal xe2x80x9cAxe2x80x9d will wait for the processing by the key distribution center.
The key distribution center will read the address information from the signal sent from terminal xe2x80x9cAxe2x80x9d and use this to access a de-cryption key previously sent in communication with terminal xe2x80x9cAxe2x80x9d. The message from terminal xe2x80x9cAxe2x80x9d will then be de-crypted and the verification information will be updated. The key distribution center will then generate a bidirectional asymmetric encryption/de-cryption key pair. The first part of this key pair will be sent to terminal xe2x80x9cAxe2x80x9d, and the second part of the key pair will be sent to terminal xe2x80x9cBxe2x80x9d. A similar communication will happen with terminal xe2x80x9cBxe2x80x9d.
The message to terminal xe2x80x9cAxe2x80x9d will consist of a subsequent call key for the next communication with a KDC, a partial session key which it received from terminal xe2x80x9cBxe2x80x9d, verification information, and two other variables xe2x80x9cYxe2x80x9d and xe2x80x9cQxe2x80x9d. These five pieces of information will be encrypted using the call set up key for the present communication with terminal xe2x80x9cAxe2x80x9d and the information will be transmitted to terminal xe2x80x9cAxe2x80x9d. A similar encrypted message will also be sent to terminal xe2x80x9cBxe2x80x9d from the KDC.
Terminal xe2x80x9cAxe2x80x9d will de-crypt the message from the KDC and verify that the information is correct. Terminal xe2x80x9cAxe2x80x9d will then store the new communication key for the next communication with the KDC, take down the channel to the KDC, and establish a communication channel with terminal xe2x80x9cBxe2x80x9d. A similar process will happen at terminal xe2x80x9cBxe2x80x9d. At this point, terminal xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d will be able to communicate securely using the partial keys that were exchanged through the KDC. Terminals xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d can then use a random number and the variables xe2x80x9cYxe2x80x9d and xe2x80x9cQxe2x80x9d to create a new key which may be used to communicate securely between terminals xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d. By using the variables and a random number to generate a new communication key, a secure communication encryption message may be employed which cannot be known by any outsiders to terminal xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d, including the KDC.
U.S. Pat. No. 4,965,804, issued to Trbovich et al., on Oct. 23, 1990, discloses a xe2x80x9cKey Management For Encrypted Packet Based Networksxe2x80x9d. This method of key management uses a key distribution center for sending keys to remote locations so that a secure communication can be made. Specifically, the system is designed to be compatible with X.25 type packet switching networks. This compatibility requires a balanced transmission which is implemented by a transparent device between the source DTE and second YDTE. The source DTE sends a transmit request to the transparent device which responds with a dummy signal back to the source DTE. The transparent device then contacts the key management system and obtains a key. A similar key is sent to the transparent device for the second DTE. The transparent devices for the first DTE and the second DTE then establish a communication network with an encrypted signal transfer, and finally the source DTE talks to the second DTE through the transparent devices and the encrypted connection.
U.S. Pat. No. 5,204,961, issued to Barlow on Apr. 20, 1993, discloses a xe2x80x9cComputer Network Rating With Multi-Level Hierarchial Security With Selectable Common Trust Realms and Corresponding Security Protocolsxe2x80x9d. The invention involves a method for setting up network communications between two trusted computer systems. Each trusted computer has a common set of protocols for the protection of data contained therein. Thus, if a user for a trusted computer system attempts to send data to a non-trusted computer system, then the trusted computer system will stop the message transfer and will not allow the communication to occur. This system operates as a method for two trusted computers to talk over a network which is not physically secure against interlopers. Each computer that is a member of a specific trust realm enforces a predefined security policy and defines security levels for the data contained within the computer. Before a trusted computer transmits a specified message, the trusted computer checks the trust realm table to verify that both the transmitting and receiving computers are part of at least one common trust realm. If both computers are part of a common trust realm, then the message will be transferred using the appropriate protocol for that trust realm. If the computers are not both members of the trust realm, then the message will not be transmitted. The communication between two trusted computers consists of a message which is transmitted as a protocol data unit which includes a sealed version of the message, authenticated identifies for the sending system and user, the message security level label, and an identifier for the selected trust realm. The transmitted message is then received, processed for validity and if valid, the message is processed within the receiving computer.
U.S. Pat. No. 5,416,842, issued to Aziz on May 16, 1995, discloses a xe2x80x9cMethod and Apparatus For Key-Management Scheme For Use With Internet Protocols at Site Firewallsxe2x80x9d. This system consists of separate private networks which communicate over an Internet type connection through firewalls. A private network xe2x80x9cIxe2x80x9d communicates through a firewall xe2x80x9cAxe2x80x9d to the Internet where the message is transferred to firewall xe2x80x9cBxe2x80x9d and then decoded and sent on to another private network xe2x80x9cJxe2x80x9d. This allows private network xe2x80x9cIxe2x80x9d and private network xe2x80x9cJxe2x80x9d to communicate in a secure encapsulated message while having firewall protection. The invention begins with a source node xe2x80x9cIxe2x80x9d sending a data gram to the firewall xe2x80x9cAxe2x80x9d. Firewall xe2x80x9cAxe2x80x9d has a secret value xe2x80x9cSAxe2x80x9d and a public value xe2x80x9cPAxe2x80x9d. Similarly, firewall xe2x80x9cBxe2x80x9d is provided with a secret value xe2x80x9cSBxe2x80x9d and a public value xe2x80x9cPBxe2x80x9d. In this manner both firewall xe2x80x9cAxe2x80x9d and firewall xe2x80x9cBxe2x80x9d can acquire a shared secret value xe2x80x9cSABxe2x80x9d without having to communicate. The communication is initiated by providing firewall xe2x80x9cAxe2x80x9d and firewall xe2x80x9cBxe2x80x9d with initial values for all other secure firewalls on the network. Firewalls xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d then use secret value xe2x80x9cSABxe2x80x9d to create a key xe2x80x9cKABxe2x80x9d. The transmitting firewall then generates a random key xe2x80x9cKPxe2x80x9d which is used to encrypt the received data. The key xe2x80x9cKPxe2x80x9d and the encrypted data are then all encrypted by the public key xe2x80x9cKABxe2x80x9d for transmission over the Internet. Firewall xe2x80x9cBxe2x80x9d will then use key xe2x80x9cKABxe2x80x9d to de-crypt the message for the private key xe2x80x9cKPxe2x80x9d and de-crypt the data that has been transmitted. In this manner the transmitting firewall can constantly be changing the private key xe2x80x9cKPxe2x80x9d which increases the security of the system.
The above-described key distribution and encryption systems suffer from the drawbacks of using known communication pathways, having known addresses, and some systems even transfer secure key information over the communication lines.
Hence, there is a need for an improved communication method which allows for encrypted information transfer to dynamic locations without transmitting the keys over the communication line.
Additionally, there remains a need for a mechanism in which to log on to a computer system securely without passing password.
In accordance with the present invention, an improved encoded or encrypted method for transferring information is provided which addresses the drawbacks of the prior art devices.
In accordance with one embodiment of the present invention a message is input to a first device which obtains a dynamic address from a first server to allow for connection to a second server.
A further embodiment of the invention allows for transmitting the message from the first device to the second server, receiving the message at the second server, storing the message until transfer to a second device as requested, and then transmitting the message to the second device from the second server.
Another embodiment of the present invention allows for encoding the message before it is input to the first device, and decoding the message after it has been received at the second device.
Yet another embodiment of the present invention allows for multiple servers which can be contacted to obtain the dynamic address of another server.
A still further embodiment of the present invention uses a remote administrator to control access both to the first server for obtaining the dynamic addresses, and to the second server for message transfers.
In accordance with another embodiment of the present invention, the user access to the secure name server is controlled by a remote administrator which creates, authorizes and deletes valid user ID/password combinations.
In accordance with another example of the present invention, the system allows for an electronic mail transfer between two users where a direct communication between the first user and second user never occurs. In this manner, two users can communicate without actually having a direct connection which is detectable by other parties.
The principal object of the present invention is to provide an easy to use, protected, electronic mail system for communication.
Another object of the present invention is to allow for the establishment of multiple electronic mail servers for different user categories.
A still further object of the present invention is to provide for a system which can communication on both secure and non-secure electronic mail servers.
Yet another object of the present invention is to provide for a program which allows for automatic and immediate deletion of electronic mail messages once they have been sent.
Other objects and further scope of the applicability of the present invention will become apparent from the detailed description to follow, taken in conjunction with the accompanying drawings wherein like parts are designated by like reference numerals.


A method an apparatus for performing a reset operation in an integrated circuit where a memory programming voltage is recovered allowing use of the memory during reset. The voltage recovery unit includes a high voltage conversion portion active for a first recovery period, and a low voltage conversion portion active for a subsequent second recovery period, the low voltage conversion portion is inactive for the first recovery period. The first and second recovery portions are responsive to assertion of a reset signal and an intermediate reset signal generated before the end of the reset period. Recovery of the programming voltage allows uncorrupted retrieval and use of a configuration word during reset. The high voltage conversion portion includes p-channel devices with robust breakdown resistance, and the low voltage conversion portion includes n-channel devices which provides improved speed of operation.

As new technologies are developed to achieve smaller and smaller integrated circuit geometries, voltage differentials and frequency of operation present problems in circuit design and device selection. One such problem exists where the design technology limits the breakdown voltage of n-type devices. Typically, n-type devices operate more quickly than p-type devices, but are limited in voltage range. As physical geometries decrease there is a resultant decrease in the breakdown voltage of n-type devices. At higher voltages, the breakdown of n-type devices may be violated. It is desireable to design circuits which satisfy the voltage requirements of n-type devices while maintaining performance of the circuit.
Integrated circuits often include a charge pump for controlling the voltage supply of an analog-to-digital converter or memory programming circuit. At smaller geometries, the voltages necessary for control and operation of these voltage supplies is beyond the voltage range of n-type devices. There is a need for a method of handling the supply voltages while maintaining the speed of the circuit and maintaining efficient production.
In the drive to reduce the size of the integrated circuit, it is desirable to minimize the circuitry and logic necessary to incorporate features. Designers seek to optimize the use of a memory in performing reset and other maintenance operations. When a memory is part of the data processing system, it is desirable to use that memory for efficient reset operations. When the memory is a programmable memory there is often an associated charge pump to generate a programming voltage. Prior to use during a reset operation, it is desirable to ensure that any programming voltages have been recovered to a lower voltage level. There is a need for a reset method which uses a programmable memory without corrupting data from that memory.

Voltage recovery circuit and method therefor


An electrical circuit such as a Wheatstone bridge has a conductive strip extending between a current input terminal and a current output terminal and includes two resistors having a connecting part therebetween, a conductive segment extending between the connecting part and a measuring terminal, the connecting part being formed as a wider portion of the conductive strip in the direction of the conductive segment, the conductive segment having an adjusting portion between the connecting part and the measuring terminal.

1. Field of the Invention
This invention relates to an electrical circuit such as a Wheatstone bridge with at least one resistance-adjusting portion.
2. Description of Related Art
Such circuits are widely used to measure the deformation of mechanical parts through the variation in the resistances of the resistors which they include and which are deformed at the same time as the part on which they are bonded or deposited. An important advantage of a Wheatstone bridge is its high stability over long periods and with respect to changes in temperature. It is however necessary to adjust the resistances to balance the bridge, i.e. to obtain a null signal between the measuring terminals when no load is applied. This is why bridges are provided with additional resistors which can be adjusted to balance the bridge and possibly its thermal sensitivity. Several methods have already been developed to effect these adjustments.
In U.S. Pat. No. 4,945,762, current-limiting resistors and adjusting resistors are placed in series. During normal operation of the circuit current flows simultaneously through the adjusting resistors and the current-limiting resistors. When an adjustment is to be made, current is caused to flow in a reverse direction in a pulsed mode so as to bypass the bridge resistors and current-limiting resistors and flow through branches formed by diodes which are conducting in this one direction only. The current passes through the adjusting resistors only, which resistors are then subject to such an intensity of current that migration of constituent atoms occurs towards the surrounding substrate, which modifies their resistance.
In other proposals, adjusting resistors connected in parallel are added or removed. A disadvantage is that the carrying out of such operations entails physical/chemical non-uniformities in the conductive material which forms the bridge or circuit, for example by oxidation. The different materials or alloys usually have characteristics which change differently with time and which also behave differently in response to variations in temperature, as the thermal behavior is also a characteristic of the material. Measurement quality is compromised by these various sources of inaccuracy.

Electrical circuit such as a Wheatstone bridge with a resistance-adjusting portion


The invention relates to a time division and wavelength division multiplex optical switching node for use in an optical communications network (2), which node combines a set of time division multiplex packets (8-1, 8-2, . . . , 8-i) into a wavelength division multiplex packet (18) to form a composite wavelength division multiplex packet, in particular by conferring on each time division multiplex packet (8-1, 8-2, . . . , 8-I) a respective appropriate multiplexing wavelength (λ1, λ2, . . . , λi), for example a wavelength specific to each time division multiplex packet. The invention has applications in high bit rate optical networks in particular, in which it offers versatility and transparent use of the different multiplexing modes.

Optical networks are used to convey very large volumes of digital data traffic on continental and intercontinental scales, for example for Internet multimedia applications. At present optical technology provides in-fiber bit rates of the order of one Terabit per second (1012 bits per second), although the theoretical limits are much higher, and is therefore the solution of the future for exchanging high-density information, especially voice and video.
FIG. 1 shows an example of an optical communications network 2 deployed on the European continent and known as the European Optical Network (EON). Like any network, it includes a set of nodes 4, which are called switching matrices, interconnected by optical fiber links 6. The connectivity of a switching matrix 4, which expresses the number of links 6 that it connects, is typically of the order of three or four. Some switching matrices 4′ relay calls to other continents.
Two multiplexing techniques are used for packet mode optical transmission networks:                Time division multiplexing (TDM). FIG. 2a shows the basic configuration of a packet 8 conforming to this multiplexing mode, referred to hereinafter as a TDM packet. The packet has a header 10 at one end and blocks of data 12 that constitute the payload of the packet. All the elements (payload and header) of a TDM packet 8 are carried on one carrier wavelength λi suitable for the network.
Wavelength division multiplexing (WDM) combines a plurality of independent data channels, each allocated its own carrier wavelength, on a single medium, in this instance an optical fiber, and reduces the bit rate per carrier, and therefore relaxes the physical constraints (bit rate limited modulation electronics, resistance to noise, etc.). FIG. 2b shows an example of a data packet 14 conveyed on a fiber using wavelength division multiplexing and four carrier wavelengths λ1 to λ4. Each carrier transmits respective sub-packets 8a to 8d having respective payloads 12a–12d and together forming the payload of the packet 14 conforming to this multiplexing mode, referred to hereinafter as a WDM packet. A WDM packet 14 generally includes a single header 10, which here is contained in the sub-packet 8d on the wavelength λ4. The sub-packets 8a–8d are transported in parallel in the fiber, using the principle of linear superposition.
Because the switching matrices 4 must be dedicated either to TDM packets or to WDM packets, a conventional optical network manages only one or the other of the two multiplexing modes.
Switching matrix input and output ports use multiplexing and demultiplexing means designed to work at a wavelength or at a set of wavelengths and to route packets in accordance with protocol rules imposed by the TDM mode or by the WDM mode.
There are also optical communications networks that route data in circuit mode, i.e. without dividing the data into packets. In this context, multigranularity optical network architectures have been proposed for managing wavelength division multiplexed information. The granularity expresses the basic vector that conveys data and, depending on the network and the location within the network, can be: i) the carrier wavelength, ii) a group of wavelengths, called a band, or iii) the carrier fiber. These three forms of granularity conform to a hierarchy in the sense that fiber level granularity is a physical member and transports all of the n wavelengths accepted by the network, group level granularity constitutes a subset of m wavelengths, and wavelength level granularity comprises only one of the n or m wavelengths.
The switching matrices of a multigranularity network comply with this hierarchy in providing three respective switching stages, each equipped with its own space-division switch, namely:                a first stage, disposed between the input and output fibers of a link, which extracts a bitstream from a selected fiber,        a second stage in which a demultiplexer receives the bitstream from a fiber selected by the first stage to extract a group therefrom, and        a third stage in which a demultiplexer receives a group from the second stage to extract a selected wavelength therefrom.
These three stages are also adapted to carry out a converse series of multiplexing operations leading to a selected fiber from a wavelength or a group.
An architecture of the above kind is advantageous because it can convey different wavelengths on a common section of the network, not individually, but as a group, which lightens routing management by using only one port at a time for collective routing.
In the current state of the art, because control is asynchronous, a multigranularity architecture cannot be envisaged in other than the circuit mode. In packet mode transmission, at least some of the information takes the form of TDM packets, especially on the links 6, which makes it necessary to retain a synchronous mode.
The document WO 01/95661 discloses a method of managing data in the form of packets in an optical communications network; the method includes a step of combining a set of time division multiplex packets into a wavelength division multiplex packet to form a composite wavelength division multiplex packet.
The above document describes a node having:                a first level consisting of time division multiplex packet switching matrices, and        a second level consisting of a wavelength division multiplex packet switching matrix.
The first and second levels are coupled by multiplexers and spectral multiplexers.
The above prior art node switches only time division multiplex packets and its core switches only wavelength division multiplex packets containing time division multiplex packets.

Time division multiplex and wavelength division multiplex optical switching node