An apparatus for and method of preventing paper double feeding in a paper feeding unit of a printer include a stripper which is installed to be inclined at a predetermined angle and attached to at least one front side of a plurality of paper guides, a lever which is installed at a rear side of the stripper and has a contact surface with paper transferred by a pickup roller, and a lever shaking unit which shakes the lever so that the contact surface intermittently contacts a back side of the paper transferred by the pickup roller. The method includes applying a first paper feeding resistance force to a first sheet of paper which is picked-up by the pickup roller and transferred into the printer, and intermittently applying a second paper feeding resistance to a rear side of a second sheet of paper.

1. Field of the Invention
The present invention relates to a printer, and more particularly, to an apparatus for and method of preventing paper double feeding in a paper feeding unit of a printer.
2. Description of the Related Art
In general, a printer or a copier includes a paper feeding unit which receives a plurality of sheets of paper and sequentially feeds the received sheets of paper.
FIG. 1 is a perspective view of a paper feeding unit of a printer employing a conventional apparatus for preventing paper double feeding, FIG. 2 is a side view schematically illustrating the paper feeding unit of the printer to explain an operation of the conventional apparatus shown in FIG. 1, and FIG. 3 is an enlarged view illustrating a front end of a sheet of paper fed in the apparatus of FIG. 2.
Referring to FIGS. 1 and 2, the paper feeding unit includes a paper cassette 20 which is installed to be detachably attached to a frame 10 of the printer, and on which a plurality of sheets of paper P are stacked, and a pickup roller 30 installed to be rotated with respect to the frame 10 of the printer and placed on an upper portion of the paper P stacked on the paper cassette 20. The pickup roller 30 is connected to a shaft 44 rotated by a driving motor 42 and to a gear group 46, is supported by a support arm 48 installed to pivot at the frame 10, and contacts the paper P stacked on the paper cassette 20 due to its weight. Also, an outer surface of the pickup roller 30 is formed of a material having a comparatively large friction coefficient so that the pickup roller 30 easily picks up the paper P. The paper feeding unit further includes a paper guide 50, which is fixed on the frame 10 of the printer and is placed at a front end of the paper cassette 20 to guide the paper P transferred into a printing unit of the printer by the pickup roller 30.
The apparatus for preventing the paper double feeding is provided in the paper feeding unit of the printer having the above structure. As shown in FIGS. 1-3, a stripper 52 generally formed of stainless plates or a synthetic material, such as TEFLON, as the apparatus for preventing the paper double feeding, is attached to a front side of the paper guide 50, that is, to a surface of the paper guide which the paper P contacts. The stripper 52 is installed to be inclined at a predetermined angle θ from a horizontal plane, to prevent double feeding of the paper P.
Referring to FIG. 3, if the pickup roller 30 that contacts a first sheet of paper P1 of the paper P stacked in the paper cassette 2 rotates, the first sheet of paper P1 is transferred into the printer by a friction force between the pickup roller 30 and the first sheet of paper P1. In this case, traveling of a second sheet of paper P2 is disturbed by the stripper 52 inclined at a predetermined tilt angle θ, so that only the first sheet of paper P1 is picked-up by the pickup roller 30 and can be transferred into the printer.
A paper feeding force Fp that acts on the first sheet of paper P1 due to the friction force between the pickup roller 30 and the first sheet of paper P1 may be obtained by Equation 1.Fp=μroll×N  (1)
Here, μroll represents a friction coefficient between the pickup roller 30 and the first sheet of paper P1, and N represents a vertical force that acts on the first paper P1 from the pickup roller 30.
Also, a second paper feeding force FD that acts on the second sheet of paper P2 due to another friction force between the first sheet of paper P1 and the second sheet of paper P2 may be obtained by Equation 2.FD=μpaper×N  (2)
Here, μpaper represents another friction coefficient between the sheets of paper P. Meanwhile, a paper feeding resistance force FN that disturbs feeding of the paper P is generated by the friction force between the paper P and a resistance generated by the stripper 52, and the paper feeding resistance force FN may be obtained by Equation 3.FN=μpaper×N+Fstripper  (3)
Here, Fstripper represents the resistance that acts on the paper P due to the stripper 52. The resistance Fstripper generated by the stripper 52 is proportional to the tilt angle θ of the stripper 52.
Likewise, the above-mentioned three forces are generated when the paper P is picked-up by the pickup roller 30 and is transferred into the printer. In order to prevent double feeding and non-picking up of the paper P, the three forces should satisfy the following conditions of Equation 4.Fp>FN>FD  (4)
More specifically, the paper feeding force Fp that acts on the first sheet of paper P1 should be larger than the paper feeding resistance FN, so that the first sheet of paper P1 is picked-up and is transferred into the printer. Accordingly, in order to satisfy the above conditions, the tilt angle θ of the stripper 52 should be properly set. If the tilt angle θ of the stripper 52 is too large, the paper feeding resistance force FN becomes larger than the paper feeding force Fp such that the first sheet of paper P1 is not picked-up.
Also, in order to prevent double feeding of the second sheet of paper P2 together with the first sheet of paper P1, the paper feeding resistance force FN should be larger than the paper feeding force FD that acts on the second sheet of paper P2. Thus, in order to satisfy the above conditions, the tilt angle θ of the stripper 52 is appropriately set.
That is, the stripper 52 as the conventional apparatus for preventing the paper double feeding has the tilt angle θ of about 70 degrees, large enough to satisfy the above-mentioned two conditions.
However, when an adhesive force is generated between the first sheet of paper P1 and the second sheet of paper P2 due to static electricity generated therebetween or an alien substance interposed therebetween, the paper feeding force FD that acts on the second sheet of paper P2 may be larger than the paper feeding resistance force FN. This is because since the paper feeding resistance force FN that acts on the second sheet of paper P2 is defined by the friction force between the second sheet of paper P2 and a third sheet of paper P3 and by the resistance Fstripper generated by the stripper 52, the paper feeding resistance force FN remains constant, whereas the adhesive force between the first sheet of paper P1 and the second sheet of paper P2 is added to the paper feeding force FD that acts on the second sheet of paper P2. In this case, a double feeding phenomenon occurs when the second sheet of paper P2 is transferred into the printer together with the first sheet of paper P1. The double feeding phenomenon may occur in a case of the third paper P3 or another paper thereunder. In this case, three or more sheets of paper are transferred into the printing unit of the printer.
As described above, the friction force or the adhesive force between the sheets of paper P is not always uniform. Thus, in order to prevent the paper double feeding, the tilt angle θ of the stripper 52 should be large. In this case, the paper feeding resistance force FN may be larger than the paper feeding force FP, so that the first sheet of paper P1 is not picked-up. Thus, the pickup roller 30 is rotated with a larger torque by using the driving motor 42 having a large capacity or controlling a deceleration ratio, so that the paper feeding force FP increases. In this case, a load on other elements of the paper feeding unit, such as the gear group 46, increases. Thus, these elements wear or break rapidly, and a life span of the elements is reduced.

Apparatus for and method of preventing paper double feeding in printer


A polyurethane or polyisocyanurate foam is derived from a mixture comprising a crude isocyanate component and a polyol component which contains all or some of the following products in a homogeneous mixture: polyols, catalysts, surfactants, water, flame-retardants, expanding agents, fillers, dyes and pigments, in which the expanding agents comprise a pentane component associated with a dialkanolamide derived from fatty or oily substances of vegetable origin.

Polyurethane is well known as a base product for the manufacture of rigid foams which are used widely as insulators in refrigerators and freezers, in insulating panels for buildings, and for the refrigeration industry, in sheets for insulating transportation means, tanks, pipes, and even for the production of high-density rigid foams for furniture or for technical products in general.
Polyurethane is also well known as a base product for the manufacture of flexible or semiflexible foams which are used widely as cushions and mattresses in the furnishing industry, and as padding in seats, arm-rest, bumpers etc. in the car industry, where it is often used with the RIM-RRIM technology.
Polyurethane foam is produced by the intimate mixing and reaction of two liquid products, an isocyanate component, usually crude MDI, and a polyol component which contains all or some of the following products in a homogeneous mixture:
polyols -- reactive products of suitable molecular weight for reacting with the isocyanate to form a rigid, flexible or semiflexible product; PA1 catalysts -- generally tertiary amines or potassium, tin or lead salts, which regulate the reaction rate; PA1 surfactants -- which affect the surface tension and regulate the formation of the foam; PA1 water which reacts with the isocyanate to produce carbon dioxide which acts as an expander; PA1 flame-retardants which regulate the behaviour of the foam with respect to fire; PA1 expanding agents, that is, low-boiling products which regulate the expansion of the foam; PA1 various additives such as fillers, dyes and pigments for various applications. PA1 continuous: the reactive polyurethane mixture is cast onto a conveyor belt, is restrained laterally, and is allowed to expand freely until the product has hardened; after curing, the product is trimmed and cut into sheets; PA1 discontinuous: the reactive mixture is poured into container tanks and is left to expand freely until a hard block of foam is formed; after curing it is trimmed and cut into sheets. PA1 continuous: the reactive mixture is cast onto various paper, metal or glass cloth coverings where it expands to fit the coverings, forming a covered rigid foam panel; the panel is then trimmed and cut to size; PA1 discontinuous: the reactive mixture is cast into moulds or presses in which the coverings are positioned and is left to expand until it fills them completely, adhering to the coverings and thus creating covered panels.
The polyol component and the isocyanate component are thermostatically controlled, metered, mixed and poured by means of suitable machines.
Various formulations of the polyol component are used to produce different types of rigid, flexible or semiflexible foams by various processes, some of which are described by way of example below.


An integrated circuit memory which includes a subcircuit for generating a programmable reference voltages on-chip from an external high-voltage supply line. Depending on the mode of operation (test, read, write, etc.), the reference voltage is changed.

The invention relates to the generation of several reference voltages in an integrated circuit, from an external voltage source and a voltage generation circuit. It can be applied especially to non-volatile memories.
Numerous integrated circuits require several reference voltages internally for low or high load current applications. In particular, non-volatile applications require multiple reference voltages for operations of reading, testing, programming or erasure. For example, to program a flash EPROM.sup.1 memory cell, it is necessary to have available a so-called programming voltage Vpp of (for example) 12 volts on the control gate of the cell, a bit line voltage of six volts applied to the drain of the cell, and a source voltage of zero volts. However, in test mode, the voltage applied to the drain of the cell will no longer be equal to six volts but will be equal to seven volts. It should therefore be possible to have both these reference voltages available. FNT .sup.1 Descriptions of flash EEPROMs may be found, for example, in Kuo et al., "A 512-kb Flash EEPROM Embedded in a 32-b Microcontroller," 27 IEEE J. SOLID-STATE CIRCUITS 574 (April 1992), and references cited therein; McConnell et al., "An Experimental 4-Mb Flash EEPROM with Sector Erase," 26 IEEE J. SOLID-STATE CIRCUITS 484ff (April 1991), and references cited therein; and Miyawaki et al., "A New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16-Mb/64-Mb Flash Memories," 27 IEEE J. SOLID-STATE CIRCUITS 583ff (April 1992), and references cited therein; all of which are hereby incorporated by reference.
This need to have numerous reference voltages is aggravated by the following factors:
1) It is desirable to avoid putting any unnecessary stress on the memory cells in operational mode, and hence it is desirable to apply to the cells, at all times, the optimum voltages corresponding to each access mode; and PA1 2) In order to obtain the advantages of on-chip-self-testing, it is desirable to have all the key elements located on-chip.
It is often not practicable to provide all these reference voltages at supply terminals of the circuit: the large number of external sources entailed would be a major drawback for the user and the large number of external supply terminals is a major drawback for the manufacturer because it increases the cost of the circuit. It is therefore desirable to find solutions internal to the circuit.
A known internal approach for low-current applications is the charge pump: starting from a nominal voltage, a higher voltage is obtained by multiplier effect. Apart from the fact that this approach is not suited to high current applications, it is also necessary to have as many charge pumps as there are internal reference voltages.
The invention proposed contains a device capable of delivering a predetermined voltage level from a choice of several possible voltage levels. In one improvement, the reference voltage delivered is stable and independent of the load current of the circuit to which it is applied. This device makes it possible to give a circuit all the reference voltages necessary, by logical selection. In the invention, resistor ratios are used to obtain different voltages. Transistors are used to set up a stable reference voltage at the output, as a function of a selected resistor ratio.
Among the innovations disclosed herein is: An integrated circuit, comprising: first and second power-supply connections; first, second, and third mutually matched field-effect transistors of a first channel conductivity type; at least one bias network, connected to provide three different constant bias voltages to the three respective gates of said transistors; said first transistor being operatively connected between said second transistor and said first power-supply connection; said second transistor, and a respective switch in series therewith, being operatively connected between said first transistor and said second power-supply connection; said third transistor, and a respective switch in series therewith, being operatively connected between said first transistor and said second power-supply connection; and logic connected to control both said switches, and to turn on no more than one thereof; whereby the potential intermediate said first and second transistors provides a reference voltage which is dependent on the state of said switches, but is otherwise substantially constant.
Among the innovations disclosed herein is: An integrated circuit, comprising: first and second power-supply connections; first, second, and third mutually matched field-effect transistors of a first channel conductivity type; at least one resistive bias network, connected to first and second power-supply connections, and configured to generate first, second, and third different respective constant bias voltages therefrom, and to provide said three bias voltages to gates of said three matched field-effect transistors; said first transistor having a source operatively connected to a first power-supply connection; said second transistor, and a respective switch in series therewith, being operatively connected, in series with said first transistor, between said first and second power-supply connections; said third transistor, and a respective switch in series therewith, also being operatively connected, in series with said first transistor, between said first and second power-supply connections; logic connected to control both said switches, and to turn on no more than one thereof; whereby the potential intermediate said first and second transistors provides a reference voltage which is dependent on the state of said switches, but is otherwise substantially constant.
Among the innovations disclosed herein is: An integrated circuit, comprising: first and second power-supply connections; first, second, and third mutually matched field-effect transistors of a first channel conductivity type; at least one bias network, connected to provide three different constant bias voltages to the three respective gates of said transistors; said first transistor having a source operatively connected to said first power-supply connection; said second transistor, and a respective switch in series therewith, being operatively connected, in series with said first transistor, between said first and second power-supply connections; said third transistor, and a respective switch in series therewith, also being operatively connected, in series with said first transistor, between said first and second power-supply connections; logic connected to control both said switches, and to turn on no more than one thereof; whereby the potential intermediate said first and second transistors provides a reference voltage which is dependent on the state of said switches, but is otherwise substantially constant.
Among the innovations disclosed herein is: An integrated circuit, comprising: a positive power-supply connection, and a ground connection; first, second, and third P-channel field-effect transistors, all having substantially identical geometries; at least one bias network, connected to provide three different constant bias voltages to the three respective gates of said transistors; said first transistor having a source operatively connected to said power-supply connection; said second transistor, and a respective switch in series therewith, being operatively connected, in series with said first transistor, between said power-supply connection and ground; at least one regulating transistor being interposed between said first and second matched transistors; said third transistor, and a respective switch in series therewith, also being operatively connected, in series with said first transistor, between said power-supply connection and ground; logic connected to control both said switches, and to turn on no more than one thereof; an N-channel output transistor connected to be controlled by a node intermediate between the channels of said first and second transistors, and accordingly to pass current from said power-supply connection to a load terminal; an additional series-connected pair of field-effect transistors, jointly connected in parallel with said output transistor, and including an additional P-channel transistor having a gate connected to the gate of said first matched transistor, and also an additional N-channel transistor having a gate connected to the gate of said regulating transistor; whereby the potential intermediate said first and second transistors provides a reference voltage which is dependent on the state of said switches, but is otherwise substantially constant.
Among the innovations disclosed herein is: A circuit for the generation of reference voltages, comprising: a first transistor placed between a positive voltage source and an output node, and having its gate biased at a first voltage; one second transistor and one third transistor connected in parallel, each being identical to said first transistor, each having its gate biased at a different respective voltage and being mounted in series with a respective switching transistor between said output node and ground; a sequence of resistors in series between the positive voltage source and the ground to deliver different bias voltages to the gates of said first, second, and transistors; logic connected and configured to make only one said switching transistor conductive at a time to generate a determined voltage level at the output of the generation stage.
Among the innovations disclosed herein is: A circuit for the generation of reference voltages according to claim 27, further having an output stage comprising: a fourth transistor capable of conducting a high current, controlled at its gate by the output of the generation stage and connected between the positive voltage source and an output of the device; a fifth transistor and a sixth transistor in series between the positive voltage source and the output of the device, the sixth transistor having a conduction electrode connected to its gate and another conduction electrode connected to the output of the device; a seventh transistor in series between the first transistor and the other transistors of the generation stage; the first transistor and the fifth transistor being identical and having their gates connected together, the sixth and seventh transistors being identical, having their gates connected together and being of the type with conduction opposite that of the first and fifth transistors.
Among the innovations disclosed herein is: An integrated circuit memory, comprising: an array of memory cells; and peripheral circuitry, including address decode logic connected to receive address bits and to access a correspondingly one of said cells; and control logic connected to receive one or more control bits and to select a mode of operation of said peripheral circuitry accordingly; reference-voltage-generating circuit, connected to receive an external voltage supply, and connected to receive bits from said control logic indicating a mode of operation, and to supply at least one reference voltage to said peripheral circuitry in dependence on said bits from said control logic; said reference-voltage-generating circuit comprising first, second, and third mutually matched field-effect transistors of a first channel conductivity type; at least one bias network, connected to provide three different constant bias voltages to the three respective gates of said transistors; said first transistor being operatively connected between said second transistor and said first power-supply connection; said second transistor, and a respective switch in series therewith, being operatively connected between said first transistor and said second power-supply connection; said third transistor, and a respective switch in series therewith, being operatively connected between said first transistor and said second power-supply connection; and logic connected to control both said switches, and to turn on no more than one thereof, in accordance with bits received from said control logic.
Among the innovations disclosed herein is: A method for generating multiple reference voltages on-chip from a single externally supplied voltage, comprising the steps of: providing first, second, and third mutually matched field-effect transistors of a first channel conductivity type; applying three different substantially constant bias voltages to the respective gates of said transistors from a voltage-dividing ladder between first and second power-supply connections; said first transistor being operatively connected between said second transistor and said first power-supply connection; selectably, when a first reference voltage is desired, connecting said second transistor, but not said third transistor, between said first transistor and said second power-supply connection; and selectably, when a second reference voltage is desired, connecting said third transistor, but not said second transistor, between said first transistor and said second power-supply connection; and connecting a node between said first and second transistors to provide a reference voltage which is substantially constant.

Dynamically switchable reference voltage generator


For a technique for maintaining consistency of data, one or more blocks of data identified by a first structure are copied to form a consistent set of data. While not acknowledging completion of write requests to any blocks of data, a second structure is created, wherein the second structure indicates which blocks of data are modified while the consistent set of data is being formed.

1. Field of the Invention
The present invention is directed to asynchronous copy in remote mirroring systems, such as peer to peer remote copy.
2. Description of the Related Art
Computing systems often include one or more host computers ("hosts") for processing data and running application programs, direct access storage devices (DASDs) for storing data, and a storage controller for controlling the transfer of data between the host computers and the DASD. Storage controllers, also referred to as control units or storage directors, manage access to a storage space comprised of numerous hard disk drives, otherwise referred to as a Direct Access Storage Device (DASD). Host computers may communicate Input/Output (I/O) requests to the storage space through the storage controller.
Some disaster recovery systems address data loss over a period of time, in which case writes to volumes on data storage may be lost. The writes may update data, write new data, or write the same data again. To assist in recovery of data writes, a copy of data may be provided at a remote location. Such copies may also be referred to as dual or shadow copies. International Business Machines Corporation (IBM), the assignee of the subject patent application, provides a remote mirroring system, including a PPRC Extended Distance service in an Enterprise Storage Server® (ESS) system. The PPRC Extended Distance service is described in IBM publication "Remote Copy: Administrator's Guide and Reference," IBM document no. SC35-0169-02 (IBM Copyright 1994, 1996), which publication is incorporated herein by reference in its entirety.
The PPRC Extended Distance service provides a technique for mirroring data in order to facilitate recovery after a system failure. Such data shadowing systems can also provide an additional remote copy for non-recovery purposes, such as local access at a remote site.
With the PPRC Extended Distance service, a primary storage subsystem maintains a copy of predefined datasets on a secondary storage subsystem. The copy may be used for disaster recovery. In particular, when an application program at a host computer submits writes for a volume at the primary storage subsystem, the PPRC Extended Distance service asynchronously transfers the writes to a secondary storage subsystem. The secondary storage subsystem updates the data in a corresponding volume.
PPRC Extended Distance service does not write to secondary storage subsystem before acknowledging the write to the primary storage subsystem. Instead, for the PPRC Extended Distance service, when a track is written, information is stored that indicates that the track is to be transferred to the secondary storage subsystem at a later time. An asynchronous process collects updates at the primary storage subsystem and sends the updates to the secondary storage subsystem.
In such mirroring systems, data is maintained in volume pairs. A volume pair is comprised of a volume in a primary storage device and a corresponding volume in a secondary storage device that includes a copy of the data maintained in the primary volume. Typically, the primary volume of the pair will be maintained in a primary direct access storage device (DASD) and the secondary volume of the pair is maintained in a secondary DASD shadowing the data on the primary DASD. A primary storage controller may be provided to control access to the primary DASD and a secondary storage controller may be provided to control access to the secondary DASD.
In many application programs, such as database systems, certain writes cannot occur unless a previous write occurred; otherwise the data integrity would be jeopardized. Such a data write whose integrity is dependent on the occurrence of a previous data writes is known as a dependent write. For instance, if a customer opens an account, deposits $400, and then withdraws $300, the withdrawal update to the system is dependent on the occurrence of the other writes, the opening of the account and the deposit. When such dependent transactions are copied from the primary volumes to secondary volumes, the transaction order must be maintained to maintain the integrity of the dependent write operation.
Volumes in the primary and secondary DASDs are consistent when all writes have been transferred in their logical order, i.e., all dependent writes transferred first before the writes dependent thereon. In the banking example, this means that the deposit is written to the secondary volume before the withdrawal. A consistency group is a collection of related volumes that need to be kept in a consistent state. A consistency transaction set is a collection of updates to the primary volumes such that dependent writes are secured in a consistent manner. Consistency groups maintain data consistency across volumes.
A consistency time is a time the system derives from the application system's time stamp to the data set. A consistency group has a consistency time for all data writes in a consistency group having a time stamp equal or earlier than the consistency time stamp. As long as the application program is writing data to the primary volume, the consistency time increases. However, if update activity ceases, then the consistency time does not change as there are no data sets with time stamps to provide a time reference for further consistency groups. If all the records in the consistency group are written to secondary volumes, then the reported consistency time reflects the latest time stamp of all records in the consistency group. Methods for maintaining the sequential consistency of data writes and forming consistency groups to maintain sequential consistency in the transfer of data between a primary DASD and secondary DASD are described in U.S. Pat. Nos. 5,615,329 and 5,504,861, which are assigned to IBM, the assignee of the subject patent application, and which are incorporated herein by reference in their entirety.
To form consistency groups among pairs of volumes participating in an asynchronous PPRC Extended Distance service, host computer Input/Output (I/O) to the primary volume is stopped in order to create a set of consistent updates. This usually requires host I/O to be quiesced, while a consistent set of updates forms on the secondary volume. Whenever host I/O is quiesced, there are detrimental effects for application program performance and availability on the host computer.
Thus, there is a need in the art for allowing the host computer application program to continue processing with minimal impact, while a consistent set of updates forms on the secondary volume.

Method, system, and program for asynchronous copy


A cable provider could offer a promotional feature, such as live pause of video, above and beyond a tier of service to which the customer subscribes, limiting the feature to being activated only upon occurrence of one or more events. In a network video delivery context, a set-top box plays live video, including an ability to pause live video upon the occurrence of an event. The system can detect an event, including an event unrelated to video, and prompt a user to pause. The system can include configuration settings enabling, for example, detection of various events, prompting the user to pause live video, and/or automatically pausing the live video. The system enables the user to play a time-shifted video corresponding to resuming the paused video playback. The system can include a Digital Video Recorder (DVR) local to the user, to facilitate the time-shifted video. The system is also compatible with a RS-DVR, where DVR functionality and time-shifted video is provided remotely from a head-end of a network video system. Additionally, the system is compatible with non-DVR network video delivery systems configured to provide live pause.

Field of the Invention
Embodiments relate generally to activating or enabling a feature, particularly a promotional feature, upon occurrence of a trigger event, including pausing live video, and more particularly to prompting a user to pause live video on the occurrence of an event.
Background Art
Service providers frequently offer customers additional features, above and beyond a tier of service to which the customer subscribes, for an additional fee. As selling such additional features is advantageous, it is often desirable for the service provider to effectively promote the feature to its customers. Alternatively, it may be desirable for a service provider to familiarize its customers to a new or existing feature they have, which is not widely known, appreciated or understood.
A common technique used by providers to promote features or services is a free preview. For example, a cable television provider might make a premium channel such as HBO or Showtime temporarily available to non-subscribers, in order to promote those services, and encourage customers to subscribe to them. This technique can be effective, but it has the downside of offering a very limited, and finite, period of time for customers to evaluate and consider the service. Furthermore, this technique works well for services such as broadcast linear television channels, where suddenly having many new customers using the services does not create any scaling issues. It is potentially problematic, however, if the services being promoted are on-demand services, where additional users create additional resource requirements. In this case, implementing a free preview period may require the service provider to build out expensive new infrastructure to support demand that is much higher than is required for normal operation. Alternatively, the free preview may create demand at a level that cannot be satisfied by existing infrastructure, creating a bad customer experience that undermines the promotional intent.
The conventional Digital Video Recorder, or DVR, is a one type of service that can be offered by multi-channel video providers, such as a cable providers. DVRs can provide a user/viewer with the ability to pause live video and/or audio, including live television, for example, using a specialized set-top box (STB) deployed at the user's home. DVR capability can also be implemented remotely from the user, for example at the headend of a network video system configured to provide video. This type of DVR is referred to herein as a remote storage DVR or RS-DVR system. In contrast to conventional DVR systems, which store programs locally, RS-DVR systems store video remotely from the user. One such network RS-DVR is described in U.S. patent application Ser. No. 12/055,795 ("the '795 application"), filed on Mar. 26, 2008, which is entitled "Digital Video Recording with Remote Storage." The '795 application is incorporated by reference in its entirety.
In conventional DVR and RS-DVR systems, a user must determine at what point it would be desirable to pause live video/audio/television. For example, a user may decide to manually pause live video when the user becomes aware of an event (e.g., doorbell chime, telephone ring). To decide, the user determines whether an event has occurred (if possible), and identifies details of the event (if possible) and whether the event merits the user's attention.
Accordingly, a user may reduce a volume level of live video, to enable the user to listen for an event, for example, resulting in self-imposed diminished enjoyment of live video. Even with such precautions, the user may suffer diminished enjoyment of the live video, due to preoccupation over whether an expected event will be missed while watching live video. The user may also be unable to identify details of an event that the user notices, forcing the user to guess at whether to pause live video based on incomplete information regarding the event. A user may pause live video for the purpose of determining additional details of the event, only to discover that the event does not merit attention or pausing of the live video. A user may place such priority on some types of events such that the user will always prefer to pause live video, and therefore desire the ability to configure a system to automatically pause upon the occurrence of such a high-priority event.
Additionally, users of non-DVR video systems, including non-DVR network video systems, typically do not have the option to pause live video. When an event occurs while viewing live video in a non-DVR video system, a user must determine whether to attend to the event and therefore become distracted from, or miss entirely, the live video.
Furthermore, users of DVR and non-DVR systems can become engrossed in live video and fail to become aware of an event that the user would otherwise be capable of perceiving. The user may enjoy live video at a volume level that masks the sound of an event, thereby rendering the event imperceptible to the user. The user may simply fail to perceive, or fail to become aware of, an event, for various reasons, while viewing live video.
What is needed is a more effective technique to promote features and services, including those related to DVR functionality, to consumers, avoiding the pitfalls of the above-described techniques.
The present embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numbers may indicate identical or functionally similar elements.

Feature activation on occurrence of an event


In plasma immersion ion implantation of a polysilicon gate, a hydride of the dopant is employed as a process gas to avoid etching the polysilicon gate, and sufficient argon gas is added to reduce added particle count to below 50 and to reduce plasma impedance fluctuations to 5% or less.

Plasma immersion ion implantation is performed by generating a plasma containing ions of species to be implanted in a semiconductor wafer or workpiece. The plasma may be generated using a plasma source such as a toroidal plasma source at the reactor chamber ceiling. Ion energy sufficient to achieve a desired ion implantation depth profile below the wafer surface is provided by coupling a very high RF bias voltage (e.g., 10 kV to 20 kV) to the semiconductor wafer through an insulated cathode electrode within the wafer support pedestal. High implant dose rate requires a high plasma ion density, which is achieved using a toroidal plasma source operating at a low chamber pressure. The requisite ion implant depth profile requires a very high ion energy, which is achieved by applying a very high RF bias voltage across the plasma sheath at the wafer surface. The process gas employed in plasma immersion ion implantation can be a fluoride or a hydride of the dopant species to be implanted.
In DRAM/flash memory fabrication, it is necessary to implant a semiconductor dopant species into the polycrystalline silicon (polysilicon) gate electrodes to increase their conductivity. The gate electrodes are formed by depositing amorphous silicon on a thin gate oxide layer and then annealing the wafer sufficiently to transform the deposited silicon from the amorphous state to a polycrystalline state. The polycrystalline silicon gate layer thus formed is about 50 nm to 80 nm thick. The implanted species is one that promotes p-type semiconductivity in silicon, such as boron, or n-type semiconductivity, such as arsenic, phosphorous or antimony. There is a need to avoid sputtering of the polycrystalline silicon gate material during the plasma immersion ion implantation. Specifically, it is desirable to minimize sputtering-induced reduction in the gate thickness to less than 10% of initial gate thickness (e.g., not more than a 5 nm to 8 nm loss in gate thickness) during the entire plasma immersion ion implantation process. The plasma immersion ion implantation process must be carried out for a sufficient time to attain a required ion implant dosage in the polysilicon gate layer, corresponding to an electrical resistivity in the range of 100-2000 Ohm/sq.
There is a further need to maintain a stable plasma to minimize plasma impedance fluctuations that would cause fluctuations in the delivered RF bias power or RF bias voltage across the plasma sheath and fluctuations in the delivered RF source power of the toroidal source. Otherwise, fluctuations in the delivered RF bias power will degrade control over ion implantation depth profile, while fluctuations in delivered RF source power will degrade control over ion implant dosage or dose rate. Currently, certain plasma immersion ion implantation processes experience frequent sporadic fluctuations in plasma impedance on the order of 100%. There is a need to reduce such fluctuations.
There is a need to reduce the deposition of solid particles on the wafer surface during plasma immersion ion implantation. Such particle deposition can occur due to (for example) accumulation of plasma by-products as a film on the chamber interior surfaces, such a film being liable to flaking from the sputtering action of the plasma. Currently, for example, certain plasma immersion ion implantation processes tend to accumulate between about 500 and 5000 particles of diameters of at least 0.12 microns on a 300 mm diameter wafer during ion implantation doping of polysilicon gates of flash memories. There is a need to reduce this particle deposition by an order of magnitude, e.g., to a range between about 5 and 50 particles of at least 0.12 microns.

Plasma immersion ion implantation process with reduced polysilicon gate loss and reduced particle deposition


A chucking device for mounting a tool on a machine tool is provided, having a mounting section for mounting the chucking device on the machine tool and a thermally expandable shrink section which comprises a holding section intended to receive the tool in shrink-fit relationship. A lead-in section is provided at the outer end of the shrink section, whose inner diameter is selected to ensure that the shank of the tool can be placed in the lead-in section and can be centered therein in a cold condition of the shrink section. A suitable rotatably driven mounting intended to receive the chucking device during clamping of the tool is provided, preferably in vertical arrangement, in order to ensure that the shank of the tool will slide into the holding section from above under the action of gravity.

The present invention relates to a chucking device for mounting a tool on a machine tool having a mounting section for mounting the chucking device on the machine tool and a thermally expandable shrink section which comprises a holding section intended to receive the tool in shrink-fit relationship.
The invention further relates to a device for the shrink-fit clamping of tools having rotatably driven mounting means adapted to receive such clamping device, and heating means for thermally expanding a shrink section of the chucking device.

Chucking device for mounting a tool on a machine tool and clamping device for the shrink-fit clamping of tools


In a method and apparatus for of balancing the phases of a plurality of amplifier modules so as to maximize the combined power output of the amplifier modules an amplifier module is selected as a reference module with a fixed phase in a first step. In a second and subsequent steps, the phase of each of the other amplifier modules is each adjusted relative to the reference module, such that the combined power output from the respective individual amplifier module and the reference module is minimized. Finally, the phase of the reference module is rotated by 180°.

This application claims the priority of German patent document No. 10 2004 006 070.3, filed Feb. 7, 2004, the disclosure of which is expressly incorporated by reference herein.
The invention relates to a method and apparatus phase balancing of amplifier modules.
When the power output of several parallel connected amplifier modules is to be combined (for example, in a Wilkinson adder), the phase of the amplifier control must be balanced beforehand, so that the total power output will be the sum of the individual outputs. Conventionally, this has been done by matching the phasing of the several amplifier modules with a reference amplifier module. Balancing is performed such that the amplifier modules were produced corresponding to a model (reference amplifier module). During the manufacturing, the output phases of the individual amplifier modules are substantially adapted by virtue of constructional methods.
One disadvantage of this method is that it requires increased balancing expenditures in the series production of components with several parallel connected amplifier modules. Another disadvantage is that phase errors (which occur, for example, because of temperature changes or aging) cannot be compensated.
It is therefore an object of the present invention to provide a phase balancing method that permits a simple phasing for several parallel connected amplifier modules.
Another object of the invention is to provide a circuit for implementing the method.
These and other objects and advantages are achieved by the method and apparatus according to the invention, in which an amplifier module is defined as a reference module with a fixed phase, in a first step. In a second and in subsequent steps, the phases of the other amplifier modules are adjusted in pairs relative to the reference module defined in the first step, such that the combined power output from the respective individual amplifier module and the reference module is minimized. In a last step, the phase of the reference module is shifted by 180°.
A circuit according to the invention for balancing the phases of a number of amplifier modules comprises a signal source which is assigned to each amplifier stage. Advantageously, a digital interface exists which is connected with the signal source.
One advantage of the method according to the invention is that phase matching of the amplifier modules to a separate model-type reference module is not required during the manufacturing. The amplifier modules can expediently be transmitter modules in an antenna system.
Another advantage is that phasing can be performed essentially automatically. In addition, the method according to the invention makes it possible to compensate for phase deviations which occur, for example, due to temperature changes or aging or the exchange of an amplifier module.
It is another advantage that the phase balancing can take place in the continuous operation of the amplifier modules.
It is still another advantage of the method according to the invention that the result of the phasing is independent of the reference module selected in the first process step.
In an advantageous embodiment of the invention, the other amplifier modules are switched off before a phase matching between the reference module and an amplifier module. As a result, an optimal matching of the phases between the two modules is achieved.
In another advantageous embodiment of the invention, the phase for each amplifier module is digitally generated and set. As a result, more precise phase values can be set in comparison to an analog generation. In addition, the phase values can be set significantly faster digitally, so that the entire phase balancing can take place more rapidly.
Advantageously, the phase value which minimizes the combined power output from the respective individual amplifier module and the reference module is stored. As a result, the phase values can again be written into the amplifier modules, at a new system start of the amplifier modules. The phase value can of course also be written into the signal source assigned to the amplifier stage.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.

Method and apparatus for phase balancing of amplifier modules


In one embodiment, an integral box comprises a base with walls, with plate(s) extending from a side wall(s). Opening(s) in the side wall(s) and/or the base allow wiring to pass into the box. This box is formed as a single, unitary component.

Wiring boxes for containing electrical connections are known. Wiring entering a wiring box is typically connected to a particular electrical fixture or receptacle such as a lighting fixture, outlet, or switch. Outlet boxes can be used in exposed-conduit wiring installations where they are exteriorly mounted to a wall, column or ceiling and exposed to various environmental conditions. Wiring boxes typically include a housing and two plates removably attached thereto. These boxes are not sealed and allow water and dirt entry. The housing includes ribs formed with the walls of the housing and plates that have openings along the edges for securely fastening the plates to the housing. The design requires many secondary processes to setup and secure the covering plates to the box.
The UL514A test, directed to electrical boxes and the integrity of the plate attachment to the housing, was used to test multiple part boxes that had a steel strip crimped to the box. The test was intended to ensure that the steel strip remained adhered to the box under various conditions. Although industry requirements dictates that the boxes pass UL514A, many commercial boxes that claim to meet the standard had a large percentage of boxes that failed.
Wiring boxes are often the subject of evaluation by organizations that promulgate standards in connection therewith and one of the standards includes that a wiring box should have a minimum resistance to the environmental forces that are typically applied to the wiring box. There remains a need for a box that is more resistant to increased environmental forces.

SIGMA ELECTRIC MANUFACTURING CORPORATION


A reading apparatus having a photo-detecting element array constituted by a plurality of photo-detecting element blocks each constituted by a plurality of photo-detecting elements, and having switching elements for transferring charges generated in the photo-detecting elements block by block to an output circuit, in which the output circuit has wirings having no crossing portions and the outputs of the photo-detecting elements can be produced as time-series signals without requiring any external memory. In the reading apparatus, the switching elements are selected block by block of the photo-detecting element array, the blocks are commonly connected so that the respective orders of adjacent two of the blocks in the output circuit are opposite to each other, and an output of the output circuit is selected by two selection circuits synchronized with the selection of the switching elements, the two selection circuits respectively having selection orders which are opposite to each other, whereby the selection circuits are switched block by block of the photo-detecting element array to thereby obtain a time-series output.

The present invention relates to a reading apparatus for use in a facsimile equipment, a scanner, or the like.
Conventionally, a thin film transistor (TFT) matrix-driven image sensor, known as a contact-type image sensor, is used in a reading apparatus.
The image sensor is configured such that image information of an original or the like that is projected on a photo-detecting element array of the image sensor generates charges in the photo-detecting elements. The charges are temporarily stored in capacitors associates with the photo-detecting elements and the stored charges are read out in time series by using TFT switches. An equivalent circuit of an example of the image sensor is shown in FIG. 8. Photo-detecting elements are grouped into m blocks so that n photo-detecting elements are assigned to each block. That is, photo-detecting elements P.sub.11 -P.sub.1n constitutes a first block, photo-detecting elements P.sub.21 -P.sub.2n constitutes a second block. The same rule applies correspondingly to the following blocks and, finally, photo-detecting elements P.sub.m1 -P.sub.mn constitutes an m-th block. The respective outputs of the photo-detecting elements are connected to the drains of corresponding TFTs which are used as switching elements, that is, T.sub.11 -T.sub.1n, T.sub.21 -T.sub.2n, . . . , T.sub.m1 -T.sub.mn. The respective sources of the TFTs are connected to common output lines S.sub.1, S.sub.2, . . . , S.sub.n respectively so that the sources of the TFTs having the same order in the respective blocks are connected to one and the same output line. The respective gates of the switching elements T.sub.11 -T.sub.1n, T.sub.21 -T.sub.2n, . . . , T.sub.m1 -T.sub.mn are connected to a gate pulse generation circuit 14 through common signal lines G.sub.1, G.sub.2, . . . , G.sub.m provided for every block. There exist inter-line capacities C.sub.1, C.sub.2, . . . , C.sub.n in the common output lines S.sub.1, S.sub.2, . . . , S.sub.n, and those capacities are respectively connected to the drains of corresponding selection switches SW.sub.1, SW.sub.2, . . . , SW.sub.n each constituted by an FET. The sources of the selection switches SW.sub.1, SW.sub.2, . . . , SW.sub.n are commonly connected to an output line COM, and the gates of those switches are connected to a selection pulse generation circuit 15.
The switching operation will now be described. Gate pulse generation circuit 14 operates to turn-on the switching elements of a block. The output signals on the common output line are successively selected by the reading signal of the selection pulse generation circuit 15 in synchronism with generation of a gate pulse. For example, first, a gate pulse is outputted from the gate pulse generation circuit 14 onto the signal line G.sub.1. As a result, the switching elements T.sub.11 -T.sub.1n of the first block are turned on, so that the respective outputs of the photo-detecting elements P.sub.11 -P.sub.1n are connected to the common output lines S.sub.1, S.sub.2, . . . , S.sub.n and stored in the line capacities C.sub.1, C.sub.2, . . . , C.sub.n. The selection switches SW.sub.1, SW.sub.2, . . . , SW.sub.n are successively turned-on by the reading signal of the selection pulse generation circuit 15 to thereby output the output signals stored in the line capacities C.sub.1, C.sub.2, . . . , C.sub.n, that is, the outputs of the first block, onto the output line COM as a time-series signal. Next, a gate pulse is outputted from the gate pulse generation circuit 14 onto the signal line G.sub.2 so that the switching elements T.sub.21 -T.sub.2n of the second block are turned on to thereby connect the outputs of the photo-detecting elements P.sub.21 -P.sub.2n to the common output lines S.sub.1, S.sub.2, . . . , S.sub.n respectively. Then selection switches SW.sub.1, SW.sub.2, . . . , SW.sub.n are successively turned-on on the basis of the reading signal of the selection pulse generation circuit 15 to thereby output the outputs of the second block onto the output line COM as a time-series signal. The same rule applies correspondingly to the following till the outputs of the m-th block are outputted onto the output line COM as a time-series signal. Thus, image information for one line of an original is read. While performing sub-scanning, the above operation is repeated till the image information of the whole original has been read as a time-series signal.
As described above, in the reading apparatus in which the output of the photo-detecting array is read in matrix, there is a problem in the wiring of the output circuit. As seen from FIG. 8, crossing portions are formed in the output lines of the respective sources of the switching elements T.sub.11 -T.sub.1n, T.sub.21 -T.sub.2n, . . . , T.sub.m1 -T.sub.mn and the common output lines S.sub.1, S.sub.2, . . . , S.sub.n. Although at the crossing portions an insulating layer is interposed between the output lines, there has been a problem in that crosstalk may be generated between the signal lines by electrostatic capacities formed at the crossing portions so that charges cannot be read correctly.
As the method of solving this problem, there has been proposed such means in which a ground layer is interposed at the crossing portions where output lines cross in matrix, as disclosed, for example, in Japanese Patent Unexamined Publication Nos. Sho-64-5057 and Sho-64-5173. In such a method, however, there has been the disadvantage of an increase in the electrostatic capacities of the wiring, thus reducing sensitivity. Further, there has been the disadvantage of remarkable unevenness in crossing portions, thus a high yield in the production process cannot be achieved.

Reading apparatus using two readout circuits connected in reverse order


A mobile device includes an originally downloaded mobile application. When a location of the mobile device is detected within a configured distance of a target enterprise store location, configuration data for the target enterprise's mobile application and services are obtained and automatically sent to the mobile device. The configuration data is applied to the original mobile application. When the user launches the original mobile application from the mobile device, the executing instance of the mobile application is transformed into the target enterprise's mobile application connected to the target enterprise's mobile application services server. The executing instance of the mobile application includes the branding, design, features, and workflow of the target enterprise's mobile application.

Mobile applications are prolific in the industry. Each consumer has many mobile applications on his/her phone. Many of these different applications perform the same or similar function, each are usually associated with a single business or entity. Each business supports its own unique interface, as a result consumer struggle with navigating the different interfaces when a mobile application is used and is unable to perform actions that the consumer desired to perform.
The numerous mobile applications also occupy a significant amount of storage space on the phone, which forces the consumer to remove applications from time to time in order to free up space for more important digital assets that the consumer does not want to delete. Consequently, the consumer may entirely forget about a business's application that the consumer once had, which is bad news for the business. Moreover, should the consumer subsequently redownload a previously deleted application, the previous saved customizations (including user identifier and password) are no longer available for use and must be re-entered by the consumer. By this point in time, the consumer may have forgotten the user identifier and password for the respective business. This is an inconvenience and most likely the consumer will re-delete the application before the consumer tries to figure out how to obtain the forgotten identifier and/or reset the forgotten password.
From the business's perspective, supporting mobile applications is a business necessity, but it is not usually within the core competency of the business. So, the business either hires technical staff to develop and support its mobile services or the business outsources its mobile services to a third-party provider. In either case, the business experiences substantial expenses and must continually update its mobile services for a variety of changing business conditions.

Location-based mobile application processing


Until a face detection result is obtained after a moving-image recording operation starts, a focal-point detection area may be set at a position based on a face detection result before the moving-image recording operation. The focal-point detection area may be set so as to fit within the angle of view after the moving-image recording operation.

1. Field of the Invention
The present invention relates to imaging apparatuses having a focus adjustment function such as an electronic still camera and a camcorder and imaging methods therefor.
2. Description of the Related Art
Conventionally, a technology has been known which detects a main subject from a captured screen. For example, a face identified from a feature of the eye or mouth of a human figure or an object identified from its color or luminance level may be detected as a main subject. In this case, the position and size of the main subject may often be output as a detection result.
Another technology has been known which handles a subject at a position touched and designated by a photographer on a touch panel as a main subject. Another technology has been known which handles a subject identified by a photographer by manipulating an operating member such as a four-way operational switch to move an instruction cursor displayed on an image-capturing standby screen as a main subject. The thus detected main subject is used as a target for focusing an imaging lens.
On the other hand, for an autofocus (hereinafter, called AF) function used in an electronic still camera or a camcorder, for example, a method has been used in which a lens position where a high-frequency component of a luminance level signal acquired from an image pick-up device such as a CCD is at a maximum is defined as an in-focus position. In this case, a method has been known in which a main subject detected in the manner as described above is defined as a ranging target area (hereinafter, called a focal-point detection area or an AF frame).
Japanese Patent Laid-Open No. 2004-205885 discloses that the center of a position in an image-capturing range designated by a user is defined as a focal-point detection area.
When still images and moving images are both captured with one camera, control may be switched between optimum modes of an image pick-up device for a still image capturing operation, a moving image capturing operation and an image-capturing standby state. However, when a moving image capturing operation is performed without changing a focal-point detection area set in a moving image-capturing standby state, the focal-point detection area may not possibly be set accurately at a subject position set in the moving image-capturing standby state.
This is caused because the number of pixels readout by the image pick-up device differs in a moving image-capturing standby state and a moving image capturing operation and thus the aspect ratio of the screen may differ.
Furthermore, when a face detected by a camera is to be defined as a main subject, it takes time after switching the control of the image pick-up device until a face detection result is output. Therefore, a face detection result is not acquired immediately after a moving image capturing operation starts, and a focal-point detection area may not possibly be set.


Attribute mapping information is stored, in which a superclass of an associated class in an integration-source ontology already associated with an integration-destination ontology, an attribute of the superclass, and an integration destination attribute of a class in the integration destination are associated with each other. An integration target class in the integration source is specified to acquire an attribute of a superclass of the integration target class. An associated class having the shortest distance from the integration target class is specified, to specify an integration-destination-associated class associated with the specified associated class. An inheritance relation is followed from the integration-destination-associated class to specify a class having the integration destination attribute corresponding to the attribute in the mapping information as a position where the class associated with the integration target class is present.

1. Field of the Invention
The present invention relates to an ontology-integration-position specifying apparatus, an ontology-integration supporting method, and a computer program product that support association between classes included in an integration-source ontology and classes included in an integration-destination ontology.
2. Description of the Related Art
In recent years, the ontology in which knowledge or a concept is systematically classified and described has been used in many industries. In a general ontology, knowledge or a concept is expressed as a class hierarchy in which an attribute (property) of a superclass is inherited by a subclass. Superclass-subclass relationships are transitive. For example, when class A is a superclass of class B, and class B is a superclass of class C, class A is a superclass of class C. On the other way around, when class C is a subclass of class B, and class B is a subclass of class A, class C is a subclass of class A. Each class in the class hierarchy is associated with data (or a group of data pieces) which is described according to the attribute of the pertinent class. The associated data (or the group of data pieces) is called an "instance" of the class or the class hierarchy.
One distinguished characteristic of the class hierarchy is that the instances held by the subclasses can be viewed from the superclasses. This is because the subclass inherits the attribute of the superclass. Further, when the instance held by the subclass is viewed from the superclass, only values corresponding to the attributes held by the superclass can be viewed.
One technique that systematically represents vocabularies and knowledge present on a web and relations therebetween is the Web Ontology Language (OWL). The OWL, which is recommended by the World Wide Web Consortium (W3C), is designed to express a classification system of deducible vocabularies based on a collection of Subject, Predicate, and Object triplets of Resource Description Framework (RDF). An ontology is also used as a data model in various areas in industries, for example, in the PLIB (ISO 13584/Parts Library), which provides an international standard for industrial data.
When the concept and the instances thereof are managed by the ontology, a plurality of ontologies sometimes needs to be integrated. For example, when a merger of a companies or unification and reorganization of departments occurs, the ontologies managed in each company or each department need to be integrated and the instances need to be managed in an integrated manner.
In some cases, it may be desirable to reuse one of the existing ontologies, rather than constructing a brand-new ontology. When one existing ontology (hereinafter also referred to as integration-destination ontology) is to be reused, classes of the other existing ontology (hereinafter also referred to as integration-source ontology) may be added to the class hierarchy of the reused, existing ontology, or the existing class hierarchy may be expanded, so that the classes are properly allocated. Thus, the instances stored in the integration-source ontology can be integrated into the integration-destination ontology and managed by the integration-destination ontology.
As a technique for integrating the ontologies, various techniques have been proposed. For example, a technique described in JP-A 2001-14166 (KOKAI) is intended to compare and analyze attributes of classes of respective ontologies, find similarity between the classes, and associates the classes with each other when the classes that belong to different ontologies have a high degree of similarity. Such a technique facilitates the integration of ontologies by clarifying the correspondence between the classes in the ontologies.
The technique disclosed in JP-A 2001-14166 (KOKAI), however, does not take into consideration the granularity of the attributes held by the classes of the integration-source ontology and the integration-destination ontology. When the corresponding classes of the two ontologies have attributes with different granularities, the association of the classes and the attributes cannot be performed properly.
The granularity of the attribute is a measure of a scope encompassed by the attribute. For example, if a generic attribute "height" of the integration-source ontology is associated with a specific attribute such as "height in lying position" or "height in upright position" of the integration-destination ontology, there is a certain difference in the scopes encompassed by the respective attributes.
When the attribute of a class included in the integration-source ontology and the attribute of a class included in the integration-destination ontology are different in granularity, one attribute of one ontology comes to be associated with plural attributes of the other ontology. When two ontologies have many attributes with different granularities, a significantly large number of attributes of one ontology end up being associated with one attribute of the other ontology. When an attribute of one ontology can be associated with plural attributes of the other ontology, it is difficult to automatically choose one proper, corresponding attribute. Then, the automatic determination of a corresponding attribute is obstructed.

This patent is subject to a terminal disclaimer.

Ontology-integration-position specifying apparatus, ontology-integration supporting method, and computer program product


The invention relates to a system and a method for the hot-dip galvanization of components, preferably for mass-production hot-dip galvanization of a plurality of identical or similar components, in particular in batches, preferably for batch galvanization.

The present invention relates to the technical field of the galvanization of iron-based and/or iron-containing components, in particular steel-based and/or steel-containing components (steel components), preferably for the automobile and/or automotive industry, by means of hot dip galvanization.
In particular, the present invention relates to a system and also a method for hot dip galvanizing of components (i.e., of iron-based and/or iron-containing components, steel-based and/or steel-containing components (steel components)), in particular for the large-scale (high-volume) hot dip galvanizing of a multiplicity of identical or similar components (e.g., automotive components), in discontinuous operation (referred to as batch galvanizing).
Metallic components of any kind consisting of iron-containing material, and in particular components made of steel, often require application-related an efficient protection against corrosion. In particular, components consiting of steel for motor vehicles (automotive), such as for example automobiles, trucks, utility vehicles and so on, require efficient protection against corrosion that withstands even long-term exposures.
In this connection it is known practice to protect steel-based components against corrosion by means of galvanizing (zinc coating). In galvanizing, the steel is provided with a generally thin zinc coat in order to protect the steel against corrosion. There are various galvanizing methods that can be used to galvanize components consisting of steel, in other words to coat them with a metallic covering of zinc, including in particular the methods of hot dip galvanizing, zinc spraying (flame spraying with zinc wire), diffusion galvanizing (Sherardizing), electrogalvanizing (electrolytic galvanizing), nonelectrolytic galvanization by means of zinc flake coatings, and also mechanical zinc coating. There are great differences between the aforesaid galvanizing methods, in particular with regard to their implementation, but also to the nature and properties of the zinc layers and/or zinc coatings produced.
Probably the most important method for corrosion protection of steel by means of metallic zinc coatings is that of hot dip galvanizing. Thereby steel is immersed continuously (e.g. coil and wire) or piecemeal (e.g. components) in a heated tank comprising liquid zinc at temperatures from around 450° C. to 600° C. (melting point of zinc: 419.5° C.), thus forming on the steel surface a resistant alloy layer of iron and zinc and, over that, a very firmly adhering pure zinc layer.
In the context of hot dip galvanizing, a distinction is made between discontinuous batch galvanizing (cf., e.g. DIN EN ISO 1461) and continuous strip galvanizing (DIN EN 10143 and DIN EN 10346). Both batch galvanizing and strip galvanizing are normalized and/or standardized processes. Strip-galvanized steel is a precursor and/or intermediate (semifinished product) which, after having been galvanized, is processed further by means in particular of forming, punching, trimming, etc., whereas components to be protected by batch galvanizing are first fully manufactured and only therafter subjected to hot dip galvanizing (thus providing the components with all-round corrosion protection). Batch galvanizing and strip galvanizing also differ in terms of the thickness of the zinc layer, resulting in different durations of protection. The zinc layer thickness on strip-galvanized sheets is usually not more than 20 to 25 micrometers, whereas the zinc layer thicknesses of batch-galvanized steel parts are customarily in the range from 50 to 200 micrometers and even more.
Hot dip galvanizing affords both active and passive corrosion protection. The passive protection is through the barrier effect of the zinc coating. The active corrosion protection occurs due to the cathodic activity of the zinc coating. Relative to more noble metal of the electrochemical series, such as for example iron, zinc serves as a sacrificial anode, protecting the underlying iron from corrosion until the zinc itself is corroded entirely.
The so-called batch galvanizing according to DIN EN ISO 1461 is used for the hot dip galvanizing of usually relatively large steel components and constructions. Thereby steel-based blanks or completed workpieces (components) being pretreated and then immersed into the zinc melt bath. The immersion allows, in particular, even internal faces, welds, and difficult-to-access locations on the components or workpieces for galvanizing to be easily reached.
Conventional hot dip galvanizing is based in particular on the dipping of iron and/or steel components into a zinc melt to form a zinc coating or zinc covering on the surface of the components. In order to ensure the adhesiveness, the imperviosity, and the unitary nature of the zinc coating, there is generally a requirement beforehand for thorough surface preparation of the components to be galvanized, customarily comprising a degrease with subsequent rinsing operation, a subsequent acidic pickling with downstream rinsing process, and, finally, a flux treatment (i.e. so-called fluxing), with a subsequent drying operation.
The typical process sequence of conventional batch galvanizing by hot dip galvanization customarily takes the following form: in the case of batch galvanizing of identical or similar components (e.g. series production of automotive components), for reasons of process economy and economics, they are typically collated and/or grouped for the entire procedure (this being done in particular by means of a common goods carrier, configured for example as a crossbeam or rack, or of a common mounting and/or attachment device for a multiplicity of these identical and/or similar components). For this purpose, a plurality of components is attached on the goods carrier via holding means, such as for example slings, tie wires or the like. The components in the grouped state are subsequently supplied via the article carrier to the subsequent treatment steps and/or stages.
First of all, the component surfaces of the grouped components are subjected to degreasing, in order to remove residues of greases and oils, wherein degreasing agents in the form, customarily, of aqueous alkaline or acidic degreasing agents are employed. Cleaning in the degreasing bath is followed customarily by a rinsing operation, typically by immersion into a water bath, in order to prevent degreasing agents being entrained with the galvanization material into the next operational step of pickling, this being especially important in the case of the switch from alkaline degreasing to an acidic base.
The next step is that of pickle treatment (pickling), which serves in particular to remove homologous impurities, such as for example rust and scale from the steel surface. Pickling is customarily accomplished in dilute hydrochloric acid, with the duration of the pickling procedure being dependent on factors including the contamination status (e.g. degree of rusting) of the galvanization material, and on the acid concentration and temperature of the pickling bath. In order to prevent and/or minimize entrainments of residual acid and/or residual salt with the galvanization material, the pickling treatment is customarily followed by a rinsing operation (rinse step).
This is followed by what is called fluxing (treatment with flux), in which the previously degreased and pickled steel surface with what is called a flux, typically comprising an aqueous solution of inorganic chlorides, most frequently with a mixture of zinc chloride (ZnCl2) and ammonium chloride (NH4Cl). On the one hand, the task of the flux is to carry out a final intensive fine-purification of the steel surface prior to the reaction of the steel surface with the molten zinc, and to dissolve the oxide skin on the zinc surface, and also to prevent renewed oxidation of the steel surface prior to the galvanizing procedure. On the other hand, the flux raises the wetting capacity between the steel surface and the molten zinc. The flux treatment is customarily followed by a drying operation in order to generate a solid film of flux on the steel surface and to remove adhering water, thus avoiding subsequently unwanted reactions (especially the formation of steam) in the liquid zinc dipping bath.
The components pretreated in the manner indicated above are then subjected to hot dip galvanizing by being immersed into the liquid zinc melt. In the case of hot dip galvanizing with pure zinc, the zinc content of the melt according to DIN EN ISO 1461 is at least 98.0 wt %. After the galvanization material has been immersed into the molten zinc, it remains in the zinc melting bath for a sufficient time period, in particular until the galvanization material has assumed its temperature and is coated with a zinc layer. The surface of the zinc melt is typically cleaned to remove, in particular, oxides, zinc ash, flux residues and the like, before the galvanization material is then extracted from the zinc melt again. The component hot dip galvanized in this way is then subjected to a cooling process (e.g. in the air or in a water bath). Lastly, the holding means for the component, such as for example slings, tie wires or the like, are removed. Subsequent to the galvanizing operation, there is customarily a reworking or aftertreatment operation, which in some cases is involved. Here excess zinc residues, particularly what are called drip edges and streaks of the zinc solidifying on the edges, and also oxide or ash residues adhering to the component, are removed as far as possible.
One criterion of the quality of hot dip galvanization is the thickness of the zinc coating in μm (micrometers). The standard DIN EN ISO 1461 specifies the minimum values of the requisite coating thicknesses to be afforded, depending on thickness of material, in batch galvanizing. In actual practice, the coat thicknesses are well above the minimum coat thicknesses specified in DIN EN ISO 1461. Generally speaking, zinc coatings produced by batch galvanizing have a thickness in the range from 50 to 200 micrometers or even more.
In the galvanizing process, as a consequence of mutual diffusion between the liquid zinc and the steel surface, a coating of iron/zinc alloy layers with differing compositions is formed on the steel part. On withdrawal of the hot dip galvanized articles, a layer of zinc—also referred to as pure zinc layer—remains adhering to the uppermost alloy layer, this layer of zinc having a composition corresponding to that of the zinc melt. On account of the high temperatures associated with the hot dipping, a relatively brittle layer is formed initially on the steel surface, this layer being based on an alloy (mixed crystals) between iron and zinc, with the pure zinc layer only being formed atop that layer. While the relatively brittle iron/zinc alloy layer does improve the strength of adhesion to the base material, it also hinders the formability of the galvanized steel. Greater amounts of silicon in the steel, of the kind used in particular for the so-called calming of the steel during its production, result in increased reactivity between the zinc melt and the base material and, consequently, in strong growth of the iron/zinc alloy layer. In this way, relatively high overall layer thicknesses are formed. While this does enable a very long period of corrosion protection, it nevertheless also raises the risk, in line with increasing thickness of the zinc layer, that the layer will flake off under mechanical exposure, particularly sudden, local exposures, thereby destroying the corrosion protection effect.
In order to counteract the above-outlined problem of the incidence of the rapidly growing, brittle and thick iron/zinc alloy layer, and also to enable relatively low layer thicknesses in conjunction with high corrosion protection in the case of galvanizing, it is known practice from the prior art additionally to add aluminum to the zinc melt or to the liquid zinc bath. For example, by adding 5 wt % of aluminum to a liquid zinc melt, a zinc/aluminum alloy is produced that has a melting temperature lower than that of pure zinc. By using a zinc/aluminum melt (Zn/Al melt) and/or a liquid zinc/aluminum bath (Zn/Al bath), on the one hand it is possible to realize much lower layer thicknesses for reliable corrosion protection (generally of below 50 micrometers); on the other hand, the brittle iron/tin alloy layer is not formed, because the aluminum—without being tied to any particular theory—initially forms, so to speak, a barrier layer on the steel surface of the component in question, with the actual zinc layer then being deposited on this barrier layer. Components hot dip galvanized with a zinc/aluminum melt are therefore readily formable, but nevertheless—in spite of the significantly lower layer thickness by comparison with conventional hot dip galvanizing with a quasi-aluminum-free zinc melt—exhibit improved corrosion protection qualities. Relative to pure zinc, a zinc/aluminum alloy used in the hot dip galvanizing bath exhibits enhanced fluidity qualities. Moreover, zinc coatings produced by hot dip galvanizing carried out using such zinc/aluminum alloys have a greater corrosion resistance (from two to six times better than that of pure zinc), enhanced shapability, and improved coatability relative to zinc coatings formed from pure zinc. This technology, moreover, can also be used to produce lead-free zinc coatings.
A hot dip galvanizing method of this kind using a zinc/aluminum melt and/or using a zinc/aluminum hot dip galvanizing bath is for example known from WO 2002/042512 A1 and the relevant equivalent publications to this patent family (e.g., EP 1 352 100 B1, DE 601 24 767 T2 and US 2003/0219543 A1). Also disclosed therein, are suitable fluxes for the hot dip galvanizing by means of zinc/aluminum melt baths, since flux compositions for zinc/aluminum hot dip galvanizing baths are different to those for conventional hot dip galvanizing with pure zinc. With the method disclosed therein it is possible to generate corrosion protection coatings having very low layer thicknesses (generally well below 50 micrometers and typically in the range from 2 to 20 micrometers) and having very low weight in conjunction with high cost-effectiveness, and accordingly the method described therein is employed commercially under the designation of microZINQ® process.
In the batch hot dip galvanizing of components in zinc/aluminum melt baths, in particular in the case of large-scale batch hot dip galvanizing of a multiplicity of identical or similar components (e.g., large-scale batch hot dip galvanizing of automotive components and/or in the automobile industry), because of the more difficult wettability of the steel with the zinc/aluminum melt and also the low thickness of the zinc coverings and/or zinc coatings, there is a problem with always subjecting the identical and/or similar components to identical operating conditions and operating sequences in an economic process sequence, in particular with implementing high-precision hot dip galvanizing reliably and reproducibly in a manner which affords identical dimensional integrities for all identical or similar components. In the prior art—as well as by costly and inconvenient pretreatment, especially with selection of specific fluxes—this is typically accomplished in particular by special process control during the galvanizing procedure, such as, for example, extended immersion times of the components into the zinc/aluminum melt, since only in this way it is ensured that there are no defects in the relatively thin zinc coatings, or no uncoated or incompletely coated regions.
In order to make the processing sequence economical for the known hot dip galvanizing of identical and/or similar components, more particularly in the case of large-scale batch hot dip galvanizing, and to ensure an identical process sequence, the prior art collates or groups a multiplicity of the identical or similar components for galvanizing, on a common goods carrier or the like, for example, and guides them in the grouped state through the individual process stages, and especially the galvanizing bath.
The known piece hot dip galvanizing, however, has various disadvantages. If the articles on the goods carrier are hung in two or more layers, and especially if the immersion movement of the goods carrier is the same as the emersion movement, the components and/or regions of components inevitably do not spend the same time in the zinc melt. This results in different reaction times between the material of the components and of the zinc melt, and, consequently, in different zinc layer thicknesses on the components. Furthermore, in the case of components with high temperature sensitivity, in particular in the case of high-strength and ultra high-strength steels, such as for example spring steels, chassis and bodywork components, and press-hardened forming parts, differences in residence times in the zinc melt affect the mechanical characteristics of the steel. With a view to ensuring defined characteristics on the part of the components, it is vital that defined operating parameters are observed for each individual component.
Furthermore, on withdrawal of the components from the zinc melt, it is inevitable that the zinc will run and will drip from edges and angles of the components. This produces zinc bumps on the component. Eliminating these zinc bumps subsequently, which is normally a manual task, represents a considerable cost factor, particularly if the piece numbers being galvanized are high and/or if the tolerance requirements to be observed are exacting. With a fully laden goods carrier, it is generally not possible to reach all of the components and there individually remove the zinc bumps directly at the site of galvanizing. Customarily, after galvanizing, the galvanized components have to be taken off from the goods carrier, and must be manually examined and worked on individually, in a very costly and inconvenient operation.
Moreover, in the case of the known batch hot dip galvanizing, the immersion and emersion movement of the goods carrier into and out of the galvanizing bath takes place at the same location. The process-related occurrence of zinc ash, as a reaction product of the flux and the zinc melt, after the immersion of the components, this ash accumulating on the surface of the zinc bath, makes it absolutely necessary, before emersion, for the zinc ash to be removed from the surface by drawing off or washing away, in order to prevent it adhering to the galvanized components on withdrawal, to create as little contamination as possible on the galvanized component. In view of the large number of components in the zinc bath and in view of the comparatively poor accessibility of the surface of the galvanizing bath, removing the zinc ash from the bath surface proves generally to be a very costly and inconvenient, and in some cases problematical, operation. On the one hand, there is a delay to the operation with a reduction in productivity at the same time within the removal of the zinc ash from the surface of the galvanizing bath and, on the other hand, there is a source of defects in relation to the quality of galvanization of the individual components.
Ultimately, with the known piece hot dip galvanizing, contaminants and zinc bumps remain on the galvanized components and must be removed by manual afterwork. This afterwork is generally very costly and time-consuming. In this regard it should be noted that afterwork here refers not only to the cleaning and/or remediation, but also, in particular, to the visible inspection. For process-related reasons, all of the components are subject to a risk of contaminants adhering or zinc bumps being present, and requiring removal. Accordingly, all of the components must be looked at individually. This inspection alone, without any subsequent steps of work that may be necessary, represents a very high cost factor, in particular in the large-scale production sector with a very large number of components to be inspected and with very high quality requirements.

Hot-dip galvanization system and hot-dip galvanization method


To satisfactorily detect an edge detection signal of a high frequency band from a captured image signal at all times.

General cameras (imaging devices) include viewfinders (display devices) for checking the composition and focus of captured images in real time. It is required with respect to captured images displayed on viewfinders to fully reproduce the angles of view and resolution of the images depending on purposes thereof. However, there are many cases, for example, in which viewfinders with HD resolution or the like which is lower than the resolution of captured images are used in high-resolution imaging devices (e.g., 4K cameras) for the reason of convenience in handling and installation.
The present applicant has proposed a technology for displaying edge information of a high-resolution image on a low-resolution display device before (refer to Patent Literature 1). This technology intends to enable focusing to be checked from edge information of a higher frequency band than a Nyquist frequency of low resolution by down-converting high frequency edge information, which is obtained by performing a filtering process on a high-resolution image, and displaying the edge information on the low-resolution display device.

Abstract: A filtering unit extracts an edge detection signal of a high frequency band from an image signal obtained from imaging, and a band control unit controls the high frequency band on the basis of lens information. For example, the filtering unit includes a first high-pass filter with a first cutoff frequency, a second high-pass filter with a second cutoff frequency that is lower than the first cutoff frequency, and an α blending unit that performs α blending on output of the first high-pass filter and output of the second high-pass filter. Even if the frequency of the edge detection signal included in the captured image signal varies due to a change in a zoom position, a lens model number, an F value or the like, the edge detection signal can be satisfactorily detected at all times.


The invention relates to the use of a deodorizer including undecylenic acid or a salt or an alkyl or polyoxyalkylenic ester or undecylenic acid to deodorize papers, cardboards and nonwovens. The invention also relates to papers, cardboards and nonwovens containing the above mentioned deodorizer.

Compositions based on undecylenic acid ester which are capable of attenuating certain undesirable odors are already known in the field of deodorization.
Thus, DE-A-2,263,509 proposes a complex deodorizing composition comprising a (C.sub.1 -C.sub.4) alkyl ester of undecylenic acid to prevent the development of the micro-organisms responsible for body odor in man.
DE-A-1,792,467 describes a composition intended to repel wild game which damage crops, based on undecylenic acid optionally combined, inter alia, with unsaturated fatty acid esters such as methyl undecylenate.
It is also known to use compositions based on undecylenic acid ester to deodorize the sludges of purification plants, liquid manures, animal feeds and paper industry effluents (see FR 2,655,856, FR 2,655,857, FR 2,655,819 and FR 2,694,197).
As regards supports of cellulosic nature, there is a great need to deodorize them either because they have a pronounced specific odor or because they are intended to come into contact with unpleasant-smelling products.
The need for deodorization in the sense defined above is evident in the case of packaging cardboards and papers before or after printing, the intrinsic odors of which is disagreeable. This need is also seen when it is desired to use papers or nonwovens as deodorizer support, in particular to filter gases (air conditioning, industrial environment), liquids or particles (vacuum cleaner bags), to collect human excrement (nappies) or animal excrement (litter) or alternatively to act in a confined atmosphere (air-freshener diffusers).

Use of a deodorizer based on undecylenic acid or on derivatives of the said acid to deodorize papers, cardboards and nonwovens


Systems and apparatus providing a carrier head for chemical mechanical polishing are described. The carrier head includes a base, a support structure attached to the base, a retaining structure attached to the base, and a connector attached to the base and the retaining structure. The support structure includes a receiving surface for contacting a substrate. The retaining structure prevents the substrate from moving along the receiving surface. The base and the retaining structure can thermally expand at different rates of expansion without causing distortion to one another.

An integrated circuit is typically formed on a substrate by the sequential deposition of conductive, semiconductive or insulative layers on a silicon substrate. One fabrication step involves depositing a filler layer over a non-planar surface, and planarizing the filler layer until the non-planar surface is exposed. For example, a conductive filler layer can be deposited on a patterned insulative layer to fill trenches or holes formed in the insulative layer. The filler layer is then planarized until the raised pattern of the insulative layer is exposed. After planarization, the portions of the conductive layer remaining between the raised pattern of the insulative layer form vias, plugs and lines that provide conductive paths between thin film circuits on the substrate.
Planarization can also be used to provide a planar layer surface for photolithography. For example, an etching step used in manufacturing integrated circuits can include depositing a photo-resist layer on an exposed surface of the substrate, and then selectively removing portions of the resist layer by a photolithographic process to provide the etch pattern on the layer. If the layer is non-planar, then photolithographic techniques of patterning the resist layer may not be suitable because the surface of the substrate may be sufficiently non-planar to prevent focusing of the photographic apparatus on the entire layer surface. The substrate surface may therefore need to be periodically planarized to restore a planar layer surface of the photolithography.
Chemical mechanical polishing (CMP) is one accepted method of planarization. This planarization method typically requires that the substrate be mounted on a carrier or polishing head of a CMP apparatus. The exposed surface of the substrate is placed against a rotating polishing disk pad or belt pad. The polishing pad can be either a "standard" pad or a fixed-abrasive pad. A standard pad has a durable roughened surface, whereas a fixed-abrasive pad has abrasive particles held in a containment media. A polishing slurry, including at least one chemically-reactive agent, and abrasive particles if a standard pad is used, is supplied to the surface of the polishing pad.

Carrier head for thermal drift compensation