A method of manufacturing a semiconductor device having the steps of: forming a plurality of gate electrodes on a semiconductor substrate; forming an insulating film on every second gate electrode of the plurality of gate electrodes; coating resist on the whole surface of the semiconductor device to form a first resist film; patterning the first resist film and removing a predetermined area to form a second resist film, the end face of the second resist film being aligned with the surface of the gate electrode without the insulating film; implanting impurity ions, using the second resist film as a mask, at an acceleration voltage allowing to stop the implanted ions near to the surface of the semiconductor substrate under the gate electrode with the insulating film, of those gate electrodes not covered with the second resist film; removing the second resist film and coating resist on the whole surface of the semiconductor device to form a third resist film; patterning the third resist film and removing a predetermined area to form a fourth resist film, the end face of the fourth resist film being aligned with the surface of the gate electrode with the insulating film; and implanting the impurity ions, using the fourth resist film as a mask, at an acceleration voltage allowing to stop the implanted impurity ions near at the surface of the semiconductor substrate under the gate electrode without the insulating film among the gate electrodes not covered with the fourth resist film.

The present invention relates to a method of manufacturing semiconductor devices particularly suitable for manufacturing mask ROMs.
A conventional method of manufacturing mask ROMs is described, for example, in the technique disclosed in Japanese Patent Laid-Open Publication No. 1-158734. This technique will be explained with reference to FIG. 6 showing cross sections of a mask ROM at each manufacturing step. As shown in FIG. 6(a), a silicon oxide film 602 having a thickness of 200 angstroms is formed on the surface of a semiconductor substrate 601 by means of thermal oxidization under an atmosphere of oxygen containing hydrochloric acid at 900.degree. C. Polysilicon is deposited on the silicon oxide film 602 to a film thickness of 4000 angstroms by means of a low pressure chemical vapor deposition (LPCVD) method. Phosphors are thermally diffused into the formed polysilicon film 603 under a phosphoryl chloride (POCl.sub.3) atmosphere. A silicon oxide film 604 is formed on the surface of the device by means of a CVD method. Resist is coated on the surface of the silicon oxide film 604 to form a resist film 605 patterned so as to cover every second gate electrode area.
Using the resist film 605 as a mask, the silicon oxide film 604 is etched by a reactive ion etching method to form a gate oxide film 604a such as shown in FIG. 6(b). The resist film 605 is removed, and resist is again coated and patterned to form a resist film 606 at the area where the gate oxide film 604 is not present.
Next, reactive ion etching is performed with a high selective etching ratio providing an etching speed of the polysilicon film 603 sufficiently faster than that of the gate oxide film 604. As a result, the polysilicon film 603 is etched at the narrow area where the resist film 606 and silicon oxide film 604a are not present. By removing the resist film 606, gate electrodes 603a with a small clearance space therebetween are formed such as shown in FIG. 6(c).
Another conventional method has been used heretofore. This method can reduce a variation of clearances between gate electrodes. This method will be explained with reference to FIG. 7. Similar to the above-described method, a silicon oxide film 702 and polysilicon film 703 are formed on a semiconductor substrate 701 in this order as shown in FIG. 7(a). Phosphors are thermally diffused in the polysilicon film 703. A silicon oxide film 704 is formed on the polysilicon film 703 to a thickness of 4000 angstroms by means of a CVD method. Resist is coated to form a resist film 705 patterned so as to cover every second gate electrode area.
Using the resist film 705 as a mask, the silicon oxide film 704 is etched by a reactive ion etching method to obtain a silicon oxide film 704a shown in FIG. 7(b). Polysilicon is deposited to a thickness of 1000 angstroms by means of an LPCVD method, and etched by an isotropic, reactive ion etching method to form side walls 706 on the sides of the silicon oxide film 704.
As shown in FIG. 7(c), a silicon oxide film 707 is deposited on the whole surface of the device as shown in FIG. 7(c). The thickness of the silicon oxide film 707 is about 4000 angstroms which is about one half of the distance between patterns of the silicon oxide film 704a. After coating resist and flattening the surface of the device, it is etched back by means of a reactive ion etching method to obtain a silicon oxide film 704b whose thickness is thinner than the side walls 706 as shown in FIG. 7(d).
The polysilicon side walls 706 and polysilicon film 703 are etched by a reactive ion etching method to leave a polysilicon film 703a and silicon oxide film 704c on the gate oxide film 702. In this manner, gate electrodes are formed in a self-alignment manner with a constant clearance between gate electrodes.
Examples of devices having gate electrodes formed by the above-described conventional methods are shown in FIGS. 8 and 9. FIG. 8 shows a large scale integrated NOR type mask ROM of a virtual ground array type, and FIG. 9 shows a large scale integrated NAND type mask ROM. In the ROM shown in FIG. 8, buried n.sup.+ diffusion regions 801, 802, 803, . . . are formed on the surface of a semiconductor substrate at a constant pitch, and gate electrodes 811, 812, 813, . . . are formed on the surface of the device perpendicular to the diffusion regions. Such an array layout is disclosed in Sharp Technical Review, pp. 71 to 75, Vol. 40, 1988. Impurity ions are implanted into areas 821 and 822 to write data. In the ROM shown in FIG. 9, element forming areas 901 and 902 surrounded by an element isolation area 900 are formed on the surface of a semiconductor substrate. Contact areas 921 and 922 connected to wiring layers are formed within the respective element forming areas 901 and 902. Gate electrodes 911, 912, 913, . . . are formed perpendicular to the element forming areas 901 and 902, and impurity ions are implanted into areas 931 and 932. For such ROMs having gate electrodes formed at a narrow pitch, it is necessary to inject data writing impurity ions into a desired area at a high precision.
Impurity ions are implanted in the following manner. As shown in FIG. 10(a), a silicon oxide film 1002 is formed on the surface of a semiconductor substrate 1001, and polysilicon gate electrodes 1003a, 1003b, . . . are disposed. Resist is coated and patterned to remove it only at the areas where impurity ions are implanted into the channel regions under the gate electrodes 1003a, 1003b, . . . . In this case, the end face of the resist film 1004 is aligned with the center between the gate electrodes 1003a and 1003b. A silicon oxide film formed on the polysilicon gate electrodes has been etched out by using ammonium fluoride solution.
Boron ions (B.sup.+) are implanted at a dose of 1.times.10.sup.14 cm.sup.-2 and at an acceleration voltage of about 160 keV in order to raise the threshold voltage of an N-channel transistor constituting a memory cell of a NOR type ROM. The width of the gate electrode is set to 0.6 .mu.m, and a clearance is set to 0.1 .mu.m, for example. If the end face of the resist film 1004 is precisely aligned with the center between gate electrodes such as shown in FIG. 10(a), then impurity ions are implanted into a region 1011 near the substrate surface under the gate electrode 1003a, and into a deeper region 1012 at the gap between the gate electrode 1003a and the resist film 1004. The region 1012 is so deep from the surface of the semiconductor substrate 1001 that the threshold voltage at the channel region is not influenced. Ions are precisely implanted into the region 1011 corresponding to the width of the subject gate electrode 1003a near the substrate surface, and are not implanted near to the substrate surface of the adjacent gate electrode 1003b.
However, if the position of the resist film 1004 is misaligned such as shown in FIG. 10(b), the following problem occurs. Assuming that the end face of the resist film 1004 is misaligned by 0.2 .mu.m which is three times (3.sigma.) as large as the standard deviation, impurity ions are implanted not only into the channel region 1011 of the subject gate electrode 1003a, but also into the channel region 1013 of the adjacent gate electrode 1003b.
Thermal treatment after implantation of impurity ions causes the ions to diffuse by about 0.1 .mu.m in the lateral direction. Therefore, as shown in FIG. 10(c), impurity ions are diffused by 0.25 .mu.m into the channel region of the adjacent gate electrode 1003b. As a result, in the NOR type ROM shown in FIG. 8, the channel width of a cell transistor is shortened and the memory cell current is reduced greatly by about 0.6 [(0.6-0.25)/0.6].
In the case of the NAND type ROM shown in FIG. 9, the channel length is shortened, resulting in a possible punch-through or leakage current at the element isolation area 900.
As described above, with the conventional manufacturing methods, misalignment of a resist film causes impurity ions to be implanted into the area under an adjacent gate electrode, resulting in a reduced cell current and punch-through.

Method of manufacturing semiconductor device


A plating apparatus capable of preventing difference in an electrode potential between the pair of cathodes and a disturbance in a current distribution in Haring cell test and so on is provided. A plating apparatus (1) has an anode (12) and a pair of cathodes (13X) (13Y) which are provided in a plating bathtub (11); a plating power source (14) to supply an electric current between the anode (12) and the pair of cathodes (13X) (13Y); and a feedback circuit (21) to have an electrode potential of a first cathode (13X) equal to an electrode potential of a second cathode (13Y) while a summation of electric currents flowing through the pair of cathodes (13X) (13Y) is kept constant.

Conventionally, Haring cell test is known as a method for evaluating a plating performance. According to Haring cell test, plating is performed with an anode disposed between a pair of cathodes, and macrothrowing power (uniform electroplating ability) of plating by which a material is plated on the pair of cathodes is evaluated.
According to electroplating, current density and an amount of a plated material (metal) basically have a proportional relationship. However, if a condition in which there is not much difference in an amount of the plated material relative to a wide range of current density is achieved, a film having a uniform thickness can be formed by plating on a product having a complex shape. Ability to provide a uniform plating-film-thickness regardless of a current density is referred to as macrothrowing power.
Macrothrowing power is largely dependent on a current distribution. A current distribution is roughly classified into a first current distribution and a second current distribution. The first current distribution is dependent on geometrical conditions (a shape of an object to be plated, a shape of a plating bathtub, an arrangement of electrodes and so on) in the plating bathtub regardless of plating bath, plating conditions and so on. The first current distribution can be determined by a mathematical calculation or the like. Majority of a plating distribution is dependent on the first current distribution.
However, when plating is actually performed, a polarization phenomenon occurs on a cathode interface, and a new current distribution, i.e. a second current distribution is generated. The second current distribution is dependent on electrochemical characteristics such as polarization on a cathode, a conductivity of the plating bath and so on, and is changed by a type of a plating bath, a type and an amount of an additive, or the like.
An example of a circuit according to which a liquid between the anode and the pair of cathodes in Haring cell test is considered as an electric resistance, will be described. As shown in FIG. 6A, in an ideal system, a ratio of a distance between an anode 112 and a cathode 113X to a distance between the anode 112 and a cathode 113Y is set to be 1:2. When plating current 3 (A) is supplied to the whole of the system, current 2 (A) flows through the anode 113X, and current 1 (A) flows through the anode 113Y. Furthermore, voltage 200 (mV) is respectively applied to resistances 115X, 115Y between the anode 112 and cathodes 113X, 113Y.
On the other hand, as shown in FIG. 6B, according to an actual system, there are resistance components 116X, 116Y such as a wiring resistance, a contact resistance of a clip. For this reason, a distribution ratio between plating currents does not become 2:1, and disturbance in the current distribution is caused. Furthermore, potential differences between the anode 112 and the cathodes 113X, 113Y are 180 (mV), 240 (mV), respectively, so they are different from each other. A matter like this is caused also by an ammeter for measuring values of electric currents which flow through the cathodes 113X, 113Y.
That is, according to the actual system, an accurate measurement of the second current distribution is disturbed by a wiring resistance, a clip contact resistance and so on.


The present invention relates to a fixture to be mounted in a mounting hole in a ceiling or the like and an attachment device of said fixture, wherein said fixture is provided with an electrical connection means and a mechanical stopping means, the electrical connection means including a power supply port that can be connected by a simple operation, and the mechanical stopping means capable of removably fixing a heavy and elongated fixture in the mounting hole, so that, when the fixture is mounted in the mounting hole, both electrical and mechanical connection is simultaneously done. By an integrated design of the fixture wherein the back of the mounting hole (a space behind the ceiling panel or the like) is used as a housing space for a lighting circuit member, etc., the fixture can be made more compact with an improved design flexibility, and changes and movements of fixtures with respect to the mounting hole become possible.

Here, the description is given centering around a downlight fixture, that is often used for shop lighting, as an example. The downlight employs a structure that an internally mirror-finished and wired housing is inserted and fixed to a mounting hole which is previously drilled in a ceiling panel and a light source bulb is fitted to the housing.
Since the drilled hole cannot be repositioned and cannot be diverted to purposes other than downlight fixtures, the entire ceiling panel has to be replaced with a new ceiling panel when the room is reformed after years.
In addition, for the insertion and fixing of the housing to the mounting hole, too, an apparatus formation to satisfy both the efficiency of fixing operation and the stability of fixing is indispensable.
As lighting becomes diversified and the interior technique has made progress, recent reforming, including the seasonal reforming of room interiors and lighting means suitable for individual types of displayed articles, is done now frequently.
As the result of diversification in lighting, in addition to conventional incandescent lamps, various types of light source bulbs have been developed, including energy saving, high efficiency and light-color-improved high luminance discharge tubes and fluorescent tubes (FDL), and various lighting circuit means and various shapes of housings and attachments that are applicable for these light sources are provided.
In designing an effect lighting, a light source to be adopted is set by simulation, taking into account the colors and reflection characteristic of interior media as well as the ceiling height of the construction site. Light representation, light source positioning and light source types are determined by taking the layout of articles and pieces of furniture into account.
Changes immediately before completion and rebuilding the ceiling surface in each reforming is quite inconvenient as it requires additional labor and costs and the closure of the shop during construction.
In shops, hotels and restaurants, legally obliged equipment such as smoke sensors, heat sensors, emergency lamps and speakers that are nonuniform in both color and shape are irregularly fitted to ceiling surfaces and make ceiling interior details ugly.
The object of the invention is to provide the fitting of various downlight fixtures with ease of adjustment immediately before completion and ease of changing in reforming. Namely, the first object is ease of fixing to and removal from the mounting hole and that solid fitting and stopping is possible, and further, that the mounting hole drilled in the ceiling surface can be jointly used for multiple purposes and functions, that the beauty as a facility can be maintained and that a permanent use of the ceiling facility can be made possible.
In the case of a conventional downlight fixture, it is inserted from underneath into the mounting hole drilled in the fitting surface beforehand and is held by a spring member that protrudes from the wall side of the fixture body and holds an edge of the mounting hole. As another hanging means, a means by which, after inserting the fixture into the mounting hole, stopping pieces provided on the wall sides of a fixture body are drawn down by inserting fingers inside the fixture (an inner space to mount a lamp) and are pressed against the hole edge, is employed.
However, by the hanging using the elasticity of said spring member, the thrust force to the mounting hole is limited and the engagement is unstable. In addition, it is not always possible to reuse the fixture after reforming the ceiling since the spring's elasticity is degraded by forced pulling. On the other hand, said stopping piece draw-down means has a drawback in that the attaching operation require a longer time compared with said spring process because an operation is necessary to be done inside the fixture and that when the fixture is mounted it is not possible to mount a light source bulb beforehand because the operation space has to be secured.
The diversification of fixtures and apparatuses during recent years is such that apparatuses such as sensors, monitor cameras and speakers, as well as luminaires, of the recessed type are commercialized, but because these apparatuses are relatively heavy, it is necessary to stably secure the mounting hole. For this reason, as hanging means that have an excellent stability of hang-fixing and do not require any in-fixture operation, proposed are a fitting device for a recessed type fixture disclosed in the Japanese Utility Model Publication No. 60-29782 and a fitting device for a recessed type luminaire disclosed in the U.S. Pat. No. 533,153.
In these fitting devices, a threaded shaft that is rotated by operation from outside the fixture keeps a function piece inside the fixture while inserting the fixture into a mounting hole, and after the insertion, extends the function piece toward a stopping zone, and then the fixture body is lowered so as to hold a mounting hole edge between the fixture and a flange.
According to the structure stated in the specifications of the above-mentioned publications, construction is complicated and the number of parts is large, and yet there is an anxiety about the sureness of operation. The second object of the present invention is to improve these points and provide a fitting device for recessed fixtures which is formed with a small number of parts and simple in construction, is easily fitted to and removed from mounting holes, and assures sure and solid hanging.
Recently, there is a trend of reducing the height of individual floors in buildings. Accordingly, the ceiling space of each floor is narrowed, and needs for shallow type downlights as one of applicable means is increased.
By recent improvements, long-breadth light sources such as compact type fluorescent tubes and high-luminance discharge tubes are popularly used because of the energy saving effect and economy. These high-efficiency discharge tubes have structurally slender tubular bodies. When a light source with such a shape is applied to a shallow type downlight fixture, it is set laterally into the embedded body together with sockets.
In this case, a problem is the insertion to and removal from a socket of these light source tube/bulbs. That is, while stopping the long bulb laterally toward the socket which is set laterally in the narrow fixture body, the end base must be rotated while pressing the same against the prescribed position of the socket end, and yet a feeling operation at a height on a stepladder is troublesome as well as there is the danger of fingers touching the base or socket end.
Also, in the case of conventional shallow type downlight fixtures, the setting position for a light source tube/bulb is a little closer to a socket with regard to a reflector aperture of the main body, taking the insertion/removal space of the tube/bulb into account. As the result, the light center of the light source cannot be set for the center of reflected light axes of the reflector, causing degradation in reflection efficiency.
The applicant for the present invention previously proposed a downlight apparatus using an embedded housing. The apparatus using an embedded housing is structurally such that a tubular housing corresponding to the size of a lamp casing is previously fitted in a mounting hole in a ceiling or the like, and a downlight fixture body is held by the housing for use. Accordingly, if there is any projection exists on the lamp casing side, such as a lamp socket, engagement and insertion of the housing is not possible.
Since an operation to fit or replace a tubular bulb of the set downlight fixture is done near a ceiling surface using a stepladder with a wall switch turned off, it is necessary to move up and down the stepladder to access the wall switch each time to make sure of lighting. If this trouble is omitted or if a shop is open and there are customers, often the operation of replacing the tubular bulb is done with the wall switch on. In this case, there is the danger of electric shocks due to fingers touching electric parts as described above.
To solve the above-mentioned problems, the third object of the present invention is to provide a high-reflection, high-efficiency luminaire in which the main body of the luminaire can be engaged with an embedded housing by improving the shallow type downlight luminaire so as to enable the operation of replacing tubular bulbs to be done easily and safely.
In recent years, there are strong needs for the multipurpose use of spaces such as offices, workshops and houses using movable partitions. Multipurpose floor lighting is required to provide variations corresponding to different purposes of use.
Also, office equipment such as personal computers and word processors are widely used, and depending on the place where these apparatuses are put, the reflection and mirroring of lighting beams may occur in display screens, and thus the irradiating direction of light sources largely affects the health and work efficiency. Desirably, light sources can be moved according to the condition of use. Up until now, people and furniture have had to move around to cope with the fixed luminaires; it should have been the other way around.
Furthermore, as a tendency, the reforming of window displays and shop displays are done frequently, and in this case, too, the movement of lighting apparatuses is required.
In the case of conventional luminaires, changes in fitting positions on ceilings and walls were done using lighting ducts, so that the movement was limited to be along such lighting ducts.
The fourth object of the present invention is to provide a luminaire of which the position and orientation can be changed to meet the above-mentioned requirements.
For fixtures fitted to ceilings, such as sensors and monitor cameras, the recessed type like a downlight luminaire is also adopted in addition to those directly fitted to ceilings.
These fixtures typically employ conventional fixtures that are directly embedded and held. As described in the prior art, however, there is also a method using embedded housings, which has an advantage that fixtures can be optionally selected and changed as needed.
The above-mentioned fitting methods are based on a precondition that the fitting surface is a double-ceiling. Today, there are many facilities that have reinforced floors and slab ceilings, and said fixtures for double-ceilings are not applicable to these facilities.
To solve this problem, the fifth object of the present invention is to provide an exposed casing for slab fitting.
A double-ceiling provided at the ceiling surface of a slab is a thin ceiling panel for decoration. So far, embedded fixtures have been limited to light-weight fixtures, taking the strength of the double-ceiling into consideration.
Recent diversification in luminaires has resulted in development of recessed-type fixtures using light sources such as multi-tube fluorescent lamps or high-luminance mercury lamps. These fixtures need stabilizers or transformers for the lighting circuits. Fitting these integrated-type fixtures to double-ceilings contains an anxiety due to the strength. In addition, a rotatable fixture dealt in the present invention has an elongated structure if it is a compact fluorescent lamp (FPL) or the like. A heavy, elongated lamp cannot be fitted to a double-ceiling which does not have sufficient strength, because there is the danger of an external force being applied to an end of the elongated lamp, which may apply an unreasonable force to the edge of the mounting hole in the ceiling. To solve this problem is the sixth object of the present invention. Basic concept of the present invention is summarized in the following: The title of application for the present invention is "EQUIPMENT USING MOUNTING HOLE OF CEILING AS FIXING ELEMENT AND ACCESSORY DEVICES".
The prescribed mounting hole in a ceiling space in which various fixtures are mounted is merely referred to as a "mounting hole" hereinafter.
The fixture may be wiring accessories, a luminaire or any one of various functional apparatuses attached to a ceiling of a residential space and is merely referred to as a "fixture" hereinafter.
(1) The "mounting hole" is internally equipped with general-purpose power supply (strong and weak electric power) and control functions. PA0 (2) The "mounting hole" internally forms a mechanical stopping mechanism for a fixture. PA0 (3) A fixture wherein mechanisms specified in Paragraph (1) (electrical) and Paragraph (2) (mechanical) described above are simultaneously connected by a touch-operation is also proposed (a unit body described in paragraph (6) mentioned later). PA0 (4) The "mounting hole" space forms a housing space for externally inserting and fitting an integrated "fixture" in whole or in part. Specifically, an embedded housing is used. PA0 (5) The invention is characterized in that structures of the above paragraphs (1), (2), (3) and (4) are integrated, depending on the function and usage of each fixture and are installed in "mounting holes." PA0 (6) The "fixture" is available with two types; a single body and a unit body that uses an embedded housing in between, which are used for the same space but for different purposes [single body.fwdarw.fixed usage, low cost; unit body.fwdarw.variable by touch-operation, movable, and available for floor operation (lamp changes, reflector cleaning, etc.)]. PA0 (7) By the integrating effect, choice and combination, of the above, multiplying/expanding effects are attained in design performance, additional function and economy. PA0 (8) When the unit body is used, since the completion inspection is finished simply by installing an embedded housing, it is possible to choose a "fixture" on the site after deciding a resident/tenant. Hence, wasted fixture and losses in installation work due to changes can be eliminated, and yet the same effect can be obtained each time the status quo ante is restored when a tenancy is canceled/expired. PA0 (9) In space production and effect lighting in a shopping center or the like, a totally uniform design can be intended in terms of light source, light distribution, usage and wiring systems by providing fixture edges with the same design (in shape and color) and the same diameter on ceiling surfaces. PA0 (10) In addition to the above-mentioned paragraph (9), when unit bodies are used in a commercial space (sales corner, show window) where layout changes and renewals in floor units are frequent, changing "fixtures" can be done flexibly with touch-operations even by shop clerks who do not have a qualification to do electrical work. That is, the effect of changing the fixture configuration is noticeably increased. It is particularly effective when tenants change (example: recessed-type downlight.fwdarw.direct-fitting fixture.fwdarw.pendant fixture). PA0 (11) For example, by the recent development of energy saving compact type fluorescent lamps (FDL) and the resultant commercialization of fixtures for 27 W (corresponding to a 100 W incandescent lamp) and 32 W (150 W), downlight fixtures that were formerly used for local lighting are rapidly shifting toward base lighting (whole lighting). In this case, a round-hole preparation of "mounting holes" can be done most speedily and at low costs by using popular electric tools. A new stopping mechanism for speedy mounting to a mounting hole is also provided by the invention. PA0 (12) Unit body type embedded housings allow unnecessary lamps to be removed and can be closed by applying flat covers without the need for selectively turning off some of lights. This means that adjustments in luminance and light distribution in changing layout can be done separately from changing light sources and lamp casings. In other words, together with the changing function, this contributes to the development in double-ceiling preparation, prefabrication and modularization (resulting in cost reduction and a reduction in construction period). PA0 (13) In the past, the light source use for a downlight fixture was an incandescent lamp. As the base was commonly available for 40 W, 60 W and 100 W lamps, luminance changes were done merely by changing lamps and even unskilled persons could do it. PA0 (14) The present invention also eliminates causes of rust and salt-induced corrosion by using plastics for the downlight fixtures that have conventionally been made of metal parts. Further, together with an effect that an integrated use of a ceiling space and a fixture is first made available by incorporating a new stopping mechanism into the "mounting hole" which enables several ten times of removals and fittings, the present invention specifically intends a semi-permanent use. PA0 (15) In addition to the advantages of common dies and divisibility stated in said Item (6), using plastics affords the following advantages:
Installation has to be conducted externally and from one direction only into the "mounting hole" according to construction procedures.
a: Examples of Complete Housing
Downlight fixtures, smoke sensors (these may be directly attached), etc.
b: Examples of Partial Housing
Component parts of semi-recessed, direct fitting type luminaires (lighting circuit members, transformers, reelers, suspension devices, extension devices, etc.)
Further, for use with a downlight unit, for example, both the single body and the unit body are produced by using a common die, dividable, and are given the low-cost performance and additional functions.
However, in the case of the recently mainstream compact type fluorescent lamps (FDL), bases differ by lamp wattage because lamps are each to be made in a set with an applicable lighting circuit.
Because of this, in changing luminance, an entire fluorescent downlight fixture is to be removed from a double-ceiling, which requires a specialist engineer and increases costs a lot. The same can be said to changing a light source.
The unit type (embedded housing) solves this problem, too.
Accordingly, an everlasting use through which no recycling is necessary is possible and energy saving and ecological requirements are satisfied. (Currently, metallic downlights are discarded each time the double-ceilings are replaced or after replacing them several times at the most, though reasons are not mentioned here.)
a: As plastic is an insulator, it allows housings of terminal blocks and so on to be integrated into lamp casings, resulting in a cost reduction.
b: An optimal curve for luminous efficiency and a stepped portion can be integrally and simultaneously formed on the reflector surface.
c: With regard to the reflector, in addition to a mirror finish, it can be finished in white for use with compact type fluorescent lams (FDL), and thereby effects, such as erasing the lamp image and eliminating glare, can be secured.
d: By compounding an after-light coating material with resin, a use as an emergency lamp which requires no power supply can be obtained.

Equipment using mounting hole of ceiling as fixing element and accessory devices


A printer buffer unit is connectable to one or a plurality of host computers and one or a plurality of printers. The printer buffer unit has a unit for detecting a break of print job data sent from a host computer, and a unit for adding a job offset command at the time of the break in sending the print job data to a printer.

1. Field of the Invention
The present invention relates to a printer buffer unit used in a system having one or a plurality of host computers which share one or a plurality of printers.
2. Related Background Art
Conventionally, in sharing one or a plurality of printers by one or a plurality of host computers, a printer buffer unit operates simply to send data from a host computer to a printer to sequentially print the data.
If a print job of a host computer has been completed and the next print job occurs, documents for the next print jobs are ejected onto the documents for the present print job. Therefore, there arises a problem that it takes time to discriminate between documents of different jobs.
Furthermore documents for different print jobs outputted from a plurality of host computers are ejected as to be superposed one upon another on the eject tray of the same printer Therefore it arises a problem that it takes time to discriminate between documents of print jobs from different host computers.
Still further, if an error such as no printing sheet, jamming, or the like occurs at a printer under operation and it becomes impossible to continue the print-out operation, there arises a problem that the print job cannot be terminated unless such an error is informed to the host computer and a printer error recovery operation is carried out manually by the operator.
Furthermore, if a plurality of printers are connected to a printer buffer unit and the sizes of printing sheets or the like for the printers are different, a host computer is required to check the printers connected to the printer buffer unit and select a suitable one


A panel display apparatus includes a V-RAM, a display controller, a low-pass filter and a panel display unit. Digital video signals read from the V-RAM by the display controller are input to the low-pass filter. Then, of the input digital video signals, high frequency components in spatial frequency characteristic thereof are removed, as required, by the low-pass filter under control of the display controller and the resulting digital video signals are fed to the panel display unit. Thus, satisfactory images are displayed on the panel display unit under the control of the display controller in accordance with the digital video signals from the low-pass filter whether the images are characters and graphics or natural pictures.

1. Field of the Invention
The present invention relates to improvement in a panel display apparatus.
2. Description of the Prior Art
FIG. 5 shows a conventional panel display apparatus such as a liquid crystal display. The panel display apparatus of FIG. 5 designed to display images on both a CRT (Cathode-Ray Tube) 5 and a panel display 7, comprises a CPU (Central Processing Unit) 1, a V-RAM (Video Random Access Memory) 2, a display controller 3, and the like. A video signal read from the V-RAM 2 is outputted by the display controller 3 in accordance with instructions of the CPU 1 as a few bit digital video signals VD.sub.o -VD.sub.k. The digital video signals VD.sub.o -VD.sub.k are converted into an analog video signal by a D/A (Digital-to-Analog) converter 4 and fed into the CRT 5. Then the CRT 5 produces an image in accordance with both the resulting analog video signal and horizontal/vertical synchronizing signals H/V that are fed by the display controller 3.
The digital video signals VD.sub.o -VD.sub.k outputted by the display controller 3 are also fed into a panel display unit 6. Then the panel display unit 6 produces an image in accordance with both the digital video signals VD.sub.o -VD.sub.k and the aforementioned horizontal/vertical synchronizing signals H/V. Thus, using the same digital video signals VD.sub.o -VD.sub.k, both the CRT 5 and the panel display 7 simultaneously reproduce the same image.
However, the conventional panel display apparatus as described above has the following problems.
Because the pixels in the panel display 7 are thoroughly independent of each other, an image reproduced on the panel display 7 can be represented as an aggregate of images in the units of pixels obtained from the sampling data which result from sampling the digital video signals VD.sub.o -VD.sub.k for each pixel. In contrast to this, in the case of an image reproduced on the CRT 5, although it is subject to sampling by a shadow mask, a video signal cannot be represented as thoroughly discrete images because of the high frequency characteristic of the CRT's electrical circuit typified by flyback transformers, the incapability of stopping down the spot diameter of scanning beam to a proper one, and other reasons. In other words, in representing an image the luminance of which is relative to the distance in a scanning direction, the luminance variation of an image reproduced on the panel display 7 results in stepped waveform, while that of an image reproduced on the CRT 5 results in rounded waveform without corners as shown in FIG. 6.
Therefore, it can be said that the luminance variation of an image reproduced on the CRT 5 can be expressed by a continuous function in which high frequency components are cut off in the spatial frequency characteristic of digital video signals toward the scanning direction.
Because of such difference in the spatial frequency characteristic of the input digital video signals VD.sub.o -VD.sub.k, in displaying characters and graphics, the panel display 7 can present satisfactory images with sharply outlined characters and graphics, while the CRT 5 displays images with somewhat blurred outlines. Further, in displaying characters and lines, the panel display 7, having independent pixels, can present sharply outlined characters and lines, while the CRT 5, poor in high frequency characteristic, results in images blurred in outline.
Meanwhile, natural pictures such as people and landscapes involve less edges in their luminance variation waveform and have more portions where the luminance at their outlines gradually varies. For this reason, in displaying natural pictures, the CRT 5, which has images blurred in outlines as described above, can offer satisfactory images, while the panel display 7, which involves stepped waveform of luminance variation, results in coarse display with the luminance variation emphasized in outlines.
In consequence, the panel display 7 is successful in character and graphic images but inferior to the CRT 5 in images of natural pictures.

Panel display apparatus to satisfactorily display both characters and natural pictures


Various blanks and constructs formed therefrom are provided. The various constructs include features for supporting a food item at an elevated position to enhance the heating, browning, and/or crisping of the food item in a microwave oven.

Microwave ovens provide a convenient means for heating a variety of food items, including dough-based products such as pizzas, pies, and sandwiches. However, microwave ovens tend to cook such items unevenly and are unable to achieve the desired balance of thorough heating and a browned, crisp crust. Thus, there is a continuing need for a microwavable package that provides the desired degree of heating, browning, and crisping of the crust or dough of a food item.


A transmission includes a first drive secured to an input, producing a fixed drive ratio; a second drive secured to an input, producing a variable drive ratio; a planetary gearset including a member connected to the second drive, and a second member; a brake releasably holding the second member rotatably fixed; a first clutch releasably connecting the first member and an output; and a second clutch releasably connecting the second member and the first drive.

1. Field of the Invention
This invention relates generally to a continually variable transmission (CVT) that is able to produce forward and reverse drive and to operate in a torque split mode.
2. Description of the Prior Art
CVT transmissions produce variable speed ratio required for a motor vehicle by changing the radial position at which a drive belt engages an input pulley and an output pulley. But CVT transmissions may have low mechanical efficiency and a limited range of drive ratio.
A need exist for a control technique or kinematic arrangement that extends the overdrive range of a CVT transmission, provides the reverse drive function required for a torque converter vehicle launch using a CVT, yet requires a minimum number of friction control elements, such as clutches and brakes.

Torque split continually variable transmission


An operating method of a semiconductor device is provided. The operating method of the semiconductor memory device includes programming a second source select transistor electrically coupled to a common source line through a first source select transistor; reprogramming the second source select transistor when a threshold voltage of the second source select transistor is less than a target voltage, and ending a program for the second source select transistor when the threshold voltage of the second source select transistor is greater than or equal to the target voltage. The programming includes electrically decoupling the second source select transistor from the common source line by turning off the first source select transistor.

1. Technical Field
The invention relates to an electronic device, more specifically, relates to a semiconductor memory device and an operating method thereof.
2. Related Art
A semiconductor memory device is a memory device using a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), or the like. The semiconductor memory device can be classified as a volatile memory device and a nonvolatile memory device.
The volatile memory device is a memory device which loses stored data when a power supply cuts off. The volatile memory device includes a static RAM (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), or the like. The nonvolatile memory device is a memory device which maintains stored data even when a power supply cuts off. The nonvolatile memory device includes a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), flash memory, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), or the like. The flash memory can be classified as a NOR-type and a NAND-type.
Recently, in order to improve a degree of integration of the semiconductor memory device, a semiconductor memory device having three-dimensional array structure has been studied.

Semiconductor memory device and operating method thereof


The present invention aims at providing an alimentative infusion liquid which has improved stability and preservability and can be administered through a peripheral vein. The infusion liquid contains sugars, amino acids, electrolytes and a fat emulsion at a specific mixing ratio and has a specific pH value and a titratable acidity. The alimentative infusion liquid of the present invention containing the above-described components has good preservability without suffering from precipitation, denaturation and the like problems. Further, since the pH value is adjusted to a specific level and the titratable acidity is retained low, administration of the infusion liquid through a peripheral vein does not cause troubles such as angialiga.

Intravenous infusion is carried out for the purpose of supplying nutrients to maintain a patient's life when oral or nasal feeding is impossible or insufficient, when the digestion and absorption functions of the patient are in a poor state, even if such a feeding means can be carried out, or when the passage of food through the digestive tract makes the patient's condition or disease more serious. Examples of commercially available infusion preparations include a sugar intravenous infusion liquid which contains reducing sugars and the like, an amino acid intravenous infusion liquid which contains essential amino acids and the like, an electrolyte infusion liquid which contains minerals and the like, a fat emulsion which contains a plant oil emulsion and the like, and a vitamin mixture. These infusion preparations are appropriately selected depending on the condition of the patient and are mixed upon use. However, mixing these preparations at the time of their use requires complex handling and, above all things, raises the problem of microbial contamination. With the aim of overcoming such problems, various infusion preparations, in which some of the aforementioned infusion liquids are mixed in advance, have been proposed. Infusion preparations which contain sugars, amino acids, electrolytes and a fat emulsion, all being essential nutrients to be supplied, are especially useful from a clinical point of view.
However, since these sugar infusion liquids, amino acid infusion liquids, electrolyte infusion liquids and fat emulsion are different from one another in terms of the conditions for their stable existence, various problems arise when they are mixed, and the mixture becomes useless in many cases.
For example, because of its unstable nature, a fat emulsion is apt to form bulky fat particles and to cause phase separation (creaming) when mixed with other infusion liquids. In particular, divalent cations contained in an electrolyte infusion liquid cause aggregation and disintegration of fat emulsion particles.
In the case of an electrolyte infusion liquid, since it contains calcium and phosphoric acid as essential components to maintain the balance of electrolytes, it is apt to form calcium phosphate by the reaction of calcium with phosphoric acid and thereby to generate turbidity and precipitation. In order to prevent the formation of turbidity and precipitation, such an electrolyte infusion liquid is usually adjusted to a low pH value (less than pH 5). When such a electrolyte infusion liquid is mixed with an amino acid infusion liquid, the pH of the mixture increases to the amino acid pH value because of the strong buffer action of amino acids, thus requiring a large quantity of acidic materials (for example, hydrochloric acid, acetic acid and the like) to keep the pH value at a low level. However, acidic materials can be used only in a limited amount because a large quantity of acid spoils the balance of the infusion components. As a consequence, the pH value of the mixture of electrolyte and amino acid infusion liquids cannot be lowered to a satisfactory level, thus resulting in the generation of turbidity and precipitation during heat sterilization of the mixture.
In addition, when a mixture of an amino acid infusion liquid with a sugar infusion liquid is sterilized by heating, it is known that considerable coloring occurs due to the Maillard's reaction.
As described above, it is difficult to prepare a storable infusion preparation which contains a sugar, amino acids, electrolytes and a fat emulsion, in advance, because mixing these different types of infusion liquids or emulsions causes various problems such as precipitation, phase separation, denaturation, coloring and the like. Because of these problems, a fat emulsion, a sugar infusion liquid, an amino acid infusion liquid and an electrolyte infusion liquid are ordinarily mixed upon use. As a consequence, an alimentative infusion liquid has been desired which contains sugars, amino acids, electrolytes and a fat emulsion and can be stably stored.
There has been required a convenient method for complete alimentation via a peripheral vein in institutions where total intravenous alimentation is scarcely employed. Also, alimentation via a peripheral vein is a preferable method in order to completely feed a patient with temporary cut-off of oral alimentation for a short period of time. However, conventional alimentative infusion liquids to be administered via a peripheral vein have a low caloric value. For the total alimentation, it is therefore necessary to administer such an infusion liquid in an increased dose. However, an increase in the administration dose is accompanied by troubles such as angialgia and phlebitis, which restricts the administration dose. Thus, it is impossible to supply a sufficient energy to a patient, which makes the patient undernourished. Under such conditions, there is a risk that the patient suffers from unfavorable symptom. On the other hand, the injection of a common infusion liquid, which is to be administered via the main vein, into a peripheral vein causes side effects such as angialgia. Thus such an infusion liquid cannot be administered via a peripheral vein in practice.
Accordingly, it has been urgently required to develop a hyperalimentative infusion liquid which can be administered via a peripheral vein and enables total alimentation.
Under these circumstances, the present inventors have conducted extensive studies on an alimentative infusion liquid containing sugars, amino acids, electrolytes and a fat emulsion, which is stable and can be administered via a peripheral vein. As a result, they have successfully found out that an alimentative infusion liquid containing the above-mentioned components, which is free from various problems, for example, precipitation, phase separation, denaturation and coloring, and can be administered via peripheral vein without any trouble, can be obtained by improving the properties of each component, the composition and the liquid properties, thus completing the present invention. Accordingly, an object of the present invention is to provide an alimentative infusion liquid containing sugars, amino acids, electrolytes and a fat emulsion, which is hyperalimentative, excellent in stability and preservability and can be administered via a peripheral vein.

Alimentative infusion liquids for administration through peripheral vein

Yoshitomi Pharmaceutical Industries, Ltd.


A temperature-controlled semiconductor laser apparatus includes a semiconductor laser element, an optical fiber, a temperature controller, a thermistor, and a package. The semiconductor laser element emits a laser beam. The optical fiber receives the laser beam emitted from the semiconductor laser element. The temperature controller cools and heats the semiconductor laser element to keep the semiconductor element at a preset temperature. The thermistor detects an ambient temperature of the semiconductor laser element. The package accommodates at least the semiconductor laser element and the temperature controller in a sealed state and having the thermistor mounted on an inner wall of the package.

The present invention relates to a semiconductor laser apparatus used in optical communications and optical information processing and, more particularly, to a temperature-controlled semiconductor laser apparatus whose temperature can be controlled using a temperature controller and a temperature detection thermistor, and a temperature control method therefor.
A combination of a temperature controller using Peltier elements and a thermistor for detecting the temperature of a portion closest to a semiconductor laser mounting portion to perform temperature control of a semiconductor laser element is popularly used as a conventional temperature-controlled semiconductor laser apparatus. An arrangement used in a conventional temperature-controlled semiconductor laser apparatus will be described below.
FIG. 9 shows an arrangement of a conventional temperature-controlled semiconductor laser module. As shown in FIG. 9, a semiconductor laser element 1 and an island 5 are soldered (not shown) on a heat sink 23. The heat sink 23 is soldered (not shown) on a carrier 12. The thermistor 2 is soldered (not shown) on the carrier 12 near the semiconductor laser element 1.
A block 11 is soldered (not shown) to the carrier 12. A solder coating is formed on the outer surface of an optical fiber 6 and is fixed to the block 11 with a soldered portion 10 at a position where light emitted from the semiconductor laser element 1 is incident on the optical fiber 6.
Lead wires 17 of a temperature controller 18 are electrically connected to the lead terminals (not shown) of a package 7 to obtain external connections. The temperature controller 18 comprises Peltier elements 14, an upper substrate 15, a lower substrate 16, and the lead wires 17.
The basic principle of the temperature controller 18 will be described below. As shown in FIG. 11, n- and p-type semiconductor layers 27 and 28 are bonded between the upper substrate 15 and the lower substrate 16. The plurality of pairs of n- and p-type semiconductor layers 27 and 28 are connected to upper and lower soldered portions 29 in a staggered manner between the upper and lower substrates 15 and 16 to constitute a series connection circuit. The upper and lower substrates 15 and 16 normally consist of a material such as a ceramic material so as to achieve electrical insulation.
When a DC current flows in a direction of an arrow in FIG. 11, the upper substrate 15 side on which the current flows from the n-type semiconductor layer to the p-type semiconductor layer absorbs heat, while the lower substrate 16 side on which the current flows from the p-type semiconductor layer to the n-type semiconductor layer generates heat. The temperature controller 18 utilizes a Peltier effect by causing the current to flow through the two types of bonded semiconductor layers.
The lower surface of the lower substrate 16 of the temperature controller 18 is fixed with a soldered portion 19 on a base 30 of the package. The carrier 12 is fixed on the upper surface of the upper substrate 15 through a soldered portion 13. The semiconductor laser element 1 and the island 5 are electrically connected through wires 4.
The island 5 and lead terminals 22 are electrically connected through wires 9 and a wiring pattern 8, and the thermistor 2 and lead terminals 21 are electrically connected through lead wires 3 and a wiring pattern 20.
After the above components are mounted, a cap 32 is welded by seam welding and sealed by the package 7 in which nitrogen gas is kept sealed, as shown in FIG. 10, thereby obtaining the conventional temperature-controlled semiconductor laser apparatus.
Temperature control of the semiconductor laser element 1 in the conventional temperature-controlled semiconductor laser apparatus will be described below. The direction and magnitude of a current supplied to the lead wires 17 are controlled in accordance with a temperature detected by the thermistor 2. By this control, the temperature of the upper substrate 15 is controlled to keep the temperature of the semiconductor laser element 1 constant.
When the temperature of the semiconductor laser element 1 which is detected by the thermistor 2 is higher than the preset temperature of the semiconductor laser element 1, a current flows in the lead wires 17 of the temperature controller 18 in a direction to cool the semiconductor laser element 1. To the contrary, when the detected temperature is lower than the preset temperature, a current flows in a direction to heat the semiconductor laser element 1. When the difference between the detected temperature of the semiconductor laser element 1 and the preset temperature is large, the value of the current is controlled to increase. When the difference is small, the value of the current is controlled to decrease.
In the conventional temperature-controlled semiconductor laser apparatus, since the thermistor 2 is fixed on the carrier 12 near the semiconductor laser e element 1 on the temperature control target side of the temperature controller 18. For this reason, a space for fixing the thermistor 2 on the carrier 12 on the temperature control target side of the temperature controller 8 must be assured. The thermistor on the temperature control target side of the temperature controller 18 must be connected to the package 7 through the lead wires 3. For this reason, heat generated outside the package 7 is transferred to the temperature control target side of the temperature controller 18, and temperature control characteristics are greatly degraded.

Temperature-controlled semiconductor laser apparatus and temperature control method therefor


A stethoscope disinfection system comprising a guide member comprising a body member, a rotation-imparting member, a slide guide track, a spring guide track, and a trolley guide track, and a trolley comprising a lower housing member, a cam member, a lock head, a spring apparatus, a brush member, an upper housing member configured to receive at least a portion of a head of a stethoscope, and a dispersing member positioned in the dispersing mechanism chamber. The system may further comprise a slide guide configured to engage with each of the arm of the lock head and the slide guide track and to translate along a length of the slide guide track.

The transmission of bacteria as a result of use of stethoscopes without engaging in proper cleaning of the stethoscope is an increasing cause for concern. Previous solutions have included the use of an alcohol swab. However, such solutions are inconvenient for the medical professional using the stethoscope, as it requires them to open a single-use swab, throw the wrapper away, and then manually clean the stethoscope. Moreover, such a solution relies on the thoroughness of the user to perform adequate cleaning.
Other solutions have utilized UC irradiation of the stethoscope. However, such solutions require a power source, which can be inconvenient for the user, either requiring replacement or recharging of batteries, or frequent trips to a device that is located near a power source. Moreover, such solutions require substantial amounts of time to be effective, creating a delay in a field where the time of interaction between the user and the patient is increasingly diminished
Yet other solutions have relied on a disinfecting spray, but do not provide for the mechanical cleaning of the stethoscope. As such, a biofilm may accumulate on the surface of the stethoscope, both reducing the effectiveness of the spray and negatively affecting the performance of the stethoscope.
Accordingly, there is a need in the art for a solution in the art to provide for a quick, reliable, and effective device for cleaning a stethoscope head.
This background information is provided to reveal information believed by the applicant to be of possible relevance to the present invention. No admission is necessarily intended, nor should be construed, that any of the preceding information constitutes prior art against the present invention.

System for stethoscope head disinfection


The invention concerns peptides which bind antibodies that are found in elevated levels in body fluids of schizophrenic patients and are found at a lower level or not found at all in body fluids of non-schizophrenic individuals. Using a computerized program, the antigenic epitope of the peptides of the invention is predicted as having a core of hydrophobic amino acids which is surrounded by positively charged amino acids. The peptides of the invention are useful in the diagnosis of schizophrenia in an individual.

Schizophrenia is a syndrome which encompasses a variety of mental symptoms like auditory hallucinations, paranoia, delusions, catatonia, bizarre behavior or emotional withdrawal. Schizophrenia affects about 1% of the total population and its economical as well as social burden on society are enormous. The onset of the disease occurs at an early age and thus patients typically need life-long medical and psychiatric supervision. Schizophrenia is, therefore, rated as one of the most costly diseases in the industrial world1.
There are various known risk factors associated with schizophrenia such as genetic predisposition, birth during winter and complications during pregnancy and birth. Viral infections and subsequent autoimmune reactions have also been proposed as possible causative factors2-4. The involvement of autoantibodies against platelets in schizophrenic patients was also shown as elevated levels of autoantibodies were detected in schizophrenic and demented patients as compared to control subjects, bipolar, depressed, personality disordered or schizoeffective patients5-6. Western Blot analysis revealed a pattern of platelet antigens recognized by autoantibodies obtained from schizophrenic patients which differed from that recognized by autoantibodies obtained from patients suffering from autoimmune thrombocytopenia and dementia7. The antigen bound specifically by autoantibodies obtained from schizophrenic patients has been characterized by its molecular weight.

Assay for the diagnosis of schizophrenia based on a new peptide


A clock data recovery circuit including a recovery unit and a loop control unit is provided. The recovery unit generates a recovery clock signal according to an original data signal. The recovery unit locks a frequency of the recovery clock signal to a correction frequency through a first loop, and locks the frequency of the recovery clock signal to a sampling frequency through a second loop. The correction frequency is smaller than the sampling frequency. The recovery unit adjusts the frequency of the recovery clock signal according to a reference clock signal and a first dividing signal in the first loop. The loop control unit switches the recovery unit to the first loop or the second loop according to a frequency difference between the reference clock signal and a second dividing signal.

1. Field of the Application
The invention relates to a clock data recovery circuit, and more particularly, to a clock data recovery circuit having two loops.
2. Description of Related Art
As for a high-speed serial transmission system, an original data signal undergoes attenuation and distortion in transmission. Therefore, a receiver of the transmission system often has to perform an appropriate recovery processing to the original data signal through a clock data recovery circuit. In terms of operation, the clock data recovery circuit may generate a periodic recovery clock signal, and may extract a recovery data signal from the original data signal through the recovery clock signal.
The circuit structure of the clock data recovery circuit may generally be divided into two types: one is a circuit structure with a reference clock signal, and the other is a circuit structure without a reference clock signal. In terms of the circuit structure with the reference clock signal, the conventional clock data recovery circuit often generates the reference clock signal by an on-chip oscillator, so as to lower hardware costs of the circuit.
However, a frequency of the on-chip oscillator often has an offset due to variations in process, voltage or temperature, and thus loops in the clock data recovery circuit are unable to be locked, thereby causing the clock data recovery circuit to extract incorrect data signals.


A single-ended operational amplifier includes an output stage, a first transconductance amplifier and a second transconductance amplifier. In an offset cancellation mode, two inputs of the first transconductance amplifier are supplied with a reference voltage to sink two currents from two inputs of the output stage respectively, the output stage generates a third current according to the difference between the two currents to charge a capacitor, and the second transconductance amplifier generates two currents according to the voltage in the capacitor to make currents in the two inputs of the output stage equal to each other, thereby canceling the offset of the single-ended operational amplifier.

While electronic devices are becoming more and more sophisticated, any minute error can have unexpected influence on the operations of these devices. Consequently, increasingly heightened requirements are being imposed on accuracy of electronic devices. FIG. 1 is a circuit diagram of a conventional current regulator 10, in which a current source 12 is connected between a voltage source VDD and a drain of a transistor 18 to provide a reference current IREF, a single-ended operational amplifier 16 has a non-inverting input connected to the drain of the transistor 18 and an output connected to a gate of the transistor 18 to establish a negative feedback path therewith, and a transistor 19 has a drain connected to an inverting input of the single-ended operational amplifier 16 and a gate connected to the output of the single-ended operational amplifier 16 to establish a positive feedback path therewith, and mirrors the current in the transistor 18 to generate a load current ILED for a light-emitting diode (LED) 14. In FIG. 1, the voltage source VOS at the inverting input of the single-ended operational amplifier. 16 represents the offset effect of the single-ended operational amplifier 16. FIG. 2 is a diagram to illustrate the I-V curve of the current regulator 10 shown in FIG. 1. Ideally, the single-ended operational amplifier 16 has no offset and the relationship between the load current ILED and the supply voltage VDD is piecewise linear as shown by the curve 22. In this case, because of the constant forward voltage of the LED 14, the voltage at the drain of the transistor 19 decreases with the decrease of the supply voltage VDD. Due to the virtual short between the inputs of the single-ended operational amplifier 16, the voltages at the drains of the transistors 18 and 19 will be equal to each other, and thus the load current ILED will remain constant, unless the supply voltage VDD decreases beyond a threshold Vth. After this point of VDD=Vth, the single-ended operational amplifier 16 can no longer keep the voltages at the drains of the transistors 18 and 19 equal to each other, and the load current ILED will decrease with the decreasing supply voltage VDD. However, the single-ended operational amplifier 16 may have offset due to unmatched components thereof. If the offset voltage VOS is positive, the load current ILED will have a peak, as shown by the curve 20 of FIG. 2. On the contrary, if the offset voltage VOS is negative, the load current ILED will fall down in advance before the supply voltage VDD becomes lower than the threshold Vth, as shown by the curve 24 of FIG. 2.
FIG. 3 is a circuit diagram of another conventional current regulator 30, in which a current source 32 is connected between a voltage source VDD and a resistor REF to provide a reference current IREF, and a single-ended operational amplifier 36 has an inverting input connected to the node A between the current source 32 and the resistor REF, an output connected to a gate of a transistor 38, and a non-inverting input connected to the node B between a source of the transistor 38 and a resistor RSET. Because of the virtual short between the inputs of the single-ended operational amplifier 36, the voltage at the node B will be equal to that at the node A, and this voltage VB will determine a load current ILED for a LED 34 serially connected to the transistor 38 and resistor RSET. In FIG. 3, the voltage source VOS at the inverting input of the single-ended operational amplifier 36 represents the offset effect of the single-ended operational amplifier 36, and FIG. 4 is a diagram to illustrate the relationship between the load current ILED and the reference current IREF in the current regulator 30 due to the offset voltage VOS. Ideally, the single-ended operational amplifier 36 has no offset and the curve representing the relationship between the load current ILED and the reference current IREF is a straight line passing through the origin, as shown by the curve 42 of FIG. 4. If the single-ended operational amplifier 36 has a positive offset, the relationship curve of the load current ILED and the reference current IREF will shift upward, as shown by the curve 40 of FIG. 4; while if the single-ended operational amplifier 36 has a negative offset, the relationship curve of the load current ILED and the reference current IREF will shift downward, as shown by the curve 44 of FIG. 4.
As shown in FIGS. 2 and 4, the offset voltage VOS of the single-ended operational amplifiers 16 and 36 may result in error in the load current ILED provided by the current regulators 10 and 30, so it is necessary to cancel the offset VOS of the single-ended operational amplifiers 16 and 36 in order to provide accurate current ILED by the current regulators 10 and 30. For offset cancellation of operational amplifiers, there have been proposed many arts, for example, "Design of Analog CMOS Integrated Circuits", Pages 474-476, McGraw-Hill International Publications, 2001, and U.S. Pat. Nos. 6,194,962, 5,061,900, 6,459,335, 6,573,783 and 5,550,512.
FIGS. 5 and 6 show two states of a conventional operational amplifier 50 with offset cancellation mechanism, respectively, in which FIG. 5 is the configuration of the operational amplifier 50 in normal operation mode, and FIG. 6 is the configuration of the operational amplifier 50 in offset cancellation mode. The operational amplifier 50 includes transconductance amplifiers 52 and 56 having their outputs 5206, 5208 and 5606, 5608 connected together respectively, an output stage 54 having inputs 5402 and 5404 respectively connected to the outputs 5206, 5606 and 5208, 5608, and outputs 5406 and 5408 respectively connected to outputs 5006 and 5008 of the operational amplifier 50, switches S1 and S2 connected between two inputs 5202 and 5204 of the transconductance amplifier 52 and a voltage source VCM, respectively, switches S3 and S4 connected between inputs 5002 and 5004 of the operational amplifier 50 and the inputs 5202 and 5204 of the transconductance amplifier 52, respectively, switches S5 and S6 connected between the outputs 5406 and 5408 of the output stage 54 and inputs 5602 and 5604 of the transconductance amplifier 56, respectively, and capacitors C1 and C2 connected between the inputs 5602 and 5604 of the transconductance amplifier 56 and a ground terminal GND.
FIG. 7 shows the circuit of the operational amplifier 50 in detail. In the offset cancellation mode, as shown in FIGS. 6 and 7, the switches S1, S2, S5 and S6 are on and the switches S3 and S4 are off. Therefore, the inputs 5202 and 5204 of the transconductance amplifier 52 are supplied with the voltage VCM, and the inputs 5602 and 5604 of the transconductance amplifier 56 are connected to the outputs 5406 and 5408 of the output stage 54 respectively. The transconductance amplifier 52 includes a differential input pair that establishes currents I1 and I2 in the outputs 5206 and 5208 according to the voltages at the inputs 5202 and 5204. In the output stage 54, current sources 5410 and 5412 are connected to the inputs 5402 and 5404 of the output stage 54 respectively, to source equal currents I3 and I4 that are partially sink by the transconductance amplifier 52 by the currents I1 and I2 so as to leave currents I5 and I6. However, even the inputs 5202 and 5204 of the transconductance amplifier 52 are connected to the same voltage source VCM, due to the offset voltage VOS in the input 5202 of the transconductance amplifier 52, the currents I1 and I2 are actually unequal to each other and consequently, the currents I5 and I6 are unequal to each other. As a result, the voltages at the outputs 5406 and 5408 of the output stage 54 are unequal to each other. The capacitors C1 and C2 store the voltages at the outputs 5406 and 5408 of the output stage 54 respectively, and the transconductance amplifier 56 includes a differential input pair that sinks currents I7 and I8 from the inputs 5402 and 5404 of the output stage 54 according to the voltages at the outputs 5406 and 5408 of the output stage 54, so as to make the currents I5 and I6 equal to each other. Then, the operational amplifier 50 is switched to the normal operation mode, where the switches S3 and S4 are on and the switches S1, S2, S5 and S6 are off, as shown in FIG. 5. In this state, the voltages stored in the capacitors C1 and C2 will make the transconductance amplifier 56 sinking the currents I7 and I8 to cancel the effect caused by the offset voltage VOS. However, the operational amplifier 50 is a two-ended operational amplifier, so it is inapplicable to the current regulators 10 and 30 shown in FIGS. 1 and 2 respectively.
Therefore, it is desired a single-ended operational amplifier which is offset cancelled.

Offset cancellation of a single-ended operational amplifier


The invention relates to a method of contraception, which method comprises administering to a woman in need thereof an emergency contraception during one or two days, followed by a prolonged low dosage contraceptive treatment until next menstrual period.

Emergency contraception (EC) refers to back-up methods for contraceptive emergencies which women can use within the first few days after unprotected intercourse to prevent an unwanted pregnancy. The WHO-recommended regimen for emergency contraception is 1.5 mg levonorgestrel as a single dose. According to WHO, emergency contraceptives are usually not suitable for regular use (WHO. Medical eligibility criteria for contraceptive use. Third edition. Geneva, 2004; WHO. Selected practice recommendations for contraceptive use. Second edition. Geneva, 2005).
Conventional oral contraceptive (OC) starting instructions require waiting until menses to begin the OC. When a woman requires birth control at an office visit occurring between menses, many physicians delay starting hormonal contraceptives. However delaying contraception may place women at risk of unintended pregnancy until following menses. For this reason, it was proposed taking hormonal birth control products immediately after an office visit, at any point in the menstrual cycle, according to a "Quick Start" method (Lesnewski and Prine, Am Fam Physician, 2006, 74:105-12; Westhoff et al, Contraception, 2002, 66(3):141-5).
One important role emergency contraception pills could play is to serve as a gateway to longer-term method use (Don Downing presentation on behalf of the SC Emergency Contraception initiative, Mar. 12-16, 2007). In an over-the counter (OTC) environment e.g. where EC pills are accessed at pharmacies or drugstores and not family planning clinics, this may be more difficult to implement since there is no required visit to a clinician. Programs have then been developed in order to propose regular contraception to women using EC (ECAfrique bulletin, January 2008 vol 5/1).


A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer (156) is formed against an edge (137) of a layer of bottom electrode/copper diffusion barrier material (136), an edge (151) of a layer of capacitor dielectric material (150) and at least some of an edge (153) of a layer of top electrode material. The sidewall spacer (156) is dielectric or non-conductive and mitigates “shorting” currents that can develop between the plates as a result of copper diffusion. Bottom electrode diffusion barrier material (136) mitigates copper diffusion and/or copper drift, thereby reducing the likelihood of premature device failure.

In the manufacture of semiconductor products such as integrated circuits, individual electrical devices are formed on or in a semiconductor substrate, and are thereafter interconnected to form circuits. Interconnection of these devices is typically accomplished by forming a multi-level interconnect network in and through one or more dielectric or non-conductive layers that are formed over the electrical devices to electrically isolate the devices from one another. A conductive material, such as copper, is deposited into vias and/or trenches formed within these dielectric layers to connect the devices and thereby establish the multi-level interconnect network.
MIM (metal insulator metal) capacitors are semiconductor devices that are formed by sandwiching a thin layer or film of dielectric material between two layers of conductive material, usually metals. The metal layers can be said to comprise some or all of top and bottom electrodes, respectively, of the capacitor. Generally the bottom electrode is in contact with a conductive copper via or trench, which can also be said to comprise some of the bottom electrode of the capacitor. At times, however, the copper can diffuse from one electrode through the dielectric layer to the other electrode and "short out" or provide a conductive pathway between the two metal layers. This can substantially compromise the capacitor's ability to perform its intended function of storing charge. This deleterious effect is only enhanced through normal operation of the capacitor as the electric field induced during operation naturally enhances the undesired transport of copper from one electrode to the other. It is therefore necessary to ensure that the MIM capacitor is designed in such a manner that the functionality of the capacitor is maintained for the required lifetime of the device and that the diffusion and/or transport of copper through the dielectric layer is sufficiently controlled or eliminated to ensure such required lifetime.
It can be appreciated that several trends presently exist in the electronics industry. Devices are continually getting smaller, faster and requiring less power, while simultaneously being able to support and perform a greater number of increasingly complex and sophisticated functions. One reason for these trends is an ever increasing demand for small, portable and multifunctional electronic devices. For example, cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market. These devices rely on one or more small batteries as a power source and also require an ever increasing computational speed and storage capacity to store and process data, such as digital audio, digital video, contact information, database data and the like.
Accordingly, there is a continuing trend in the semiconductor industry to manufacture integrated circuits (ICs) with higher densities. To achieve high densities, there has been and continues to be efforts toward scaling down dimensions (e.g., at submicron levels) on semiconductor wafers. In order to accomplish such high densities, smaller feature sizes, smaller separations between features and layers, and/or more precise feature shapes are required. The scaling-down of integrated circuit dimensions can facilitate faster circuit performance and/or switching speeds, and can lead to higher effective yield in IC fabrication by providing more circuits on a semiconductor die and/or more die per semiconductor wafer, for example.
As device sizes continue to shrink, however, the close proximity of certain areas can lead to undesirable results. With regard to MIM capacitors, for example, bringing the metal layers closer together by reducing the thickness of the thin dielectric film can allow diffused copper to more readily short out the capacitor thereby compromising the capacitor's reliability and useful life. Still, a thin dielectric layer remains desirable as the capacitance, or ability of a capacitor to store charge, changes as a function of the distance between the metal plates, among other things. In particular, the capacitance goes up as the plates are brought closer together, but decreases as the plates are moved further apart. Accordingly, it would be desirable to fabricate a MIM capacitor in a manner that mitigates adverse effects associated with copper diffusion while concurrently allowing the size of the device to be reduced.

Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode


There is provided a boot block flash memory control circuit for controlling a boot block flash memory, the boot block flash memory including at least one symmetrical block each having a first capacity and a plurality of asymmetrical blocks each having a capacity smaller than the first capacity. The boot block flash memory control circuit detects a first address signal designating an address in the boot block flash memory and a first command signal for causing the boot block flash memory to operate, and based on the detected first address signal and first command signal, outputs a second command signal and a second address signal for erasing data stored in one of the at least the one symmetrical block or a subset of the plurality of asymmetrical blocks.

1. Field of the Invention
The present invention relates to a semiconductor memory device (e.g., an IC memory card) utilizing a boot block flash memory; a boot block flash memory control circuit used for such a semiconductor memory device; and an erasure method for a boot block flash memory.
2. Description of the Related Art
Flash memories can be classified into symmetrical block flash memories and boot block flash memories. A symmetrical block memory includes xe2x80x9csymmetrical blocksxe2x80x9d, i.e., blocks having the same capacity. A boot block flash memory includes both symmetrical blocks and boot blocks, such that each boot block has a different capacity from that of each symmetrical block. Conventionally, a majority of flash memory-based IC memory cards, as shown in FIG. 12A, adopt a symmetrical block flash memory structure having symmetrical blocks of e.g., 64 kbytes. Therefore, conventional IC memory card applications often incorporate card controlling software intended for such IC memory cards of a symmetrical block flash memory type. Such card controlling software is not intended for IC memory cards of a boot block flash memory type.
Accordingly, there is a problem in that a majority of IC memory card applications on the market, whose card controlling software cannot be updated, can only utilize IC memory cards of a symmetrical block flash memory type.
Furthermore, an IC memory card of a boot block flash memory type as shown in FIG. 12B, may have a different boot block size (capacity) from manufacturer to manufacturer. Therefore, each IC memory card product requires a specially-designed data rewriting program. This requirement detracts from their versatility.
Hence, in order for IC memory cards to be versatile, they need to utilize symmetrical block flash memories. Thus, IC memory cards of a symmetrical block flash memory type may be versatilely used with respect to IC memory card applications which are adapted thereto; however, there still remains a problem with IC memory cards of a boot block flash memory type, in that such IC memory cards cannot be versatilely used.
Accordingly, a semiconductor memory device is proposed in Japanese Laid-Open Publication No. 6-119230, for example, in which a boot block mode and a symmetrical block mode are switchable so that either a symmetrical block flash memory portion or a boot block flash memory portion thereof can be used at a time, as shown in FIGS. 13A and 13B.
However, the technique disclosed in Japanese Laid-Open Publication No. 6-119230 requires both a boot block memory and a symmetrical block memory to be provided on a chip, resulting in the problem of increased chip area and hence increased cost.
On the other hand, Japanese Laid-Open Publication No. 10-241377 discloses a semiconductor memory device featuring a boot block flash memory in which the same address counter is used for designating cells in both symmetrical blocks and irregular blocks (i.e., boot blocks), thereby attempting to reduce the scale of the circuitry.
However, when performing a block erasure, the technique disclosed in Japanese Laid-Open Publication No. 10-241377 cannot change the size of the block to be erased; i.e., the boot blocks cannot be operated in the same fashion as symmetrical blocks. As a result, this boot block flash memory is not interchangeable with a symmetrical block flash memory. Another problem associated with conventional IC memory cards is that, when erasing data in a plurality of boot blocks in an IC memory card of a boot flash memory type, a host system must designate individual ones of the plurality of boot blocks, and it is necessary to issue plural instances of an erase command.
According to one aspect of the present invention, there is provided a boot block flash memory control circuit for controlling a boot block flash memory, the boot block flash memory including at least one symmetrical block each having a first capacity and a plurality of asymmetrical blocks each having a capacity smaller than the first capacity, wherein: the boot block flash memory control circuit detects a first address signal designating an address in the boot block flash memory and a first command signal for causing the boot block flash memory to operate, and based on the detected first address signal and first command signal, outputs a second command signal and a second address signal for erasing data stored in one of the at least the one symmetrical block or a subset of the plurality of asymmetrical blocks.
In one embodiment of the invention, a total capacity of the subset of asymmetrical blocks is equal to the first capacity of the at least one symmetrical block.
In another embodiment of the invention, while data stored in the subset of asymmetrical blocks is erased, a READY signal and an operation status signal, which are similar to a READY signal and an operation status signal to be output when data stored in one of the at least one symmetrical block is erased, are output.
In still another embodiment of the invention, the boot block flash memory control circuit further includes : a boot block address detection circuit for detecting a first block designating address signal which designates the subset of asymmetrical blocks and outputting a first signal based on the first block designating address signal; a command detection circuit for outputting a second signal based on the first signal, a first block erase command signal for erasing data stored in the subset of asymmetrical blocks, and a first control signal; and an address/command generation circuit for outputting the second address signal and the second command signal to the subset of asymmetrical blocks based on the second signal and a second control signal from the boot block flash memory.
In still another embodiment of the invention, the boot block flash memory control circuit further includes a READY signal/status signal control circuit for outputting a signal indicating an erasure state while the subset of asymmetrical blocks are erased.
In still another embodiment of the invention, at least one of the plurality of asymmetrical blocks includes a boot block or a parameter block.
According to another aspect of the present invention, there is provided an IC memory card including: a boot block flash memory; and an interface IC for controlling the boot block flash memory based on an external signal, wherein the interface IC includes the aforementioned boot block flash memory control circuit.
In one embodiment of the invention, in a memory space of the boot block flash memory, a plurality of asymmetrical blocks in the boot block flash memory are decoded to an address region which is substantially unlikely to be accessed.
In another embodiment of the invention, in a memory space of the boot block flash memory, a plurality of asymmetrical blocks in the boot block flash memory are decoded so as to be deleted from the memory space.
According to yet another aspect of the present invention, there is provided a semiconductor memory device including: a host system; a boot block flash memory; and a boot block flash memory control circuit for controlling the flash memory based on a signal from the host system, wherein the boot block flash memory control circuit is the aforementioned boot block flash memory control circuit.
According to yet another aspect of the present invention, there is provided a method for erasing data stored in a boot block flash memory including a plurality of asymmetrical blocks, including the steps of: outputting a first signal based on a first block designating address signal which indicates a block designating address of a subset of the plurality of asymmetrical blocks input from the host system; outputting a second signal based on the first signal, a first block erase command signal, and a first control signal; outputting a second block designating address signal and a second block erase command signal to the boot block flash memory, based on the second signal and a second control signal from the boot block flash memory; and outputting to the host system a signal indicating an erasure state of the boot block flash memory while erasing data stored in a subset of a plurality of asymmetrical blocks in the boot block flash memory.
In one embodiment of the invention, the plurality of asymmetrical blocks are decoded in such a manner that erasure of data stored in the plurality of asymmetrical blocks is prohibited irrespective of the first block designating address signal which is input from the host system.
Hereinafter, the effects of the present invention will be described.
According to the present invention, in order to make it possible to utilize a boot block flash memory in the same manner as a symmetrical block flash memory, a boot block flash memory control circuit is provided in an interface portion of a boot block flash memory. When a first erase command signal and a first address signal are issued from a host system, the boot block flash memory control circuit can detect that the address signal designates a subset of a plurality of asymmetrical blocks. Then, the boot block flash memory control circuit outputs a second address signal and a second erase command signal for performing a data erasure for the subset of asymmetrical blocks. As a result, as described in Example 1 below, the data stored in the subset of asymmetrical blocks can be erased by only a single instance of a first erase command signal issued from a host system. The host system is not required to issue a plurality of instances of the first block erase command signal while switching the first block designating address signal, unlike in conventional systems. Moreover, the host system can deal with a subset of a plurality of asymmetrical blocks as if one virtual block.
According to the present invention, it is preferable to perform a data erasure for a number of asymmetrical blocks so that the combined capacity of such asymmetrical blocks becomes equal to the capacity of each symmetrical block present in the boot block flash memory. As a result, as described in Example 2 below, the size of the blocks to be erased can be unified, so that operations on an IC memory card including boot blocks can properly take place by employing a host system containing software which is designed for IC memory cards of a symmetrical block flash memory type. In this case, the asymmetrical blocks within such a group of combined asymmetrical blocks can be erased in a sequential manner.
Furthermore, according to the present invention, all of asymmetrical blocks in a boot block flash memory may be decoded to address regions within a memory space which are least likely to be accessed by a host system. In this case, as described in Example 3 below, all asymmetrical blocks can be concentrated in regions within the memory space of the IC memory card which are least likely to be accessed by a host system, but the host system can still access the boot blocks. When a user uses an IC memory card, there is a general tendency that the memory space is accessed beginning from the first address. Therefore, by ensuring that the asymmetrical blocks are decoded to the vicinity of the last address in the memory space, the probability of the asymmetrical blocks being made any use of is advantageously minimized.
On the other hand, the block erase time required for a symmetrical block is four times as long as the block erase time required for a virtual symmetrical block (in which asymmetrical blocks are sequentially erased). By placing the asymmetrical blocks in the vicinity of the last address, which is less likely to be accessed, any deterioration in performance which would otherwise occur can be prevented.
Alternatively, according to the present invention, an asymmetrical block section may be decoded so as to be deleted from the memory space (hereinafter such decoding will be referred to as a xe2x80x9cdeletion-decodexe2x80x9d), so that a host system cannot access the asymmetrical blocks in a boot block flash memory corresponding to addresses which are input from the host system. In this case, as described in Example 4 below, the asymmetrical blocks are deleted from the memory space of the IC memory card, so that the host system is prevented from accessing the boot block section.
As described above, the block erase time required for a symmetrical block is four times as long as the block erase time required for a virtual symmetrical block (in which asymmetrical blocks are sequentially erased). Therefore, card controlling software which is designed for IC memory cards of a symmetrical block flash memory type may run the risk of overflowing a wait time which is associated with an erase time for a particular IC memory card. Accordingly, an IC memory card can be constructed which has a memory space only including symmetrical blocks and no asymmetrical block sections, whereby operations can occur satisfactorily.
Furthermore, according to the present invention, while a subset of a plurality of asymmetrical blocks are being subjected to a data erasure, a READY signal and an operation status signal similar to those used while a host system is performing a data erasure for a symmetrical block may be output to the host system. As a result, as described in Example 5 below, the data erasure for the subset of asymmetrical blocks appears to the host system as if an erase operation for a single symmetrical block.
Thus, the invention described herein makes possible the advantages of: (1) providing a boot block flash memory control circuit which, with an erase command signal for erasing data in one symmetrical block of a boot block flash memory, is capable of erasing data in a plurality of asymmetrical blocks, and which can avoid increase in the chip area of a single flash memory structure; an IC memory card and a semiconductor memory device incorporating such a boot block flash memory control circuit; and an erasure method for the boot block flash memory, and (2) providing a boot block flash memory control circuit which allows a plurality of asymmetrical blocks to be operated as symmetrical blocks, and which allows IC memory cards to be versatilely used with conventional IC memory card applications in the same fashion as a symmetrical block flash memory; an IC memory card and a semiconductor memory device incorporating such a boot block flash memory control circuit; and an erasure method for the boot block flash memory.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.

Boot block flash memory control circuit; IC memory card and semiconductor memory device incorporating the same; and erasure method for boot block flash memory