A method and apparatus are described for controlling the flow of power in each input line to a three phase AC inductive load in order to reduce the amount of VAR in the system, and thus increase the operational efficiency of the inductive load. Solid state relays are positioned in series in each of the three inductive load line inputs, and current allowed to flow to the inductive load only during the time during which the SSRs are in a conducting state. The calculation of VAR is achieved by processing data from each of the input lines using a separate controller boards each dedicated to each of the lines. The controller in turn, based on the calculated VAR, increments the time, either increasing or decreasing it from a predetermined value, during which the SSRs in that line remains in the non-conducting state.

1. Field of the Invention
This invention relates methods and apparatus for controlling the input to 3-phase alternating current (AC) induction motors. More particularly it relates to methods and apparatus for separately controlling the power being supplied through each of the three input lines to such a motor, using dedicated circuits to calculate the measure of reactive power and adjust the time during which solid state relays connected in series in each of the lines are maintained in a non-conducting state.
2. Description of the Related Art
It is well known that power is wasted when an alternating current (AC) induction motor is operated under a load below its rated load, or under a varying load. It is also well know that inherent in the operation of a three-phase alternating current induction motor is the presence of reactive power, expressed as voltamps reactive (VAR), the measure of VAR related to the operational inefficiency of the motor. The greater the VAR, the greater the loss of power in the system.
The presence of VAR is caused in part by the natural inductance of the motor windings, and the interaction of motor rotor and windings, which effects tend to exert a counter force to the flow of power to the system. Power in turn is the product of the instantaneous current (measured in amperes) times the instantaneous voltage (measured in volts) traveling in a wire connected to a motor. When voltage and current values are plotted on a point by point basis, with, for example, a vertical axis Y representing magnitude and a horizontal axis X representing time, separate waveforms are generated for both voltage and current. Generally sinusoidal, over a full current cycle, the separate wave forms for current and voltage during one half cycle will be on the positive side of X axis, and during the other half cycle will be on the negative side of the X axis. These same waveforms may also contain multiple harmonics. In the case of the three-phase motor when current and voltage are plotted together, because of the inductance, and generated voltamps reactance of the motor resulting from the movement of the rotor relative to the motor windings, this inherent "backpressure" causes the current waveform to lag the voltage waveform.
When the voltage and current values are taken from their respective waveforms and multiplied on a point by point basis along the X axis, a voltamp (VA) waveform is generated. When plotted along the X and Y axis, the VA waveform will generally have mostly positive values, and to a lesser extent negative values with reference to the X axis. During that period of operation where the VA waveform takes on a negative value and lies below the X axis, there is a loss of power being sent to the motor. It is this negative part of the waveform which lies below the X axis which is a measure of the voltamps reactive (VAR).
Previous attempts to increase the operating efficiency of AC induction motors are described in various U.S. patents, including U.S. Pat. Nos. 4,439,718 and 4,052,648 to Nola, U.S. Pat. No. 4,379,258 to Sugimoto and U.S. Pat. No. 5,134,356 to El Sharkawi et al.
Another approach is described in U.S. Pat. No. 6,737,827 to Cashatt, this patent commonly assigned to Enviro World Systems, Inc., and incorporated herein by reference. In Cashatt, a method and apparatus is disclosed to control the input to both single and three phase motors using a single microprocessor to manage the control circuits and calculate the time when the conducting state of in-line, solid state relays are to be changed from non-conducting to conducting. By controlling the timing of the change, the inventor therein was able to bring the voltage and current waveforms closer together, to thus reduce the amount of VAR generated, and thereby increase motor efficiency.
In practice, in the case of a three phase system it has been found that the calculations required to be performed by the microprocessor is substantial, and thus the operational speed by which calculations can be conducted for each of the three input lines limits the frequency by which the solid state relays (SSRs) can be switched on and off. In addition, the sum of the instantaneous current and voltage values in each of the three lines may vary, and thus inaccuracies in calculated values can result when these variations are not taken into account. Accordingly, there remains a need to improve the degree of control in the switching of the SSRs from the non-conducting to the conducting state in order to improve the operational efficiency of the motor being managed.

Method and apparatus using VAR measurements to control power input to a three-phase induction motor circuit


A surgical scissors instrument having disposed at its distal end two bipolar electrode structures which function to coagulate tissue immediately prior to its being severed by scissor action. The instrument comprises a first scissors blade having a distal end and a second scissors blade having a distal end, wherein at least one of the blades is pivotable in relation to the other blade. A first electrically insulated bipolar electrode structure is disposed longitudinally distally from the distal end of the first scissors blade, and a second electrically insulated bipolar electrode structure is disposed longitudinally distally from the distal end of the second scissors blade. The instrument thereby permits a physician to precisely apply electrical energy only at the distal end of the scissor's blades, and to thereafter immediately cut coagulated tissue situated immediately forward of the blade members.

This invention relates in general to surgical scissors, and in particular to a surgical scissors instrument having cooperating cutting blades and disposed at their distal ends are two forceps jaws comprising bipolar electrode structures which can function to coagulate tissue immediately prior to its being severed by scissor action of the cutting blades
Electrocauterization is a process whereby blood vessels (commonly called "bleeders") in tissue or alone which are cut during a surgical procedure are sealed closed by applying electrical energy at the site to, essentially, fuse by heat the vessel opening. To provide electrical energy at the site of bleeding, an instrument capable of conducting electricity must be placed at that site. The conductive instrument may be comprised of one electrode (monopolar) which cooperates with a remote conductive body plate electrode, or the instrument may be comprised of two closely spaced electrodes (bipolar). Current passing from one electrode to the other produces the heat sufficient to seal blood vessels or to coagulate blood and other fluids so coagulable. A bipolar instrument is generally preferred by a physician since current travel is over a short distance and is predictable. A monopolar instrument usually requires electric current to travel a relatively long distance to the body plate electrode, with current directability and effect being unpredictable and possibly harmful to a patient.
Electrosurgical scissors and electrosurgical forceps individually are known in the art. Additionally, in U.S. Pat. No. 5,342,381, issued Aug. 30, 1994, commonly assigned and incorporated herein by reference, the applicant thereof describes a combination bipolar scissors and forceps instrument comprising two blade members which are configured to form forceps jaws at their distal ends and scissors blades proximal to the jaws. The entire blade members, both forceps and scissors portions, are electrically conductive, with the scissors blades electrically insulated from each other along their interfacing surfaces. Thus, both the forceps portion and the scissors portion function to coagulate tissue.
While the combination scissors and forceps instrument described above is highly effective in most surgical procedures, a physician may desire a concentration of electrical energy only at the distal ends or tips of a scissors instrument instead of having electrical energy present in the entire blade structures. Delivery of energy only distally permits the physician to exercise a more precise control of coagulation activity.
It is therefore a primary object of the present invention to provide a surgical scissors instrument having at its distal end bipolar electrode structures which function to coagulate tissue immediately prior to tissue severance by the blades of the scissors which are electrically passive.
Another object of the present invention is to provide a surgical scissors instrument wherein distally-disposed electrode structures extend distally from respective electrically insulated housings which also have secured thereto the cutting blades of the scissors.
Yet another object of the present invention is to provide a surgical scissors instrument wherein distally-disposed electrode structures additionally function as jaws of a forceps.
These and other objects of the present invention will become apparent throughout the description which follows.

Surgical scissors with bipolar distal electrodes


Systems, methods, apparatus and software can implement a multipathing driver using dynamically loadable device policy modules that provide device specific functionality for providing at least one of input/output (I/O) operation scheduling, path selection, and I/O operation error analysis. Because the device policy modules include device specific functionality, various different devices from different manufacturers can be more efficiently and robustly supported.

Distributed computing systems are an increasingly important part of research, governmental, and enterprise computing systems. Among the advantages of such computing systems are their ability to handle a variety of different computing scenarios including large computational problems, high volume data processing situations, and high availability situations. Such distributed computing systems typically utilize one or more storage devices in support of the computing systems operations. These storage devices can be quite numerous and/or heterogeneous. In an effort to aggregate such storage devices and to make such storage devices more manageable and flexible, storage virtualization techniques are often used. Storage virtualization techniques establish relationships between physical storage devices, e.g. disk drives, tape drives, optical drives, etc., and virtual or logical storage devices such as volumes, virtual disks, and virtual logical units (sometimes referred to as virtual LUNs). In so doing, virtualization techniques provide system-wide features, e.g., naming, sizing, and management, better suited to the entire computing system than those features dictated by the physical characteristics of storage devices. Additionally, virtualization techniques enable and/or enhance certain computing system operations such as clustering and data backup and restore.
FIG. 1 illustrates a simplified example of a computing system 100. The members of the computing system 100 include host 130 and host 140. As members of computing system 100, hosts 130 and 140, typically some type of application, data, or file server, are often referred to "nodes." Hosts 130 and 140 can be designed to operate completely independently of each other, or may interoperate to form some manner of cluster. Thus, hosts 130 and 140 are typically individual computer systems having some or all of the software and hardware components well known to those having skill in the art. FIG. 8 (described below) illustrates some of the features common to such computer systems. In support of various applications and operations, hosts 130 and 140 can exchange data over, for example, network 120, typically a local area network (LAN), e.g., an enterprise-wide intranet, or a wide area network (WAN) such as the Internet. Additionally, network 120 provides a communication path for various client computer systems 110 to communicate with hosts 130 and 140. In addition to network 120, hosts 130 and 140 can communicate with each other over a private network (not shown).
Other elements of computing system 100 include storage area network (SAN) 150 and storage devices such as tape library 160 (typically including one or more tape drives), a group of disk drives 170 (i.e., "just a bunch of disks" or "JBOD"), and intelligent storage array 180. As shown in FIG. 1, both hosts 130 and 140 are coupled to SAN 150. SAN 150 is conventionally a high-speed network that allows the establishment of direct connections between storage devices 160, 170, and 180 and hosts 130 and 140. SAN 150 can also include one or more SAN specific devices such as SAN switches, SAN routers, SAN hubs, or some type of storage appliance. Thus, SAN 150 is shared between the hosts and allows for the sharing of storage devices between the hosts to provide greater availability and reliability of storage. Although hosts 130 and 140 are shown connected to storage devices 160, 170, and 180 through SAN 150, this need not be the case. Shared resources can be directly connected to some or all of the hosts in the computing system, and computing system 100 need not include a SAN. Alternatively, hosts 130 and 140 can be connected to multiple SANs.
FIG. 2 illustrates in greater detail several components of computing system 100. For example, disk array 180 is shown to include two input/output (I/O) ports 181 and 186. Associated with each I/O port is a respective storage controller (182 and 187), and each storage controller generally manages I/O operations to and from the storage array through the associated I/O port. In this example, each storage controller includes a processor (183 and 188), a cache memory (184 and 189) and a regular memory (185 and 190). Although one or more of each of these components is typical in disk arrays, other variations and combinations are well known in the art. The disk array also includes some number of disk drives (logical units (LUNs) 191–195) accessible by both storage controllers. As illustrated, each disk drive is shown as an LUN which is generally an indivisible unit presented by a storage device to its host(s). Logical unit numbers, also sometimes referred to as LUNs, are typically assigned to each disk drive in an array so the host can address and access the data on those devices. In some implementations, an LUN can include multiple devices, e.g., several disk drives, that are logically presented as a single device.
FIG. 2 also illustrates some of the software and hardware components present in hosts 130 and 140. Both hosts 130 and 140 execute one or more application programs (131 and 141) respectively. Such applications can include, but are not limited to, database administration systems (DBMS), file servers, application servers, web servers, backup and restore software, customer relationship management software, and the like. The applications and other software not shown, e.g., operating systems, file systems, and applications executing on client computer systems 110 can initiate or request I/O operations against storage devices such as disk array 180. Hosts 130 and 140 also execute volume manager (133 and 143) which enables physical resources configured in the computing system to be managed as logical devices. An example of software that performs some or all of the functions of volume manager 330 is the VERITAS Volume Manager™ product provided by VERITAS Software Corporation. Hosts 130 and 140 take advantage of the fact that disk array 180 has more than one I/O port using dynamic multipathing (DMP) drivers (135 and 145) as well as multiple host bus adaptors (HBAs) 137, 139, 147, and 149. The HBAs provide a hardware interface between the host bus and the storage network, typically implemented as a Fibre Channel network. Hosts 130 and 140 each have multiple HBAs to provide redundancy and/or to take better advantage of storage devices having multiple ports.
The DMP functionality enables greater reliability and performance by using path failover and load balancing. In general, the multipathing policy used by DMP drivers 135 and 145 depends on the characteristics of the disk array in use. Active/active disk arrays (A/A arrays) permit several paths to be used concurrently for I/O operations. Such arrays enable DMP to provide greater I/O throughput by balancing the I/O load uniformly across the multiple paths to the disk devices. In the event of a loss of one connection to an array, the DMP driver automatically routes I/O operations over the other available connections to the array. Active/passive arrays in so-called auto-trespass mode (A/P arrays) allow I/O operations on a primary (active) path while a secondary (passive) path is used if the primary path fails. Failover occurs when I/O is received or sent on the secondary path. Active/passive arrays in explicit failover mode (A/PF arrays) typically require a special command to be issued to the array for failover to occur. Active/passive arrays with LUN group failover (A/PG arrays) treat a group of LUNs that are connected through a controller as a single failover entity. Failover occurs at the controller level, and not at the LUN level (as would typically be the case for an A/P array in auto-trespass mode). The primary and secondary controller are each connected to a separate group of LUNs. If a single LUN in the primary controller's LUN group fails, all LUNs in that group fail over to the secondary controller's passive LUN group.
Implementation of the above-described multipathing policies depends in large part on the specific hardware present in the storage devices in use. Where there is sufficient commonality among the storage devices to be supported, or where only a single type of storage device is to be supported, implementation of theses multipathing policies is relatively straight forward. However, in heterogeneous environments where storage devices of different types, different models, and/or from different manufactures are present and/or anticipated, multipathing support will typically need to rely on implementations specific to the various different devices.
Accordingly, it is desirable to have efficient and convenient mechanisms for providing multipathing functionality that is specific to particular storage devices without having to provide completely separate multipathing drivers for each supported storage device.

System and method for dynamically loadable storage device I/O policy modules


A ferroelectric liquid crystal display device comprising a substrate of a plurality of scanning electrodes and a plurality of signal electrodes in the form of a matrix, a switching device formed at each intersecting point of the electrodes, a liquid crystal cell injected with a ferroelectric liquid crystal and a drive controlling means which can apply a signal having a polarity opposite to that of the signal corresponding to a required display from the signal electrode in synchronization with that the signal is applied from the scanning electrode to turn the switching device ON; apply a signal corresponding to the required display from the signal electrode in synchronization with that the signal is applied again from the scanning electrode after a predetermined period of time to turn the switching device ON; and apply a signal from the signal electrode so that the voltage applied to the liquid crystal may be zero in synchronization with that the signal is applied again from the scanning electrode after a predetermined period of time to turn the switching device ON.

1. Field of the Invention
The present invention relates to a ferroelectric liquid crystal display device and more particularly, to a liquid crystal display device combining a switching device and a ferroelectric liquid crystal.
2. Description of the Relates Art
A liquid crystal display device is largely used in a watch, an electronic calculator, a word processor, a personal computer, a pocket television or the like. Recently, a display device of high quality which is capable of large-amount displaying has been especially demanded. As such a display device of high quality, a liquid crystal display device is generally known, which is formed by combining an active matrix substrate on which a thin film transistor (TFT) is arranged in the form of matrix with a twisted nematic (TN) liquid crystal.
However, a serious defect of the liquid crystal display device is that its visual angle is narrow. This problem is peculiar to the TN display. Therefore, as long as this display method is used, the defect can not be really improved. In addition, there is a strong demand for decreasing a driving voltage in respect of economical aspect.
Meanwhile, a visual angle is wide in a ferroelectric liquid crystal. Since the ferroelectric liquid crystal does not have a clear threshold value, if a pulse width for switching is increased, the driving voltage can be decreased theoretically. However, there is the following defect in the normal ferroelectric liquid crystal display device, high contrast is not likely to be obtained because of molecular fluctuation due to a bias voltage.
Thus, it is proposed that the ferroelectric liquid crystal is combined with the active matrix substrate in order to implement a liquid crystal display device in which the visual angle is wide, the driving voltage is low, and the contrast is high.
The ferroelectric liquid crystal display device (Appl. Phys. Lett., 36, 899 (1980); Japanese Opened Patent No. 107216/1981; U.S. Pat. No. 4,367,924) uses a ferroelectric liquid crystal such as a chiral smectic C phase, a chiral smectic F phase or a chiral smectic I phase. Although the ferroelectric liquid crystal has a herical structure, it is found that the helical structure is broken if the ferroelectric liquid crystal is sandwiched between liquid crystal cells having a cell thickness thinner than its herical pitch. Actually, as shown in FIG. 1, it is found that a region where a liquid crystal molecule is inclined from a normal line of a smectic layer by an angle of .theta. to be stable and a region where it is inclined in the opposite direction by an angle of .theta. to be stable can exist together. When an electric field is applied in the direction perpendicular to the surface of FIG. 1, the directions of the liquid crystal molecule and its spontaneous polarization can be uniformly arranged. Therefore, two states can be switched by changing the polarity of the electric field to be applied. Since bireferegent light is changed in the ferroelectric liquid crystal in the cell through the switching operation, transmitted light can be controlled by putting the ferroelectric liquid crystal display device between two polarizers. In addition, even if application of the voltage stops, since the orientation of the liquid crystal molecule is maintained at a state before the voltage is applied by orientation controlling force of an interface, a memory effect can be also obtained. In addition, in regard to a time required for driving the switching operation, a high-speed response of an order of .mu.sec can be obtained since the spontaneous polarization of the liquid crystal and the electric field directly act thereon.
FIG. 2 shows the relation between an applied voltage waveform in the ferroelectric liquid crystal display device in which the direction of the polarization axis of polarizing plates crossing at right angles with each other coincides with the direction of longitudinal axis of the molecule at one state of bistable states of the ferroelectric liquid crystal display device, and an amount of the transmitted light. Since the ferroelectric liquid crystal display device has a memory characteristic, preferable switching between two values can be implemented by applying a short pulse and maintaining an electroless state thereafter.
Next, the active matrix substrate will be described. FIG. 3 shows an equivalent circuit of an active matrix type liquid crystal display device using a thin film transistor (TFT) which is a typical 3-terminal type device.
Referring to FIG. 3, reference character G designates a gate electrode, reference character S designates a source electrode, reference character D designates a drain electrode, reference character V.sub.com designates a common electrode, and reference character LC designates a liquid crystal capacity. When the liquid crystal is driven, an electric field is applied to the gate electrode by applying a signal from a scanning line and then the TFT turns ON. In synchronization with this, when a signal is applied to the source electrode from a signal line, an electric charge is stored in the liquid crystal capacity through the drain electrode. Thus, the liquid crystal responds by the thus generated electric field.
In a case where the ferroelectric liquid crystal is employed to the active matrix type liquid crystal display, driving waveforms shown in FIGS. 4 and 5 are used.
However, according to the driving method shown in FIG. 4, for example, when display at a certain pixel is not changed for a long period of time, a voltage of the same polarity is applied to the ferroelectric liquid crystal of that pixel. This is a considerably big problem in view of reliability and it is almost impossible to manufacture a practical display device.
Meanwhile, according to the driving method shown in FIG. 5, the voltage applied to each pixel is not partial to minus nor plus, so that the method is thought preferable in view of reliability. However, the following problem is generated in view of a practical display device. That is, a pulse width required for switching the typical ferroelectric liquid crystal is approximately 100 .mu.sec at a room temperature when the voltage is 10V. Although a more high-speed ferroelectric liquid crystal has been reported, generally it is necessary to increase the spontaneous polarization of the ferroelectric liquid crystal in order to increase the switching speed of the display formed of a liquid crystal material. However, as the spontaneous polarization is increased, it is difficult to obtain preferable bistable switching operation. Since the driving voltage of the liquid crystal display device driven by the TFT is approximately 5V, when it is assumed that the driving voltage is 5V and the pulse width necessary for the switching is 200 .mu.sec, in the driving waveforms shown in FIG. 5, a writing time per scanning line is 600 .mu.sec. When the liquid crystal display device having 1000 scanning lines is implemented, a time required for rewriting one screen is 600 .mu.sec. If the driving voltage is decreased, that time is further increased. This is long as for the rewriting time. Therefore, this problem has to be improved in order to implement a large-capacity active matrix type ferroelectric liquid crystal display device of high quality.

Ferroelectric liquid crystal display device


A valve body is provided with at one end with a threaded shank for hermetic coupling to a gas container. The valve body is further provided with a handwheel incorporating a gas status indicator device. That device includes a spring-loaded plunger having a head and a helical stem that is engaged in a cavity of a rotatable body so that an axial movement of the plunger, in opposition to a spring biasing force, results in a rotation of the rotatable body. A visible portion of the rotatable body is marked so as to provide an indication of the axial position of the plunger relative to the handwheel, to thereby indicate gas pressure.

1. Field of the Invention
The present invention relates to a flow control valve with device for indicating the status of a fluid, particularly for gas containers.
2. Description of the Prior Art
As it is known, conventional cylinders or bottles containing liquefied or compressed gases are equipped with a valve for connecting the cylinder, either directly or by means of pressure reduction units, to the user devices to be supplied.
Those conventional devices allow to separate, when required, the user devices from the cylinder in which the fluid is contained.
In order to have an indication regarding the status of the fluid inside the cylinder, it is possible, by means of a connector, to connect a pressure gauge capable of indicating the level of pressure of the fluid.
However, that type of device protrudes externally from the body of the valve and is therefore exposed to accidental impacts that can compromise its operation, drastically lowering the safety level in using the cylinder to which it is applied.
In addition to what has been described above, a pressure sensing means is also known for checking the tightness of the system components that connect the cylinder to the user devices; this means still provides for the application of devices that are external with respect to the valve.
U.S. Pat. No. 6,182,692 discloses a valve unit that includes a pressure gauge integrated in the handwheel, and EP-A-0869310 discloses a tap for gas cylinders that includes a pressure gauge integrated in the knob.

Flow control valve with device for indicating the status of a fluid, particularly for gas containers


A method of making a semiconductor device includes the steps of etching, with a resist pattern (3) used as a mask, a contact pattern (4) in at least one interlayer insulation film (2) made on a silicon substrate (1); forming on the contact pattern an insulation film (5) containing silicon as a main component; and oxidizing by heat treatment the insulation film to provide an oxide film (6) including a side wall oxide film on an inside wall of the contact pattern.

1. Field of the Invention
The present invention relates to methods of making a semiconductor device (hereinafter xe2x80x9cLSI devicexe2x80x9d).
2. Description of the Related Art
An LSI device has many technical requirements such as high-speeds, low power consumption, versatile functions, and high integration degrees, and it is necessary to develop a circuit pattern which has no less functions and/or better electrical characteristics at a smaller occupied area than those of the current LSI devices.
In the process for making LSI devices, a number of treatments or photolithographic techniques (hereinafter xe2x80x9clithographic techniquesxe2x80x9d) are applied to the surface of a semiconductor silicon wafer (hereinafter xe2x80x9cwaferxe2x80x9d) to form a microscopic circuit pattern thereon.
A photoresist pattern corresponding to the circuit pattern formed by lithographic technique is used as a masking material to perform etching a thin film material or injecting an impurity ion. By repeating such treatments for a number of times, a desired LSI circuit pattern is formed.
However, the resolution with which the microscopic circuit pattern is formed in the lithographic technique and the circuit pattern is positioned on the layer is approaching the limit. Consequently, the formed photoresist pattern fails to meet the required working precision for the LSI circuit pattern.
In FIGS. 2(a) and 3(a), a silicon monocrystal substrate (hereinafter xe2x80x9csilicon substratexe2x80x9d) is indicated by reference numeral 21. A field oxide (SiO2) film 22 having a thickness of 2000-8000 xc3x85 is formed by the well known LOCOS process. A channel stopper or impurity diffusion region (not shown) is provided in the silicon substrate 21 to form an electrical insulation region.
An electrode pattern 23 is made from a polycrystal silicon (hereinafter xe2x80x9cpolysiliconxe2x80x9d) having a thickness of 1000-4000 xc3x85 or a film containing a metal of high melting point, such as tungsten, molybdenum, or titanium, or a eutectic film of silicon and a metal having a high melting point. A thin silicon oxide film (not shown) having a thickness of 50-500 xc3x85 is made under the electrode pattern 23.
An interlayer insulation or oxide film 24 having a thickness of 1000-8000 xc3x85 is formed. A photoresist film 25 is formed by the lithographic technique to provide a photoresist pattern 26. The photoresist film 25 is used as a mask to etch a contact pattern or hole 26xe2x80x2 in the interlayer insulation film 24.
Problems arising from the fact that the lithographic technique reaches its precision limit will be described with reference to FIGS. 2(b)-(d) and 3(b)-(d).
In FIGS. 2(b) and 3(b), the photoresist pattern 26a formed by the lithographic technique is slightly offset from the underground pattern to make contact with the electrode pattern 23.
Consequently, a portion of the contact pattern 26axe2x80x2 is formed on the edge of the electrode pattern 23. As a result, a wiring material formed within the contact pattern 26axe2x80x2 makes contact with the electrode pattern 23 as shown by A in FIG. 3(b), providing a electrical circuit failure or defect LSI device.
This problem results from the fact that the photoresist pattern 26a is formed at a slightly offset position by the lithographic technique. This problem has been negligible in making LSI devices having a circuit pattern dimension of 0.5 xcexcm or more. However, this problem is no longer negligible for a circuit pattern dimension of 0.4 xcexcm or less.
In FIGS. 2(c) and 3(c), the contact pattern 26 is slightly offset in the direction opposite to that of FIGS. 2(b) and 3(b). The contact pattern 26b formed on the photoresist film 25 is offset from the electrode pattern 23 and laid on the edge of the field oxide film 22. Consequently, the contact pattern 26bxe2x80x2 formed in the interlayer insulation film 24 cuts a portion of the field oxide film 22 as shown by B in FIG. 3(c). As a result, a portion of the channel stopper (not shown) formed under the field oxide film 22 is exposed.
When a wiring material is formed, the exposed portion is prone to an electrical leak to the silicon substrate 21, providing a defective LSI device.
In FIGS. 2(d) and 3(d), the contact pattern 26c formed on the photoresist film 25 is larger than the designed pattern.
Similarly to the problems in FIGS. 2(b), 2(c), 3(b), and 3(c), the wiring material formed within the contact pattern 26cxe2x80x2 makes connection with the electrode pattern 23 as shown by C in FIG. 3(d) or allows an electrical leak from the field oxide film 22 to the silicon substrate 21 as shown by Cxe2x80x2 in FIG. 3(d).
In addition, the precision problem, such as the too large contact pattern 26cxe2x80x2, reduces the tolerance for positioning offset so that the yield of LSI devices is reduced by both of the factors of positioning and dimension precision. A number of measures for minimizing these disadvantages have been proposed.
A representative example will be described with reference to FIGS. 4(a)-(d).
In FIG. 4(a), reference numeral 21 denotes a semiconductor substrate, 24 an interlayer insulation film, 25 a photoresist film, 26 a photoresist pattern formed in the photoresist film 25, and 26xe2x80x2 a contact pattern formed in the interlayer insulation film 24.
A substrate portion 21xe2x80x2 is exposed by etching the interlayer insulation film 24, and its surface is slightly damaged by the etching process. This damage is omitted in FIGS. 2(a)-(d) and 3(a)-(d).
In FIG. 4(b), the photoresist film 25 is removed.
In FIG. 4(c), an insulation film material or silicon oxide film 41 is formed on the interlayer insulation film 24 and within the contact pattern 26xe2x80x2 by the chemical vapor deposition (CVD) process to a thickness of 600-4000 xc3x85.
In FIG. 4(d), an anisotropic etching process is applied to the entire surface of the oxide film 41 to proceed in the perpendicular direction (hereinafter xe2x80x9cetchback processxe2x80x9d). Consequently, only the oxide films 41xe2x80x2 on the side walls of the contact pattern 26xe2x80x2 remain.
Consequently, the diameter of the contact pattern or hole 26xe2x80x2 is reduced by the side wall oxide films 41xe2x80x2 to thereby minimize the above problems in FIGS. 2 and 3. In this method, however, the silicon substrate portion 21xe2x80x3 is exposed again upon formation of the side wall oxide film 41xe2x80x2 so that the etching damage is accumulated.
In addition, the thickness of the side wall oxide film 41xe2x80x2 is determined by the thickness of the oxide film 41 formed by the CVD process, which in return determines the effective size of the final contact pattern 26xe2x80x2. Consequently, in order to minimize the problems of FIGS. 2 and 3 by reducing the size of the contact pattern 26xe2x80x2, it is desired to form a thick oxide film 41 by the CVD process.
However, the contact pattern 26xe2x80x2 itself is very small and can be formed too small to provide satisfactory etchback process as shown at 27 in FIG. 5(a) owing to the precision problem of the lithographic technique. Consequently, a defective opening 41xe2x80x3 of the contact pattern 27 can be made as shown in FIG. 5(b).
The defective opening 27 can also result from variations in the thickness of the oxide film 41 formed by the CVD process, leading to a defective LSI device.
If the etchback process is increased to reduce the frequency that the defective opening of the contact pattern 27 is produced, the damage to the substrate portion 21xe2x80x3 exposed by the etching process in FIG. 4(d) increases.
The damage, which appeared to be caused by impurities injected in the etching process or crystal defect produced in the silicon substrate 21, increases variations in the electrical resistance at the contact or increases the electrical resistance. Such variations in the electrical resistance are no longer negligible for submicron technology.
In order to reduce the number of defective openings of the contact pattern and variations in the electrical resistance at the contact area, it is necessary to reduce the thickness of the oxide film 41 formed by the CVD process. However, such reduction of the oxide film 41 is disadvantageous for solving the problems of FIGS. 2 and 3.
That is, the measure of FIG. 4(d) is not fully satisfactory, and there is a need for further improvement.
Accordingly, it is an object of the invention to provide a method of making a semiconductor device, which is capable of minimizing the etching dimension of a contact pattern formed in an insulation film without changing the lithographic technique.
According to the invention there is provided a method of making a semiconductor device, comprising the steps of etching, with a resist pattern used as a mask, a contact pattern in at least one interlayer insulation film made on a silicon substrate; forming on the contact pattern an insulating film containing silicon as a main component; and oxidizing by heat treatment the insulation film to form an oxide film including a side wall oxide film on an inside wall of the contact pattern.
According to an embodiment of the invention, the etching step is made such that the etching pattern does not reach the silicon substrate.
According to another embodiment of the invention, the etching step makes use of a difference in etching speed between the interlayer insulation films.
According to still another embodiment of the invention, the interlayer insulation films are a nitride film and an interlayer oxide film beneath the nitride film, with the contact pattern formed in the nitride film, and the method further comprising the step of applying, subsequent to formation of the side wall oxide films, a blanket etchback process to simultaneously etch the interlayer oxide film.
According to yet another embodiment of the invention, the interlayer insulation films are an oxide film and a nitride film beneath the oxide film, with the contact pattern formed in the oxide film, and the method further comprising the step of applying, subsequent to formation of the side wall oxide films, a blanket etchback process, followed by etching the nitride film.
According to another embodiment of the invention, the interlayer insulation films are a first interlayer oxide film, a nitride film, and a second interlayer oxide film, with the contact pattern formed in the first oxide film, and the method further comprising the step of applying, subsequent to formation of the side wall oxide film, a blanket etchback process, followed by etching the nitride and second interlayer oxide films.
According to still another embodiment of the invention, the interlayer insulation films are a first interlayer oxide film, a nitride film, and a second interlayer oxide film, with the contact pattern formed in the first oxide and nitride films, the method further comprising the step of applying, subsequent to formation of the side wall oxide film, a blanket etchback process to simultaneously etch the second interlayer oxide film.


A signal modulation method used for a digital channel of digital recording media and digital communication. The method includes the steps of (a) receiving data in a first data unit of a first bit length and RLL encoding the received data into a (d,k) code word; and (b) receiving data in a second data unit of a second bit length and RLL encoding the received data if a number of consecutive zeroes is less than d when two codes words encoded in said step (a) are concatenated. Therefore, a higher resolution than that of other modulation codes is achieved, for a minimum time interval, 4T (diffraction limit). The DC component of a modulated code can be suppressed by controlling merging bits.

1. Field of the Invention
The present invention relates to a signal modulation method, and more particularly, to a run length limit (RLL) coding method for enhancing the recording density of digital recording media.
2. Description of the Related Art
There are various methods for modulating a signal, during the recording and reproduction of the signal used for digital optical recording media and magnetic recording media. Modified frequency modulation (FM) is a representative modulation method.
Such modulation methods are used for compact disks, first-generation magneto-optical disks, and second-generation re-recordable optical disks. The optical disk modulation method is either a peak detecting method, for detecting the position of a peak, or an edge detecting method for detecting the edge of a mark. Minimum and maximum time intervals between such peaks or edges are critical characteristic values. They determine the resolution which is related to the recording density of a reproduced signal and a jitter margin, and are expressed as the restriction RLL of the number of continuous `0`s. Other critical variables which determine the recording density are error propagation, whether the number of input bits is variable, and the ratio of the number of input bits to the number of output bits, namely, the conversion ratio.
RLL (2,7) is a conventional modulation method used for first-generation magneto-optical disks. It has a relatively small jitter margin to be used for the edge detecting method. RLL (1,7) is a method obtained by improving the conventional modulation method. With this method, a large jitter margin can be secured by reducing the size of the minimum mark, and by improving a capacity and the size of a window by 33%. However, the RLL (1,7) modulation method has a problem in that the recording density is relatively low for a given resolution, in the case of optical recording, in which the minimum time interval is 2T and 3T (the diffraction limit).

Signal modulation method employing multilevel run length limit coding scheme


In a compact information terminal apparatus including display means having a displaying function equivalent to that of a personal computer, a browser for browsing a hyper text can easily be manipulated without altering the hyper text formed for the personal computer. When a position other than a hot spot of the hyper text on a browsing view is designated by using a position designating input device which can be manipulated by one hand, a group of operation buttons of the browser for the hyper text is displayed in the vicinity of a designated position.

1. Field of the Invention
The present invention relates to a compact information terminal apparatus in which a hyper text such as an HTML (hyper text markup language) document can be inspected or browsed by connecting the apparatus to a network such as an Internet.
2. Related Background Art
As an inputting system for portable compact information terminals, a system in which a liquid crystal display device of touch panel type is provided in PDA (personal digital assistants) and the like and an operation is effected through pen input, and a system in which a compact liquid crystal is provided in a cellular phone and the like and an operation is effected by using up-and-down and left-and-right direction input switches are already known.
The inputting system using the touch panel has characteristics that a position can be designated directly by a pen device and a hand-writing character can be inputted. On the other hand, the inputting system using the direction switches has characteristics that it can be manipulated by one hand and the operation can easily be effected by using an instruction input system mainly including a text menu.
Further, it is general to browse the HTML document by effecting access to a WWW (world wide web) server through the Internet. The HTML document permits insertion of a character, image, figure and voice and can be linked to other document by describing tag called as anchor with text. An area described by the anchor tag is called as an anchor spot or a hot spot in browser (inspection software).
Further, the HTML is generally formed to be browsed by a personal computer having a resolving power greater than VGA (video graphics array) (640×480 pixels). Although cellular phones capable of drowsing the HTML document have remarkably been progressed, since a display of the cellular phone has a resolving power lower than that of the personal computer, layout must be devised.
There is no conventional information terminal in which portability and compactness permitting one hand manipulation and displaying ability equivalent to that of the personal computer are compatible. Thus, also regarding the browser for the HTML document, there is no browser having GUI (graphical user interface) suitable for such device. To the contrary, an information terminal according to the present invention has a resolving power of a display equivalent to that of a personal computer and is designed as a compact information terminal capable of being manipulated by one hand.
Although the browser for the personal computer generally has the GUI (graphical user interface) as shown in FIG. 9, since a menu and buttons are arranged end zones of a picture plane (view), when selection is effected, a cursor must be shifted toward the end of the picture plane, and, depending upon the input device, it takes a relatively long term to shift the cursor.
For example, in the inputting method using the direction input switches, although manipulation can be effected by one hand, since input is permitted only in the shifting direction of the cursor, it is impossible to designate an absolute position on the picture plane. As a result, in the browser such as WWW browser for the HTML document, for example, whenever a scrolling operation is performed, the cursor must be shifted greatly up to the desired button.
Further, regarding the input device, when the touch panel is used among the conventional operating systems, since the touch panel must be held by one hand and the touch panel must be touched by a pen held by the other hand, such device cannot be manipulated only by one hand.
For example, an example of the portable information terminal of touch panel type is disclosed in Japanese Patent Application Laid-open No. 11-175258 "Method and apparatus for using touch view display for portable communication device of intelligent type"). However, GUI of this example is similar to that of the personal computer, and it is difficult to perform the software operation by one hand.
Further, another example of the information terminal of a cellular phone type is disclosed in Japanese Patent Application Laid-open No. 2000-036856 ("Context sensing pop-up window for cellular phone"). However, since such a terminal generally has a display view smaller than that of the personal computer, layout of the HTML document must be devised.

Compact information terminal apparatus, method for controlling such apparatus and medium


The present invention is directed to a method and system for continuously displaying image pages of digital content which are available over a network. More specifically, the method and system enables a user to view image pages in a continuous manner while a limited number of image pages are being downloaded at a given time. Several image pages which are adjacent to the image page(s) the user is currently viewing may be stored in temporary memory. The image pages in the temporary memory are utilized so that, within the image pages, the user can move the displayed image pages up and down without experiencing any discontinuation. In order to ensure continuous display throughout the entire digital content, the next possible set of image pages is constantly determined and obtained to update the current set of image pages in the temporary memory.

As the use of computers and computer-based networks continues to expand, content providers are preparing and distributing more and more content in electronic form. This content includes traditional media such as books, magazines, newspapers, newsletters, manuals, guides, references, articles, reports, documents, etc., that exist in print, as well as electronic media in which the aforesaid content exists in digital form or is transformed from print into digital form. The Internet, in particular, has facilitated the wider publication of digital content through downloading and display of images of digital content. As data transmission speeds increase, more and more images of pages of digital content are becoming available online. A page image allows a reader to see the page of content as it would appear in print.
However, while simply providing an image (or images) of digital content can be easily facilitated, images corresponding to the conversion of pages of a book into electronic form may not be well suited in some viewing scenarios. Typically, users want to have a reading experience of the digital images of a book that is close to or better than a reading experience of the print form of the book. It is also true that users want to read the digital images of the book without significant delay or discomfort. In current typical embodiments, the data transmission speeds of digital images of a book may be restricted by a bandwidth of a network. Consequently, only limited portions of the digital images of a book are downloaded at a time and displayed via the web browser. This approach may be useful to evenly distribute downloading time among many users and allocate a fraction of the bandwidth to each user. However this approach also poses some problems. For example, there can be a significant lag time (a delay between downloading each portion of the digital images), which will cause discomfort for the user. Further, within the display window, the movement from one portion to another of the displayed digital image can be halted for a moment if the selected portion has not yet been downloaded.


According to one embodiment, a memory controller controlling a NAND memory having D bits/cell, includes: a code encoder which generates a code word having correction capability of t symbols; a write control unit which controls writing of the code word to the NAND memory; and a code decoder which decodes the code word read from the NAND memory, wherein the write control unit dispersedly allocates 2×D pages stored in adjacent two word lines in a block of the NAND memory to 2×D/t or more code words.

In a storage device using a NAND flash memory (NAND memory), error correction (Error Check and Correct) is performed, and a data which is to be written in the NAND memory is encoded to be written in each page of the NAND memory. As error correction process, there is an inner-page ECC (Error Check and Correct) where one code word is configured with symbols in the same page and an inter-page ECC where one code word is configured with symbol in different pages. In a case where random error is beyond correction capability (error-correctable number of symbols) of the inner-page ECC, or in a case where burst error, that is, data loss in unit of a page occurs due to circuit disorder, the error can be corrected by using the inter-page ECC.

Memory controller, storage device, and memory control method


The present invention relates to inorganic fibres having a composition comprising:                61.0 to 70.8 wt % SiO2;        28.0 to 39.0 wt % CaO;        0.10 to 0.85 wt % MgO        other components, if any, providing the balance up to 100 wt %,

The insulation material industry has determined that it is desirable to utilize fibres in thermal, electrical and acoustical insulating applications, which do not persist in physiological fluids. That is, fibre compositions which are considered have low biopersistence (i.e. bio-soluble) in physiological fluids.
While candidate silicate materials have been proposed, the use temperature limit of these materials have not been high enough to accommodate many of the applications to which high temperature resistant fibres are applied. For example, such bio-soluble fibres exhibit high shrinkage at use temperatures and/or reduced mechanical strength when exposed to use temperatures ranging from 1000° C. to 1500° C. as compared to the performance of refractory ceramic fibres.
The high temperature resistant fibres should exhibit minimal shrinkage at expected exposure temperatures, and after prolonged or continuous exposure to the expected use temperatures, in order to provide effective thermal protection to the article being insulated. In addition to bio-solublity and high temperature resistance the fibres should possess a low diameter and low shot content for the resultant insulation materials to have low density and thermal conductivity. The multitude of requirements do not end there, with fibres also needing to be non-reactive to other materials in the insulation system they may form part of.
In 1987 Manville Corporation developed bio-soluble high temperature resistant fibres based on a calcium magnesium silicate chemistry (U.S. Pat. No. 5,714,421). Such material not only had a higher temperature capability than traditional glass wools, but also had a higher solubility in body fluids than the aluminosilicate fibres mostly used for high temperature insulation. U.S. Pat. No. 5,714,421 taught the necessity to combine silica, calcia and magnesia with a variety of other metal oxide additives to obtain the desired combination of fibre properties and form.
While there are many commercial examples of the biosoluble high temperature resistant fibres which have stemmed from magnesia, calcia, silica systems, there is still a need for improved bio-soluble high temperature resistant fibres and insulation material thereof.
International Application WO 87/05007 discloses inorganic fibres consisting essentially of SiO2, CaO with specified ranges of MgO and Al2O3, which were obtained from metal oxides rather than raw by-product materials with variable composition. It was observed that lower Al2O3 levels resulted in a surprisingly high bio-solubility level.
International Application WO 94/15883 discloses CaO/MgO/SiO2fibres with additional constituents Al2O3, ZrO2, and TiO2, for which saline solubility and refractoriness were investigated. The document states that saline solubility appeared to increase with increasing amounts of MgO, whereas ZrO2 and Al2O3 were detrimental to solubility. The presence of TiO2 (0.71-0.74 mol %) and Al2O3 (0.51-0.55 mol %) led to the fibres failing the shrinkage criterion of 3.5% or less at 1260° C. The document further states that fibres that are too high in SiO2 are difficult or impossible to form, and cites fibres having 70.04, 73.09, 73.28 and 78.07 wt % SiO2 as examples of compositions which could not be fiberized.
U.S. Pat. No. 6,953,757 discloses an inorganic high silica fibre composition comprising predominately silica, calcia, magnesia and zirconia and optionally viscosity modifiers, such as alumina and boria, to enable product fiberisation.
JP2003003335 disclosures the inorganic fibres comprising silica and calcia to avoid precipitation of cristobalite at the fibres are heated to 1000° C. or greater. To avoid precipitation of cristobalite, the levels of Na2O, K2O, TiO2, Fe2O3 and MgO are reduced or not added, with high purity calcia and silica used as raw materials.
US2004/254056 claimed CaO/SiO2 fibres comprising greater than or equal to 72 wt % SiO2, or for which the sum SiO2+ZrO2+B2O3+5*P2O5 was greater than 72 wt %. Such fibres had a low propensity for reaction with aluminosilicate bricks whereas fibres with lower SiO2+ZrO2+B2O3+5*P2O5 content tended to react adversely with aluminosilicate bricks.
Despite advances in the field, there is still a need for a simplified fibre composition which is not reliant upon a range of additives to obtain the required combination of fibre properties and form. There is also a need for a simplified fibre composition which is not reliant on high impurity raw materials in their production, with the purification processes often used to produce such high purity raw materials increasing the carbon footprint of the resultant inorganic fibres.

Abstract: The sum of SiO2 and CaO is greater than or equal to 98.8 wt % and the other components comprise less than 0.70 wt % Al2O3, if any.


The present invention is directed to methods and devices for detection of cerebrospinal fluid leaks by detection of the CSF protein beta-2 transferrin. The microfluidic devices and methods of the invention combine capture and specific labeling of transferrin from a sample with a subsequent step of isoelectric focusing to separate transferrin isoforms for detection. Microfluidic channels and chambers are patterned on a substrate, designed so that on one region (i.e., a microfluidic channel or chamber) of the substrate transferrin is selectively captured from the sample and labeled, and in a second region of the substrate, transferrin isoforms are separated using isoelectric focusing. Detection of two transferrin bands, indicating the presence of beta-2-transferrin, indicates the presence of CSF in the sample. The devices and methods of the invention provide a safe, efficient, and ultrarapid modality with high specificity and sensitivity for the detection of CSF in the acute care setting.

The ability to rapidly distinguish non-sialated proteins from sialated proteins in a sample is vital to the management of various pathologies; such as; early detection of cerebrospinal fluid (CSF) leakage, endometriosis, melanoma, breast cancer, oral cancer, Alzheimer's disease and similar sialated/non-sialated protein or tau-protein diseases. CSF leakage refers to the escape of the fluid that surrounds the brain and spinal cord, and is caused by rupture of the membrane which surrounds the brain and spinal cord and contains the CSF. Head trauma is responsible for 50-80% of all cases of CSF leakage. Each year in the United States, over one million people are treated and released from hospital emergency departments with traumatic head injuries. Approximately 2 to 3% of head injuries result in the occurrence of CSF leaks; thus this is a relatively common condition seen in hospital emergency rooms. CSF leakage may also result from certain head, spine or brain surgeries, spinal taps, or accidental punctures during neural blockade. The main complication of CSF leakage is cerebral infection (meningitis and brain abscess), which occurs in 25-50% of cases. The prompt initiation of treatment with antibiotics and/or surgical treatment of fistulas is necessary to avoid severe complications. Appropriate treatment therefore requires a rapid and reliable method for determination of CSF leakage.
Radiologic methods, such as CT and MRI scans, can diagnose fractures and detect fluid levels within sinuses, thus suggesting, but not confirming cerebrospinal fluid leakage. Other radiologic techniques include contrast and radionuclide cisternography. Contrast cisternography can locate the site of leakage but may not detect intermittent leaks. Radionuclide cisternography is expensive, has a high false positive rate, and is not accurate in determining the location of leakage. Exploratory surgery, involving the detection of preoperative intrathecally applied fluorescein, is highly sensitive, but this invasive method may also entail some risks to the patient. Measurement of protein and glucose concentrations, such as glucose dipstick tests, have been used in the past as indicators for the presence of CSF. These methods are safe and non-invasive, but have poor reliability.
Beta-2-transferrin is a non-glycosylated (asialated) isoform of transferrin found only in cerebrospinal fluid, ocular fluids, and perilymph. The technology is still unavailable to raise antibodies to target and differentiate between glycosylated and non-glycosylated epitopes. Beta-2-transferrin may be separated from the sialated beta-1-transferrin isoforms and detected by immunofixation electrophoresis using antibodies that bind all transferrin isoforms. With a sensitivity of 94%-100%, and a specificity of 98%-100%, this assay has become the gold standard in detection of CSF leakage. However, because immunofixation electrophoresis is necessary to detect beta-2 transferrin, the assay is expensive ($230-300/sample), and carries multiple added costs for specimen handling, archiving, shipping and storage. Each sample must be provided in high volume, requiring as much as 1-2 ml of sample per assay. Moreover, special technical skills and experienced technicians are required to assure test precision and reliability, mandating that beta-2 transferrin assays be performed by specialty laboratories. As a result, turn-around time for results to reach the caregiver may take up to 4 days, often resulting in additional hospitalization time for the patient suspected of having a cerebrospinal fluid leak, who must remain in the hospital for monitoring until the test results are determined.
Endometriosis is a medical condition that affects 2 to 5 percent of all women. Cells lining the uterus or endometrium grow in other areas of the body, causing pain, irregular bleeding, and even infertility.
Currently, the only accurate diagnosis of the disease requires a laparoscopy, a procedure involving a "belly-button cut" and insertion of a lighted instrument into the navel. However a less invasive method would be the accurate and rapid diagnosis using the methods and the device described herein. Antibodies to the transferrin protein and α2-Heremans Schmidt glycoprotein (a 2-HSG) has been described (Pillai S., Zhou G. X., Arnaud P., Jiang H., Butler W. J. & Zhang H. (1996) Antibodies to endometrial transferrin and alpha 2-Heremans Schmidt (HS) glycoprotein in patients with endometriosis [published erratum appears in Am J Reprod Immunol 1997 March; 37(3):277]. Am J Reprod Immunol, 35, 483 and Mathur S. P., Holt V. L., Lee J. H., Jiang H. & Rust P. F. (1998) Levels of antibodies to transferrin and alpha 2-HS glycoprotein in women with and without endometriosis. Am J Reprod Immunol, 40, 69) and proposed as diagnostic markers.
Sialic acid-rich glycoproteins (sialoglycoproteins) bind selectin in humans and other organisms. Metastatic cancer cells often express a high density of sialic acid-rich glycoproteins. One example of the use of our methods and device may be in the diagnosis of melanoma. Melanoma is a malignant cancer of the skin. It is the eighth most common cancer in the United States and causes 1 to 2 percent of all cancer deaths. The diagnosis of melanoma is made on the basis of an excisional biopsy. However, not all excisional biopsies result in the diagnosis of melanoma. Also, recurrent nevus may be interpreted erroneously as a melanoma. HMB-45 is an antibody widely used in diagnostic pathology owing to its great specificity in identifying melanomas. Sialylation of antigen is crucial to HMB-45 binding, and suggests that the absence of staining in normal adult melanocytes, dermal nevi, and other melanocytic lesions may be a result of differential sialylation. Similarly, the differential detection of non-sialated and sialated proteins may aid in the rapid diagnosis of breast cancer, oral cancer, Alzheimer's disease and similar sialated/non-sialated protein or tau-protein diseases.
The present invention satisfies a need in the art by providing devices and methods for sensitive, specific and rapid detection of non-sialated protein in a patient sample using microfluidics technology.

Methods and apparatus for the detection and differentiation of non-sialated proteins from sialated proteins in a fluid sample


In various examples, a hub for a medical device includes a hub housing including a passage from a proximal end of the hub housing to a distal end of the hub housing. A valve is disposed within the hub. The valve is configured to allow passage of an insertable device through the valve while inhibiting leakage of fluid from the valve. A cap is engaged to the hub housing. The cap includes an opening therethrough sized and shaped to allow passage of the insertable device through the opening. The opening allows access to the passage of the hub housing. An angled sidewall is disposed within the hub. The angled sidewall is configured to retain and deform the valve into a curved shape.

The present invention relates to a medical device, and more specifically relates to a medical device including a hemostatic valve configured to inhibit fluid leakage from the medical device.
When inserting a device, such as a catheter, introducer, or other access device, within a patient, fluid of a higher pressure can be experienced within the patient, and in turn, the device, than is experienced in atmospheric conditions external to the device and the patient. This is particularly true with insertion of the device within an artery. Such a pressure differential can often lead to fluid leaking, spraying, or otherwise exiting from the device, which is typically not a desirable performance characteristic of such a device.

This patent is subject to a terminal disclaimer.


A signal transmission structure is provided. The structure mainly comprises at least a conductive via, at least a via land and a conductive wall. One end of the conductive via is connected to the via land. The conductive wall covers only a portion of the inner wall of a through hole in the core layer of a circuit substrate. The conductive wall has a semi-circular or a C-shaped structure. Therefore, when a signal passes the conductive via and the via land of the circuit substrate through the conductive wall in the interior of the via, because of a more continuous impedance between the via land and the conductive wall, signal reflection due to impedance mismatch along the signal transmission pathway can be reduced to enhance signal transmission quality.

1. Field of the Invention
The present invention relates to a signal transmission structure. More particularly, the present invention relates to a signal transmission structure and circuit substrate thereof capable of reducing insertion loss during signal transmission.
2. Description of the Related Art
A conventional circuit substrate comprises a multiple patterned circuit layers and a plurality of dielectric layers alternately laminated on top of each other. The patterned circuit layers are formed, for example, by patterning copper foils in photolithographic and etching processes. The dielectric layers are disposed between neighboring patterned circuit layers to isolate the patterned circuit layers. In addition, the laminated circuit layers are electrically connected to each other through plating through holes (PTH) or conductive vias. The method of forming a conductive via includes performing a sequence of photolithographic processes to form a hole in the dielectric layer and then filling the hole with a conductive material to form a conductive via for electrically connecting at least two patterned circuit layers. The method of forming a plated-through-hole includes performing a mechanical drilling process to form a through hole in the laminated circuit layers and the dielectric layers or a dielectric core and then performing an electroplating operation to form a plated layer on the interior wall of the hole for electrically connecting at least two patterned circuit layers.
FIG. 1 is a schematic cross-sectional view of a conventional circuit substrate. As shown in FIG. 1, the circuit substrate 100 comprises a lamination of six patterned circuit layers. The circuit substrate 100 has a laminated layer 110 comprising a top circuit structure 120, a core layer 130 and a bottom circuit structure 140. Wherein the top circuit structure 120 comprises a plurality of patterned circuit layers and at least a dielectric layer laminated sequentially over each other above the core layer 130. Furthermore, the via lands 124 and 126 of each patterned circuit layer are electrically connected through a conductive via 125. The bottom circuit structure 140 comprises a plurality of patterned circuit layers and at least a dielectric layer laminated sequentially over each other below the core layer 130. Furthermore, the via lands 144 and 146 of each patterned circuit layer are electrically connected through a conductive via 145. In addition, the core layer 130 has a plurality of through holes 132 that connect an upper surface 130a of the core layer 130 with a lower surface 130b of the core layer 130. The inner wall of each through hole 132 is completely covered by a conductive wall 134 such that the via land 126 of the top circuit structure 120 is electrically connected to the via land 146 of the bottom circuit structure 140. Moreover, a dielectric material 150 may fill the hollow portion within the conductive wall 134 and the through hole 132.
As shown in FIG. 1, the two via lands 126 and 146 disposed on the top surface 130a and the bottom surface 130b of the dielectric core layer 130 are completely covered both ends of a through hole 132. Furthermore, these via lands 126, 146 are electrically connected to each other through a hollow cylindrical conductive wall 134. Therefore, a signal on a signal line in the top circuit structure 120 can transmit in a downward direction sequentially through a connection pad 122, the conductive vias 123, 125 and the via lands 124, 126. After passing through the conductive wall 134 which is inside the through hole 132 in the core layer 130, the signal passes sequentially through the via lands 146, 144, the conductive vias 145, 143 and another connection pad 142 to be connected externally. The aforementioned conductive structures provide a signal transmission pathway linking two devices or two terminals (not shown).
Note that in the prior art the line width of the signal lines electrically connecting two devices or two terminals must be uniform. In other words, the electrical impedance in various parts of the signal line should be constant so that the characteristic impedance is kept at a constant value when electrical signals are transmitted along the signal line. In particular, for high speed and high frequency signal transmission, fine impedance matching design between two terminals of a signal transmission path is very important to reduce signal reflection which may occur because of impedance mismatch in the signal transmission path. In other words, reducing insertion loss and correspondingly increasing the dropping of return loss during signal transmission will prevent affecting signal transmission quality. However, the two via lands 126 and 146 in a conventional design cover an area larger than the hole area of the through hole 132. Furthermore, the conductive wall 134 completely covers the inner wall of the through hole 132 in the core layer 130 that alteration of a large impedance may occur when a signal passes through the relatively large area of the two via lands 126 and 146 and the hollow cylindrical conductive wall 134. Consequently, the impedance mismatch between the conductive wall 134 and the top circuit structure 120 or the bottom circuit structure 140 becomes more serious. Moreover, when a differential signal respectively flows through the conductive walls 134, 138 on the inner walls of two neighboring through holes 132 and 136, due to electromagnetic coupling between the two conductive walls 134, 138, switching a signal will interrupt another signal in one of the neighboring through holes 132, 126 and generate cross talk. Thus, signal transmission quality will be influenced.
To resolve the aforementioned problem, the distance between two neighboring through holes 132 and 136 has to be increased. In other words, the distance between two neighboring conductive walls is increased to avoid cross talk. However, this method requires larger layout area and hence cannot be applied to a limited or high-density area of circuit layout.
In addition, a differential signal transmitting amidst the signal transmission structure will change the current return circuit and the electric field when passing through the two hollow cylindrical conductive walls 134 and 138 due to the electromagnetic coupling between the conductive walls. Accordingly, a change in the characteristic impedance will occur. Hence, when the signal is transmitted to the second through holes 132, 136, signal reflection phenomenon will occur due to non-continuous impedance in the two conductive walls 134 and 138. As a result, signal transmission quality will be affected.
For transmission of a single signal or a differential signal, the higher the operating frequency, corresponding to a same operating frequency, the greater the return loss is when the signal passes the through hole 132, so that impedance mismatch becomes more serious. Furthermore, the higher the operating frequency, corresponding to a same operating frequency, the greater the insertion loss will be increased when the signal passes the through hole 132, so that impedance mismatch becomes more serious.
As described, a signal passing through a relatively expansive via lands 126, 146 and a hollow cylindrical conductive wall 134 having a relatively large cross-sectional large area, the characteristic impedance of the top circuit structure 120 and the bottom circuit structure 140 of the circuit substrate 100 will increase with frequency. Thus, the difference from originally designed impedance value will increase leading to an aggravation of impedance mismatch in the same signal transmission pathway.

Signal transmission structure and circuit substrate thereof


The present invention provides a dual switching power supply system that is immune to malfunction caused by the off noises of the switch control signals. The dual switching power supply system of the invention generates stable voltage outputs without the necessity of making any difficult and unsatisfactory adjustment in the PCB layout process. The dual switching power supply system of the invention preferably comprises: a first switch control means for outputting a first switch control signal; a second switch control means for outputting a second switch control signal; and a phase shifting means for shifting the phase of the second switch control signal by a predetermined amount while keeping the frequencies of the first and switch control signal equal.

1. Field of the Invention
The present invention relates generally to a dual switching power supply system free from any malfunction caused by coupling of the off noise of the voltage sensing signal in one switching power supply to the voltage sensing signal in the other switching power supply.
2. Description of the Prior Art
A dual switching power supply (SPS) system is primarily useful in a circuit that needs a variable voltage output. For example, in a multi-frequency monitor, the voltage required for different frequencies can vary from 60 volts to 150 volts. A set of power supplies with an extra control circuit may solve this problem, but this results in occupying more space and lower efficiency. Therefore a dual switching power supply system is utilized to overcome these disadvantages. This kind of system usually uses a current mode circuit with two SPSs and the two SPSs have to work at the same frequency to avoid interference. The two switch control signals in the two SPSs are on/off square waves. When they are in-phase and are working at the same frequency, the off noise of the voltage sensing signal with a shorter on-time (the time period when signal is "high") may disturb the voltage sensing signal with a longer on-time to an extent that the DC output voltage signal of the dual SPS system has severe ripples and causes instability. Such a phenomenon is found to be most obvious in the applications to monitor circuits because of the display of distorted pictures on the screen.
FIG. 1 shows a typical current mode dual switching power supply system for a monitor circuit. The frequencies of the two SPSs have to be the same as the horizontal synchronization (h-sync) signal of the monitor or the overall system will contain interference. The system includes at least two current mode control integrated circuits (IC) CON1 and CON2. Commercially available UC3842 of Unitrode Co. is an example of such an IC. Please refer to FIG. 2 for the waveforms and timing relations of the signals mentioned below. The width of the h-sync pulses is exaggerated and the signal is assumed to be an ideal square wave for easier understanding. The input AC voltage passes through a full-wave bridge rectifier RF, a high capacitance capacitor C.sub.h1 and then the transformer X1 to provide the desired level of output DC voltage. CON1 generates a control signal to control the on/off of the NMOS transistor Q1 which works as a switch. After CON1 is activated, capacitor C.sub.11 is charged up in a rate decided by the values of C.sub.11 and R1. Meanwhile, signal 111 at one end of C.sub.11 is detected by CON1 through pin #4 to see whether it is greater than a predetermined value V.sub.sense1. If so, the internal circuit of CON1 automatically lowers the voltage of signal 111 to zero, then C.sub.11 is charged up again and signal 111 starts a next cycle. Thus signal 111 is an oscillating saw wave. The input synchronization triggering signal h-sync from the monitor carries a square pulse passing through a filtering diode D1 and a differentiating capacitor C.sub.12, and results in an impulse signal 112 at the rising edge of the h-sync signal at node N.sub.1. The impulse adds to signal 111 and forces the voltage of signal 111 to exceed V.sub.sense1. When this happens, the voltage of signal 111 drops to zero right away and starts another cycle. Thus synchronizes signal 111 with the h-sync signal.
The gate terminal G.sub.1 of NMOS transistor Q1 is connected to pin #6 of CON1 to receive the switch control signal 113. Under the control of CON1, signal 113 goes to "high" when signal 111 falls to zero voltage. This turns on the transistor Q1 and the current passing through resister R.sub.s1 increases gradually because of the inductance of the coils of the transformer X1. The source terminal S.sub.1 of the NMOS transistor Q1, which is also the voltage sensing terminal, is connected to pin #3 of CON1. The voltage at S.sub.1, which is signal 114 in FIG. 2, is checked by CON1 to determine whether it is higher than a predetermined value V.sub.sense2. If so, the control IC CON1 turns off Q1 by dropping the voltage of signal 113 and the voltage at S.sub.1 to zero. Signals 111, 113 and 114 stay at zero voltage as the h-sync signal remains "low". The next cycle starts when the h-sync signal goes to "high" again. Therefore the frequencies of the switch control signal 113 and the voltage sensing signal 114 equal the frequency of the h-sync signal and the synchronization between the monitor and SPS1 is achieved.
Considering SPS2 at the bottom of FIG. 1, we can see that it is the same as SPS1 and receives the same h-sync signal for synchronization purpose. As a result, the switch control signal 123 at pin #6 of the control IC CON2 has the same frequency and phase as the switch control signal 113 and the h-sync signal from the monitor. Thus the synchronization process between the monitor, SPS1 and SPS2 is complete.
However, because of probable different loading requirements for the two SPSs, the two switch control signals at the two gate terminals, i.e. signal 113 and 123, may have a different duration of on-times. For convenience, assume that the on-time of signal 113 is shorter than that of signal 123 as shown in FIG. 2. The switching and state changing of the NMOS transistors and the transformers induce noise in the transient states of the two voltage sensing signals. Due to ground and other wiring on the printed circuit board (PCB), noise of one voltage sensing signal couples to the other voltage sensing signal. This can be observed from FIG. 2. Because the two on times are not of equal duration, the off noise of signal 114 couples onto the slope portion of signal 124 and, depending on the amplitude of the noise and the difference between the duration of two on-times, it may push the voltage of signal 124 to a level higher than V.sub.sense2 and force signal 123 to go "low" before the moment it is designed to if noise is not present. This turns off the NMOS transistor Q2 prematurely and causes the output of the power supply system to be unstable. Prior art solutions to this problem include reducing the amplitude of the off noise and better PCB layout processing. However, difficulties still exist and the result may not be satisfactory even when great care is exercised.

Method and apparatus for preventing improper switching of a dual power supply


The invention provides a ferrite material (ferrite sintered body, ferrite powders) having a composition formula of (1-x-y-z)(Li0.5Fe0.5)O.xZnO.y(Mn, Fe)2O3.zCuO, wherein x, y, z, and a satisfy 0.175≦x≦0.29; 0.475≦y≦0.51; 0.07≦z≦0.22; and 0.02≦a≦0.055 in a case of a=Mn/(Mn+Fe). At least one of Co oxide, Co hydroxide, and Co carbonate in an amount of 1 wt. % or less on the basis of CoO may be contained in 100 wt % of the ferrite material. The ferrite material has a normalized impedance ZN of 40000 Ω/m or more at 30 MHz and a normalized impedance ZN of 60000 Ω/m or more at 100 MHz as well as a specific resistance of 106 Ωm or more.

1. Field of the Invention
The present invention relates to a ferrite material having high impedance in a high-frequency band, and a method for producing the same.
2. Description of Related Art
Various types of noise filters for inhibiting transmission of noise of electronic appliances have been proposed and employed, and as filters for inhibiting transmission of signal components in a high-frequency band, for example, noise filters obtained by winding coils on ferrite cores have been known.
For these noise filters, magnetic impedance of ferrite materials has be utilized, and along with the miniaturization of various types of electronic appliances in recent years, ferrite materials having high impedance particularly in a high-frequency band have been desired.
Conventionally, Mn—Zn-based or Ni—Zn-based ferrite materials have been employed. Since Mn—Zn-based ferrite materials have high magnetic permeability, the materials have high impedance in kHz band, however the specific resistance thereof is as low as 1 Ωm and therefore, loss due to eddy current in the ferrites is increased in MHz band. Accordingly, the impedance is lowered at frequency of 10 MHz or more and the materials are difficult to be used for removing noise in a high-frequency band of 30 MHz or more. Furthermore, since the specific resistance is low, it is also difficult to directly wind a coil on a core and production steps such as a step of inserting an insulating material between the core and the coil are increased and the miniaturization is thus difficult.
On the other hand, since Ni—Zn-based ferrites have resistivity as high as 106 Ωm or more, the effect of eddy current loss is small, and high impedance can be obtained at a frequency of 10 MHz or more as compared with the Mn—Zn-based ferrites. Therefore, the Ni—Zn-based ferrites are mainly used for removing noise in a high-frequency band of 30 MHz or more. Further, since the Ni—Zn-based ferrites have high specific resistance, the ferrites have advantages that direct winding of a coil on a core is possible and the miniaturization is also possible.
However, since the Ni—Zn-based ferrites have high magnetostriction and show large change of magnetic characteristics by external stress, if a coiling is firmed on a ferrite core and thereafter molding with a resin is carried out in order to improve the reliability, there is a problem of changing magnetic permeability by the stress. Further, since costly Ni is contained as a main component, there is another problem that production cost is high.
As a material containing no costly Ni and having small magnetostriction, Li-based ferrite materials have been known. For example, Japanese Patent Application Laid-Open No. 2004-153197 has proposed a Li—Cu—Zn ferrite having a material composition defined as Li0.5xZnzCuaFe2+0.5x-yMnyO4 (0.10<x<1.00; 0.13<y<0.80; 0<z<0.90; 0.02<a<0.40; and 0.5x+z+a≠1), so that low temperature sintering is made possible and improved specific resistance can be thus achieved.

Ferrite material and method for producing ferrite material


The present application provides an anti-fuse one-time programmable (OTP) memory array and a manufacturing method of the anti-fuse one-time programmable (OTP) memory array. The memory array includes: active areas; pairs of programming word lines and read word lines; and dummy word lines. The active areas extend along a first direction in a semiconductor substrate, and are separately arranged along a second direction. The programming word lines, the read word lines and the dummy word lines extend along the second direction over the semiconductor substrate. A region in which a pair of programming word line and read word line are intersected with one of the active areas defines a unit cell in the memory array. The dummy word lines respectively lie between adjacent pairs of programming word lines and read word lines. A region in which one of the dummy word lines is intersected with one of the active areas defines an isolation transistor.

Nonvolatile memory devices can retain data even when their power supply is cut off. According to programmable times, the nonvolatile memory devices can be further divided into multi-time-programmable (MTP) memory devices and one-time-programmable (OTP) memory devices. Users can program a MTP memory device multiple times to modify the data stored in the MTP memory device. On the other hand, an OTP memory device can be only programmed once, and data stored in the OTP memory device cannot be modified.
Further, the OTP memory device may be classified into a fuse type and an anti-fuse type according to a programmed state of the OTP memory device. The fuse type OTP memory device is short before being programmed, and open after being programmed. In contrast, the anti-fuse type OTP memory device is open before being programmed, and is short after being programmed. As compared to the fuse type OTP memory device, the anti-fuse type OTP memory device is more compatible with complementary metal-oxide-semiconductor CMOS) fabricating process.
Isolation between unit cells in an anti-fuse OTP memory array is important for blocking crosstalk between the unit cells. However, an insulating structure spreading between the unit cells for realizing such isolation may pose obstacles for down scaling the anti-fuse OTP memory array.

One-time programmable memory array and manufacturing method thereof


This invention features devices and methods for analyte processing and detection, and use of such methods, e.g., in the treatment and diagnosis of disease or determining the presence of a pathogen.

This invention features devices and methods for analyte processing and detection, and use of such methods in the treatment and diagnosis of disease.
Biocompatible magnetic sensors have been designed to detect molecular interactions in biological media. Upon target binding, these sensors cause changes in the spin-spin relaxation times of neighboring water molecules (or any solvent molecule with free hydrogens) of a sample, which can be detected by magnetic resonance techniques. Thus, by using these sensors in a sample, it is possible to detect the presence of an analyte at very low concentration—for example, small molecules, specific DNA, RNA, proteins, carbohydrates, organisms, and pathogens (e.g., viruses).
In general, magnetic sensors are superparamagnetic particles that bind or otherwise link to their intended molecular target to form clusters (aggregates). It is thought that when superparamagnetic particles assemble into clusters and the effective cross sectional area becomes larger, the ability of the clustered superparamagnetic particles to dephase the spins of surrounding water (or other solvent) protons is altered, leading to a change in the measured relaxation rates (e.g., 1/T2). Additionally, cluster formation is designed to be reversible (e.g., by temperature shift, chemical cleavage, pH shift, etc.) so that "forward" or "reverse" assays can be developed for detection of specific analytes. Forward (clustering) and reverse (declustering) types of assays can be used to detect a wide variety of biologically relevant materials.
There is a need in the art for a rapid, commercially realizable, fluidics-based device capable of multiplexed analyte detection suitable for use with magnetic nanosensors.

Conduit-containing devices and methods for analyte processing and detection