A novel metal-encapsulated fullerene compound wherein a side chain is introduced in a metal-encapsulated fullerene is provided.. A metal-encapsulated fullerene compound represented by the following structural formula (1) is synthesized by causing a disilirane derivative or digermirane derivative having the following structural formula (2) to react with a metal-encapsulation fullerene so as to add functional groups to the fullerene. ##STR1## Herein, M is an encapsulated metal atom, m is an integer from 1 to 3, n is an even number from 28 to 200, and R is a t-butyl group or an aromatic group having alkyl groups in the 2,6-positions, such as mesityl, 2,6-diethylphenyl or 2,6-dimethylphenyl groups.

1. Field of the Invention
This invention relates to a useful metal-encapsulated fullerene compound having application as a functional material, a superconducting material, an electronics material or a pharmaceutical material.
2. Description of the Related Art
An all-carbon fullerene is a recently discovered carbon allotrope typified by Buckminsterfullerene (C.sub.60), and it has attracted attention in recent years because of its unique cage (shell) structure. After discovery of macroscopic preparations of all-carbon fullerenes in 1990, various physical and chemical properties of the fullerenes were clarified, and since many derivatives of all-carbon fullerene have now been synthesized, nowadays they are applied to electrical conductors, semiconductors and pharmaceutical products. Many reports about application of all-carbon fullerenes and their derivatives have appeared in the literature (Gendaikagaku, No. 253, April 1992, pp. 12-19, and Kagaku, Vol. 50, June 1995, pp. 12-16), and in particular, biological activity have emerged for derivatives of all-carbon fullerene (J. Am. Chem. Soc., 1993, Vol. 115, p. 6506) which have led to further research.
A metal-encapsulated fullerene is a new material closely related to an all-carbon fullerene. This material is comprised of an ordinary fullerene cage and a metal atom incorporated into inside of its shell structure. The physical and chemical properties of metal-encapsulated fullerenes can be controlled by changing their encapsulated elements, suggesting many potential applications. After the invention of a method for macroscopic synthesis of lanthanum-encapsulated fullerenes La.sub.m @C.sub.n (R. Smalley et al., J. Phys. Chem. 1991, Vol. 95, p.7564), intensive research is now being carried out. According to Smalley's report, it is possible to produce one-lanthanum-encapsulated fullerenes firstname.lastname@example.com with n=36-122, two-lanthanum-encapsulated fullerenes La.sub.2 @C.sub.n up to n=110, and three-lanthanum-encapsulated fullerenes La.sub.3 @C.sub.n up to n=98. Although there is essentially no higher limit, there is a lower limit for the value of n in M.sub.m @C.sub.n fullerenes. And it is thought that the limit depends on the size and number of encapsulated metals or metal ions.
In the case of firstname.lastname@example.com, a method has been described for obtaining a pure sample and its characterizations have been reported (K. Kikuchi et al., Chem. Phys. Lett. 1993, Vol. 216, p. 67 and J. Am. Chem. Soc. 1994, Vol. 116, p. 9367; T. Suzuki et al., J. Am. Chem. Soc. 1993, Vol. 115, p. 11006; K. Yamamoto et al., J. Phys. Chem. 1994, Vol. 98, p. 2008 and J. Phys. Chem. 1994, Vol. 98, p. 12831). In the case of fullerenes encapsulating two lanthanum atoms, the characterization of La.sub.2 @C.sub.80 has been reported (T. Suzuki et al., Angew. Chem. Int. Ed. Engl. 1995, Vol. 34, p. 1094).
The synthesis of scandium-encapsulated fullerenes, Sc.sub.m @C.sub.n (m=1-3), is reported by H. Shinohara in Nature 1992, Vol. 357, p. 52. The separation methods are described for Sc.sub.2 @C.sub.n (n=74, 82, 84) in J. Phys. Chem. 1993, Vol. 97, p. 4259, and for Sc.sub.3 @C.sub.82 in J. Phys. Chem. 1994, Vol. 98, p. 8597.
The first synthesis of yttrium-encapsulated fullerenes, Y.sub.m @C.sub.n, was reported by J. Weaver et al. (Chem. Phys. Lett. 1992, Vol. 190, p. 460), and the characterization of firstname.lastname@example.com was described by K. Kikuchi et al. in J. Am. Chem. Soc. 1994, Vol. 116, p. 9367.
The production and extraction of lanthanoid-encapsulated fullerenes, M.sub.m @C.sub.n (M=Ce, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er) are described by R. L. Whetten et al. in J. Phys. Chem. 1992, Vol. 96, p. 6869, and the production of other lanthanoid-encapsulated fullerenes, M.sub.m @C.sub.n (M=Pr, Eu, Yb, Lu) is reported by R. S. Ruoff et al. in J. Phys. Chem. 1993, Vol. 97, p. 6801. Of these, the isolation and characterization of firstname.lastname@example.com were reported by H. Funasaka et al. in Chem. Phys. Lett. 1995, Vol. 232, p. 273 and J. Phys. Chem. 1995, Vol. 99, p. 1826.
As to an actinoid-encapsulated fullerene, the synthesis of uranium-encapsulated fullerenes U.sub.m @C.sub.n (m=1-2, n=28-80) is reported by R. Smalley et al. in Science 1992, Vol. 257, p. 1661.
In the case of alkali-metal-encapsulated fullerenes, potassium and cesium have been reported. The production of potassium-encapsulated fullerenes, firstname.lastname@example.com, is reported by R. Smalley et al. in J. Am. Chem. Soc. 1988, Vol. 119, p. 4464, and of cesium-encapsulated fullerenes, firstname.lastname@example.com, by R. Smalley et al. (J. Am. Chem. Soc. 1988, Vol. 110, p. 4464).
Fullerenes encapsulating an alkaline earth metal have been reported for calcium, strontium and barium. The production and extraction of a calcium-encapsulated fullerene, firstname.lastname@example.com, was first performed by R. Smalley et al. (Chem. Phys. Lett. 1993, Vol. 207, p. 354 and Z. Phys. 1993, Vol. D26, p. 297), after which the production of other firstname.lastname@example.com fullerenes was confirmed by K. J. Fisher et al. (J. Chem. Soc., Chem. Commun. 1993, 941). The production of strontium-encapsulated fullerenes, Sr.sub.m @C.sub.n, and barium-encapsulated fullerenes, Ba.sub.m @C.sub.n, was reported by K. J. Fisher et al. (J. Chem. Soc., Chem. Commun. 1993, 1361).
As an example of fullerenes encapsulating a transition metal, the synthesis of an iron-encapsulated fullerene, email@example.com, is reported by C. N. R. Rao et al. (J. Am. Chem. Soc. 1992, Vol. 114, p. 2272, and Indian J. Chem. 1992, Vol. 31, p. F17). The first synthesis of a cobalt-encapsulated fullerene, email@example.com, is described by D. S. Bethune et al. in Nature 1993, Vol. 363, p. 605.
As described hereinabove, it has been reported that a variety of metal elements are encapsulated in fullerenes, most of the reports concern methods of their production, isolation and characterization. Since all-carbon fullerene derivatives have biological activity, various potential applications of metal-encapsulated fullerenes, such as biological activity, are now envisaged. In addition, in the case of missile therapy of cancer using radioactive elements, fullerenes encapsulating radioactive elements are expected to play an important role. When you test biological activity of a certain substance or use it in a treatment for cancer, its water solubility must be enhanced and its affinity for the organism must be increased. Therefore it is necessary to synthesize derivatives of metal-encapsulated fullerenes with hydrophilic groups in the same way as the case for all-carbon fullerenes. To date, however, no metal-encapsulated fullerene derivative has been successfully synthesized in test tube amounts, and its method of synthesis remains unclear. This is why there have so far been no reports for the biological activity of metal-encapsulated fullerene compounds, and why there have so far been no successful development and no synthesis of functional materials, semiconductor materials, electronics materials and pharmaceutical materials using these metal-encapsulated fullerenes or metal-encapsulated fullerene compounds at the present time.

Metal-encapsulated fullerene compound and a method of synthesizing such compound


Methods, systems, and machine readable mediums are disclosed for viewing multidimensional data. In one embodiment, a method is disclosed which comprises displaying multidimensional data in a table format, the table format having a plurality of rows, a plurality of columns, and a plurality of cells displaying data, a first column of the plurality of columns including data having at least two hierarchical levels. Data for at least a first set of the plurality of cells is displayed in a graphical format, the first set including cells in the first column, the graphical format of the cells in the first set in the first column indicating a hierarchical level associated with the cell data and a mechanism is displayed for a first one of the rows to display at least one additional row having data in the first column associated with a lower hierarchical level of the first row data.

Data may be displayed in any number of different ways. One traditional approach that has been used to display data is a tabular representation. In a tabular representation, data is displayed in a table format with records displayed as rows in the table and attributes of the records displayed as columns. The attribute values are displayed in a textual format in cells (the intersection of a row and a column). With large data sets, a user has to scroll through multiple pages to view all the data. Additionally, this type of view does not facilitate rapid user comprehension of the data set.
Another technique that has been used is to display data in a table format, but instead of displaying the data values as textual values, the data is displayed as graphical bars. To get more detailed information, the user may specify a focus region to see the textual values of the data. This technique may allow a user to view large amounts of data on a single screen and more easily notice data trends with data sets having two dimensions of data. However, this type of display does not provide for the comprehension of hierarchical relationships in multidimensional data having multiple hierarchical levels.


A member tilting mechanism includes a housing rear having a concave spherical portion, a cap support having a convex spherical portion, a plate pivot having a pivot portion, which is a tubular portion with an arc-like cross section, a spring plate which presses against the cap support towards the housing rear in such a manner that the plate pivot is allowed to tilt in such a state that the pivot portion is held by the concave spherical portion and the convex spherical portion, a tapping screw for fixing the spring plate to the housing rear, and a stopper that is fixed to the housing rear for restricting the deformation of the spring plate in an anti-pressing direction. According to this structure, the stopper restricts the deflection of the spring plate in the anti-pressing direction so as to prevent the excessive tilt of the plate pivot.

1. Field of the Invention
The present invention relates to a member tilting mechanism for use in, for example, a vehicle door or side mirror system and a mirror system incorporating the member tilting mechanism.
2. Description of the Related Art
In general, a tilting mechanism is adopted to be installed in, for example, a vehicle door or side mirror system for tilting a mirror surface vertically and horizontally so as to adjust the mirror surface angularly. This tilting mechanism is normally provided within a mirror housing and is configured as described in, for example, JP-A-2003-194040 (FIGS. 6 and 7). Namely, this tilting mechanism includes, as shown in instant FIG. 10, a housing front 2 that is fixed to a body member (not shown) and is adapted to accommodate therein a motor 1, a housing rear 3 that is covered by the housing front 2, a plate pivot 4 that is mounted on the housing rear 3 and on which a mirror (not shown) is mounted, and a substantially semispherical cap support 5 which holds the plate pivot 4 in such a manner as to be tilted together with the housing rear 3 therebetween.
On the housing rear 3, a concave spherical portion 3a is formed and a cylindrical support tube portion 3b is provided at a center of the concave spherical portion 3a so formed in such manner as to protrude along a central axis thereof. In addition, a convex spherical portion 5a is formed on the cap support 5 along an outer circumference thereof, and a through hole 5b is also formed in the cap support 5 so that the support tube portion 3b can pass therethrough. Furthermore, a pivot portion 4a, which is a tubular portion with an arc-like cross section, is formed on the plate pivot 4 in such a manner as to slide and tilt while being held between the concave spherical portion 3a and the convex spherical portion 5a.
The support tube portion 3b is put in such a state that the support tube portion 3b is caused to lie or is passed in the through hole 5b in the cap support 5, and a tapping screw 7 is screwed into a mount hole in the support tube portion 3b from an upper end of the support tube portion 3b with a spring plate 6, which is a leaf spring member, placed on the upper end of the support tube portion 3b, whereby the spring plate 6 is fixed in place thereat. The spring plate 6 is formed into a cruciform shape, and a spring center portion 6a is fixed to the support tube portion by means of the tapping screw 7, and distal end portions of deflection portions 6b which extend from the spring center portion 6a radially in four directions are made to press against an outer edge portion of the cap support 5 so that the cap support 5 is pressed towards the housing rear 3. According to this structure, the convex spherical portion 5a is brought into press contact with the pivot portion 4a, which is, in turn, brought into press contact with the concave spherical portion 3a, whereby the convex spherical portion 5a and the pivot portion 4a are allowed to slide relative to the pivot portion 4a and the concave spherical portion 3a, respectively, through such spherical contacts. Consequently, the plate pivot 4 is supported in such a manner as to be tilted in all directions relative to the housing rear 3.
In addition, an adjusting screw 2a is provided in the housing front 2 in such a manner as to protrude therefrom, and an adjusting nut 9 is screwed on the adjusting screw 2a. A worm wheel 10, which is connected to a rotational shaft of the motor 1 and is allowed to move relatively in an axial direction of the rotational shaft, is brought into integral engagement with an outer circumference of the adjusting nut 9 relative to a rotational direction. Furthermore, a spherical joint portion 9a is formed at a distal end portion of the adjusting nut 9, which is then made to fit in a concave joint portion 4b formed in the plate pivot 4 in a press fit state.
Consequently, by driving the motor 1, the adjusting nut 9 moves in the axial direction via the worm wheel 10, so that the plate pivot 4 in which the distal end portion of the adjusting nut 9 is fitted is pushed or pulled, whereby the pivot plate 4 can be electrically tilted together with the mirror. Note that the motor 1, adjusting screw 2a, adjusting nut 9, worm wheel 10 and concave joint portion 4b are each provided in two for vertical and horizontal adjustments.
The related art still has, however, the following problems to be solved.
In the tilting mechanism described in JP-A-2003-194040, when mirrors are replaced at a repair shop or the like, if the mirror is pulled in a direction A indicated in FIG. 10, the plate pivot 4, which is fixed to the mirror, is also pulled in the direction A. While the plate pivot 4 can normally be deflected to a position where a restriction is applied, in the event that the mirror continues to be pulled further in the direction A from that condition, the spring plate 6 is deflected in an opposite direction to the pressing direction (an anti-pressing direction B), whereby the mirror and the plate pivot 4 are deflected excessively, often leading to a problem that the adjusting nut 9 is dislocated from the adjusting screw 2a.
In addition, while the adjusting nut 9 continues to push the plate pivot 4 until a restriction is applied while being operated electrically, the plate pivot 4 is lifted excessively by such an extent that the spring plate 6 deflects, whereby the plate pivot 4 and the housing rear 3 are made to be separated from each other, often leading to a problem that loosening (beating) occurs in the mirror.
To cope with this, while there is considered a method for making it difficult for the spring plate 6 to be deflected by increasing the spring constant thereof, in this case, the sliding resistance of the pivot portion 4a is also increased, often resulting in a problem that the increase in the sliding resistance inconveniently constitutes a cause for a malfunction.

Member tilting mechanism and mirror system


A communication apparatus includes a storage part configured to store a first key generated according to authentication with a transmission source, identification information of the transmission source, and first information remaining unchanged regardless of the initialization of a coupling status and corresponding to the transmission source, with the first key, the identification information and the first information mapped to each other, an acquisition part configured to acquire a public key from the transmission source holding the identification information responsive to the first information stored on the storage part if the identification information of the transmission source has changed in response to the initialization of the coupling status, and a calculation part configured to generate an encryption key for use in encryption and decryption of data transmitted by the transmission source, based on the first key responsive to the first information, and the public key.

A digital interface installed on a digital versatile disc (DVD) player or the like includes an IEEE1394 high performance serial bus performing copyright management, data encryption, and communication.
In an encryption method applied in encryption and communication, authentication is performed first between a transmitter and a receiver. Two types of authentication are formulated, namely, full authentication based on a public key encryption method and restricted authentication based on a secret key method. The restricted authentication handles two types of data (content), namely, no more copy data and copy one generation data. The full authentication handles copy never data in addition to the no more copy data and the copy one generation data. Once authentication of any type has been successfully completed, a transmitter 100 and a receiver 200 share the similar authentication key Kauth. The transmitter 100 produces an exchange key Kx on a per data type basis (such as no more copy, copy one generation, and copy never). The transmitter 100 then encrypts the exchange key Kx with the authentication key Kauth into an encryption exchange key Ksx, and then transmits the encryption exchange key Ksx to the receiver 200. Upon receiving the encryption exchange key Ksx, the receiver 200 decrypts the encryption exchange key Ksx with the shared authentication key Kauth into the original exchange key Kx. The receiver 200 has thus successfully performed the authentication process, and commonly shares the similar exchange key Kx with the transmitter 100.
The transmitter 100 prepares another public key, namely, nonce for content channel (Nc). The transmitter 100 performs a calculation process using two keys, i.e., the exchange key Kx and the public key Nc, thereby producing a content key Kc. The transmitter 100 encrypts data to be transmitted using the content key Kc (encryption key) and then transmits the encrypted data to the receiver 200. The receiver 200 produces the content key Kc using the two keys, i.e., the public key Nc and the shared exchange key Kx, and decrypts the encrypted data from the transmitter 100 using the content key Kc.
Through the encryption method described above, the receiver 200, once successfully authenticated, can check the content of the encrypted data. A receiver which has not undergone the authentication process cannot recognize the value of the content key Kc (the exchange key Kx). Even if the transmitted encrypted data has been successfully acquired, the receiver cannot decrypt the encrypted data. Unauthorized copying is thus prevented.
A similar technique is discussed in the paper entitled "High-speed Interface, Application to IEEE1394 AV Devices" authored by Shinji TAKADA, and published by Nikkan Kogyo Shimbun Ltd., January 2000, pp. 133-149.
In order to transfer data, the authentication process needs to be performed between the transmitter and the receiver using one of the full authentication and the restricted authentication. The full authentication and the restricted authentication undergo a complex calculation process, and take time. In particular, the full authentication includes an extremely complex calculation process that is based on a digital signature algorithm (DSA) and a Deffie-Hellman (DH) key exchange algorithm based on elliptic curve cryptographic technique. A long period of time is needed to perform the authentication process.
If noise is induced on an IEEE1394 bus, a bus reset can be initialized. The authentication process needs to be performed again subsequent to the bus reset. For this reason, the encrypted data cannot be decrypted on the receiver until the authentication process and key exchanging subsequent to the authentication process are completed. Data communication is thus suspended for a long period of time.

Communication apparatus, data communication method, and network system


A data driver is provided that comprises: a state controller that effects transition to any of multiple states including a display ON state, a display OFF state and a sleep state, then outputs a drive control signal associated with a state of a transition destination; and a drive circuit that drive the data lines using drive power corresponding to a drive signal based on the drive control signal. When first setting data is input during the sleep state, the state controller effects transition from the sleep state to the display OFF state, and when second setting data is input during the sleep state and is followed by input of the first setting data, the state controller effects transition from the sleep state to the display OFF state, then effects transition from the display OFF state to the display ON state.

1. Field of the Invention
The present invention relates to a data driver and an electro-optic device.
2. Description of the Related Art
Display panels, typically in the form of liquid crystal panels, are installed in portable apparatuses such as cellular phones. For this reason, further reduction of consumption power is required for a display panel and a drive circuit, which drives the display panel.
The drive circuit generally includes a digital component and an analog component. Because the digital component is composed of a CMOS (complementary metal oxide semiconductor) circuit, its power consumption can be reduced by an appropriate control, which does not vary signals of the digital component. The power consumption of the analog component of the drive circuit can be reduced by an appropriate control, which shuts off current of a current source, for example.
The drive circuit may have a power circuit for generating drive power and an oscillating circuit for generating a clock for drive control and display control. Such power circuits and oscillating circuits require a certain period to attain steady operation. Moreover, it is necessary to consider product-to-product variations in some cases. This has made it problematic to conduct the above-described fine-tuned control for the drive circuit.
The present invention has been made in consideration of the above-described technical problem, and its purpose is to provide a data driver and an electro-optic device, in which control is simpler and more fine-tuned.


An electronic device includes a plurality of chip components and an insulating case. The chip components are arranged in a first direction. The case includes a plate portion, a first protrusion portion, and a second protrusion portion. The plate portion faces first side surfaces of the chip components. The first protrusion portion is formed along a plate-portion first side of the plate portion and protrudes from the plate portion toward a downside perpendicular to the first direction. The second protrusion portion is formed to the first protrusion portion in a second direction and protrudes from the plate portion toward the downside. A protrusion length of the first protrusion portion and the second protrusion portion from the plate portion toward the downside is smaller than a protrusion length of the chip component included in the chip components from the plate portion toward the downside.

The present invention relates to an electronic component including a plurality of chip components.
An electronic device in which a plurality of chip components, such as chip capacitors, is integrated using a board is proposed (see Patent Document 1). In such an electronic device, the plurality of chip components can be mounted altogether on the board, and an advantageous effect for simplification and speeding up of mounting process is thereby exhibited as compared with ones in which chip components are mounted individually.
In conventional electronic devices in which a plurality of chip components is integrated with a case or so, however, the plurality of chip components needs to be positioned to the case and assembled one by one at the time of assembling, and there is a problem that it takes time and effort to position the chip components and the case and to store the chip components into the case.    Patent Document 1: JPH118158 (A)


An apparatus for applying a coating to an object includes a pair of reciprocating members which each include a porous resilient pad mounted for movement toward and away from each other. The apparatus includes a coating supply system for supplying coating to the resilient pads. The pads have a movement sequence from an initial rest position where the pads are spaced apart from one another to a coating loading position where the pads are in physical contact and have a degree of compression with each other to load the coating onto the pads, then the pads are moved to an intermediate rest position with the pads spaced apart an the object to be coated is moved between the pads. The sequence then includes a coating delivery position where the pads are in physical contact with each other and the object so that the pads have a degree of compression with each other and the object thereby applying the coating to the object.

Medical devices are often assembled from components formed from many different materials. It often is necessary to apply a coating of a lubricant to one or more of the components so that a component of one material will readily slide against a component of another material. Examples of this type of application are catheters with guidewires, over-needle catheters, syringe plunger stopper within a syringe barrel, needles for penetration of blood collection tube stoppers and the like. In other medical device applications, a lubricant is applied to a device to ease its penetration into the body. Examples of these applications are surgical blades, hypodermic needles, peripheral venous catheters and the like.
In all of these medical device lubrication applications, there are strict requirements on the amounts of lubricant, the uniformity of the application and a need to avoid contamination of the device with foreign material other than the lubricant. A further requirement on application of lubricant results from the high volume production requirements often resulting in the use of high speed assembly equipment. Thus, any lubricant application must be precise and compatible with high volume production.
Currently, a commonly used lubricant for medical devices is "silicone," i.e., polydimethyl siloxane having a Brookfield viscosity between about 1,000 and 20,000 centistokes (cs). For some applications, the silicone is applied "neat", i.e., without solvent. An example of neat application of silicone to syringe plunger stoppers is disclosed in U.S. Pat. No. 5,207,293 to Eden et al. This patent discloses a method and apparatus for lubricating syringe stoppers by moving the stoppers between a pair of wheels which are positioned partially in a reservoir containing lubricant so that with rotation of the wheels, lubricant is transferred to the stoppers.
Another commonly used neat application method is tumbling a measured quantity of small parts, such as stoppers, with a measured quantity of lubricant so that the parts acquire a coating of the lubricant.
Silicone lubricant also may be sprayed onto the parts either neat or in a carrier solvent. Neat spraying has been found to work well for interior surfaces such as inside syringe barrels. Solvent based dipping or spraying is commonly used for coating hypodermic needles and catheters. Chlorofluorcarbon solvents have proven to be very satisfactory for the delivery of silicone onto medical devices because they are non-toxic, non-flammable, inert, evaporate rapidly without leaving residue and are available in very high purity. Unfortunately, because of the belief that chlorofluorocarbon solvents are responsible for destruction of ozone in the upper atmosphere, most commonly used chlorofluorocarbon solvents will no longer be available. Alternate solvents such as hydrocarbons are flammable, and aqueous based systems generally are not practical for silicones.
Thus, there is a need for an apparatus that is compatible with high production volume and capable of uniformly delivering precise quantities of lubricant to medical devices.

Method for coating objects with a porous resilient matrix


A printer monitoring interface is disclosed that uses a combination of dynamic three dimensional representations of a printing system and actual photographic images (still or video) of problem areas to give an operator monitoring the printing system realtime feedback, in both graphical and actual-image form, of areas of the printing system experiencing problems. The graphical images (which may also be actual photographic images) provide the operator with a representation of the overall system, and the actual images of problem areas provide the operator with the ability to actually see the problem that is occurring. The graphical and actual-image views are combined so that the operator can quickly and easily identify where in the system the problem is occurring, and quickly diagnose problems and determine solutions.

1. Field of the Invention
This invention relates to the monitoring of printing systems and, more particularly, to a system for providing realtime status information for a printing system.
2. Description of the Related Art
The ability to instantly communicate the status of a printer to a user is limited by the text-based and two-dimensional graphical user interfaces used for communicating the printer status in the prior art. Problems are depicted in text format or diagram drawings; such depictions provide a generic representation of a problem and do not fully communicate the actual state of the printer. For example, if a paper jam occurs in the printing system, the printer operator must often reference a diagram displayed on a small screen that displays an iconic representation of the problem area without giving anything other than a general indication where in the printing system the particular area is located. This makes it very difficult to determine precisely where the printer jam has occurred or to diagnose the exact nature of the problem, and is particularly problematic in large, high-production printing systems that may occupy one or more entire room(s). Because these high-production printers are very expensive to run, quickly identifying and diagnosing printing problems and identifying the system state saves time and money by increasing printer up-time.
Accordingly, it would be desirable to have a printer monitoring system that provides a user with a more realistic depiction of the printing system being monitored and that can display actual views of problem areas correlated to the particular location in the overall printing system in which the problems are occurring.


A vehicle is disclosed. The vehicle includes a body. The body includes a forward end and a rearward end spaced from each other along a longitudinal axis. The forward end of the body defines an opening for allowing airflow into the body. The vehicle also includes a venturi brake duct assembly positioned relative to the opening to receive the airflow from the opening and to guide the airflow to a brake device for cooling the brake device.

Vehicles can include a brake duct which collects a flow of air and directs the airflow to a brake device to cool the brake device. Generally the brake duct is in fluid communication with an opening in a forward end of the vehicle. For example, the opening may be defined in a front bumper.
Many different brake ducts have been designed. For example, one type of brake duct utilizes a square or circular cross-sectional tube having a constant cross-sectional area, and this tube directs the airflow to the brake device. Another type of brake duct utilizes a ramp that is formed in the front bumper which changes the direction of the airflow, and thus does not utilize a tube. Yet another type of brake duct utilizes a flap that can move between a first position closing the opening and a second position opening the opening. With this type of brake duct, the flap is motorized to move the flap between the positions, and thus does not utilize a tube. The above discussed brake ducts can cause drag on the vehicle which can affect the fuel efficiency of the vehicle.


The present invention provides a flash EPROM cell structure that has the advantages of source-side injection, but which is formed in such a way as to allow it to be utilized in a virtual-ground buried bit-line array layout. The buried bit-line array confers two advantages over the more conventional T-cell array. It allows contacts to be shared among a large number of cells, thereby reducing the layout area associated with each cell. This leads to smaller chip size. Moreover, the yield of the array is significantly increased due to the drastic reduction in the total number of contacts in the array.

1. Field of the Invention
The present invention relates to electrically programmable read only memory (EPROM) devices and, in particular, to a flash EPROM cell that utilizes source-side injection, but which is formed to allow it to be utilized in a virtual ground buried bit-line array.
2. Discussion of the Prior Art
A. T. Wu et al., "A Novel High-Speed Five-Volt Programming EPROM Structure With Source-Side Injection", IEDM 1986, p. 584, introduced the concept of source-side injection EPROM cells. Source-side injection cells provide for improved efficiency of hot electron injection during programming. A further key feature of the Wu et al. cell is that the efficiency of hot electron injection is no longer a function of the drain junction profile, in contrast to conventional EPROM cells.
These features make the Wu et al. cell particularly suitable for use as a flash memory cell. In a "flash" EPROM, all storage registers in the memory array are electrically erased in a single operation. A flash cell requires the erasing source or drain node to have a high junction breakdown voltage, whereas the abrupt junction profile required for a conventional EPROM cell gives rise to a low junction breakdown voltage. This advantage of the Wu et al cell architecture was highlighted in U.S. Pat. No. 4,794,565, issued Dec. 27, 1988.
As described in the two above-cited Wu et al. documents, the source-side select gate of the device was a floating node. This gives rise to serious problems, since the floating node tends to become charged during cell programming, changing the device's characteristics.
K. Naruke et al., (1) "A New Flash-Erase EEPROM Cell With A Sidewall Select-Gate On Its Source Side", IEDM 1989, p. 603 and (2) European Patent Application No. 0 335 395, also disclose a flash EPROM cell based on the concept of source-side injection. The concept is much the same as that disclosed in the above-cited Wu et al. patent except that Naruke et al. specifically state that contact is made to the select gate and describe a masking technique for accomplishing this.
The Naruke et al. cell is shown in plan and cross-sectional view in FIGS. 1A-1C. The Naruke et al. array layout is shown in FIG. 2.
The main disadvantage of the Naruke et al. cell relates to the array layout. The above-cited Naruke et al. European patent application specifies that the select gate electrode extends in a direction perpendicular to the flow of current from source to drain. This implies that the only possible array configuration is the one shown in FIG. 2, which is commonly referred to as a "T-cell" array. This type of array is the one most commonly used for EPROM and flash memories, but has some disadvantages for very high density memories. Specifically, the T-cell array needs one contact for every two memory cells. Thus, a 16 Mbit array would require 8 million contacts. This large number of contacts creates serious yield limitations for this technology.
In addition, the Naruke et al. cell requires a narrow polysilicon spacer, which forms the select gate, to run the entire length of each word line. The difficulty of reliably forming this structure tends to further degrade the yield of the array. Moreover, the high resistance per unit length of the spacer increases the word line turn-on delay, degrading array access speed.

Buried bit-line source-side injection flash memory cell


A coated article with metallic finish which comprises a base layer of a paint containing metallic powder and, if necessary, color pigment applied to the substrate and a topcoat applied to said base layer, said topcoat being formed by applying and curing a coating material composed mainly of a silyl group-containing vinyl polymer or copolymer having the main chain composed substantially of a vinyl polymer and at least one silicon atom connected to a hydrolyzable group at the terminal or side chain per molecule.

1. Field of the Invention:
This invention relates to a coated article with metallic finish. More particularly, it relates to a coated article with metallic finish formed by applying a priming coat containing metal powder and, if necessary, a color pigment, to the substrate, and subsequently applying a topcoat containing a vinyl polymer having the main chain composed substantially of vinyl polymer chain and having at least one silyl group having a silicon atom connected to a hydrolyzable group at the side chain or terminal per molecule, and finally curing the coating.
2. Description of the Prior Art:
Heretofore, the metallic finish of automotive bodies has been accomplished with a variety of paints such as nitrocellulose lacquer, modified acrylic lacquer, straight acrylic lacquer, polyurethane paint, and baking enamel. These paints, however, were not satisfactory in fastness to weathering when used as a topcoat for metallic finish. In actual use, the coated film of these paints undergoes cracking, discoloration, blistering, and peeling when exposed to intense sunlight for a long period of time.

Kanegafuchi Kagaku Kogyo Kabushiki Kaisha


Methods for manufacturing 7-ethyl-10-[4-(1-piperidino)-1-piperidino]-carbonyloxy-camptothecin are described comprising                I. reacting a mixture of 1-chlorocarbonyl-4-piperidinopiperidine hydrochloride and 7-ethyl-10-hydroxycamptothecin in a polar aprotic solvent with a base in the presence of catalytic amounts of a N-containing cyclic organic compound having 3 to 20 carbon atoms and optionally in the presence of a water binding agent in an amount which effectively binds any water present in the above reactants and solvents; or        II. reacting:                    (a) 7-Ethyl-10-hydroxycamptothecin in a polar aprotic solvent with phosgene, trichlormethyl-chloroformate, bis(trichloromethyl)carbonate or a alternative to phosgene and a base in the presence of catalytic amounts of a N-containing cyclic organic compound having 3 to 20 carbon atoms; and            (b) subsequently with piperidinopiperidine and an amine base.

U.S. Pat. No. 4,604,463 describes the preparation of 7-Ethyl-10-[4-(1-piperidino)-1-piperidino]-carbonyloxycamptothecin (I) by condensation of 7-ethyl-10-hydroxycamptothecin (II) with 1-chlorocarbonyl-4-piperidinopiperidine hydrochloride (III) in pyridine at room temperature.
According to WO200519223 this method leads to coloured impurities in the product. In order to avoid these, 7-Ethyl-10-[4-(1-piperidino)-1-piperidino]-carbonyloxycamptothecin was prepared by condensation of
7-ethyl-10-hydroxycamptothecin of formula
with 1-chlorocarbonyl-4-piperidinopiperidine hydrochloride of formula
in a polar aprotic solvent such as acetonitrile and in the presence of 4-dimethyl-aminopyridine. The condensation proceeds in suspension, where the polar aprotic solvent dissolves only 4-dimethylaminopyridine whereas 7-ethyl-10-hydroxycamptothecin and 1-chlorocarbonyl-4-piperidinopiperidine hydrochloride in this polar aprotic solvent remain undissolved. The amount of 1-chlorocarbonyl-4-piperidinopiperidine hydrochloride employed in the condensation reaction is preferably 1.3 to 3 mol, more preferably 1.6 to 1.9 mol, per 1 mol of 7-ethyl-10-hydroxycamptothecin. The amount of 4-dimethylaminopyridine used in the condensation ranges preferably between 1.5 and 4 mol, more preferably between 1.8 and 2.2 mol, per 1 mol of 7-ethyl-10-hydroxycamptothecin. The amount of the polar aprotic solvent used in the condensation is preferably 400 to 600 mol, more preferably 430 to 460 mol, per mol of 7-ethyl-10-hydroxycamptothecin. The condensation is performed preferably at a temperature from 70 to 80° C., more preferably at 73 to 77° C.


A semiconductor memory device is described that has an improved read characteristics. The semiconductor memory device includes a plurality of memory cells, a reference cell, a comparator located between the memory cells and the reference cell, and a discriminator coupled to the comparator. The comparator compares the actual signal equivalent to a value of a current flowing in each of the memory cells and reference signals equivalent to a value of a current flowing in the reference cell with each other to output a comparison result signal in each of data reading operation modes. The discriminator discriminates a value of data stored in each of the memory cells based on the comparison result signal. The discriminator includes a circuit shared for discrimination of a data value in each of the data reading operation modes.

1. Field of the Invention
The present invention relates generally to a semiconductor memory device. More particularly, this invention relates to a flash EEPROM (Electrical Erasable and Programmable Read Only Memory) with improved read characteristics for data having multi values.
2. Description of the Related Art
Considerable attention has recently been given to non-volatile semiconductor memories, such as a ferro-electric memory, EPROM (Erasable and Programmable Read Only Memory) and EEPROM (Electrically Erasable and Programmable Read Only Memory). To store data, an EPROM and EEPROM use a floating gate for storing charges and a control gate for detecting a change in threshold voltage according to the presence or absence of charges in the floating gate. EEPROMs include a flash EEPROM which can perform data erasure for the entire memory chip or partial data erasure for each of a plurality of blocks in the memory cell array. There are two general types of memory cells in a flash EEPROM: a split gate type and a stacked gate type.
1) Split Gate Memory Cell
International Publication WO92/18980 discloses a split gate flash EEPROM. FIG. 1 presents a schematic cross-sectional view illustrating a split gate memory cell 101 disclosed in this publication.
The split gate memory cell 101, which is formed on a single crystalline silicon substrate 102 having a P type conductivity, has a source S of an N type conductivity, a drain D of the N type conductivity, and a channel CH defined between the source S and drain D. The memory cell 101 further has a first insulator film 103, a floating gate FG provided on the first insulator film 103, a second insulator film 104 provided on the floating gate FG, and a control gate CG provided on the second insulator film 104. A part of the control gate CG is arranged on the channel CH via the first insulator film 103 to serve as a select gate 105.
FIG. 2 is a block diagram showing a flash EEPROM 121 having a plurality of split gate memory cells 101. The flash EEPROM 121 includes a memory cell array 122, a row decoder 123, a column decoder 124, an address pad 125, an address buffer 126, an address latch 127, a data pin 128, an input buffer 129, a group of sense amplifiers 130, an output buffer 131, a source voltage controller 132, a drain voltage controller 133, a gate voltage controller 134 and a control core circuit 140.
The memory cell array 122 has a matrix of split gate memory cells 101, a plurality of word lines WLa to WLz, each commonly connected to the control gates CG of an associated row of memory cells 101, a plurality of bit lines BLa to BLz, each commonly connected to the drains D of an associated column of memory cells 101, and a common source line SL connected to the sources S of all the memory cells 101. The word lines WLa-WLz are connected to the row decoder 123, and the bit lines BLa-BLz are connected to the column decoder 124.
The address pad 125 receives a row address and a column address supplied from an external unit (not shown) and transfers the row and column addresses to the address latch 127 via the address buffer 126. The address latch 127 transfers the latched row address to the row decoder 123 and transfers the latched column address to the column decoder 124.
The row decoder 123 selects one word line (e.g., WLm) from the word lines WLa-WLz in accordance with the row address and connects the selected word line WLm to the gate voltage controller 134. The column decoder 124 selects one bit line (e.g., BLm) from the bit lines BLa-BLz in accordance with the column address and connects the selected bit line BLm to the sense amplifier groups 130 or the drain voltage controller 133.
The gate voltage controller 134 controls the electric potential on the word line WLm, which is connected thereto via the row decoder 123, in accordance with the individual operation modes shown in FIG. 3. The drain voltage control 133 controls the electric potential on the bit line BLm, which is connected thereto via the column decoder 124, in accordance with the individual operation modes shown in FIG. 3.
The common source line SL is connected to the source voltage controller 132, which controls the electric potential on the common source line SL in accordance with the individual operation modes shown in FIG. 3.
The data pin 128 receives data supplied from the external unit (not shown) and supplies the data to the input buffer 129. The input buffer 129 transfers the data to the column decoder 124. The column decoder 124 controls the electric potential on any selected one of the bit lines BLa-BLz in accordance with that data.
Data read from an arbitrary memory cell 101 is transferred from the associated one of the bit lines BLa-BLz to the sense amplifier group 130 via the column decoder 124. The sense amplifier group 130 includes a plurality of sense amplifiers (not shown). The column decoder 124 operates to connect the selected bit line BLm to the sense amplifiers. The sense amplifier group 130 discriminates data and sends this data to the external unit via the output buffer 131 and the data pin 128.
The control core circuit 140 controls the operations of the row decoder 123, the column decoder 124, the address buffer 126, the address latch 127, the input buffer 129, the sense amplifier group 130, the output buffer 131, the source voltage controller 132, the drain voltage controller 133 and the gate voltage controller 134.
The individual operation modes (erase mode, write mode and read mode) of the flash EEPROM 121 will now be discussed referring to FIG. 3.
(a) Erase Mode
In erase mode, the electric potential on the common source line SL and all the bit lines BLa-BLz is held at the ground level (0 V). A voltage of 14 to 15 V is applied to a selected word line WLm, and the electric potentials on the non-selected word lines WLa-WLl and WLn-WLz are kept at the ground level. Therefore, the control gates CG of the individual memory cells 101 that are connected to the selected word line WLm are pulled up to 14 to 15 V. Accordingly, data stored in all the memory cells 101 connected to the selected word line WLm are erased.
When the electric potential of the control gate CG is 14 to 15 V and the electric potentials of the source and the substrate are 0 V, a high electric field is produced between the control gate CG and the floating gate FG. Then, a Fowler-Nordheim (FN) tunnel current flows between both gates. Consequently, electrons in the floating gate FG are pulled out to the control gate CG, so that data stored in the memory cells 101 are erased. This erasing operation is based on the electrostatic capacitances between the source S and the substrate 102 and floating gate FG being significantly greater than that between the control gate CG and the floating gate FG. Simultaneous selection of a plurality of word lines in the word lines WLa-WLz permits data erasure of all the memory cells 101 connected to the selected word lines. That is, as the memory cell array 122 is divided into a plurality of blocks corresponding to plural sets of word lines WLa-WLz, data erasure can be performed on each block. This erasing operation is called "block erasure".
(b) Write Mode
In write mode, the electric potential on the selected bit line BLm is kept at the ground level, while the electric potentials on the other bit lines (non-selected bit lines) BLa-BLl and BLn-BLz are kept at a level greater than the electric potential on the selected word line (in this case, 2 V).
A voltage of 2 V is applied to the word line WLm connected to the control gate CG of the selected memory cell 101, while the electric potentials on the other word lines (non-selected word lines) WLa-WLl and WLn-WLz are kept at the ground level. A voltage of 12 V is applied to the common source line SL.
Consequently, the electric potential of the floating gate FG is pulled up by the capacitive coupling between the source S and the floating gate FG. This produces a high electric field between the channel CH and the floating gate FG. Then, the electrons in the channel CH are accelerated to become hot electrons. Hot electrons are supplied to the floating gate FG as indicated by the arrow A in FIG. 1. As a result, charges are stored in the floating gate FG of the selected memory cell 101 and 1-bit data is written and stored there.
In each memory cell 101, a transistor, which includes a control gate CG, source S and drain D, has a threshold voltage Vth of 0.5 V. In the selected memory cell 101, therefore, electrons in the drain D are moved in the channel CH in the inverted state. Thus the current (cell current) flows to the drain D from the source S. This writing operation, unlike the erasing operation, may be executed for each selected memory cell 101.
(c) Read Mode
In read mode, a voltage of 4 V is applied to the word line WLm connected to the control gate CG of the selected memory cell 101, and the electric potentials on the other (non-selected) word lines WLa-WLl and WLn-WLz are held at the ground level. A voltage of 2 V is applied to the bit line BLm connected to the drain D of the selected memory cell 101, while the electric potentials on the other bit lines (non-selected bit lines) BLa-BLl and BLn-BLz are kept at the ground level.
As a result, the current (cell current), which flows to the source S of the memory cell 101 in the erased state from the drain D thereof, becomes greater than the cell current flowing in the memory cell 101 in the written state. This is because the channel CH directly below the floating gate FG of the data-erased memory cell 101 is enabled, while the channel CH directly below the floating gate FG of the data-written memory cell 101 is disabled. This will be discussed specifically.
As electrons are drained from the floating gate FG of the data-erased memory cell 101, the floating gate FG is positively charged. Therefore, the channel CH or the memory cell is enabled, permitting the current to flow. As electrons are supplied into the floating gate FG of the data-written memory cell 101, the floating gate FG is negatively charged. Thus, the channel CH or the memory cell is disabled to prevent the flow of the current.
Each sense amplifier in the sense amplifier group 130 discriminates the level of the cell current Id flowing in the associated memory cell 101 to read a data value stored in the memory cell 101. For instance, a data value "1" is read from the memory cell 101 in the erased state, and a data value "0" is read from the memory cell 101 in the written state. In this manner, binary data having a data value "1" indicating the erased state and a data value "0" indicating the written state are stored in each memory cell 101. Unlike the erasing operation, this reading operation may be performed for each selected memory cell 101.
U.S. Pat. No. 5,029,130 discloses a flash EEPROM in which the source S is called "drain" and the drain D is called "source". FIG. 4 is a schematic cross-sectional view illustrating a split gate memory cell 110, disclosed in this publication. FIG. 5 is a block diagram showing a flash EEPROM 111 that uses the split gate memory cells 110. FIG. 6 shows electric potentials on the individual lines and the substrate in the individual operation modes of the flash EEPROM 111.
The split gate memory cell 110 in FIG. 4 differs from the split gate memory cell 101 in that the source S and drain D in the former memory cell are called by the opposite names in the latter memory cell. Specifically, the source S in the memory cell 110 is called the drain D in the memory cell 101, while the drain D in the memory cell 110 is called the source S in the memory cell 101.
The flash EEPROM 111 in FIG. 5 differs from the flash EEPROM 121 in that the common source line SL is grounded. In any operation mode, the electron potential on the source line SL is kept at the ground level.
There has been a proposal to replace the source voltage controller 132 in the flash EEPROM 121 with a source current controller. In this case, the source current controller controls the electric potential on the common source line SL in accordance with the individual operation modes as shown in FIG. 3 by controlling the cell current value Id to a given value.
It has also been proposed to replace the drain voltage controller 133 in the flash EEPROM 121 or the flash EEPROM 111 with a drain current controller. In this case, the drain current controller controls the electric potential on the bit line BLm in accordance with the individual operation modes as shown in FIG. 3 or FIG. 6 by controlling the cell current value Id to a given value.
Further, it has been proposed to design the flash EEPROM 121 so as not to connect the sources S of the whole memory cells 110 to the common source line SL, but to selectively connect the sources S of a row of memory cells 110 to the common source line. In this case, the flash EEPROM 121 is provided with a source line decoder, which selects one source line in accordance with the column address and connects the selected source line to the source voltage controller 132.
In order to improve the integration of flash EEPROMs, recently, some attempts have been made to store data having three or more values (multi value) besides storing two-value (1-bit) data in each memory cell in the erased state and the written state.
FIG. 7 presents a characteristic graph illustrating the relationship between the value of the cell current Id flowing through the split gate memory cell 101 or 110 and the electric potential Vfg of the floating gate FG. This electric potential Vfg of the floating gate FG (hereinafter referred to as "floating gate potential") indicates the electric potential of the floating gate FG with respect to the electric potential of the source S and is closely associated with the cell current. As apparent from this graph, multi-value data having four values ("00", "01", "10" and "11"), for example, can be stored in each memory cell. The floating gate potential Vfg is given by the following equation: EQU Vfg=Vfgw+Vfgc
where Vfgw is the electric potential that is produced by the charges stored in the floating gate FG in write mode, and Vfgc is the potential produced by the capacitive coupling with the drain D. In a read operation, the electric potential Vfgc is constant so that the cell current value Id is primarily determined by the electric potential Vfgw. In a write operation, the amount of charges in the floating gate FG may be controlled by adjusting the write operation time or the applied voltage. That is, the floating gate potential Vfg may be controlled by adjusting the write operation time or the write operation voltage to control the amount of charges in the floating gate FG. This control permits the cell current value Id in read mode to be set to an arbitrary value.
Suppose that, as shown in FIG. 7, a data value "00" is associated with the area of the cell current value Id, which is less than 40 .mu.A, a data value "01" is associated with the area of the cell current value Id that is equal to or greater than 40 .mu.A and less than 80 .mu.A, a data value "10" is associated with the area of the cell current value Id that is equal to or greater than 80 .mu.A and less than 120 .mu.A, and a data value "11" is associated with the area of the cell current value Id that is equal to or greater than 120 .mu.A. In this case, the write operation time is adjusted such that individual floating gate potentials Vfg (Va, Vb and Vc) corresponding to the individual cell current values Id (40 .mu.A, 80 .mu.A and 120 .mu.A) in write mode are acquired.
Since electrons have been drained from the floating gate FG of a data-erased memory cell 101 or 110, that memory cell is in the same state as the state in which the data value "11" is stored. At this time, the floating gate has an electric potential Vfg equal to or greater than the electric potential Vc (2.5 V).
When the writing operation commences and charges are stored in the floating gate FG, the floating gate potential Vfg drops. If the writing operation is stopped when the floating gate potential Vfg becomes equal to or greater than Vb (1.5 V) and less than Vc (2.5 V), the data value "10" is written in the memory cell 101 or 110. If the writing operation is stopped at the time the floating gate potential Vfg becomes equal to or greater than Va (1.0 V) and less than Vb, the data value "01" is written in the memory cell 101 or 110. If the writing operation is stopped when the floating gate potential Vfg becomes less than Va, the data value "00" is written in the memory cell 101 or 110. In this manner, four-value (2-bit) data is stored in a single memory cell 101 or 111.
Since a constant voltage (4 V) is applied to the control gate CG in read mode, the channel CH serves as a constant resistor. Therefore, the transistor having the floating gate FG, the source S and the drain D are connected in series to the constant resistor (the channel CH) in the split gate memory cell 101 or 110. When the floating gate potential Vfg is less than a given value (3.5 V), therefore, the cell current value Id varies in accordance with the characteristics of the transistor.
When the floating gate potential Vfg is smaller than the threshold voltage Vth (0.5 V) of the transistor in the memory cell 101 or 110, which has the floating gate FG, the source S and the drain D, the cell current value Id is 0. When the floating gate potential Vfg exceeds the threshold voltage Vth, the cell current value Id increases (See FIG. 7). When the floating gate potential Vfg exceeds 3.5 V, the cell current value Id is saturated due to the dominance of the constant resistor (the channel CH).
2) Stacked Gate Memory Cell
FIG. 8 is a schematic cross-sectional view showing a stacked gate memory cell 201. The stacked gate memory cell 201 has a source S and a drain D both having an N type conductivity and defined on a single crystalline silicon substrate 202 having a P type conductivity, and a channel CH defined between the source S and the drain D. The stacked gate memory cell 201 further has a first insulator film 203, a floating gate FG arranged on the first insulator film 203, a second insulator film 204 arranged on the floating gate FG, and a control gate CG arranged on the second insulator film 204. The floating gate FG and the control gate CG are stacked one on the other without being deviating from each other. Therefore, the source S and the drain D are symmetrical to the gates FG and CG and the channel CH.
FIG. 9 is a block diagram showing a flash EEPROM 221 having a plurality of stacked gate memory cells 201. This flash EEPROM 221 differs from the flash EEPROM 121 using the split gate memory cells 101 shown in FIG. 1 in the following points:
(1) The memory cell array 122 has a plurality of stacked gate memory cells 201 arranged in a matrix form. PA1 (2) The sources S of the individual memory cells 201 aligned in individual columns are commonly connected to the associated bit lines BLa-BLz. PA1 (3) The drains D of all the memory cells 201 are connected to a common drain line DL, which is connected to a common drain line bias circuit 222. The bias circuit 222 controls the electric potential on the common drain line DL in accordance with the individual operation mode under the control of the control core circuit 140.
The names for the sources S and the drains D of the split gate memory cell 101 and the stacked gate memory cell 201 are determined based on the reading operation; the terminal to which a high electric potential is applied in the reading operation is called a "drain" while the terminal to which a low electric potential is applied is called a "source". The same applies to the names for those terminals, the source S or the drain D, in the writing operation and the erasing operation.
The individual operation modes (erase mode, write mode and read mode) of the flash EEPROM 221 will now be discussed referring to FIG. 10.
(a) Erase Mode
In erase mode, all the bit lines BLa-BLz are set in the open state and the electric potential on the selected word line WLm is kept at the ground level. The common drain line bias circuit 222 applies a voltage of 12 V to the drains D of the memory cells 201, connected to the selected word line WLm, via the common drain line DL. As a result, the FN tunnel current flows, and the electrons in the floating gates FG are drained toward the drains D, so that data stored in the memory cells 201 are erased. This erasing operation is executed for all the memory cells 201 connected to the selected word line WLm. By selecting a plurality of word lines in the word lines WLa-WLz, data in all the memory cells 201 connected to those selected word lines may be erased (block erasure).
(b) Write Mode
In write mode, a voltage of 12 V is applied to the word line WLm that is connected to the control gate CG of the selected memory cell 201, and the electric potentials on the other word lines (the non-selected word lines) WLa-WLl and WLn-WLz are kept at the ground level. A voltage of 5 V is applied to the bit line BLm connected to the source S of the selected memory cell 201, and the electric potentials on the other bit lines (the non-selected bit lines) BLa-BLl and BLn-BLz are kept at the ground level. The common drain line bias circuit 222 holds the electric potentials of the drains D of all the memory cells 201 at the ground level via the common drain line DL.
Then, the capacitive coupling with the control gates CG pulls up the electric potentials of the floating gates FG and causes hot electrons produced in the vicinity of the sources S to be supplied into the floating gates FG. As a result, charges are stored in the floating gate FG of the selected memory cell 201 and 1-bit data is written and stored there.
(c) Read Mode
In the read mode, a voltage of 5 V is applied to the word line WLm connected to the control gate CG of the selected memory cell 201, while the electric potentials on the other words lines (the non-selected word lines) WLa-WLl and WLn-WLz are held at the ground level. The electric potentials on all the bit lines BLa-BLz are kept at the ground level. The common drain line bias circuit 222 applies a voltage of 5 V to the drains D of all the memory cells 201 via the common drain line DL.
As a result, the cell current, which flows to the source S of any data-erased memory cell 201 from the drain D thereof, becomes greater than the cell current flowing in any data-written memory cell 201 as in the case of the split gate memory cell 101. It is thus possible to store two values, the data value "1" in the erased state and the data value "0" in the written state, in each memory cell 201.
A flash EEPROM using stacked gate memory cells 201 that store multi-value data has been proposed. FIG. 11 presents a characteristic graph illustrating the relationship between the value of the cell current Id flowing through the stacked gate memory cell 201 and the electric potential Vfg of the floating gate FG. The floating gate potential Vfg is the electric potential of the floating gate with respect to the electric potential of the source S.
In the stacked gate memory cell 201, the floating gate FG and the control gate CG are stacked on one another in alignment. In the stacked gate memory cell 201, unlike in the split gate memory cell 101, the channel CH does not serve as a constant resistor but has only the function of a transistor. When the floating gate potential Vfg is less than the threshold voltage Vth (1 V) of the memory cell 201, therefore, the cell current value Id become zero. When the floating gate potential Vfg exceeds the threshold voltage Vth, the cell current value Id is positively proportional to the floating gate potential Vfg, and multi-value data may be stored in the memory cell.
Even in the stacked gate memory cell 201, therefore, the floating gate potential Vfg is controlled by adjusting the write operation time or the applied voltage to control the amount of charges of the floating gate FG or the electric potential Vfg.
Suppose that, as shown in FIG. 11, the data value "00" is associated with the area of the cell current value Id which is less than 40 .mu.A, the data value "01" is associated with the area of the cell current value Id that is equal to or greater than 40 .mu.A and less than 80 .mu.A, the data value "10" is associated with the area of the cell current value Id that is equal to or greater than 80 .mu.A and less than 120 .mu.A, and the data value "11" is associated with the area of the cell current value Id that is equal to or greater than 120 .mu.A and less than 160 .mu.A. In this case, the write operation time is adjusted in such a way that individual floating gate potentials Vfg (Va, Vb, Vc and Vd) respectively correspond to the individual cell current values Id (40 .mu.A, 80 .mu.A, 120 .mu.A and 160 .mu.A). In this manner, four-value (2-bit) data may be stored in a single memory cell 201.
To accurately write data in the multi-value storing operation of a flash EEPROM, it is essential to precisely control the floating gate potential Vfg of the memory cell 101, 110 or 201 in write mode. That is, it is important to accurately set the floating gate potential Vfg of the memory cell after writing to the desired value. For example, Japanese Unexamined Patent Publication No. 4-57294 discloses a currently popular verify write technique.
The verify write technique first performs writing to memory cells 101, 110 or 201 for a given time (several hundred nanoseconds to several microseconds) and then performs a read operation for verification (verify read operation). In the subsequent writing operation, the data value to be written is compared with the data value that has been read in the read operation (comparing operation). The read data value is what has actually been written in the writing operation. When the data value to be written and the read data value do not match with each other, writing is executed again for a given time. The cycle of the writing operation, the verify read operation and the comparison is repeated until both data values match.
In the above-described non-volatile semiconductor memory, a data value that has been written is discriminated by comparing a read data value (the value of the current flowing in a memory cell) with a reference data value in the verify read operation.
The reference data value is generated by using a circuit that has a reference cell as shown in, for example, FIG. 12. FIG. 12 shows a circuit which is adapted for reading data from the memory cells 101 of the split gate flash EEPROM adapted for data writing and data reading. In general, the discrimination of 4-value data requires seven types of threshold values, namely, a threshold value E for verify read determination in erase mode, threshold values R1 to R3 for normal read determination, and threshold values P1 to P3 for verify read determination in write mode.
FIG. 13 shows the distribution of the cell current that an EEPROM for 4-value data requires. Although the cell current varies cell by cell, the cell current of each cell should fall within four ranges corresponding to four values. For this purpose, seven types of threshold values are set between the individual current ranges.
The circuit in FIG. 12 has seven reference cells 301 to 307 associated with the seven threshold values needed for reading and determining 4-value data and a reference cell switching circuit 308 for selectively connecting the reference cell necessary for each operation to a sense amplifier circuit 309.
The sense amplifier circuit 309 compares the reference current, which is produced in the selected reference cell, with the actual current that flows through the memory cell 101 of interest and outputs the comparison result. When the reference current is equal to or larger than the real current, for example, a signal of an H (High) level is output. When the reference current is less than the real current, a signal of an L (Low) level is output. This sense amplifier circuit 309 is incorporated in the sense amplifier group 130. In FIG. 12, the column decoder 124 located between the memory cells 101 and the sense amplifier circuit 309 is omitted for simplifying this description.
The circuit in FIG. 12 further comprises a reference potential generator 310 for applying voltages to the floating gates FG of the reference cells 301-307. This generator 310 is provided to easily acquire from the reference cells the currents used as references for the determination in read mode. The voltages generated by this generator 310 are not applied to the memory cells 101 or 110. Note that there is a case where a stacked gate flash EEPROM uses ordinary MOS transistors that do not have floating gates as reference cells.
To directly apply a voltage to the floating gate FG, the reference cells 301-307 in the prior art are formed with different shapes and in a different process from those of the actual memory cells 101. Even if the reference cells 301-307 are designed strictly, the formed reference cells would have characteristics little different from those of the actual memory cells due to a slight process variation. This variation in characteristics does not raise a significant problem in a binary memory, which affords a large margin for the threshold values for data determination. In a multi-value memory, which cannot afford a large margin for the threshold values for data determination, however, such a variation may raise a problem like an error in data discrimination based on the threshold values or the occurrence of an undiscriminatable state. This problem becomes more serious as the number of values in multi-value data increases.

Semiconductor memory device with improved read characteristics for data having multi values


A method for preventing a call of packet data from colliding in a WLL system is disclosed, by which the packet transmission times of respective terminals are allocated using random numbers. The method includes initializing the random number and a call connecting time and transmitting packet data to a Radio Port (RP) after the initialization is completed. New and unique random numbers are assigned to the respective terminals based on the packet data transmitted from the terminals. The packet data is transmitted to the RP at the call connecting times corresponding to the random numbers.

1. Field of the Invention
The present invention relates to a packet data transmission in a Wireless Local Loop (WLL) system and, more particularly, to a method for preventing a call collision of packet data.
2. Background of the Related Art
Generally, a Wireless Local Loop (WLL) System provides respective subscribers with wireless subscriber lines, unlike the background art wired subscriber network that connects an exchanger and the respective subscribers using wired subscriber lines. According to the background art, the voice band data transmission speed is limited to 64 kbps. However, a digital wireless line subscriber network can provide high speed digital data service, more than 64 kbps without using a modem. Also, a service supplier can reduce the installation expenses, installation terms, and various additional services using the WLL system. For example, the WLL system can provide Plain Old Telephone Service (POTS), data service, and Integrated Services Digital Network BRD (ISDN BRD) service.
The WLL system can be technically divided into a WLL exclusive technique, a cellular technique, and a cordless technique. The cellular technique is considered the most suitable idea for embodying the WLL system. Also, the WLL system has similar characteristics to those of a mobile communication network regarding the use of a wireless channel as a communication media. However, the WLL system has better a propagation environment than that of the mobile communication network because the WLL system does not have roving characteristics. In the WLL system, an antenna of a terminal can be installed at a high position, such as a rooftop. Therefore a line-of-sight is ensured and the signal propagation suffers a small loss of about 20 dB/decade. Therefore, a broad region can be served with the same transmission power as that of the mobile communication network.
Fading phenomena caused by multiple channels happens even less than in the mobile communication network, of a point-to-mobile station method, because the WLL system uses a point-to-point communication method. Also a hand-off is not generated because the WLL system is a fixed wireless communication network and the call disconnect is not generated. Therefore, an additional wireless channel for hand-off is not necessary.
A radio port and a terminal in the WLL system exchange data by establishing a communication path. The exchange method can be divided into a circuit exchange method, which sets communication paths whenever data is transmitted between transmission and receive terminals; a message exchange method, that is, an accumulation exchange method, in which an exchanger receives a message from a caller and transmits the message to a receiver; and a packet exchange method that transmits information as a packet unit, which is made by dividing data into packets and adding a header to the respective packets. With the packet exchange method, the exchanger selects an appropriate path according to an address of the receiver and transmits the packet. The packet exchange method includes a datagram method in which the respective packets are transmitted independently, regardless of their order. The datagram method has advantages such that a call setting step can be omitted when the path is set and it is flexible with respect to the call collision of the packet data.
The basic structure of the packet data transmission system, including the background art WLL system, will be described with reference to FIG. 1. The data transmission system including the background art WLL system comprises terminals A–C (100–120), which generate packet data; a WLL system 200 that transmits the generated packet data; an internet network 300 that transmits the packet data received from the WLL system 200 to an object terminal (not shown); a Public Switched Telephone Network (PSTN) network 400 that receives the packet data, transmitted from the WLL system 200, and transmits it to the object terminal (not shown); and an Operation Maintenance Center (OMC) 500 that serves the packet data transmitted from the WLL system 200. The WLL system 200 is located at a final end among the network elements and comprises a Radio Interface Unit (RIU) 210 that performs a Radio Frequency (RF) sending/receiving function for sending/receiving information through a radio interface, transmits a signal that is changed from RF to baseband to a subscriber interface, and converts a baseband signal to an RF signal; a Radio Port (RP) 220 and 221 for setting a call, restoring a call, and processing data related to power control; a Radio Port Controller (RPC) 230 for managing the RP 220 and 221 and controlling a message process needed to originate/terminate the call process; and a Radio Port Operation & Maintenance Center (RPOM) 240 for managing the RPC 230, the RP 220, 221, and the RIU 210 and performing subscriber and service management. In addition, the RP 220 includes a Packet Data Management Unit (PDMU) 220A that participates in the call connect between the terminal and the RP.
The packet data transmission method will be described with reference to FIGS. 1 through 4 as follows. The RP 220 transmits preamble data, used for synchronization, to terminals A–C 100–120 through a pilot channel and RIU 210 (S100). The RP 220 can transmit the preamble data to the terminals A–C 100–120 through the RIU 210 and the pilot channel because a PN code and a Hadamard code of the PDMU 220A and of the terminals A–C 100–120 are same.
The RP 220, which transmitted the preamble data to the terminals A–C 100–120, checks whether or not it is synchronized (S110 and S120). If so, the RP 220 transmits controlling information, carrying a terminal ID, to the terminals A–C 100–120 through a signal channel (S130). However, if the RP 220 is not synchronized, the RP 220 transmits preamble data to the terminals A–C 100–120, again, for synchronization.
The terminals A–C 100–120 receiving the controlling information identify whether there is an error in the controlling information (S140 and S150). If there is no error in the controlling information, the terminals A–C 100–120 check whether the terminal ID in the controlling information corresponds to their own ID (S160 and S170). If the IDs correspond with each other, terminals A–C 100–120 transmit packet data to the RP 220 through the RIU 210 and the signal channel (S180).
The structure of the general packet data will be described with reference to FIG. 2 as follows. The packet data comprises a protocol head 10, which is the controlling information part, and data 20. The protocol head 10 comprises IP addresses of the originating/terminating sides, identifying an origin and a destination, and Media Access Control (MAC) addresses (not shown), which are checksums for detecting data error, that is, physical addresses.
However, if there is an error in the controlling information or the terminal IDs do not correspond, terminals A–C 100–120 throw away the received controlling information and perform the synchronization operation again (S220).
The RP 220 transmits the packet data received from terminals A–C 100–120 to the RPC 230 (S190). The RPC 230 transmits the packet data to the object terminal (not shown) through the PSTN network 400, if the packet data transmitted from the RP 220 is voice packet data, and the object terminal (not shown) serves the transmitted voice packet data. However, if the RPC 230 receives general packet data, the RPC 230 transmits the general packet data to the object terminal through the internet network 300 and the object terminal serves the transmitted general packet data. Also, if the RPC 230 receives Operation & Maintenance (OM) data, the RPC 230 transmits the O&M data to the RPOM 240. The RPOM 240 transmits the O&M data to the OMC 500, and the OMC 500 serves the transmitted O&M data (S200 and S210).
However, when the packet data is transmitted using the packet exchange method, in the transmission system including the WLL system, the terminals A–C 100–120 share the same signal channel, unlike in the circuit exchange method. Therefore, as shown in FIG. 3, it is possible for all of the terminals A–C 100–120 to attempt a call connection at the same time. In this case, a call collision is generated between the terminals A–C 100–120 and the RP 220. Therefore, the packet data transmitted from terminals A–C 100–120 to the RP 220 may be lost or distorted.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.

Method for preventing call collision of packet data in a WLL system


High data rate, high diversity transmission is provided in a dual transmit antenna system over multiple sample times through the use of coding.

Multiple input multiple output (MIMO) is a radio communication technique in which both a transmitter and a receiver use multiple antennas to wirelessly communicate with one another. By using multiple antennas at the transmitter and receiver, a level of spatial diversity is achieved that may enable a wireless link to overcome certain deleterious channel effects, such as multipath fading. However, the use of multiple antennas alone may result in a sub-optimal level of diversity. There is a need for techniques and structures that are capable of enhancing the level of diversity achievable in a multiple antenna system.

High rate, high diversity transmission on multiple transmit antennas


This application provides for a new, synergistic combination of components for training an element of the golf swing normally referred to as lag. This new combination consists of a basic lag swing trainer which enables the golfer to attach additional multiple training tools or regulation golf clubs that can be interchangeably used at the same time. The additional combinations of tools that can be attached are unlimited, thereby letting golfers work on more than one of the various aspects of the swing all at the same time, for example, training the golfer in the proper sensations of the backswing technique, the swing plane, and the release of the golf club thru the hitting area. The Golf Swing Lag Training System provides any golfer with all of the kinesthetic and visual feedback that is essential to learning how to lag the golf club like a tour pro.

This invention relates to a new combination of components for giving unmistakable positive audio, visual and kinesthetic feedback to the user for training the movements of the body to properly execute a motion in the golf swing called lag. And, in particular, to a new combination of components and a method which includes a basic swing lag trainer to which the golfer can attach multiple training tools at the same time. For the first time in the history of golf instruction, a golfer can now combine and use multiple unlimited training tools together in order to learn how to develop the lag of a tour pro. This synergistic combination of elements provides a level of instruction and instant results that has been unattainable with any previous training aid by itself.
The golf swing is a most complicated movement that is best accomplished by the interaction of the alternating contraction and relaxation of opposing muscle groups. Because this movement occurs in less than two seconds and must be coordinated to the millisecond, it cannot be controlled by conscious thought. It must be trained through the subconscious mind. Thus while in training, it is desirable that the golfer have audio, visual and kinetic feedback of how the club is swung in a correct golfing stroke, so that they can keep mental interference to a minimum.
Once the club is cocked in the backswing, the most common mechanical fault among golfers is the premature releasing of the ninety-degree angle between the radial surface of the leading arm and the club. Professional golfers are said to retain this power angle through their swings longer than less accomplished amateur golfers and therefore, consistently obtain more accuracy and distance in their golf shots. Basically tour pros develop lag in their swings and amateur golfers do the opposite. The opposite of lag, the most common fault of recreational golfers, is called by many names, namely releasing early, flipping, clubhead throwaway, chicken winging, scooping, etc. 'Coming over the top and casting' the golf club is one of the most common descriptions given to this amateur affliction. Generally speaking, unless you are a Tour Pro or low single digit handicap golfer, you're 'coming over the top and casting' the golf club. Obviously, human beings as a rule, make the wrong moves when first presented with the problem of hitting a golf ball far and straight. Human being's are evidently pre-programmed by their DNA to make the 'coming over the top and casting' move. That would explain why seventy-eight percent of all golfers can't break ninety. The chief culprit in a golfer's poor scoring efforts resides mostly in the upper right quadrant of the body for a right-handed golfer. They bring this area of the body into play at the wrong time in the swing. I've long been fascinated with the three-dimensional aspects of the golf swing, such as the ninety degree and forty-five degree angles created as a golfer moves the club thru a full golf swing, things such as the clubhead rotating clockwise and counter-clockwise as it moves through the various positions of the swing. Unfortunately the straight shaft of a golf club is one-dimensional and does not give a golfer enough three-dimensional feedback to learn how the club should be positioned in time and space and the body sequencing needed to create the lag of a tour pro.
We have found that the holy grail of the mechanics of the golf swing is creating and sustaining lag and then releasing that lag at the exact millisecond which ensures solid contact with and compression of the golf ball. Lag in the golf swing is usually thought of as 'holding the ninety degree angle' formed by the leading arm and the club shaft. Lag allows you to create centrifugal force, which stores power until it is released at impact creating what every golfer desires, namely shots that fly long and straight. Lag creates the forward leaning shaft at impact, which is the popular term now for what happens in a tour pro's swing. Actually this is just one of the manifestations or effects that happen when you create lag in your swing.
We've all noticed that the tour pro's and their swings vary in setup, grip, body style—just about everything imaginable. But, the one thing they all do is create lag. To create lag, they all make the same motion from the "delivery zone" thru impact. So, it makes total good sense to concentrate on learning the one mechanical motion that separates the tour pros from the amateurs, lag. Unfortunately, this lag is an elusive feeling to capture on a consistent basis. The problem we all face is that, even though we know what happens mechanically in the golf swing down to the millisecond, we don't know how that movement feels. Albert Einstein explains the problem with this quote—"The only source of knowledge is experience, everything else is just data." We have all of this information about the swing, but it is only data. It doesn't and can't give us the feeling that a tour pro experiences when they create lag in their swings. And, since, we don't know the feel of lag and haven't experienced that feeling on a consistent basis, we are unable to create it at will.
Stewart Maiden, who was the teacher of Bobby Jones, agrees with us. He said, in 1922, that 'coming over the top and casting' the golf club was the main fault of the average golfer and the main cause of every other fault in their golf swings.
Obviously, conventional golf instruction hasn't addressed this issue or we wouldn't have the cover of golf magazines proclaiming how to correct your slice every other year for at least the last fifty years. One article will tell you how you should hold the ninety degree power angle of the lead forearm and the club as you swing down to the ball, the next article will tell you that you must release that angle right away in order to hold the angle. Conflicting advice is very common in conventional golf instruction and especially so in the matter of learning lag. Because of this dichotomy, golfers have no easy roadmap to achieving the lag of the tour pros in their own swings.
We happened upon the Golf Swing Lag Training System by a serendipitous sequence of events. For the last 25 years, we have been holding golf schools in Lawrence, Kans. and around the country. In 2004, I co-authored a book named Tour Tempo. It was published by Doubleday of New York and became an international best seller, because, for the first time in the history of golf, we explained how to easily learn the tempo of a tour pro by sequencing your swing to a series of scientifically spaced tones that were based on the swings of the tour pros.
Over this course of time, I would also continue to invent training aids that I thought would help the average golfer that came to our golf schools get better. It finally dawned on me that this lagging of the club was a very difficult proposition to master, and that this mechanical motion of lagging was what I had been actually working on all these years. The challenge, then, was to invent a simple to use system that gave golfers the ability to immediately learn the lag of a tour pro, and then, to combine that with Tour Tempo and allow them to now play the best golf of their lives.
We have accomplished this with the Golf Swing Lag Training System. It works with all golfers, from tour pros thru beginners. The reason it works is explained by Percy Boomer, the author of 'On Learning Golf' (the longest continuously published golf instruction book in the history of golf). He said that you learn the golf swing by stringing together a series of sensations. So, to paraphrase Percy, you link together a series of perceptions and/or feelings to learn how to create and sustain the lag of a tour pro in the golf swing. After over fifty-two years of playing golf and over twenty-seven years of teaching golf, I have to agree with Percy Boomer, learning to lag the club like a golf pro must be done by sensation, or as its more commonly known, by feel.
We have achieved significant, immediate results in clubhead speed, which is one of the main indicators of whether a golfer has lag or not. For example, a PGA tour pro has an average driver clubhead speed of 105 mph to 115 mph. Your recreational golfer's average driver clubhead speed is around 80 to 90 mph
We have sixty and seventy year old male golfers increasing their clubhead speed from an average of eighty mph with a driver to eighty-eight mph in less than five minutes of use of the Golf Swing Lag Training System. To give you an idea of how good this is we only need to peruse a 2007 study by the Department of Exercise and Sport Science, University of San Francisco, San Francisco, Calif. as reported in the Journal of Strength and Conditioning Research. They did a study to see how much more clubhead speed could be developed by older male golfers if they embarked on an 8-week progressive functional training program.
After putting in thirty-six hours of progressive functional training, which consisted of three 90 minute sessions a week for eight weeks, the golfers increased their clubhead speeds from 79.1 to 83.0 miles per hour. The authors of the study were very happy with a four mph increase with eight weeks of working out, when we were able to double that increase in five minutes. One of our test subjects, a sixty three year old male, increased his driver clubhead speed from 88 mph to over 105 mph in less than a month. Another test subject, a sixty year old lady golfer, increased her clubhead speed from 80 mph to 96 mph in less than a day. So we can see that by using the Golf Swing Lag Training System, golfer's have experienced new and unexpected results manifested by immediate and substantial increases in clubhead speed and lag.
The Golf Swing Lag Training System consists of five main components. The first is a basic lag trainer that through a clamping means can be interchangeably attached to the four other accessories, although it is not limited to the four, as we will explain. The basic lag trainer gives the golfer the sensation of how the wrists and forearms are used in the swing. The second component of the Golf Swing Lag Training System is a three-dimensional trainer that gives positive and negative feedback to the golfer as the swinging movement is made from start to finish. The third is an air resistance device that provides the correct feel of how the body is connectedly turned and rotated in the swing. The fourth is a shaft that includes a sliding mechanism that is best when only used with one arm at a time, although it could be used with both arms simultaneously. The sliding mechanism is constructed so that multiple and unique types of resistance can be attached to it. It gives the golfer the sensation of the correct release of the club through impact. The fifth component is a device that trains the golfer through kinesthetic feel how to engage the correct muscles at address and also how to use these muscles to start swinging the club into the backswing.
Even though we have found that this combination of devices is the best, it should be noted that regulation golf clubs and unlimited combinations of other training aids could also be mounted onto the basic lag trainer in order to learn the feel of a correct swing that exhibits the lag of a tour pro.
We have found that when any of these components or even other swing trainers are used only by themselves the results can be immediate, but with continued use of the individual trainer, these initial results will not endure. The golfer will only develop another incorrect movement in their swing, thereby losing the initial benefit that they experienced with that individual swing trainer. We have also found that for the majority of golfers, that the correct movements in the golf swing must be continually reinforced.
That's why the Golf Swing Lag Training System when joined together in the various combinations with the basic lag trainer obtains results that are quite immediate and spectacular and with continued use, they will endure for as long as the golfer plays the game. The students experience feelings and positions that their bodies have never gotten into, enabling them to dramatically increase their clubhead speed and impact alignments through emulating the lag of a tour pro. The point here is that you cannot repeat something that you've never been able to feel.
It's this new combination that provides the correct feelings of lag that are not available when the components are used separately.
A well known golf instructor, Manuel de la Torre, once said that it was important not to give a student something to work on that if they overdid it, it would become the opposite fault, i.e. correcting a slice and thereby turning that fault into a pull hook. With the Golf Swing Lag Training System, there is no problem with repeating the drills over and over, because the student is performing in real time the correct body movements and getting the instant feedback that helps them learn to lag the club like a tour pro. This provides the golfer with feedback on the correct holistic movement of the body in relation to the golf club throughout the entire stroke in an incrementally adjustable manner.
Another advantage that this device provides is that it helps a golfer co-ordinate the swinging of the arms and hands with the turning of the body. Most golfers don't know how to do this correctly. Any amateur golfer will tell you that it is very difficult to consistently replicate the coordination of the correct timing of all the body parts used in the golf swing. Many devices have been invented to alert the golfer when they are prematurely releasing the club with the incorrect movement. However, the Golf Swing Lag Training System is the only one that teaches the golfer the exact movements that they should be performing with their hand and wrists as they are coordinated with the turning of the body. Once the feel of lag is accomplished and trained, then ball contact is more consistent with every stroke in golf, from chipping and pitching, to the full swing. The Golf Swing Lag Training System provides immediate results in distance and accuracy of shots and can be used to rekindle the feeling of the correct swing even after a winter away from golf practice.
It should also be apparent that this could help any game where a participant is involved with an implement used to strike a ball. It is also apparent that various lengths and weights should be available to accommodate the difference in the bodies of men, women and children golfers.