A very long instruction word (VLIW) architecture and method provide for functionally expanding a parcel. The instruction register of the VLIW architecture is divided into a plurality of parcels, each of which has corresponding processing logic. The processing logic performs various functions based on the data within the corresponding parcel. A single parcel, however, can only specify a limited number of functions or include a limited amount of data for processing such that the level of optimization for a given VLIW may be impeded. The selector logic and processing logic, however, allow for data from a non-corresponding parcel to be selected and processed. In this manner, the functions and/or amount of data for processing in a single parcel can be expanded by using data from a non-corresponding parcel.

A modern computer system typically comprises a central processing unit (CPU), and other supporting hardware such as system memory, communications busses, input/output controllers, storage devices, etc. The CPU is the heart of the system. It executes the instructions which comprise a computer program and directs the operation of the other system components.
From the standpoint of the computer's hardware, all systems, from the earliest to the most modern, operate in fundamentally the same manner. Processors are capable of performing a limited set of very simple operations, such as arithmetic, logical comparisons, and movement of data from one location to another. But each operation is performed very quickly. The programs which direct the machine to perform massive numbers of these very simple operations give the illusion that the machine is doing something sophisticated. What is perceived by the user as a new or improved capability of a computer system is made possible by performing essentially the same set of very simple operations, but doing it much faster. Therefore continuing improvements to computer systems require that these systems be made ever faster.
The overall speed of a computer system (also called the "throughput") may be crudely measured as the number of operations performed per unit of time. Conceptually, the simplest of all possible improvements to system speed is to increase the clock speeds of the various components, and particularly the clock speed of the processor. E.g., if everything runs twice as fast but otherwise works in exactly the same manner, the system will perform a given task in half the time. Early computer processors, which were constructed from many discrete components, were susceptible to significant speed improvements by shrinking component size, reducing component number, and eventually, packaging the entire processor as an integrated circuit on a single chip. The reduced size made it possible to increase the clock speed of the processor, and accordingly increase system speed.
Despite the enormous improvement in speed obtained from integrated circuitry, the demand for ever faster computer systems has continued. Hardware designers have been able to obtain still further improvements in speed by greater integration (i.e., increasing the number of circuits packed onto a single chip), by further reducing the size of the circuits, and by various other techniques. However, designers can see that physical size reductions can not continue indefinitely, and there are limits to their ability to continue to increase clock speeds of processors. Attention has therefore been directed to other approaches for further improvements in overall speed of the computer system.
Without changing the clock speed, it is still possible to improve system speed by using multiple processors. The modest cost of individual processors packaged on integrated circuit chips has made this practical. It is now nearly universal, for example, to use slave processors to perform various tasks within a computer system, such as input/output device communications and control. Typically, such slave processors execute a single special-purpose program repeatedly. The use of such slave processors considerably improves system speed, by off-loading work from the CPU to the slave. It is also possible for multiple CPUs to be placed in a single computer system, typically a host-based system which services multiple users simultaneously. Each of the different CPUs can separately execute a different task on behalf of a different user, thus increasing the overall speed of the system to execute multiple tasks simultaneously.
It is much more difficult, however, to improve the speed at which a single task, such as an application program, executes. The problem with multiple CPUs is the coordination of function. For slave I/O processors this is not so difficult because function is pre-defined and limited. It is much more difficult to coordinate function among multiple CPUs executing general purpose application programs, the details of which the system designers don't know in advance. Most application programs follow a single path or flow of steps performed by the processor. While it is sometimes possible to break up this single path into multiple parallel paths, there is no known algorithmic approach for doing so. Generally, this must be done on a case-by-case basis, and in a non-automated manner. Such a time-consuming approach to programming is not justified for a vast array of application programs.
Thus, while multiple processors improve overall system performance, there are still many reasons to improve the speed of the individual CPU. If the CPU clock speed is given, it is possible to further increase the speed of the CPU (i.e., the number of operations executed per second) by increasing the average number of operations executed per clock cycle.
Various processor hardware design techniques have been used to increase the average number of operations executed per clock cycle. These have involved, for example, the use of pipelines, multiple execution units with look ahead hardware for finding instructions to execute in parallel, etc. Limited improvement is possible using these techniques, but the hardware support required is often massive.
Another approach is a hybrid in which a single CPU has characteristics of both a uniprocessor and a parallel machine. In this approach, a single instruction register and instruction sequence unit execute programs under a single flow of control, but multiple arithmetic/logic units (ALUs) within the CPU can perform multiple primitive operations (i.e., simple arithmetic, logic, or data transfer operations) simultaneously. Rather than hardware determining all the simultaneous operations to be performed at execution time, a compiler determines this before execution and formats the instructions in such a way to specify the parallel operations. Because the instruction word held in the instruction register must specify multiple independent operations to be performed by the different ALUs, this approach will typically employ a very long instruction word (VLIW) to perform such multiple independent operations, and it is commonly known as a VLIW architecture.
Several academic papers have suggested that a VLIW architecture can in many applications achieve greater parallelism and greater speed than multiple independent processors operating in parallel. The theory underlying VLIW is that the typical application program has a single flow of control, but many of the primitive operations within that flow can be performed in parallel. Therefore an automated compiler for a VLIW machine does not have to alter program flow (something which has been almost impossible to automate in parallel processor machines). It only has to determine which primitive operations can be performed in parallel. While even this is a difficult task in practice, it should lend itself to automation much more readily than the altering of program flow.
Although there has been some research and experimentation concerning VLIW architectures, such machines have yet to gain widespread commercial acceptance. The VLIW architectural concept is still in its early stages of evolution. A number of problems must be overcome before such machines can effectively compete commercially with more evolved older designs.
One such problem is the size and format of the instruction word. The expected size of the instruction word imposes significant burdens on the supporting hardware, such as memory, instruction cache, buses, etc. VLIW designs anticipate a large instruction word for several reasons. First, each of the ALUs requires its own command, which can include an operation code, source and destination designations, etc. Second, there must be a conditional branching mechanism appropriate to the VLIW architecture. Because many simple operations are being performed with each instruction, the effectiveness of a VLIW machine would be limited if only one conditional branch were allowed in a given instruction, as is usually the case in a conventional machine. Therefore it is desirable to permit conditional branching to multiple destinations from a single VLIW instruction, a characteristic referred to as N-way branching. Of course, all of the branch conditions and destinations must in some way be specified in the instruction. Third, because a theoretically pure VLIW design employs a large pool of data registers, and other special registers, any of which can be assigned arbitrarily as source or destination for the various operations, the number of bits in the instruction required for identifying each source and destination register is greater than for a conventional design employing a smaller number of registers.
A research report entitled "Some Design Ideas for a VLIW Architecture for Sequential-Natured Software," by Kemal Ebcioglu and published in Proceedings of IFIP WG 10.3Working Conference on Parallel Processing, (M. Cosuard et al., ed.) North Hellard 1988, discusses known techniques for compiling code into VLIWs and known VLIW architectures. Mr. Ebcioglu also suggests additional VLIW compilation techniques and VLIW architecture.
The major hardware components of a computer system 100 for utilizing a VLIW processor architecture are shown in FIG. 1. A CPU 101 for processing instructions is coupled to separate caches 103 and 104. Instruction cache (I-cache) 103 stores instructions for execution by CPU 101. Although illustrated as separate elements, the I-cache 103 and the data cache (D-cache) 104 can be disposed on the same chip as the CPU 101 and are often considered as forming a part of the CPU 101. D-cache 104 stores data to be used by CPU 101. Both caches communicate with random access, "main storage," memory 102. The CPU 101 and the main storage 102 also communicate via a bus interface 105 and system bus 110. Various I/O processing units (IOPs) 111-115 attach to the system bus 110 and support communication with a variety of storage and I/O devices, such as direct access storage devices (DASD), tape drives, workstations, printers, and remote communication lines.
FIG. 2 is a high level diagram of the major components of CPU 101 (except for main storage 102). It should be understood, however, that in FIG. 2 the various data paths within CPU 101 have been represented in greatly simplified form for clarity. In reality, many separate data paths into and out of the various components are required to support simultaneous data flow to and from multiple ALUs, registers, cache locations, etc. Additionally, many data and control lines have been omitted entirely from FIG. 2 for clarity.
An instruction register 200 stores the current instruction being executed by the CPU 101. The very long instruction word for which this approach is named becomes an integral part of the hardware when it is loaded into the instruction register 200. This single register must be large enough to store a full VLIW instruction because the entire instruction is needed to control the hardware for one cycle. The instruction contains "parcels" or "slots," each of which is equivalent to one elementary or primitive operation (such as ADD, COMPARE, or LOAD). When loaded into the instruction register 200, each parcel occupies a specific set of bit positions, and will control those hardware resources hard-wired to those positions. If an instruction does not contain the maximum number of parcels, (due to the compiler's inability to find sufficient parallelism for that point in the program) then the unused bit portions must be reset appropriately. The instruction also includes "mask" fields, which are the values against which conditional code settings are compared. The instruction further includes "next" fields which contain the address of the VLIW instruction to be loaded next if the condition codes match the corresponding mask.
Connected to the instruction register 200 is the I-cache 103 which stores the next instructions to be executed. As is well known, this I-cache 103 can include a series or levels of cache. Typically the levels of I-cache range from L0 cache to L1 cache on chip and L2 cache and L3 cache off chip. Preferably, the next instruction should be found in the L0 cache which is located closest to the instruction register 200; thus, reducing the amount of time needed to load the next instruction into the instruction register 200. Each successive level of cache is located further from the instruction register 200; and consequently, requires a longer period of time to load an instruction into the instruction register 200. Instructions not stored in the I-cache 103 are stored in main storage 102 connected to the I-cache 103. Besides storing instructions, main storage 102 may also store data.
Instruction decode and sequencer logic 202 is connected to the instruction register 200 and the I-cache 103. The instruction decode and sequencer logic 202 decodes the instruction in instruction register 200 to determine the operations to be performed, and determines the address of the next instruction to execute. Determining the next instruction to execute is performed in part based on the condition code values stored in condition registers 208. These condition code values are discussed in greater detail below.
Connected to the instruction register 200 are a plurality of arithmetic/logic units ALU0-ALU(N+M) where N+M can be any desired number but is typically 16 or less. Likewise, the number of parcels N+M can be any desired number. Each parcel provides an instruction to a corresponding one of ALU0-ALU(N+M) via the instruction decode and sequencer logic 202 (the connections between instruction decode and sequencer logic 202 and the ALU0-ALU(N+M) have been omitted for clarity). This same parcel will tell the ALU where to find the data upon which to operate, such as in the parcel itself or in one of a plurality of general purpose registers (GPRs) 204 connected to ALU0-ALU (N+M). As illustrated in FIG. 2, each of ALU0-ALU (N+M) can access GPRs 204. In fact, one GPR in the GPRs 204 is often used by more than one ALU in the same cycle, and each of ALU0-ALU(N+M) often accesses more than one GPR in the same cycle.
The VLIW hardware architecture of FIG. 2 includes two different types of ALUs. ALU0-ALU(N) execute normal arithmetic, logical and data movement operations. In ALU0-ALU(N), source data is supplied by either the parcel or from the GPRs 204, and target operand data flows from ALU0-ALU9 to the GPRs 204. These operations are referred to as "RR" operations or "register-register" operations. The parcels corresponding to ALU0-ALU(N) are also referred to as "RR" parcels.
ALU(N+1)-ALU(N+M) also perform the same operations as ALU0-ALU(N), but have additional functional capabilities. Specifically, ALU(N+1)-ALU(N+M) can also execute "RS" operations or "register-storage" operations. RS operations have some operands in the GPRs 204 and some operands in D-cache 104 which is connected to ALU(N+1)-ALU(N+M) and the GPRs 204. The value of this additional hardware is considered significant enough to implement for some ALUs, but not worth implementing for all ALUs. The parcels corresponding to ALU(N+1)-ALU(N+M) are called "RS" parcels. It is very important to assign the RS parcels to positions in the instruction register which control ALUs with the RS capability. The compiler must make sure that the number of RS operations in each VLIW instruction does not exceed the number of ALUs with that capability. Again, while the number of RR and RS ALUs in this embodiment is eight, any desired number of RR and RS ALUs could be used.
As illustrated in FIG. 2, ALU0-ALU(N+M) are also connected to condition registers 208. Each of ALU0-ALU(N+M) produces one condition code value on each cycle, and the results thereof are sent to condition registers 208. As discussed in Mr. Ebcioglu's paper, condition code values can represent greater than, less than, and equals for, for example, comparison operations. As a default, the condition code value output by an ALU will be stored in a specific condition register in condition registers 208 based on the position of the ALU. A parcel, however, can include a condition register select (CRS) field which will cause condition registers 208 to redirect the output of the corresponding ALU to a condition register in condition registers 208 specified by the CRS field.
As illustrated in FIG. 2, the D-cache 104 is also connected to the main storage 102. As discussed above, instructions and data reside together in main storage 102, but they are stored in two separate cache units. The separate units must each be large enough to accommodate the largest expected uses.
The VLIW architecture discussed above has been described in general terms. The number of ALUs, lengths of instruction registers, and size of GPRs, D-cache and main storage are all variables for the computer architect.
The connections between the instruction register 200 and the ALUs will now be described in greater detail. FIG. 3 illustrates in greater detail the connections between one ALU and a corresponding parcel 300, GPRs 204, and condition registers 208. Specifically, FIG. 3 illustrates in greater detail the connections to the source inputs 310 and 312 of one ALU. Since the connections between each ALU, the parcel corresponding thereto, the GPRs 204, and the condition registers 208 are the same, FIG. 3 only illustrates the connections of one ALU for the sake of clarity. Furthermore, it should be understood that the various data paths within CPU 101 have been represented in FIG. 3 in greatly simplified form for clarity. As would be recognized by one of skill in the art, in reality, many separate data paths into and out of the various components are required to support simultaneous data flow to and from multiple ALUs, registers, cache locations, etc. Additionally, many data and control lines have been omitted entirely from FIG. 3 for clarity.
Furthermore, it should be understood that while the VLIW architecture of FIGS. 1-3 is not the subject of the present application, these figures do not represent prior art.
FIG. 3 illustrates one example of a parcel in instruction register 200. In FIG. 3, four 3-to-8 decoders 302, 304, 316, and 318 are connected to the parcel 300. The 3-to-8 decoders 302 and 304 form part of a first selector logic 309, and the 3-to-8 decoders 316 and 318 form part of a second selector logic 324.
The two 3-to-8 decoders 302 and 304 supply decoded output to respective 8-way selectors 306 and 308 also forming part of the selector logic 309. The 8-way selector 306 is connected to the GPRs 204, and the 8-way selector 308 is connected to the GPRs 204 via the 8-way selector 306. The output of the 8-way selector 308 is connected to both source inputs 310 and 312 of the ALU. Similarly, the two 3-to-8 decoders 316 and 318 supply decoded output to respective 8-way selectors 320 and 322 also forming part of the second selector logic 324. The 8-way selector 320 is connected to GPRs 204, and the 8-way selector 322 is connected to GPRs 204 via the 8-way selector 320. The output of the 8-way selector 322 is connected to both source inputs 310 and 312 of the ALU. Additionally, the immediate field of the parcel 300 is connected to the two source inputs 310 and 312 of the ALU.
The condition code values output by the ALU are sent to a condition register selector 314. The condition register selector 314 selects one of the condition registers 208 in which to store the condition code values. As discussed above, this selection is performed according to a positional default unless the parcel includes a CRS field. Accordingly, the condition register selector 314 is also connected to the parcel 300 to receive the contents of a CRS field should one be present.
Next, the operation of the VLIW architecture illustrated in FIG. 3 will be described. Typically, the instruction register 200 is 500-1000 bits in length, and contains a predetermined number of parcels. Typically, each parcel is 32 bits long.
FIG. 3 illustrates one parcel 300. As illustrated, the first field of 6 bits of the parcel indicates the operation code OP, the next field RA of 6 bits indicates the source register, the following field RT of 5 bits indicates the destination register, the next bit is the safety bit SF, and the final 14 bits are the immediate field UI.
The operation code OP indicates the operation to be performed by the ALU (i.e., the instruction primitive). Typically, a VLIW architecture is based on a Reduced Instruction Set Computer (RISC) instruction set (i.e., instruction primitives from a RISC architecture). The source register field RA indicates the register from the GPRs 204 supplying one input to the ALU, the destination register field RT indicates the register in the GPRs 204 for storing the result produced by the ALU, the safety bit SF is used to mark a register during speculative code movement which is not material to this application and therefore will not be discussed further, and the immediate field stores data which forms the second input to the ALU.
The GPRs 204 preferably include 64 64-bit registers divided into eight groups each. The first selector logic 309 selects and outputs the contents of one of the GPRs 204 based on the register address field RA. Specifically, the upper 3 bits of the source register field RA are converted by the 3-to-8 decoder 302 to form an 8 bit selection address. The 8-way selector 306 uses the output of the 3-to-8 selector 302 to address one of the eight GPR groups in the GPRs 204. The lower 3 bits of the source address field RA designate a particular GPR within the group selected by the upper three bits. These lower 3 bits are decoded by the 3-to-8 decoder 304, and the 8-way selector 308 selects the specific GPR within the GPR group selected by the 8-way selector 306 based on the decoded output of the 3-to-8 decoder 304.
As shown in FIG. 3, the contents of the GPR selected by the 8-way selectors 306 and 308 may by supplied to either source input 310 or 312 of the ALU. As further shown, the immediate field of the parcel 300 may also be supplied to either source input 310 or 312 of the ALU.
For instance, assume that the operation to be performed is an ADDI operation wherein the contents of the GPR indicated by source register field RA are added to the data in the immediate field of the parcel 300. In this instance, the contents of the register addressed by the source register field RA are supplied to one of the source inputs 310 and 312 of the ALU, while the contents of the immediate field are supplied to the other of the source inputs 310 and 312 of the ALU. As one skilled in the art will readily appreciate, a controller (not shown) determines which of the ALU source inputs 310 and 312 receives the output of the 8-way selector 308 and the immediate field of the parcel 300.
The ALU then performs the addition operation, and outputs the result to either a GPR in the GPRs 204 designated by the destination register field RT, or a location within the D-cache 104 designated by destination register field RT.
The destination register field RT, however, includes only 5-bits. This is one bit less than the number required to address one of the 64 64-bit GPRs 204. To supply the sixth and most significant bit, the VLIW architecture of FIG. 3 employs parcel affinity. According to parcel affinity, the RR and RS parcels are alternately arranged in the instruction register 200 to form RR and RS parcel pairs. The first RR and RS parcel pair is an odd numbered pair, while the second parcel pair is an even numbered pair. The remaining parcel pairs are also designated odd or even based on whether the number of the parcel pair is even or odd. The most significant, sixth bit, is then set to one for odd parcel pairs and set to zero for even parcel pairs. The placement of parcels within even and odd parcel pairs is handled by the VLIW compiler.
Although not shown in FIG. 3, selector logic, similar to the first selector logic 309, supplies the ALU output to the GPR of GPRs 204 specified by the destination register field RT.
The condition code value produced by the ALU, such as carry overs during an addition operation, are supplied to the condition register selector 314. Based on the position of the ALU, the condition register selector 314 supplies the condition code value output by the ALU to an associated condition register within the condition registers 208 since the parcel 300 does not include a CRS field.
FIG. 3 further includes second selector logic 324. The second selector logic 324 performs the same operation as the first selector logic 309, but does so based on a second source register field RB (not shown). As discussed above, many parcel formats exist. For instance, parcel 300 could instruct that the contents of two GPRs in GPRs 204 are to be operated on. In this instance, the parcel 300 would include a second source register field RB. The first selector logic 309 would use the contents of the first source register field RA to send the contents of one of the GPRs 204 to one of the source inputs 310 and 312 of the ALU, and the second selector logic 324 would use the contents of the second source register field RB to send the contents of one of the GPRs 204 to the other of the source inputs 310 and 312 of the ALU. Of course, as recognized by one skilled in the art, the controller would have to control the outputs of the 8-way selectors 308 and 322 such that the register contents were sent to each of the ALU source inputs 310 and 312.
Besides arithmetic and logic operations, RISC primitives (i.e., operations directed by the parcels) include load/store operations. A load/store operation causes the processor to load data stored in one of the GPRs 204, D-cache 104, or main storage 102 and store this data in one of the GPRs 204, D-cache 102 or main storage 102. Such instructions are well-known in the art and will not be discussed in detail.
As discussed above with respect to FIG. 3, a parcel in a VLIW includes two and sometimes three register fields. Furthermore, while previous non-VLIW and some VLIW architectures included only 32 general purpose registers, the VLIW architecture of the embodiment of FIG. 3 preferably includes 64 64-bit GPRs. Thus, larger source and target register fields are required to address a particular GPR. Consequently, the number of GPRs and the number of register fields within a parcel have shrunk the remaining available space within a parcel.
For instance, in parcel 300 illustrated in FIG. 3, insufficient space exists for a CRS field which would instruct condition register selector 314 as to the condition register in the condition registers 208 in which to store the condition code values. Accordingly, the VLIW architecture of FIG. 3 must rely on a condition register selector 314 performing in a default mode wherein the condition register selector 314 stores the condition code values output by the ALU in one of the condition registers 208 which corresponds to the ALU based on the position of the ALU.
As one skilled in the art will readily appreciate, having to operate in this manner limits the level of optimization. For instance, for a condition code value to travel from the condition register storing the condition code value according to the default storage methodology to a component requiring the condition code value may take more than one clock cycle. By contrast, the propagation delay between that same component and a different condition register may only be one clock cycle or less. If the parcel 300 included a CRS field, the condition code value could have been directed to this closer condition register. When the processing of a parcel unexpectedly takes longer than one clock cycle, then the processing of the entire VLIW is delayed until processing of this parcel can be completed. Accordingly, such unexpected delays significantly and detrimentally affect optimization.
As a further consequence of the limited space available within a parcel, the immediate field of this embodiment is only 14 bits long. As one skilled in the art will appreciate, besides representing a mismatch with the instruction set architecture which is based on powers of 2, this places a limit on the value which the immediate field may represent. For instance, an immediate field of 14 bits cannot represent a number greater than 16,384. Unfortunately, many operations require operating on much larger numbers. Due to the limits placed on the immediate field, however, such functions may not be performed using a single immediate field. Instead, the immediate field must be broken into a series of RISC instructions by the compiler and performed over several VLIW. Accordingly, the operation takes several clock cycles to perform, and instructions dependent on the result must be delayed to subsequent VLIW by the compiler. Again, this places a severe limit upon the level of optimization.
Similarly, the memory offset required to perform a load/store operation may be larger than the size of the displacement field (D-field) in the load/store parcel. Accordingly, the load/store instruction must also be broken into a series of RISC instructions causing the operation to take several clock cycles.
One possible solution would, of course, be to expand the size of VLIW. It is, however, desirable to reduce or maintain the size of the instruction word, the attendant complexity and cost of the processor, and the instruction bandwidth, while at the same time maintaining sufficient flexibility of function to realize the advantages of the VLIW architecture. Additionally, the benefit of VLIW diminishes once a certain size is exceeded due, for example, to an increase in unexpected delays associated therewith.

VLIW architecture and method for expanding a parcel

International Business Machines Corporation


A system, method and computer-readable medium for facilitating customer service feedback utilizing embedded feedback links are provided. A consumer generates an inquiry to a service provider. The service provider generates a responsive communication that includes at least one feedback link embedded within the response communication. The consumer can manipulate the feedback link to instantiate a variety of actions, including the escalation of the consumer inquiry.

Consumer relations is a key component for merchants offering products or services. In one aspect, a merchant can focus on providing efficient purchase mechanisms for end consumers to encourage repeat purchases and/or recommendations to other consumers. In another aspect, the merchant can focus on providing efficient customer services mechanisms to establish clear communication channels for consumer feedback. The ability to resolve consumer feedback, such as a consumer inquiry, can often result in a consumer making a purchase or becoming a repeat customer.
In a traditional merchant model, a merchant may provide one or more customer service agents in a physical location to take consumer inquiries and attempt to resolve any outstanding issues. If the customer service agent is not capable of resolving an initial consumer inquiry, the agent can escalate the issue and involve additional customer service agents, such as a manager/supervisor. As part of the escalation process, the merchant may obtain live feedback from the consumer about whether the customer service agent(s) and the merchant's customer service processes were adequate.
The development and evolution of computer communication networks, such as the Internet, provides a new environment for merchants to reach consumers. In one common embodiment, a merchant utilizes a network interface, such as a World Wide Web ("Web") site, to offer products/services for sale. In such an environment, consumers interface with merchants through the network interface, such as a Web browser software application, and/or by additional communication mechanisms, such as electronic mail ("email"). Accordingly, purchases between the consumer and the merchant can be completed without any physical interaction between the parties. Such transactions are generally referred to as electronic commerce, or e-commerce, transactions.
Typically, an e-commerce merchant focuses on the mechanisms and features that promote efficient e-commerce transactions for consumers. However, because there is generally little or no physical interaction between the consumer and the merchant, customer service may be more difficult to accomplish properly. Many e-commerce merchants include some type of customer service mechanism that allows a consumer to send a consumer inquiry to the merchant. For example, e-commerce merchants can provide network-based consumer inquiry forms that transmit a consumer inquiry to the merchant via the communication network. Additionally, e-commerce merchants can publish specific electronic mail addresses that accept consumer inquiries. Once the merchant has obtained the consumer inquiry, most merchants attempt to resolve the consumer inquiry and notify the consumer with a responsive communication, typically in the form of an electronic mail message.
Although many merchants provide some form of customer service that allows a consumer to send consumer inquiries and receive a response, conventional e-commerce methodologies do not provide an efficient manner to escalate consumer inquiries that are not initially resolved by the response from the merchant. In one aspect, some e-commerce merchants provide an electronic mail address that a user can utilize to provide additional feedback. However, the electronic address approach can be deficient in that there is little control of the type of consumer feedback that the merchant will receive. Further, this approach also requires the user to initiate additional tasks, e.g., the free-form creation of an electronic mail, to provide feedback. In another aspect, some e-commerce merchants send consumers follow up messages that include some type of survey, either directly embedded in the message or accessed via a communication network link, for the consumer to complete. The follow up survey approach is generally not effective because consumers are typically not inclined to fill out surveys from merchants. Moreover, because the survey is transmitted as a separate message, this approach is not effective to allow a consumer to escalate a consumer inquiry at the time the escalation is needed.
Thus, there is a need for a customer service solution that provides an efficient framework for obtaining consumer inquiry feedback, including the ability to escalate an unresolved consumer inquiry.

System and method for facilitating customer service utilizing embedded client feedback links


The invention discloses an insertable medical device for delivering one or more pro-healing agents to a site of deployment of a stent in a blood vessel. The surface of the insertable medical device is coated with nano-carriers that include the one or more pro-healing agents encapsulated with one or more biological agents. The nano-carriers are released when the insertable medical device is expanded at the site. The nano-carriers thus released penetrate tissues at the site resulting in dissolution of the one or more biological agents. Thereafter, the one or more pro-healing agents are released from the nano-carriers at the site. Thus, an in-tissue release of the one or more pro-healing agents at the site is achieved thereby improving endothealization, extracellular matrix formation and healing at the site post deployment of the stent in the blood vessel.

The current methods of treating blockages in blood vessels include Percutaneous Transluminal Coronary Angioplasty (PTCA). The PTCA includes use of angioplasty balloons, Drug Eluting Stents (DESs) and Bare Metal Stents (BMSs).
In instances where the angioplasty balloons are used for treating the blockages, the inflation of the angioplasty balloons may stretch luminal layers of the blood vessel thereby resulting in inflammation at the site of treatment. The inflammation may further lead to restenosis thereby delaying healing of the blood vessel. In addition to the angioplasty balloons, the BMSs are also used post angioplasty.
The BMSs are generally covered by the tissues of the blood vessel in a timely manner. Thus, proper endothealisation may be achieved in case of the BMSs. However, because of the body's immune response to the BMSs and because of the injuries that may occur while deploying the BMSs, instances of inflammations may occur. The inflammations may eventually lead to restenosis.
As compared to the BMSs, the use of the DESs is associated with reduced instances of restenosis. However, the DESs coated on the inner surface with drugs may not allow the tissues of the blood vessel to cover the DESs thereby leading to improper endothealisation and delayed healing. Therefore, the use of the DESs is associated with problems like partial endothealisation and improper formation of extracellular matrix. The partial endothealisation and improper formation of extracellular matrix may further lead to delayed healing of the blood vessel thereby leading to unpredictable outcomes. The unpredictable outcomes may include sub-acute thrombus formation and late catch up that is not observed with the BMSs.
Additionally, the currently used DESs are coated with an anti-proliferative or immunosupressive drugs on an inner surface as well as an outer surface of the DESs. The anti-proliferative or immunosupressive drugs have the property of blocking a proliferation cell cycle of the tissues of the blood vessel. Further, the current DESs employ polymers for loading the drugs on the DESs. The use of polymers results in inflammation at the site of deployment of the DESs. The polymers also lead to complications like, improper coverage of the lesions in the blood vessel, improper release of the drug from the DESs, poor in-tissue drug release and in-tissue drug diffusion, thrombus formation, delayed healing, improper healing, focal restenosis and edge restenosis. The use of the polymers may not facilitate the tissues of the blood vessel to cover the DESs completely and in a timely manner thereby leading to poor endothealisation.
Further, because of the above-mentioned complications associated with the DESs, the patients are often prescribed with a long-term anti-platelet therapy that may extend up to the lifetime of the patient. This post-deployment drug regime has its own side effects and complications.
Therefore, there is a need in the art for an improved method for healing the blood vessels post deployment of the DESs. Further, there is need in the art for a medical device that can improve the performance of the DESs.

Method and an insertable medical device for delivering one or more pro-healing agents to a target site within a blood vessel post-deployment of a stent

Concept Medical Research Private Limited


A problem is, in a liquid crystal film in which an alignment layer and a liquid crystal composition layer having homogeneous alignment are formed on a support substrate, to improve adhesion between the alignment layer and the liquid crystal composition layer, and durability under a severe environment such as high temperature and high humidity. A solution is a non-liquid crystalline polymerizable compound having a radically polymerizable group and a cationically polymerizable group in a molecule is simultaneously used as an antistripping additive in a polymerizable liquid crystal composition layer having homogeneous alignment.

1. Field of the Invention
The present invention relates to a film having optical anisotropy (optically anisotropic film) that is obtained using a polymerizable liquid crystal composition containing an antistripping additive, and a liquid crystal display device including the optically anisotropic film.
2. Description of the Related Art
A polymerizable liquid crystal compound is used for an optically anisotropic film such as a polarizing plate, a polarized light reflecting plate and a retardation film (Patent literature No. 1). The reason is that the compound shows optical anisotropy in a liquid crystal state and the anisotropy is immobilized by polymerization. Optical characteristics required for the optically anisotropic film are different depending on a purpose, and therefore a compound having characteristics fit for the purpose is required. Control of the anisotropy is difficult alone by a compound used for an optical isomer in many cases. Therefore, such a compound may be occasionally used in the form of a composition in combination with various compounds.
The polymerizable liquid crystal composition may be occasionally used in the form of ink prepared by adding an organic solvent in order to adjust coating properties. In order to manufacture a film having optical anisotropy by using the polymerizable liquid crystal composition, the polymerizable liquid crystal compound, a photopolymerization initiator, a surfactant and so forth are dissolved into the organic solvent to prepare ink in which solution viscosity, levelability or the like is adjusted. The ink is applied to a substrate subjected to alignment treatment to dry a solvent to align a polymerizable liquid crystal composition on the substrate. Next, the composition is irradiated with ultraviolet light and polymerized, thereby immobilizing an alignment state.
The present inventors have so far found a polymerizable liquid crystal compound allowing formation of uniform homeotropic alignment on a glass substrate or a plastic substrate without forming an alignment layer on a support substrate using the polymerizable liquid crystal compound, and having excellent adhesion (Patent literature Nos. 6 and 7).
Moreover, as an apparatus allowing an observer to recognize a three-dimensional image, an image display apparatus is known in which the apparatus include an image generation part for displaying an image for a right eye and an image for a left eye on different regions, respectively, and a polarization axis control plate for mutually orthogonalizing polarization axes of polarized light entered into two different regions (see Patent literature Nos. 2 to 4, for example). A retardation film used for the three-dimensional image display apparatus is mainly formed into a patterned retardation film prepared by applying a polymerizable liquid crystal compound having a liquid crystal phase as a retardation material onto an alignment layer subjected to patterned alignment treatment, and photocuring the applied material. The polymerizable liquid crystal composition mainly used for the patterned retardation film forms homogeneous alignment, and an alignment layer is substantially necessary to form the homogeneous alignment. For the alignment layer, polyimide obtained by heating and imidizing polyamic acid is widely used, but imidization requires heating to 200° C. or higher, and thus use of such polyimide for a plastic substrate is quite difficult. A method for directly rubbing a plastic substrate is also applied without using polyimide, special facilities are necessary for removing dust and static electricity generated by the rubbing.
Consequently, a photoalignment technique also has been recently applied in which a certain polymer solution is applied to a plastics substrate, and then the applied material is irradiated with polarized ultraviolet light to provide the material with alignment ability. However, the technique has a problem of insufficient adhesion and durability of an interface between an alignment layer and a liquid crystal composition layer in a patterned retardation film including only the polymerizable liquid crystal compound. The insufficient adhesion and durability may occasionally cause, for example, when a protective film is stuck on the patterned retardation film for preventing scratching or dirt or the like during transportation, deposition of a liquid crystal composition layer of the patterned retardation film onto an adhesive surface side of the protective film upon removing the protective film to damage the patterned retardation film. In order to solve such a problem, a patterned retardation film formed of a liquid crystal composition layer containing an antistripping additive has been desired (see Patent literature No. 5). In Patent literature Nos. 6 and 7 as described above, study has been conducted on adhesion between a liquid crystal composition layer in homeotropic alignment, but no study has been conducted on adhesion and durability of a liquid crystal composition layer in homogeneous alignment. In particular, no study has been made on durability under a severe environment such as high humidity and high temperature.

Film using polymerizable liquid crystal composition containing peeling preventive agent


A food container for microwave heating or cooking has: a bottom portion having an area which is covered with a microwave non-transmittable material and which is located between the center and the periphery of the bottom portion; a side wall having an area covered with a microwave non-transmittable material; and a leg structure provided under the bottom portion. The temperature rises in the center portion and near the circumferential side portion is facilitated, thereby effectively and easily achieving uniform heating of a food such as a frozen food.

1. Field of the Invention
This invention relates to a food container containing processed or precooked foods, which are subjected to microwave heating, or chilled or frozen foods, which are subjected to microwave cooking or heating, and particularly to that allows for uniform temperature increases and uniform heat distribution in filled precooked foods (the aforesaid foods are hereinafter referred to as "precooked foods") when heated with a microwave oven.
2. Background of the Art
Precooked foods, which are easily used simply by heating with a microwave oven when served, are commercially available. Such precooked foods include gratin, lasagna, rice with curry, or the like, which is packed into a container for microwave heating. Heretofore, the containers for microwave heating normally have been made of a microwave transmittable material. However, the containers are associated with problems in that, upon heating with a microwave oven, the temperature of a portion of the precooked food near an inner side wall of the container is high while that of a center portion of the precooked food is low, and in that the temperature near the upper surface of the precooked food rises quickly while the temperature near the bottom of the container rises slowly.
In view of the above problems of unevenness in temperature and heating rates, various types of containers, which alleviate uneven heating when heating the containers containing precooked foods with a microwave oven, have been developed.
For example, Japanese Patent Publication No. 59-6789 discloses a food package for heating or cooking precooked foods using a hot air convection type of home-use microwave oven, which food package comprises a bottom, a circumferential side wall having an upper edge outwardly curved, and a tray having circumferential rims extending horizontally, wherein a circumferential surface of the side wall of the container, or at least an inner surface thereof, or an upper portion of the rims and a wall portion adjacent to their corners are made of or coated with a microwave reflective material or microwave non-transmittable material, and wherein the bottom is made of a microwave transmittable material, or is detachable.
Further, Japanese Patent Laid-open No. 52-112150 discloses a food container for microwave heating, comprising: a body having a bottom wall, a side circumferential wall, and projections projecting from the bottom wall and forming a plurality of segments; and a lid having a top wall made of a microwave transmittable material, a circumferential side wall, and projections projecting from the side circumferential wall and the top wall, wherein a plurality of individual segments are formed, separately from each other, by combining the body, the lid, and the respective circumferential wall and projections, and wherein the circumferential side wall and the projections of the lid extend to the interior of the segments of the body so as to fit into the circumferential side wall and the projections of the body. This patent application also teaches that selective heating suitable for a food stored in each individual segment can be conducted by selectively locating microwave-transmittable portions and microwave non-transmittable portions formed on the outer surface of the container, using a metal foil or ink, which does not transmit microwaves, on the outer surface of the body and the lid, thereby preventing transmission of microwaves therethrough.
As described above, various types of food containers for microwave heating have been developed. However, the container disclosed in Japanese patent publication No. 59-6789 can prevent an extreme temperature rise on the inner side of the circumferential walls or the corners; however, since, in the container, the side circumferential walls or the corners formed by the rims and the container are simply coated with a microwave non-transmittable material, a temperature rise in the center of the container, especially in the center of a frozen food adjacent to the bottom, cannot be controlled effectively. Thus, the container has a problem in that it is difficult to uniformly heat a precooked food at an even temperature rise.
On the other hand, the container for microwave heating disclosed in Japanese Patent Laid-open No. 52-112150 is designed for heating different foods stored in the respective segments by differentiating heating manners depending on the food; however, since heating of the respective segments is conducted by passing microwaves through a microwave transmission hole having a limited area located in the center, the temperature rises quickly in the center, but the temperature rises slowly at the circumferential wall and the corners. Thus, nonuniformity of heating cannot be avoided.
As described above, heretofore, any containers containing a frozen food for microwave heating do not allow uniform heating in the frozen food placed evenly in the containers, thereby limiting embodiments or applications of the containers.

Food container for microwave heating or cooking


The present invention relates to clinical decision support systems. In detail, the present invention relates to a method for determining the initial fibrinogen concentration in a biological sample, to the use of fibrinogen added to a biological sample in at least one predetermined concentration, to a device for determining the initial fibrinogen concentration in a biological sample, to a computer program comprising program code means for causing a computer to carry out at least several steps of the method according to the invention, to a computer readable non-transitory storage medium containing instructions for carrying out at least some steps of the method according to the invention, and to a kit for determining the initial fibrinogen concentration in a biological sample.

Fibrinogen is an important protein involved in coagulation. During normal blood flow, fibrinogen is soluble; however upon activation of the coagulation system fibrinogen is eventually converted by thrombin into fibrin. Fibrin subsequently polymerizes into insoluble fibrin fibers that, together with preferably activated platelets, form a clot. The normal concentration of fibrinogen is approximately 2.5 g/l with a range of about 1.5 to 3 g/l [Greer et al. (Ed.), Wintrobe's Clinical Hematology, 11th edition, page 720]. Yet in many cases the fibrinogen concentration can be outside the normal range, which might be associated with pathological disorders. For example, in hereditary hypofibrinogenemia patients the low concentration of fibrinogen due to sustained bleeding results in a dangerous situation which can be countered by the addition of blood products. On the other side of the spectrum elevated concentrations of fibrinogen are found to be correlated with an elevated risk of myocardial infarction (Bom et al., Arterioscler. Thromb. Vasc. Biol. (1998) 18(4): 621-625), thrombosis (Kamath and Lip, Q. J. Med. (2003) 96(10): 711-729) and prolonged inflammatory processes such as rheumatoid arthritis (Rooney et al., Rheumatology (2011) 50(8): 1458-1465). As a result of these varying fibrinogen concentrations and associated pathologies, the fibrinogen concentration test is a valuable clinical test. Unfortunately however, reliable point of care (POC) fibrinogen tests are not available and central lab test ordering in general takes to long for time critical situations, for example in the operating theater.
Numerous methods have been developed intending to accurately detect the level of fibrinogen in a plasma or blood sample (see for example Palarati et al., Clinical Chemistry (1991) 37(5): 714-719, for an overview of available techniques or EP 2 259 069).
Unfortunately all presently available methods are either very labor-intensive, such as the clot-recovery method, or need a calibration curve derived from a plasma sample with a known fibrinogen level to infer the sample's fibrinogen level, such as the Clauss assay or prothrombin-time-derived method. Whereas the former involves a lot of hands on time and therefore is difficult to automate, the latter needs calibration plasmas to be included in the test protocol. Such a method requiring at least two reference samples of blood plasma to calibrate the measurement is disclosed in EP 0 059 277. These kinds of methods are, however, not suitable for being incorporated in an automated device, e.g. a hand held point of care (POC), to detect the level of fibrinogen.

Method for determining the fibrinogen concentration in a biological sample


The invention relates to a rubber tire having a rubber tread intended to be ground-contacting which is relative electrically insulating and which has at least one thin, narrow, carbon black reinforced rubber strip integral the outer surface, or face, of said tread, each strip extending laterally across the tread to each of the tire's carbon black reinforced sidewalls.. In one aspect, said outer rubber strip, extends laterally across the outer surface of the tread which is designed to be ground contacting and connects with carbon black reinforced tire sidewalls to provide a path of reduced electrical resistance from the outer surface of the tire tread to the bead portion of the tire carcass and, thereby, such a reduced electrical resistance path from a vehicle to the road surface.. In another aspect, the said rubber tread intended to be ground-contacting, is primarily reinforced with silica.

Pneumatic rubber tires can be prepared with a rubber tread composed of diene-based, sulfur curable, elastomer(s) which can be quantitatively reinforced with silica and a minimal amount of carbon black, if any. The tire tread is designed to be ground-contacting and is usually of a lug and groove or a rib and groove design. Such designs are well known to those skilled in such art.
The tire may also be of a cap/base construction in which the tread cap is the outer portion of the tread designed to be ground-contacting with the associated lugs and grooves and/or ribs and grooves and the tread base underlies the tread cap and is positioned between the tread cap and the supporting tire carcass. Such tire construction is well known to those skilled in such art.
Rubber by itself, without added ingredients, is generally considered as being substantially an electrical insulator or, in other words, a rather poor conductor of electricity.
A carbon black reinforced rubber vehicular tire, while still providing a degree of resistance to flow of electricity, has a considerably higher electrical conductivity, or lower resistance to flow of electricity, than rubber without the carbon black reinforcement.
Silica is, basically, a relatively poor conductor of electricity and thus a substantially silica reinforced rubber tire tread which contains only a minimal amount, if any, of carbon black reinforcement is believed to be a relatively good electrical insulator, particularly as compared to a quantitatively carbon black reinforced rubber tire tread.
Therefore, it is desirable to provide a suitable path of relatively low electrical resistance between the tire bead portion and the tread outer surface for such a tire having a quantitative silica reinforced rubber tread and minimal, if any, carbon black reinforcement.
While the dissipation of generated electrical energy may not be completely understood, it is believed that, in one aspect and insofar as a vehicular tire is concerned, electricity may be transmitted primarily from the metal rim, of steel or aluminum, for example, thence on or through the carbon black reinforced rubber surface of the tire carcass to the outer surface of a carbon black reinforced rubber tread and thence to the ground.
As used herein, the terms "quantitatively reinforced with silica", "quantitative silica reinforced rubber" and the like are generally used in conjunction with a tire tread, and with a rubber tire tread cap, in a tread cap/base construction, which contains about 30 to about 100, sometimes preferably about 30 to about 90 phr, of silica, and which may also optionally contain carbon black in which the carbon black is present in not more than about 30 phr. Often it is preferred that the ratio of silica to carbon black is at least 2/1 and sometimes at least 10/1.
The term "phr" as used herein, and according to conventional practice, refers to "parts of a respective material per 100 parts by weight of rubber". In the description herein, rubber and elastomer are used interchangeably.
In the description herein, the term "vulcanized" or "vulcanizable", may, on occasion, be used interchangeably with the terms "cured" and "curable".

Tire with outer carbon black reinforced rubber strip for static reduction


A device, system and method for role based data collection and public-safety incident response is provided. A computing device receives a call to report a public-safety incident. The computing device determines a role of a caller on the call, the role of the caller being relative to the public-safety incident. The computing device retrieves, from one or more memories, data dependent on the role of the caller. The computing device controls a notification device to provide the data dependent on the role of the caller.

When a caller uses a device, such as a phone, to call a public-safety answering point (PSAP, for example a 911 call center), to report an incident, it may be important to efficiently collect information from the caller in order to determine how to respond to the incident.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.
The apparatus and method components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.

Device, system and method for role based data collection and public-safety incident response


An indexable milling insert, including an upperside, an underside parallel to an imaginary reference plane, and two cutting edges. Each cutting edge includes a cutting edge line and is formed between a chip surface included in the upperside and a first clearance surface extending between the upperside and the underside, the first clearance surface forming an acute, nominal first clearance angle (α) with a normal to the reference plane. Each cutting edge includes a main edge, which is at least partly convexly curved as viewed in plane elevation from above, and which extends from an initial end, which determines the maximal cutting depth of the milling insert, to a corner edge having a radius of curvature that is smaller than the radius of curvature of the main edge, the main edge rising in the direction from the initial end toward the corner edge such that the distance thereof to the underside successively increases in the direction. A second clearance surface is formed between the cutting edge line and the first clearance surface, the second clearance surface having a width of at most 0.3 mm and a nominal second clearance angle (λ) that is smaller than the first clearance angle. The second clearance surface is of uniform width and the second clearance angle decreases successively in the direction from the initial end toward the corner edge.

Generally, milling tools and the milling inserts thereof are used for chip removing or cutting machining of workpieces of various metallic materials, such as steel, aluminum, titanium, etc., which in practice have most varying properties in respect of, for instance, workability, generation of heat, sticking, and so on. Milling inserts of the kind initially mentioned (known as "router inserts" by those skilled in the art) are especially suitable for milling in easily machined materials, such as aluminum, in which the milling inserts have great cutting capacity and generate the smoothest possible surfaces. For this reason, the milling inserts are manufactured having a positive cutting geometry so far that the cutting edge angle between the individual chip surface and the appurtenant clearance surface is acute (e.g., within the range of 65-75°), at the same time as the milling inserts are mounted with positive tipping-in angles in the appurtenant seatings in the milling cutter body as viewed axially as well as radially. In such a way, the milling inserts can "dig themselves" into the material in an efficient and powerful way, and thereby remove large amounts of chips per time unit. In order to generate smooth (usually plane, curved or cylindrical) surfaces, the main edge of the individual cutting edge has to be given a convexly curved or cambered shape as viewed in plane elevation, so that the cutting edge line of the main edge, in spite of the axially positive tipping-in of the milling inserts into the milling cutter body will follow or be tangent to an imaginary cylinder, the diameter of which is determined by the radial distance between the rotation axis of the milling cutter body and the cutting edge line of the main edge. It should also be mentioned that the milling inserts in question, by having at least two serviceable cutting edges, and thereby being indexable, get a service life that is at least twice as large as those milling inserts only having one cutting edge.
A problem with previously known, high-capacity milling inserts (see, for instance, WO/02/055245 A1 and SE 527617 C2) is, however, that the same under certain circumstances may be subjected to vibrations, which, if they become regenerative and are allowed to grow in strength in an uncontrolled way, may lead to drastic consequences, such as tool or machine breakdowns, rejections of expensive workpieces, personal risks of injury, etc. The risk of emergence of vibrations is particularly great when the milling tool is slender and operates using great cutting depths, e.g., in aluminum. As long as the cutting depths are small or moderate (up to 2 mm), initial vibration tendencies usually die out by themselves, but when the cutting depths increase, for instance to ¼ of the length of the cutting edge or more, from which it follows that also the cutting forces are enhanced, it often occurs that the vibrations are fed back and grow in an uncontrolled way. The risk of vibration is particularly marked for tools of steel, such as shank-end mills, the length of which is many times greater than the diameter (L>3×D).
The present invention aims at overcoming the above-mentioned problems and at providing an improved milling insert of the indexable type. An object of the invention to provide a milling insert manufactured from cemented carbide or another hard and wear-resistant material, which has an inherent ability to automatically damp or deaden vibrations as soon as these tend to arise. The ultimate purpose of counteracting the emergence of vibrations is to make it possible to increase the axial cutting depth and thereby the removal volume, without risking damage the tool and/or the machine by escalating vibrations.
Another object of the invention is to realize the vibration damping function by ways that are technically simple and thereby inexpensive.
Yet another object of the invention is to provide a milling insert that is particularly suitable to use in shank-end mills.


In a facet mirror with a number of mirror facets, wherein the mirror facets are provided with reflecting surfaces, the mirror facets are mounted jointly in a basic body via bearing devices. The mirror facets comprise mirror bodies contacting at the periphery with the bearing devices via a surface, line or point contact. The preferred field of use of the facet mirrors is a projection objective of a projection exposure machine in microlithography for fabricating semiconductor elements.

1. Field of the Invention
The invention relates to a facet mirror comprising a number of mirror facets, wherein the mirror facets are provided with reflecting surfaces and a bearing device in each case, to a system for adjusting the mirror facets of a facet mirror, and to the use of such a facet mirror in microlithography.
2. Description of the Related Art
Reference is made to EP 0 726 479 A2, EP 0 901 992 A1, GB 2 255 195 A, DE 23 637 65, Patent Abstract of Japan 2000 167683A, RO 101091B, U.S. Pat. No. 6,154,302 A, U.S. Pat. No. 6,227,673 B U.S. Pat. No. 1, 4,195,913 and U.S. Pat. No. 4,740,276 in relation to the prior art.
It is scarcely possible in the case of the known facet mirrors to realize the accuracies required for the mirror facets during adjustment, which are required for the preferred application of the above-named invention in an objective for semiconductor lithography, in particular for use under radiation in the extreme ultraviolet region. Moreover, during an adjustment of the mirror facets it is possible to access the individual mirror facets only from the side of their reflecting surface, and so aligning the individual mirrors under illumination is relatively complicated and difficult.

Facet mirror having a number of mirror facets


A mobile communication system includes wireless base stations, a mobile station communicating with the wireless base stations, and a radio network controller controlling the wireless base stations. The mobile communication system includes a power controller which controls a power of control bits in downlink based on the number of wireless base stations simultaneously communicating with the mobile station.

1. Field of the Invention
The present invention relates to a mobile communication system, a wireless base station, a radio network controller, and a power control method.
2. Description of the Related Art
In a mobile communication system, generally, multipath fading or the like causes instantaneous level fluctuations on a receiver side, sometimes drastically degrading reception characteristics of uplink in a wireless base station or reception characteristics of downlink in a mobile station. As a technology to reduce such degradation, in a mobile communication system using CDMA, transmission power control is individually performed for uplink and downlink.
Hereinafter, an outline of the transmission power control in uplink is shown (for example, see 3GPP, "TS25.211 V5.6.0 Physical channels and mapping of transport channels onto physical channels (FDD)" and 3GPP, "TS25.214 V5.9.0 Physical layer procedures (FDD)"). FIG. 1 shows a configuration of transmission power control loops based on SIR measurement. The transmission power control includes two loops of inner and outer loops. In the inner loop, SIR of a received signal at each slot is measured by a SIR measurement unit 17. Transmission power control (TPC) bits to control an increase and a decrease of transmission power are created in a TPC command creation unit 19 so that the measured SIR value is equal to a target SIR value. The created TPC bits are transmitted on a dedicated physical control channel DPCCH in paired link (downlink when controlling the transmission power in uplink). On the other hand, the same target SIR value does not always provide same reception quality (BLER or BER) depending on differences in the number of propagation paths, a propagation environment such as moving speed of the mobile station (maximum Doppler frequency), and the SIR measurement method. Accordingly, in a BLER measurement unit 14, the reception quality is measured through the outer loop for a longer interval, and the target SIR value is corrected in a target SIR correction value creation unit 16 in long cycles based on the measured reception quality. For example, when the outer loop control is performed based on BLER, BLER is measured based on the number of transport blocks in a data series whose calculated CRC results are correct after error correction decoding, and a correction value of the target SIR value is obtained so that this measured BLER value is equal to a required BLER value.
Herein, FIG. 2 shows a frame structure of dedicated physical channel DPCH composed of DPCCH as a downlink dedicated physical channel for notification of the transmission power control bits and DPDCH as a dedicated physical data channel. A portion indicated by "TPC" includes the aforementioned transmission power control bits. A portion indicated by "TFCI" is called a transport format combination indicator and includes information indicating a transport format combination. A portion indicated by "Pilot" includes dedicated pilot bits. The power of these three pieces of information, i.e. TPC bits, TFCI bits, and Pilot bits, is set to the value which is equal to "DPDCH power+power offset". The power-offset values are signaled through an upper layer.
When the mobile station communicates with a plurality of wireless base stations, the plurality of wireless base stations individually perform the transmission power control and send transmission control bit patterns using the downlink DPCCH. At this time, in uplink, the reception quality of at least one of the above plurality of wireless base stations should meet required quality. Accordingly, the mobile station reduces the transmission power when at least one of the transmission power control bit patterns of the downlink indicates a power reduction command to reduce power. The mobile station increases the transmission power only when all the transmission power control bit patterns indicate a power increase command to increase power.
As described above, generally, in the case of communicating with a plurality of wireless base stations, the mobile station increases the transmission power only when each of the transmission power control bit patterns from the above plurality of wireless base stations indicates the power increase command and reduces the transmission power when any one of the transmission power control bit patterns indicates the power reduction command. Herein, there are no problems when an error rate of the transmission power control bits is 0%. However, actually, the error rate of the transmission power control bits is not 0%, and errors could occur. In this case, when any one of the power increase commands is mistaken for the power reduction command, the mobile station reduces the transmission power. The transmission power of the mobile station tends to be smaller than the required transmission power as a whole. This results in degradation in the uplink reception quality in the wireless base stations.
In the light of the aforementioned problem, an object of the present invention is to provide a mobile communication system, a wireless base station, a radio network controller, and a power control method capable of reducing the error rate of the transmission power control bits and maintaining uplink reception quality of each wireless base station.

Mobile communication system, wireless base station, radio network controller, and power control method


Exemplary embodiments of the present invention relate methods and devices for measuring flow rate of particulate matter within an exhaust gas stream. In one particular exemplary embodiment, a sensor for detecting and monitoring particulate matter within an exhaust flow path of an engine is provided. The sensor includes a housing having an attachment for mounting the sensor. The sensor also includes a sensing rod supported by an insulating base. The sensing rod is attached to the housing and includes a probe adapted to be placed within the exhaust flow path. The probe includes a section having an increased surface area per unit length as compared to at least one other section of the probe. The sensing rod is configured to detect particulate matter flowing through the exhaust component and generates a signal based thereupon. The sensor further includes an electrical connector in communication with the sensing rod. The electrical connector is configured to transmit the signal generated by the sensing rod to a controller.

Emissions from stationary and mobile fossil burning devices have been and will continue to be of particular concern in view of accumulating laws and regulations restricting emissions from such devices. In one aspect, particulate matter within emission has been regulated causing industries, particularly the automotive industry, to utilize particulate matter removal devices. Such removal devices are configured to catch or trap particulate matter flowing through an exhaust gas stream prior to exiting an exhaust system of the emission generating device.
In another aspect, filters are used for removal of such particulate matter from exhaust gas streams, such as those generated by diesel engines, gasoline engines or otherwise. To determine when the particulate matter filter is reaching its capacity, the total volume or volume flow rate of particulate matter flowing into the filter or within the exhaust gas stream is monitored. This monitoring is often achieved through a particulate matter sensor exposed to the exhaust gas flow. In this configuration, the particulate matter sensor includes a probe extending into the exhaust gas flow. Some exhaust gas sensors function by transmitting signals based upon a resistance across the probe of the sensor for example, as particulate matter builds up across the sensor, the resistance changes thereby varying the output of the probe and accordingly providing an indication of the amount of particulate matter that has traveled past the sensor and into the filter.
However, many of these sensors fail to provide accurate readings of particulate matter flowing past the sensor or within an exhaust gas stream. For example, many of these sensors are not sufficiently robust to withstand forces or temperatures encountered by such sensors. Other problems with these sensors are their inability to accurately indicate the presence of particulate matter within an exhaust gas flow due to poor signal noise ratio and accumulation of particles on the sensor and other similar deficiencies. Still other problems exist as well.
Accordingly, in view of the shortcomings of previous sensor designs, as described above, there is a need for improved methods and devices for monitoring the flow of particulate matter flowing within and exhaust gas stream.


In accordance with the present invention, a liner for a hat, cap or similar head covering comprises a layer of moisture absorbent material which is backed by a layer of moisture impervious material. Further, adhesive means are provided for releasably securing the liner to the sweatband of the hat, cap or similar headgear. The bottom and side edges of the moisture absorbing layer are sealed to prevent the migration of moisture, oil, grease and other contaminants through these edges of the liner. The upper edge of the liner is left unsealed so that a wicking action encourages the transport of moisture from the body of the moisture absorbing layer to the top edge where it may be evaporated.

This invention relates to protective liners for the inside sweatband area of helmets, hats, caps and similar headgear and more particularly to a protective liner which is disposable.
Hats, caps and similar headgear are commonly provided with sweatbands lining the lower inside portion of the headgear in order to prevent the head of the user from directly contacting the material of the hat or cap. Such sweatbands are rarely completely effective in preventing moisture from migrating into the material of the hat or cap itself. Such headgear, unless constructed of moisture impervious materials such as solid plastic as would be true of a protective helmet, are likely to become rapidly stained by sweat, oil, grease and dirt and thus rendered unattractive. A stained hat or cap may thus be discarded well before the end of its useful lifetime. It is, therefore, desirable to have additional means for protecting a hat or cap from the migration of moisture and other contaminants through the sweatband into the material of the hat or cap.
It is known in the prior art to provide a disposable liner to be placed on or behind the sweatband to provide an additional barrier to the migration of moisture and contaminants into the material of the hat or cap.
U.S. Pat. No. 5,025,504 issued to Benston, et al. on Jun. 25, 1991 for "Liner For A Helmet, Hat, Cap Or Other Head Covering" discloses a liner for head coverings having a body with a central section and tapered end sections. The body includes liquid absorbing material and is releasably secured to the head covering. The liners of Benston are formed with a core of fibers, including thermoplastic fibers, sandwiched between facing and backing sheets. The sections of the liner allow the liner to be cut in transverse segments to adjust its length.
U.S. Pat. No. 3,578,736 issued to Dootson on May 18, 1971 for "Hat And Sweatband Insert Therefor" discloses a sweatband insert having a moisture absorbent face portion and a moisture impervious back portion with an upstanding central member. The central member provides a grasping portion for easy insertion of the insert behind the sweatband and also exposes a portion of the liner to facilitate the evaporation of moisture from the liner.
Similar disposable inserts or liners are disclosed in U.S. Pat. No. 2,445,209 and U.S. Pat. No. 1,957,356.
Although these and other examples are known in the prior art of disposable liners for head coverings, the need exists for an improved form of disposable liner which further facilitates the protective function of the liner by encouraging the transportation of contaminant containing moisture away from the hat or cap and which further embodies ease of manufacture and use.


A starting circuit of a starting device for a high-pressure discharge lamp including an auxiliary light source has a diode placed in a forward direction in one of a pair of output lines which connect a main lighting circuit for generating AC voltage to the high-pressure discharge lamp and the auxiliary light source; a capacitor having one end connected to a cathode side of the diode; a boosting transformer including a primary winding, and a secondary winding having one end connected to an anode side of the diode or to the other output line and also having the other end connected to the other end of the capacitor; a high-frequency voltage generation circuit for continuously generating high-frequency voltage in combination with the primary winding; and a short-circuit switch for maintaining a short-circuit condition at both ends of the diode after the high-pressure discharge lamp is started.

1. Field of the Invention
The present invention relates to a starting circuit of a starting device for a high-pressure discharge lamp including an auxiliary light source, the starting circuit being capable of reliably starting the high-pressure discharge lamp including the auxiliary light source.
2. Description of the Related Art
A high-pressure discharge lamp is mainly provided for a lighting system which is used for a liquid crystal projector and an optical device such as an exposure device. In recent years, an auxiliary light source is arranged in a high-pressure discharge lamp in response to demand for reduction in initial start (cold start) time as well as in restart (hot start) time and in response to demand for lowering the voltage required for starting (e.g., Patent document 1: Japanese Laid-Open Patent Publication No. 2003-203605).
As shown in FIG. 9, an auxiliary light source 3 arranged in a lighting system 1 described in Patent document 1 includes a discharge chamber 7 having discharge space 7a enclosing therein material M2 which emits ultraviolet rays when excited by discharge, and a starting electrode 8 that is arranged so as to be opposite via the discharge chamber 7 to one of metal foils 6b which is embedded in one of sealing portions 5b of a high-pressure discharge lamp 2. A conductive wire 9 is electrically connected to the starting electrode 8 so as to apply high-frequency high voltage between the one of the metal foils 6b and the starting electrode 8. Such a configuration that has electrodes arranged outside the discharge space 7a is called "electrodeless type".
In order to start the high-pressure discharge lamp 2 of the lighting system 1, high-frequency high voltage is applied between the one of the metal foils 6b and the starting electrode 8. Dielectric barrier discharge is then generated between the one of the metal foils 6b and the starting electrode 8 via the discharge space 7a of the discharge chamber 7. The material M2 enclosed in the discharge space 7a is excited by the dielectric barrier discharge, thereby emitting ultraviolet rays UV. The ultraviolet rays UV irradiate light-emitting material M1 enclosed in a light-emitting portion 5a in the high-pressure discharge lamp 2, whereby the light-emitting material M1 is ionized. Consequently, discharge between main discharge electrodes 6a is accelerated, whereby the high-pressure discharge lamp 2 is started by applying lower voltage.
In order to start the auxiliary light source of the above-described "electrodeless type", high-frequency high voltage needs to be applied to the auxiliary light source so as to produce capacitive coupling and then to cause excitation. Accordingly, various types of starting devices for the high-pressure discharge lamp, which are capable of generating high-frequency high voltage, have been developed (e.g., Patent document 2: Japanese Laid-Open Patent Publication No. 2007-109510).
In a starting device 100 for a high-pressure discharge lamp disclosed in Patent document 2, as shown in FIG. 10, a voltage generation circuit 104 and an inverter 106 are connected to a high-pressure discharge lamp 102 via an output line 108 and the other output line 110 so as to supply stabilized electric power to the high-pressure discharge lamp 102. The output line 108 is connected to a secondary winding 114 of a transformer 112. A primary winding 116 of the transformer 112 and a capacitor 118 are connected in parallel with each other to constitute a parallel resonant circuit. Voltage having predetermined frequency is applied from periodical voltage applying means 120 to the primary winding 116 and the capacitor 118. That is, a starting circuit 122 for the high-pressure discharge lamp 102 is composed of the transformer 112, the capacitor 118, and the periodical voltage applying means 120.
To start the high-pressure discharge lamp 102, periodical voltage is applied from the periodical voltage applying means 120 to the primary winding 116 and the capacitor 118 (i.e., the parallel resonant circuit). When frequency of the voltage applied from the periodical voltage applying means 120 corresponds to fundamental resonant frequency or high-order resonant frequency of the parallel resonant circuit, resonant current flows through the parallel resonant circuit, and high voltage is generated in the primary winding 116. With the high voltage generated in the primary winding 116, higher voltage is generated in the secondary winding 114, the higher voltage being boosted in accordance with a turns ratio (a ratio of the number of turns of wire in the primary winding 116 to the number of turns of wire in the secondary winding 114).
The higher voltage generated in the secondary winding 114 is superimposed with output voltage from the voltage generation circuit 104 and the inverter 106, and the resultant voltage is applied to the high-pressure discharge lamp 102, whereby high-frequency high voltage can be applied to the high-pressure discharge lamp 102.
However, the starting device 100 for the high-pressure discharge lamp disclosed in Patent document 2 has the following problems. That is, in the starting device 100 for the high-pressure discharge lamp, the secondary winding 114 of the transformer 112 is placed in the output line 108, and high rated current is fed to the high-pressure discharge lamp 102 through the secondary winding 114 when light is emitted steadily. Therefore, there has been required a large-size, expensive transformer 112 which includes a secondary winding 114 capable of accommodating high rated current. As a result, the starting device 100 for the high-pressure discharge lamp needs to be upsized and thus becomes expensive.

Starting circuit of starting device for high-pressure discharge lamp including auxiliary light source, starting device including the starting circuit, and lighting system including the starting device


A motor module includes: a motor; a driving unit; a control unit; a communication unit that performs communication via a network in the vehicle; and a connection unit to which an operation module is connected without going through the network. The control unit determines identification information of a vehicle-mounted device based on a voltage applied according to a connection state between the motor module and the operation module, controls the driving unit based on control information with information which coincides with the identification information transmitted from a management module that manages the motor module and received by the communication unit, and controls the driving unit to operate the vehicle-mounted device based on an operation signal input from the operation module according to an operation state of the operation module via the connection unit.

In order to operate a vehicle-mounted device mounted on a vehicle such as an automobile, a motor module as disclosed in, for example, WO-A1-2010/110112 is used. This motor module is integrated with a motor, which is a power source for the vehicle-mounted device, a mechanism of decelerating a rotation of a rotary shaft of the motor, a sensor of detecting a rotation speed of the motor, a driving unit of driving the motor, a control unit of operating the driving unit to control the drive of the motor, and the like.
In addition to the above configuration, there is also a motor module integrated with a memory that stores information for operating the vehicle-mounted device, and a communication unit that communicates with another module or apparatus via a network such as LAN or CAN built in the vehicle. For example, JP-A-2015-020647 and JP-A-2015-020648 disclose a vehicle-mounted device control system including such a motor module (a slave device) and a management module (a master device) that manages the motor module. The management module is configured with an electronic control unit (ECU) including a control unit having a CPU or the like, a memory, a communication unit that performs communication via a network of a vehicle, and the like, or a module having other functions.
In order for the motor module to control an operation of the vehicle-mounted device and for the management module to control the motor module, it is necessary to perform initial settings. Therefore, in JP-A-2015-020647 and JP-A-2015-020648, identification information of the slave device and a driver (software) for the master device to control the slave device are stored in a memory of the slave device in advance. The slave device transmits the identification information and the driver stored in the memory of the slave device to the master device via the network. When the master device receives the identification information and the driver from the slave device, the master device associates the identification information and the driver, and stores the identification information and the driver in the memory. After that, the master device transmits a control command according to a condition indicated by the driver to the slave device together with identification information. The slave device receives the control command, controls an operation of a main body unit such as a motor based on the control command, and operates the vehicle-mounted device.
On the other hand, JP-A-2006-256547 and JP-A-2013-192012 disclose a technology in which a slave device determines identification information of the slave device based on a voltage applied from a master device or another slave device. Specifically, a resistance circuit provided in a plurality of slave devices is connected in series to an electric wire connected to a voltage supply unit provided in the master device, and a voltage is applied to the electric wire from the voltage supply unit. Then, the slave device determines the identification information of the slave device, based on a voltage division value of a resistance circuit of the slave device.
Further, JP-A-2017-133876 discloses a technology of identifying a slave device based on an open-circuited and short-circuited state of an identification terminal of a master device (main unit) to which the slave device (module) is directly connected. Specifically, by connecting any two of the three identification terminals respectively provided in a plurality of connectors provided on the master device and two connection terminals provided on the slave device, the open-circuited and short-circuited state between the identification terminals is changed. The master device determines a connector to which the slave device is connected, a type of the slave device corresponding to the connector, or a CAN ID, based on the open-circuited and short-circuited state between the identification terminals.

Motor module, management module, vehicle-mounted device control system


A method of quantum efficiency (QE) photovoltaic measurement is provided that includes coupling measurement electronics to a p-n junction of a Cell Under Test (CUT) that are capable of measuring a pulsed DC photocurrent. The measurement electronics output a response by the CUT to turning on and turning off the pulsed DC photocurrent that are digitized and analyzed for the magnitude that is representative of a conversion efficiency of the CUT to a wavelength of the DC photocurrent, where a measured decay time represents the p-n junction or the minority carrier lifetime. The CUT is exposed to the pulsed DC photocurrent, where signatures of the response to turning off and on to the pulsed DC photocurrent overlap, where a combined amplitude of the response is proportional to an efficiency of a production of photocarriers, where a value of a spectral response at a wavelength is determined.

Methods and systems for measurement of the Quantum Efficiency (QE) and Current Voltage Characteristic (IV or JV) of photovoltaic devices have been available for decades. The methods employ the use of a light source producing a broad spectrum followed by either a monochromator or filter wheel to generate a set of wavelengths used to probe the desired spectral response of the photovoltaic Cell Under Test (CUT). These methods are hereafter referred to as the "traditional method".
Recently, fast methods for measuring the QE of a cell have been developed and made commercially available. However, these methods require electrical contact to the cell and cannot be applied directly to PV strings or modules, or to partially completed cells.
What is needed is a contact-free QE measurement method that can be applied directly to PV strings or modules, or to partially completed cells.

Methods and systems for characterizing photovoltaic cell and module performance at various stages in the manufacturing process


The invention provides a method of calculating uncertainty in the system represented as two or more modules comprising the steps of passing uncertainty information from each module to at least one further module; and calculating uncertainty in the measurement result from the information exchanged between the modules. The invention also provides a method of propagating uncertainty in a measurement system and also provides related systems for calculating uncertainty and propagating uncertainty.

There are currently many ways to improve the design and performance of measurement systems, and systems components. Such improvements may lead to increased system reliability and flexibility, lower costs of installation and ongoing ownership, easier maintenance, repair and upgrading.
It is generally accepted that measurement results must be qualified with statements of uncertainty. In fact, the correct calculation and reporting of uncertainties is needed to achieve traceability of measurement results. Such calculation and reporting is an issue for national metrology institutes as well as for accredited calibration laboratories. Correct manipulation of uncertainties may also be a requirement for ISO 9000 certification of some organisations.
It would be particularly desirable for measurement systems to be able to determine the uncertainty in any measurement result automatically by using data from the uncertainties associated with individual sub-systems and transducers.

Uncertainty propagation system and method


A fixing device includes a fixing member of which surface is deformable, a heating unit that heats the fixing member, a pressurizing unit having an endless member and a pressurizing member. The pressurizing member includes an elastic layer and presses the endless member against the fixing member to bring the endless member into pressure contact with the fixing member. The elastic layer has an apparent hardness (ASKER-C) which is larger than that at a point where an apparent hardness starts to change rapidly with respect to a rubber thickness in a load application direction.

1. Field of the Invention
The present invention relates to a fixing device of an image forming apparatus. More particularly, the present invention relates to a fixing device that includes an endless member that is brought into pressure contact with a fixing member.
2. Description of the Related Art
A heat fixing device is used in an image forming apparatus such as a copier, a printer, or a facsimile. A typical heat fixing device fixes an unfixed toner image onto a paper sheet by use of heat and pressure. For example, Japanese Patent No. 3298354 discloses a conventional heat fixing device that employs a belt-nip system. In such a belt-nip system, a fixing member, such as a fixing roller, is brought into pressure contact with an endless pressure-contact member, such as an endless belt, to form a nip portion between the fixing member and the endless pressure-contact member. A paper sheet with an unfixed toner image thereon is passed through the nip portion. As a result, the paper sheet is heated and pressurized, so that the unfixed toner image is fixed onto the paper sheet.
The conventional heat-fixing device includes a heating-fixing roller having an elastically deformable surface that is subjected to local elastic deformation at the exit (nip exit) of a nip portion. Such local deformation at the nip exit, however, leads to variations in the surface speed of the heating-fixing roller (see FIG. 4 of Japanese Patent No. 3298354). The variations in the surface speed of the heating-fixing roller leads to shifting of writing position of an image, which in turn leads to degradation in image quality.
In addition, a hard member is pressed against an elastic layer of the heating-fixing roller to locally cause deformation of the elastic layer, so that a nip portion having a small curvature is formed. This configuration, however, imposes a large load on the paper sheet, which disadvantageously leads to damage to the recoding medium and/or curling of the recoding medium.

Fixing device and image forming apparatus