A simple method is developed for detection of fast neutrons for systems of detection of radioactive materials, which does not involve moderator systems, operates on the real time scale and ensures high detection efficiency. The method includes conversion of the cascade of gamma-quanta formed as a result of inelastic scattering of neutrons in a converter material with high atomic number into a set of light scintillations by a scintillator, processing of signals obtained in recording of said scintillations, formation of counting pulses with frequency proportional to the neutron flux and their recording according to an appropriate algorithm. Inorganic scintillators with high effective atomic number are used, and, as converter materials for inelastic scattering of neutrons, materials with high atomic numbers are used, which are a constituent part of said inorganic scintillators. Processing of the obtained signals is carried out by their integration with time constant of at least 30 microseconds, and formation of counting pulses is made by selection of the integrated signals in the energy range equivalent to 10-300 keV. Examples of inorganic scintillators comprising material with high effective atomic number used as the converter are crystals BGO, GSO, ZnWO, CWO, CsI(Tl), NaI(Tl), and LiI(Eu).

The invention is related to the field of detection of radioactive contamination sources and the presence of radioactive materials in moving objects, and is designed for complexes and systems of radiation monitoring used in dosimetric customs and security services related to tasks of nuclear safety and State Atom Inspection.
For detection of fast neutrons, the technologies generally used are organic hydrogen-containing materials based on plastics (CH), or stilbene [Patent of Russian Federation No. 2088952, G01T 1/20], or helium counters [V. I. Ivanov, Course of Dosimetry, Moscow: Energoatomizdat, 1988, p. 399]. For detection of thermal neutrons, scintillation crystal 6Li(Eu) containing 6Li is used [Yu. K. Akimov, Scintillation methods for detection of high energy particles, Moscow: Ed. Moscow State University, 1963]. This scintillator, however, has low detection efficiency of fast neutrons and is also highly hygroscopic, which hinders its broad application.
The detection efficiency with these materials does not exceed 1-10%.
A method for detection of fast neutrons is known [Patent of Russian Federation No. 2129289, G01T 1/167], based on the mechanism of elastic scattering of fast neutrons in a hydrogen-containing material with subsequent recording of "thermal" neutrons by 3He-based counters. Signals obtained in the counters are amplified to the required level, and counter pulses are formed with frequency proportional to the neutron flux, with subsequent detection of neutrons using appropriate algorithms.
The efficiency of methods using the elastic scattering mechanism does not exceed 10%, and for reliable detection of weak fluxes of fast neutrons, detector panels of large volume, area, and weight are to be used. Thus, neutron detectors based on 3He-counters used in the "Yantar" system produced by "ASPEKT" involves 8 tubes filled with 3He, with dimensions Ø30×900 mm, placed in a polyethylene moderator. The efficiency of fast neutron detection using this method is 8%. The sensitivity of the detector panel of 120×100×1000 mm dimensions is 350 pulses-cm2/neutron·s, and weight is 130 kg.
Another known method of fast neutron detection [Data sheet of NUCSAFE ins. Last modified, Oct. 29, 2007] is based on elastic scattering of fast neutrons in hydrogen-containing material with subsequent recording of "thermal" and "slow" neutrons by a scintillating glass fiber placed in a hydrogen-containing material. Signals recorded in the scintillating glass fiber are amplified to the required level, counting pulses are shaped with frequency proportional to the neutron flux, and neutrons are detected according to the appropriate algorithm.
However, as in the first method, ensuring high sensitivity to fast neutrons requires the use of moderators made of hydrogen-containing material. Because the scintillation glass fiber has low sensitivity to fast neutrons, obtaining the desired sensitivity requires the use of detector panels of large volume, area and, consequently, weight. The efficiency of fast neutron detection by this method also does not exceed 8%. The sensitivity of a detector panel of 1000 to 6000 cm2 area is ˜300 pulses-cm2/neutron·s.
Still another known method of fast neutron detection [M. Anelli., G. Battistoni, C. Bini, et. al., Measurement and simulation of the neutron response and detection efficiency of a Pb-scintillating fiber calorimeter, Nuclear Instruments and Methods in Physics Research A 581 (2007) 368-372] is based on inelastic scattering of fast neutrons in lead, which is used as a converter. 200 layers of lead foil of 0.5 mm thickness are used, in the grooves of which fiber organic scintillators are placed, and signals are recorded that result from interaction of organic fiber scintillators with cascades of gamma-quanta formed due to inelastic scattering of neutrons in the lead foil (converter). Then their full analysis is carried out with subsequent conversion of the obtained information into a digital code using 40+40 blocks of analog-to-digital converters. The obtained data array is written onto a digital carrier and is processed using powerful computers. Then counting pulses are formed with frequency proportional to the neutron flux, counting rate is calculated depending on the neutron flux, and neutrons are recorded according to the appropriate algorithm.
However, this method of fast neutron detection is rather complex and labor-consuming, because it requires full analysis of all signals emerging from the interaction of fast neutrons with the converter (the presence of which increases the detector size), preliminary recording of intermediary data onto the information carrier and subsequent data processing using powerful computers. This makes this method not suitable for its use in radioactive materials detection systems operating on the real time scale.
The last of these analogs has been chosen as a prototype.

Institute of Scintillation Materials, National Academy of Sciences of Ukraine


An automotive discharge bulb having a light emitting tube includes a ceramic tube with paired electrodes oppositely placed, and contains a light emitting material and starting rare gas. A transversal section of the ceramic tube is longitudinally elongated. In the ceramic tube having a longitudinally elongated transversal section, an arc generated into an upwardly convex shape and the tube wall do not make contact.

1. Field of the Invention
The present invention relates to an automotive discharge bulb having a light emitting tube that includes a ceramic tube in which electrodes are oppositely placed. The light emitting tube is filled with a light emitting material and a starting rare gas. The present invention further relates to an automotive headlamp having the discharge bulb.
2. Description of the Related Art
Generally, a discharge bulb having a glass arc tube is used as a light source for an automotive headlamp. However, the related art discharge bulb has encountered problems. For example, but not by way of limitation, metal halide filled in the light emitting tube promotes corrosion of the light emitting tube (or glass tube). Further, blackening and devitrification phenomena occur. Thus, no appropriate light distribution is obtained, and the life of the discharge bulb is not very long.
Recently, there has been proposed a related art discharge bulb (see FIG. 18) having a light emitting tube 110 that includes a right-circular-cylindrical ceramic tube 120, of which both ends are sealed with cylindrical insulating elements 130, and in which electrodes 140, 140 are oppositely placed, and that is filled with a light emitting material together with a starting rare gas, as described in JP-A-2001-76677 (see Paragraph No. 0005 of the specification and FIG. 5 thereof). The ceramic tube 120 is stable against metal halide, and has a long life, as compared with the glass arc tube.
Naturally, the discharge bulb for use in an automotive headlamp is required to have a good rising characteristic of luminous flux to obtain predetermined luminous flux immediately after the lamp is turned on. This is the same with the discharge bulb having a light emitting tube constituted by a right-circular-cylindrical ceramic tube, which is described in JP '677. This discharge bulb is required to have the ceramic tube, whose diameter is relatively small (whose enclosed space has small capacity), so as to improve the rising characteristic of luminous flux.
However, an arc generated by discharge between the electrodes has an upwardly convex shape. Therefore, as the diameter of the ceramic tube is decreased, the central part of high temperature arc is brought into substantial contact with a tube wall. Thus, the ceramic tube is required to have higher thermal shock resistance. Consequently, very limited ceramic materials are available as the material of the ceramic tube of the light emitting tube.
The related discharge bulb has another problem that when the central part of the high-temperature arc is put into large contact with the tube wall, an amount of heat radiated from the tube wall increases, and this increase in the amount of radiated heat delays the rise in luminous flux. Thus, the rising characteristic of luminous flux is degraded.

Automotive discharge bulb and automotive headlamp


An electro-pneumatic actuator for a waste gate includes an electric actuator to impart linear motion to an actuator shaft, and a pneumatic chamber defining a passage extending therethrough, the actuator shaft extending through the passage, the pneumatic chamber being sealed with respect to the actuator shaft. A piston is disposed in the pneumatic chamber and arranged for movement in the pneumatic chamber, the piston being affixed to the actuator shaft such that the actuator shaft and the piston move together as a unit. There is a port into the pneumatic chamber for feeding a gas into the pneumatic chamber or exhausting the gas therefrom so as to exert a pressure force on the piston and thereby provide a pneumatic assist to the force exerted on the actuator shaft.

The present disclosure relates generally to exhaust gas-driven turbochargers having a waste gate for bypassing exhaust gas around the turbine during certain operating conditions. The disclosure relates in particular to an electro-pneumatic actuator for effecting movement of the waste gate.
Recent increases in gasoline turbocharger performance requirements and stricter emission regulations have driven the need for waste gate actuation to move from pneumatic systems to electric systems for increased controllability, faster response time, and potentially reduced overall system costs. The difficulties associated with electric actuation are, among others, the need to over-size the electric motor because the motor is required to operate in a stall condition for extended periods of time in order to maintain the waste gate in a closed position against high loads. Typically in a continuous stall condition, an electric motor, because of internal heating of the motor coils, can provide less than half of its peak force. This means that there must be a significant over-sizing of the motor to ensure it has sufficient force in the stall condition, which results in large package size, increased weight, and unnecessary force surplus during more-favorable operating conditions.

Electro-pneumatic actuator for a turbocharger waste gate, and a turbocharger and a method employing same


A method of handling load-and-reserve instructions in a multi-processor computer system wherein the processing units have multi-level caches. Symmetric multi-processor (SMP) computers use cache coherency to ensure the same values for a given memory address are provided to all processors in the system. Load-and-reserve instructions used, for example, in quick read-and-write operations, can become unnecessarily complicated. The present invention provides a method of accessing values in the computer's memory by loading the value from the memory device into all of said caches, and sending a reserve bus operation from a higher-level cache to the next lower-level cache only when the value is to be cast out of the higher cache, and thereafter casting out the value from the higher cache after sending the reserve bus operation. This procedure is preferably used for all caches in a multi-level cache architecture, i.e., when the value is to be cast out of any given cache, a reserve bus operation is sent from the given cache to the next lower-level cache (i.e., the adjacent cache which lies closer to the bus), but the reserve bus operation is not sent to all lower caches. Any attempt by any other processing unit in the computer system to write to an address of the memory device which is associated with the value will then be forwarded to all higher-level caches. The marking of the block as reserved is removed in response to any such attempt to write to the address.

1. Field of the Invention
The present invention generally relates to computer systems and more particularly to a method of handling instructions for operating a cache used by a computer processor.
2. Description of the Related Art
The basic structure of a conventional multi-processor computer system 10 is shown in FIG. 1. Computer system 10 has several processing units 12a, 12b, and 12c which are connected to various peripheral devices, including input/output (I/O) devices 14 (such as a display monitor, keyboard, and permanent storage device), memory device 16 (such as dynamic random access memory or DRAM) that is used by the processing units to carry out program instructions, and firmware 18 whose primary purpose is to seek out and load an operating system from one of the peripherals (usually the permanent memory device) whenever the computer is first turned on. Processing units 12a-12c communicate with the peripheral devices by various means, including a bus 20. Computer system 10 may have many additional components which are not shown, such as serial and parallel ports for connection to, e.g., modems or printers. Those skilled in the art will further appreciate that there are other components that might be used in conjunction with those shown in the block diagram of FIG. 1; for example, a display adapter might be used to control a video display monitor, a memory controller can be used to access memory 16, etc. The computer can also have more than three processing units.
In a symmetric multi-processor (SMP) computer, all of the processing units 12a-12c are generally identical; that is, they all use a common set or subset of instructions and protocols to operate and generally have the same architecture. A typical architecture is shown in FIG. 2. A processing unit 12 includes a processor 22 having a plurality of registers and execution units, which carry out program instructions in order to operate the computer. The processor can also have caches, such as an instruction cache 24 and a data cache 26. These caches are referred to as "on-board" when they are integrally packaged with the processor's registers and execution units. Caches are commonly used to temporarily store values that might be repeatedly accessed by a processor, in order to speed up processing by avoiding the longer step of loading the values from memory 16.
Processing unit 12 can include additional caches, such as cache 28. Cache 28 is referred to as a level 2 (L2) cache since it supports the on-board (level 1) caches 24 and 26. In other words, cache 28 acts as an intermediary between memory 16 and the on-board caches, and can store a much larger amount of information (instructions and data) than the on-board caches can, but at a longer access penalty. For example, cache 28 may be a chip having a storage capacity of 256 or 512 kilobytes, while the processor 12 may be an IBM PowerPC.TM. 604-series processor having on-board caches with 64 kilobytes of total storage. Cache 28 is connected to bus 20, and all loading of information from memory 16 into processor 12 must come through cache 28. Although FIG. 2 depicts only a two-level cache hierarchy, multi-level cache hierarchies can be provided where there are many levels of serially connected caches.
In an SMP computer, it is important to provide a coherent memory system, that is, to cause writes to each individual memory location to be serialized in some order for all processors. For example, assume a location in memory is modified by a sequence of writes to take on the values 1, 2, 3, 4. In a cache-coherent system, all processors will observe the writes to a given location to take place in the order shown. However, it is possible for a processing element to miss a write to the memory location. A given processing element reading the memory location could see the sequence 1, 3, 4, missing the update to the value 2. A system that implements these properties is said to be "coherent." It is important to note that virtually all coherency protocols operate only to the granularity of the size of a cache block. That is to say, the coherency protocol controls the movement of and write permissions for data on a cache block basis and not separately for each individual memory location.
There are a number of protocols and techniques for achieving cache coherence that are known to those skilled in the art. At the heart of all these mechanisms for maintaining coherency is the requirement that the protocols allow only one processor to have a "permission" that allows a write to a given memory location (cache block) at any given point in time. As a consequence of this requirement, whenever a processing element attempts to write to a memory location, it must first inform all other processing elements of its desire to write the location and receive permission from all other processing elements to carry out the write. The key issue is that all other processors in the system must be informed of the write by the initiating processor before the write occurs.
To further illustrate how cache coherence is implemented in multi-level hierarchies, consider FIG. 4. FIG. 4 shows an SMP computer system with three processing units (40, 41, 42) consisting of processors (40a, 41a, 42a) each having an L1 cache (40b, 41b, 42b), an L2 cache (40c, 41c, 42c), and finally, an L3 cache (40d, 41d, 42d). In this hierarchy, each lower-level cache (i.e., an L3 cache is "lower" than an L2) is typically larger in size and has a longer access time than the next higher-level cache. Furthermore, it is common, although not absolutely required, that the lower-level caches contain copies of all blocks present in the higher-level caches. For example, if a block is present in the L2 cache of a given processing unit, that implies the L3 cache for that processing unit also has a (potentially stale) copy of the block. Furthermore, if a block is present in the Li cache of a given processing unit, it is also present in the L2 and L3 caches of that processing unit. This property is known as inclusion and is well-known to those skilled in the art. Henceforth, it is assumed that the principle of inclusion applies to the caches related to the present invention.
To implement cache coherency in a system such as is shown in FIG. 4, the processors communicate over a common generalized interconnect (43). The processors pass messages over the interconnect indicating their desire to read or write memory locations. When an operation is placed on the interconnect, all of the other processors "snoop" this operation and decide if the state of their caches can allow the requested operation to proceed and, if so, under what conditions.
This communication is necessary because, in systems with caches, the most recent valid copy of a given block of memory may have moved from the system memory 44 to one or more of the caches in the system. If a processor (say 40a) attempts to access a memory location not present within its cache hierarchy (40b, 40c, and 40d), the correct version of the block, which contains the actual value for the memory location, may either be in the system memory 44 or in one of more of the caches in processing units 41 and 42. If the correct version is in one or more of the other caches in the system, it is necessary to obtain the correct value from the cache(s) in the system instead of system memory.
For example, consider a processor, say 40a, attempting to read a location in memory. It first polls its own L1 cache (40b). If the block is not present in the L1 cache (40b), the request is forwarded to the L2 cache (40c). If the block is not present in the L2 cache, the request is forwarded on to the L3 cache (40d). If the block is not present in the L3 cache (40d), the request is then presented on the generalized interconnect (43) to be serviced. Once an operation has been placed on the generalized interconnect, all other processing units "snoop" the operation and determine if the block is present in their caches. If a given processing unit, say 42, has the block of data requested by processing unit 40 in its L1 cache (42a), and that data is modified, by the principle of inclusion, the L2 cache (42c) and the L3 cache (42d) also have copies of the block (however, their copies are stale, since the copy in the processor's cache is modified). Therefore, when the L3 cache (42d) of processing unit 42 snoops the read operation, it will determine that the block requested is present and modified in a higher-level cache. When this occurs, the L3 cache 42c places a message on the generalized interconnect informing processing unit 40 that it must "retry" it's operation again at a later time, because the actual value of the memory location is in the L1 cache at the top of the memory hierarchy and must be retrieved to make it available to service the read request of processing unit 40.
Once the request from processing unit 40 has been retried, the L3 cache (42d) begins a process to retrieve the modified data from the L1 cache and make it available at the L3 cache 42d, main memory 44, or both, depending on the exact details of the implementation which are not specifically relevant to this invention. To retrieve the block from the higher-level caches, the L3 cache (42d) sends messages through the inter-cache connections (42x, 42y) to the higher-level caches (42c, 42d) requesting the block be retrieved. These messages propagate up the processing unit hierarchy until they reach the L1 cache and cause the block to be moved down the hierarchy to the lowest level (the L3 cache or main memory) to be able to service the request from processing unit 40.
Processing unit 40 specifically its L3 cache 40d) eventually represents the read request on the generalized interconnect. At this point, however, the modified data has been retrieved from the L1 cache of processing unit 42 and the read request from processor 40a will be satisfied. The scenario just described is commonly referred to as a "snoop push." A read request is snooped on the generalized interconnect which causes processing unit 42 to "push" the block to the bottom of the hierarchy to satisfy the read request made by processing unit 40.
The key point to note is that, when a processor wishes to read or write a block, it must communicate that desire with the other processing units in the system in order to maintain cache coherence. To achieve this, the cache-coherence protocol associates with each block in each level of the cache hierarchy, a status indicator indicating the current "state" of the block. The state information is used to allow certain optimizations in the coherency protocol that reduce message traffic on the generalized interconnect (43) and the inter-cache connections (40x, 40y, 41x, 41y, 42x, 42y). As one example of this mechanism, when a processing unit executes a read, it receives a message indicating whether or not the read must be retired later. If the read operation is not retried, the message usually also includes information allowing the processing unit to determine if any other processing unit also has a still active copy of the block (this is accomplished by having the other lowest-level caches give a "shared" or "not shared" indication for any read they do not retry). Therefore, a processing unit can determine whether any other processor in the system has a copy of the block. If no other processing unit has an active copy of the block, the reading processing unit marks the state of the block as "exclusive." If a block is marked exclusive it is permissible to allow the processing unit to later write the block without first communicating with other processing units in the system because no other processing unit has a copy of the block. Therefore, in general, it is possible for a processor to read or write a location without first communicating this intention onto the interconnection. However, this only occurs in cases where the coherency protocol has insured that no other processor has an interest in the block. Several details of the exact workings of a multi-level cache coherence protocol have been omitted in this discussion to simplify it. However, the essential aspects that bear on the invention have been described. Those aspects not described are well-known to those skilled in the art.
Another aspect of multi-level cache structures relevant to the invention, are the operations known as evictions. The blocks in any cache are divided into groups of blocks called "sets." A set is the collection of blocks that a given memory block can reside in. For any given memory block, there is a unique set in the cache that the block can be mapped into, according to preset mapping functions. The number of blocks in a set is referred to as the associativity of the cache (e.g., 2-way set associative means that, for any given memory block, there are two blocks in the cache that the memory block can be mapped into). However, several different blocks in main memory can be mapped to any given set.
When all of the blocks in a set for a given cache are full and that cache receives a request, be it a read or write, to a memory location that maps into the full set, the cache must "evict" one of the blocks currently in the set. The cache chooses a block by one of a number of means known to those skilled in the art (least recently used (LRU), random, pseudo-LRU, etc.) to be evicted. If the data in the chosen block is modified, that data is written to the next lowest level in the memory hierarchy which may be another cache (in the case of the L1 or L2 cache) or main memory (in the case of an L3 cache). Note that, by the principle of inclusion, the lower level of the hierarchy will already have a block available to hold the written modified data. However, if the data in the chosen block is not modified, the block is simply abandoned and not written to the next lowest level in the hierarchy. This process of removing a block from one level of the hierarchy is known as an "eviction." At the end of this process, the cache no longer holds a copy of the evicted block and no longer actively participates in the coherency protocol for the evicted block because, when the cache snoops an operation (either on the generalized interconnect 43 or the inter-cache connections 40x, 41x, 42x, 40y, 41y, 42y) the block will not be found in the cache.
Another aspect of symmetric multiprocessors is relevant to the invention. In symmetric multiprocessors, it is necessary to provide a means of synchronizing the actions of the various processors in a system to allow cooperation among processors working on a task. To achieve this, most modern processors include in their instruction sets explicit instructions to handle synchronization. In particular, the PowerPC.TM. instruction set provides two instructions known as "lwrx" and "stcx." These instructions come in two forms: "lwarx" and "stwcx" for 32-bit implementations and "ldarx" and "stdcx" for 64-bit implementations. Henceforth, the terms "lwarx" and "stwcx" are used to denote instructions for either implementation (the ldarx and stdcx instructions have essentially the same semantics with the exception that ldarx and stdcx operate on 8-byte quantities, and lwarx and stwcx operate on 4-byte quantities). These instructions serve to build synchronization primitives.
The lwarx instruction loads an aligned 4-byte word of memory into a register in the processor. In addition, lwarx places a "reservation" on the block of memory that contains the word of memory accessed. In most implementations, the reservation is placed on a block that is the same size as the block size used in the cache coherency protocol. A reservation contains the address of the block and a flag. This flag is made active, and the address of the block is loaded when a lwarx instruction successfully reads the word of memory referenced. If a reservation is valid (the flag is active) the processor and the memory hierarchy are obligated to cooperatively monitor the entire system for any operation that may write to the block for which the reservation exists. If such a write occurs, the flag in the reservation is reset. The reservation flag is used to control the behavior of the stwcx instruction.
The stwcx instruction is the counterpart to lwarx. The stwcx instruction first determines if the reservation flag is valid. If so, the stwcx instruction performs a store to the 4-byte word of memory specified, sets a condition code register to indicate that the store succeeded, and resets the reservation flag. If, on the other hand, the reservation flag in the reservation is not valid, the stwcx instruction does not perform a store to memory and sets a condition code register indicating that the store failed. The stwcx instruction is often referred to as a "conditional store" due to the fact that the store is conditional on the status of the reservation flag.
The general concept underlying the lwarx/stwcx instruction sequence is to allow a processor to read a memory location, modify the location in some way, and to store the new value to memory while ensuring that no other processor has altered the memory location from the point in time when the lwarx was executed until the stwcx completes. Such a sequence is usually referred to as an "atomic read-modify-write" sequence because the processor was able to read the location, modify it, and then write the new value without interruption by another processor writing to the location. The lwarx/stwcx sequence of operations does not occur as one uninterruptable sequence, but rather, the fact that the processor is able to execute a lwarx and then later successfully complete the stwcx ensures the programmer that the read-modify-write sequence did, in fact, occur as if it were atomic. This atomic property of a lwarx/stwcx sequence can be used to implement a number of synchronization primitives well-known to those skilled in the art.
From the descriptions of cache coherency and the semantics of the lwarx/stwcx instruction, it should be clear that there is a strong relationship between these two aspects of a symmetric multiprocessor system. The cache-coherency protocol seeks to control when processors can write to a memory location by serializing all writes to a given memory location in a certain order that all processors observe. To achieve this aim, the cache coherency protocol requires that a processor that wishes to write to a memory location inform all other processors (if any others have an interest in the block) of the desire to execute a write and obtain permission from these other processors before executing the write. Thus, information about writes to all memory locations is communicated throughout the system as writes are attempted. The lwarx/stwcx instructions, in contrast, seek to ensure that, once a lwarx is executed, any writes that occur after the lwarx that could potentially alter the memory location loaded by the lwarx will invalidate the reservation flag in the processor and thereby prevent the stwcx from storing to memory. Both of these goals rely on being able to determine when writes to memory locations occur. In fact, most implementations of the lwarx/stwcx instruction semantics rely on already existing cache-coherency protocol to aid in ensuring the lwarx/stwcx sequences are, in fact, atomic. Virtually all current implementations make the reservation valid for an aligned block of memory the same size as the block size used by the cache-coherency algorithm. This block is referred to as a reservation granule. This construction allows the mechanisms that implement lwarx/stwcx instruction semantics to re-use the messages that are communicated throughout the system for cache coherency to also aid in maintaining the semantics of lwarx/stwcx instructions. As a consequence of this implementation, any write that occurs to any location within the reservation granule will cancel the reservation, even if that write did not alter the particular location that was loaded by the lwarx instruction. This lack of precision in resetting the reservation flag is a typical trade-off made in implementations to allow the re-use of the cache-coherency messages as a means of implementing lwarx/stwcx instruction semantics.
To further understand how cache coherency and the implementation of lwarx/stwcx sequences are related, refer to FIG. 5, which shows one processing unit with the additional constructs necessary to support lwarx/stwcx explicitly shown (note that the processing units in FIG. 4 include these same constructs even though they are not explicitly shown in FIG. 4). For each cache in FIG. 5, there is a reservation unit (50a, 50b, 50c). These units contain the reservation, both the address (50d, 50e, 50f) and the flag (50g, 50h, 50i). These units each snoop their respective buses (51, 52, 53) for any write operation within the reservation granule address (50d, 50e, 50f) and invalidate the flag (50g, 50h, 50i) when such an operation is detected. As such, the reservation units are a party to the cache-coherency scheme. They monitor the buses and respond to bus transactions in a manner similar to the caches themselves.
In the prior art, the reservation unit addresses and flags are set in one of two general ways. At one extreme, if a processor attempts to issue a lwarx to a memory location whose block is not present in any cache of it's memory hierarchy, a read operation is propagated from the processor at the top of the hierarchy through each of the caches in the hierarchy and finally out on the generalized interconnect to be serviced, as was described earlier. However, unlike the earlier example, these read operations are tagged with a special indicator to inform the reservation units in the caches that the read is for a lwarx and that the reservation units should set the address and flag. At the other extreme, a processor can issue a lwarx to a memory location in a block already present in the L1 cache. This situation is known as an "lwarx hit." In this case, the processor's reservation unit will set its reservation address and flag (50d and 50g, respectively) and will issue a special bus operation know as a lwarx reserve (hereafter RESERVE) on the connection between the L1 and L2 cache (51). The L2 cache will receive the RESERVE message, which includes the address of the reservation, and will set its reservation address (50e) and flag (50h). In addition, the L2 cache will forward the RESERVE message on to the L3 cache which will repeat the actions taken by the L2 cache; at which point, all the reservation units will be properly set. Note that the process of propagating the RESERVE messages from L1 to L3 can take an arbitrary amount of time, in general, depending on availability of the inter-cache connections (51 and 52) and specific details of the particular implementation.
There is one other way the reservation units can be set. This situation occurs when a block has been partially, but not completely, evicted from a cache hierarchy. For example, assume that the processor executes a lwarx instruction to an address that is in a block not present in the L1 cache, but is present in the L2 cache (and by the inclusion principle, the L3 cache). In this case, the processor will issue a read that is marked as a read for a lwarx to the L2 cache. The L2 cache will determine that it has a copy of the block and return this block to the processor directly. Once the block is returned to the processor, the processor updates its reservation address and flag. The L2 cache will also set its reservation and send a RESERVE bus operation to the L3 cache to inform the L3 cache of the reservation. This scenario is merely a combination of the two cases described earlier. In general, a read from the processor with the lwarx indication propagates down the hierarchy setting reservation units until it encounters a cache that has a copy of the block which satisfies the read. That cache then propagates a RESERVE bus operation down the remainder of the hierarchy to set the remaining reservation units.
In this manner, all of the reservation units in the hierarchy are loaded as a result of a lwarx instruction with the proper reservation information and can begin snooping for transactions that write to the reservation granule. This allows the reservation units to reset the reservation flags and prevent a stwcx instruction from completing when the memory location for the reservation could have potentially been modified.
To illustrate the interplay between cache coherency and the reservation units, consider the second case discussed earlier where a processor executes a lwarx to a location present in the L1 cache. The processor will set its reservation and present a RESERVE bus operation on the inter-cache connection between the L1 and L2 caches (51). As was discussed earlier, an arbitrary amount of time can pass before a RESERVE bus operation can be propagated to the lowest level cache. It is possible for a write operation within the reservation granule to occur on the generalized interconnect after reservation has been made in the L1 cache, but before the RESERVE bus operations have been propagated to the L3 cache. In this case, the L3 cache has not been informed of the reservation and it would appear that the system could function incorrectly. This is not the case, however. Instead, the lowest-level cache, to ensure coherency, is required to propagate information about the write observed on the bus to the top of the hierarchy to ensure coherence. This will cause the L1 reservation unit to be informed of the write and thereby cause the L1 reservation unit to reset the reservation flag. In general, cache coherency requires that information about all writes (including those that occur to blocks with reservations) be propagated up the cache hierarchy of any processing unit to the highest level of the hierarchy that has a copy of the block present. Therefore, information about writes will be propagated up to the level at which a copy of the block is present, allowing the processor reservation flag to be reset when another processor executes a write to the reservation granule, even if the L3 cache has not yet been informed of the reservation.
However, if a block has been partially or completely evicted from a memory hierarchy, the cache-coherency protocol will not propagate information about writes any higher than the level of the highest cache that has a copy of the block present (the eviction of a block does not alter the validity of any reservation flags). In this case, some other mechanism must be responsible to propagate information about writes up the hierarchy to the processor in order to reset the reservation flag in the processor. This is the role of the reservation units. If a block has been evicted from a given level of the cache hierarchy, the cache no longer participates in the coherency protocol; however, the reservation does continue to participate. If the reservation unit detects a write to the block with an active reservation, the reservation unit will reset the reservation flag and propagate the information about the write up to the higher levels of the hierarchy to ensure that the semantics of the lwarx/stwcx instruction are preserved. However, until a block is evicted from a given level of the cache hierarchy, it is not necessary to involve the reservation unit due to the fact that the coherency mechanism will ensure that information about writes is propagated up to at least this level of the hierarchy. When a prior art system propagates RESERVE bus operations down the entire hierarchy on a lwarx hit, it serves only to make the reservation units ready to snoop for writes earlier than is absolutely necessary. The reservation units must snoop for writes only after the block has been removed from a given level of the cache hierarchy. Setting the reservation unit before the block is evicted is not strictly necessary.
It is important to note that, in prior-art systems, any time a lwarx instruction is executed by the processor and finds the block in the cache hierarchy, the RESERVE bus operations are propagated down through the rest of the hierarchy. This happens even if the processor already has an outstanding reservation for the block. As an example, a common synchronization primitive implemented with lwarx/stwcx, called test-and-test-and-set, first does a lwarx to a location in memory. If this location has a non-zero value, the processor branches back to the lwarx and reads the value again until it becomes zero. Once the lwarx returns a zero, the processor continues trying to change the value to one with a stwcx instruction. If this succeeds, the processor was able to read the zero, change it to one, and write it back again atomically. This procedure is the atomic read-modify-write sequence discussed earlier and sets a lock that prevents other processors from making progress (the other processors now read one and cannot proceed until they themselves have read a zero, and then have successfully modified it atomically to one). On average, a given processor will "spin" on the lwarx returning a one because some other processor already has the lock. In this case, for each lwarx that returns a one, a RESERVE operation is propagated down the entire hierarchy and onto the generalized interconnect (typically, the block with the memory location of the lock will be found in the L1 cache). The repeated broadcasting of RESERVE bus operations is known as a "lwarx storm." This imposes a severe performance degradation and is a limitation of the prior-art systems. It would, therefore, be desirable to devise a more efficient method of implementing lwarx/stwcx semantics, so as to reduce system bus traffic and achieve higher overall system performance. It would be particularly advantageous if the reserve bus operation were not required to be transmitted down the entire depth of the cache hierarchy.

Demand-based larx-reserve protocol for SMP system buses

International Business Machines Corporation


Systems and methods of establishing group calls are provided. Contact index information is synchronized between a communication unit and a contact synchronization server. A group call request message, including index information for one or more contacts, is sent from a communication unit to a signaling server. The signaling server uses the index information to obtain communication unit addresses from the contact synchronization server.

The explosive growth of communication networks such as the Internet and wireless communication networks has reduced the need to travel for group activities. Instead, group activities are now commonly conducted remotely, using various types of wired and wireless communication networks. There are various techniques for establishing group communications. Originally, group communications were established using a conference call in which the originator of the conference call dialed telephone number of each participant and the originator's communication device would bridge each participant into the conference call. Communication network-based conference bridges are now commonly employed for group communications in which the conference originator distributes a call-in number for the network-based conference bridge, and each participant must call the number of the conference bridge in order to join the group communication.


A method, system and computer program product for electronically communicating a correct Uniform Resource Locator (URL). The browser detects a copying of a URL to be placed in an electronic communication. In response to determining that the URL specifies an address of a loopback interface of the computing device via a localhost, the browser obtains the Fully Qualified Domain Name (FQDN) or Internet Protocol (IP) address of the computing device hosting the resource (e.g., application) referenced by the URL. The browser replaces the localhost in the URL with either the FQDN or IP address of the computing device. The modified URL is then made available to be shared with other users via electronic communication. In this manner, the localhost is automatically replaced with the correct domain name or IP address thereby ensuring that third party users will be able to retrieve the resource hosted on the computing device.

In computer networking, the localhost (meaning this computer) is the standard hostname given to the address of a loopback network interface. On modern computer systems, the localhost as a hostname translates to an IPv4 address in the 127.0.0.0/8 (loopback) net block, usually 127.0.0.1.
Localhost is specified where one would otherwise use the hostname of a computer. For example, directing a web browser installed on a system running an HTTP server to the Uniform Resource Locator (URL) of http://localhost will display the home page of the local website, provided the server is configured to service the loopback interface.
Using the loopback interface is useful for testing software, such as web based applications, since it bypasses local network interface hardware. Connecting to locally hosted network services using loopback addresses puts less of a load on network resources.
While using the loopback interface is useful for testing software, the developer of the software may want to share in an electronic communication (e.g., e-mail, instant message) the URL that specifies the location of the application on the local machine. However, in order for other users to retrieve the application via the use of the URL, the localhost in the URL needs to be replaced with either the fully qualified domain name or the Internet Protocol (IP) address of the machine that is hosting the application.
Currently, in order to communicate the appropriate URL to the other users to retrieve the application hosted on the developer's machine, the developer manually copies the URL from his/her browser and replaces the localhost with either the fully qualified domain name or the Internet Protocol (IP) address of the machine that is hosting the application. However, such a process leads to errors, such as when the developer incorrectly copies and pastes the URL into a communication (e.g., e-mail) to another user or incorrectly types the domain name/IP address that replaces the localhost in the URL.

Automatically replacing localhost as hostname in URL with fully qualified domain name or IP address

International Business Machines Corporation


A tissue penetrating catheter that is usable to advance a tissue penetrator from within a blood vessel, through the wall of the blood vessel to a target location. The catheter includes at least one stabilizing device thereon for stabilizing catheter prior to advancing the tissue penetrator. The tissue penetrator may extend through a lumen in the body of the catheter and project transversely through an exit port. The stabilizing device may be located closely adjacent to the exit port, or may surround the exit port. The stabilizing device may be one or more balloons, or other mechanical structure that is expandable into contact with the inner luminal wall of the blood vessel. Desirably, the exit port is forced into contact with the blood vessel wall to shorten the distance that the tissue penetrator projects from the catheter body to the target location. The catheter is particular useful for forming blood flow tracts between blood vessels, in particular in coronary revascularization procedures. Methods of utilizing such a catheter to bypass an arterial obstruction is also disclosed.

Atherosclerotic cardiovascular disease remains a major cause of premature death and morbidity, in most regions of the world. Various transluminal, catheter-based interventional techniques have been used, or proposed for use, to dilate or otherwise treat atherosclerotic obstructions that occur in coronary and/or peripheral arteries. These therapies have traditionally focused on treating the disease intraluminally, or from "within" the vessel lumen.
The devices, systems and methods proposed in previous disclosures from which the present application claims priority introduce a new method of percutaneous revascularization wherein the cardiac veins may either be arterialized, or may be simply used as bypass grafts. Various percutaneous, transluminal techniques have thus been developed for bypassing obstructions in coronary or peripheral arteries through the use of the adjacent vein(s) as in situ bypass conduit(s); (e.g. using catheters to perform extra luminal procedures outside the diseased vessel lumen. In some instances, these procedures may be performed by a venous approach wherein a tissue penetrating catheter is inserted into a vein and the desired passageway or puncture is initially formed by facilitating the passage of a tissue penetrator (e.g., a flow of energy or an elongate penetration member) from a catheter, through the wall of the vein in which the catheter is positioned, and into a target location such as the lumen of an adjacent vessel (e.g. the artery). Alternatively, some of these procedures may be performed by an arterial approach wherein the catheter is inserted into an artery and the desired passageway or puncture is initially formed by facilitating the passage of a tissue penetrator (e.g., a flow of energy or elongate penetration member) from the catheter, through the wall of the artery in which the catheter is positioned, and into the target location such as the lumen of an adjacent vessel (e.g. a vein).
The present invention derives from and expands upon the previous disclosures with respect to stabilizing a tissue penetration catheter in a body lumen.
The prior art has included tissue penetrating catheters for uses other than those claimed in this patent application, but such prior art tissue penetrating catheters fail to include all of the elements required for optimal use in the methods of this invention or for precise targeting of the location at which the penetration tract is to be made. For example, U.S. Pat. No. 5,464,395 (Faxon et al.) discloses a catheter for delivering therapeutic and/or diagnostic agents to tissues surrounding a body passageway (e.g., the lumen of a blood vessel). The catheter devices disclosed by Faxon et al. generally comprise a catheter, a needle cannula that is able to be projected outboard of the catheter so as to deliver the desired agents to the tissue, and preferably one or more inflatable balloons useable to perform a balloon angioplasty procedure in addition to the injection of drugs or other therapeutic or diagnostic agents into tissues surrounding the vessel in which the catheter is positioned. However, the Faxon et al. device does not incorporate any means for precisely aiming its needle to a specific target location. Thus, while the Faxon et al. device may be useable to deliver drugs or other materials to relatively non-specific locations surrounding a vessel in which the catheter is positioned, its lack of sophisticated orientation and aiming apparatus renders it less than optimal for performing injections into specific or discrete target locations such as small anatomical structures, other blood vessels, etc.
Accordingly, there remains a need in the art for the development of new stabilized tissue penetrating catheters that can be used for revascularization, drug delivery, transluminal interstitial interventions and other procedures wherein it is desired to pass a tissue penetrator from a catheter, through the wall of a vessel (e.g, blood vessel or other body lumen) in which the catheter is positioned and to a target location (e.g., another blood vessel, a specific location within tissue, an organ, tumor or other anatomical target structure or lesion.

This patent is subject to a terminal disclaimer.


A light beam scanning optical apparatus which writes two lines at one scan on a photosensitive member with light beams emitted from two light sources. A light source unit of the apparatus has a first movable retainer block which retains a first laser diode and a second movable retainer block which retains a second laser diode. The second movable retainer block becomes adjustable two-dimensionally on a base block by loosening screws which fit the second movable retainer block to the base block.

1. Field of the Invention
The present invention relates to a light source device and a light beam scanning optical apparatus, and in particular, to a light source device and a light beam scanning optical apparatus to be used as image writing means of a laser printer or a digital copying machine.
2. Description of Related Arts
Conventionally, a variety of light beam scanning optical apparatuses have been known as means for writing an image onto a photosensitive member. In those apparatuses, a light beam emitted from a light source unit is scanned as deflected by a polygon mirror and focused on a photosensitive member via an f.theta.-lens or the like. A variety of optical members are housed in a box-shaped housing 100 opened upward as shown in FIG. 15. For example, the light source unit and the polygon mirror are housed in a recess portion 101 and a recess portion 102 of the housing 100, respectively, and after completing various adjustment works, the housing 100 is enclosed by a lid member (not shown).
In recent years, there has been growing demands for increasing a pixel density and increasing an image writing velocity. In compliance with these demands, there has been developed a multi-beam type optical apparatus in which two light sources are provided and light beams emitted from the respective light sources are scanned as deflected in a state in which they are close to each other in a sub-scanning direction so as to write two lines during one scan.
In the multi-beam system, two light sources are housed in the aforementioned recess portion 101, where members for retaining the light sources (laser diodes) are required to be adjusted in position from the directions of arrows h, and he for positional adjustment of the light beams. However, the side walls of the housing 100 become an obstacle in this adjustment, and therefore, it has been required to form an opening in either one of the directions of arrows h.sub.1 and h.sub.2 and execute the adjustment by inserting an adjusting instrument such as a screwdriver through this opening. As described above, it has been hard and troublesome to execute the positional adjustment sideways after the light source unit has been assembled into the housing 100.

Light source device and light beam scanning optical apparatus


To provide a disk playback system that effectively uses the maximum playback speed and maximum search speed that the system owns.

The present invention relates to a disk playback system that is used in a CD-ROM playback apparatus or the like that reads out information recorded on a disk to transfer to an external device.
Taking a CD-ROM playback apparatus as an example, we describe a conventional kind of disk playback system. The CD-ROM playback apparatus receives a command from an external device such as a personal computer to search for a desired position and reads out desired data from the data recorded on a disk to transfer to an external device. An audio CD (compact disk) and a CD-ROM disk are recorded with a constant linear velocity (CLV) and supposed to be played back at one time the velocity.
In recent years, as personal computers increase their speed, high-speed readout and high-speed access are demanded for CD-ROM playback apparatus as a peripheral equipment of computers. In order to satisfy such demands, CD-ROM playback apparatuses that perform a constant high-speed readout at 2 times or 4 times the CLV or the like during playback time of a CD-ROM disk are now on the market. However, in order to raise search speed with constant high-speed readout at 2 times or 4 times the CLV or the like, loads on the disk motor that drives the disk become exceedingly large, so that there has been a problem that a large-sized disk motor at high cost is required.
Therefore, there are sold at a market CD-ROM playback D apparatuses that employ the CAV playback method that plays back at CAV (constant angular velocity) a disk that has been recorded at CLV, the wide-range CLV playback method that is CLV but has a very wide playback range and can perform high-speed searches and constant high-speed playbacks, or the PCAV (partial CAV) playback method that is a combination of the CAV playback method and the wide-range CLV playback method. CD-ROM playback apparatuses that employ these methods all realize high-speed searches by lightening the loads on their disk motors to use low-priced and compact disk motors.
Now, in a CD-ROM playback system that employs the above CAV playback method, wide-range CLV playback method, PCAV playback method, or the like, the maximum operation speed of the system, that is, the maximal processing capacity of signals is specified, and the system is constructed in such a way as the outermost perimeter of the disk is N times the velocity, if the maximum operation speed of the system is N times the velocity. However, in most disks, data is not recorded to the outermost perimeter, and the above speed is a playback criterion, even if the data-recorded area is small, so that there has been a lot of waste. Therefore, in the Japanese Patent Application No. 6-103878, there is proposed a disk playback system that operates in such a way as the criterion of disk playback speed is determined so as to obtain the maximum search speed and high-speed readout, depending on the outermost perimeter of the data-recorded area.
In the above disk playback system, the criterion of the disk speed control is, as mentioned above, the outermost perimeter of the data-recorded area in which data is recorded. Therefore, the playback speed criterion mentioned above is used even if only the data near the inner perimeter of the disk, of the data recorded on the disk, is actually used, or the use frequency of the data at the outer perimeter is very low. Therefore, in the above disk playback system, there has been a problem that the maximum playback speed and maximum search speed that the system owns cannot be effectively used.
An object of the present invention is to provide a disk playback system that effectively uses the maximum playback speed and maximum search speed that the system owns.
The disk playback system stated in claim 1 of the present invention searches for a desired position of a disk on which information data is recorded at a constant linear velocity when received a command from an external device, reads out desired information data from the aforementioned information data, and outputs information data corresponding to the playback format of the aforementioned disk, being characterized in that the playback system is equipped with a determining means that, if the address information of the newest address accessed by an access instruction of the disk is address information indicative of an address outer than the outermost address that has been accessed, renews stored address information to the address information of the newest address, and determines a criterion for speed control of the disk, based on the newest renewed address information, and a rotation control means that controls the speed of the disk, based on the criterion determined by the determining means.
When a disk is played back in a system whose maximum processing capacity is N times the CLV, and if an approximately inner one half area of the data to be played back has been used, for example, the above determining means determines the speed criterion so as to perform processing at that position, i.e., the outermost track position that has been accessed, at N times the velocity, i.e. the maximum processing capacity. When receiving an access instruction for a further outside perimeter, the determining means determines again the speed criterion. By this means, the maximum search speed and high-speed readout can be obtained, depending on the outermost perimeter of the data-recorded area that has been accessed.
The disk playback system stated in claim 2 of the present invention is characterized in that in the disk playback system of claim 1, the aforementioned rotation control means is a CAV control circuit that rotates the disk at a constant angular velocity (CAV).
When a disk is played back in a system whose maximum processing capacity is N times the velocity (CLV), and if an approximately inner one half area of the disk to be played back has been used, for example, the above determining means determines the speed criterion for the angular velocity of the disk so as to perform processing at that position, i.e., the outermost track position that has been accessed, at N time the velocity, i.e. the maximum processing capacity. At this time, the speed at the innermost perimeter becomes N/1.6 times the velocity, and the criterion speed for readout becomes high. When receiving an access instruction for a further outside perimeter, the determining means determines again the speed criterion. By this means, the maximum search speed and high-speed readout can be obtained, depending on the outermost perimeter of the data-recorded area that has been accessed.
The disk playback system stated in claim 3 of the present invention is characterized in that, in the disk playback system of claim 1, the rotation control means is equipped with a CLV control circuit that rotates the disk at the constant linear velocity (CLV) and a variable clock generating circuit that supplies the CLV control circuit with a comparison clock that varies with the output of the determining means.
When a disk is played back in a system whose maximum processing capacity is N times the velocity, and if an approximately inner one half area of the disk to be played back has been used, for example, the above determining means determines the speed criterion for the linear velocity of the disk so as to be able to perform processing at that position, i.e., the outermost track position that has been accessed, at N times the velocity, i.e. the maximum processing capacity. At this time, N/1.6 becomes the criterion for CLV, and readout speed becomes high. When receiving an access instruction for a further outside perimeter, the determining means determines again the speed criterion. By this means, the maximum search speed and high-speed readout can be obtained, depending on the outermost perimeter of the data-recorded area that has been accessed.
The disk playback system stated in claim 4 according to the present invention searches for a desired position of a disk on which information data is recorded at a constant linear velocity, when received a command from an external device, reads out desired information data from the aforementioned information data, and outputs information data corresponding to the playback format of the disk, being characterized in that the playback system is equipped with a determining means that, if the address information of the newest address accessed by an access instruction of the aforementioned disk is address information indicative of an address outer perimeter than the outermost address that has been accessed, renews stored address information to the address information of the newest address, and determines a criterion for speed control of the disk, based on the newest renewed address information, and also equipped with a first rotation control means that rotates the disk at constant angular velocity (CAV), based on the criterion determined by the determining means, a second rotation control means that rotates the disk at constant linear velocity (CLV), and a switching means that switches the first and second rotation control means.
When a disk is played back in a system whose maximum processing capacity is N times the velocity, and if an approximately inner one half area of the disk to be played back has been used, the above determining means determines a speed criterion for the angular velocity and linear velocity of the disk so as to be able to perform processing at that position, i.e., the outermost track position that has been accessed, at N times the velocity, i.e. the maximum processing capacity. At this time, when the disk is rotated at constant angular velocity (CAV), by using the first rotation control means, the speed at the innermost perimeter becomes N/1.6 times the velocity, and the criterion speed for readout becomes high. When the disk is rotated at constant linear velocity (CLV), using the second rotation control means, N/1.6 becomes the criterion for CLV, and readout speed becomes high. When receiving an access instruction for a further outside perimeter than the stored address, the determining means determines again the speed criterion. By this means, the maximum search speed and high-speed readout can be obtained, depending on the outermost perimeter of the data-recorded area that has been accessed.

Abstract: A disk playback system that searches for a desired position of a disk (2) on which information data is recorded at constant linear velocity after receiving a command from an external device, reads out desired information data, and outputs information data corresponding to the playback format of the disk. An outermost-perimeter-address memory circuit (21) renews stored address information to the newest address information, if the address information of the newest address accessed according to an access instruction of said disk indicates the newest address is outer perimeter than the outermost address that has been accessed, and determines a criterion for speed control of the disk (2), based on the renewed address information. A CAV control circuit (20) controls the speed of the disk 2, based on the determined criterion.

Matsushita Electric Industrial Co., Ltd.


A first subscriber authenticates himself to a second subscriber with a certificate associated to the first subscriber. The certificate specifies one or several characteristics, which have to be fulfilled by the second subscriber. In the course of the authentication, it is verified using the certificate whether the second subscriber fulfills the characteristics, wherein a criterion required for successful authentication is that the second subscriber fulfills the characteristics(s). Characteristics of the second subscriber are verified in the framework of the authentication process, the second subscriber representing the authenticator with respect to whom the authentication is carried out. In this way, certificates for authentication dedicated communication links between two communication partners can be determined. The method can be used for any subscribers in a communication network, e.g., representing components of an automation system, such as, for example, control devices, field devices, sensors, actuators and the like.

Described below is a method for certificate-based authentication in which a first subscriber authenticates itself to a second subscriber with the aid of a digital certificate assigned to the first subscriber.
Digital certificates are well known. They contain the identity of an entity in the form of a person or institution or machine for which the certificate has been issued. Here and in the following, the concept of a subscriber to which a certificate can be assigned is used. In this context, a subscriber can be a computer or a machine for which the certificate has been issued. A subscriber can also refer to a computer or a machine which manages the certificate for a person or institution. The certificate is assigned to the computer or the machine by the responsibility for the certificate management.
A certificate contains a public key for the corresponding entity and the owner of the certificate can be confirmed by a digital signature in the certificate. In this context, the digital signature is calculated by a certificate authority. A root certificate from this authority or a certificate chain to the root certificate can be used to verify the signature as valid. A digital certificate can contain additional encrypted information in the form of so-called attributes which can be used to define authorizations for the user of the certificate or restrictions on the use of the certificate. For example, it is known, how to use an attribute to restrict the certificate or the cryptographic key confirmed by the certificate to certain types of communications or communication protocols only. It is also known how to restrict the geographic validity of a certificate so that, in the course of an authentication, the certificate can only be used by subscribers in a predetermined geographical area.
Also known is how to encrypt WLAN network names in a certificate as certificate extensions in order in this way to select a suitable certificate from a plurality of certificates held by the subscriber which is authenticating itself.
In addition, the encryption of authorization information is described in certificates. This authorization information is used to define the accesses that may be effected by the subscriber authenticated by the certificate. It is also known how to encrypt role information in certificates in order to simplify the administration of authorized accesses to a plurality of subscribers. In this context, a subscriber is granted or refused access to another subscriber in dependence on the role stored in the certificate.
Although known certificate extensions permit a restriction of the use of the certificate, they do not permit the definition of dedicated communication connections between two communication partners which are to have exclusive use of the certificate.

Method for certificate-based authentication


A brake pipe leakage test for a train is performed using an improved brake pipe drop pressure method prior to departure of the train consist from a railyard terminal. The train consist includes a brake, a brake pipe, and a brake pipe cutoff valve. The method comprising the steps of: (a) charging the brake pipe to within approximately 15 psi of a drop method setup pressure; (b) applying the brake on each locomotive and each railcar in the train consist; (c) making a prefigured reduction in pressure within the brake pipe; (d) determining length of the train consist; (e) waiting a predetermined time for the reduction in pressure to occur within the brake pipe, the predetermined time depending upon the length of the train consist; (f) closing the brake pipe cutoff valve after waiting the predetermined time thereby closing the brake pipe; (g) waiting a prespecified time during which pressure within the brake pipe settles; (h) monitoring leakage from the brake pipe for approximately one minute; (i) passing the train consist from the brake pipe leakage test only if the leakage does not exceed approximately 5 psi during the one minute period; (j) locating and repairing source(s) of the excessive leakage if the train consist fails the brake pipe leakage test; and (k) repeating the brake pipe leakage test after the source(s) of the excessive leakage have been located and repaired and until the train consist passes the brake pipe leakage test.

As is generally well known in the railway brake equipment art, various procedures for predeparture inspection and brake testing have been employed in the railway industry since development of the first railcar trains well over a century ago. Mandated now by the Federal Railroad Administration (hereinafter referred to as "FRA"), the procedure for the predeparture inspection and testing of air brake equipment (hereinafter "terminal test procedure") must be performed prior to departure of a train from a railyard terminal. The terminal test procedure includes an initial brake pipe leakage test followed by a brake application test and a brake release test.
Before the terminal test procedure can be performed, one or more locomotives are aligned on a railyard track with one or more railcars and coupled together to form what in the railroad industry is referred to as a train consist. The locomotives and the railcars not only must be physically coupled together but their air hoses must also be connected together to form what is called an air brake pipe. The air brake pipe is essentially a continuous pipe running from a head of train locomotive to a last railcar in the train consist. The continuous air brake pipe serves to supply the brakes of each vehicle in the train consist with the air pressure required for brake operation and for performance of the aforementioned brake pipe leakage, brake application and brake release tests.
The initial brake pipe leakage test of the terminal test procedure may be performed by either the Traditional Brake Pipe Drop Pressure Method or the more recently introduced Air Flow Method. Basically, the Traditional Brake Pipe Drop Pressure Method involves charging the brake pipe to within approximately 15 psi of a drop method setup pressure as measured at predefined points along the train consist. The brake pipe is sufficiently pressurized to apply the brakes on each railcar in the train consist. A prefigured full service reduction in the pressure within the brake pipe is then made. After listening for the exhaust from the brake pipe to stop so as to determine when the prefigured reduction has been achieved, a brake pipe cutoff valve is closed. Following a prespecified time during which the brake pipe pressure settles, the leakage from the brake pipe is monitored for one minute. Only if the leakage does not exceed 5 psi within the one minute period does the train consist pass the brake pipe leakage test.
The Air Flow Method essentially involves charging the brake pipe to within approximately 15 psi of an air flow method setup pressure as measured at predefined points along the train consist and so that the brake pipe pressure at the last railcar is greater than or equal to 75 psi. The brake pipe is sufficiently pressurized to apply the brakes on each railcar in the train consist. The air flow within the brake pipe is measured. Only if the air flow is less than 60 cubic feet per minute does the train consist pass the brake pipe leakage test. No matter which method is performed, if the train consist fails the brake pipe leakage test, the source(s) of the excessive leakage must be located and repaired and the brake pipe leakage test repeated.
The brake application and release tests of the terminal test procedure have traditionally been labor intensive operations, generally requiring at least two railyard workers to perform. For example, beginning with the brake application test, a cab worker situated in a cab of the head of train locomotive manually applies the brakes of the train consist in response to the instructions of one or more other workers commonly (and hereinafter) referred to as maintainers located outside the train consist. The brakes are manually applied typically through a brake handle situated on a cab control unit located in the head of train locomotive. (Although one of the maintainers could climb into the cab to perform the brake handle manipulations, it is advisable that the brake controls be staffed during the terminal test procedure.) The maintainer(s) then walk the length of the train consist from the head of train locomotive to the last railcar inspecting the brake equipment of each locomotive and each railcar and visually verifying that the brakes have applied.
Nearly identical to the brake application test, the brake release test also generally requires at least two railyard workers to perform. The maintainer(s) return to the head of train locomotive to inform the cab worker to release the brakes. The cab worker manually releases the brakes through the brake handle. The maintainer(s) then again walk the length of the train consist inspecting the brake equipment of each railcar and each locomotive and visually verifying that the brakes have released. The maintainer(s) may then return to the head of train locomotive to inform the cab worker to reapply the brakes.
The inspection conducted during the brake application and release tests includes examination of the brake equipment including brake piston travel, brake shoes, brake cylinders, rigging and other brake system components. The brake application and release tests also entail listening for leaks from the brake system components and the hose couplings. Any and all problems revealed during the course of the inspection must be corrected prior to the departure of the train consist, except as allowed by the Power Brake Law.
The brake application and release tests thus require (1) the labor of at least two railyard workers (i.e., one in the cab to apply and release the brakes and one to walk the train to inspect, and verify application and release of, the brakes) and (2) generally, three trips by one or more workers between the head of train locomotive and the last railcar.
The present automated terminal test system substantially improves upon several existing components of a train consist. Generally, a typical head of train locomotive has a cab control unit, computer controlled brake equipment such as WABCO EPIC.RTM. Brake Equipment, cab integration equipment such as WABCO Cab Integration Equipment for controlling train operation, a cab keyboard for accessing the cab integration equipment, a cab display for monitoring train operation, a typical head of train device, and, possibly, a systems integrator such as Integrated Cab Electronics (ICE) made by General Motors Corporation or Integrated Function Control (IFC) made by General Electric Corporation. The cab control unit, the cab display, the cab keyboard and the brake equipment essentially comprise the cab integration equipment. Therefore, for the purposes of the present invention set forth below, communication to the cab integration equipment signifies communication to the brake equipment, the cab control unit and the cab display and vice versa. These elements, however, are herein generally set forth separately in terms of their function and interrelationship as basic foundation for the detailed description and claims to follow.
Referring still to the elements of the typical head of train locomotive, the cab control unit includes an automatic brake handle and an independent brake handle. The automatic brake handle permits the application and release of the brakes on each locomotive and each railcar in the train consist. The independent brake handle permits the application and release of the brakes on each locomotive in the train consist.
The typical head of train device is connected to and monitors the pressure within the brake pipe on the head of train locomotive. The typical head of train device also receives communications from a typical end of train device. The typical end of train device is connected to the brake pipe on a last railcar of the train consist. The typical end of train device monitors both the pressure within the brake pipe on the last railcar and the movement of the last railcar. The typical end of train device transmits the resulting last railcar brake pipe pressure data and the last railcar motion data to the typical head of train device.
In a standalone head of train locomotive (i.e., a head of train locomotive not equipped with the systems integrator), a train operator uses the cab keyboard to input various commands to the cab integration equipment so as to control the operation of the train. The parameters associated with train operation are monitored on the cab display. In a non-standalone head of train locomotive (i.e., one equipped with the systems integrator), the systems integrator essentially controls the cab integration equipment; the details of such control not being necessary to an understanding of the present invention. The systems integrator provides an integrator keyboard as a means for inputting the various commands to the cab integration equipment. The systems integrator provides an integrator display for monitoring the parameters associated with train operation. Consequently, in non-standalone locomotives, the inputting and monitoring functions are accomplished through the integrator keyboard and the integrator display, respectively, of the systems integrator rather than the cab keyboard and the cab display of the cab integration equipment.
In the standalone head of train locomotive, the typical head of train device relays to the cab integration equipment through a first communications link the last railcar brake pipe pressure data, the last railcar motion data and the head of train brake pipe pressure data. The cab integration equipment outputs such data to the cab display for monitoring by the train operator. Additionally, the cab integration equipment relays such data to the computer controlled brake equipment through a second communications link. The computer controlled brake equipment uses such data to control the application and release of the brakes of the train consist and to maintain proper brake pipe pressure.
In the non-standalone head of train locomotive, the typical head of train device relays to the systems integrator through a first integrator link the last railcar brake pipe pressure data, the last railcar motion data and the head of train brake pipe pressure data. The systems integrator outputs such data to the integrator display for monitoring by the train operator. In addition, the systems integrator relays such data to the computer controlled brake equipment through a second integrator link. The computer controlled brake equipment uses such data to control the application and release of the brakes of the train consist and to maintain proper brake pipe pressure.
It should be emphasized that in both standalone or non-standalone head of train locomotives the last railcar brake pipe pressure data, the last railcar motion data, and the head of train brake pipe pressure data will ultimately be relayed from the head of train device to the computer controlled brake equipment, part of the cab integration equipment.
It should be further noted that, in a train consist having either the standalone or the non-standalone head of train locomotive, an automated terminal test system of any type will still require the maintainer(s) to walk the length of the train consist for the purpose of inspecting the brake equipment and verifying application and release of the brakes. The present invention, however, both avoids the need for the cab worker as it gives the maintainer(s) control of the brakes from outside the train consist and reduces the number of walks the maintainer(s) must make between the head of train locomotive and the last railcar during the terminal test.

Method for performing a brake pipe leakage test


The present invention relates to T cells, in particular a non-activated T cell, comprising an exogenous nucleic acid encoding a T cell Receptor (TCR) specific for a virus. An embodiment of the invention is directed to a non-activated (resting) T cell expressing Hepatitis B virus (HBV) envelope s183-191 TCR capable of inhibiting viral replication and which shows reduced expression of perforins and/or granzymes in response to stimulation as compared to an activated T cell expressing the said TCR. Also encompassed are methods for producing such cells, compositions, pharmaceutical compositions and kits comprising such cells and medical uses thereof.

Current antiviral therapies are able to control HBV replication but cannot eliminate HBV cccDNA from infected hepatocytes. Standard therapeutic strategies are expensive, and either require life-long treatment, as is the case for treatment with nucleoside/nucleotide analogues, or are associated with severe negative side effects, as with IFN-α therapy. After several years of exposure to HBV antigens, HBV-specific T cells are often deleted or functionally exhausted in chronically-infected patients. Strategies to manipulate the virus-specific T cell response could lead to clinical therapies to treat chronic infections or prevent mortality related to severe acute infections.
Adoptive transfer of T lymphocytes engineered to achieve tumor specificity through the genetic insertion of either T cell receptors or chimeric antigen receptors (CARs) allows remarkable control of disseminated tumors. Engineering new HBV-specific T cell immunity through adoptive transfer of T cells expressing HBV-specific T cell receptors can reconstitute antiviral immunity that resembles one present in patients that resolve acute infection to control the virus, and represents a promising therapeutic strategy.
T cells engineered to express a hepatitis B virus (HBV)-specific TCR have been shown to be able to recognize natural hepatocellular carcinoma (HCC) cells expressing HBV antigens from integrated HBV DNA (Gehring et al., J Hepatol (2011) 55(1): 103-110), and activated T cells engineered by electroporation to express HBV-specific TCR have been shown to be capable of preventing HCC tumor cell seeding, and multiple infusions of such cells have been shown to control tumor growth in vivo (Koh et al., Mol Ther Nucleic Acids (2013) 2: e114). Moreover, adoptive T cell therapy with T cells expressing HBV surface Antigen (HBsAg)-specific TCR has been shown to suppress levels of HBsAg in a liver transplant patient with HCC metastases (Qasim et al., J Hepatol (2015) 62(2): 486-491).
However, there are serious side effects and/or toxicities associated with adoptive T cell therapy. Expression of low levels of target antigen in normal tissues, or cross-reactivity of the TCR with endogenous protein, can result in serious adverse effects. For example, Morgan et al., J Immunother (2013) 36(2): 133-151 describe neurological toxicity associated with adoptive T cell therapy with T cells engineered to express Anti-MAGE-A3 TCR, possibly as a result of expression of MAGE-A12 in human brain. Toxicity concerns have hindered implementation of therapy with adoptive transfer of virus-specific T cells directed against viruses infecting essential organs.

Non-activated t cells expressing exogenous virus-specific T cell receptor (TCR)


A confocal scanning system for the multispectral imaging of fluorescence from a tissue sample based on time domain mapping of spectral components of the fluorescence using coated fiber tips disposed on multimode optical fibers. A fiber grating spectrometer based on two serial arrays of coated fiber tips disposed on multi-mode fiber, and delay lines between them provide spectral slices of the florescence. The coated fiber tips are arranged such that the shortest wavelength spectral components are reflected first and the longest wavelength components last. Fiber-based delay lines delay the reflections from each successive fiber tip such that they are uniformly separated in time, and in the order of its spectral wavelength number. The spectral bins are used to colorize the images to show the presence of abnormal tissue at cellular spatial resolution. A second scan with increased laser flux can destroy the diseased tissue revealed by the first scan.

Various imaging systems and techniques have been used for biomedical applications, such as tissue mapping. One approach to tissue mapping involves multispectral imaging, where the tissue to be mapped is conjugate with a detector array, such as charge coupled device (CCD) or a photo-diode array. In the array, the spatial data is directly obtained in the image. A tunable filter, such a liquid crystal filter (LCTF) or acousto-optical tunable filter (AOTF) can be placed before the detector array, and images collected for each color setting of the filter. Alternatively, a volume hologram can be placed before the detector array, with images collected by pixel arrays positioned where each color is diffracted.
The above imaging systems, however, are generally limited in terms of temporal response time, typically about 25 microseconds (for the AOTF) to 100 milliseconds (for the LCTF) per wavelength. For weak intrinsic fluorescence, these later systems also have long array integration times, leading to multispectral-image acquisition times of several seconds—which are too long for live biological samples. Other approaches use confocal microscopy where high resolution images are obtained using a condenser lens to focus illuminating light from a point source into a diffracted limited spot within a specimen. An objective lens then focuses the light emitted from that spot onto a small pinhole and a detector measures the amount of light passing through the pinhole. Because only light from within the illuminated spot is focused through the pinhole, any stray light is filtered out, greatly improving the image quality. A coherent image is created by scanning point by point over the desired field of view, and recording the intensity of the light emitted from each spot, as small spots are illuminated at any one time. Scanning can be accomplished in several ways, such as laser scanning.
Multi-spectral confocal mapping holds great promise for imaging cancer cells at the cellular and molecular levels. Indeed, the National Institute of Health (NIH) has encouraged research and development pertaining to in-vivo image guided cancer interventions. Also, many cancers can be detected with multi-spectral imaging of fluorescence. See Thiberville, L., Moreno-Swirc, S., Vercauteren, T., Peltier, E., Cave, C., Heckly, G. B., "In Vivo Imaging of The Bronchial Wall Microstructure Using Fibered Confocal Fluorescence Microscopy," Am J Respir Crit Care Med 175, 22-31 (2007); Fu, S., Chia, T. C., Kwek, L. C., Diong, C. H., Tang, C. L., Choen, F. S., Krishnan, S. M., "Application of Laser Induced Autofluorescence Spectra Detection In Human Colorectal Cancer Screening," Proc. SPIE-OSA Biomedical Optics 5141, 298-304 (2003); and Ramanujan, V. K., Ren, S., Park, S., Farkas, D. L., "Non-Invasive, Contrast-Enhanced Spectral Imaging of Breast Cancer Signatures In Preclinical Animal Models In Vivo," J Cel Sci Therapy 1, 102-106 (2010).
Moreover, spectroscopic tools can provide multi-spectral data during laser excitation of fluorescence, 2-photon, and Raman spectroscopies, especially useful where samples are labeled with a variety of molecular-specific contrast agents. Multi-spectral imaging is typically done with one grating and multiple pixels in a detector array, but this approach is limited by read-out noise and dark current. As such, most biomedical applications center on labeled tissue and/or the use of costly PMT arrays, preventing clinical applications in humans. This latter limitation is addressed in U.S. Pat. No. 7,366,365 entitled "Tissue Scanning Apparatus and Method." In this latter patent, there is described a system for multispectral confocal mapping of tissue suitable for scanning in-vivo or ex-vivo tissues where spectra can be acquired for each pixel in a confocal spatial scan. More particularly, there is described a confocal spatial scan system in conjunction with a fast fiber Bragg grating spectrometer. This combination maps wavelengths into time slots and is fiber based. The fiber that connects the fast optical spectrum analyzer to the scanner functions as the pinhole in a confocal microscope. That is, the cleaved end of fiber provides the confocal pinhole. The spectrum analyzer provides spectra derived from un-blazed fiber Bragg gratings that have delay lines between the gratings. The use of a single detector in a confocal arrangement easily offers spectral resolutions of about 1-2 nm.
Unfortunately, this latter approach above cannot offer spectral resolution above 10 nm in a practical and cost effective manner, a regime particularly useful for applications in humans such as optical biopsy and surgical margin assessments. Moreover, the fiber Bragg gratings in the '365 patent are realized using single mode fiber typically having a core diameter of about 3 μm, thereby limiting the collection efficiency, impractical for weak intrinsic fluorescence.

System for multispectral imaging of fluorescence


Municipal solid waste (MSW) material is sized to provide a particulate material which is density separated into organic and inorganic portions using a suitable polar acidic organic liquid medium. The organic-MSW portion is digested in the polar acidic organic medium such as phenol at conditions of 500-850.degree. F. temperature, 300-2000 psig pressure and 5-100 minutes residence time. The digested organic material is then fractionated to produce gas, a light liquid boiling below about 170.degree. C., the polar acidic organic liquid medium such as phenol, boiling between 170 and 220.degree. C., and a liquid slurry boiling above about 220.degree. C. and including a powder material melting above about 400.degree. C. The recovered acidic organic liquid fraction is preferably recycled back to the density separation and/or digesting steps for further use in the process. The liquid slurry fraction product having heating value of 9,000-16,000 Btu/lb. can be utilized as a clean fuel for combustion such as in steam boilers, or it can be catalytically hydrogenated for producing lower boiling hydrocarbon liquid fuels.

This invention pertains to treating municipal solid waste (MSW) and producing clean hydrocarbon liquid fuel products. It pertains particularly to processing sized particulate municipal solid waste materials by density separation in a suitable liquid medium into organic and inorganic portions, digestion of the organic portion, and fractionation of the digested organic material to produce clean hydrocarbon liquid and slurry fuel products having high heating values.
Great quantities of municipal solid waste (MSW) materials are generated and collected regularly in both rural and urban areas of the United States and other developed countries, and require suitable disposal methods, such as by incineration or by being placed in landfills. However, such disposal methods are becoming increasingly expensive and/or environmentally undesirable. Processing of municipal solid waste (MSW) materials to produce solid fuel products suitable for combustion in steam boilers of electric power plants is known, and some such processing plants are in use. However, such solid fuels have serious disadvantages including undesirably high moisture content, high ash contents and low heating value. Other processes for utilizing carbonaceous waste materials as a water slurry to produce gaseous or slurry fuels are disclosed by U.S. Pat. Nos. 5,485,728 and 5,685,153 to Dickinson. Because of the growing economic and environmental needs to recycle and reuse increasing amounts of municipal solid waste (MSW) material more efficiently, improvements and innovations in such waste treatment processes are needed and have been sought.

Treating municipal solid waste for producing hydrocarbon fuel products