A semiconductor device, which can use silicon-germanium for a source/drain extension of pMOS, form a silicide layer on the source/drain, and realize a high-speed operation, is provided by comprising a gate electrode formed in a first conductive type region of a semiconductor substrate via an insulator, a first sidewall formed on a side face of the gate electrode, a second sidewall formed on a side face of the first sidewall, a semiconductor layer formed below the second sidewall, including a first impurity layer of a second conductive type and containing germanium, a second impurity layer formed in a region outside the second sidewall and containing impurities of the second conductive type with a higher concentration than those in the first impurity layer, and a silicide layer formed on the second impurity layer.

1. Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method, and more particularly, it relates to a semiconductor device which uses silicon germanium and its manufacturing method.
2. Description of the Related Art
Miniaturization of a semiconductor device has been accompanied by attention paid to a strained silicon device to achieve a higher speed operation in a metal oxide semiconductor (MOS) device. In a complementally MOS field effect transistor (CMOSFET) formed on silicon, since carrier (i.e., hole) mobility in a channel region of p channel MOSFET (pMOS) is lower than carrier (i.e., electron) mobility in a channel region of an n channel MOSFET (nMOS), pMOS operating in a higher speed is desired to be achieved. In the pMOS, it is known that the carrier (i.e., hole) mobility is enhanced by applying compressive stress to the channel region.
There is known a method of enhancing carrier (i.e., hole) mobility by applying compressive stress to the channel region by using a semiconductor having larger atomic radius than that of silicon, such as germanium or silicon germanium (SiGe), for a source/drain and/or source/drain extension of a silicon pMOS device (see, e.g., Jpn. Pat. Appln. KOKAI Publication No. 8-186257).
Additionally, a method of efficiently forming an SiGe layer on a drain extension and/or a drain is disclosed by P. R. Childambaram et al., in 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 48-49. According to this method, a shallow trench is formed in a silicon substrate on which a SiGe layer is selectively formed by epitaxial growth, then the drain extension and/or the drain are formed therein. Further, a silicide layer (e.g., nickel silicide layer (NiSi)) is formed on the drain of the SiGe layer.
However, if germanium is contained in the source/drain on which the silicide layer is formed, a problem of a deposition failure such as agglomeration of silicide metal (e.g., nickel) and/or peeling off of the silicide film or the like occurs during the formation of the silicide layer on the source/drain.
To solve the problem, an attempt has been made to prevent the deposition failure by epitaxially growing a silicon film on the source/drain made of SiGe, and then forming the silicide layer thereon. However, if a portion of the silicon film is not sufficiently thick, there is a possibility to cause segregation of a silicide metal (e.g., Ni) due to contacting the silicide layer with the SiGe layer.

Semiconductor device and its manufacturing method


The method executes the application and if there are no errors from the execution of the application, the method ends. If errors exist, the errors are collected from the execution of the application in an error report. Labeled application paths are created by adding a unique label to individual application paths where the application paths are individual loops and individual functions in the application. An analysis is created of the labeled application paths by executing the application with the labeled paths, reviewing the error report for data related to the labels and if an error is sufficiently related to application paths with labels, storing the path that created the errors in a report. If an error is not sufficient related to the application path with labels, the method is repeated by the creating the analysis again by substituting additional application paths for the application paths.

This Background is intended to provide the basic context of this patent application and it is not intended to describe a specific problem to be solved.
Commercial software ships with undetected bugs despite the combined best efforts of programmers, sophisticated program analysis tools that detect program errors, and extensive testing. When run with certain inputs, these undetected software errors cause crashes that are disruptive at best, and cost money and lives at worst. To fix the problem, a programmer often has to painstakingly try and work backwards from the crash to isolate and debug the root cause of the error. This process is tedious, error-prone, and involves guesswork as typically the only information available is the stack trace and register values at the point where the program crashed.
Statistical debugging aims to streamline and automate the process of isolating the bug responsible for the program crash. It achieves this goal by collecting information about program execution from both successful and failing runs of a program and applying statistical techniques to pinpoint the likely cause of the software crash.

Statistical debugging using paths and adaptive profiling


A working vehicle includes: an air cleaner provided with a vacuator; a planar portion located below the air cleaner; an emission receiver provided to the planar portion at a position right under the vacuator, the emission receiver being recessed downward while having an upper opening, the emission receiver including a bottom surface; and a discharge channel having a base end that is in communication with the emission receiver through a communication opening and a distal end that is opened to an outside of the working vehicle through a discharge port, the discharge channel having an inclined surface inclined downward from the communication opening toward discharge port.

It is typically known that an air cleaner for intake air for an engine, which is attached to a working vehicle such as a tractor and a hydraulic excavator, centrifugally separates dust or the like sucked with outer air to prevent adhesion of the dust to a filter element, and discharges the dust, which is collected in a bottom portion of a casing, from the bottom portion through a vacuator (see, for instance, Patent Literatures 1 and 2).
The air cleaner is housed in an engine compartment along with the engine. The dust from the vacuator of the air cleaner is discharged from the engine compartment through an inclined or pipe-shaped guide member provided in the engine compartment.
In some working vehicles, the air cleaner is attached outside the engine compartment due to limitations of an installation space in the engine compartment. In this case, dust from the vacuator is directly discharged outside as long as no obstacle is present below the air cleaner.


Circuits and methods to provide a digital clock signal, which can be instantly halted without glitches and then resumes under control of an asynchronous suspend signal with whole width clock pulses has been achieved. The circuit suspends the clock output in either a high or a low state, instantaneously with the suspend signal. There is no restriction on either the suspend pulse width or position in relation to the input clock. The asynchronous logic implementation is using standard cell logic gates. The circuit functionality is not dependent on the manufacturing technology, i.e. CMOS, bipolar, BI-CMOS, GaAs, etc. implementations are all valid.

(1) Field of the Invention
This invention relates generally to the field of digital clock circuits and relates more specifically to a clock circuit, which can be instantly suspended and then resumed again with whole width clock pulses.
(2) Description of the Prior Art
Especially in applications as charge pumps or memory cells oscillators are used to provide clock signals. It is often required to suspend and then to resume the operation of such a clock. The challenge of the designers of such circuits is to allow a digital clock signal to be instantly halted without glitches, either in the high or low state, and then resume under control of an asynchronous "suspend" signal.
A glitch is defined as a high/low period that has not the same "width" as an input clock high/low period.
For example, a use for this would be a clock for a charge pump, which has to be instantly "suspended" and then "resumed" with whole width clock pulses.
There are patents or patent publications dealing with clock circuits, which can be suspended and then resumed, but they stop the output clock in a fixed state only (for example always low) after the suspend signal has occurred:
U.S. Patent (U.S. Pat. No. 5,808,486 to Smiley) proposes a clock enabling circuit that generates an output clock signal such that when the enable output signal changes to a logical false, the output clock signal returns to its steady-state value in a manner that does not produce any glitches, and preserves the duty cycle of the input clock. The circuit comprises a first D flip-flop that is positive-edge triggered, a second D flip-flop that is negative-edge triggered, and a two-input AND gate. The first flip-flop has the D input connected to a constant positive voltage, the positive-edge triggered clock input connected to the input clock signal, the Q output connected to the AND gate, and the Q-complement output connected to the asynchronous reset of the second flip-flop. The second flip-flop has the D input connected to the enable output signal, the negative-edge triggered clock input connected to the input clock signal, the Q output connected to the asynchronous reset of the first flip-flop, and the Q-complement output connected to the AND gate. The output of the AND gate is the output clock signal.
U.S. Patent Application Publication (US 2007/0152719 to Wu et al.) discloses a clock switching circuit, which comprises: a clock generator, receiving two different clock signals; a logic gate, coupled to an enable-signal generator and an output-clock generator, wherein during clock switching, the logic gate turns off output clock according to the signal edges of those two clock signals to avoid the problems of clock glitch and timing insufficiency, and the logic gate will not restore clock output until an appropriate timing occurs.
(U.S. Pat. No. 7,295,044 to Bucossi et al.) proposes a digital clock generation circuit (and a method for operating the same). The digital clock generation circuit includes a first, a second, a third differential comparator circuits. The first differential comparator circuit receives the positive differential clock signal and a reference voltage, and generates a first output signal. The second differential comparator circuit receives the positive and negative differential clock signal, and generates a second output signal. The third differential comparator circuit receives the reference voltage and the negative differential clock signal, and generates a third output signal. A high-high detecting circuit receives the first output signal, and the third output signal, and generates an Enable signal. The digital clock generation circuit further includes a latch circuit which receives the second output signal, and the Enable signal and generates a digital clock signal. The latch circuit comprises a latch with glitch or noise immunity.
(U.S. Pat. No. 6,021,501 to Shay) discloses a power management system. The system includes an oscillator interface for use in a power management system, a power recycle circuit for use in a power management system, a pad clock and self test for use in a power management system, a clock enable circuit for use in a power management system, a power level detect circuit for use in a power management system, an internal source clock generation circuit for use in a power management system, and a power-save mode change detection circuit for use in a power management system. The oscillator interface includes an circuit for interfacing with an external oscillator used as a source of oscillations. A clock stabilization filter masks out spurious crystal frequencies in the oscillations during start-up of the power management system following an enabling of a feedback loop. The clock stabilization filter has circuitry which provides that the oscillations will start with a rising transition after filtering. A bypassing circuit enables the clock stabilization filter when the external oscillator is a crystal oscillator and for bypassing the clock stabilization filter when the external oscillator is a can oscillator. A masking circuit masks the oscillations from the rest of the power management system. The masking circuit has circuitry which disables the clock masking after a falling edge of the oscillations and stats back up with a rising transition of the oscillations.

Glitch-free clock suspend and resume circuit


Disclosed herein is a method of determining the nature of a fault in a radiotherapy device comprising a linear accelerator. The radiotherapy device is configured to provide therapeutic radiation to a patient. The radiotherapy device comprises a vacuum tube comprising an electron gun, a waveguide configured to accelerate electrons emitted by the electron gun toward a target to produce said radiation, and a flight tube. The electron gun is located at a first end of the vacuum tube and the flight tube is located at a second end of the vacuum tube. The radiotherapy device further comprises a first and a second sensor. The first sensor is configured to provide signals indicative of pressure at a first region inside the vacuum tube and the second sensor is configured to provide signals indicative of pressure at a second region inside the vacuum tube. The first region is closer to the first end of the vacuum tube than the second region is. The method comprises processing a first value derived from signals from the first sensor and a second value derived from signals from the second sensor. The first value is indicative of pressure at the first region inside the vacuum tube, and the second value is indicative of pressure at the second region inside the vacuum tube. Processing the first and second value comprises comparing the first value with a first threshold and comparing the second value with a second threshold; and, based on the processing of the signals, determining that the nature of the fault is associated with the flight tube.

Radiotherapy devices are an important tool in modern cancer treatment. Radiotherapy devices are large, complex machines, with many moving parts and inter-operating mechanisms. Despite precision engineering and rigorous testing, some component parts of a radiotherapy machines may start to degrade over the lifetime of the machine. This can sometimes lead to sub-optimal operation and even the occasional safety override.
If at any point during treatment a radiotherapy device starts to function outside of its normal operating parameters, a safety override or "interrupt" occurs, whereby the machine stops delivering radiation to ensure patient safety. Such an event is inconvenient, as it adds time to the treatment, and in some cases means the treatment session must finish prematurely. Unplanned equipment downtime can disrupt planned treatment schedules, and may be expensive for the owner, be it due to loss of revenue, servicing and repair costs, or both.
It has been surmised that, as with other industries, predictive maintenance and/or remote diagnostic techniques could be applied to radiotherapy machines. However, given the complexity of the machines and the sheer volume of data which may be gathered during operation, it is difficult to know how to analyse any available data to inform the predictive maintenance techniques. For example, while particular data patterns may be indicative of a particular fault, identifying the link between particular data patterns and the particular fault is often non-intuitive even for experienced service engineers. Even when a problematic machine is identified, trying to ascertain the nature of the fault is very difficult given the abundance of data and the complex interrelationships between the various components of the machine. In other words, even if a wealth of data from a radiotherapy device is available, successfully determining the nature of a fault is not a trivial matter.
The present invention seeks to address these and other disadvantages encountered in the prior art by providing a method of identifying, preferably remotely, the nature of a fault in a radiotherapy device, for example a device which is performing sub-optimally.

Method for use with a radiotherapy device


The power supply includes a transformer for generating a first output voltage by a first secondary winding, and a superimposing voltage by a second secondary winding, and a driver. Furthermore, the circuit includes first and second rectifying and smoothing circuits for respectively rectifying and smoothing the first output voltage and superimposing voltage, and an adder for adding the rectified and smoothed superimposing voltage on the rectified and smoothed first output voltage to output a second output voltage. The first and second output voltages are fed back respectively by DC coupling, the fed-back first and second output voltages are respectively adjusted by first and second feedback factors, and the adjusted feedback components are combined and amplified to be applied to the driver for PWM-control.

1. Field of the Invention
The present invention relates to a power supply apparatus and a printing apparatus. Particularly, the present invention relates to a power supply apparatus and a printing apparatus which prints an image on a print medium using an inkjet printhead, and using the power supply apparatus.
2. Description of the Related Art
Inkjet printers as computer peripheral devices have developed to multi-function printers including scanner and copy functions, and also a FAX function in recent years, and have higher degrees of penetration into the market year by year due to their higher cost performance ratios.
In general, a switching power supply is used as a power supply of an inkjet printer. A conventional dropper type power supply, which operates at a commercial frequency (50/60 Hz), is falling out of use since it is inferior in terms of power conversion efficiency, heat generation, and the like.
Switching power supplies are classified into some types based on their switching methods, and a flyback method is most popularly used in terms of its simple circuit arrangement and cost. Recently, many control ICs exclusively used for such flyback method have been provided from respective manufacturers, and a circuit having high reliability can be designed relatively easily.
FIG. 8 is a circuit diagram showing an example of a conventional switching power supply using the flyback method. In this example, an IC 1 is a commercially available PWM (Pulse Width Modulation) control IC, and implements feedback control of a current mode. An outline of the operation of the circuit shown in FIG. 8 will be described below.
An input voltage of a commercial frequency of 50 Hz or 60 Hz is rectified by a bridge diode BD1, and is then smoothed by an electrolytic capacitor C1 to generate a DC voltage Vin(DC). This DC voltage Vin(DC) is about 140 V in Japan, or is about 320 V in a 230-V region in Europe and the like. This DC voltage Vin(DC) is supplied to a transformer T1, and undergoes switching control by a transistor Q1. As a result, an energy accumulated on a primary side winding 11 of the transformer T1 is transferred to a secondary side winding 12, thereby generating a DC output voltage Vo.
More specifically, in the flyback method, an energy is accumulated on the primary side winding 11 (n1: the number of windings) of the transformer during a turn-on period of the transistor Q1 in FIG. 8, and the accumulated energy is transferred to the secondary side winding 12 (n2: the number of windings) during an off period of the transistor Q1. The energy transferred to the secondary side winding 12 in this way is rectified and smoothed by a diode D2 and electrolyte capacitor C4 to generate the DC output voltage Vo. The output voltage Vo is voltage-divided by resistors R6 and R7, and a divided voltage (a voltage of a node Vref1) is input to a reference terminal (REF) of a constant voltage regulator, that is, a so-called shunt regulator IC 3. FIGS. 15A and 15B are explanatory circuit diagrams of the shunt regulator IC 3. The shunt regulator IC 3 is one kind of so-called error amplifiers. In the example of FIG. 8, a cathode (K) is connected to a photocoupler IC 2, and an anode (A) is connected to ground. Therefore, an anode voltage Va is 0 V. The shunt regulator IC 3 has an error amplifier (comparator) 151 and a fixed reference voltage circuit 152 arranged in the regulator. The shunt regulator IC 3 compares a voltage of the node Vref1 input to the reference terminal (REF) with an output voltage of the fixed reference voltage circuit 152, and outputs a voltage Vk. In this example, the fixed reference voltage circuit generates 2.5 V. The cathode voltage Vk as an output voltage of the regulator IC 3 is controlled, so that the reference voltage Vref1 input to the reference terminal (REF) of the IC 3 always becomes DC 2.5 V, thus achieving feedback control. Please refer to specialized books and the like for the detailed operation of the shunt regulator since it is well known in this art, and a description thereof will not be given. Note that symbols R1, R2, R3 and R5 in FIG. 8 are resisters, C2 is another electrolytic capacitor.
For example, when the output voltage Vo rises, and the input voltage Vref1 of the shunt regulator IC 3 consequently rises, the output Vk of the shunt regulator IC 3 drops conversely. As a result, a current which flows through a resistor R9 and an LED 15 of the photocoupler IC 2 increases. Then, a collector current which flows through a phototransistor 16 of the photocoupler IC 2 increases, and a potential of a feedback terminal FB of the control IC 1 drops. Then, finally, a pulse width, in other words, an ON duty of a PWM signal output from a DRV terminal of the control IC 1 drops, and a turn-on time of the transistor Q1 is consequently shortened (conversely, a turn-off time is prolonged). As a result, an energy accumulated on the primary side winding 11 of the transformer decreases, that to be transferred to the secondary side winding 12 decreases accordingly, and the output voltage Vo drops finally.
In this way, when the output voltage Vo rises, the feedback control effects to cancel it. Conversely, when the output voltage Vo drops, the feedback control effects to raise that voltage, thereby obtaining the stable DC output voltage Vo. More specifically, a circuit bounded by a broken line 14 in FIG. 8 is a control circuit which is responsible for gain adjustment and phase adjustment required for such feedback control, and functions to stably operate the entire system. The control circuit 14 has an input node 14in and output node 14out. More specifically, a resistor R8 and capacitor C5 in the broken line 14 serve as such gain and phase adjustment parameters. Note that hereinafter, the circuit portion bounded by the broken line 14 will be referred to as an error amplifier.
The description will be further continued with reference to FIG. 8. The transformer T1 includes an auxiliary winding 13, which is used to generate a power supply voltage Vcc for the control IC 1. More specifically, a voltage generated by the auxiliary winding 13 is rectified and smoothed by a diode D1 and electrolyte capacitor C3, and is further stepped down by a transistor Q2 and Zener diode ZD1, thus generating the power supply voltage Vcc of the control IC 1. In the example of FIG. 8, Vcc=15 V, and hence, the Zener diode ZD1 also has a 15-V specification. Note that the control IC 1 is connected to the transistor Q1 via a resistor R4, and has a CS terminal required to detect a current flowing through the transistor Q1 and an HV terminal required to detect a voltage Vin (DC).
FIG. 9 is a block diagram showing an outline of the feedback control of the switching power supply shown in FIG. 8.
As shown in FIG. 9, a PWM control unit 80 including a dedicated IC and the like normally supplies a PWM control signal 81 to a driver 82 including a switching element (Q1), and the driver 82 drives a transformer 83. As a result, an energy is transferred to the output side of the transformer 83, and an output voltage Vo1 is generated via a rectifying and smoothing circuit 84 in the example shown in FIG. 8.
A framework of the feedback control will be described below with reference to FIG. 8 again. A voltage variation of the output voltage Vo1 is detected as a feedback current If1(dc). In the circuit shown in FIG. 8, the current If1(dc) is given by:If1(dc)=(Vo1−Vref)/R6  (1)where Vref is a reference voltage of the reference terminal (REF) of the shunt regulator IC 3, and is, for example, DC 2.5 V. This feedback current If1(dc) flows into the reference node Vref1. On the other hand, a current Iref1 which flows out from the node Vref1 is given by:Iref1=Vref/R7  (2)
Then, since the entire system is controlled so that If1(dc) and Iref1 become equal to each other, equation (3) is obtained from equations (1) and (2). That is, we have:Vo1=(R6+R7)/R7*Vref  (3)In this way, the output voltage Vo1 is controlled based on equation (3).
Referring back to FIG. 9, the description will be continued. A feedback factor α1 corresponds to a coefficient when the output Vo1 is considered as a variable in equation (1) which defines the feedback current If1(dc), and is 1/R6. A degree D(α1) at which the feedback factor α1 contributes to the feedback control is 1.0. This is because the circuit shown in FIG. 8 includes only one output as a feedback control target. By contrast, as will be described later, in case of a power supply having two outputs, since contributions of feedback factors are weighted between the two outputs, degrees D(αn) assume values which satisfy 0<D(αn)<1 (n=1, 2). Referring back to FIG. 9, the feedback signal weighted by a weighting circuit 86 is input to an error amplifier 89, and its output is provided to the PWM control unit 80, thus executing the aforementioned PWM control.
Details of the operation of the switching power supply shown in FIG. 8 will be described below with reference to waveforms of the respective units.
FIG. 10 is a signal waveform chart showing a drain-source voltage Vds and drain current Id of the transistor Q1, a current which flows through the secondary side winding 12 of the transformer, that is, a current Is which flows through the rectifier diode D2, and an output current Io in the switching power supply.
Note that FIG. 10 shows, as a representative example, waveforms of a current-discontinuous mode of the flyback method. Note that as is apparent to an ordinary skilled person in the art, when a load power increases, and a PWM ON duty becomes equal to or higher than 50%, the current-discontinuous mode set so far transits to a current-continuous mode. However, such mode transition is not directly related to the gist of the present invention, and a description thereof will not be given.
In FIG. 10, a basic cycle T of a switching operation is, for example, 16.7 μsec when the operation frequency is 60 kHz. This cycle includes a period Ton in which the transistor Q1 is turned on, and a period Toff in which the transistor Q1 is turned off. Furthermore, the period Toff includes a period Toff1 in which an energy is discharged from the secondary side winding 12 of the transformer via the diode D2 and electrolyte capacitor C4, and a standby period Toff2 after discharging is complete and until the transistor Q1 is turned on again. In the period Toff2, as can be seen from FIG. 10, the drain-source voltage of the transistor Q1 resonates. This is a phenomenon generally caused by a resonance system formed by an inductance value L1 of the primary side winding 11 of the transformer, a leakage inductance value Lleak, and a total capacitance value Clump between the drain and source of the transistor Q1. However, since this phenomenon is not directly related to the gist of the present invention, a detailed description thereof will not be given.
In the current-discontinuous mode shown in FIG. 10, an energy is accumulated on the primary side winding 11 of the transformer during the period Ton. This energy is given by:P1=½*L1*Ip2  (4)where L1 is an inductance value of the primary side winding 11, and Ip is a peak value of a current which flows through the primary side winding 11 during the period Ton, as shown in FIG. 10.
Next, an energy generated by the transformer per unit time is described by:P2=½*L1*Ip2*f*η  (5)where f is a switching frequency, and η indicates energy conversion efficiency of the transformer. A product of the energy amount P1 generated on the primary side of the transformer and the efficiency η is an energy amount which is actually transferred to the secondary side of the transformer. For example, f is 60 kHz, 100 kHz, or the like, and η is 0.95 or the like.
That is, about 95% of the energy generated on the primary side of the transformer is transferred to the secondary side, and the remaining 5% is dissipated as heat by a core and the windings of the transformer. Note that for reference, the total efficiency of a switching power supply of the flyback method of several ten W output is about 85%. In addition to the aforementioned dissipation by the transformer alone, that by an EMI filter circuit (not shown) of an input unit, that by the switching element Q1, that by the rectifier D2 in the secondary side circuit, that by resistors in the circuit shown in FIG. 8, and the like are included.
The description will be continued with reference to FIG. 10 again. In equation (4), the energy P1 accumulated during the period Ton is transferred to the secondary side winding 12 of the transformer during the period Toff1. This switching control method will be referred to as a flyback method hereinafter. By contrast, a method in which an energy is transferred from the primary side to the secondary side of the transformer during the period Ton of the transistor Q1 is available, and will be referred to as a forward method hereinafter. Please refer to specialized books for details of the forward method.
In the circuit shown in FIG. 8, one output Vo (for example, DC 24 V) is generated as an output voltage. However, in an inkjet printer, as shown in, for example, FIG. 11, the output voltage Vo is supplied to a printhead 3 and motor driver 44, and is also supplied to a DC-DC converter 45 which is used to generate several types of logic circuit voltages.
FIG. 11 is a block diagram showing the arrangement of a power supply unit of the inkjet printer.
These logic circuit voltages include, for example, DC 1.5 V used as voltages of a CPU and ASIC core, DC 3.3 V supplied to an ASIC input/output unit (I/O) and memory device, DC 5V supplied to sensors and a display unit, and the like. Note that as shown in FIG. 11, motors connected to the motor driver 44 include a conveyance motor M2, and a carriage motor M1 which drives a carriage which mounts the printhead 3 and is scanned. Furthermore, in a recent multi-function printer (MFP), the motors include a scanner (SC) motor M3 used to scan a scanner unit and the like. In order to meet a recent power-saving requirement, an energy-saving control signal (Esave) required to guide a power supply circuit 42 to intermittent oscillations in a standby state or sleep state of a printer is normally included.
In the arrangement example shown in FIG. 11, both of a driving voltage of the printhead 3 and a voltage of the motor driver 44 are indicated by one output voltage DC 24 V. However, due to recent high-speed trends of printers, a case in which higher voltages DC 27 V, DC 32V, and the like are used as a motor driving voltage is increasing. In such case, two outputs, that is, a printhead driving voltage (DC 24 V) and motor driving voltage (for example, DC 32 V) are generated.
FIG. 12 is a circuit diagram showing an example of a switching power supply having two output voltages. The same symbols and the same reference numerals in FIG. 12 denote components common to FIG. 8.
A major difference from the circuit shown in FIG. 8 lies in that two types of output voltages Vo1 and Vo2 are generated. For example, the output Vo1 is DC 24 V corresponding to a head driving voltage, and the output Vo2 is DC 32 V corresponding to a motor driving voltage. In order to generate these two types of output voltages, two windings 12 (n2: the number of windings) and 12a (n3: the number of windings) are provided to the secondary side of a transformer T9, so that the output voltage Vo1 is generated from the winding 12 (n2: the number of windings), and the output voltage Vo2 is generated from the winding 12a (n3: the number of windings). Note that symbols Is1, Is2 represent the output current from the windings 12, 12a, respectively. As is apparent to an ordinary skilled person in this art, the windings 12 and 12a may be configured via an intermediate tap 51 (the windings 12 and 12a share a specific pin terminal of the transformer), or the respective windings may be independently wound.
As a rectifying and smoothing circuit from the added winding 12a, a diode D51 and electrolyte capacitor C51 are arranged. To the input terminal (REF) of the shunt regulator IC 3, a feedback from the output voltage Vo2 is input in addition to that from the output voltage Vo1. In this case, the feedback from the output voltage Vo1 is attained by DC coupling via the resistor R6, but that from the output voltage Vo2 is attained by AC coupling by means of a resistor R51 and capacitor C52 (a broken line 52 in FIG. 12).
This is because since the output voltage Vo1 is used as a driving voltage of the printhead, as described above, very high precision control is required, while since the output voltage Vo2 is a voltage used to drive a DC motor and the like, variations to some extent are tolerated. Therefore, as for the output voltage Vo2, the feedback by means of the AC coupling is used so as to avoid an extreme voltage drop at a timing at which a large current is instantaneously supplied (for example, a motor activation timing). In other words, in the example of the circuit shown in FIG. 12, the feedback of the output voltage Vo1 is always prioritized. On the other hand, as for the output voltage Vo2, feedback control according to a feedback factor decided by a CR time constant of the resistor R51 and capacitor C52 is implemented only for instantaneously large load variations.
Note that Japanese Patent Laid-Open No. 6-178537 is available as an example of a related art associated with feedback control of a switching power supply which generates two output voltages.
Japanese Patent Laid-Open No. 6-178537 discloses a method of selecting an output voltage used as a feedback control target in accordance with respective load currents of a plurality of output voltages. According to Japanese Patent Laid-Open No. 6-178537, an output voltage with a larger load current is selected to execute feedback control.
However, the conventional circuit shown in FIG. 12 suffers the following problems. That is, since the feedback of the output voltage Vo2 is attained by the AC coupling, even though a printhead driving operation is normally set in a quiescent period during, for example, a high-speed print medium conveyance execution period in a print operation sequence, the feedback of the printhead voltage Vo1 is unwantedly prioritized. For this reason, the motor driving voltage Vo2 largely varies consequently, thus adversely influencing motor servo-control. Thus, in practice, high-speed control of motors is implemented within a range in which stability of such servo-control is maintained in the conventional circuit.
On the other hand, in the circuit shown in FIG. 12, the feedback of the output Vo2 corresponding to the motor driving voltage may also be attained by DC coupling as in the output Vo1. In this case, a relative feedback factor ratio between the respective outputs has to be decided, and when a large ratio is set for the output Vo1 corresponding to the printhead voltage, the stability of the output Vo1 is maintained. However, at a motor driving or stop timing, variations caused by overshooting or undershooting of the motor driving voltage Vo2 become larger than those in the case of the AC coupling. Conversely, a large feedback factor is set for the output Vo2, variations of the printhead voltage Vo1 increase, thus seriously deteriorating image quality.
FIG. 13 is a signal waveform chart showing voltage and current waveforms of the respective units in the 2-output voltage switching power supply shown in FIG. 12.
For example, at an activation timing (t=t1) of the conveyance motor M2, when a load current Io2 of the output Vo2 corresponding to the motor driving voltage is reduced by a peak current Ip1, the output Vo2 drops (undershoots) to Vp21 at that instance. A feedback current If2(ac) shown in FIG. 13 flows out from the node Vref1 toward the CR circuit 52, and the potential of the node Vref1 drops by that current flow-out amount.
As a result, the output voltage Vk of the shunt regulator IC 3 rises, and the ON duty of the PWM control by the control IC 1 increases to increase an energy generated by the transformer T9, thus effecting the feedback control that blocks the output voltage Vo2 from dropping. However, in the circuit shown in FIG. 12, even after the output current Io2 is stabilized to Ip2 at time t=t2, the output voltage Vo2 unwantedly drops by ΔVf compared to a level Vp20 before time t=t1, thus becoming a level Vp22.
This is because, as can be seen from the arrangement shown in FIG. 12, during a stable period of the output voltage Vo2, the feedback of that output does not function due to the AC coupling, and only the feedback of the output Vo1 is virtually effective. In other words, since the feedback of the output Vo2 is uncontrolled in terms of DC during a period T2, it exhibits a voltage drop tendency as its load current increases. For example, during a high-speed print medium conveyance period by the conveyance motor M2 shown in FIG. 11, the voltage drop ΔVf of the motor driving voltage Vo2 reaches about 3 to 4 V.
The description will be continued with reference to FIG. 13 again. At time t=t3, the driving operation of the conveyance motor M2 is stopped, and the current Io2 returns to zero. The output Vo2 instantaneously rises (overshoots) to Vp23 accordingly, and the feedback current If2(ac) reversely flows in from the CR circuit 52 to the node Vref1. As a result, the potential of the node Vref1 rises, the output voltage Vk of the shunt regulator IC 3 drops, and the ON duty of the PWM control by the control IC 1 decreases, thus reducing an energy generated by the transformer T9. In this manner, the feedback control that blocks the output voltage Vo2 from rising is effected.
Note that as shown in FIG. 13, the other output Vo1 is influenced by the large variations of the voltage Vo2 at times t=t1 and t3, and changes slightly in directions opposite to the voltage Vo2. That is, at instances of the large variations of the output Vo2, the output current Io1 of the output Vo1 exhibits only moderate changes, as shown in FIG. 13. For this reason, as described above, due to transfer of a large energy from the transformer by the feedback control caused by variations of the output Vo2, the output voltage Vo1 rises slightly at time t=t1, and reaches a Vp11 level, as shown in FIG. 13. Likewise, at time t=t3, the output Vo1 slightly drops to a Vp12 level conversely.
FIG. 14 is a block diagram showing the feedback control arrangement of the 2-output voltage switching power supply shown in FIG. 12. A difference from the 1-output voltage switching power supply described above with reference to FIG. 9 lies in that the transformer 83 has two outputs (83a and 83b), which are generated as the outputs Vo1 and Vo2 via rectifying and smoothing circuits 84a and 84b, respectively, as shown in FIG. 14. Also, respective feedback components from the outputs Vo1 and Vo2 are added by an adder 88 via weighting circuits 86, 87 which respectively weight feedback components by feedback factors α1 and α2, and the addition result is processed by the error amplifier 89 and is finally fed back to the PWM control unit 80. Thus, the driver 82 including the switching element (Q1) undergoes PWM control, thus controlling an energy to be generated by the transformer 83.
Especially, a change of the output voltage Vo1 is reflected to the feedback control via the feedback factor α1, and a change of the output voltage Vo2 is reflected to the feedback control via the feedback factor α2. As will be described later, these feedback factors α1 and α2 correspond to degrees of contribution of the corresponding outputs to the feedback control.
The description will be continued with reference to FIGS. 12 and 14. Since the feedback of the output voltage Vo1 is attained by the DC coupling, the constant feedback current If1(dc) always flows in from an output terminal Vo1 toward a reference terminal Vref1 of the shunt regulator IC 3. The current If1(dc) is given by:If1(dc)=(Vo1−Vref)/R6  (6)where the reference voltage Vref is, for example, DC 2.5 V. On the other hand, since the feedback of the output voltage Vo2 is attained by the AC coupling, the feedback current If2(ac) which flows in from an output terminal Vo2 to the node Vref1 is cut-off to zero by the capacitor C52 during a stable period of the output voltage Vo2. Therefore, a total sum of currents which flow into a node Vref1 in a Vo2 stable period is given by:If1(dc)+If2(ac)≈If1(dc)(∵If2(ac)≈0)  (7)
Therefore, expression (8) is obtained from equation (6) and expression (7). That is, we have:If1(dc)+If2(ac)≈(Vo1−Vref)/R6  (8)
Also, from expression (8), the feedback factors α1 and α2 are calculated, as given by:α1=1/R6,α2=0  (9)This is because when the output voltages Vo1 and Vo2 are considered as variables in expression (8), their coefficients correspond to the feedback factors. However, in practice, the variable Vo2 does not appear in expression (8), and α2 becomes zero.
Next, from equations (9), feedback contributions ratios D(α1) and D(α2) of α1 and α2 are calculated, as given by:
                                                                        D                                                  (                  α1                  )                                            =                                                          α1                /                                  (                                      α1                    +                    α2                                    )                                                                                =                                          1.0                                                          (        10        )                                          D                                (            α2            )                          =        0                            (        11        )
As can be seen from the above description, only the output Vo1 contributes to the feedback during a stable period of the output voltage Vo2 (the period T2 in FIG. 13).
On the other hand, as shown in FIG. 12, the current Iref1 which flows out from the node Vref1 is given by:Iref1=Vref/R7  (12)Since the current which flows into the node Vref1 and that which flows out from that node are controlled to be equal to each other by the operation of the error amplifier 14 including the shunt regulator IC 3, equation (13) holds. That is, we have:If1(dc)+If2(ac)=Vref/R7  (13)In this case, expression (14) is obtained from expression (7). That is, we have:If1(dc)≈Vref/R7  (14)
On the other hand, when the motor driving voltage instantaneously varies like in a period T1 in FIG. 13 (for example, at activation timings of the conveyance motor M2 and carriage motor M1), the output Vo2 is reduced by a voltage which contributes to supplying a large current. For this reason, if the feedback of the output Vo2 is not taken into consideration, the output voltage Vo2 causes a large voltage drop at that instance, and the servo-control of motors may become abnormal. For this reason, since the circuit shown in FIG. 12 adopts the feedback by means of the AC coupling of the output Vo2, the following feedback correction is executed against such instantaneous variations of the output Vo2. That is, letting ΔVp be a voltage variation of the output Vo2, the feedback current If2(ac) from the output Vo2 flows out from the node Vref1 to the CR circuit 52 (see FIG. 12)If2(ac)=−ΔVp/R51*exp(−T/CR)  (15)
In this case, the minus sign in equation (15) means flowing-out of the current from the node Vref1. Also, C of the CR time constant in equation (15) is a value of the capacitor C52, R is that of the resistor R51, and a variable T corresponds to an elapsed time since the motor activation timing, that is, an elapsed time from time t=t1 in FIG. 13. Furthermore, the period T1 of Vref1 shown in FIG. 13 reveals a potential drop state of the node Vref1 by a flow-out amount of the current If2(ac). In FIG. 13, Ifp21 shows a minimum value of the current If2(ac) during a time interval T1, and Ifp 22 shows a maximum value of the current If2 (ac) during a time interval T3. Also, in FIG. 13, a time interval T1 from times t=t1 to t2 is associated with the CR time constant in equation (15).
As described above, during the period T1 in FIG. 13, from equations (6) and (15), a total sum of feedback currents is calculated, as given by:If1(dc)+If2(ac)=(Vo1−Vref)/R6−ΔVp/R51*exp(−T/CR)  (16)From equation (16), respective coefficients of the variables Vo1 and ΔVp, that is, feedback factors are respectively calculated, as given by:α1=1/R6  (17)α2=−1/R51*exp(−t/CR)  (18)
In equation (18), the minus sign of α2 indicates a drop of the output voltage Vo2, and conversely, a plus sign indicates a rise of the output voltage Vo2. Also, as can be seen from equation (18), the feedback factor at time t=0 is larger as the resistor R51 in FIG. 12 decreases.
That is, the current which flows out from the node Vref1 increases with decreasing resistor R51, and a change of the output voltage Vo2 is consequently reflected to the node Vref1 at a high sensitivity, thus transferring the change to the subsequent error amplifier 14. However, when the value of the resistor R51 is set to be too small, the influence of the feedback factor α2 becomes too large, thus causing excessive overshooting or undershooting at a return timing from variations of the output voltage Vo2, and adversely influencing the other output Vo1.
Also, as can be seen from equation (18), the feedback factor of the output Vo2 includes an exponential function. For this reason, for example, when there are a plurality of motors (carriage motor M1, conveyance motor M2, scanner motor M3, and the like) of different activation currents, it is difficult to optimally control all the motors using one type of the CR time constant.
As described above, in the conventional 2-output voltage switching power supply shown in FIG. 12, an optimal feedback factor cannot be selected at the time of instantaneous variations of the motor driving voltage caused at activation timings of the plurality of motors having different activation currents. Furthermore, the feedback factor α2 of the motor driving voltage becomes zero in effect after the motors reach nearly a stabilized condition, thus consequently causing a drop of that output voltage. As a result, in the conventional circuit shown in FIG. 12, the printhead driving voltage can be precisely maintained, while the motor driving voltage unwantedly drops in a high-speed print medium conveyance period or the like. Hence, it is difficult to attain a high-speed throughput.

Power supply apparatus and printing apparatus


Misalignment created during a multiple-patterning process is a serious challenge for critical dimension (CD) control and layout design in continuing integrated-circuit device scaling. A number of post-lithography misalignment correction technologies based on the shadow effect are invented for multi-patterning lithographic applications. When applied to transfer patterns from a top layer to an underneath layer, the subtractive shadow effect in anisotropic plasma etching combined with a hard-mask process, will shift the position of features such that the previously produced misalignment can be corrected. Also, additive shadow effect in a sputtering/evaporation process can be used. Misalignment correction methods allow the semiconductor industry to print sub-32 nm (half-pitch) features using the double-patterning technique with currently existing lithographic tools (e.g., 193-nm DUV scanner), therefore postponing the need of expensive next-generation lithography (NGL). The misalignment correction methods can be applied to existing lithography technologies to print features smaller than their physical resolution limits.

Optical DUV (deep ultraviolet, 193 nm) immersion lithography with NA≈1.3 has the capability of printing half-pitch features down to about 40 nm. The potential next-generation lithography (NGL) technologies include EUV (extreme ultraviolet), maskless, and nano-imprint lithography [1]. However, all these NGL technologies face their own technological challenges and still need a long development time before their applications in high-throughput manufacturing. Recently, double patterning has attracted much industrial interest which prints less dense line/space or contact hole patterns twice on the same wafer to finally obtain dense patterns with double spatial frequency [2]. In principle, a similar multiple-patterning concept can be developed but both need extremely high alignment accuracy. It is a severe challenge to significantly reduce the misalignment budget in a lithographic process to meet the multiple-patterning requirement at 32 nm half pitch and below. Therefore, post-lithography misalignment correction will be a promising alternative technology enabling multiple patterning (including double patterning) for future semiconductor manufacturing. It provides a production-worthy method for the whole semiconductor industry to continue device scaling beyond sub-40 nm generation with no need of NGL technology.
Several post-lithography misalignment correction techniques based on the shadow effect in anisotropic plasma etch or sputtering/evaporation processes are invented which allow us to significantly reduce the misalignment created in a lithographic process. Next, we demonstrate the forming mechanism of misaligned dense line/space patterns during a double-patterning process. Similar misalignment mechanism exists in the multiple-patterning process.
In FIG. 1, the cross-section view of a double-patterning process flow to print misaligned dense line/space and contact hole patterns is shown. Starting with a targeted layer on top of the substrate, semi-dense features are printed on the targeted layer using standard lithographic and dry etching processes (shown in FIG. 1(B)), with their pitch size twice the size of desired pitch as shown in FIG. 1 (E). After that, another resist film is spun on the top and the wafer is exposed again with the same pattern shifted by a distance such that ideally every trench center in the resist will be coincident with the center of corresponding line structure underneath. However, as shown in FIG. 1(C), the trench is not located right at the center of the line (e.g., A≠B) due to an unavoidable misalignment during a lithographic process. Consequently, this misalignment will be transferred to the targeted layer underneath in the following plasma etching process assuming its etching direction is vertical as shown in FIG. 1(D). This results in unequal width of the final dense features (e.g., length C≠D) and brings serious challenges to process yield and circuit design/layout. Similar problem exists in a multiple-patterning process to obtain dense features with their pitch reduced to ⅓, ¼, . . . , of the original size corresponding to the resolution limit of a conventional lithographic tool.
The process flow shown in FIG. 2 is similar to previously described process except that a sacrificial layer is deposited before the second lithographic step. This sacrificial layer finally will be released and can be polished to flatten the surface (e.g., with a CMP process) resulting in an improved lithographic process window. However, if the plasma etching direction is vertical, the misalignment is still transferred to the targeted layer as shown in FIG. 2(F) (e.g., C≠D).
As demonstrated before, if the ions' incident direction is vertical to the substrate surface, the misalignment will be transferred to the targeted layer. Next, we shall describe a so-called shadow effect which occurs in both subtractive anisotropic plasma etching and additive sputtering/evaporation processes, and can be used to correct the misalignment created during a lithographic process. As shown in FIG. 3, we compare two plasma etching processes in which one etching is in vertical direction as shown in FIG. 3(A), and the other etching is tilted by certain angle as shown in FIG. 3(B). The tilted etching can be achieved by either directly tilting the ions' bombarding direction or tilting the wafer surface. Both dash lines drawn in the figure represent the central position of the right-side structure formed in a vertical etching process. When the etching direction is tilted as shown in FIG. 3(B), two effects occur. First, the slope of left side walls of the etched structures becomes more vertical while the opposite happens to the slope of right side walls, which results in asymmetric final structures. Secondly, relative to the dashed line which indicates the center of a final structure produced in the vertical etching, the mass center of the asymmetric structure formed in a tilted etching process moves toward the right side. The shift distance depends on the etching direction as well as the etching selectivity. Even though the etched structures are asymmetric, this asymmetry will not be transferred to the substrate if we can use those structures as a hard mask with high selectivity when etching the underneath substrate.
The shadow effect also occurs in an additive process such as sputtering or evaporation deposition as shown in FIG. 4. First, a dense structure is patterned and etched into the substrate. When the sputtering direction is tilted toward the right side, the step coverage is not conformal as deposition occurs only on the top and left side walls. This effect can also be used to correct misalignment.
The misalignment correction process can vary, depending on whether a sacrificial layer is used between two exposures (e.g., in a double-patterning process) and when the misalignment can be measured. We shall demonstrate the correction processes based on the shadow effect of anisotropic plasma etching without a sacrificial layer first.

Post-lithography misalignment correction with shadow effect for multiple patterning


A clock circuit includes an oscillator for generating a reference frequency signal, and a spread spectrum clock generator cooperating with the oscillator for generating a spread spectrum clock output signal having a fundamental frequency and reduced amplitude EMI spectral components at harmonics of the fundamental frequency. The spread spectrum clock generator preferably includes a clock pulse generator for generating a series of clock pulses, and a spread spectrum modulator for frequency modulating the clock pulse generator to broaden and flatten amplitudes of EMI spectral components which would otherwise be produced by the clock pulse generator. The spread spectrum modulator frequency modulates the clock pulses with specific profiles of frequency deviation versus the period of the profile. Electronic devices including the spread spectrum clock circuit and associated method are also disclosed.

Many electronic devices employ microprocessors or other digital circuits which require one or more clock signals for synchronization. A clock signal permits the precise timing of events in the microprocessor, for example. Typical microprocessors may be supervised or synchronized by a free-running oscillator, such as driven by a crystal, an LC-tuned circuit, or an external clock source. Clocking rates up to and beyond 40 MHz are common in personal computers. The parameters of a clock signal are typically specified for a microprocessor and may include minimum and maximum allowable clock frequencies, tolerances on the high and low voltage levels, maximum rise and fall times on the waveform edges, pulse-width tolerance if the waveform is not a square wave, and the timing relationship between clock phases if two-clock phase signals are needed. (See Electronics Engineers' Handbook, by Fink et al., p. 8-111, 1989.)
Unfortunately, high performance, microprocessor-based devices using leading edge, high speed circuits are particularly susceptible to generating and radiating electromagnetic interference (EMI). The spectral components of the EMI emissions typically have peak amplitudes at harmonics of the fundamental frequency of the clock circuit. Accordingly, many regulatory agencies, such as the FCC in the United States, have established testing procedures and maximum allowable emissions for such products. For example, the Commission Electrotechnique Internationale (Comite International Special Des Perturbations Radioelectriques (C.I.S.P.R.)) has guidelines establishing measurement equipment and techniques for determining compliance with regulations. More particularly, for the frequency band of interest to clock circuits, the measured 6 dB bandwidth is a relatively wide 120 KHz.
In order to comply with such government limits on EMI emissions, costly suppression measures or extensive shielding may be required. Other approaches for reducing EMI include careful routing of signal traces on printed circuit boards to minimize loops and other potentially radiating structures. Unfortunately, such an approach often leads to more expensive multilayer circuit boards with internal ground planes. In addition, greater engineering effort must go into reducing EMI emissions. The difficulties caused by EMI emissions are made worse at higher processor and clock speeds.
Power switching circuits also tend to generate EMI emissions due to the rapid switching of high currents and high voltages. EMI noise reduction in such circuits is generally achieved by suppression of the noise source, isolation of the noise coupling path, and filtering or shielding as reported, for example, in Reduction of Power Supply EMI Emission by Switching Frequency Modulation, Lin et al., Virginia Power Electronics Center the VPEC Tenth Annual Power Electronics Seminar, pp. 129-136, Sep. 20-22, 1992. The article further discloses that it is possible to modify the EMI spectrum of the switching power supply circuit to pass regulatory tests by modulating the switching frequency so that side-bands are created thereby smearing the emission spectrum.
In particular the Lin et al. article discloses a switching frequency of 90 KHz that is frequency modulated with a simple sine wave at 400 Hz with the frequency variation selected to be 15 KHz. Improvement of emissions at 90 KHz was reported, which is important because the fundamental frequency EMI determines the amplitude of a required EMI filter for the switching circuit. The article further discloses that from the EMI point of view, a larger frequency variation may be selected and, since there are side-band harmonic frequencies created by the simple sine wave frequency modulation, it is necessary for the switching circuit that these side-bands do not fall within the audible range.
The regulatory requirements for switching power supply circuits fall within a different regulatory category than clock circuits. In particular, as specified by C.I.S.P.R., such switching circuits are only measured for a relatively small 6 dB bandwidth of 9 KHz. Accordingly, approaches described for compliance with such a regulatory test for such a small bandwidth are not adequate to address the difficulties associated with reducing EMI components for high speed digital circuits operating in the tens of megahertz range. The problem associated with lowering measurable EMI emissions is especially difficult where the measured bandwidth is relatively large, such as 120 KHz as in the C.I.S.P.R. regulations which pertain to emissions as generated at typical clock frequencies.

Spread spectrum clock generator and associated method


A wireless TV system includes a base station including a wireless signal processor to process a predetermined video signal into a wireless signal, and a transmitter to transmit the wireless signal from the wireless signal processor; and a wireless TV comprising a receiver to receive the wireless signal from the transmitter, an LCD displaying a picture based on the wireless signal, a backlight unit to illuminate the LCD, a battery to supply power, an inverter to supply the power from the battery to the backlight unit, and a controller to determine whether a wireless communication state is normal or abnormal based on the received wireless signal and to control the inverter to lower a brightness level of the LCD into a predetermined brightness level when the wireless communication state is abnormal.

1. Field of the Invention
The present invention relates to a wireless television (TV) system, and more particularly, to a wireless TV system and a control method thereof, in which wasteful power consumption is reduced.
2. Description of the Related Art
Recently, use of various wireless appliances has increased as technology has developed and information technology has accelerated. As one of the wireless appliances, a wireless TV system generally comprises a base station processing a broadcast signal received through an antenna or a predetermined video signal received through a predetermined video cable, and outputting a wireless signal; and a wireless TV receiving the wireless signal from the base station, and processing the wireless signal to be displayed on a liquid crystal display (LCD).
In such a wireless TV system, wireless communication is interactively achieved between the base station and the wireless TV. That is, when a user wants to watch TV and selects a broadcast channel while carrying the wireless TV, the base station wirelessly transmits a video signal corresponding to the broadcast channel selected by the wireless TV, and the wireless TV receives the video signal through wireless communication and displays it on the LCD.
In the conventional wireless TV system, the wireless communication between the base station and the wireless TV may not go smoothly, or the base station may not transmit the requested video signal to the wireless TV even though there is no problem in the wireless communication.
However, even if the wireless communication does not go smoothly or even if there is no problem in the wireless communication but the base station does not transmit the requested video signal to the wireless TV, the wireless TV still normally operates to display a picture based on the video signal onto the LCD, thereby wastefully consuming limited power of a battery.

Wireless TV system and control method thereof


The invention relates to a process for the preparation of phosphonium sulfonates, particularly tetraalkylphosphonium fluoroalkylsulfonates, in the presence of amine-type bases.

Tetraalkylphosphonium fluoroalkylsulfonates are known to be prepared by reactions between sulfonyl derivatives and tetraalkylphosphonium halide derivatives in the presence of bases. These compounds are useful as antistatic agents in polymeric compositions, particularly in plastics such as PET (polyethylene terephthalate), PA (polyamide), PC (polycarbonate), polyketone and mixtures of butadiene-acrylonitrile-styrene. For their use as antistatic additives, these compounds are added to polymers either alone or in combination with other additives such as UV absorbers, flame retardants, light stabilizers, antioxidants, etc.
EP1462438 describes the preparation of tetrabutylphosphonium nonafluorobutane-1-sulfonate by combining an aqueous solution of tetrabutylphosphonium halide with an aqueous solution of (C4F9)-sulfonyl-O- M+, where M is a metal, to give a biphasic mixture which is separated and from which the bottom layer is recovered, preferably by solidification.
EP1737814 describes a process for the preparation of tetrabutylphosphonium nonafluorobutane-1-sulfonate which includes combining (C4F9)-sulfonyl-O- M+, where M is lithium or sodium, with tetrabutylphosphonium-halide in an aqueous solution.
EP182574 describes a process for the preparation of tetrabutylphosphonium nonafluorobutane-1-sulfonate which includes combining, in an aqueous solution, (C4F9)-sulfonyl-F with either tetrabutylphosphonium-OH or tetrabutylphosphonium-halide and a base selected from sodium hydroxide and lithium hydroxide.
WO2008108983 describes the reaction between potassium 1,1,2,3,3,3-esafluoropropanesulfonate and tetra-n-butylphosphonium bromide.
The above-mentioned procedures all involve the use of metals from which the desired compounds are difficult to be separated, thereby being very frequently contaminated therewith. The presence of metal traces in the tetraalkylphosphonium fluoroalkylsulfonate compounds leads to serious drawbacks. In fact, for their use as antistatic agents, the above-mentioned compounds should be highly purified because the presence of even a minimum of metal impurities leads to serious consequences in the preparation of plastic materials to which such compounds are added.

Process for the preparation of phosphonium sulfonates


A memory module system may include a serial presence detect (SPD) memory and a memory controller. The SPD memory may store first SPD data and second SPD data of a memory module. The SPD memory may be partitioned into at least two regions that may operate as multiple SPD ROMs. The memory controller may boot the memory module system based on a comparison between the first SPD data and the second SPD data when an initialization signal is input to the memory module system. The memory module system may be booted stably and may prevent system breakdowns.

1. Field
The example embodiments relate to booting a system, and more particularly to a memory module system using a partitioned serial presence detect (SPD) memory and a method of booting the memory module system.
2. Description of Related Art
Many systems may include a small software program for initially booting a system, basically checking a system, and loading application programs before other programs like, for example, an operating system (OS) operate. Such a small software program may be stored in a read-only memory (ROM) type device. The device may be one of a variety of ROMs. These ROMs may be referred to as SPD ROMs.
FIG. 1 is a block diagram illustrating a conventional SPD ROM.
Referring to FIG. 1, the software program may exist in a used region 110. The conventional SPD ROM 100 may be only partially used since a software program stored in the conventional SPD ROM 100 may be small in size. The software program stored in the conventional SPD ROM 100 may not need large changes. However, the conventional SPD ROM 100 may be changed so as to modify the software program when a load function or a check function of an initial application program is changed. Also, the conventional SPD ROM 100 may need to be changed to recover the software program when an application program of a system (not shown) including the conventional SPD ROM 100 is corrupted. An error in an application program may corrupt a conventional SPD ROM 100 which may cause the software program to fail.
The software program in the conventional SPD ROM 100 may be changed by changing the hardware of the conventional SPD ROM 100 directly or by modifying the software program. However, changing the software program these ways may take a long time.
FIG. 2 is a flow chart illustrating a method of booting a system using a conventional SPD ROM.
Referring to FIG. 2, an initialization signal may be input to the system (S210), and SPD data may be read from the conventional SPD ROM (S220). If the SPD data is normal (S230: YES), booting the system may be finished (S260). If the SPD data is abnormal (S230: NO), booting the system may be performed by using an external memory (S250) or the system may break down (S270). That is, the system may break down or use the external memory when the SPD data is abnormal, so booting the system with a conventional SPD ROM may be unstable.

Memory module system using a partitioned serial presence detect memory