A filter insert (40) includes filters (43) having electrodes (48, 60) and contacts (54, 64) axially, mechanically engaging contact post members (28) of a connector (20) to provide filtering extending between signal and ground conductors in the form of connector contacts to filter unwanted signal frequencies. An alternative insert (68) includes filters (69) having slotted beam elements (78) that engage post members (28) from a side thereof with a common ground bus (90) tying the filters to ground. A further alternative insert (108) provides contact elements (116) connecting filters (103) to signal and ground conductors in the form of the wires (104) of a cable (102). The contact elements (54, 64, 78, 116) of the inserts (40, 68, 108) bite into the signal and ground conductors or contacts of a connector or a cable to provide a solderless interconnection of the insert. Filters, including dielectric elements (56, 86, 126,) and inductive elements (44) are contemplated to provide C, LC and pi-filters.

Proliferation of electronic devices utilized to transmit, receive, and manipulate date has led to problems caused by electromagnetic interference (EMI) wherein radiation from voltages induced by the proximity of signals interferes with the transmission and reception of data signals, typically in the form of digital pulses. Additionally, a need has developed to protect the solid state and other circuit devices from electrostatic discharge (ESD), that can damage or destroy the sensitive and fragile elements of solid state devices. These two developments have led to a widespread use of filters of various kinds that operate, in one case, to filter out unwanted EMI from signal transmission, and in the other case, to filter out ESD voltage transits. One widespread use has been to provide filter elements proximate to circuit boards or to cable connected to such boards within connectors. U.S. Pat. No. 4,853,659 issued Aug. 1, 1989 is drawn to a planar pi-network filter assembly that utilizes capacitors and inductors incorporated into a connector to filter out unwanted components of signals transmitted through such connector. U.S. Pat. No. 4,729,752 issued Mar. 8, 1988 is drawn to a transit suppression device incorporated into a connector including a bi-directional diode incorporated as well as a filter means that functions to provide both filter and transit protection. Reference may be had to these prior art patents for a discussion or protection against surges and a filtering of signals from connector conductors.
In the foregoing examples and in many of the filters employed for both purposes, filtering and voltage surge protection, the elements, filters and/or diodes are fabricated with the electrodes thereof soldered to connector contacts, the post portions thereof, and to ground circuits to carry off the unwanted signal components or voltage transits to ground. Because of this, care must be taken relative to the particular solders used, connectors oft times being soldered to printed circuit boards after the assembly of the filter components and the use of solder in such assembly. Additionally, for many connector designs, the physical packaging required for filters simply will not fit within the dimensional parameters of the connector, making a retrofit difficult.
Accordingly, it is an object of the present invention to provide a filter insert that can be attached to the signal and ground conductors of transmission paths, connectors or cable, to effectively filter out unwanted signal components. It is a further object to provide an add-on filter insert that may be utilized with existing connector and cable designs which drastically reduces the use of solder. It is yet a further object of the invention to provide a novel connector or cable filter insert assembly in combination and readily applicable to closely spaced signal and ground conductors in connectors or cable or the like. It is finally an object of the invention to provide an interconnection between filter elements and signal and ground connectors that readily and easily can be applied without the use of solder.


An air filtering device including a circular plate, plurality of fan blades fixedly attached to the circular plate, the fan blades extending downwardly from the lower surface of the circular plate; a filter frame having an air permeable cylindrical inner wall, having an upper wall, having a lower wall, and having an air permeable cylindrical outer wall, the air permeable cylindrical inner wall, the air permeable cylindrical outer wall, the upper wall and the lower wall defining a cylindrical filter media containing space; air filtering media extending annularly around the air permeable cylindrical inner wall within the cylindrical filter media containing space; and, a filter frame attaching mechanism attaching the filter frame so that it extends annularly around the outer edges of the fan blades.

Air in homes or in business workplaces typically includes a colloid suspension of smoke particles, plant pollens, mold spores, and dust particles. Cigarette smoke suspended in the air of a home or a workplace, commonly known as secondhand smoke, is widely suspected as being a carcinogen. Pollen and mold spores suspended in the air of a home or a workplace are common allergens which may cause sinusitis or hayfever, and other respiratory ailments. Dust suspended in the air may be harmful to persons in a home or workplace who have emphysema or asthma. Additionally, airborne smoke and dust tends to discolor and soil items in a home or workplace such as curtains and furniture. Thus, it is widely seen as desireable to create home and workplace environments whose air is substantially free of airborne smoke, pollen, mold spores, and dust.
Several types of apparatus for cleaning and filtering air within a home or workplace are known. Many have disadvantages. For example, free standing electric air cleaning machines, typically incorporating an air impeller and a filtering medium mounted in the path of air flow, take up useable space within a room and typically create undesirable background noise. Another air filtering device having disadvantages is a carbon filter or an electrostatic air filter which is installable as an auxiliary element of a building's central air and heating system. Such systems are mechanically complex, and are expensive to construct, maintain, and operate.
The instant inventive air filtering device overcomes such disadvantages, among others, by providing a mechanically simple air filter which is economical to construct and operate, which takes up virtually no living or working space of a home or workplace, and which creates virtually no background noise. Such benefits are obtained through the provision of a centrifugal fan having a filtering media attached thereto and disposed therearound, the centrifugal fan and filtering media assembly being attachable to and rotatable by the rotor plate of a common ceiling fan; such ceiling fan having its fan blades removed.


A process for preparing a 3-aminophenylacetylene compound of formula (5), including: a) reacting a 3-haloaniline compound of formula (1) with an acetylene compound of formula (2) in the presence of a palladium compound, a copper compound, and an amine compound of formula (3) to form an aniline compound of formula (4); b) precipitating the aniline compound of formula (4) in the form of a crystal, and isolating it by solid/liquid separation; and c) reacting the aniline compound of formula (4) with a base to obtain 3-aminophenylacetylene.

1. Field of the Invention
The present invention relates to a process for preparing 3-aminophenylacetylenes useful as synthetic raw materials for pharmaceutical and agricultural chemicals, thermosetting resins, nonlinear optical materials, and the like.
2. Description of the Related Art
3-aminophenylacetylenes are interesting compounds having an amino group capable of forming polyimide, polyimine, or the like, and an acetylene group having polymerizability both present in the same molecule, and have received attention as the objects of study in various fields. They are useful as, for example, synthetic intermediates for thermosetting resins (see, for example, U.S. Pat. Nos. 4,485,231, 4,442,278, and 5,138,028, and JP-A-4-275259), nonlinear optical materials (see, for example, JP-A-1-233263, and JP-A-63-68549), pharmaceutical and agricultural chemicals (see, for example, U.S. Pat. No. 5,360,802, JP-A-57-118568, and JP-A-59-164160), and the like.
As described above, 3-aminophenylacetylenes has been used for various purposes in many fields and a variety of processes for preparing the same have been known. The processes known heretofore can be broadly divided into two types: (1) a process involving a reduction of only the nitro group present in a precursor having both an acetylene group and a nitro group; and (2) a process not involving a step of forming a nitro intermediate.
As the processes of type (1), there are known a process in which 3-nitrophenylacetylene is condensed with an acetone and the resultant condensation derivatives is reduced using a Ru catalyst (see, for example, J. Org. Chem., vol. 44, p. 1233 (1979)), using cobalt polysulfide (CoSx) or ruthenium (IV) sulfide (see, for example, J. Org. Chem., vol. 44, p. 3671, (1979)), or using an iron or an iron salt (see, for example, JP-A-10-36325).
As the processes via route (2), there are known a process in which trialkylstannyl acetylene which is an organotin compound and 3-iodoaniline are subjected to coupling in the presence of a palladium catalyst (see, for example, Macromolecules, vol. 19, p. 2093 (1986)); and a process comprising reacting a 3-haloaniline with a protected acetylene compound in the presence of a strong base, a palladium compound, and a copper compound (see, for example, U.S. Pat. No. 5,902,902).
Further, in the process according to U.S. Pat. No. 5,902,902, the use of diazabicyclooctane, diazabicycloundecane, and 1,1,3,3-tetramethylguanidine as the preferred strong bases in the reaction between 3-haloaniline and an acetylene compound is exemplified.
On the other hand, in recent years, the burden of chemical preparing processes on the environment has become a problem. This has resulted in demands for a clean chemical reaction leaving less waste, and using a minimum of harmful solvents, reaction agents, or the like (see, for example, Kagaku Frontier 4 (Green Chemistry), Kagaku Doujinn, translated by GSC Network, Nov. 30, 2001).
In the preparing process through route (1), it is important to reduce only a nitro group in the system where an acetylene group and a nitro group are both present in a molecule. In actuality, however, it is difficult to implement perfect selectivity to the reduction of nitro group only. Further, the process requires the preparation of a special catalyst such as cobalt polysulfide (CoSx), and the removal of the iron compound used as a reducing agent which after-treatment thereof is complicated. These and other aspects have caused not only an increase in cost but have also led to complication of operations including waste disposal.
On the other hand, the process not involving a step of forming a nitro intermediate of route (2) avoids the problem regarding reduction. However, in the process disclosed in the literature Macromolecules, vol. 19, p. 2093 (1986), a toxic organotin compound is used, which is not fit for preparation on an industrial scale from the viewpoint of the environment.
Also, the strong bases such as diazabicyclooctane, diazabicycloundecane, and 1,1,3,3-tetramethylguanidine in U.S. Pat. No. 5,902,902 are relatively expensive. In addition, the process of U.S. Pat. No. 5,902,902 is a process in which a reaction product is extracted with methylene chloride, followed by purification by silica gel column chromatography. This process is thus not fit for preparation on an industrial scale because of the complicated operations, and has also presented a problem from the viewpoint of the waste material.
Thus, conventional processes can not be said by any means to be an advantageous process in view of ease of operation, safety, preparing cost, throughput per reaction, separation and purification of the target substance, consideration of the environment, and the like.

Process for preparing 3-aminophenylacetylenes


Methods and apparatus relating to scheduling of air link resources, e.g., traffic segments, in wireless communications are described. Various described methods and apparatus are well suited to wireless peer to peer networks in which traffic scheduling is decentralized, e.g. an ad hoc peer to peer network. A first wireless terminal receives a transmission request and quality of service information from a second wireless terminal corresponding to a connection. The first wireless terminal decides not to receiver yield, determines a request response transmission power level as a function of the received quality of service information, and transmits, at the determined power level, a generated request response signal. By controllably adjusting the transmission power level of a request response, transmitter yielding decisions of lower priority links are impacted, since lower priority links measure and use received power level information corresponding to request responses of higher priority links in their transmitter yielding decisions.

In a wireless communications system lacking centralized control, the scheduling of traffic segments can be a challenging task. Wireless terminals corresponding to different connections may desire to use the same traffic segment concurrently. Depending on conditions and/or location, at times it may be acceptable for two connections to use the same traffic segment, while at other times it may not be tolerable. When making wireless terminal transmission determinations, situational awareness, e.g., situational awareness of the needs and/or requirements of other wireless terminals and/or other connections in its vicinity, can be beneficial. Rigid approaches to transmission determination, although easy to implement, may lead to traffic air link resource usage inefficiencies. Based on the above discussion it should be appreciated there is a need for methods and apparatus that are adaptive and allow for some flexibility relative to whether or not traffic data is to be transmitted.

Methods and apparatus supporting adaptive decentralized traffic scheduling for wireless communications


In a rigid thin-walled inner receptacle from thermoplastic material for storage and transport of fluid or free-flowing loads, with a cage of crossed hollow bars closely surrounding the plastic receptacle as a support jacket and a bottom pallet which supports the receptacle and on which the support jacket is firmly attached, the crossed vertically and horizontally extending hollow bars which are welded to each other at welding points and configured such that they are free of any dimples in their contact area at a point of intersection, and each of the hollow bars are provided laterally next to the point of intersection with at least one dimple laterally and at a distance from the point of intersection respectively the welding point.

The invention relates to a pallet container having a thin-walled rigid inner receptacle made from thermoplastic material for the storage and transport of fluid or free-flowing goods, wherein the plastic container is closely surrounded by an outer cage jacket as a supporting casing of crossed hollow bars and a bottom pallet on which the thermoplastic receptacle is supported and which is firmly connected with the supporting casing.
Pallet containers of the type that have a supporting casing from welded hollow bars are generally known, as for example the pallet container disclosed in EP 0 734 987 A (Sch). The supporting casing of the pallet container disclosed there consists of hollow bars having a circular profile that are highly compressed at the welded intersection points. From EP 07 55 863 (F) another pallet container is known with hollow bars that have a square profiled cross section and that are each partially slightly compressed, about 1 mm, at four contact points and only in the areas of intersections in order to facilitate a better welding action, while along the entire length of the hollow bars, they retain a cross section without any dimples, or have any cross section-reducing dents whatsoever.
Another pallet container, known from the DE 196 42 242 A, has a cage jacket from hollow bars that have an open trapezoid shaped profile, where the straight surfaces laterally flanged outwards, are welded together in the area where the bars intersect.
The bottom pallet of the pallet containers may be configured as a flat pallet made from plastic or wood or configured as a steel tube frame; and attachment of the cage jacket is usually realized by attachment means such as for example, screws, brackets, clamps or grips that engage with the lower horizontal and circumferentially extending cage bars. These attachment means are nailed, riveted, screwed or welded to the upper plate or the upper outer edge of the pallet.
The drawbacks of the embodiment of a pallet container disclosed in the afore-described EP 0 734 967 A are such, that the circular hollow profile of the horizontal and vertical cage hollow bars, particularly in the area of the intersections, are prone to considerable deformation, specifically at the side of the welding points and therefore exhibit a markedly reduced section modulus as compared to the other areas. Also, welding the hollow bars causes material brittleness precisely in the area of the dented hollow bar profile. Additionally, the hollow bar profile is still deeper dimpled next to the dimples for the welding points and thus, further weakened.
In industrial applications, for example when the pallet containers are utilized in the chemical industry, they have to pass a governmental approval inspection and fulfill various quality controls. For example, the filled pallet containers have to undergo interior pressure tests and drop tests in which the pallet container is dropped from specified heights. Pallet containers or combination IBCs (IBC=Intermediate Bulk Container) of the type discussed here—with a filling volume of usually 1000 liters—are preferably used in the transport of liquids. When transporting filled combination-IBCs in particular by truck, the content in the fluid container is prone to considerable gushing motions which are generated by transport shocks, such as for example when the transport vehicle rides on bumpy roads. Thus, constantly changing pressure forces are exerted on the interior receptacle walls, which in turn lead to radial vibrational motion of the cage jacket (dynamic continuous vibrational stress). Depending on the configuration of the cage jacket, especially during long transports over bad roads, vibrational stress builds up to such an extent that the cage bars get fatigued and/or break. Pallet containers of this type are therefore not suitable for multiple usage or for export to the USA.


Provided is an apparatus for protecting a passenger of an automobile, including: an automobile body; a biaxial FIS sensor mounted at a front center of the automobile body to sense decelerations on an X axis which is in a length direction of the automobile body and a Y axis which is in a width direction of the automobile body during an automobile impact; a deceleration meter sensing a first deceleration during the automobile impact; and a controller determining an airbag splaying time based on a displacement value and a predicted displacement value moving forward from an initial position of the passenger calculated based on the first deceleration, and an X-axial velocity variation and a Y-axial velocity variation measured from the biaxial FIS sensor.

Generally, various safety devices for protecting a driver and a passenger against unexpected situations which may occur at some time are provided in an automobile, and representatively, an airbag device for directly protecting the driver and the passenger seated in a front seat of the automobile is included.
When an impact to the automobile occurs, compression gas is momentarily injected into the airbag by impact force and thus, the air bag device covers front sides of the driver and the passenger in the front seats while the airbag is expanded at a rapid speed to protect the driver and the passenger from windshield glass of the automobile or a front object.
Generally, a representative type of front impact includes 100% front, offset, oblique, or pole impacts. In the case where a passenger restriction device is controlled by using a deceleration measured by an air-bag control unit (ACU) mounted in a passenger boarding chamber, performance of the 100% front and pole impacts may be secured, but performance of the offset and oblique impacts is hardly secured. In the case of the offset and oblique impacts, even though an impact degree is severe, a magnitude of the deceleration in the ACU which occurs at an early stage of the impact is not large, and as a result, it is difficult to control the passenger restriction device.
In order to solve the problem, a front impact sensor (FIS) is mounted on the front of the automobile. The FIS is used to sense the deformation of the front of the automobile at the early stage while mounted at the front of the automobile. The passenger restriction device is controlled by using the deceleration obtained therefrom together. Further, in order to prevent a malfunction of the passenger restriction device due to a malfunction of the sensor, a separate shaping sensor is mounted to operate the passenger restriction device only when the shaping sensor determines the impact.
In the case of using the FIS, the performance of the offset and oblique impact may be secured, but there is a problem as follows. Since the sensor is mounted at the front of the automobile, the sensor during the impact is broken or a wire harness connecting the sensor and the ACU may be cut. Further, there is a problem in that cost is increased due to the addition of two left and right FISs and the wire harness.

Apparatus for protecting passenger of autombile and control methodlamp


The present disclosure provides an improved approach to implement structure learning of neural networks by exploiting correlations in the data/problem the networks aim to solve. A greedy approach is described that finds bottlenecks of information gain from the bottom convolutional layers all the way to the fully connected layers. Rather than simply making the architecture deeper, additional computation and capacitance is only added where it is required.

Neural networks pertain to computational approaches that are loosely modeled after the neural structures of biological brain processing that can be used for solving complex computational problems. Neural networks are normally organized as a set of layers, where each layer includes a set of interconnected nodes that include various functions. Weighted connections implement functions that are processed within the network to perform various analytical operations. Learning processes may be employed to construct and modify the networks and the associated weights for the connectors within the network. By modifying the connector weights, this permits the network to learn over time from past analysis to improve future analysis results.
Neural networks may be employed to perform any appropriate type of data analysis, but is particularly suitable to be applied to complex analysis tasks such as pattern analysis and classification. Direct application of these techniques are therefore suitable, for example, to implement machine vision functions such as recognition and classification of specific objects and object classes from image data captured by digital imaging devices.
There are numerous types of neural networks that are known in the art. Deep neural networks is a type of neural network where deep learning techniques are applied to implement a cascade of many layers of nonlinear processing to perform analytical functions. Deep learning algorithms transform their inputs through more layers than shallow learning algorithms. At each layer, the signal is transformed by a processing unit, such as an artificial neuron, whose parameters are learned through training.
A convolutional neural network is a type of neural network where the connectivity pattern in the network is inspired by biological visual cortex functioning. Visual fields are constructed through the network, where the response of an individual artificial neuron to an input stimulus can be approximated mathematically by a convolution operation.
Convolutional deep neural networks have been implemented in the known art. LeNet (LeCun et al. (1998), AlexNet (Krizhevsky et al. (2012), GoogLeNet (Szegedy et al. (2015), and VGGNet (Simonyan & Zisserman (2015) are all examples of ConvNet architectures that implement different types of deep neural networks. These models are quite different (e.g., different depth, width, and activation functions). However, these models are all the same in one key respect—each one is a hand designed structure which embodies the architects' insights about the problem at hand.
These networks follow a relatively straightforward recipe, starting with a convolutional layer that learns low-level features resembling Gabor filters or some representations thereof. The later layers encode higher-level features such as object parts (parts of faces, cars, and so on). Finally, at the top, there is a layer that returns a probability distribution over classes. While there approach provide some structure, in the label space, to the output that is produced by a trained network, the issue is that this structure is seldom utilized when these networks are designed and trained.
Structure learning in probabilistic graphical models have been suggested, where the conventional algorithms for structure learning in deep convolutional networks typically fall into one of two categories: those that make the nets smaller, and those that make the nets better. One suggested approach focuses on taking unwieldy pretrained networks and squeezing them into networks with a smaller memory footprint, thus requiring fewer computational resources. This class of techniques follows the "teacher-student" paradigm where the goals is to create a student network which mimics the teacher. This means that one needs to start with both an Oracle architecture and its learned weights—training the student only happens later. When distilling an ensemble of specialists on very large datasets, the computationally expensive ensemble training step must be performed first.
Feng et al, "Learning the Structure of Deep Convolutional Networks" is an example of a technique for automatically learning aspects of the structure of a deep model. This approach uses an Indian Buffet Process to propose a new convolutional neural network model to identify a structure, where after the structure is determined, pruning is performed to create a more compact representation of the network. However, one drawback with this approach is that the number of layers remain static, where it is only the known individual layers within the static number of layers that is augmented to be more or less complex through the structure learning process. As such, this approach is unable to identify any new layers that may be needed to optimize the structure.
Therefore, there is a need for an improved approach to implement structure learning for convolutional neural networks.

Structure learning in convolutional neural networks


To provide encoder count error detection circuitry and an encoder count error detection method capable of realizing a highly reliable encoder by providing detection of the count errors of count signals used to measure displacement, an encoder count error detection circuitry and detection method configured as count error detection circuitry for an encoder outputting pulse trains according to the displacement of a measured object, doubles, triples, or quadruples one or more fundamental signals used for measuring displacement to convert to count signals, and compares the output signals of the counter counting these count signals with the level of these fundamental signals to detect count errors in the count signals.

Encoders are usually classified as rotary encoders and linear encoders, and rotary encoders are further classified as incremental encoders and absolute encoders. In particular, absolute encoders include multiple rotation-type encoders which detect the number of rotations. As described, for example, in Japanese Published Patent Application No. 6-41853, some multiple rotation encoders have mechanisms for detecting the displacement and angle of displacement within a single rotation, and some have mechanisms for detecting the number of rotations in more than one rotation.
The multiple rotation encoder described in Japanese Published Patent Application No. 6-41853 is equipped with an optical absolute value encoder for detecting the absolute angle within a single rotation, and a magnetic encoder for detecting multiple rotations. The optical absolute value encoder for detecting the absolute angle within a single rotation includes a rotating disk attached to the shaft for detecting the absolute angle within a single rotation, an LED for projecting light to this disk, a light receiving element photodiode array for receiving light from this LED through a stationary slit, and a waveform shaping circuit for shaping the waveforms of the detected signals from this photodiode array, among other parts. The magnetic encoder for detecting multiple rotations includes a rotating disk equipped with a magnet (a so-called "ring magnet") on the rotating part, a magnetic resistance element for detecting the rotation of this rotating disk, a waveform shaping circuit for shaping the waveforms of the signals from this magnetic resistance element, and a control circuit (counter) for counting the detected signals of multiple rotations and storing numerical values, among other parts.
Because magnetic poles reverse during one rotation, the rotation of the ring magnet can be detected by the magnetic resistance element by detecting change in these magnetic poles. Moreover, the mechanisms of such an encoder for detecting a single rotation and multiple rotations may be either optical or magnetic mechanisms, and such aspects as the structure and attachment location of their parts have various arrangements depending on the type of encoder.
As described, for example, in Japanese Published Patent Application No. 7-218290, only an optical system may be used for the detection mechanism and an optical system may be used to generate the signals used for detecting multiple rotations.
As described in Japanese Published Patent Application No. 10-325740, only an optical system may be used for the detection mechanism and the high-order bits of absolute signals may be used for the signals used to detect multiple rotations. Encoders where the multiple rotation detection part is magnetic are usually considered better because they may run with less power and may provide for prolonging the lifetime of the backup power.
Whichever system is used, the fundamental signals used to detect multiple rotations, as illustrated in FIG. 6, usually include Phase A and Phase B signals which differ in electrical angle by a 90° phase and complete one cycle per single rotation. Using signals with such a phase difference makes it possible to detect the direction of rotation and count the number of rotations according to the direction of rotation. Thus, FIG. 6 is a timing chart showing the state of each fundamental signal used to detect multiple rotations.
Because one count per single rotation may be used when using such fundamental signals to count the number of rotations, the change points for either the Phase A or Phase B signal is normally used to count the number of rotations. FIG. 7 is a timing chart using the Phase A and Phase B signals and the three low-order bit outputs Count (0) to Count (2) outputted by the counter to show the operation of such multiple rotation counting. In this example, a rotation is counted by detecting the rising edge of the Phase A signal. If the direction of rotation is clockwise, the count outputs Count (0) to Count (2) of the counter are incremented at each rising edge of the Phase A signal, and the number of rotations is counted as "0, 1, 2, 3. . . "
However, if an occurrence such as pulse breakup due to noise or oscillation makes it impossible to detect the rising edge of Phase A, this produces a count error as illustrated in FIG. 8, but inability to recognize count errors from the states of the Phase A and Phase B signals and the count outputs Count (0) to Count (2) may lead to overlooking count errors. Thus, FIG. 8 is a timing chart illustrating the state when a detection error (NG) occurs at an edge of Phase A in FIG. 7.
More precisely, such problems occur because when the levels of the Phase A and Phase B signals change as shown in Table 1, the corresponding states of the count output Count (0) can be both 0 and 1, and the correlation between these make it impossible to detect count errors.
TABLE 1Phase APhase BCount (0)000/1100/1010/1110/1
When such a detection error occurs in the multiple rotation part of a multiple rotation encoder, it constitutes a single rotation error, which is an error the extremely high figure for position control data of which runs the risk of creating fatal problems.
Although the same manner of counting using the Phase A and Phase B signals is also used by these incremental encoders and absolute encoders to detect displacement in a single rotation, this case also risks generating count errors in the same manner. Consequently, such count errors must be prevented to improve the reliability of encoders.

Encoder count error detection circuitry and encoder count error detection method


A drug delivery device may include an Inertial Measurement Unit (IMU) is provided. The IMU may include an accelerometer, a magnetometer, or a gyroscope. Motion parameters may be detected when the drug delivery device is shipped, being prepared for activation for use, or during use. The IMU may provide data indicative of a rapid deceleration, such as when a package containing the drug delivery device is dropped, or some other physical event experienced by the drug delivery device. The drug delivery device may also include internal or external pressure sensors or a blood glucose sensor that may coordinate with the IMU to provide additional feedback regarding the status of the device or user. A controller of the drug delivery device may generate a response depending on the particular parameters being monitored or may change device operational parameters as a result of detected system events.

Many conventional drug delivery devices fail to include sensors that may determine an operational status of the drug delivery device or status of the user of the drug delivery device. As a result, these conventional drug delivery devices typically place burdensome requirements on the users to assess and confirm proper operation of the devices or a status of the user. Users often find these requirements inconvenient and time-consuming.
Accordingly, there is a need for a drug delivery device that includes sensors for accurately determining the operational status of the device and health status of the user to obviate the need to place burdensome requirements on the user to do so directly.

Event detection for drug delivery system


A method and system for providing group services in a telecommunications network. Groups of subscribers can be created and each group associated with its own telephone number. A member of a group can communicate with others in that group using a group service and the telephone number associated with the group. In one aspect, a number of different, and separately processed, group services are provided which can be accessed using a common group telephone dialing number.

The development of telecommunications technology has provided people with more means by which to communicate with others. In addition to standard person-to-person voice calls, people can now use other means of communication such as text messaging, multimedia messaging, voice mail, conference calling and the like.
However, despite the advances made in telecommunications technology, on the whole communications still tend to be used for one-on-one communication. The lack of convenient ways in which to utilize existing technology for group communication has prevented its wide scale use in this manner.
WO 02/17653 describes a mobile communication system and method for broadcasting emails and voice mails to registered groups. The sender's address can be replaced with the destination group's address upon broadcast, to enable a reply to go to all group members.
WO 98/10608 describes a mobile station for a communications network, which stores groups of directory numbers in a memory. The mobile user can prepare a message and select a desired group. The mobile station then sends the message to each of the directory numbers appearing in the selected group.
WO 2004/008335 describes an invention for providing chat group services to mobile terminals that permits integrated voice and text messaging. Each participating mobile terminal runs a chat application, and a server connected to the wireless network runs applications and components for supporting the chat group services on the mobile terminals.
U.S. 2004/0005040 describes a system for integrating electronic mail, voice mail and fax mail in a universal mailbox. Message receivers may access their messages with a telephone or computer irrespective of the communication medium used by the sender.
Group voice dispatch services, also known as "Push to Talk" (PTT), are known, for example the Nextel iDen™ system. These systems allow groups to be defined, for which group communications services such as half-duplex voice calls, are provided. However, these systems require specially adapted handsets, which may be specific to a particular type of network, and therefore wide adoption of the technology, particularly for users of other types of mobile communications networks, has yet occurred.
Whilst various types of group communication in telecommunications systems are known, prior systems have not been particularly convenient to use, and therefore many users have been prevented or discouraged from adopting the technology.

Provision of group services in a telecommunications network

Orange Personal Communication Services Limited


A device for protecting a front spar structure of a central casing -of an aircraft wing and at least one item of equipment situated in the wing, comprising:                a shielding surface extending in front of the front spar of the central casing, from a surface of an intersection between the wing and the fuselage delimited by the root of the wing, transversely to the surface of intersection, to a first rib of the central casing partially surrounding at least one item of equipment; and        means -for fixing the shielding surface to the central casing producing an isostatic link.

Such a protection device comprises a shielding surface extending in front of the front spar of the central casing, from the surface of intersection between the wing and the fuselage delimited by the root of the wing, transversely to the surface of intersection, to a first rib of the central casing partially surrounding at least one item of equipment, and means for fixing the shielding surface to the central casing producing an isostatic link. Such a device makes it possible to protect the systems situated in the area of the root of the wing by benefiting from a robustness comparable to those of the shieldings that exist in other areas.
Unlike the shieldings of the prior art which were placed in proximity to the aerodynamic surfaces or which were planar, the device proposed in the present embodiment is placed in proximity to sensitive areas, set back from the aerodynamic surface, and surrounds the sensitive systems.
This makes it possible not only to give them more protection, but also to minimize the protection surface area, thus allowing for a weight saving without compromising the functionalities of the fuselage fairing.
Finally, the design simplicity of the device limits the installation times, which is particularly appreciable in an area where it is done on the final assembly line.

Device for protecting the front spar structure of a central casing of an aircraft wing and at least one piece of equipment located in said wing


A NAND-structure and amorphous-silicon based ROM device is provided. This ROM device is of the type including an array of MOSFET memory cells that are constructed based on a silicon-on-insulator (SOI) structure, so as to isolate the source/drain regions from the underlying substrate to prevent the occurrence of leakage current therebetween. Further, the SOI structure prevents occurrence of breakdown at the diode junction between the source/drain regions and the substrate for increased operating voltage. In this ROM device, the source/drain regions for the MOSFET memory cells are formed from the intrinsic amorphous-silicon, instead of highly-doped polysilicon, so that the fabrication process for the ROM device is significantly simplified.

1. Field of the Invention
This invention relates to semiconductor memory devices, and more particularly, to a NAND-structured amorphous silicon based semiconductor read-only memory (ROM) device, of the type including an array of MOSFET (metal-oxide semiconductor field-effect transistor) memory cells whose source/drain regions are formed from amorphous silicon and constructed based on a silicon-on-insulator (SOI) structure.
2. Description of Prior Art
Read-only memory (ROM) is a nonvolatile semiconductor memory widely used in computer and microprocessor systems for permanently storing information including programs and data that are repeatedly used, such as the BIOS (abbreviation for Basic Input/Output System, a widely used operating system on personal computers) or the like. The manufacture of ROMs involves very complicated and time-consuming processes and requires costly equipment and material to achieve. Therefore, the binary code to be permanently stored in ROMs is usually first defined by the customer and then furnished to the factory to be programmed into the ROMs.
Most ROMs are identical in semiconductor structure except for the different binary code stored therein. Therefore, the ROM devices can be fabricated up to the stage ready for data programming and then the semi-finished products are stocked in inventory awaiting customer orders. The customer then furnishes the data to the factory where the data are stored into the semi-finished ROMs by using the so-called mask-programming process. This procedure is now a standard method in the semiconductor industry for fabricating ROMs.
In most conventional ROMs, metal-oxide semiconductor field-effect transistors (MOSFET) are used as the memory cells for permanent storage of binary data. In the mask-programming process stage, an impurity material is doped into selected channel regions so as to provide the associated memory cells with different threshold voltage levels representing the storage of different values of the binary-coded data. Whether one MOSFET memory cell is set to store a binary digit of 0 or 1 depends on whether the associated channel region is doped with impurities or not. If one channel region is doped with impurities, the associated MOSFET memory cell is set to a low threshold voltage, effectively setting the MOSFET memory cell to a permanently-ON state representing the storage of a first binary digit, for example 0; otherwise, the MOSFET memory cell is set to a high threshold voltage, effectively setting the MOSFET memory cell to a permanently-OFF state representing the storage of a second binary digit, for example 1.
One conventional ROM device is shown in FIGS. 1A through 1C, in which FIG. 1A is a schematic top view of the ROM device; FIG. 1B is a cross-sectional view of the ROM device of FIG. 1 cut along the line IB--IB; and FIG. 1C is a cross-sectional view of the ROM device of FIG. 1 cut along the line IC--IC.
As shown, the conventional ROM device includes a semiconductor substrate, such as a P-type silicon substrate, on which a plurality of parallel-spaced bit lines 11 and a plurality of parallel-spaced word lines 13 crossing the bit lines 11 are formed. The word lines 13 are isolated from the underlying bit lines by an oxidation layer 12. This ROM device includes an array of MOSFET memory cells 14, each being associated with one segment of the word lines 13 between each neighboring pair of bit lines 11.
As shown in FIG. 1C, in the method for fabricating the conventional ROM device, the first step is to conduct an ion-implantation process so as to dope an N-type impurity material, such as arsenic (As), into selected regions of the substrate 10 to form a plurality of parallel-spaced diffusion regions serving as the bit lines 11. The interval region between each neighboring pair of the bit lines 11 serves as a channel region 16. Subsequently, a thermal oxidation process is performed on the wafer so as to form the oxidation layer 12 over the entire top surface of the wafer. Next, a conductive layer, such as a highly-doped polysilicon layer is formed over the wafer, and then selectively removed through a photolithographic and etching process. The remaining portions of the conductive layer serve as the word lines 13. This completes the fabrication of a semi-finished product of the ROM device awaiting for customer order.
In the mask-programming process, a mask layer 15 is first formed over the wafer. This mask layer 15 is predefined to form a plurality of contact windows according to the bit pattern of the binary-coded data that are to be programmed into the ROM device for permanent storage. These contact windows expose those channel regions that are associated with a selected group of the MOSFET memory cells of the ROM device that are to be set to a permanently-ON state. The covered MOSFET memory cells are to be set to a permanently-OFF state. Subsequently, an ion-implantation process is performed on the wafer so as to dope a P-type impurity material, such as boron (B), through the contact windows in the mask layer 15 into the exposed channel regions. This completes the so-called code implantation process.
In the finished product of the ROM device, the doped channel regions cause the associated MOSFET memory cells to be set to a low threshold voltage, effectively setting those MOSFET memory cells to a permanently-ON state representing the permanent storage of a first binary digit, for example 0. On the other hand, the undoped channel regions cause the associated MOSFET memory cells to be set to a high threshold voltage, effectively setting those MOSFET memory cells to a permanently-OFF state representing the permanent storage of a second binary digit, for example 1.
In the foregoing ROM device, since the source/drain regions are formed in the substrate by ion implantation, the isolation between the source/drain regions and the substrate is poor. Moreover, since a diode junction is used for the isolation of the source/drain regions from the substrate, the leakage current will be increased as the applied voltage is increased. Still further, since the magnitude of this leakage current is proportional to the contact area between the source/drain regions and the substrate, the operating voltage is limited to a small magnitude for prevention of a large leakage current.

Nand-structured and amorphous silicon based read-only memory device and method of fabricating the same


A control method of sound producing, sound producing apparatus, and portable apparatus are provided. The control method of sound producing is for a portable device, including the following steps. (a) A first detected parameter indicating a detected excursion of a speaker of the portable device is generated. (b) A second audio signal is generated based on a first audio signal, wherein the second audio signal is generated selectively by compensation according to at least the first detected parameter. (c) A gain value is determined according to at least the first detected parameter and a third audio signal is generated based on the second audio signal according to the gain value.

1. Technical Field
The disclosed embodiments relate in general to a control method of sound producing, a sound producing apparatus for a portable device, and a portable apparatus.
2. Description of the Related Art
A speaker reproducing audible sound is typically limited to its maximum excursion, temperature rising, transducer's non-linearity and its corresponding amplifier induced nonlinearity. In general, a speaker is driven under a rated power for a long period, and under a maximum power in a short period, which are determined by the manufacturer. The driven power restrictions confine the maximum excursion as well as temperature rising of a speaker in a safe range. For a reproduced signal of a large dynamic range without any distortion, the loudness of the speaker is small, especially for a handheld device under the power restrictions. Consequently, a dynamic range compression (DRC) technology has been introduced in a speaker system for decades so as to trade-off the distortion and loudness under the power restrictions.

Control method of sound producing, sound producing apparatus, and portable apparatus


A structure for use in a static induction transistor includes a semiconductor body having first and second semiconductor layers on a substrate, with the second layer having a dopant concentration of around an order of magnitude higher than the dopant concentration of the first layer. A plurality of sources are located on the second layer. A plurality of gates are ion implanted in the second layer, an end one of the gates being connected to all of the plurality of gates and constituting a gate bus. The gate bus has an extension connecting the gate bus in the second layer of higher dopant concentration to the first layer of lower dopant concentration. The extension is ion implanted in either a series of steps or a sloping surface which is formed in the first and second layers.

1. Field of the invention
The invention in general relates to semiconductors, and more particularly to a silicon carbide static induction transistor with high gate-to-drain breakdown voltage
2. Description of related art
A typical SIT (static induction transistor) is a vertical structure semiconductor device wherein electrical current flows from a plurality of source regions to a drain region, on opposite sides of a substrate member. Current flowing from source to drain is controlled by a potential barrier induced by gate regions positioned between the sources. The region between the source and gates is known as the channel region, while the region between the bottom of the channel region and drain is known as the drift region.
Conventional SITs have a gate-to-drain breakdown voltage measurable in hundreds of volts. For many applications, however, it would be desirable to have a gate-to-drain breakdown voltage measurable in the thousands of volts. It is an object of the present invention to provide a semiconductor structure for use in a SIT wherein a gate-to-drain breakdown voltage in the thousands of volts is achieved.

Semiconductor structure for use in a static induction transistor having improved gate-to-drain breakdown voltage


An air spring (2) includes: an upper surface plate (21); a lower surface plate (22); an elastic film (23) airtightly coupling a peripheral portion of the upper surface plate (21) and a peripheral portion of the lower surface plate (22) to each other to form an air chamber (24) inside the elastic film (23); an elastic stopper (25) connected to the lower surface plate (22); and at least one of an internal pipe (45) or internal wire (55) extending from an upper surface of the upper surface plate (21) to a side surface of the elastic stopper (25). A part of a pipe and/or wire extending between a carbody (11) and a bogie (1) of a railcar (100) is constituted by the internal pipe (45) and/or internal wire (55) of the air spring (2).

A carbody of a railcar is supported by a bogie through a carbody suspension including a bolster spring. The bolster spring is a spring provided between a bogie frame of the bogie and the carbody. The bolster spring relaxes an impact transferred from the bogie to the carbody to improve ride quality of the railcar. Typically used as the bolster spring is an air spring.
The railcar is provided with pipes and wires extending between the carbody and the bogie. One of the pipes extending between the carbody and the bogie is a brake pipe. The brake pipe is a pipe connecting a compressor provided at the carbody with brake equipment provided at each of wheels of the bogie. Compressed air is supplied from the compressor through the brake pipe to the brake equipment. Examples of the wires extending between the carbody and the bogie include lead wires of electric motors, ground wires, and sensor wires. Examples of a method of wiring the lead wires of the electric motor include a method in which the lead wires are wired upward from the electric motor provided at the bogie directly to the carbody and a method in which the lead wires are gathered at a middle portion of the bogie and then wired upward to the carbody.
When separating the carbody and the bogie from each other for maintenance, the pipes and wires extending between the carbody and the bogie need to be detached to the carbody side and the bogie side. Since work of separating the carbody and the bogie from each other and coupling the carbody and the bogie to each other includes work of disconnecting and connecting the wires and pipes extending between the carbody and the bogie, such work requires a lot of labor and is complicated. A technology of simplifying the work of separating the carbody and the bogie from each other and coupling the carbody and the bogie to each other has been proposed. For example, according to the railcar described in PTL 1, an interposed member is provided between the air spring and the carbody. A brake connection pipe connected to a brake mechanism through a hose is provided in the interposed member, the brake mechanism being provided at the bogie. The brake connection pipe communicates with a positioning pin provided on an upper surface of the interposed member. Further, a connection pipe and a level controlling valve are provided in the interposed member, and compressed air is supplied through the connection pipe and the level controlling valve to an air chamber of the air spring. The connection pipe communicates with a positioning pin provided on the upper surface of the interposed member. When the carbody is placed on the interposed member, an air pressure source provided at the carbody and the brake mechanism are connected to each other through the brake connection pipe and the hose, and the air pressure source provided at the carbody and the air chamber of the air spring are connected to each other through the connection pipe.


A self-supporting pneumatic tire, capable of continued operation during under-inflation conditions, has at least one insert located in each tire sidewall. Forming the interior surface of the self-supporting tire is a stiffening layer of material having characteristics similar to that of the insert. In the tread region of the tire, and radially inward of the innermost carcass layer, and possibly in the interior bead region of the tire, is a partial inner liner layer of the bromobutyl rubber.

One of the major improvements in tires in the previous century was the development of an inner liner. The presence of the inner liner, extending from bead to bead, radially inward of the tire casing, permitted the elimination of an inner tube. The inner liner is formed of a low permeability material to retain air inside the tire when the tire is properly mounted on a wheel.
Rubbers, such as butyl, bromobutyl, and halobutyl rubber, which are relatively impermeable to air are often used as a major proportion of inner liners. For instance, U.S. Pat. No. 2,676,636 discloses the use of butyl rubber as a highly air-impermeable inner liner for tires. Halobutyl rubbers are frequently employed as inner liners because they offer both excellent gas barrier properties and low temperature flexural properties.
The inner liner is normally prepared by conventional calendering or milling techniques to form a strip of uncured compounded rubber of appropriate width which is sometimes referred to as a gum strip. Typically, the gum strip is the first element of the tire applied to a tire building drum, over and around which the remainder of the tire is built. When the tire is cured, the inner liner becomes an integral, co-cured, part of the tire. Tire inner liners and their methods of preparation are well known to those having skill in such art.
Also known in the tire industry are self-supporting tires, capable of permitting travel even when the tire is underinflated. Such tires are disclosed in U.S. Pat. Nos. 4,365,659, 5,158,627, 5,368,082 and 6,453,961. A common characteristic of a self-supporting tire is the presence of rubber elements in the sidewalls of the tire. The rubber elements prevent collapse of the tire sidewall during underinflation operation.

This patent is subject to a terminal disclaimer.

Self-supporting pneumatic tire with a partial inner liner


A method for producing work is disclosed. The method includes increasing the pressure of a working fluid including carbon dioxide from a first pressure at least equal to a triple point pressure to a second pressure above the triple point pressure. The method also includes heating the working fluid, extracting mechanical work by expanding a first portion of the heated working fluid to a third pressure, supplying a second portion of the heated working fluid as a motive fluid to an ejector, increasing the pressure of the expanded working fluid by supplying the expanded working fluid to the ejector to combine with the motive fluid and form an output fluid at the fourth pressure, the fourth pressure at least equal to the triple point pressure of the working fluid. The method also includes refrigerating the output fluid to condense a vapor phase into a liquid phase.

Carbon dioxide has a number of properties that make it attractive for use in industrial applications. Some inherent advantages of the use of CO2 include high thermal conductivity in both liquid and solid phases, low density variation, high density, small or no undercooling, chemically stable, phase separation capable, compatible with container materials, non-toxic, non-flammable, non-polluting, cheap and abundant.
Most thermal energy storage systems are high temperature. In current technologies, the use of CO2 for an energy storage/working fluid has been largely dismissed because of a reliance on cycles operating wholly above the triple point pressure, which for carbon dioxide is high. This would require additional high-temperature heat sources. Additionally, for carbon capture and storage (CCS) or carbon capture, use and storage (CCUS) carbon dioxide recovered from a process or atmospheric source must be further "upgraded" to increase its pressure and purity in order to satisfy downstream transportation, use and storage requirements. The upgrade of carbon dioxide for CCS/CCUS is problematic because many capture processes operate at low-pressure, below the triple point pressure of CO2, such that CO2 cannot be condensed to a liquid. Furthermore, some capture processes operate cyclically or intermittently, requiring an upgrade system to be available on demand.
Purification processes such as phase separation, adsorption, absorption and membrane separation operate more effectively at higher pressure. To pressurize a fluid comprising CO2 initially below its triple point pressure, the fluid cannot be condensed and pumped, so vapor phase compression is necessary. Vapor compression typically requires more energy and more expensive equipment than liquid phase pressurization.

System and method for carbon dioxide upgrade and energy storage using an ejector

Arizona Board of Regents on behalf of Arizona State University


The input-output buffer circuit is provided with a PMOS transistor and an NMOS transistor which form an output driver which are ordinary MOS transistors instead of high breakdown voltage transistors. A resistor is inserted between drains of those MOS transistors and an external terminal. The resistance of this resistor is such that it generates a voltage drop as to cause a potential of drains of the PMOS transistor and the NMOS transistor not to exceed a voltage which can be safely applied to those MOS transistors and to become a potential which is at least a threshold level of an input buffer, when a current path extending from the external terminal to a power supply terminal through a parasitic diode of the PMOS transistor is formed.

The present invention relates to an input-output buffer circuit effecting signal input-output control normally even when a signal having a voltage higher than a power supply voltage of the input-output buffer circuit is inputted from an external source.
As the semiconductor fabrication process uses finer line widths, the power supply voltage for driving a semiconductor integrated circuit (hereafter simply referred to as IC) implemented as a single chip tends to become lower. On the other hand, a commercially available electronic device is constructed in many cases by mounting a plurality of ICs having different specifications on the same printed circuit board. In some cases, therefore, ICs driven with high voltages according to conventional specifications and ICs driven with low voltages according to current and future trends are present on the same electronic device. In this case, an IC is often supplied with an input signal having a voltage higher than a power supply voltage of the IC itself.
In general, an IC has an input-output buffer circuit for effecting the signal input-output control in a stage immediately preceding its output terminal. Signals inputted and outputted via the external terminal pass through the input-output buffer circuit. FIG. 5 is a circuit diagram showing a conventional input-output buffer circuit and its operation.
The IC 100 has an external terminal 17 connected to a signal line 9. In a stage immediately preceding the external terminal 17, the IC 100 has an input-output buffer circuit which includes a PMOS transistor MP and an NMOS transistor MN forming an output driver, an input buffer 16 for inputting a signal fed from the external terminal 17, a NAND gate 31, a NOR gate 32, and an inverter 33.
The PMOS transistor MP is connected at its source to a power supply terminal 12, and connected at its drain to the external terminal 17. The NMOS transistor MN is connected at its source to the ground, and connected at its drain to the external terminal 17.
The NOR gate 32 is supplied at its first input terminal with output data and supplied at its second input terminal with an output enable signal. An output terminal of the NOR gate 32 is connected to the NMOS transistor MN at its gate. The inverter 33 is supplied with the output enable signal and supplies its inverted output to a first input terminal of the NAND gate 31. A second input terminal of the NAND gate 31 is supplied with the output data. An output terminal of the NAND gate 31 is connected to the PMOS transistor MP at its gate.
Operation of the input-output buffer circuit will now be explained. First, in output mode, i.e. when the output enable signal has logic level xe2x80x9cLxe2x80x9d (low), output data of a logic level xe2x80x9cHxe2x80x9d turns on the PMOS transistor MP and turns off the NMOS transistor MN. At this time, therefore, a potential equivalent to a power supply voltage fed from the power supply terminal 12 is supplied to the output terminal 17. A signal of the logic level xe2x80x9cHxe2x80x9d is thus outputted.
On the other hand, output data of a logic level xe2x80x9cLxe2x80x9d turns off the PMOS transistor MP and turns on the NMOS transistor MN. Therefore, the external terminal 17 becomes equal to a ground potential, and a signal of a logic level xe2x80x9cLxe2x80x9d is outputted. In other words, when the output enable signal has a logic level xe2x80x9cLxe2x80x9d, the signal of the logic level indicated by the output data is outputted from the external terminal 17 as it is via mutually connected drains of the PMOS transistor MP and the NMOS transistor MN.
On the other hand, in input mode, i.e. when the output enable signal is provided with a logic level xe2x80x9cHxe2x80x9d (high), both the PMOS transistor MP and the NMOS transistor MN turn off. In other words, the external terminal 17 assumes a high impedance state. Irrespective of the logic state of the output data, the signal outputted to the outside assumes an indefinite state. In this state, a signal inputted from the outside to the external terminal 17 is inputted to an input buffer 16 and processed as input data.
As illustrated, the external terminal 17 of the IC 100 is connected to an external terminal 51 of another IC 200 via the signal line 9. A signal outputted from an input-output buffer circuit 56 included in the IC 200 is inputted to the external terminal 17. The internal circuit of the IC 200 is driven with a voltage higher than the power supply voltage with which the internal circuit of the IC 100 is driven. In FIG. 5, a power supply voltage supplied from a power supply terminal 11 is higher than the power supply voltage from the power supply terminal 12. In some cases, therefore, a signal having a voltage higher than the drive power supply voltage of the IC 100, i.e., a signal having a voltage higher than the voltage fed from the power supply terminal 12 is inputted to the IC 100.
If the drive power supply voltage of the IC 200, i.e., a signal having a voltage supplied from the power supply terminal 11 is inputted to the external terminal 17, then a current flows to the power supply terminal 12 through a parasitic diode 15 of the PMOS transistor MP as illustrated. This current makes the power supply voltage supplied to various circuits in the IC 100 unstable, and causes false operation or destruction of the PMOS transistor MP.
In the conventional input-output buffer circuit, a power supply terminal 13 for supplying a voltage having the same potential as the drive power supply voltage of the IC 200 is provided in the IC 100. The voltage fed from the power supply terminal 13 is applied to the PMOS transistor MP at its back gate. As a result, the external terminal 17 becomes equal in potential to the back gate of the PMOS transistor MP. A current is prevented from flowing to the power supply terminal 12 through the parasitic diode 15.
In the conventional input-output buffer circuit, however, a voltage higher than the voltage applied to other transistors included in the internal circuit is applied to the drains of the PMOS transistor MP and the NMOS transistor MN which form the output driver. Therefore, it is necessary to select a transistor having a high breakdown voltage as each of the PMOS transistor MP and the NMOS transistor MN. Furthermore, with the advance of smaller scale processes, implementation itself of transistors having a high breakdown voltage also becomes difficult.
Furthermore, since the back gate potential of the PMOS transistor MP becomes higher than the potential of the source connected to the power supply terminal 12, the transistor capability of the PMOS transistor MP becomes lower. For achieving a drive capability equivalent to that of ordinary transistors, therefore, it is necessary to increase the transistor size. Furthermore, there is a problem that the IC 100 needs the power supply terminal 13 for supplying the high voltage apart from the power supply terminal 12 for supplying the drive power supply voltage of the internal circuit.
It is an object of the present invention to provide an input-output buffer circuit to which an input signal having a potential higher than the drive power supply voltage can be inputted without using high breakdown voltage transistors.
The above described problems are solved and the object is achieved by the following aspects of the present invention. The input-output buffer circuit according to one aspect of the present invention includes an input buffer; a PMOS transistor and an NMOS transistor for forming an output buffer, drains of the PMOS transistor and the NMOS transistor being connected together; an output switchover circuit for switching an output mode for outputting output data from an external terminal to outside over to an input mode for inputting input data from the external terminal to the input buffer, and vice versa, according to an output enable signal; and a resistor disposed on a current path between the drains of the PMOS transistor and the NMOS transistor and the external terminal, and when a signal having a potential higher than a power supply potential for driving the own input-output buffer circuit is inputted to the external terminal, and thereby a current path extending from the external terminal to a power supply terminal through a parasitic diode of the PMOS transistor is formed, the resistor conducts potential lowering from the potential of the external terminal so as to cause a potential of drains of the PMOS transistor and the NMOS transistor not to exceed a voltage which can be applied to the PMOS transistor and the NMOS transistor and to become a potential which is at least a threshold level of the input buffer.
According to the above-mentioned aspect of the present invention, a resistor is inserted between the drains of the PMOS transistor and the NMOS transistor which form the output driver and the external terminal. Accordingly, even if a signal having a potential higher than the power supply potential for driving the own input-output buffer circuit is inputted to the external terminal, the potential of the signal can be lowered by the potential drop caused by the resistor. It thus becomes possible to always apply a voltage less than a voltage which can be applied to those MOS transistors, to the drains of the PMOS transistor and the NMOS transistor.
Further, it is preferable that the input-output buffer circuit further includes a comparator circuit for comparing the potential of the external terminal with the power supply potential, and the output switchover circuit is supplied with a comparison result from the comparator circuit. When the comparison result indicates that the potential of the external terminal is higher than the power supply potential, the output switchover circuit turns on the NMOS transistor connected at its source to a ground terminal.
Accordingly, the NMOS transistor connected at its source to the ground is turned on when the comparator circuit has judged the potential of the external terminal to be higher than the power supply potential. As a result, a current can be led from the external terminal to the ground terminal through the resistor.
Further, it is preferable that the input-output buffer circuit further includes a comparator circuit for comparing the potential of the external terminal with the power supply potential; and a back gate potential switchover circuit for receiving a comparison result of the comparator circuit. When the comparison result indicates that the potential of the external terminal is higher than the power supply potential, the back gate potential switchover circuit causes a back gate potential of the PMOS transistor to coincide with a ground potential, whereas when the comparison result indicates that the potential of the external terminal is equal to or less than the power supply potential, the back gate potential switchover circuit causes the back gate potential of the PMOS transistor to coincide with the power supply potential.
Accordingly, the back gate potential of the PMOS transistor is made to coincide with the ground potential when the comparator circuit has judged the potential of the external terminal to be higher than the power supply potential. In that case, therefore, a current can be led from the external terminal to the ground terminal through the resistor, the parasitic PNP transistor of the PMOS transistor, and the well resistor of the PMOS transistor.
Further, it is preferable that the input-output buffer circuit further includes a current control circuit responsive to the potential of the external terminal being higher than the power supply potential, for controlling a potential lowered by using the resistor so as to cause the potential lowered by using the resistor to become equal to the power supply potential.
Accordingly, the current control circuit controls the potential of a first end of the resistor so as to cause it to coincide with the power supply potential, when the current control circuit has judged the potential of the first end of the resistor to be higher than the power supply potential. It thus becomes possible to always apply a voltage less than a voltage which can be applied to those MOS transistors, to the drains of the PMOS transistor and the NMOS transistor.


A display panel driving apparatus is disclosed. In one aspect the apparatus includes a gate driving part and a data driving part. The gate driving part is configured to increase a gate signal applied to a gate line of a display panel from an OFF voltage to a ON voltage, in response to an activation of a gate clock signal. It is also configured to decrease the gate signal from the ON voltage to a kickback compensation voltage between the OFF voltage and the ON voltage through a plurality of steps in response to an activation of a kickback compensation signal. The data driving part is configured to apply a data signal to a data line of the display panel. Therefore, a data-charging rate may be increased, and thus a display quality of the display apparatus may be increased.

Field
The present disclosure generally relates to a method of driving a display panel, a display panel driving apparatus performing the method and a display apparatus having the display panel driving apparatus. More particularly, the disclosed technology relates to a method of driving a display panel used in a display apparatus, a display panel driving apparatus performing the method and a display apparatus having the display panel driving apparatus.
Description of the Related Technology
A display panel of a display apparatus, such as a liquid crystal display apparatus, generally includes a gate line, a data line, a switching element electrically connected to the gate line and the data line, and a pixel electrode electrically connected to the switching element.
A gate signal applied to the gate line is usually transited from a gate-off voltage (or OFF voltage) to a gate-on voltage (or ON voltage) during a horizontal period, the switching element is turned on in response to an activation of the gate signal, and thus a data signal applied to the data line is charged to the pixel electrode.
The gate signal is typically transited from the ON voltage to the OFF voltage after the horizontal period, the switching element is turned off in response to an inactivation of the gate signal, and thus the data signal is not charged to the pixel electrode.
When the gate signal is inactivated, a kickback voltage is usually generated due to a parasitic capacitance of the switching element, and the kickback voltage often deteriorates a display quality of the display apparatus.
A technique for inserting a kickback compensation period when the gate signal is decreased from the ON voltage to a kickback compensation voltage (or compensation voltage) greater than the OFF voltage in a period when the gate signal is decreased from the ON voltage to the OFF voltage has been developed, so as to decrease the kickback voltage.
However, when the kickback compensation voltage is decreased and the kickback compensation period is increased so as to decrease the kickback voltage, a data-charging rate regarding a data signal charged to the pixel electrode is decreased and thus the display quality of the display apparatus is deteriorated.

Method of driving a display panel, display panel driving apparatus for performing the method and display apparatus having the display panel driving apparatus


A solid-state imaging device includes a substrate in which a plurality of pixels including photoelectric converters are formed, a wiring layer that includes wirings in a plurality of layers formed via an interlayer insulating film in a front surface side of the substrate, a base electrode pad portion that includes a portion of the wirings formed in the wiring layer, an opening that penetrates the substrate from a rear surface side of the substrate and reaches the base electrode pad portion, and an embedded electrode pad layer that is formed so as to be embedded in the opening by electroless plating.

The present disclosure relates to a backside-illuminated solid-state imaging device and a manufacturing method thereof, an electronic apparatus using the solid-state imaging device.
In the related art, in a solid-state imaging device, backside-illuminated solid-state imaging devices are suggested for improving photoelectric conversion efficiency or sensitivity to incident light (Japanese Unexamined Patent Application Publication Nos. 2005-347707 and 2005-353631). In backside-illuminated solid-state imaging devices, photodiodes are formed on a semiconductor substrate as a photoelectric converter, pixel transistors and a wiring layer constituting a signal circuit, or the like, are formed on the front surface side of the semiconductor substrate, and light is incident from the rear surface side of the semiconductor substrate.
In the backside-illuminated solid-state imaging device, a portion of a multilayer wiring formed on the front surface side of the semiconductor substrate is provided as a pad electrode, a desired electric potential is supplied to the multilayer wiring due to the fact that an external terminal is connected to the pad electrode. In this case, a wiring bonding is connected from the rear surface side of the semiconductor substrate in the pad electrode which is formed in a portion of the multilayer wiring.
FIG. 6 is a schematic cross-sectional diagram illustrating a main portion of the backside-illuminated solid-state imaging device 100 of the related art. Particularly, the cross-sectional diagram illustrated in FIG. 6 illustrates a region including a pad region 127 formed in the peripheral region of the rear surface side of the backside-illuminated solid-state imaging device.
The backside-illuminated solid-state imaging device 100 includes an imaging region 103 in which photodiodes PD used as the photoelectric converter and a plurality of pixels including a plurality of pixel transistors (MOS transistors) are formed on a silicon substrate 112, and a peripheral circuit portion. In addition, the pad region 127 is formed in the peripheral region. Pixel transistors (not shown) constituting pixels are formed on the front surface side of the silicon substrate 112. Moreover, a wiring layer 113 including wirings 1M to 3M of multilayer structure (three layers in FIG. 6) is formed via an interlayer insulating film 114 in the front surface side of the silicon substrate 112. For example, the wirings 1M to 3M are formed of metal materials such as Cu, Al. In addition, the wiring 3M of the third layer is formed of an Al wiring, and the pad electrode 124 is formed in the pad region 127. A supporting substrate 116 is bonded, for example, by the silicon substrate via an adhesive layer 115 in the front surface side of the wiring layer 113.
On the other hand, an antireflective film 118, a color filter layer 119, and an on-chip lens 120 are formed on the rear surface side of the silicon substrate 112 corresponding to the imaging region 103.
In the pad region 127, an opening 123 for exposing the pad electrode 124 connected to the wiring 3M of the wiring layer 113 is formed. The opening 123 is formed at the same time as the shape forming process of the on-chip lens 120 is performed after forming an organic material constituting the on-chip lens 120, and the opening 123 is formed so that the pad electrode 124 is exposed from the rear surface of the substrate 122. In addition, when the pad electrode 124 is connected to the external terminal, a wire bonding 126, for example, a thin wire of Au (a so-called bonding wire) is connected to the pad electrode 124 which is exposed into the opening 123 in the pad region 127. Thereby, a desired electric potential is supplied from the external terminal.


A surface emitting semiconductor laser device including a substrate, a bottom DBR, and a mesa post having a layer structure, the layer structure including a top DBR including a plurality of pairs, each of said pairs including an Al-containing high-reflectivity layer and an Al-containing low-reflectivity layer, an active layer structure sandwiched between the DBRs for emitting laser, and a current confinement layer disposed within or in a vicinity of one of the DBRs, the current confinement layer including a central current injection area and an annular current blocking area encircling the central current injection area, the annular current blocking area being formed by selective oxidation of Al in an AlXGa1-XAs layer (0.95≦x<1) having a thickness below 60 nm, the Al-containing low-reflectivity layer including Al at an atomic ratio not more than 0.8 and below 0.9. The progress of the oxidation in the Al-containing compound semiconductor layers can be suppressed during the formation of the current confinement oxide area by restricting the Al content in the specified range, thereby realizing the surface emitting semiconductor laser device having the longer lifetime, or the higher reliability.

1. Field of the Invention
The present invention relates to a surface emitting semiconductor laser device with a current confinement oxide area, and more in particular to the surface emitting semiconductor laser device with the current confinement oxide area having a longer lifetime, or a higher reliability.
2. Description of the Related Art
A surface emitting semiconductor laser device emitting light in a direction perpendicular to a substrate attracts public attention in the data communication field because of the possible arrangement of a plurality of the laser devices in a two-dimensional array on a single substrate, different from a conventional Fabry-Perot semiconductor laser device.
The surface emitting semiconductor laser device includes a pair of DBRs (Distributed Bragg Reflector) (for example, Al(Ga)As/Ga(Al)As in the GaAs-based reflector) and an active layer acting as an emitting region sandwiched between the reflectors overlying a GaAs or InP substrate.
In order to increase the current injection efficiency and to reduce the threshold current, a surface emitting semiconductor laser device has been proposed having the current confinement structure formed by an Al oxide area.
For example, a GaInNAs-based material can be formed on the GaAs substrate, thereby providing a AlGaAs-based DBR mirror having an excellent thermal conductivity and a higher reflectivity. Accordingly, the mirror is promising in the surface emitting semiconductor laser device which emits light in a longer wavelength region from 1.2 to 1.6 μm.
As shown in FIG. 1, a conventional 850 nm-range surface emitting semiconductor laser device 10 includes a layer structure, overlying an n-GaAs substrate 12, having a bottom distributed Bragg reflector (hereinafter referred to as "DBR") mirror 14 having 35 pairs of n-Al0.9GaAs/n-Al0.2GaAs layers each having a thickness of λ/4n ("λ" is a lasing wavelength and "n" is a refractive index), a bottom cladding layer 16, a quantum well active layer 18, a top cladding layer 20 and a top DBR mirror 22 having 25 pairs of p-Al0.9GaAs/p-Al0.2GaAs each having a thickness of λ/4n.
In the top DBR mirror 22, one of the layers close to the active layer 18 is formed as an AlAs layer 24 in place of the Al0.9GaAs layer, and Al of the AlAs layer 24 in the area other than a current injection area is selectively oxidized to form a current confinement area formed by an Al oxide area 25 which surrounds the current injection area.
The top DBR mirror 22 in the layer structure is configured to be a circular mesa post 23 having a diameter of 30 μm from the top to the layer near to the active layer 18 formed by the photolithographic and etching process.
The annular current confinement area made of the Al oxide area 25 is formed in the mesa post 23 by selectively oxidizing the Al in the AlAs layer 24 inwardly from the outer periphery of the mesa post 23 by means of the oxidation treatment of the layer structure at about 400° C. in a water vapor ambient. When, for example, the Al oxide area 25 includes an annular ring having a width of 10 μm, the surface area of the central AlAs area 24 or the surface area for the current injection (aperture) is about 80 μm2 having a circular shape with a diameter of 10 μm.
The mesa post 23 is surrounded by, for example, a polyimide section 26, and a ring-shaped electrode acting as a p-side electrode 28 is mounted in contact with the periphery of the top surface of the mesa post 23 by the width from 5 μm to 10 μm. After the thickness of the n-GaAs substrate 12 is adjusted to about 200 μm by polishing the bottom surface thereof, an n-side electrode 30 is formed thereon.
An electrode pad 32 for connection with an external terminal is mounted on the polyimide section 26 and in contact with the ring-shaped electrode 28.
In the conventional current confinement oxide layer structure, the conversion of the AlAs layer into the Al oxide area by the oxidation contracts the volume thereof to generate stress in the compound semiconductor layers adjacent to the Al oxide area. Thereby, the active layer is deteriorated to reduce the lifetime of the device because the active layer exists in the vicinity of the Al oxide area.
Thus, in order to prevent reduction of the device lifetime, use of an Al0.98Ga0.02As layer containing a smaller amount of gallium (Ga) has been proposed in place of the AlAs layer. Further, the prevention of the stress is attempted by decreasing the thickness of the AlAs layer to about 40 nm.
However, the oxidation rate is reduced by one order compared with that of the AlAs layer having an ordinary thickness of 60 nm when the Al0.98Ga0.02As layer or the thinner AlAs layer is used.
Accordingly, in order to obtain the Al oxide area having the same width in the Al0.98Ga0.02As layer or the thinner AlAs layer, the time of the oxidation should be increased or the oxidation temperature should be elevated.
As a result, as shown in FIG. 2, a problem arises that the Al0.9Ga0.1As layer having the higher Al content or the lower refractive index layer in the DBR mirror is oxidized in the annular shape along the periphery of the mesa post because the top DBR mirror is exposed to the severe oxidation conditions during the oxidation of the AlAs layer (current confinement layer).
The width of the oxide area formed in the DBR mirror depends on the oxidation conditions including the composition and the thickness of the Al oxide area for the current confinement and the composition and the thickness of the compound semiconductor layers in the DBR mirror, and at least about 2 to 5 μm is inevitably oxidized.
Although the oxidation amount of about 2 to 5 μm is smaller with respect to the diameter of the mesa post, the volume contraction is large enough to be neglected because the number of the Al0.9Ga0.1As layers constituting the DBR mirror is large and each of the layers has an increased film thickness even if the oxide width is only several μm. The stress generated due to the volume contraction may adversely influence the reliability of the surface emitting semiconductor laser device.
Since the thickness of the DBR mirror is λ/4n, the influence increases with the increase of the wavelength of the surface emitting semiconductor laser device.
Further, as shown in FIG. 3, when a force is applied to the mesa post in the direction of the arrow shown therein, the stress is generated on the boundary between the AlAs layer 24 and the Al oxide area 25 or the vicinity of the front edge of the Al oxide area 25 (near to the center of the mesa post, a region "C" shown in FIG. 3).
Actually, the specimen of the surface emitting semiconductor laser device which was compulsorily deteriorated through the reliability test was observed with a transmission electro-microscope to confirm the occurrence of rearrangement around the region "C" in FIG. 3.
The factors exerting the stress on the surface emitting semiconductor laser device includes the external factor and the internal factor. The external factors includes, for example, a dielectric, a protection film made of polyimide and an electrode. Further, in the mounting step of the surface emitting semiconductor laser device, the various forces may be applied to the mesa post.
The internal factor includes a distortion generated in the layer film after the crystal growth. Especially, the thickness of the layer structure having the top and bottom DBR mirrors amounts to 10 μm in the surface emitting semiconductor laser device, and the distortion in the layer structure including the compound semiconductor layers is not negligible.
Further, since the thickness of the compound semiconductor layers is established to be ¼n (wherein "n" is a refractive index) times the wavelength, the thickness of the DBR mirror is increased in the surface emitting semiconductor laser device having a longer wavelength range of 1.2 to 1.6 μm. The thickness of the layer structure increases with the increase of the DBR mirror to increase the distortion, thereby significantly exerting the adverse influence to the lifetime of the surface emitting semiconductor laser device.
A countermeasure for improving the device reliability includes the reduction of the stress applied to the front edge of the Al oxide area.

Surface emitting semiconductor laser device


The disclosure relates to a method of globally balancing the transmit power in a cellular radio system with tight reuse of frequencies, to a central controller node, and to an access point that in combination with conventional power control schemes balances the downlink transmission power on re-used frequencies in order to balance co-channel interference in a multi-cell environment. The power balancing scheme takes the instantaneous channel variation and co-channel interference into account and satisfies the throughput requirements of the different cells when allocating downlink power to the user equipments. Global power balancing dynamically assigns a token to or takes a token away from an individual reused radio channel based on quality of, or based on transmission power in the channel. The balancing of transmission power, along with the conventional power scheme, prevents a global increase or global decrease of interference in the multi-cellular system.

The aim of a power allocation scheme is to dynamically allocate the RF power to the UE:s in a cell in order to balance the downlink co-channel interference in multi-cell environment. This is particularly important in a multi-cell orthogonal frequency division multiple access (OFDMA) based environment with tight frequency reuse, e.g. reuse 1 or reuse 3.
In an OFDMA based system the available bandwidth is sub-divided into several chunks of frequencies. A chunk is usually a two-dimensional radio resource, defined in both time and frequency domain and comprises of orthogonal sub-carriers. Each UE estimates the downlink channel quality on each chunk and reports the measured quality, e.g. a channel quality indicator (CQI), to the network. The CQI can be measured by an UE on pilot symbols. Downlink channel quality measurements can use any other suitable measurable signal that can depict the downlink instantaneous channel quality. Based on the reported CQI a radio network controller (RNC) dynamically allocates the chunks to be used for transmission of data to the UE:s in the downlink. To allocate chunks the RNC uses any conventional frequency allocation scheme. Base stations, also referred to as access points (AP:s), transmits on the selected chunks using a certain power level which is determined by a conventional power control scheme managed by the RNC.


A restraint assembly which is a bolted lattice structure for preventing the in-core guide tubes from experiencing excessive flow induced vibrations is described. In one embodiment, the restraint assembly includes upper and lower restraint brackets secured to an in-core housing and in-core guide tube assembly. The restraint brackets are located approximately equal distance from the end supports of the in-core guide tube and in-core housing assembly. The upper restraint bracket is welded between sections of the in-core guide tube, and the lower restraint bracket is welded between the in-core guide tube and the in-core housing. Each bracket includes four flanges, and each flange has tapped, or threaded, openings therein. Each bracket also includes cylindrical sections extending from the flanges, and in one embodiment, the cylindrical sections have inner and outer diameters which match the inner and outer diameters of the in-core housing and the in-core guide tube. The brackets are interconnected by plates and threaded bolts. More specifically, the brackets of each ICGT and ICH assembly are connected to brackets of adjacent assemblies by plates and bolts. The bolts are sized and torqued to ensure that a sufficient preload is maintained to prevent any slippage. The bolt heads are tack welded to the restraint plates after final assembly. The assembly also includes a shroud attachment plate and a restraint support bracket configured to be welded to a shroud.

Boiling water nuclear reactors typically include a reactor core located within a reactor pressure vessel (RPV). A known RPV includes a substantially cylindrical shell. The shell, for example, can be about twenty feet in diameter and about seven inches thick. The cylindrical shell is closed at its top end by a removable top head. The top head is removable so that components, such a fuel bundles, located in the RPV can be accessed. The RPV cylindrical shell is closed at its bottom end by a dome shaped bottom head assembly welded to the shell. A plurality of openings, sometimes referred to as penetrations, are formed in the bottom head dome so that components can extend within the RPV.
For example, in-core guide tubes (ICGT) and in-core housings (ICH) are long tubes which are welded together end to end to form an assembly, and the ICGT and ICH support and protect the in-core instrumentation. The bottom end of the ICH penetrates the bottom of the reactor pressure vessel and is welded to the bottom head dome. Welding the ICH to the bottom head dome provides rotational, vertical and horizontal support of the assembly. The top end of the ICGT penetrates the core plate, and the ICGT makes a slip fit with the core plate. The slip fit with the core plate provides only horizontal support of the assembly. The distance between upper and lower end supports is approximately 16 feet.
During operation, fluid flows along the outside of the ICH/ICGT assembly. Particularly, fluid flows parallel to the axis of the assembly as well as across the assembly. Such flow causes flow induced vibrations (FIV) in the assembly. If unsupported between the ends, the ICH/ICGT assembly would experience vibration levels above acceptable limits.
Known restraints for the ICH/ICGT assembly include a lattice arrangement of bolted plates which tie the ICGTs together. In at least one known reactor, two sets of lattices are attached to the shroud and tie the ICGTs together to reduce the FIV to an acceptable level. Tying the ICGTs together changes the natural frequency of the ICH/ICGT assemblies. Thus, the FIV may be reduced by connecting the ICGTs.
The known restraint structures are expensive to fabricate and are difficult to install. It would be desirable to provide a simpler but effective restraint configuration for ICH/ICGT assemblies. Of course, such a restraint should not add significant fabrication and maintenance costs to the reactor.

In-core guide tube restraint for a boiling water reactor