The present invention relates to symmetric and asymmetric dimeric Dmt (2′,6′-ditnethyl) compounds and Dmt derivative compounds with dual δ and μ opioid receptor antagonist activity. Also, the present invention provides compositions comprising these compounds and it provides methods of using these compounds.

Endogenous opioids such as endomorphin-1 [EM-1] and endomorphin-2 [EM-2] are believed to be involved in the modulation of pain perception, in mood and behavior, learning and memory, diverse neuroendocrine functions, immune regulation and cardiovascular and respiratory function. Opioids also have a wide range of therapeutic utilities, such as treatment of opiate and alcohol abuse, neurological diseases, neuropeptide or neurotransmitter imbalances, neurological and immune system dysfunctions, graft rejections, pain control, shock and brain injuries.
There are believed to be three types of opiate receptors, namely δ, κ and μ. Genes encoding these three main receptor types now have been cloned. Sequencing of the cloned opioid receptor genes has revealed a substantial degree of amino acid homology between different receptor types (Evans et al., Science 258: 1952-1955 (1992); Kieffer et al., PNAS USA 89: 12048-12052 (1992); Meng et al., PNAS USA 90: 9954-9958 (1993); Thompson et al., Neuron 11: 903-913 (1993)), which explains the tendency of opioid receptor ligands, even those reported to be selective, to bind to more than one type of opioid receptor. Based on differences in the binding profiles of natural and synthetic ligands, subtypes of opioid receptors have been suggested, including μ1 and μ2 (Pasternak et al., Life Sci. 38: 1889-1898 (1986)) and κ1 and κ2 (Zukin et al., PNAS USA 85: 4061-4065 (1988)). Different subtypes of a given type of opioid receptor may co-exist in a single cell (Evans et al. (1992), supra; and Kieffer et al. (1992), supra).
The μ-opioid receptor in the brain appears to mediate analgesia (Kosterlitz et al., Br. J. Pharmacol. 68: 333-342 (1980)). It is also believed to be involved with other undesirable effects, such as respiratory depression (Ward et al., Soc. Neurosci. Symp. 8: 388 (abstract) (1982)), suppression of the immune system (Plotnikoff et al., Enkephalins and Endorphins: Stress and the Immune System, Plenum Press, NY (1986); Yalya et al., Life Sci. 41: 2503-2510 (1987)) and addiction (Roemer et al., Life Sci. 27: 971-978 (1981)). Its side effects in the periphery include inhibition of intestinal motility (Ward et al., Eur. J. Pharmacol. 85: 163-170 (1982)) and secretion in the small intestine (Coupar, Br. J. Pharmacol. 80: 371-376 (1983)).
δ-Opioid receptors also mediate analgesic but are not involved in addiction. They may have an indirect role in immune suppression and act in concert with μ-opioid receptors.
There appears to be a single binding site for agonists and antagonists in the ligand-binding domain of δ receptors. Thus, the "message domain" of δ-agonists and δ-antagonists probably presents a similar low energy conformer in order to fit the receptor cavity. The minimum size of that "message domain" constitutes the dimensions of a dipeptide (Temussi et al., Biochem. Biophys. Res. Commun. 198: 933-939 (1994); Mosberg et al., Lett. Pept. Sci. 1: 69-72 (1994); and Salvadori et al., J. Med. Chem. 42: 3100-3108 (1997)), which has a specific spatial geometry in solution (Bryant et al., Trends Pharmacol. Sci. 18: 42-46 (1998); Bryant et al., Biol. Chem. 378: 107-114 (1997); Crescenzi et al., Eur. J. Biochem. 247: 66-73 (1997); and Guerrini et al., Bioorg. Med. Chem. 6: 57-62 (1998)) as seen in the crystallographic evidence for TIPP analogues (Flippen-Anderson et al., J. Pept. Res. 49: 384-393 (1997)) and N,N(Me)2-Dmt-Tic-OH (Bryant et al. J. Med. Chem. 45, 5506-5513 (2002).
The Dmt-Tic pharmacophore represents a distinct class of δ-opioid antagonists (Salvadori et al., Mol. Med. 1: 678-689 (1995); Bryant et al. (1998), supra; Lazarus et al., Drug Dev. Today 284-294 (1998); Bryant et al., Biopolymers/Pept. Sci. 71, 86-102 (2003)). Observations of differences between the δ opioid receptor binding of Dmt-Tic peptides and their Tyr-Tic cognates (Salvadori et al. (1995), supra; Lazarus et al. (1998), supra; and Lazarus et al., Int'l Symp. on Peptide Chem. and Biol., Changchung, PRC (1999)) indicates that Dmt assumes a predominant role in the alignment or anchoring of the peptide within δ, μ and κ opioid receptor binding sites (Bryant et al. (1998), supra; and Bryant et al. (1997), supra; Crescenzi et al. (1997), supra; and Guerrini et al. (1998), supra) or affects the conformation of the dipeptide antagonists in solution (Bryant et al. (1997), supra; and Crescenzi et al. (1997), supra). Furthermore, observations of differences between the spectra of activity exhibited by the Tyr-Tic cognates of certain Dmt-Tic peptides (Schiller et al., PNAS USA 89: 11871-11875 (1992); Schiller et al., J. Med. Chem. 36: 3182-3187 (1993); Schiller et al., Peptides Hodges and Smith, eds., ESCOM (1994); pp. 483-486; Temussi et al. (1994), supra; Mosberg et al. (1994), supra; Salvadori et al. (1995), supra; Lazarus et al. (1998), supra; and Lazarus et al. (1999), supra) and the corresponding Dmt-Tic peptides suggests that the C-terminal "address" portion of the peptide can influence the "message domain."
Recently, cyclic peptides and di- and tri-peptides comprising the pharmacophore Dmt-Tic have been developed and have been shown to exhibit high selectivity, affinity and potency for the δ-opioid receptor. Such peptides have been shown to function as agonists, partial agonists, antagonists, partial antagonists or mixed antagonists/agonists for opioid receptors (see Lazarus et al., U.S. Pat. No. 5,780,589, and Schiller, U.S. Pat. No. 5,811,400).
A variety of modifications to the Tic residue differentially changes receptor selectivity, including alterations in its electronic configuration and chirality, as well as its replacement by heteroaliphatic/heteroaromatic nuclei or D-Phe (Santagada et al., Med. Chem. Lett., 10, 2745-2748 (2000); Pagé et al., Bioorg. Med. Chem. Lett., 10, 167-170 (2000); Salvadori et al., Mol. Med., 1: 678-689 (1995); Balboni et al., Peptides, 21: 1663-1671 (2000); and Capasso et al., FEBS Lett., 417: 141-144 (1997)). Changes wrought by altering the distance to a third aromatic center at the C-terminus by an interposed sequence, a spacer or linker ("X"), induces profound changes in the affinity, selectivity and bioactivity of a ligand (Capasso et al., FEBS Lett., 417: 141-144 (1997); Salvadori et al., J. Med. Chem., 42: 5010-5019 (1999); Pagé et al., J. Med. Chem., 44: 2387-2390 (2001); Balboni et al., J. Med. Chem. 45, 5556-5563 (2002)).
Moreover, it is known that tail-to-tail condensation of pharmacophores such as dimeric dermorphin analogues (Lazarus et al., J. Biol. Chem. 264, 354-362 (1989)), biphalin [Tyr-D-Ala-Gly-Phe-NH—)2]—a dimericenkephalin analogue, and norbinaltrophimine (norBNI)—a dimer of naltrexone derivatives, significantly improves opioid receptor affinity and altered biological activity (Portoghese et al., Trends Pharmacol. Sci., 10: 230-235 (1989); Portoghese et al., J. Med. Chem., 35: 1927-1937 (1992); Portoghese et al., J. Med. Chem., 44: 2259-2269 (2001); Lipkowski et al., Peptides, 3: 697-700 (1982); Lazarus et al., J. Biol. Chem., 264: 354-362 (1989); Horan et al., J. Pharmacol. Exp. Ther., 265: 1446-54 (1993); Weltrowska et al., J. Peptide Res., 63: 63-68 (2004); Portoghese et al., Life Sci., 40: 1287-1292 (1987)).
The uniqueness of the δ receptor has led to the use of moderately δ-selective alkaloid antagonists in clinical trials, such as for the amelioration of the effects of alcoholism (Froehlich et al., Alcohol. Clin. Exp. Res. 20: A181-A186 (1996)), the treatment of autism (Lensing et al., Neuropsychobiol. 31: 16-23 (1995)), and Tourette's syndrome (Chappell, Lancet 343: 556 (1994)). The δ-opiate antagonist naltrindole (Portoghese et al., Eur. J. Pharm. 146: 185-186 (1998)) has been shown to inhibit the reinforcing properties of cocaine (Menkens et al., Eur. J. Pharm. 219: 346-346 (1992)), to moderate the behavioral effects of amphetamines (Jones et al., J. Pharmacol. Exp. Ther. 262: 638-645 (1992)), and to suppress the immune system (Jones et al. (1992), supra) for successful organ transplantation (House et al., Neurosci. Lett. 198: 119-122 (1995)) in animal models (Arakawa et al., Transplant Proc. 24: 696-697 (1992); Arakawa et al., Transplant 53: 951-953 (1992); and Arakawa et al., Transplant. Proc. 25: 738-740 (1993)). The same effects also have been shown for 7-benzylspiroindanylnaltrexone (Lipper et al., Eur. J. Pharmacol. 354: R3-R5 (1998)).
The intractable membrane barriers, such as the blood-brain barrier (BBB), must be circumvented in order for peptide antagonists to express activity in vivo (Ermisch et al., Physiol. Rev. 73: 489-527 (1993)). The requisite physicochemical properties of compounds capable of passing through this barrier include low molecular weight (<800 Da) and high octanol-water coefficient characteristics.
In view of the above, the present invention provides more potent μ-opioid antagonists and δ-opioid antagonists, whereby the antagonists have a high dual binding affinity and biological activity toward δ-opioid and μ-opioid receptors, providing a means to simultaneously down-regulate two independent opioid receptors, and whereby the antagonists can pass through the blood-brain barrier following systemic or oral administration. Also, the present invention provides compositions comprising these compounds and it provides methods of using these compounds as therapeutic agents in the treatment of tolerance, alcohol dependency, and drug addiction.
The present invention also transforms selective μ-opioid receptor agonists into potent μ-opioid receptor antagonists. Also, the present invention provides compositions comprising these compounds and it provides methods of using these compounds as therapeutic agents in the treatment of drug tolerance, alcohol dependency, and drug addiction.
These and other objects of the present invention, as well as additional inventive features, will be apparent to the ordinarily skilled artisan from the detailed description provided herein.

Dmt-derivative compounds and related compositions and methods of use

The United States of America as represented by the Secretary of the Department of Health and Human Services


A separation element formed of one of a conduction region and a metal layer is placed between two elements in proximity to each other. The separation element is connected to a high resistance element and to a direct current terminal pad. A connection route extending from the direct current terminal pad to the separation element is a route in which a potential does not vibrate with high frequency. This results in a placement of a high frequency GND potential between the two elements, at least one of which is subjected to transmitting the high frequency signals, whereby leak of the high frequency signals can be prevented between the two elements.

1. Field of the Invention
The present invention relates to a compound semiconductor device, and more particularly to a compound semiconductor device which is improved in isolation thereof.
2. Description of the Related Art
A monolithic microwave integrated circuit (MMIC) of a compound semiconductor device uses microwaves having a GHz band in many cases, thus resulting in an increasing demand for improvement in isolation.
For example, in a case where two elements (any of an FET, a wiring, an electrode pad, and an impurity region) are placed in proximity to each other in the same chip, a technology, in which a high concentration impurity region is placed between the two elements, is known. The high concentration impurity region improves the isolation between these two elements either by using a floating potential or by applying a GND (ground) potential. This technology is described for instance in Japanese Patent Application Publication No. 2004-134589.
As described in the patent application publication, when the high concentration impurity region to which a GND potential is applied is placed between the two elements (for example, two adjacent FETs) in proximity to each other, high frequency signals which transmit in the FET leak to the GND potential in some cases.
That is to say, carriers drift by the bias between the two FETs and the high concentration impurity region being at the GND potential so that the high frequency signals which transmit in the two FETs leak via the high concentration impurity region to the ground. Accordingly, there has been a problem where an increase in insertion loss is observed in a case of switch MMIC, for example.
On the other hand, when the high concentration impurity region in an electrically floating state in potential is placed between two elements (for example, FETs) in proximity thereto, the small amplitude high frequency signals leaking from the FET to a substrate can be absorbed by the high concentration impurity region, thereby resulting in improved isolation between the two FETs.
However, when large amplitude high frequency signals leak from the FET to the substrate, the potential itself of the high concentration impurity region in the electrically floating state in potential varies. This is because the power of the leaked high frequency signals is so large that the potential of the high concentration impurity region varies. As a result, there arises a problem that sufficient isolation cannot be ensured between the two elements such as the FET, and the like.


Generation of a three-dimensional, immersed image display, by generating a straight-ahead three-dimensional view for display on a portion of a display area and generating at least one of a side peripheral, top peripheral, bottom peripheral and rear three-dimensional view for display on a contiguous substantial remainder of the display area. In an embodiment, the size of the display area used for displaying the one or more peripheral and/or rear views is adjustable. The field of view of the one or more peripheral and/or rear views preferably also is adjustable.

1. Field of the Invention
This invention relates to three-dimensional (3D) graphics.
2. Background of the Related Art
Systems for the processing and display of 3D graphics typically include the display on a display device such as a video monitor of an imaginary or real place or object so as to provide a viewer with a sensation that the place or object exists in three dimensions. This typically is accomplished by providing visual cues, such as scaling down the size of distant objects or showing certain objects partially blocked by others, to impart to the viewer the impression of being in a 3D environment.
The computer-generation of 3D graphics on the screen of a video monitor is a well-known process. It consists of generating a set of three-dimensional (x, y, z) coordinates and performing a computer-generated series of transformations on the coordinates. The coordinates represent the objects in the scene. The transformations represent how the viewer sees the objects on the screen.
3D graphics programming is usually performed utilizing a software library that allows the programmer to program 3D graphics without concerning himself with various details of placing pixels on the screen. There is a great deal of similarity in the operation of the various software libraries, and anyone skilled in the art of using one library would have sufficient skill to use any of the other libraries. Thus, the choice of which library to use is an implementation detail.
The method of representing objects in 3D varies somewhat between software libraries, although the primary meaning of a set of coordinates is always the same. Various methods exist for defining and coloring surfaces of objects in a scene, but these methods are easily translated between libraries.
The transformations applied to coordinates by various 3D software libraries almost always have the same meaning. The transformations typically consist of a 4.times.4 matrix of numbers. It is well known in the art how to mathematically apply one or more transformation matrices to a set of coordinates to provide 3D effects on the computer screen. Transformation matrices are chosen so that there is an analogy between the mathematics of 3D rendering and our understanding of how pictures are taken by a photographic camera. The camera analogy is well understood by persons skilled in the art of computerized construction of 3D images, and its use greatly simplifies such discussions.
Immersive 3D environments are environments in which the viewer is given the impression of being brought into and navigating within the 3D environment. Many 3D graphics environments are not immersive. In non-immersive 3D environments, a viewer is merely provided with the sensation of being placed in front of the 3D scene and looks in. One recent use of immersive 3D graphics is virtual reality (VR), which attempts to give the viewer the impression of being inside a 3D representation of a real or imaginary place. The growing availability of VR graphics tools has resulted in the viewer being placed inside more or less abstract 3D scenes.
With VR, the viewer is immersed in a 3D scene, but the viewer still lacks important perceptual tools that are available to people in the real world. Specifically, typical views of VR provide little or no perceptual context. For example, a viewer of a VR system experiences "tunnel vision," in which the video monitor appears to be window placed several feet from the viewer through which he or she views objects and places on the other side of the window. This limits the viewer's field to a few degrees, eliminating most of the normal field of vision. This lack of perceptual context can limit effective use of the 3D presentation with effects varying from missed sightings to physical nausea on the part of the viewer.
Objects "behind" the viewer in 3D space must be treated as real even though they are not immediately visible, if an effective presentation and impression on the viewer is to be made. For example, if the viewer faces a tree, turns around, and walks backward, he will "hit" the tree in 3D space even though he cannot "see" it. Or, if the viewer walks past a tree too closely, he will hit the tree. In real life, one is aware of these objects through mechanisms such as peripheral vision and quick head turns.
Current VR technology has used various methods to attempt to provide visual context and to compensate for the lack of peripheral vision. These methods include wide angle views of the scene (like a fish-eye lens), an approximation of quick head turns (looking left and right), and overhead maps centered on the viewer. However, wide angle views distort the scene, and an approximation of quick head turns can be disorienting to the viewer. One technique used inside virtual vehicles (e.g., a tank) involves showing views out of front and side windows, without any attempt to connect or relate the views.

Peripheral vision simulator for immersive 3D virtual environments


A method and apparatus for manipulating a contact tip of a welding device includes a member, e.g., a clutch bearing or other device, that securely grasps the contact tip and minimizes damage thereto. The method and apparatus can be used to install or remove a contact tip into/from a welding device, e.g., without the need to remove the nozzle of the welding device.

Welding equipment, e.g., metal inert gas (MIG) or Gas Metal Arc Welding (GMAW) welding equipment, can be used for welding one metal workpiece to another metal workpiece. A welding gun can be designed to allow a user or robot to direct a metal welding wire toward a specific location on a target metal workpiece. The components of a typical welding gun include a handle, a gooseneck, a retaining head, a contact tip, and a nozzle. The welding wire is fed through the welding gun, and ultimately through a passageway in the contact tip, which is disposed at an end of the welding gun. The welding wire, when energized for welding, carries a high electrical potential. When the welding wire makes contact with the target metal workpiece an electrical circuit is completed and current flows through the welding wire, across the metal workpiece and to ground. The current causes the welding wire and the metal of the workpieces in contact with the welding wire to melt, allowing workpieces to be joined.
Extreme heat is caused by the resulting current flow. Since the contact tip usually includes copper or a copper alloy, the extreme heat tends to cause it to wear out relatively quickly. In addition, connection between welding gun components can loosen during use, and loose connections can be a source of electrical resistance and in turn generate excessive heat within a welding gun. Heat in welding guns translates into shorter consumable life, tip burn back, and even melting of components.
The proper installation of a contact tip in a welding device is important for maintaining consistency and efficiency in the welding process. Currently, weld operators use a wide variety of tools to remove and replace contact tips, such as pliers or clamping tools. These tools can prevent the weld operator from consistently changing a tip, which can reduce the efficiency of the welding process. Furthermore, these tools can damage the contact tip, thereby inhibiting its performance and creating more down time by increasing the frequency of contact tip changes. In addition, score marks on a contact tip resulting from a clamping device can provide a place for spatter to adhere and for heat to build up, requiring additional tip changes and down time.
Therefore, a need exists in the art for a means of installing a contact tip that minimizes damage to the tip and increases the consistency of the installation, extending the usable lifetime of the contact tip and minimizing down time due to frequent contact tip changes.

Contact tip installation tool for a welding device


A solder mask defined bond pad or a non-solder mask defined bond pad may be configured to center the solder over the bond pad using either surface attractive forces or capillary action. In some embodiments, a stub trace may be provided, for example, in opposition to the real trace to provide a capillary counter-attractive force on the solder. In other embodiments, the surface attractive action of the edge of the solder mask may be utilized to center the solder. In still other embodiments, the natural attractive force of a trace on solder may be utilized to appropriately position solder where desired, for example, to line up with other solder deposits.

This invention relates generally to solder bonding techniques for integrated circuit devices.
Referring to FIG. 10, commonly solder is deposited on a solder pad 62 which is coupled to other electrical components on an integrated circuit by a trace 60. The solder deposition area is defined by the inwardmost edge 64 of a solder mask. Thus, in the embodiment illustrated in FIG. 10, the solder is deposited inside the circle 64. The solder mask prevents solder outflow over the mask thereby preventing the solder from moving outwardly beyond the edge 64.
The solder may be in the form of conventional solder balls which are deposited in a solid configuration and then reflowed thereafter. Alternating the solder may be a liquid or paste upon deposition.
Referring to FIG. 11, one problem with existing techniques for depositing solder is that when soft the solder 66 tends to wick along the trace 60. Without limitation, it is believed that the wicking is a result of capillary attraction between the solder 66 and the trace 60. As a result, the solder 66 ends up being displaced with respect to the pad 62, as indicated in FIG. 11. In particular, the solder may abut the solder mask edge 64. Generally, the solder does not extend onto the solder mask since the mask functions to control solder flow.
Thus, improper contact may result between the solder and the solder pad 62 as a result of the wicking action of the solder. Of course, this problem may be reduced by decreasing the diameter of the opening 64 in the solder mask. However, this creates tighter tolerances in the process flow. One adverse result may be that the solder mask opening is misaligned to the pad 62 to such an extent that the solder mask opening does not permit the solder to be placed on the pad.
In ball grid array (BGA) packaging techniques an array of solder pads may be aligned with an array of solder balls. If the balls tend to wick away from their solder pads, the balls may become misaligned with other balls in the array. Thus, there may be no way to cause an integrated circuit connector to appropriately connect to all the balls because all the balls have been randomly misaligned. Referring to FIG. 12, the ball 68 on the top has wicked to the right because its trace 60 extends to the right whereas the ball 76 on the bottom has wicked to the left because of the leftward extension of its trace 70. The center line "CL" of the pads 62 and 72 may have been the projected alignment between the balls. In fact the balls are substantially misaligned.
Still another problem that may arise in the prior art is the surface action effects of the edge of the solder resist mask. FIG. 13 illustrates a conventional solder mask defined pad (SDP). In this case, the useful portion of the pad 80 is effectively defined by the opening 82 in the solder mask. This is because the size of the opening 82 is less than the size of the pad 80. Thus, wicking along the trace 78 may be prevented. However, the mask may tend to attract the solder 84 to its edge, for example as a result of surface attraction effects. Again, the problem is similar to the problem described previously in that the solder tends to be attracted away from its desired location.
Thus, there is a need for better ways to appropriately position solder on bond pads coupled to conductive traces.

Positioning flowable solder for bonding integrated circuit elements


A filter system for reflectively blocking laser radiation in the visible spectrum includes a multilayer interference structure arranged for reflectively blocking a continuous band of wavelengths including the laser radiation and transmitting other wavelengths in the visible spectrum. The filter system is arranged to control transmission of the other wavelengths of the visible spectrum such that the filter system has an essentially neutral transmission color and maximum photopic transmission consistent with the band of wavelengths reflectively blocked.

The present invention relates to narrow-band, reflective, multilayer, interference filters for blocking (reflecting) passage of laser or near-monochromatic radiation having a wavelength in the visible portion of the electromagnetic spectrum (visible wavelength), while transmitting other visible wavelengths. The invention is related in particular to such a filter wherein layers thereof are arranged such that the transmission characteristic of the filter is color neutral.
Narrow-band, reflective, multilayer, interference filters are extensively used in many types of laser-based direct-vision optical systems for protecting the eyes of a user from damage by stray laser radiation. One particular type of laser-based system in which such filters are employed is a laser surgery system which delivers laser radiation to a surgical site on a patient for tissue ablation, incision, cautery, or the like, while permitting a surgeon operating the system to observe the site and its surroundings during the operation.
In order to permit maximum transmission through such a filter it must be designed to reflect over as narrow a bandwidth as possible. Because of this, the filter typically has more individual layers and is of much greater thickness than a multilayer laser-cavity reflector which has no other requirements than an ability to reflect a particular laser wavelength to a desired degree.
A particular problem with prior art visible-wavelength laser blocking filters is that their reflection bandwidth, while significantly narrower than a conventional highly reflecting multilayer laser reflector, still blocks visible light at longer and shorter wavelengths than the laser radiation wavelength. Because of this, light which is transmitted through such prior-art filters has a pronounced color. For example, a filter that blocks (green) laser radiation having a wavelength about 530 nanometers (nm) will have a pronounced magenta color. For a surgeon using a laser-surgery system including such a filter, a pronounced transmission color can provide difficulty in properly assessing conditions in a surgical site being treated. Additionally, prior-art reflective-laser blocking filters often have a relatively-low photopic transmission, for example, less than about fifty percent, as a result of too great a reflection bandwidth. This can further complicate assessment of treatment conditions.

Laser blocking filter with neutral transmission color


A switch calibration mechanism having a cam member that is rotatable about a longitudinal axis and that moves along said axis responsive to such rotation. A cam surface on the cam member cooperates with a cam follower on a movable calibrating member to adjust the operating point of a switch during longitudinal movement of the cam member.

This application relates to the art of switches and, more particularly, to calibration mechanisms for switches. The invention is particularly applicable for use in a temperature responsive switch and will be described with specific reference thereto. However, it will be appreciated that the invention has broader aspects and can be used in any switch requiring calibration.
Many temperature responsive switches require calibration to operate at a desired temperature. Calibration mechanisms are frequently complicated and difficult to adjust, and are sometimes unstable so that the desired calibration is lost. It would be desirable to have a relatively simple and inexpensive calibration mechanism that has good stability and is simple to adjust.


An image segmentation method system, the system comprising: a training subsystem configured to train a segmentation machine learning model using annotated training data comprising images associated with respective segmentation annotations, so as to generate a trained segmentation machine learning model; a model evaluator; and a segmentation subsystem configured to perform segmentation of a structure or material in an image using the trained segmentation machine learning model. The model evaluator is configured to evaluate the segmentation machine learning model by (i) controlling the segmentation subsystem to segment at least one evaluation image associated with an existing segmentation annotation using the segmentation machine learning model and thereby generate a segmentation of the annotated evaluation image, and (ii) forming a comparison of the segmentation of the annotated evaluation image and the existing segmentation annotation. The method includes deploying the trained segmentation machine learning model for use if the comparison indicates that the segmentation machine learning model is satisfactory.

Accurate segmentation and identification of a medical image are required for quantitative analysis and disease diagnosis. Segmentation is the process of delineating an object (e.g. an anatomical structure or tissue) in a medical image from its background. Identification is the process of identifying the object and correctly labelling it. Conventionally, segmentation and identification are performed manually or semi-manually. The manual method requires an expert with sufficient knowledge in the field to draw the contours of a targeted object and label the extracted object.
There also exist computer-aided systems provide semi-manual segmentation and identification. For example, such a system may detect the approximate contour of an object of interest based on selected parameters including intensity, edge, 2D/3D curvature, shape or other 2D/3D geometric characteristics. An expert then refines the segmentation or identification manually. Alternatively, an experts may provide such a system with input data, such as the approximate location of a targeted object; the computer-aided system then performs segmentation and identification.
Both manual and semi-manual methods are labour intensive and time-consuming. Moreover, the quality of the results relies heavily on the expert's expertise. Significant variations in the resulting segmented and identified objects can arise depending on operator/expert.
In the last few years, machine learning, especially deep learning (e.g. deep neural networks or deep convolutional neural networks) has outperformed humans in many visual recognition tasks, including in medical imaging.
WO 2018/015414 A1 discloses a method and system for artificial intelligence based medical image segmentation. The method includes receiving a medical image of a patient, automatically determining a current segmentation context based on the medical image, and automatically selecting at least one segmentation algorithm from a plurality of segmentation algorithms based on the current segmentation context A target anatomical structure is segmented in the medical image using the selected at least one segmentation algorithm.
U.S. patent application publication no. 2018/0240235 A1 discloses a method for segmentation of an image of a target patient, comprising: providing a target 2D slice and nearest neighbour 2D slice(s) of a 3D anatomical image, and computing, by a trained multi-slice fully convolutional neural network (multi-slice FCN), a segmentation region including a defined intra-body anatomical feature that extends spatially across the target 2D slice and the nearest neighbour 2D slice(s), wherein the target 2D slice and each of the nearest neighbour 2D slice(s) are processed by a corresponding contracting component of sequential contracting components of the multi-slice FCN according to the order of the target 2D slice and the nearest neighbour 2D slice(s) based on the sequence of 2D slices extracted from the 3D anatomical image, wherein outputs of the sequential contracting components are combined and processed by a single expanding component that outputs a segmentation mask for the target 2D slice.
U.S. Pat. No. 9,589,974 discloses a system and method for applying deep convolutional neural networks to medical images to generate a real-time or near real-time diagnosis or diagnostic recommendation. The method includes performing image segmentation of a plurality of medical images, the image segmentation comprising isolating a region of interest from each image; applying a cascaded deep convolutional neural network detection structure to the segmented images, the detection structure comprising: i) a first stage employing a first convolutional neural network to screen all possible locations in each 2D slice of the segmented medical images by a sliding window methodology to identify one or more candidate locations; and ii) a second stage employing a second convolutional neural network to screen 3D volumes constructed from the candidate locations by selecting at least one random location within each volume with a random scale and a random viewing angle to identify one or more refined locations and classifying the refined locations; and automatically generating a report comprising a diagnosis or diagnostic recommendation.
However, there are problems in applying such techniques to segmentation and identification of medical images: machine learning algorithms require ground truth data for training and validation, but this data is produced by human experts annotating the data—which is time-consuming and expensive; the improvement of machine learning models replies ideally on the addition of erroneous results (such as when the trained model fails in segmentation or identification of a medical image), but it is difficult to manage the training and retraining processes efficiently; a high number of training images (ideally more than a thousand) are difficult or impossible to obtain in some biomedical applications and, with limited training data, it is difficult efficiently to train a segmentation and identification model.

Method and system for image segmentation and identification


A characteristic point detection circuit detects a characteristic point from a base band video signal and generates a characteristic point file. A compressed video signal received from the digital satellite broadcast is supplied to a multiplexing circuit as it is in the form of a bit stream. The multiplexing circuit multiplexes the compressed video signal and characteristic point file. A control circuit obtains the characteristic point file from an optical disc during reproduction, and controls reproduction of the compressed video signal. As described herein above, the supplied compressed video signal is recorded in a recording medium without deterioration of the image quality, and the recorded video signal accepts random access.

1. Field of the Invention
This invention relates to an apparatus and method for recording, an apparatus and method for reproducing, an apparatus and method for recording/reproducing, a recording medium, and a distribution medium and more particularly to an apparatus and method for recording, an apparatus and method for reproducing, an apparatus and method for recording/reproducing, a recording medium, and a distribution medium which are suitably used for recording video signals and reproducing recorded video signals.
2. Description of Related Art
Recently, DVD-RAM has been proposed as a recordable optical disk. Such a recordable optical disk is proposed as a large capacity medium having several G bytes, and is promising as a medium for recording AV (Audio Visual) signals such as video signals.
As the supply source of digital AV signals which are possible to be recorded in a recordable optical disk, currently VHS or 8 mm video tapes and digital satellite broadcast are available, and in future, digital ground wave television broadcast will be available.
Digital video signals supplied from such sources are generally compressed according to MPEG (Moving Picture Experts Group)-2 system. Therefore, when a digital video signal supplied from such source is recorded in the recordable optical disk, a video signal compressed according to MPEG-2 system is once decoded, then encoded according to MPEG-2 system, and recorded in the recordable optical disk.
However, such processing including decoding, encoding, and subsequent recording in an optical disk results in deteriorated image quality of the recorded video signal.
In order to minimize the deterioration of image quality, a method in which a supplied bit stream is recorded as it is in a recordable optical disk without encoding and decoding a compressed video signal supplied from a source has been developed. In other words, the method in which the optical disk is used as a data streamer has been developed.
There is no management data for random access to a recorded bit stream in the recordable optical disk in which a video signal is recorded without encoding and decoding as described herein above. In detail, in the optical disk in which the video signal is recorded as described herein above, no management information for indicating a sector position where the provided program starts is recorded. Therefore, in the case of an optical disk in which a bit stream from a source as described herein above is recorded as it is, random access to the recorded video signal is impossible, the greatest advantage of a disk type recording medium is limited.
If an optical disk in which a bit stream formed by encoding an analog input in a recording apparatus is recorded is distinguished from an optical disc in which a bit stream supplied from a source is recorded as it is, the recording/reproducing apparatus involves two types of optical disk resultantly, such mechanism leads to high cost.

Encoded signal characteristic point processing apparatus


A method of connecting an optical fiber to a planar optical waveguide is provided in which an end face of a waveguide chip in which planar optical waveguides are formed is abutted against an end face of a fiber aligning jig on which optical fibers are arranged, to thereby connect the optical fiber to the corresponding planar optical waveguide. At least one marker is formed in each of the waveguide chip and the fiber aligning jig, and also at least one pin guide groove is formed in each of the waveguide chip and the fiber aligning jig, using the marker as a reference mark. The markers of the waveguide chip and the fiber aligning jig are aligned with each other along optical axes of the planar optical waveguides when the waveguide chip and the fiber aligning jig are abutted against each other. Further, fiber guide grooves are formed in the fiber aligning jig, using the marker as a reference mark. The waveguide chip and the fiber aligning jig are abutted against each other, and the planar optical waveguide and the optical fiber are aligned with each other by means of a common guide pin laid along the corresponding pin guide grooves.

1. Field of the Invention
The present invention relates to a method of connecting an optical fiber to a planar optical waveguide, and more particularly, to a connection method which permits easy, low-loss connection of an optical fiber to one of planar optical waveguides formed in an optical component.
2. Description of Related Art
When constructing an optical communication system, optical waveguide chips are used as optical components. Optical waveguide chips are generally classified into those in which silica glass is deposited on, e.g., a Si substrate whose refractive index is different from that of the silica glass, to form planar optical waveguides, and those in which semiconductor thin films of various compositions are successively formed on a special semiconductor substrate of, e.g., InGaAsP, to form planar optical waveguides.
In order for an optical waveguide chip to properly function as an optical component in an optical communication system, optical fibers are connected to the planar optical waveguides formed in the optical waveguide chip, with each axis thereof aligned with each axis of the planar optical waveguides, so that light can be transmitted from one optical fiber to the other through the planar optical waveguide.
In general, optical fibers are connected to planar optical waveguides in the following manner: First, the optical waveguide chip is positioned and fixed in a specific casing, and an optical fiber is abutted against one end of the planar optical waveguide. With light entered from the other end of the planar optical waveguide, the optical fiber is shifted relative to the planar optical waveguide, and while the optical fiber is located at a position where the intensity of light transmitted therethrough is a maximum, the fiber is firmly bonded to the planar optical waveguide by an adhesive or the like.
Subsequently, another optical fiber is connected to the other end of the planar optical waveguide in a similar manner. Namely, with light transmitted through the previously connected optical fiber, the optical fiber to be connected is positioned and bonded to the planar optical waveguide.
In the connection method described above, there is employed no particular mechanical member which keeps each axis of optical fiber aligned with each axis of the planar optical waveguides formed in an optical waveguide chip, for preventing unwanted movement after axis alignment procedures. Thus, the connection reliability is low, possibly causing an increase of the connection loss, when the connection is subject to temperature variation or external stress.
Further, the above connection method requires considerable time for the abutting of the optical fiber onto the planar optical waveguide, preparations for the transmission of light to the optical fibers, preparations for the measurement of the intensity of output light, etc. In addition, expensive apparatuses are needed for the positioning of the optical fibers and the optical waveguide chip.

Method of connecting an optical fiber to an optical waveguide


A shutoff valve assembly which includes a valve body comprising a first and second flanged sections disposed on opposite sides of a main flow chamber; a disc seat disposed within the valve body a shutoff disc having a diameter substantially the same as the outer diameter of the disc seat; a disc shaft perpendicularly disposed within a sidewall of the valve body and mechanically affixed to the shutoff disc at a recessed portion of the inner surface of the valve body such that the disc does not restrict fluid flow, provide turbulence or cause a pressure drop while in the open position, the disc shaft having an inner end disposed within the valve body and an outer end disposed external of the valve body, the inner end being a terminal end and the outer end being sealed by means of a packing gland which prevents leakage of fluid from the shutoff valve; a positive spring actuator assembly comprising a lever attached to the disc shaft, a spring connected to the lever which is capable of rotating the disc shaft about its axis, and a fail safe fusible link connected to the lever means in such a manner that the disc is in an open position during normal operations and closed when the fusible link is severed due to increased external temperatures or mechanically released; and an external bypass valve capable of directing the fluid flow from one side of the disc to the opposite side when the disc is in the closed position.

In the design and construction of fuel hydrant pits it is highly desirable, and in most instances mandatory, that an emergency shutoff valve be disposed between the hydrant riser and the hydrant valve. Conventional fusible link valve assemblies include a valve body, a shutoff disc, a disc seat, a disc shaft, a positive spring actuator assembly, and a bypass valve.
One disadvantage of conventional valves is that their discs are sealably connected to the disc shaft by means of various o-rings disposed about the disc shaft on both sides of the disc mount. The o-rings would melt from the heat of a fire, and hence be destroyed, such that fluid would leak out from the disc shaft and feed the fire. Still another problem resides in the disc mount design itself which in conventional valves causes the shutoff disc to protrude into the fluid flow path while in the open position, thereby restricting fluid flow, creating turbulence and increasing the pressure drop between the hydrant riser and the hydrant valve.
It would be most desirable to design a fusible link shutoff valve which does not leak during normal operations, a valve which is capable of allowing the fluid flow to be bypassed externally when the valve is in the closed position, and a valve which provides unrestricted fluid flow, no turbulence and low pressure drop.
The present invention also provides many additional advantages which shall become apparent as described below.


The SOFC of the present invention has a plurality of individual solid oxide fuel cells (84) disposed within an generating chamber (10), a fuel supply unit (38) for supplying fuel to the individual solid oxide fuel cells, a temperature sensor (142) for measuring the temperature of the generating chamber (T1), and a control section (110) for changing the amount of fuel supplied in response to an amount of generation required based on control characteristics for supplying fuel, wherein the control section is furnished with a temperature band for monitoring purposes, having a minimum temperature value (Ta) and a maximum temperature value (Tb) for adaptive control, predetermined based on a minimum amount and maximum amount of rated electrical generation, and a maximum temperature value for adaptive control in response to anomalies, which is higher than the maximum temperature value (Tb) of the adaptive control temperature band, and a minimum temperature value for adaptive control in response to anomalies, which is lower than the minimum temperature value (Ta) of the adaptive control temperature band, and the control section is furnished with: an anomaly response control section for executing anomaly response control by restricting operation of the fuel cell when the generating chamber temperature (T1) is higher than the maximum temperature value for anomaly response control or lower than the minimum temperature value for anomaly response control, and with an adaptive control section for executing adaptive control by correcting the amount of fuel supplied based on a temperature signal from the temperature measurement sensor so that the generating chamber temperature (T1) is kept within the temperature band when the generating chamber temperature (T1) exceeds the minimum temperature value (Ta) or maximum temperature (Tb) for adaptive control and goes outside the temperature band.

Solid oxide fuel cell device ("SOFC" below) is a fuel cell device for generating electricity by causing an electrical generating reaction to take place at a relatively high temperature using an oxide ion electrically conductive solid electrolyte as an electrolyte, with electrodes attached on both sides thereof, and with fuel gas supplied to one side thereof and an oxidant (air, oxygen, etc.) supplied to the other side thereof.
In such SOFC, steam or CO2 is produced by the reaction between oxygen ions passed through the oxide ion conducting solid electrolyte with the fuel, thereby generating electrical and thermal energy. The electrical energy is extracted from the SOFC, where it is used for various electrical purposes. At the same time, thermal energy is transferred to the fuel, SOFC, oxidant, etc., and used to raise the temperature thereof.
It was common in the conventional SOFC to operate in a state whereby electrical generation output was held fixed, but when the SOFC is installed in facilities where there is virtually no electrical demand at night, or where there are large changes in electrical demand between day and night, etc., there is a need to vary the electrical generation output value in accordance with the amount of electrical generation required.
Patent Document 1 proposes an SOFC in which the SOFC operating condition can be stabilized in a short time period by controlling the SOFC to prevent sudden changes in SOFC reaction temperature when the electrical generation value is changed in accordance with the amount of electrical generation required.
In other words, in the SOFC of Patent Document 1, sudden changes in SOFC reaction temperature can be prevented by controlling the amount of oxidant supply and/or the oxidant temperature so that the SOFC reaction temperature T0 prior to the change in generation output at SOFC reaction temperature T satisfies "T0−10≦T≦T0+10."


Systems and methods are provided for amplifying a composite input signal, comprising a drive signal and an envelope signal, at a power amplifier. A secondary modulation, representing a portion of the composite input signal falling outside of a frequency band associated with the envelope signal, is produced for the drive signal. The secondary modulation is applied to the drive signal. The drive signal is amplified at the power amplifier to produce an amplified signal. At least a portion of the envelope signal is employed to drive a supply terminal of the power amplifier.

RF power amplifiers used for wireless communication transmitters require high linearity to preserve modulation accuracy and to limit spectral regrowth. Linear amplifiers are capable of electrical (DC power in to RF power out) efficiencies greater than fifty percent when operated at saturation. However, they are generally not operated at an optimal level of efficiency due to the need to provide high linearity. For constant envelope waveforms, linear amplifiers are often operated below saturation to provide for operation in their linear region. Time varying envelopes present an additional challenge.
One technique for enhancing the efficiency of an amplifier system is Envelope Elimination and Restoration (EER). The EER technique detects the envelope of the incoming signal to produce an amplitude modulated (AM) component of the incoming signal and a phase modulated (PM) component with a constant envelope. The PM signal component is provided to the input of the power amplifier along a PM path and the AM component is employed to modulate the supply of the power amplifier along an AM path. Since the signal input into the power amplifier has a constant amplitude envelope, a more efficient class of power amplifier can be employed to amplify the input signal. Additionally, since the supply signal changes with the desired power of the amplified signal, the amplifier can be operated at compression enhancing the efficiency of the amplifier.

Enhanced bandwidth envelope elimination and restoration


A method is disclosed for treating an area on a surface to increase affinity for a fluid including organic light emitting diode (OLED) material.

Displays for electronic equipment such as personal computers and digital cameras can make use of organic light emitting diode (OLED) technology. When electrical current is applied to an OLED, a bright light can be emitted, by a process of electroluminescence.
A difficulty in mass-producing displays using OLED technology is depositing the OLED material in the precise locations where the pixels should be located.

Hewlett-Packard Development Company, L.P.


On a wafer that includes multiple distinct designs in each die region, a memory is included in each die region. The memory stores information specific to the design implemented in the same die region. Such stored information may include a circuit design identifier or a proprietary technology identifier. Such identifiers minimize IC confusion and aid in tracking usage of proprietary technology.

The present invention relates to configurable integrated circuits, such as ASICs and gate arrays, and particularly, the invention relates to electronic identification of configurable integrated circuit designs.
Configurable integrated circuits are integrated circuits (ICs) that are customized and fabricated to meet the specific needs of a particular user, typically an IC designer. Configurable ICs include application-specific integrated circuits (ASICs), such as gate arrays which are partially customizable, and standard cells which are completely customizable by a user of such circuits.
In particular, gate arrays are popular among IC designers as a generally economical way of creating unique ICs for use in their electronic designs. Gate arrays are generally composed of a predefined matrix (or array) of function blocks, which can be formed into a specific, unique circuit by interconnecting the function blocks. Because gate arrays are already predesigned and often prefabricated up to the point where a user can customize them, gate arrays are often used as low-cost prototypes in the electronics design process.
The fabrication of configurable ICs is usually done on a silicon wafer. The wafer is divided into multiple die, where each die is eventually separated from the rest of the wafer to become an individual IC. Once the die have been separated, the die are tested and packaged.
Typically a single IC design is placed on a wafer. In other words, the same design is placed in each die on the wafer. Placing different IC designs into the distinct die on the wafer is generally undesirable because the die are not always easily visually distinguishable. IC designs become easily confused and mixed together during the testing and packaging process.
Frequently, an IC designer using a configurable IC will only require very few configurable ICs to be manufactured and customized for their use, especially when the IC is to be a prototype. It is not unheard of that IC designers require only one prototype to be manufactured. IC designers often do not need (or want to pay for) the multiple ICs that are formed as a result of placing the designer""s design into each die on the wafer.
If the IC designer desires only one custom IC, however, as a prototype or for another low volume production reason, the manufacturer is faced with two choices: (1) either place only one design on a wafer, or (2) place multiple distinct designs on a single wafer. The first option, placing only one design on a wafer, is expensive and wasteful for the manufacturer. Further, if the configurable IC is sold based on charging the IC designer low fees for prototypes, it becomes strongly desirable to place multiple designs on a wafer so that the cost of producing the prototypes for the new design may be shared with other designs.
Still, if the manufacturer cannot identify which design is included on which die, placing multiple designs on a wafer will become burdensome and drive costs upward. Accurate testing and packaging may not occur or the IC designer may not receive the correct design. Hence, most manufacturers that are involved in low volume production of particular designs try to avoid placing multiple designs on a single wafer.
To minimize the burdens of fabricating multiple distinct IC designs on a single wafer, a small memory is included in each die region. In one embodiment, the memory is a mask-programmed ROM. The memory stores information specific to the design included in the particular die region. For instance, the. memory may include a circuit design identifier in one embodiment. In another embodiment, the memory may include a customer identifier. Once the fabrication process is complete and the die separated from the wafer, the memory can be electronically read to identify the circuit design included. In this manner, design misidentification is minimized. The design identifier can further be used to select test patterns for use in testing the IC.
In still other embodiments of the invention, proprietary technology identifiers are stored in the memory. These proprietary technology identifiers are useful for identifying any proprietary technology that may be incorporated in the circuit design. Such information is particularly useful to owners/licensors of the proprietary technology in tracking where and by whom the proprietary technology is being utilized.

Design information memory for configurable integrated circuits


Disclosed is a bonding method for dissimilar materials made from metals and its resulting structures. The materials to be bonded are formed by layering three or more sheets such that a dissimilar material interface and a same material interface are formed. A first current is conducted between a three-sheet layered plate material wherein an aluminum alloy plate, a zinc plated steel plate and a bare steel plate, for example, are layered in order. A nugget is formed in an interface between the zinc plated steel plate and the bare steel plate, which are the same materials. Then, a second current greater than the first current is conducted, and a nugget is formed in an interface between the aluminum alloy plate and the zinc plated steel plate.

When bonding dissimilar metals, if the bonding process used is the same as that used for bonding the same materials, then sufficient seam strength cannot be obtained since a weak intermetallic compound is formed. For example, when an aluminum alloy and a steel material are bonded, weak intermetallic compounds having high hardness such as Fe2Al5 or FeAl3 are formed. It is necessary to control such intermetallic compounds so as to secure the seam strength.
However, a fine and rigid oxide coating is formed on a surface of the aluminum alloy. To remove such a coating, it is necessary to provide a large amount of heat at the time of the bonding operation. As such, a thick intermetallic compound layer grows, which may then cause a problem as the strength of the bonded portion becomes weak.
Thus, when using a combination of such dissimilar metallic materials, the dissimilar materials have been traditionally bonded through a mechanical fastening operation by means of a bolt, rivet, etc. However, this results in an increase of weight or cost. For the bonding operation of such dissimilar metals, a friction pressure bonding is utilized in some components. However, such a friction pressure bonding operation is limitedly used in a bonding operation between rotation bodies having a desired symmetry, etc. Thus, its application is quite limited. Bonding operations such as explosion bonding or hot rolling are well known. However, such operations have facility and efficiency problems, making it difficult to broadly apply such operations to conventional dissimilar metals.
Japanese Laid-Open Patent Publication No. (Hei) 4-127973 discloses a method of performing a resistance welding operation with a current conducting time equal to or less than 10 ms. Such a method is performed when a clad material formed of two types of materials that are same as the dissimilar metals is interposed between the dissimilar metallic materials to be bonded. This is so that the same materials are bonded to each other.
However, in this method, three sheets of the plates are required where two sheets of the plates would have been required. When considering actual manufacturing, fixating the clad material is required in addition to inserting the clad material. Further, new equipment should be assembled in an established welding line, thereby causing a cost increase. Moreover, when bonding aluminum and steel, since the aluminum clad steel itself is manufactured by bonding the dissimilar materials to each other, manufacturing conditions become critical. Thus, it is difficult to obtain a cheap clad material with a stable performance.
Japanese Laid-Open Patent Publication No. (Hei) 6-39558 discloses a method of bonding materials comprising plating aluminum alloy having Al content equal to or more than 20 wt % or pure aluminum on a surface of the steel, contacting the steel with the aluminum material such that the aluminum alloy or pure aluminum has a thickness equal to or more than 2 μm, conducting the current by layering such a plating surface on the aluminum material, preferably fusing the plating layer and hardly fusing the steel material side.
This aluminum plating operation requires a large amount of heat in order to destroy a rigid oxide coating on the surface of the steel at the time of bonding the aluminum plating surface and the aluminum material. Thus, a weak intermetallic compound is formed on an interface between the aluminum plate and the steel, increasing the likelihood that the bond will fail.
When resistance welding three or more sheets of dissimilar material, both the dissimilar material interface and the same material interface are present at the same time. When the resistance heating of the dissimilar material interface is less than the resistance heating of the same material interface, a nugget is formed on the same material interface due to the difference in the resistance heating, while hardly forming on the dissimilar material interface. In such a case, in order to obtain sufficient bonding strength in each of the interfaces, it is necessary to provide enough heat for the nugget to have the desired diameter on the dissimilar material interface side. However, when the necessary heat is provided to produce a large enough nugget on the dissimilar material interface, the resistance heating in the same material interface becomes excessive. Thus, the thickness decreases by such a resistance heating in a low melting point side material, i.e., the aluminum material side in the above-mentioned bonding example of the aluminum and the steel.

Bonding method of dissimilar materials made from metals and bonding structure thereof


The present disclosure describes techniques for DVD-RAM header or land/groove detection. In some aspects, a wobble signal is integrated, an offset is removed from the integrated wobble signal, and a header is detected in the non-offset integrated wobble signal. In some aspects, a threshold value is adjusted based on a comparison of the received wobble signal and the threshold value, and a header is detected based on the adjusted threshold value.

The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Optical storage media, such as digital versatile discs (DVDs), are an effective solution for storing data. DVD media is typically low cost, re-writable, portable, and compatible with most optical drive-equipped devices. Data of a DVD is stored as pits or marks on circular land and groove tracks that an optical head can read, write, and/or re-write as the disc rotates. The land and groove tracks of a DVD may be spiral or concentric depending on the type of the DVD.
Discs employing concentric tracks, such as DVD-random access memory (DVD-RAM) discs, can include embossed headers to address data and indicate whether the data lies in a land track or groove track. A signal provided by the optical head can be analyzed to detect and read header information. The optical head is configured and positioned for reading and/or writing data to a particular land or groove track based on the header information. The signal provided by the optical head, however, can include noise, an offset, and/or various disruptions making header and land/groove detection difficult and complex. Failing to properly detect a header, or incorrectly interpreting noise as a header, degrades performance of a DVD-RAM drive as the information needed to configure and position the optical head is unavailable or incorrect.


An improved method of addressing devices in a local area network is disclosed. A small plug-in tag may be added to each device on the network. The tag is given an easily remembered name provided by the user. In addition the tag can be given a pictorial icon which can be represented by a moderate number of bits. The name and the optional icon may be visible on a label on the tag. The tag contains a chip with a small memory into which the name and optionally the bit map representation of the icon is entered. In addition, an optional unique identifier may be entered. Pins on the tag are connected to the device which has its own network address, such as an Ethernet address. Optionally, the network address may be copied into the unique identifier, or the unique identifier may be copied into the network address. The use of the tag permits easy configuration and reconfiguration of the network. The invention is particularly applicable in home or small office networks where computer-knowledgeable persons are not available to perform configuration functions.

The present invention relates to the networking of devices, in particular to methods by which devices are addressed in a local area network.
In a communication network such as a local area network (LAN), devices communicate with each other by sending digital messages. Devices may include printers, storage units, computers, controllers, and others. A typical LAN is one conforming to Ethernet standards. See, e.g., IEEE 802.3 Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, and related standards. When more than two devices are present, it is necessary that each device be addressable so that messages may be directed to it. A network address is commonly entered into a device during its manufacture, in particular into an interface card of the device. The address is generally unchangeable. It may be considered to be analogous to a serial number, in that at least ideally no two devices have the same address. However the uniqueness of addresses is difficult to enforce, and typically some devices somewhere will have a common address. In an Ethernet application, the network address is a 48-bit sequence which does not correspond to any name that can be readily remembered by a user. Any device on the Ethernet network that wishes to send a message to another device uses that other device's network address as the destination part of the message header.
A key process that must take place upon initial set-up of the network or upon reconfiguration is the learning of the addresses of all devices that may participate in communications. When new devices are installed on a network, it is necessary for each device, including those previously installed, to ascertain the network addresses of the devices with which it communicates. It is also highly desirable to be able to assign easily remembered names to the devices. One particular computer on the network typically begins the process by issuing a request message using a global address, or a partially global address to devices of a particular type, such as all printers or printers of a particular type. All devices that recognize that address respond giving, among other information, their network addresses. After the computer receives the network addresses of all new devices, the user of that computer then assigns names to each device. A message is sent to each new device giving its assigned name, and that name is stored in a register in the device. A translation is entered in the originating computer so that future references to a user assigned device name causes that device's network address to be entered as destination into the header of messages to that device. For subsequent operations of this address discovery process, each device returns its assigned name along with the network address.
In Ethernet networks controlled by an Apple computer, address discovery is performed by the Name Binding Protocol [G. S. Sidhu, R. F. Andrews, and A. B. Oppenheimer, "Inside Apple Talk", Addison-Wesley, 1990, pp. 7-4 to 7-17]. Here the name includes three fields, and generic or global values are permitted in each. One field is the name itself. Another field is the device type. The final zone field is set to a null value for a simple Ethernet network. The protocol begins with a message with a global name and either global or specific type. All devices that satisfy that specification respond, giving their addresses. The next step in the process is a message to each device giving it its assigned name. That name is then entered into the memory of the device. Subsequent replies to address discovery messages include the name in addition to the address. A somewhat similar procedure is performed in networks using the Internet Protocol (IP) by the Address Resolution Protocol [S. A. Thomas, "IPng and the TCP/IP Protocols", John Wiley & Sons, 1995, pp. 132–137]. See, e.g., D. Plummer, "An Ethernet Address Resolution Protocol," IETF Network Working Group, RFC 826 (November 1982).
The current procedures for address administration as described above may cause difficulties, particularly for users who are not adept at computer operations. This is especially likely to be true in a home or small business environment. The user operations necessary to assign and distribute device names are difficult ones. A further problem arises when a device is moved to a different location and it is desired to change that device's name to correspond to the new location. The user must again go through the difficult procedure of name assignment. If the user neglects to do this, as is likely, then the device will retain its previous name, which may now indicate a wrong location.
An additional problem arises when network addresses are not unique. This is particularly serious in a mobile network, or when the local area network is connected to a global network, such as the Internet, where addresses are expected to be unique globally.

Electronically readable name tags for network communications


Methods of activating an apo-peroxidase are provided. The methods include the steps of providing a solution comprising an apo-peroxidase and a heme choline ester, hydrolyzing the heme choline ester with a choline esterase, and converting the apo-peroxidase to active peroxidase. The methods disclosed herein also provide for detecting the presence of an analyte in a sample. The methods include providing a binder capable of specifically binding the analyte wherein the binder is attached to a solid surface, applying the sample to the solid surface under conditions that permit binder-analyte binding, adding a choline esterase-conjugated binder that binds to the analyte, adding an apo-peroxidase, a heme choline ester, a peroxide, and a peroxide-activated signal generator, and detecting the signal produced by the peroxide-activated signal generator. An associated kit and components are also provided.

Single-stage enzyme-linked immunosorbent assays (ELISA) are commonly used for the qualitative or quantitative determination of an analyte. In this process an analyte is affixed to a surface and an antibody, specific for the analyte, is added. The antibody is covalently linked to an enzyme or can itself be detected by a secondary antibody or streptavidin or avidin, which is linked to an enzyme through bioconjugation. An enzymatic substrate is then added to produce a signal, such as color change, fluorescence or luminescence, which indicates the quantity of analyte in the sample. Since a single enzyme reacts with more than one enzymatic substrate, the signal is amplified and thereby increases the sensitivity of the analysis.
Successive enzymatic reactions can also be employed to increase the amplification effect. A first enzyme is used to generate multiple copies of a second enzyme, which in turn produce multiple copies of a detectable species such as an optical agent, a fluorescent dye, or a luminescent agent. In this manner signal amplification is increased through the use of coupled enzymatic reactions.


One embodiment of the present invention provides a system that avoids write-after-write (WAW) hazards while speculatively executing instructions. The system starts in a normal execution mode, wherein the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint, defers the instruction, and executes subsequent instructions in an execute-ahead mode. During this execute-ahead mode, instructions that cannot be executed because of unresolved data dependencies are deferred, and other non-deferred instructions are executed in program order. If an unresolved data dependency is resolved during the execute-ahead mode, the system moves into a deferred mode wherein the system executes deferred instructions. While executing a deferred instruction, if dependency information for an associated destination register indicates that a WAW hazard potentially exists with a following non-deferred instruction, the system executes the deferred instruction to produce a result, and forwards the result to be used by subsequent instructions in a pipeline and/or deferred queue for the processor. The system does so without committing the result to the architectural state of the destination register. In this way, the system makes the result available to the subsequent instructions without overwriting a result produced by the following non-deferred instruction, thereby avoiding a WAW hazard.

1. Field of the Invention
The present invention relates to techniques for improving computer system performance. More specifically, the present invention relates to a method and an apparatus for avoiding hazards involving data dependencies in a processor that supports speculative program execution.
2. Related Art
Advances in semiconductor fabrication technology have given rise to dramatic increases in microprocessor clock speeds. This increase in microprocessor clock speeds has not been matched by a corresponding increase in memory access speeds. Hence, the disparity between microprocessor clock speeds and memory access speeds continues to grow, and is beginning to create significant performance problems. Execution profiles for fast microprocessor systems show that a large fraction of execution time is spent not within the microprocessor core, but within memory structures outside of the microprocessor core. This means that the microprocessor systems spend a large fraction of time waiting for memory references to complete instead of performing computational operations.
Efficient caching schemes can help reduce the number of memory accesses that are performed. However, when a memory reference, such as a load operation generates a cache miss, the subsequent access to level-two (L2) cache or memory can require dozens or hundreds of clock cycles to complete, during which time the processor is typically idle, performing no useful work.
A number of techniques are presently used (or have been proposed) to hide this cache-miss latency. Some processors support out-of-order execution, in which instructions are kept in an issue queue, and are issued "out-of-order" when operands become available. However, allowing instructions to issue out-of-order greatly increases the complexity of a processor, because the processor must provide mechanisms to avoid problems caused by data dependencies between instructions that execute out-of-order. These inter-instruction data dependencies give rise to a number of problems, such as read-after-write (RAW) hazards, write-after-write (WAW) hazards, and write-after-read (WAR) hazards.
Conventional out-of-order processors deal with RAW hazards by structuring an issue queue as a content-addressable-memory (CAM). Unfortunately, this type of CAM structure has a complexity that grows quadratically with the number of entries in the issue queue and the issue width of the processor. Moreover, performance considerations make it highly desirable to pick ready consumer instructions in the same cycle as producers make the data available. This factor along with the timing constraints introduced by higher clock frequencies limits the size of the issue queue to 128 or fewer entries, which is not sufficient to hide memory latencies as processors continue to get faster.
Conventional out-of order machines deal with WAW and WAR hazards through register renaming. In a system that supports register renaming, producer instructions specify architectural registers as their destinations, and these architectural registers are mapped by hardware onto unique physical registers. This eliminates WAW and WAR hazards, because the unique physical register cannot be overwritten by another producer instruction. Unfortunately, the register renaming circuitry is also structured as a CAM, which similarly has a complexity that grows quadratically with the number of entries in the issue queue and with the issue width of the processor. Furthermore, constraints on the number of physical registers which are available for register renaming purposes also limits the size of the issue queue.
Hence, what is needed is a method and an apparatus for hiding memory latency and dealing with data dependencies without the above-described drawbacks of existing processor designs.

This patent is subject to a terminal disclaimer.

Method and apparatus for avoiding write-after-write hazards in an execute-ahead processor