A single-crystal silicon layer is formed by graphoepitaxy from a low-melting-point metal layer which contains dissolved polycrystalline or amorphous silicon, or from a melt of a silicon-containing low-melting-point metal, using step differences formed on a substrate as a seed for the epitaxial growth. This single-crystal silicon layer is used as dual-gate MOSTFTS, or bottom-gate MOSTFTS, of an electrooptical device such as an LCD integrating a display section and a peripheral-driving-circuit section. This process enables production of a uniform single-crystal silicon thin-film having high electron/hole mobility at a relatively low temperature. The display section includes LDD-nMOSTFTs or pMOSTFTs having high switching characteristics and a low leakage current. The peripheral-driving-circuit section includes cMOSTFTs, nMOSTFTs, pMOSTFTs, or a combination thereof, having high driving ability.

The present invention relates to a method of producing an electrooptical device and also to a method of producing a driving substrate for such an electrooptical device, the method being particularly suitable for production of, for example, a liquid crystal display device having an active region and a passive region, wherein the active region including a thin-film insulating-gate field-effect transistor of dual-gate type (hereinafter referred to as dual-gate MOSTFT)or of a bottom-gate type (hereinafter referred to as bottom-gate MOSTFT) using a single-crystal silicon layer grown by graphoepitaxy on an insulating substrate. The bottom-gate MOSTFT includes both an inverse-stagger NSI type and an inverse stagger ISI type MOSTFTS.
Various types of active-matrix liquid crystal displays are known: for example, a liquid crystal display having a display section using amorphous silicon for TFTS and an IC for an external driving circuit; a liquid crystal display integrating a driving circuit and a display section using solid-phase-deposited polycrystalline silicon for TFTS, as disclosed in Japanese Patent Application Laid-Open No. 6-242433); and a liquid crystal display device integrating a driving circuit and a display section using excimer laser annealing polycrystalline silicon TFTs, as disclosed in Japanese Patent Application Laid-Open No. 7-131030.
Although these known amorphous silicon TFTs have high productivity, they are not suitable for production of p-channel MOSTFTs (hereinafter referred to as pMOSTFTs) due to a low electron mobility of 0.5 to 1.0 cm2/vxc2x7sec. Since a peripheral driving section using pMOSTFTs and a display section cannot be formed on the same substrate, the driver IC must be an external component, which is mounted by, for example, a tape automated bonding (TAB) method, causing an impediment to reduction of the cost. This configuration inhibits production of high-resolution devices. Furthermore, the electron mobility as small as 0.5 to 1.0 cm2/vxc2x7sec can produce only a small ON current; hence, the size of the transistors in the display section is inevitably large, resulting in a small aperture ratio of pixels.
Conventional polycrystalline silicon TFTs have an electron mobility of 70 to 100 cm2/vxc2x7sec and can facilitate production of high-resolution devices, so that liquid crystal displays (LCDS) which use polycrystalline silicon and which are integrated with driving circuits are becoming conspicuous. The above electron mobility, however, is insufficient for driving a large LCD of 15 inches or more, and thus ICs for an external driving circuit are still required.
TFTs using polycrystalline silicon formed by a solid-phase deposition process require annealing at a temperature of 600xc2x0 C. or more for ten or more hours and thermal oxidation at approximately 1,000xc2x0 C. to form a gate SiO2 layer, necessitating the use of a semiconductor production apparatus. Thus, the wafer size is limited to 8 to 12 inches and the use of expensive heat-resistant quartz glass is inevitable, causing an impediment to reduction in the cost. Thus, the use of such TFTs is limited to EVF and audiovisual (AV) projectors.
Polycrystalline silicon TFTs produced by excimer laser annealing have many problems, including unstable output of the excimer lasers, low productivity, increasing price of the apparatus with increasing size, low yield and low quality.
These problems are pronounced when large glass substrates having a side length of, for example, 1 meter are used.
It is an object of the present invention is to make it possible to produce an active matrix substrate incorporating a high-performance driver, as well as an electrooptical device which is typically a display thin-film semiconductor device using such an active matrix substrate, through a uniform deposition of a single-crystal silicon layer having high electron/hole mobility particularly in a peripheral-driving-circuit section.
It is also an object of the present invention to implement a structure in which a display section and a peripheral-driving-circuit portion are integrated, wherein the display section comprises an n-channel MOSTFT (referred to as xe2x80x9cnMOSTFTxe2x80x9d, hereinafter) or a pMOSTFT employing an LDD (Lightly Doped Drain) structure having high switching characteristic and operable with reduced leak current, or a complementary insulating gate field effect transistor (referred to as cMOSTFT) having high driving performance, while the peripheral-driving-circuit is constituted by a cMOSTFT, nMOSTFT, pMOSTFT or a combination thereof.
It is also an object to implement a large-size display panel having high image quality, high definition, narrow peripheral frame and high efficiency, while allowing the use of a large-sized glass substrate having a comparatively low distortion point, and while achieving a high yield and reduction in the production cost due to elimination of necessity for the use of expensive production facilities, as well as easy control of the threshold value which permits reduction in the electrical resistance to offer high-speed of operation and greater size of the display.
To these ends, according to one aspect of the present invention, there is provided a method of producing an electrooptical device having a first substrate, i.e., a driving substrate, carrying a display section provided with pixel electrodes, e.g., pixel electrodes arranged in the form of a matrix, and a peripheral-driving-circuit section provided on a periphery of the display section, a second substrate, i.e., a counter substrate, and an optical material such as a liquid crystal disposed between the first substrate and the second substrate, as well as a method for producing the driving substrate for such an electrooptical device; the method comprising the steps of: a gate-forming step for forming a gate portion including a gate electrode and a gate insulating film on one face of the first substrate; a step-forming step for forming a step difference on the one face of the first substrate; a layer-forming step for forming a polycrystalline or amorphous silicon layer having a predetermined thickness on the first substrate having the gate portion and the step difference and then forming a low-melting-point metal layer on or under the polycrystalline or amorphous silicon layer, or of forming a low-melting-point metal layer containing silicon on the first substrate having the step difference; a heating step for dissolving silicon of the polycrystalline or amorphous layer or of the low-melting-point metal layer into the low-melting-point metal layer by heating; a deposition step for depositing on the first substrate a single-crystal semiconductor layer by allowing the silicon of the polycrystalline or amorphous silicon layer or of the low-melting-point metal layer to grow by graphoepitaxy by a cooling treatment using as a seed the step difference on the substrate; a treating step for effecting a predetermined treatment on the single-crystal semiconductor layer, thereby forming a channel region, a source region and a drain region; and a step for forming a first thin-film transistor MOSTFT) of dual-gate type having the gate portions on the above and below the channel region and constituting at least part of the peripheral-driving-circuit section. In accordance with the present invention, the thin-film transistor may be either a field effect transistor (FET) or a bipolar transistor, and the FET may be either a MOSFET or a junction type.
The present invention offers the following remarkable advantages (A) to (G), by virtue of the use of a single-crystal silicon layer as a dual-gate MOSTFT of a peripheral driving circuit as a driving substrate such as an active matrix substrate or as a dual-gate MOSTFT of a peripheral driving circuit of an electrooptical device such as an LCD of the type having a display-driver integrated structure, wherein the single-crystal silicon layer is graphoepitaxially grown from a polycrystalline or amorphous silicon layer or from a low-melting-point metal layer using the step difference formed on the substrate as a seed.
(A) It is possible to produce an electrooptical device such as a display thin-film semiconductor device incorporating a high-performance driver, by virtue of the use of a single-crystal silicon layer having a high electron mobility of 540 cm2/vxc2x7sec or higher that has been grown by graphoepitaxy conducted by using as a seed the bottom corner of a step of a predetermined size and shape formed on a substrate. Preferably, the step is formed to provide an indented section having such a cross-section that both side faces of the indented section are perpendicular to the bottom or slanted to form a basilar angle of not greater than 90xc2x0 with respect to the bottom face of the indented section.
(B) Since the single-crystal silicon thin-film has high electron and hole mobility, single-crystal silicon top-gate MOSTFTs can form a structure having a display section and a peripheral driving circuit section integrated with each other, wherein the display section has nMOSTFTs, pMOSTFTS or cMOSTFTs having high switching characteristics and, preferably, a lightly-doped drain (LDD) structure that reduces leak current through reducing the electric field intensity, while the peripheral driving circuit includes cMOSTFTs, nMOSTFTs, pMOSTFTs, or a combination thereof, having high driving characteristics, whereby production of a large display panel with high quality, high definition, a narrow frame, and high efficiency is facilitated. In contrast to pMOSTFT that can hardly provide high hole mobility, the single-crystal silicon thin-film has high hole mobility and, therefore, a peripheral driving circuit for driving electrons and holes independently or in combination can be implemented and integrated with display TFTs of nMOS, pMOS or cMOS LDD-type. In a compact or small panel, either of a pair of vertical peripheral driving circuits may be omitted.
(C) In particular, the use of dual-gate MOSTFTs in the peripheral driving circuit makes it possible to obtain cMOS, nMOS or pMOSTFTs having driving power 1.5 to 2.0 times as large that obtainable with the use of single-gate TFTs, thus achieving higher performance and greater driving power of the TFTs, offering advantages particularly when TFTs having large driving power are to be used in a local portion of the peripheral driving circuit. For instance, this feature not only allows omission of one of a pair of peripheral vertical driver circuits but also enables the present invention to be advantageously applied to organic ELs and FEDS. Furthermore, the dual-gate structure can easily be changed to a top-gate type structure or a bottom-gate type structure through a selection of one of the upper and lower gates and, in addition, ensures safe operation even in the event of a failure in one of the upper.and lower gates because the other gate can safely be used.
(D) The polycrystalline or amorphous silicon layer can be formed by a plasma-enhanced or reduced-pressure CVD process at a substrate temperature of 100 to 400xc2x0 C., by using the above-mentioned step difference as a seed for the graphoepitaxy, and the low-melting-point metal layer can be formed by a vacuum evaporation process or a sputtering process and, in addition, the above-mentioned epitaxial growth of silicon can be achieved at a comparatively low heating temperature of, for example, 930xc2x0 C., so that the single-crystal silicon layer can be uniformly formed on the insulating substrate at a relatively low temperature of, for example, 400 to 450xc2x0 C.
(E) The method in accordance with the present invention does not include annealing at a middle temperature (approximately 600xc2x0 C.) for more than ten hours and excimer laser annealing that are required in solid-phase growth, thus offering a greater yield and reduction in the production cost due to elimination of the use of an expensive production facility.
(F) In the graphoepitaxy in the present invention, a single-crystal silicon thin-film having a variety of P-type impurity concentration and high mobility can be readily produced by adjusting the ratio of polycrystalline silicon or amorphous silicon to a low-melting-point metal, the heating temperature of the substrate, and the cooling rate, thus enabling easy control of the threshold voltage (Vth) of the device, which in turn enables the device to operate at a high speed due to reduced resistance.
(G) The low-melting-point metal layer containing polycrystalline or amorphous silicon when deposited may be doped with an adequate amount of Group III or V impurity, such as boron, phosphorus, antimony, arsenic, bismuth or aluminum, so that the type and the concentration of the impurity in the epitaxial single-crystal silicon, that is, the type (P-type or N-type) and the carrier concentration, are controllable.
In accordance with the present invention, it is preferred to form the aforementioned step difference in the insulating substrate or in a diffusion barrier such as a film of silicon nitride (referred to as SiN, hereinafter) or both in the insulating substrate and the diffusion barrier, so as to provide an indented section having such a cross-section that both side faces of the indented section are perpendicular to the bottom or slanted to form a basilar angle of not greater than 90xc2x0 with respect to the bottom face of the indented section, and to use this step difference as a seed for the graphoepitaxy of the single-crystal silicon layer. Preferably, the step difference is formed along at least one side of a device region including the channel region, the source region and the drain region of the first thin-film transistor. When a passive device such as a resistor is formed of the aforementioned single-crystal silicon layer, the step difference is formed along at least one side of the device region in which the resistor is formed.
The first thin-film transistor such as MOSTFT may be formed inside, outside or both inside and outside the indented section defined by the step difference.
The step difference may be formed by a dry etching process, such as a reactive ion etching process, and the polycrystalline or amorphous silicon layer is formed preferably by a low-temperature deposition process at a substrate temperature of 100 to 400xc2x0 C., for example, a reduced-pressure CVD process, a catalytic CVD process, a plasma-enhanced CVD process, or a sputtering process so that the thickness becomes several xcexcm to 0.005 xcexcm, followed by the deposition of the low-melting-point metal layer by a vacuum evaporation process or a sputtering process so that the thickness becomes several tens to several hundreds times the thickness of the polycrystalline or amorphous silicon layer, and then the aforesaid heating treatment is executed.
In this case, the low-melting-point metal layer may be formed above or below the polycrystalline or amorphous silicon layer formed by the low-temperature deposition process. Alternatively, the aforementioned low-melting-point metal layer containing silicon is deposited and then subjected to the heating treatment.
The substrate may be an insulating substrate, for example, a glass substrate or a heat-resistant organic substrate, and the low-melting-point metal layer may be formed of at least one metal selected from the group consisting of indium, gallium, tin, bismuth, lead, zinc, antimony and aluminum.
When the low-melting-point metal layer is formed of indium, this layer is heated preferably at 850 to 1,100xc2x0 C. and more preferably 900 to 950xc2x0 C. in a hydrogen-based atmosphere (pure hydrogen, a nitrogen-hydrogen mixture, or an argon-hydrogen mixture) to form an indium-silicon melt and, when the low-melting-point metal layer is formed of indium-gallium, this layer is heated preferably at 300 to 1,100xc2x0 C. and more preferably 350 to 600xc2x0 C. in a hydrogen-based atmosphere to form an indium-gallium-silicon melt, whereas, when the low-melting-point metal layer is formed of gallium, this layer is heated preferably at 400 to 1,100xc2x0 C. and more preferably 420 to 600xc2x0 C. in a hydrogen-based atmosphere to form a gallium-silicon melt. The substrate may be uniformly heated using an electrical furnace or a lamp or, alternatively, a predetermined region of the substrate may be locally heated using laser or electron beams.
With reference to FIG. 11, the melting point of the silicon-containing low-melting-point metal decreases as the content of the low-melting-point metal increases. The indium melt layer containing silicon, e.g., by 1 percent by weight, is formed at a substrate temperature of 850 to 1,100xc2x0 C. when indium is used, because such a substrate temperature facilitates use of glass having low heat resistance, such as crystallized glass, in addition to quartz glass, as a substrate. A gallium melt layer containing 1 percent by weight of silicon may be formed at a temperature of 400 to 1,100xc2x0 C. on any glass substrate.
When indium-gallium-silicon or gallium-silicon is used, a glass substrate having a low distortion point or a heat-resistant organic substrate can be used, so that a semiconductive crystalline layer can be formed on a large glass substrate having an area of, for example, 1 m2, which is inexpensive and can readily be prepared in the form of a rolled long glass sheet. A single-crystal silicon thin-film can be formed continuously or discontinuously on the long glass or organic substrate by the described process employing graphoepitaxy.
Since the components of the glass having the low distortion point rapidly diffuse into the upper layer, a thin diffusion-barrier layer composed of, for example, silicon nitride having a thickness of 50 to 200 nm is preferably formed to suppress such diffusion. Thus, the polycrystalline or amorphous silicon layer or a silicon-containing low-melting-point metal layer is formed on the diffusion-barrier layer.
The silicon-containing low-melting-point metal layer is slowly cooled so that the single-crystal silicon layer is deposited by graphoepitaxy using the step difference as a seed, and then the low-melting-point metal layer is removed by, for example, hydrochloric acid, followed by a predetermined treatment to form an active device and a passive device.
After the low-melting-point metal layer such as of indium deposited on the single-crystal silicon layer after the cooling is dissolved and removed by, for example, hydrochloric acid, only a trace amount (approximately 1016 atoms/cc) of indium remains in the silicon layer, so that the single-crystal silicon layer becomes a p-type thin-film semiconductor. This layer is advantageous for production of a nMOSTFT. An n-type impurity such as phosphorus may be ion-implanted into the entire surface or selective regions of the single-crystal silicon layer to form an n-type single-crystal silicon thin-film, whereby a pMOSTFT can also be obtained. A cMOSTFT can also be formed. The polycrystalline or amorphous silicon layer or the silicon-containing low-melting-point metal layer may be doped with a Group III or V impurity having a large solubility, such as boron, phosphorus, antimony, arsenic, or bismuth, in a proper amount, during the deposition of this layer so as to control the type and/or the concentration of the impurity in the epitaxially grown silicon layer, that is, to control the doping type (n- or p-) and/or the concentration of the carrier.
Accordingly, the single-crystal silicon layer grown by graphoepitaxy on the substrate is used as a channel region, a source region and a drain region of a dual-gate MOSTFT which constitutes at least a part of the peripheral driving circuit, the type and the concentration of each region being controllable, as described above.
Thin-film transistors in the peripheral-driving-circuit section and the display section may constitute n-channel, p-channel or complementary insulating-gate field-effect transistors: for example, a thin-film transistor may comprise a combination of a complementary type and an n-channel type, a complementary type and a p-channel type, or a complementary type, an n-channel type and a p-channel type. Preferably at least a part of the thin-film transistors in the peripheral-driving-circuit section and/or the display section has a lightly-doped drain (LDD) structure of a single type having a LDD section between the gate and the source or drain, or of a double type having LDD sections between the gate and source and between the gate and the drain, respectively.
Preferably, the MOSTFT constitutes an LDD-type TFT of an nMOS, a pMOS or a cMOS in the display section, and a cMOSTFT, an nMOSTFT, a pMOSTFT, or a mixture thereof, in the peripheral-driving-circuit section.
The MOSTFT is preferably formed on at least one of the interior and the exterior of the indented section of the substrate.
In such a case, the step difference is formed on one surface of the first substrate, and a single-crystal, polycrystalline or amorphous silicon layer is formed on the surface having the step difference. The single-crystal, polycrystalline or amorphous silicon layer is used as a channel region, a source region and a drain region of a second thin-film transistor, and at least one gate section is provided above and/or below the channel region. That is, the second thin-film transistor may be a top-gate, bottom-gate or dual-gate thin-film transistor.
In this case also, the step difference forms an indented section having a cross-section in which a side face is perpendicular to or slanted to the bottom face so as to have a basilar angle of preferably 90xc2x0 or less, and the step difference functions as a seed for graphoepitaxy of the single-crystal silicon layer.
The second thin-film transistor may be formed in a region including the indented section defined by the step difference formed in the first substrate and/or the film formed on the first substrate, and the graphoepitaxial single-crystal silicon layer may be used to form the source, drain and channel regions of the second thin-film transistor, as in the case of the first thin-film transistor.
In this second thin-film transistor also, the type and the concentration of the Group III or V impurity in the single-crystal, polycrystalline or amorphous silicon layer may be controlled as described above, and a step difference may be formed along at least one side of a device region including the channel region, the source region and the drain region of the second thin-film transistor. A gate electrode below the single-crystal, polycrystalline or amorphous silicon layer is preferably trapezoidal at the side end section. A diffusion-barrier layer may be provided between the first substrate and the single-crystal, polycrystalline or amorphous silicon layer.
The source or drain electrodes of the first and/or second thin-film transistors are preferably formed on a region including the step difference.
The first thin-film transistor may comprise at least the dual-gate type among a top-gate type having a gate section above the channel region, a bottom-gate type having a gate section below the channel region, and a dual-gate type having one gate section above and one below the channel region, and the switching device may comprise one of a top-gate second thin-film transistor, a bottom-gate second thin-film transistor and a dual-gate second thin-film transistor.
In this case, the gate section formed below the channel region in the bottom-gate or dual-gate second thin-film transistor preferably comprises a heat resistant material, and an upper-gate electrode of the second thin-film transistor and a gate electrode of the first thin-film transistor may comprise a common material.
The peripheral-driving-circuit section may comprise, in addition to the above-mentioned first thin-film transistor, at least one of a top-gate, bottom-gate or dual-gate thin-film transistor having a channel region of a polycrystalline or amorphous silicon layer and a gate region formed above or below the channel region, and may further comprise a diode, a resistor, a capacitor and an inductor, each comprising a single-crystal, polycrystalline or amorphous silicon layer.
Thin-film transistors in the peripheral driving circuit and/or the display section have a single-gate or a multi-gate configuration.
Preferably, when the n- or p-channel thin-film transistor in the peripheral-driving-circuit section and/or the display section is a dual-gate type, the upper or a lower-gate electrode is electrically opened or a given negative voltage for the n-channel type or a given positive voltage for the p-channel type is applied so that the dual-gate type thin-film transistors operate as bottom- or top-gate type thin-film transistors.
The thin-film transistor in the peripheral-driving-circuit section may be the first thin-film transistor of an n-channel, p-channel or complementary type, and the thin-film transistor in the display section may be an n-channel, p-channel or complementary type when the channel region is a single-crystal silicon layer, a polycrystalline silicon layer, or an amorphous silicon layer.
After the single-crystal silicon layer is deposited, an upper-gate section including a gate insulating film and a gate electrode may be formed on the single-crystal silicon layer, and the single-crystal silicon layer may be doped with a Group III or V impurity through the upper-gate section to form the channel region, the source region and the drain region.
When the second thin-film transistor is a bottom-gate type or a dual-gate type, a lower-gate electrode composed of a heat resistant material is provided below the channel region, and a gate insulating film is formed on the gate electrode to form a lower-gate section, and the second thin-film transistor is formed by the same steps including the step for forming the step difference as those in the first thin-film transistor. In such a case the upper-gate electrode of the second thin-film transistor and the gate electrode of the first thin-film transistor may be composed of a common material.
The single-crystal silicon layer formed on the lower-gate section may be doped with a Group III or V impurity to form a source region and a drain region, followed by an activation treatment.
The source and drain regions of the second thin-film transistor may be formed by ion-implantation of the above impurity on the single-crystal silicon layer through a resist mask and may be subjected to activation treatment, and the gate electrode of the first thin-film transistor, and the upper-gate electrode of the second thin-film transistor, if necessary, may be formed after the formation of the gate insulating film.
When the thin-film transistor is a top-gate type, the source and drain regions of the first and second thin-film transistors may be formed on the single-crystal silicon layer by ion implantation of the impurity through a resist mask and may be subjected to activation treatment, and then the gate sections including the gate insulating films and the gate electrodes of the first and second thin-film transistors may be formed.
Alternatively, when the thin-film transistor is of the top-gate type, the gate sections including the gate insulating films and the gate electrodes of the first and second thin-film transistors may be formed, and then the source and drain regions of the first and second thin-film transistors may be formed on the single-crystal silicon layer by ion implantation of the impurity through a resist mask, followed by an activation treatment.
The resist mask used when the LDD structure was formed may be left unremoved and the ion implantation for forming the source and drain regions may be performed through a resist mask which covers the remaining mask.
The substrate may be optically opaque or transparent, and may be provided with pixel electrodes for a reflective or transmissive display.
The display section may have a lamination configuration of the pixel electrodes and a color filter layer which may be formed on a display array, whereby the aperture ratio and the luminance are improved and costs can be decreased due to omission of a color filter substrate and improved productivity.
When the pixel electrodes are reflective electrodes, unevenness is preferably imparted to a resin film so that the resin film has optimized reflective characteristics and viewing-angle characteristics, and then the pixel electrodes are formed, whereas, when the pixel electrodes are transparent electrodes, the surface is preferably planarized by a transparent planarization film and then the pixel electrodes are formed on the planarized plane.
The display section is illuminated or dimmed by being driven by the above-described MOSTFT: for instance, the display section may comprise, for example, a liquid crystal display (LCD), an electroluminescent (EL) display, a field emission display (FED), a light-emitting polymer display (LEPD), or a light-emitting diode (LED) display. In this case, the arrangement may be such that a plurality of pixel electrodes are arranged in a matrix in the display section and a switching device is connected to each pixel electrode.
In accordance with a second aspect of the present invention, there is provided a method of producing an electrooptical device having a first substrate, i.e., a driving substrate, carrying a display section provided with pixel electrodes, e.g., pixel electrodes arranged in the form of a matrix, and a peripheral-driving-circuit section proivded on a periphery of the display section, a second substrate, i.e., a counter substrate, and an optical material such as a liquid crystald disposed between the first substrate and the second substrate, as well as a method for producing the driving substrate for such an electrooptical device, the method comprising the steps of:
a gete-forming step for forming a gate portion including a gaqte electrode andd a gate insulating filim on one face of the first substrate;
a step-forming step for forming a step difference on the one face of the first substrate;
a layer-forming step for forming a melt layer of a low-melting-point metal containing silicon on the first substrate having the gate portion and the step difference;
a deposition step for deposititing a single-crystal silicon layer by allowing the silicon of the melt layer to grow by graphoepitaxy by a cooling treatment using as a seed the step difference on the substrate;
a step for effecting a predetermined treatment on the single-crystal silicon layer, thereby forming a channel region, a source region and a drain region; and
a step for forming a first thin-film transistor (MOSTFT) of dual gate type having the gate portions on the above and below the channel region and constituting at least part of the peripheral-driving-sircuit section. In accordance with the second aspect of the present invention, the thin-film transistor may be either a field effect transistor (FET) or a bipolar transistor, and the FET may be either a MOSTFT or a junction type.
The second aspect of the present invention offers the following remarkable advantages (A) to (G), by virture of the use of a single-crystal silicon layer as a dual-gate MOSTFT of a peripheral driving circuit as a driving substrate such as an active matrix substrate or as a dual-gate MOSTFT of a peripheral driving circuit of an electrooptical device such as an LCD of the type having a display-driver integrated structure, wherein the single-crystal silicon layer is graphoepitaxially grown from a melt of a low-melting-point metal containing silicon using the step difference formed on the substrate as a seed.
(A) It is possible to produce an electrooptical device such as a display thin-film semiconductor device incorporating a high-performance driver, by virtue of the use of a single-crystal silicon layer having a high electron mobility of 540 cm2/vxc2x7sec or higher that has been grown by graphoepitaxy conducted by using as a seed the bottom corner of a step of a predetermined size and shape formed on a substrate. Preferably, the step is formed to provide an indented section having such a cross-section that both side faces of the indented section are perpendicular to the bottom or slanted to form a basilar angle of not greater than 90xc2x0 with respect to the bottom face of the indented section.
(B) Since the single-crystal silicon thin-film has high electron and hole mobility, single-crystal silicon top-gate MOSTFTs can form a structure having a display section and a peripheral driving circuit section integrated with each other, wherein the display section has nMOSTFTs, pMOSTFTs or cMOSTFTs having high switching characteristics and, preferably, a lightly-doped drain (LDD) structure that reduces leak current through reducing the electric field intensity, while the peripheral driving circuit includes cMOSTFTs, nMOSTFTs, pMOSTFTs, or a combination thereof, having high driving characteristics, whereby production of a large display panel with high quality, high definition, a narrow frame, and high efficiency is facilitated. In contrast to pMOSTFT that can hardly provide high hole mobility, the single-crystal silicon thin-film has high hole mobility and, therefore, a peripheral driving circuit for driving electrons and holes independently or in combination can be implemented and integrated with display TFTs of nMOS, pMOS or cMOS LDD-type. In compact to medium-sized panels, one of a pair of vertical peripheral driving circuits may be omitted.
(C) In particular, the use of dual-gate MOSTFTs in the peripheral driving circuit makes it possible to obtain cMOS, nMOS or pMOSTFTs having driving power 1.5 to 2.0 times as large that obtainable with the use of single-gate TFTS, thus achieving higher performance and greater driving power of the TFTs, offering advantages particularly when TFTs having large driving power are to be used in a local portion of the peripheral driving circuit. For instance, this feature not only allows omission of one of a pair of peripheral vertical driver circuits but also enables the present invention to be advantageously applied to organic ELs and FEDS. Furthermore, the dual-gate structure can easily be changed to a top-gate type structure or a bottom-gate type structure through a selection of one of the upper and lower gates and, in addition, ensures safe operation even in the event of a failure in one of the upper and lower gates because the other gate can safely be used.
(D) The melt of the low-melting-point metal is prepared at a temperature of, for example, 350xc2x0 C., by using the above-mentioned step difference as a seed for the graphoepitaxy, and the melt can be fromed on the substrate which is heated at a temperature slightly higher than the temperature of the melt by an application process, so that the single-crystal silicon film can be uniformly formed at a relatively low temperature of, for example, 300 to 400xc2x0 C.
(E) The method in accordance with the present invention does not include annealing at a middle temperature (approximately 600xc2x0 C.) for more than ten hours and excimer laser annealing that are required in solid-phase growth, thus offering a greater yield and reduction in the production cost due to elimination of the use of an expensive production facility.
(F) In the graphoepitaxy, a single-crystal silicon layer having a variety of P-type impurity concentration and high mobility can be readily produced by adjusting the composition ratio of the melt, the temperature of the melt, the heating temperature of the substrate, and the cooling rate, thus enabling easy control of the threshold voltage (Vth) of the device, which in turn enables the device to operate at a high speed due to reduced resistance.
(G) The melt layer of the low-melting-point metal containing silicon may be doped with an adequate amount of Group III or V impurity, such as boron, phosphorus, antimony, arsenic, bismuth or aluminum, so that the type and the concentration of the impurity in the epitaxial single-crystal silicon layer, that is, the type (P-type or N-type) and the carrier concentration, are controllable.
The step difference may be formed by a dry etching process, such as a reactive ion etching process, and the melt of the low-melting-point metal containing 2.0 to 0.005 percent by weight of, for example, 1 percent by weight of silicon may be applied to the heated insulating substrate and maintained for a predetermined period, for example, several to several tens of minutes, and then a cooling treatment may be performed. This can provide a single-crystal silicon layer having a thickness of several to 0.005 xcexcm, for example, 1 xcexcm.
The substrate may be an insulating substrate, for example, a glass substrate or a heat-resistant organic substrate, and the low-melting-point metal may comprise at least one metal selected from the group consisting of indium, gallium, tin, bismuth, lead, zinc, antimony, and aluminum.
When the low-melting-point metal comprises indium, the melt may be applied to the insulating substrate heated preferably at a temperature of 850 to 1,100xc2x0 C. and more preferably 900 to 950xc2x0 C. and when the low-meting-point metal comprises indium-gallium, the melt may be applied to the insulating substrate heated preferably at a temperature of 300 to 1,100xc2x0 C. and more preferably 350 to 600xc2x0 C., whereas when the low-melting-point layer comprises gallium, the melt may be applied to the insulating substrate heated preferably at a temperature of 400 to 1,100xc2x0 C. and more preferably 420 to 600xc2x0 C. The substrate may be uniformly heated using an electrical furnace or a lamp or, alternatively, a predetermined region of the substrate may be locally heated using laser or electron beams.
With reference to FIG. 11, the melting point of the silicon-containing low-melting-point metal decreases as the content of the low-melting-point metal increases. The indium melt layer containing silicon, e.g., by 1 percent by weight, is formed at a substrate temperature of 850 to 1,100xc2x0 C. when indium is used, because such a substrate temperature facilitates use of glass having low heat resistance, such as crystallized glass, in addition to quartz glass, as a substrate. A gallium melt layer containing 1 percent by weight of silicon may be formed at a temperature of 400 to 1,100xc2x0 C. on any glass substrate.
When indium-gallium-silicon or gallium-silicon is used, a glass substrate having a low distortion point or a heat-resistant organic substrate can be used, so that a semiconductive crystalline layer can be formed on a large glass substrate having an area of, for example, 1 m2, which is inexpensive and can readily be prepared in the form of a rolled long glass sheet. A single-crystal silicon thin-film can be formed continuously or discontinuously on the long glass or organic substrate by the described process employing graphoepitaxy.
While the substrate is cooled after being maintained for a fixed period in the aforementioned application process, a dipping process in which the glass substrate is dipped with the melt and maintained for a fixed period and then, the substrate is gradually pulled up, or a floating process in which the substrate is cooled while being moved in the melt or while the surface of the substrate is being moved at an adequate speed may be employed. The thickness of an eptaxially grown layer, and the carrier impurity concentration can be controlled by the composition ratio and the temperature of the melt and the pulling-up speed. The substrate can be continuously or intermittently processed by the application process, dipping process and floating process, so that mass productivity is increased.
Since the components of the glass having the low distortion point rapidly diffuse into the upper layer, a thin diffusion-barrier layer composed of, for example, silicon nitride having a thickness of 50 to 200 nm is preferably formed to suppress such diffusion. Thus, the polycrystalline or amorphous silicon layer or a silicon-containing low-melting-point metal layer is formed on the diffusion-barrier layer.
The silicon-containing low-melting-point metal layer is slowly cooled so that the single-crystal silicon layer is deposited by graphoepitaxy using the step difference as a seed, and then the low-melting-point metal layer is removed by, for example, hydrochloric acid, followed by a predetermined treatment to form an active device and a passive device.
After the low-melting-point metal layer such as of indium deposited on the single-crystal silicon layer after the cooling is dissolved and removed by, for example, hydrochloric acid, only a trace amount (approximately 1016 atoms/cc) of indium remains in the silicon layer, so that the single-crystal silicon layer becomes a p-type thin-film semiconductor. This layer is advantageous for production of a nMOSTFT. An n-type impurity such as phosphorus may be ion-implanted into the entire surface or selective regions of the single-crystal silicon layer to form an n-type single-crystal silicon thin-film, whereby a pMOSTFT can also be obtained. A cMOSTFT can also be formed. The polycrystalline or amorphous silicon layer or the silicon-containing low-melting-point metal layer may be doped with a Group III or V impurity having a large solubility, such as boron, phosphorus, antimony, arsenic, or bismuth, in a proper amount, during the deposition of this layer so as to control the type and/or the concentration of the impurity in the epitaxially grown silicon layer, that is, to control the doping type (n- or p-) and/or the concentration of the carrier.
Accordingly, the single-crystal silicon layer grown by graphoepitaxy on the substrate is used as a channel region, a source region and a drain region of a top-gate MOSTFT which constitutes at least a part of the peripheral driving circuit, the type and the concentration of each region being controllable, as described above.
Thin-film transistors in the peripheral-driving-circuit section and the display section may constitute n-channel, p-channel or complementary insulating-gate field-effect transistors: for example, a thin-film transistor may comprise a combination of a complementary type and an n-channel type, a complementary type and a p-channel type, or a complementary type, an n-channel type and a p-channel type. Preferably at least a part of the thin-film transistors in the peripheral-driving-circuit section and/or the display section has a lightly-doped drain (LDD) structure of a single type having a LDD section between the gate and the source or drain, or of a double type having LDD sections between the gate and source and between the gate and the drain, respectively.
Preferably, the MOSTFT constitutes an LDD-type TFT of an nMOS, a pMOS or a cMOS in the display section, and a cMOSTFT, an nMOSTFT, a pMOSTFT, or a mixture thereof, in the peripheral-driving-circuit section.
The MOSTFT is preferably formed on at least one of the interior and the exterior of the indented section of the substrate.
In such a case, the step difference is formed on one surface of the first substrate, and a single-crystal, polycrystalline or amorphous silicon layer is formed on the surface having the step difference. The single-crystal, polycrystalline or amorphous silicon layer is used as a channel region, a source region and a drain region of a second thin-film transistor, and at least one gate section is provided above and/or below the channel region. That is, the second thin-film transistor may be a top-gate, bottom-gate or dual-gate thin-film transistor.
In this case also, the step difference forms an indented section having a cross-section in which a side face is perpendicular to or slanted to the bottom face so as to have a basilar angle of preferably 90xc2x0 or less, and the step difference functions as a seed for graphoepitaxy of the single-crystal silicon layer.
The second thin-film transistor may be formed in a region including the indented section defined by the step difference formed in the first substrate and/or the film formed on the first substrate, and the graphoepitaxial single-crystal silicon layer may be used to form the source, drain and channel regions of the second thin-film transistor, as in the case of the first thin-film transistor.
In this second thin-film transistor also, the type and the concentration of the Group III or V impurity in the single-crystal, polycrystalline or amorphous silicon layer may be controlled as described above, and a step difference may be formed along at least one side of a device region including the channel region, the source region and the drain region of the second thin-film transistor. A gate electrode below the single-crystal, polycrystalline or amorphous silicon layer is preferably trapezoidal at the side end section. A diffusion-barrier layer may be provided between the first substrate and the single-crystal, polycrystalline or amorphous silicon layer.
The source or drain electrodes of the first and/or second thin-film transistors are preferably formed on a region including the step difference.
The first thin-film transistor may comprise at least the top-gate type among a top-gate type having a gate section above the channel region, a bottom-gate type having a gate section below the channel region, and a dual-gate type having one gate section above and one below the channel region, and the switching device may comprise one of a top-gate second thin-film transistor, a bottom-gate second thin-film transistor and a dual-gate second thin-film transistor.
In this case, the gate section formed below the channel region in the bottom-gate or dual-gate second thin-film transistor preferably comprises a heat resistant material, and an upper-gate electrode of the second thin-film transistor and a gate electrode of the first thin-film transistor may comprise a common material.
The peripheral-driving-circuit section may comprise, in addition to the above-mentioned first thin-film transistor, at least one of a top-gate, bottom-gate or dual-gate thin-film transistor having a channel region of a polycrystalline or amorphous silicon layer and a gate region formed above or below the channel region, and may further comprise a diode, a resistor, a capacitor and an inductor, each comprising a single-crystal, polycrystalline or amorphous silicon layer.
Thin-film transistors in the peripheral driving circuit and/or the display section have a single-gate or a multi-gate configuration.
Preferably, when the n- or p-channel thin-film transistor in the peripheral-driving-circuit section and/or the display section is a dual-gate type, the upper or a lower-gate electrode is electrically opened or a given negative voltage for the n-channel type or a given positive voltage for the p-channel type is applied so that the dual-gate type thin-film transistors operate as bottom- or top-gate type thin-film transistors.
The thin-film transistor in the peripheral-driving-circuit section may be the first thin-film transistor of an n-channel, p-channel or complementary type, and the thin-film transistor in the display section may be an n-channel, p-channel or complementary type when the channel region is a single-crystal silicon layer, a polycrystalline silicon layer, or an amorphous silicon layer.
After the single-crystal silicon layer is deposited, an upper-gate section including a gate insulating film and a gate electrode may be formed on the single-crystal silicon layer, and the single-crystal silicon layer may be doped with a Group III or V impurity through the upper-gate section to form the channel region, the source region and the drain region.
When the second thin-film transistor is a bottom-gate type or a dual-gate type, a lower-gate electrode composed of a heat resistant material is provided below the channel region, and a gate insulating film is formed on the gate electrode to form a lower-gate section, and the second thin-film transistor is formed by the same steps including the step for forming the step difference as those in the first thin-film transistor. In such a case the upper-gate electrode of the second thin-film transistor and the gate electrode of the first thin-film transistor may be composed of a common material.
The single-crystal silicon layer formed on the lower-gate section may be doped with a Group III or V impurity to form a source region and a drain region, followed by an activation treatment.
The source and drain regions of the second thin-film transistor may be formed by ion-implantation of the above impurity on the single-crystal silicon layer through a resist mask and may be subjected to activation treatment, and the gate electrode of the first thin-film transistor, and the upper-gate electrode of the second thin-film transistor, if necessary, may be formed after the formation of the gate insulating film.
When the thin-film transistor is a top-gate type, the source and drain regions of the first and second thin-film transistors may be formed on the single-crystal silicon layer by ion implantation of the impurity through a resist mask and may be subjected to activation treatment, and then the gate sections including the gate insulating films and the gate electrodes of the first and second thin-film transistors may be formed.
Alternatively, when the thin-film transistor is of the top-gate type, the gate sections including the gate insulating films and the gate electrodes of the first and second thin-film transistors may be formed, and then the source and drain regions of the first and second thin-film transistors may be formed on the single-crystal silicon layer by ion implantation of the impurity through a resist mask, followed by an activation treatment.
The resist mask used when the LDD structure was formed may be left unremoved and the ion implantation for forming the source and drain regions may be performed through a resist mask which covers the remaining mask.
The substrate may be optically opaque or transparent, and may be provided with pixel electrodes for a reflective or transmissive display.
The display section may have a lamination configuration of the pixel electrodes and a color filter layer which may be formed on a display array, whereby the aperture ratio and the luminance are improved and costs can be decreased due to omission of a color filter substrate and improved productivity.
When the pixel electrodes are reflective electrodes, unevenness is preferably imparted to a resin film so that the resin film has optimized reflective characteristics and viewing-angle characteristics, and then the pixel electrodes are formed, whereas, when the pixel electrodes are transparent electrodes, the surface is preferably planarized by a transparent planarization film and then the pixel electrodes are formed on the planarized plane.
The display section is illuminated or dimmed by being driven by the above-described MOSTFT: for instance, the display section may comprise, for example, a liquid crystal display (LCD), an electroluminescent (EL) display, a field emission display (FED), a light-emitting polymer display (LEPD), or a light-emitting diode (LED) display. In this case, the arrangement may be such that a plurality of pixel electrodes are arranged in a matrix in the display section and a switching device is connected to each pixel electrode.
In accordance with a third aspect of the present invention, there is provided a method of producing an electrooptical device, as well as a method of producing a driving substrate for such an electrooptical device, having a first substrate carrying a display section provided with pixel electrodes and a peripheral-driving-circuit section provided on a periphery of the display section, a second substrate, and an optical material disposed between the first substrate and the second substrate; the method comprising the steps of: a gate-forming step for forming a gate portion including a gate electrode and a gate insulating film on one face of the first substrate; a step-forming step for forming a step difference on the one face of the first substrate; a layer-forming step for forming a polycrystalline or amorphous silicon layer having a predetermined thickness on the first substrate having the gate portion and the step difference and then forming a low-melting-point metal layer on or under the polycrystalline or amorphous silicon layer, or of forming a low-melting-point metal layer containing silicon on the first substrate having the step difference; a heating step for dissolving silicon of the polycrystalline or amorphous layer or of the low-melting-point metal layer into the low-melting-point metal layer by heating; a deposition step for depositing on the first substrate a single-crystal silicon layer by allowing the silicon of the polycrystalline or amorphous silicon layer or of the low-melting-point metal layer to grow by graphoepitaxy by a cooling treatment using as a seed the step difference on the substrate; a step for effecting a predetermined treatment on the single-crystal silicon layer, thereby forming a channel region, a source region and a drain region; and a step for forming a first thin-film transistor of bottom-gate type having the gate portions on the below the channel region and constituting at least part of the peripheral-driving-circuit section. The above-mentioned thin-film transistor may be a field effect transistor (FET) or a bipolar transistor. The FET, when used, may be a MOS-type FET or a junction-type FET.
In accordance with this aspect of the present invention, the same advantages as those offered by the first aspect of the invention are obtainable, except for the advantage derived in the first aspect from the use of the dual-gate structure of the thin-film transistor.
In accordance with the present invention, it is preferred to form the aforementioned step difference in the insulating substrate or in a diffusion barrier such as a film of silicon nitride (referred to as SiN, hereinafter) or both in the insulating substrate and the diffusion barrier, so as to provide an indented section having such a cross-section that both side faces of the indented section are perpendicular to the bottom or slanted to form a basilar angle of not greater than 90xc2x0 with respect to the bottom face of the indented section, and to use this step difference as a seed for the graphoepitaxy of the single-crystal silicon layer. Preferably, the step difference is formed along at least one side of a device region including the channel region, the source region and the drain region of the first thin-film transistor. When a passive device such as a resistor is formed of the aforementioned single-crystal silicon layer, the step difference is formed along at least one side of the device region in which the resistor is formed.
The first thin-film transistor such as MOSTFT may be formed inside, outside or both inside and outside the indented section defined by the step difference.
The step difference may be formed by a dry etching process, such as a reactive ion etching process, and the polycrystalline or amorphous silicon layer is formed preferably by a low-temperature deposition process at a substrate temperature of 100 to 400xc2x0 C., for example, a reduced-pressure CVD process, a catalytic CVD process, a plasma-enhanced CVD process, or a sputtering process so that the thickness becomes several xcexcm to 0.005 xcexcm, followed by the deposition of the low-melting-point metal layer by a vacuum evaporation process or a sputtering process so that the thickness becomes several tens to several hundreds times the thickness of the polycrystalline or amorphous silicon layer, and then the heating treatment is executed.
In this case, the low-melting-point metal layer may be formed above or below the polycrystalline or amorphous silicon layer formed by the low-temperature deposition process. Alternatively, the aforementioned low-melting-point metal layer containing silicon is deposited and then subjected to the heating treatment.
The substrate may be an insulating substrate, for example, a glass substrate or a heat-resistant organic substrate, and the low-melting-point metal layer may be formed of at least one metal selected from the group consisting of indium, gallium, tin, bismuth, lead, zinc, antimony and aluminum.
When the low-melting-point metal layer is formed of indium, this layer is heated preferably at 850 to 1,100xc2x0 C. and more preferably 900 to 950xc2x0 C. in a hydrogen-based atmosphere (pure hydrogen, a nitrogen-hydrogen mixture, or an argon-hydrogen mixture) to form an indium-silicon melt and, when the low-melting-point metal layer is formed of indium-gallium, this layer is heated preferably at 300 to 1,100xc2x0 C. and more preferably 350 to 600xc2x0 C. in a hydrogen-based atmosphere to form an indium-gallium-silicon melt, whereas, when the low-melting-point metal layer is formed of gallium, this layer is heated preferably at 400 to 1,100xc2x0 C. and more preferably 420 to 600xc2x0 C. in a hydrogen-based atmosphere to form a gallium-silicon melt. The substrate may be uniformly heated using an electrical furnace or a lamp or, alternatively, a predetermined region of the substrate may be locally heated using laser or electron beams.
With reference to FIG. 11, the melting point of the silicon-containing low-melting-point metal decreases as the content of the low-melting-point metal increases. The indium melt layer containing silicon, e.g., by 1 percent by weight, is formed at a substrate temperature of 850 to 1,100xc2x0 C. when indium is used, because such a substrate temperature facilitates use of glass having low heat resistance, such as crystallized glass, in addition to quartz glass, as a substrate. A gallium melt layer containing 1 percent by weight of silicon may be formed at a temperature of 400 to 1,100xc2x0 C. on any glass substrate.
When indium-gallium-silicon or gallium-silicon is used, a glass substrate having a low distortion point or a heat-resistant organic substrate can be used, so that a single-crystal silicon layer can be formed on a large glass substrate having an area of, for example, 1 m2, which is inexpensive and can readily be prepared in the form of a rolled long glass sheet.
Since the components of the glass having the low distortion point rapidly diffuse into the upper layer, a thin diffusion-barrier layer composed of, for example, silicon nitride having a thickness of 50 to 200 nm is preferably formed to suppress such diffusion. Thus, the polycrystalline or amorphous silicon layer or a silicon-containing low-melting-point metal layer is formed on the diffusion-barrier layer.
The silicon-containing low-melting-point metal layer is slowly cooled so that the single-crystal silicon layer is deposited by graphoepitaxy using the step difference as a seed, and then the low-melting-point metal layer is removed by, for example, hydrochloric acid, followed by a predetermined treatment to form an active device and a passive device.
After the low-melting-point metal layer such as of indium deposited on the single-crystal silicon layer after the cooling is dissolved and removed by, for example, hydrochloric acid, only a trace amount (approximately 1016 atoms/cc) of indium remains in the silicon layer, so that the single-crystal silicon layer becomes a p-type thin-film semiconductor. This layer is advantageous for production of a nMOSTFT. An n-type impurity such as phosphorus may be ion-implanted into the entire surface or selective regions of the single-crystal silicon layer to form an n-type single-crystal silicon thin-film, whereby a pMOSTFT can also be obtained. A cMOSTFT can also be formed. A cMOSTFT can also be formed. The polycrystalline or amorphous silicon layer or the silicon-containing low-melting-point metal layer may be doped with a Group III or V impurity having a large solubility, such as boron, phosphorus, antimony, arsenic, or bismuth, in a proper amount, during the deposition of this layer so as to control the type and/or the concentration of the impurity in the epitaxially grown silicon layer, that is, to control the doping type (n- or p-) and/or the concentration of the carrier.
Accordingly, the single-crystal silicon layer grown by graphoepitaxy on the substrate is used as a channel region, a source region and a drain region of a dual-gate MOSTFT which constitutes at least a part of the peripheral driving circuit, the type and the concentration of each region being controllable, as described above.
Thin-film transistors in the peripheral-driving-circuit section and the display section may constitute n-channel, p-channel or complementary insulating-gate field-effect transistors: for example, a thin-film transistor may comprise a combination of a complementary type and an n-channel type, a complementary type and a p-channel type, or a complementary type, an n-channel type and a p-channel type. Preferably at least a part of the thin-film transistors in the peripheral-driving-circuit section and/or the display section has a lightly-doped drain (LDD) structure of a single type having a LDD section between the gate and the source or drain, or of a double type having LDD sections between the gate and source and between the gate and the drain, respectively.
Preferably, the MOSTFT constitutes an LDD-type TFT of an nMOS, a pMOS or a cMOS in the display section, and a cMOSTFT, an nMOSTFT, a pMOSTFT, or a mixture thereof, in the peripheral-driving-circuit section.
The MOSTFT is preferably formed on at least one of the interior and the exterior of the indented section of the substrate.
In such a case, the step difference is formed on one surface of the first substrate, and a single-crystal, polycrystalline or amorphous silicon layer is formed on the surface having the step difference. The single-crystal, polycrystalline or amorphous silicon layer is used as a channel region, a source region and a drain region of a second thin-film transistor, and at least one gate section is provided above and/or below the channel region. That is, the second thin-film transistor may be a top-gate, bottom-gate or dual-gate thin-film transistor.
In this case also, the step difference forms an indented section having a cross-section in which a side face is perpendicular to or slanted to the bottom face so as to have a basilar angle of preferably 90xc2x0 or less, and the step difference functions as a seed for graphoepitaxy of the single-crystal silicon layer.
The second thin-film transistor may be formed in a region including the indented section defined by the step difference formed in the first substrate and/or the film formed on the first substrate, and the graphoepitaxial single-crystal silicon layer may be used to form the source, drain and channel regions of the second thin-film transistor, as in the case of the first thin-film transistor.
In this second thin-film transistor also, the type and the concentration of the Group III or V impurity in the single-crystal, polycrystalline or amorphous silicon layer may be controlled as described above, and a step difference may be formed along at least one side of a device region including the channel region, the source region and the drain region of the second thin-film transistor. A gate electrode below the single-crystal, polycrystalline or amorphous silicon layer is preferably trapezoidal at the side end section. A diffusion-barrier layer may be provided between the first substrate and the single-crystal, polycrystalline or amorphous silicon layer.
The source or drain electrodes of the first and/or second thin-film transistors are preferably formed on a region including the step difference.
The first thin-film transistor may comprise at least the bottom-gate type among a top-gate type having a gate section above the channel region, a bottom-gate type having a gate section below the channel region, and a dual-gate type having one gate section above and one below the channel region, and the switching device may comprise one of a top-gate second thin-film transistor, a bottom-gate second thin-film transistor and a dual-gate second thin-film transistor.
In this case, the gate section formed below the channel region in the bottom-gate or dual-gate second thin-film transistor preferably comprises a heat resistant material, and an upper-gate electrode of the second thin-film transistor and a gate electrode of the first thin-film transistor may comprise a common material.
The peripheral-driving-circuit section may comprise, in addition to the above-mentioned first thin-film transistor, at least one of a top-gate, bottom-gate or dual-gate thin-film transistor having a channel region of a polycrystalline or amorphous silicon layer and a gate region formed above or below the channel region, and may further comprise a diode, a resistor, a capacitor and an inductor, each comprising a single-crystal, polycrystalline or amorphous silicon layer.
Thin-film transistors in the peripheral driving circuit and/or the display section have a single-gate or a multi-gate configuration.
Preferably, when the n- or p-channel thin-film transistor in the peripheral-driving-circuit section and/or the display section is a dual-gate type, the upper or a lower-gate electrode is electrically opened or a given negative voltage for the n-channel type or a given positive voltage for the p-channel type is applied so that the dual-gate type thin-film transistors operate as bottom- or top-gate type thin-film transistors.
The thin-film transistor in the peripheral-driving-circuit section may be the first thin-film transistor of an n-channel, p-channel or complementary type, and the thin-film transistor in the display section may be an n-channel, p-channel or complementary type when the channel region is a single-crystal silicon layer, a polycrystalline silicon layer, or an amorphous silicon layer.
After the single-crystal silicon layer is deposited, an upper-gate section including a gate insulating film and a gate electrode may be formed on the single-crystal silicon layer, and the single-crystal silicon layer may be doped with a Group III or V impurity through the upper-gate section to form the channel region, the source region and the drain region.
When the second thin-film transistor is a bottom-gate type or a dual-gate type, a lower-gate electrode composed of a heat resistant material is provided below the channel region, and a gate insulating film is formed on the gate electrode to form a lower-gate section, and the second thin-film transistor is formed by the same steps including the step for forming the step difference as those in the first thin-film transistor. In such a case the upper-gate electrode of the second thin-film transistor and the gate electrode of the first thin-film transistor may be composed of a common material.
The single-crystal silicon layer formed on the lower-gate section may be doped with a Group III or V impurity to form a source region and a drain region, followed by an activation treatment.
The source and drain regions of the second thin-film transistor may be formed by ion-implantation of the above impurity on the single-crystal silicon layer through a resist mask and may be subjected to activation treatment, and the gate electrode of the second thin-film transistor may be formed after the formation of the gate insulating film.
The method also may be such that, when the second thin-film transistor is of the top-gate type, the source and drain regions of the first and second thin-film transistors are formed by ion implantation of the above-mentioned impurities through a mask constituted by a resist, followed by an activation treatment, and thereafter a gate portion composed of a gate insulating film and the gate electrode of the second thin-film transistor is formed.
The method also may be such that, when the second thin-film transistor is of the top-gate type, a gate portion of the second thin-film transistor, composed of a gate insulating film and a gate electrode made of a heat-resistant material, is formed after the deposition of the single-crystal silicon layer, and the source and drain regions of the first and second thin-film transistors are formed by ion implantation of the above-mentioned impurities through a mask constituted by the above-mentioned gate portion and a resist, followed by an activation treatment.
The resist mask used when the LDD structure was formed may be left unremoved and the ion implantation for forming the source and drain regions may be performed through a resist mask which covers the remaining mask.
The substrate may be optically opaque or transparent, and may be provided with pixel electrodes for a reflective or transmissive display.
The display section may have a lamination configuration of the pixel electrodes and a color filter layer which may be formed on a display array, whereby the aperture ratio and the luminance are improved and costs can be decreased due to omission of a color filter substrate and improved productivity.
When the pixel electrodes are reflective electrodes, unevenness is preferably imparted to a resin film so that the resin film has optimized reflective characteristics and viewing-angle characteristics, and then the pixel electrodes are formed, whereas, when the pixel electrodes are transparent electrodes, the surface is preferably planarized by a transparent planarization film and then the pixel electrodes are formed on the planarized plane.
The display section is illuminated or dimmed by being driven by the above-described MOSTFT: for instance, the display section may comprise, for example, a liquid crystal display (LCD), an electroluminescent (EL) display, a field emission display (FED), a light-emitting polymer display (LEPD), or a light-emitting diode (LED) display. In this case, the arrangement may be such that a plurality of pixel electrodes are arranged in a matrix in the display section and a switching device is connected to each pixel electrode.
In accordance with a fourth aspect of the present invention, there is provided a method of producing an electrooptical device, as well as a method of producing a driving substrate for such an electrooptical device, having a first substrate carrying a display section provided with pixel electrodes and a peripheral-driving-circuit section provided on a periphery of the display section, a second substrate, and an optical material disposed between the first substrate and the second substrate; the method comprising the steps of: a gate-forming step for forming a gate portion including a gate electrode and a gate insulating film on one face of the first substrate; a step-forming step for forming a step difference on the one face of the first substrate; a layer-forming step for forming a melt layer of a low-melting-point metal containing silicon on the first substrate having the gate portion and the step difference; a deposition step for depositing a single-crystal silicon layer by allowing the silicon of the melt layer to grow by graphoepitaxy by a cooling treatment using as a seed the step difference on the substrate; a step for effecting a predetermined treatment on the single-crystal silicon layer, thereby forming a channel region, a source region and a drain region; and a step for forming a first thin-film transistor of bottom-gate type having the gate portions on the below the channel region and constituting at least part of the peripheral-driving-circuit section. The above-mentioned thin-film transistor may be a field effect transistor (FET) or a bipolar transistor. The FET, when used, may be a MOS-type FET or a junction-type FET.
In accordance with this aspect of the present invention, the same advantages as those offered by the first aspect of the invention are obtainable, except for the advantage derived in the first aspect from the use of the dual-gate structure of the thin-film transistor. In addition, this aspect offers the following advantage by virtue of the use of the melt layer of silicon-containing low-melting-point metal.
Namely, the melt of the low-melting-point metal can be prepared at a comparatively low temperature of, for example, 350xc2x0 C., and can easily be applied to the substrate having the step differences serving as the seed, provided that the substrate has been heated to a temperature slightly above the temperature at which the melt is prepared. Thus, a single-crystal silicon layer can uniformly be formed at a comparatively low temperature of from, for example, 350 to 400xc2x0 C.
In the graphoepitaxy in used in this aspect of the present invention, a single-crystal silicon thin-film having a variety of P-type impurity concentration and high mobility can be readily produced by adjusting the composition ratio of the melt of the melting-point metal, the temperature of the melt, the heating temperature of the substrate, and the cooling rate, thus enabling easy control of the threshold voltage (Vth) of the device, which in turn enables the device to operate at a high speed due to reduced resistance.
The melt layer of the silicon-containing low-melting-point metal may be doped with an adequate amount of Group III or V impurity, such as boron, phosphorus, antimony, arsenic, bismuth or aluminum, so that the type and the concentration of the impurity in the epitaxial single-crystal silicon, that is, the type (P-type or N-type) and the carrier concentration, are controllable.
Other features of the fourth aspect are substantially the same as those of the first, second and third aspects of the present invention.

Method of producing electrooptical device and method of producing driving substrate for driving electrooptical device


An LNG storage tank comprises a heat insulating wall on an inner surface of the storage tank, a sealing wall contacting LNG on the heat insulating wall, and a structure to support the sealing wall. The structure comprises an anchor structure, which comprises an anchor member between the inner surface of the storage tank and the sealing wall to secure the sealing wall to the inner surface, and a heat-insulating material around the anchor member. The anchor member is coupled at several portions to the inner surface. The structure provides a simple configuration to the heat insulating wall and the sealing wall, and a simple connection therebetween, enabling convenient construction thereof while increasing sealing reliability. The structure simplifies an assembled structure and a manufacturing process, reducing a construction time of the tank while efficiently relieving stress on the tank.

The present invention relates to liquefied natural gas (LNG) storage tanks built for marine vessels, and more particularly to the anchor and corner structures which are used to construct a heat insulating wall and sealing walls of an LNG storage tank built in a marine vessel for storage and transport of liquefied natural gas in a cryogenic state.
Liquefied natural gas (LNG) is formed through liquefaction of natural gas (i.e., a fossil fuel) and stored in LNG storage tanks. Depending on location, the LNG storage tanks are typically classified into on-land storage tanks built above or in the ground, and movable storage tanks installed on carriers such as vehicles, marine vessels, etc.
Since LNG is likely to explode if in a collision and is stored in a cryogenic state, the LNG storage tank must be firmly collision resistant and liquid-tight.
Compared with the on-land storage tank, which experiences little movement of the LNG, the LNG storage tank installed on vehicles or marine vessels experiences movement of the LNG, and is thus required to have a countermeasure capable of relieving mechanical stress caused by the movement of the LNG. In this regard, since the LNG storage tank installed in the marine vessel with the countermeasure against the mechanical stress can also be used as the on-land storage tank, the structure of the LNG storage tank installed in the marine vessel will hereinafter be described as an example.
FIG. 1 is a cross-sectional view schematically showing a marine vessel in which a conventional LNG storage tank is installed.
Referring to FIG. 1, the marine vessel 1 with the conventional LNG storage tank has a double walled hull, which comprises of an outer wall 16 and an inner wall 12 formed inside the outer wall 16. The inner and outer walls 12, 16 of the marine vessel 1 are connected to each other by connection ribs 13. In some cases, the marine vessel 1 can be made of a single walled hull.
The interior of the hull, that is, the interior of the inner wall 12, can be divided by one or more partitions 14. The partitions 14 can be formed by known cofferdams, which are installed in typical floating storage offloading vessels like the marine vessel 1 of FIG. 1.
Each of the inner spaces divided by the partitions 14 can be utilized as a storage tank 10 to store a cryogenic liquid such as LNG.
Here, an inner peripheral surface of the storage tank 10 is sealed liquid-tight by a sealing wall 50. In other words, the sealing wall 50 defines a single storage space with a plurality of metal plates welded together, so that the storage tank 10 can store and transport LNG without any leakage.
The sealing wall 50 in direct contact with LNG in the cryogenic state can be formed with corrugation to endure the temperature variation caused by the loading and unloading of LNG, as known in the art. The sealing wall 50 is connected to the inner wall 12 or the partition 14 of the vessel 1 by a plurality of anchor structures 30. Thus, the sealing wall 50 cannot be moved with respect to the hull.
A heat insulating wall is arranged between the sealing wall 50 and the inner wall 12 or the partition 14 to form a heat insulating layer therebetween. The heat insulating wall includes a corner structure 20 placed at a corner of the storage tank 10, an anchor structure 30 placed around an anchor member (not shown), and a planar structure 40 placed on a planar section of the storage tank 10. In this way, the overall heat insulating layer can be formed on the storage tank 10 by the corner structure 20, anchor structure 30, and planar structure 40.
Here, the anchor structure 30 comprises of a rod-shaped anchor member directly connected between the sealing wall and the hull to secure the sealing wall to the hull, and a heat-insulating material surrounding the anchor member.
The anchor structure 30 mainly serves to support the sealing wall 50, whereas the corner structure 20 and the planar structure 40 mainly serve to support the load the LNG exerts on the sealing wall 50. The corner structure 20 and the planar structure 40 are not directly connected to the anchor structure 30.
FIG. 2 is a cross-sectional view showing a part of a conventional LNG storage tank disclosed in Korean Patent No. 499710 issued to the applicant of this invention.
Referring to FIG. 2, the conventional LNG storage tank 10 includes a primary heat insulating wall 24, 34, 44 and a secondary heat insulating wall 22, 32, 42 sequentially stacked on the bottom of the hull, and a secondary sealing wall 23, 33, 43 between the primary heat insulating wall 24, 34, 44 and the secondary heat insulating wall 22, 32, 42 to seal the heat insulating walls. In addition, a primary sealing wall 50 is placed on the primary heat insulating wall 24, 34, 44.
The LNG storage tank 10 constructed as described above further includes a corner structure 20 placed at an inside corner, an anchor structure 30 spaced a predetermined distance from the bottom, and a planar structure 40 slidably interposed between corner structures 20 or anchor structures 30. The corner structure 20, the anchor structure 30, and the planar structure 40 are manufactured as unit modules that can be assembled onto the storage tank 10. Then, with these structures assembled onto the storage tank 10, the primary sealing wall 50 is finally placed on the assembled structures to provide a liquid-tight seal to the heat insulating walls, thereby defining a space to store the LNG.
As shown in FIG. 2, each of the corner structure 20, the anchor structure 30, and the planar structure 40 contains the primary heat insulating wall 24, 34, 44, the secondary heat insulating wall 22, 32, 42, and the secondary sealing wall 23, 33, 43, which will be commonly defined as heat insulating wall structures 20, 30, 40.
Meanwhile, in each unit module of the heat insulating wall structures 20, 30 and 40, the secondary sealing wall and each of the heat insulating walls are bonded together by adhesives. Typically, the secondary heat insulating wall 22, 32, 42 includes polyurethane foam, an insulating material, and a plate bonded to a lower surface of the polyurethane foam. The primary heat insulating wall 24, 34, 44 includes the polyurethane foam, and a plate bonded to the upper surface of the polyurethane foam by an adhesive. In addition, the primary sealing wall is positioned on the primary heat insulating wall 24, 34, 44, and welded to the anchor structure 30.
The secondary heat insulating wall 42 of the planar structure 40 is formed at a lower end with a flange 42a greater than the secondary heat insulating wall 42. The flange 42a is fitted into a groove formed in the lower end of the anchor structure 30 to slide somewhat therein.
In the construction shown in the drawing, the anchor structure 30 includes an anchor support rod 36, a securing member 37 positioned at a lower portion of the anchor structure 30, the primary anchor heat insulating wall 34, the secondary anchor heat insulating wall 32, and the secondary sealing wall 33 interposed between the primary anchor heat insulating wall 34 and the secondary anchor heat insulating wall 32. The anchor support rod 36 is connected at one end to the primary sealing wall 50, and at the other end to the inner wall 12 of the hull via the securing member 37.
The anchor support rod 36 of the anchor structure 30 has an upper end welded to the primary sealing wall 50.
Furthermore, the anchor structure 30 is positioned at a connection between the adjacent planar structures 40 to connect the planar structures 40, which are secured to the inner wall 12 or the partition 14 defines the storage tank 10. The securing member 37 of the anchor structure 30 is placed around the anchor support rod 36.
As such, since the heat insulating wall structures of the conventional LNG storage tank comprise the primary and secondary heat insulating walls, and the primary and secondary sealing walls, the conventional LNG storage tank is complicated in overall construction, in particular, in construction for connecting the secondary sealing wall, which makes it difficult to construct the heat insulting walls. Furthermore, the complexity in construction and installation of the anchor structure or the connecting structure for the secondary sealing walls deteriorates the reliability in the sealing properties of the secondary sealing wall, which can cause leakage of the LNG.
Furthermore, for the conventional anchor structure 30 which connects the inner surface of the hull and the primary sealing wall 50 via the anchor support rod 36, and the conventional corner structure 20 which supports only the load of the LNG exerted on the sealing wall 50 without supporting the sealing wall 50, it has been required to further improve the capability of absorbing stress occurred from the thermal deformation of the storage tank or deformation of the hull resulting from the loading and unloading of the LNG in the cryogenic state.
In order to achieve reduce the boiled off gas (BOG), which is a loss caused by vaporization of the LNG in the cryogenic state, and simplification in the construction and manufacturing process while solving the aforementioned problems, an LNG storage tank having a new construction completely different from that of the conventional LNG storage tank has been suggested. As a result, there is a needs for an improved anchor and corner structures corresponding to the new LNG storage tank.

Anchor for liquefied natural gas storage tank


The image processing apparatus includes a memory configured to store information on a specific image pickup condition under which a specific blur component is generated in an input image produced by image capturing using an optical system, the specific blur component being caused by the optical system;                an image pickup condition acquirer configured to acquire information on an actual image pickup condition when capturing the input image; and        a processor configured to perform, when the actual image pickup condition coincides with the specific image pickup condition, a blur detection process to detect the specific blur component included in the input image.

1. Field of the Invention
The present invention relates to an image processing technique that is performed on an image acquired through image capturing by an image pickup apparatus such as a digital still camera and a video camera.
2. Description of the Related Art
Various electronic image processing techniques that are performed on an image (captured image) acquired by image capturing have been conventionally proposed. For example, Japanese patent Laid-Open No. 2011-187208 discloses an image processing technique of recognizing a face of a person in a captured image to paint or blur other areas than the face, or to clip areas around the face. In addition, Japanese patent Laid-Open No. 2004-145287 discloses an image processing technique of performing determination required for a process using information on a captured image and information on an image pickup condition under which image capturing to acquire the captured image is performed. In addition, Japanese patent Laid-Open No. 2011-44825 discloses an image processing technique of acquiring information on a distance (object distance) to an object included in a captured image and performing an image restoration process thereon using image restoration filters different depending on the object distance.
Captured images acquired by image capturing through an optical system mostly include degradation due to imaging performance (such as aberration and diffraction) of the optical system. In an out-of-focus area including an object like a point light source, an uneven blur (such as a peripheral blur or a highly asymmetric blur), which while be described later, is generated due to the imaging performance. It is desirable that such an uneven blur be removed or reduced by an image process.
However, it is difficult in the image process to accurately distinguish the uneven blur generated in the out-of-focus area caused by the imaging performance of the optical system from an object having an uneven shape. Such difficulty may cause erroneous detection of an area including the uneven-shaped object as an area including the uneven blur and may cause execution of an image process on the erroneously detected area, thereby providing an image different from a desired captured image. None of Japanese patent Laid-Open Nos. 2011-187208, 2004-145287 and 2011-44825 disclose a method of detecting the uneven blur with high accuracy.

Image processing apparatus, image pickup apparatus, non-transitory storage medium storing image processing program and image processing method


A connecting rod of an internal combustion engine, and an internal combustion engine including the connecting rod, a piston, a crankshaft and a float bearing as main moving parts. A piston is connected to a connecting rod by a spherical joint and has radial ribs on a rear face of a crown part; a connecting rod is of an integrated, one-piece type having integrally a spherical small end part to be connected to the piston and an annular big end part; the crankshaft is of an assembly type, and a float bearing is interposed between the big end part and a crank pin.

An internal combustion engine of related art in which a connecting rod with an integral big end part is connected to an assembly-type crankshaft appears for example in JP-A-6-280847.
A connecting rod for an internal combustion engine of related art that is connected to a piston by a spherical joint appears for example in JP-A-9-144879. The content of JP-A-9-144879 will be explained with reference to FIG. 12.
A crankshaft shown in JP-A-6-280847 is an assembled member made up of a first section, a second section, a third section and a fourth section; a recess is provided in each of a first crank web mounted on the first section and a second crank web mounted on the second section, and a pin is rotatably fitted in bearings in these recesses.
The connecting rod has an integral big end, a hole is provided in the big end, and a pin is rotatably fitted in this hole.
When the crankshaft is made an assembly type like this, unnecessary metal can be removed to reduce its weight, and by the connecting rod being made of integral big end type, compared to a connecting rod with a two-piece big end, bolts can be dispensed with and weight can be reduced.
When the above-mentioned bearings between the recesses and the pin are needle bearings, the big end of the connecting rod becomes large, the weight of the connecting rod becomes large, and consequently the above-mentioned weight-reducing effects of the assembly type crankshaft and the integral big end type connecting rod are reduced.
Thus, to reduce the weight of an internal combustion engine, for example to raise the speed, the output and the durability of the internal combustion engine, it is important to reduce the weights of the main moving parts, and if weight-reduction of the main moving parts is not carried out comprehensively, a large, synergetic effect cannot be obtained. By the combination of main moving parts, not only reduced weight but also other effects such as strength and ease-of-assembly benefits can be expected.
The connecting rod 200 shown in FIG. 12 is a member having a convex spherical surface 202 formed on a small end part 201, and this convex spherical surface 202 fits slidably against a concave spherical surface 204 provided on the piston 203 side. That is, the connecting rod 200 and the piston 203 are connected by a spherical joint 205 formed by the convex spherical surface 202 and the concave spherical surface 204.
The crankshaft 200 described above swings along with the reciprocal motion of the piston 203 and rotates a crankshaft (not shown).
Accordingly, if the weight of the main moving parts such as the crankshaft 200, the piston 203 and the crankshaft (the parts that transmit power in the internal combustion engine) can be reduced, their respective inertias decrease, the loads on the areas supporting these parts can be reduced, and higher output can be obtained through higher internal combustion engine speeds.
Thus, in the internal combustion engine, means have been awaited for achieving higher speeds, higher power and better durability through weight-reduction of the connecting rod itself and comprehensive weight-reduction of the other main moving parts and for increasing for example strength and ease-of-assembly through the effective combination of main moving parts.

This patent is subject to a terminal disclaimer.

Internal combustion engine and connecting rod therefor


A method for hip distraction includes positioning a patient on a slide-resisting pad placed on a surgical table; tilting the surgical table so that the patient is in a first degree of inclination; applying a distraction force to a leg of the patient while the patient is in the first degree of inclination so that a hip joint of the patient is distracted, wherein the distraction force is opposed by a combination of a slide-resisting friction force provided by the slide-resisting pad and a gravitational force attributable to the first degree of inclination; reducing the tilt of the surgical table in accordance with a reduction of the distraction force over time so that the patient is in a second degree of inclination; and performing at least a portion of a surgical procedure on the distracted hip joint while the patient is in the second degree of inclination.

When performing surgical procedures on the hip joint, it is common to distract the hip joint prior to the surgery in order to provide additional room within the hip joint during the surgery and in order to better present selected anatomy to the surgeon during the surgery. Hip distraction is commonly achieved by applying a distraction force to the distal end of the leg of the patient. Generally, a surgical boot is placed on the foot and lower leg of the patient, the surgical boot is connected to a distraction frame, and the distraction frame is used to apply a distraction force to the surgical boot, whereby to apply a distraction force to the leg of the patient.
With conventional hip distraction, it is common to provide a padded post (often referred to as a perineal post) between the legs of the patient. This padded post provides a counterforce to the anatomy when the distraction force is applied to the surgical boot. However, the use of a padded post can create complications, since the padded post can press against the pudendal nerve of the patient, and/or the sciatic nerve of the patient, during distraction. Additionally, the padded post can exert pressure on the blood vessels in the leg of the patient during distraction. Thus, it would be desirable to minimize or eliminate the use of the padded post if other means could be used to provide a counterforce to the anatomy when the distraction force is applied to the surgical boot.
With some surgeries, it can be desirable to position the patient in the so-called "Trendelenburg position", e.g., during abdominal surgery. When disposed in the Trendelenburg position, the patient lies on the surgical table "flat on their back", with their feet higher than their head, e.g., by approximately 15-30 degrees. In order to facilitate this arrangement, the surgical table is typically tilted so that the patient's head is angled downward and the patient's feet are angled upward.
In the case of hip arthroscopy, it has been recognized that positioning the patient in this manner can facilitate distraction of the hip joint without a perineal post; that is, the gravitational weight of the patient inclined in the Trendelenburg position counteracts the distraction force in lieu of the perineal post. The frictional forces of the patient on the surgical table also contribute to counteract the distraction force. This approach has sometimes been referred to as "post-less" or "post-free" hip arthroscopy.
There are a number of benefits of post-less hip distraction, including eliminating the risk of damage caused by pressure against the pudendal nerve, the sciatic nerve, and/or the blood vessels of the patient during distraction. Another benefit is that no force is transferred to the non-operative leg, which can eliminate risks associated with forces being applied to the non-operative leg (such as neurovascular damage). Yet another benefit of post-less hip distraction is that a post-less procedure results in less pelvic tilt than conventional distraction using a post.

Systems and methods for supporting and stabilizing a patient during hip distraction


A serializer receives parallel data and a control signal. The serializer splits the parallel data into multiple subportions of data and, based on the control signal, sequentially outputs each of said subportions as serial output data in one or more serial output channels. The number of serial output channels is dictated by the control signal.

1. Technical Field
The present disclosure relates generally to a serializer for producing serial data. More particularly, the present disclosure relates to a programmable serializer for producing serial data for a video display.
2. Background Information
In some situations, video data is converted from a parallel format to a serial format. A serializer is a device that converts such parallel data to serial data. An application of a serializer is for a cellular telephone in which the logic (e.g., a processor) that generates the video data and the display on which the video data is provided are provided in two separate parts of the telephone separated by a hinge. That is, the processor is in the main part of the phone and the display is provided in a cover that flips open and shut via a hinge. In such "flip phones," it is desirable to minimize the number of signal conductors that pass through the hinge. By serializing the video data, fewer conductors are needed in the hinge assembly.
The output rate of the serial data produced by a serializer must generally match the consumption rate of the target device. In the context in which the target device is a display, the output data rate of the serializer must generally match the resolution of the display. Most serializers, however, are capable of only a fixed serialization ratio. This limitation means, in turn, that the resolution of the display is limited by the output data rate of the serializer. A manufacturer of the cell phone may be forced to use a different serializer if it is desired to incorporate into the phone a display with a different (e.g., higher) resolution.

Programmable serializer for a video display