A method of managing reliance in an electronic transaction system includes a certification authority issuing a primary certificate to a subscriber and forwarding to a reliance server, information about the issued primary certificate. The reliance server maintains the forwarded information about issued primary certificate. The subscriber forms a transaction and then provides the transaction to a relying party. The transaction includes the primary certificate or a reference thereto. The relying party sends to the reliance server a request for assurance based on the transaction received from the subscriber. The reliance server determines whether to provide the requested assurance based on the information about the issued primary certificate and on the requested assurance. Based on the determining, the reliance server issues to the relying party a secondary certificate providing the assurance to the relying party.

Systems for accomplishing business transactions electronically are becoming increasingly widespread, partly because of the advent of global computer networks such as the Internet, and partly because of the evolution and maturity of public key cryptography, which enhances the security of such commerce. The application of public key cryptography to electronic commerce has been heretofore envisioned in documents such as Recommendation X.509 of the International Telecommunications Union (ITU, formerly CCITT) (hereinafter "Standard X.509"), the Digital Signature Guidelines of the American Bar Association's Information Security Committee (December 1995 edition, hereinafter "ABA Guidelines"), and statutes and regulations such as the Utah Digital Signature Act, Utah Code Ann. title 46, chapter 3 (1996) (hereinafter "Utah Act").
The backdrop established in these and other documents addresses some problems but leaves many of them unsolved and unresolved.
2.1 Conventional Approaches to Digital Signature Certification
To use secure electronic commerce according to the conventional methods, each user has a pair of related keys, namely a private key (to be kept secret by the user) and a public key (which can be known by anyone without compromising the secrecy of the corresponding private key). Using a particular public key, an algorithm can determine whether the corresponding private key was used to sign or authenticate a given message. For example, if A wishes to send B a message, and provide B with a high degree of assurance that the message is genuinely A's, then A can digitally sign the message using A's private key, and B can thereafter verify that the message is truly A's using A's public key.
A public key is simply a value (generally a number), and has no intrinsic association with anyone, including the person whose message it is to authenticate. Widespread, commercial use of digital signatures requires reliable information associating public keys with identified persons. Messages of those identified persons can then be authenticated using the keys.
Digital signature certificates (sometimes also called public key certificates or simply certificates) meet this need. These certificates are generally issued by trusted third parties known as certification authorities (CAs) and they certify (1) that the issuing certification authority has identified the subject of the certificate (often according to specifications delineated in a certification practice statement), and (2) that a specified public key (in the certificate) corresponds to the a private key held by the subject of the certificate. A structure for public-key certificates is included in the X.509 standard cited earlier. The content of a certificate is often specified in a statute or regulation. A typical X.509 certificate has the format shown in FIG. 1.
In order to assure that a certificate's authenticity can be subsequently verified, the certification authority digitally signs the certificate when issuing it. The issuing certification authority's digital signature can itself be verified by reference to a public key (the certification authority's public key), which is associated with the certification authority in another certificate issued by a second certification authority to the first certification authority. That other certification authority's digital signature can be verifiable by a public key listed in yet another certificate, and so on along a chain of certificates until one reaches a so-called root or prime certification authority whose public key is widely and reliably distributed. For maximum assurance of the authenticity of a certificate relied upon in a transaction, the relying party must, using conventional methods, verify each certificate in the chain. An example of a certification chain is shown in FIG. 2, wherein a root certification authority issues a certificate to certification authority CA-1 which in turn certifies certification authorities CA-2 and CA-5. Certification authority CA-2 certifies CA-3 which certifies CA-4 which certifies subscriber-1. Certification authority CA-5 certifies subscriber-2.
Most legal systems treat a certificate as a representation, finding, or conclusion made pursuant to a contract between the issuing certification authority and the subscriber, i.e., the person identified in the certificate as the holder of the private key corresponding to the public key listed in the certificate. Persons other than the subscriber may rely on the certificate. The certification authority's duties in relation to those relying parties may stem from rules governing representations or false statements, rules treating the relying party as a third-party beneficiary of the contract between the certification authority and subscriber, statutes governing digital signatures, or a blend of all of the above as well as perhaps additional legal principles.
Often, a party's right to rely on a certificate is limited. In the law applicable to misrepresentations, for example, reliance is generally required to be reasonable. Further, reliance on some certificates is specified to be per se unreliable. A bright line separates certain classes of clearly unreliable certificates from all others, and a relying party relies on them at its own peril, without recourse against the issuing certification authority or subscriber for a defect in the certificate. Certificates that are per se unreliable are conventionally termed invalid, and may include any certificate which:                (1) Has, expired (i.e., the time of reliance is later than the date specified in the certificate for its expiration);        (2) Has been revoked (i.e., have been declared permanently invalid by the certification authority which issued the certificate); and        (3) Is suspended at the time of reliance (i.e. has been declared temporarily invalid by the certification authority which issued the certificate).
In addition, a certificate which has not been accepted by its subscriber or issued by a certification authority should not be considered to have taken effect, and could, perhaps rather loosely, be considered invalid.
Suspending and/or revoking certificates are an important means of minimizing the consequences of errors by the certification authority or subscriber. Depending on applicable legal rules, a certification authority may avert further loss due to inaccuracy in the certificate by revoking it. A subscriber can revoke a certificate to prevent reliance on forged digital signatures created using a compromised, e.g., lost or stolen, private key. Certificates which become invalid by revocation are generally listed in a certificate revocation list (CRL), according to ITU X.509. Suspension, or temporary invalidation, was not contemplated in ITU X.509, and may or may not be included in the CRL. Certificates which become invalid by virtue of their age need not be listed in a CRL because each certificate contains its own expiration date.
As a practical matter, the conventional CRL-based system works as follows. Before a subscriber can create a verifiable digital signature, the signer must arrange for a certification authority to issue a certificate identifying the subscriber with the subscriber's public key. The subscriber receives back and accepts the issued certificate, and then creates digital signatures and attaches a copy of the certificate to each of them. When the other party to a transaction receives such a digital signature, the other party must check with the certification authority, generally via its on-line database, to determine whether the certificate is currently valid. If so, and if the digital signature can be verified by the public key in the certificate, the party is usually in a strong position to rely on the digital signature.
2.2 Problems with the Conventional Approaches to Digital Signature Certification
The system summarized above and envisioned in Standard X.509, the ABA Guidelines, the Utah Act, and similar documents has several deficiencies, including:                Little support for risk management: The conventional system provides very few facilities or opportunities to enable a certification authority to manage the risk of certification. The certification authority is not informed when anyone relies on a certificate that the certification authority has issued or the extent to which anyone relies on any certificate it has issued. The certification authority also has no way of monitoring outstanding certificates, ascertaining whether problems arise, evaluating which factors affect the risk of faulty certification or the scope of exposure to risk that the certification authority should prudently undertake. Furthermore, conventional systems provide few facilities to help subscribers and relying parties manage their risks, including the risk of keeping the private key secure.        Relying party is under-served: To a great extent, it is the relying party, not the subscriber, who bears the risk of fraud or forgery in the transaction. If a document is forged or is fraudulently altered, the relying party will suffer the consequences, which, according to the law of most states, is that the message is treated as void. Although the relying party has the keenest interest in the information security of the transaction, the certification authority's service contract is entirely with the subscriber. In the case of a fraud or forgery, the subscriber may even be the perpetrator. The roles of the conventional system thus set the certification authority up to deal with relatively disinterested parties or even perpetrators in problem cases, but to have no contact with the party who primarily bears the loss. This state of affairs exposes the certification authority to serious liability risks in relation to the relying party and causes the certification authority to forgo the business opportunity of serving the relying party. Rather than dealing exclusively with the subscriber, the digital signature infrastructure also needs a way of dealing with the relying party.        Cost front-loaded onto subscriber: Since the certification authority's contract is with the subscriber alone, not with the relying party, the certification authority has no alternative but to recover all costs and profit from the subscriber, even though, as previously noted, the relying party has the principal interest in the security of the signed message.        Lack of robustness: Because the conventional system fails to address risk management and the needs of relying parties, certification authorities have tended to interpret their rotes narrowly. A certification authority may, for example, promise to look by rote at an apparent driver's license, or accept at face value a notarized application for certification, without purposefully endeavoring to serve the real business need for certification, which is to assure the expectations of the parties to the transaction. This mechanical approach to certification limits the potential for CAs to add further value to electronic commerce transactions. A more robust system needs to be serviceable for certifying authorization, accreditation, legal status of a juridical entity, and credit, for example.

This patent is subject to a terminal disclaimer.

Reliance server for electronic transaction system


Non-Volatile RAM Cell and Array using Nanotube Switch Position for Information State. A non-volatile memory array includes a plurality of memory cells, each cell receiving a bit line, word line, and release line. Each memory cell includes a cell selection transistor with first, second and third nodes. The first and second nodes are in respective electrical communication with the bit line and the word line. Each cell further includes an electromechanically deflectable switch, having a first, second and third node. The first node is in electrical communication with the release line, and a third node is in electrical communication with the third node of the cell selection transistor. The electromechanically deflectable switch includes a nanotube switching element physically positioned between the first and third nodes of the switch and in electrical communication with the second node of the switch. The second node of the switch is in communication with a reference signal. Each nanotube switching element is deflectable into contact with the third node of the switch in response to signals at the first and second node of the cell selection transistor and is releasable from such contact in response to a signal at the release line. In preferred embodiments, the cell selection transistor is a FET and the second node of the transistor is a gate of the FET.

Important characteristics for a memory cell in electronic device are low cost, nonvolatility, high density, low power, and high speed. Conventional memory solutions include Read Only Memory (ROM), Programmable Read only Memory (PROM), Electrically Programmable Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM).
ROM is relatively low cost but cannot be rewritten. PROM can be electrically programmed but with only a single write cycle. EPROM has read cycles that are fast relative to ROM and PROM read cycles, but has relatively long erase times and reliability only over a few iterative read/write cycles. EEPROM (or "Flash") is inexpensive, and has low power consumption but has long write cycles (ms) and low relative speed in comparison to DRAM or SRAM. Flash also has a finite number of read/write cycles leading to low long-term reliability. ROM, PROM, EPROM and EEPROM are all non-volatile, meaning that if power to the memory is interrupted the memory will retain the information stored in the memory cells.
DRAM stores charge on transistor gates that act as capacitors but must be electrically refreshed every few milliseconds complicating system design by requiring separate circuitry to "refresh" the memory contents before the capacitors discharge. SRAM does not need to be refreshed and is fast relative to DRAM, but has lower density and is more expensive relative to DRAM. Both SRAM and DRAM are volatile, meaning that if power to the memory is interrupted the memory will lose the information stored in the memory cells.
Consequently, existing technologies are either non-volatile but are not randomly accessible and have low density, high cost, and limited ability to allow multiples writes with high reliability of the circuit's function, or they are volatile and complicate system design or have low density. Some emerging technologies have attempted to address these shortcomings.
For example, magnetic RAM (MRAM) or ferromagnetic RAM (FRAM) utilizes the orientation of magnetization or a ferromagnetic region to generate a nonvolatile memory cell. MRAM utilizes a magnetoresistive memory element involving the anisotropic magnetoresistance or giant magnetoresistance of ferromagnetic materials yielding nonvolatility. Both of these types of memory cells have relatively high resistance and low-density. A different memory cell based upon magnetic tunnel junctions has also been examined but has not led to large-scale commercialized MRAM devices. FRAM uses a circuit architecture similar to DRAM but which uses a thin film ferroelectric capacitor. This capacitor is purported to retain its electrical polarization after an externally applied electric field is removed yielding a nonvolatile memory. FRAM suffers from a large memory cell size, and it is difficult to manufacture as a large-scale integrated component. See U.S. Pat. Nos. 4,853,893; 4,888,630; 5,198,994.
Another technology having non-volatile memory is phase change memory. This technology stores information via a structural phase change in thin-film alloys incorporating elements such as selenium or tellurium. These alloys are purported to remain stable in both crystalline and amorphous states allowing the formation of a bi-stable switch. While the nonvolatility condition is met, this technology appears to suffer from slow operations, difficulty of manufacture and reliability and has not reached a state of commercialization. See U.S. Pat. Nos. 3,448,302; 4,845,533; 4,876,667; 6,044,008.
Wire crossbar memory (MWCM) has also been proposed. See U.S. Pat. Nos. 6,128,214; 6,159,620; 6,198,655. These memory proposals envision molecules as bi-stable switches. Two wires (either a metal or semiconducting type) have a layer of molecules or molecule compounds sandwiched in between. Chemical assembly and electrochemical oxidation or reduction are used to generate an "on" or "off" state. This form of memory requires highly specialized wire junctions and may not retain non-volatility owing to the inherent instability found in redox processes.
Recently, memory devices have been proposed which use nanoscopic wires, such as single-walled carbon nanotubes, to form crossbar junctions to serve as memory cells. See WO 01/03208, Nanoscopic Wire-Based Devices, Arrays, and Methods of Their Manufacture; and Thomas Rueckes et al., "Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing," Science, vol. 289, pp. 94–97, 7 Jul., 2000. Hereinafter these devices are called nanotube wire crossbar memories (NTWCMs). Under these proposals, individual single-walled nanotube wires suspended over other wires define memory cells. Electrical signals are written to one or both wires to cause them to physically attract or repel relative to one another. Each physical state (i.e., attracted or repelled wires) corresponds to an electrical state. Repelled wires are an open circuit junction. Attracted wires are a closed state forming a rectified junction. When electrical power is removed from the junction, the wires retain their physical (and thus electrical) state thereby forming a non-volatile memory cell.
The NTWCM proposals to date rely on directed growth or chemical self-assembly techniques to grow the individual nanotubes needed for the memory cells. These techniques are now believed to be difficult to employ at commercial scales using modem technology. Moreover, they may contain inherent limitations such as the length of the nanotubes that may be grown reliably using these techniques, and it may difficult to control the statistical variance of geometries of nanotube wires so grown.
The ideal memory for at least some purposes is one which would offer low cost per bit, high density, fast random access, read/write cycle times of equal duration, low power consumption, operation over a wide temperature range, a single low-voltage power supply, with a high degree of radiation tolerance. The non-volatile described herein cell offers high speed read, but also high speed write (nanosecond) vs. the slow (microsecond & millisecond) write time of EEPROM and FLASH EEPROM type of memories. The memory is much denser than conventional SRAM because it has a two device, NT and 3 array line structure, and offers competitive performance. The density is less than that of DRAM cells, however, the product offers NDRO operation and non-volatility.
U.S. Patent Publication No. 2003-0021966 discloses, among other things, electromechanical circuits, such as memory cells, in which circuits include a structure having electrically conductive traces and supports extending from a surface of a substrate. Nanotube ribbons are suspended by the supports that cross the electrically conductive traces. Each ribbon comprises one or more nanotubes. The ribbons are formed from selectively removing material from a layer or matted fabric of nanotubes.
For example, as disclosed in U.S. Patent Application Publication No. 2003-0021966, a nanofabric may be patterned into ribbons, and the ribbons can be used as components to create non-volatile electromechanical memory cells. The ribbon is electromechanically-deflectable in response to electrical stimulus of control traces and/or the ribbon. The deflected physical state of the ribbon may be made to represent a corresponding information state. The deflected physical state has non-volatile properties, meaning the ribbon retains its physical (and therefore informational) state even if power to the memory cell is removed. As explained in U.S. Patent Application Publication No. 2003-0124325, three-trace architectures may be used for electromechanical memory cells, in which the two of the traces are electrodes to control the deflection of the ribbon.

Non-volatile RAM cell and array using nanotube switch position for information state


A semiconductor device includes an element formed on a first surface of a semiconductor substrate, a via-hole passing through the semiconductor substrate from the first surface to a second surface of the semiconductor substrate, and an electrode formed on the inner wall of the via-hole, the electrode passing through the semiconductor substrate from the first surface to the second surface. The electrode in the via-hole is electrically connected to at least one electrode of the element; the semiconductor substrate is mounted on a surface mount board; and the electrode formed on the inner wall of the via-hole is electrically connected to an electrode of the surface mount board by a conductive bonding material, such as a conductive adhesive. A method for fabricating the semiconductor device is also disclosed.

1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same. In particular, the invention relates to the structure of a semiconductor device, such as a high-frequency semiconductor device provided with back panel ground and a high-power semiconductor device provided with a heat-dissipating function.
2. Description of the Related Art
FIG. 1 is a sectional view of a conventional semiconductor device provided with a heat-dissipating function on the back surface. The semiconductor device includes a field-effect transistor (FET) 5, which includes a gate electrode 2, a source electrode 3, and a drain electrode 4, disposed on a semiconductor substrate (wafer) 1. The surface of the FET 5 is covered by an insulating film 6. A heat sink electrode (plated heat sink; PHS) 7 composed of Au or the like is formed on the entire back surface of the semiconductor substrate 1. A via-hole 8, which is tapered from the lower surface to the upper surface, is made in the semiconductor substrate 1, and the lower surface of the source electrode 3 is exposed to the via-hole 8. The lower surface of the source electrode 3 which is exposed to the via-hole 8 and the heat sink electrode 7 are electrically and thermally connected to each other by a via-hole electrode 9 composed of Au or the like formed in the via-hole 8.
When the semiconductor device is mounted on a surface mount board or the like, the heat sink electrode 7 on the back surface is connected to a ground line of the surface mount board.
A method for fabricating the semiconductor device will be briefly described. After the FET 5 is formed on the semiconductor substrate 1, etching is performed on the back surface of the semiconductor substrate 1 to form the via-hole 8 beneath. By depositing an electrode-forming metal, such as Au, on the inner wall of the via-hole 8 and on the entire back surface of the substrate 1, the via-hole electrode 9 and the heat sink electrode 7 are formed.
FIG. 2 is a sectional view of another conventional semiconductor device provided with a heat-dissipating function on the back surface. In order to fabricate this semiconductor device, a FET 5, which includes a gate electrode 2, a source electrode 3, and a drain electrode 4, is formed on a first surface (front surface) of a semiconductor substrate 1, and then etching is performed from the front surface of the semiconductor substrate 1 toward the second surface (back surface) to make a via-hole 11 which does not completely pass through the semiconductor substrate 1. Next, a wiring electrode 12 and a via-hole electrode 13 are continuously formed on the source electrode 3 and the inner wall of the via-hole 11, respectively. The semiconductor substrate 1 is then ground and etched from the back surface so that the via-hole 11 reaches the back surface of the semiconductor substrate 1 and the via-hole electrode 13 is exposed on the back surface of the semiconductor substrate 1. A heat sink electrode 7 is then formed on the entire back surface of the semiconductor substrate 1, and thus the heat sink electrode 7 and the via-hole electrode 13 are electrically and thermally connected to each other.
In a semiconductor device having either one of the structures described above, since the heat generated from the FET 5 is absorbed by the heat sink electrode 7 provided on the back surface through the via-hole electrode 9 or 13, and then is dissipated into the air or to the base of the package, etc., it is possible to reduce an increase in the temperature of the FET 5. The heat sink electrode 7 on the back surface is also used as a grounding electrode.
However, in the semiconductor device having such a structure, since the semiconductor substrate 1 and the heat sink electrode 7 are bonded to each other, when the temperature changes in the semiconductor device, the FET 5 is subjected to a mechanical stress due to a difference in the coefficient of thermal expansion between the semiconductor substrate 1 and the heat sink electrode 7, which may result in damage to the FET 5 and degradation in device performance. Additionally, since the heat sink electrode 7 must be formed on the entire back surface of the semiconductor substrate 1, the number of steps in the fabrication process of semiconductor devices increases, resulting in an increase in fabrication cost.
In the conventional semiconductor device shown in FIG. 1, since the via-hole 8 is made from the back surface of the semiconductor substrate 1, when the individually divided semiconductor devices (FET 5 chips) are mounted on the base of the package, etc., by die bonding, air bubbles are likely to remain between the via-hole 8 and the package, etc. If air bubbles are enclosed in the via-hole 8, the air bubbles may expand due to the heating in the fabrication process or heat generated by the semiconductor device, resulting in damage to the semiconductor device.
In the conventional semiconductor device shown in FIG. 2, since the via-hole electrode 13 must be exposed by grinding and etching the semiconductor substrate 1 from the back surface, the operation of decreasing the thickness of the semiconductor substrate 1 (grinding) must be stopped with exact timing when the via-hole electrode 13 is exposed on the back surface of the semiconductor substrate 1. In such a process, a technique for monitoring and controlling the grinding step with high accuracy is required.
Accordingly, it is an object of the present invention to provide a semiconductor device in which damage to the device and degradation in performance do not easily occur due to heating or a change in temperature, the control in the fabrication process is facilitated, and the fabrication cost is low, and to provide a method for fabricating the semiconductor device.
In one aspect of the present invention, a semiconductor device includes an element formed on a first surface of a semiconductor substrate, a via-hole passing through the semiconductor substrate from the first surface to a second surface of the semiconductor substrate, and a via-hole electrode formed on the inner wall of the via-hole, the via-hole electrode passing through the semiconductor substrate from the first surface to the second surface. The via-hole electrode is electrically connected to an electrode of the element, the semiconductor substrate is mounted on a surface mount board, and the via-hole electrode is electrically connected to an electrode of the surface mount board by a conductive bonding material, such as a conductive adhesive, e.g., silver paste.
In another aspect of the present invention, a method for fabricating a semiconductor device includes the steps of (a) forming a via-hole in a semiconductor substrate provided with an element so that the via-hole passes through the semiconductor substrate from a first surface to a second surface, and forming a via-hole electrode on the inner wall of the via-hole so as to be electrically connected to an electrode of the element and to pass through the semiconductor substrate from the first surface to the second surface; and (b) fixing the semiconductor substrate on a surface mount board by a conductive adhesive and electrically connecting the via-hole electrode and an electrode of the surface mount board by the conductive bonding material entering from the bottom opening of the via-hole electrode.
Preferably, the step (a) includes sub-steps of forming a concave section on the first surface of the semiconductor substrate, forming the via-hole electrode in the concave section; and milling the second surface of the semiconductor substrate so that the via-hole and the via-hole electrode are exposed on the second surface of the semiconductor substrate.
In accordance with the present invention, in the semiconductor device and the method for fabricating the same, since the via-hole provided in the semiconductor substrate and the electrode on the inner wall of the via-hole pass through the substrate from the first surface to the second surface, when the semiconductor substrate provided with the element is mounted on a surface mount board, such as a package, air is prevented from being entrapped in the via-hole, and thus there is no possibility that the semiconductor substrate is damaged by an expansion of air in the via-hole due to heating and a change in temperature, as is the case in the conventional semiconductor device.
Since the via-hole and the electrode on the inner wall thereof penetrate the semiconductor substrate, when the semiconductor substrate is mounted on a surface mount board, it is possible to check the position of the electrode of the surface mount board through the via-hole, thus facilitating the assembly of the semiconductor device. Furthermore, the semiconductor substrate is tightly fixed by the conductive adhesive which enters the via-hole from the surface of the surface mount board.
When the electrode on the inner wall of the via-hole is exposed on the second surface of the semiconductor substrate by decreasing the thickness from the second surface of the semiconductor substrate by grinding, etc., a technique for decreasing the thickness of the substrate with high accuracy is not required, unlike the conventional semiconductor device in which the electrode remains at the opened portion of the via-hole, thus facilitating the fabrication process.
As compared with the conventional semiconductor device, since an electrode for back panel ground, such as a PHS, is not provided on the back surface, there is no possibility that warping will occur in the semiconductor substrate due to a difference in the coefficient of thermal expansion between the semiconductor substrate and the electrode for back panel ground. Since the electrode for back panel ground is not required, the fabrication cost is reduced.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.

Semiconductor device and method for making the same


A tether device for pool floats includes a float attachment unit having an elongated cord with connectors permanently affixed to each end. A soft sleeve is positioned along the cord and between the connectors. The device also includes an anchor unit having a tether that is interposed between a weighted element and a hook.

Whether lounging in a backyard pool or taking a swim at the beach, pool floats are among the most common devices used by recreational swimmers. Whether the float is in the form of an inflatable inner tube or a foam lounger, swimmers and beach-goers alike utilize these extremely lightweight and portable floats for a variety of waterborne activities.
However, owing to their lightweight construction, many floats are extremely vulnerable to wind and currents when they are in the water. This is particularly true when the float is in open bodies of water such as the ocean, lakes and rivers, for example. As a result, it is not uncommon for a user who is occupying the float to be forced to continuously swim or paddle, in order to remain in the same general area. This is undesirable in many cases as one of the primary uses of the float is to allow the user to relax. In addition to the above, when the user is not resting on the float, care must be taken to prevent it from drifting away. In this regard, users are often forced to carry the float out of the water, where it is out of sight, and hope that no one steals it.
Although there are known anchor devices for boats and other large craft, these devices are not suitable for use in the above described situation, as the shape and material of these anchors would easily tear the float fabric if and when contact between the two surfaces is made. Moreover, owing to the large size of traditional anchors, there is no way to easily store the devices together when one or both are not being utilized.
Accordingly, it would be beneficial to provide a tether device that can be secured to any type of pool float in order to maintain the same in a stationary position when in the water, and without suffering from the drawbacks of the above noted devices.


The present invention introduces a new and refined method to produce α-Al2O3 layers with substantially better wear resistance and toughness than the prior art. The α-Al2O3 layer of the present invention is formed on a bonding layer of (Ti,Al)(C,O,N) with increasing aluminium content towards the outer surface. Nucleation of α-Al2O3 is obtained through a nucleation step being composed of both aluminising and oxidisation steps. The α-Al2O3 layer according to this invention has a thickness ranging from 1 to 20 μm and is composed of columnar grains. The length/width ratio of the alumina grains is from 2 to 12, preferably 5 to 9. The layer is characterised by a strong (012) growth texture, measured using XRD, and by the almost total absence (104), (110), (113) and (116) diffraction peaks.

In the description of the background of the present invention that follows reference is made to certain structures and methods, however, such references should not necessarily be construed as an admission that these structures and methods qualify as prior art under the applicable statutory provisions. Applicants reserve the right to demonstrate that any of the referenced subject matter does not constitute prior art with regard to the present invention.
A crucial step in deposition of different Al2O3 polymorphs is the nucleation step. κ-Al2O3 can be grown in a controlled way on {111} planes of TiN, Ti(C,N) or TiC having the face-centered cubic structure. Transmission electron microscopy (TEM) has confirmed the growth mode which is that of the close-packed (001) planes of κ-Al2O3 on the close-packed {111} planes of the cubic phase with the following epitaxial orientation relationships: (001)κ//(111)TiX; [100]κ; [112]TiX. An explanation and a model for the CVD growth of metastable κ-Al2O3 has been proposed (Y. Yoursdshahyan, C. Ruberto, M. Halvarsson, V. Langer, S. Ruppi, U. Rolander and B. I. Lundqvist, Theoretical Structure Determination of a Complex Material: κ-Al2O3, J. Am. Ceram. Soc. 82(6)1365-1380 (1999)).
When properly nucleated, κ-Al2O3 layers can be grown to a considerable thickness (>10 μm). The growth of even thicker layers of κ-Al2O3 can be ensured through re-nucleation on thin layers of, for example, TiN inserted in the growing κ-Al2O3 layer. When nucleation is ensured the κ→α transformation can be avoided during deposition by using a relatively low deposition temperature (<1000° C.). During metal cutting high temperature conditions may be created such that the κ→α phase transformation has been confirmed to occur. In addition to phase stability there are several reasons why α-Al2O3 should be preferred for many metal cutting applications. α-Al2O3 exhibits better wear properties in cast iron, as discussed in U.S. Pat. No. 5,137,774. Further, a layer which has been nucleated as α-Al2O3 does not contain any transformation cracks and stresses. Nucleated α-Al2O3 should be more ductile than α-Al2O3 formed totally or partially as a result of phase transformation, and even more ductile than κ-Al2O3, the plasticity of which is limited by the defect structure.
However, a stable α-Al2O3 phase has been found to be more difficult to be nucleated and grown at reasonable CVD temperatures than the metastable κ-Al2O3. It has been experimentally confirmed that α-Al2O3 can be nucleated, for example, on Ti2O3 surfaces, bonding layers of (Ti,Al)(C,O), as shown in U.S. Pat. No. 5,137,774, or by controlling the oxidation potential using CO/CO2 mixtures, as shown in U.S. Pat. No. 5,654,035. The bottom line in all these approaches is that nucleation must not take place on the 111-surfaces of TiC, TiN, Ti(C,N) or Ti(C,O,N), otherwise κ-Al2O3 is obtained.
It should also be noted that in conventional prior art methods higher deposition temperatures are usually used to deposit α-Al2O3. When the nucleation control is not complete, as is the case in many conventional products, the resulting α-Al2O3 layers have, at least partly, been formed as a result of the κ-Al2O3→α-Al2O3 phase transformation. This is especially the case when thick Al2O3 layers are considered. These kind of α-Al2O3 layers are composed of larger grains with phase-transformation cracks. These coatings exhibit much lower mechanical strength and ductility than α-Al2O3 coatings that are composed of nucleated α-Al2O3.
The control of the α-Al2O3 polymorph on an industrial scale was achieved in the beginning of the 1990's with commercial products based on U.S. Pat. No. 5,137,774. In addition, α-Al2O3 has been deposited with preferred coating textures. In U.S. Pat. No. 5,654,035 an alumina layer textured in the (012) direction, and in U.S. Pat. No. 5,980,988 an alumina layer textured in the (110) direction are disclosed. In U.S. Pat. No. 5,863,640 a preferred growth either along (012), (104), or (110) directions is disclosed. U.S. Pat. No. 6,333,103 describes a modified method to control the nucleation and growth of α-Al2O3 along the (10(10)) direction.


A FET bidirectional switching arrangement comprises first and second FETs, and a limiting arrangement connected to the FETs. The FETs are operable in response to a first bias condition to pass current in series through the FETs in either of two opposite directions, and operable in response to a second bias condtion to block current through the FETs in both of the two opposite directions. The limiting arrangement senses the direction of current flowing through the FETs and limits a forward bias on a first pn junction of the first FET when the current flows in a first direction of the two opposite directions to limit undesired current flow through the first pn junction of the first FET. When the current flows in a second direction of the two opposite directions, the limiting arrangement limits a forward bias on a first pn junction of the second FET to limit undesired current flow through the first pn junction of the second FET.

A known FET switching arrangement comprises two FETs connected source-to-source and gate-to-gate, each FET having a substrate or bulk region which is connected to its source. A biasing impedance is connected between the gates and sources of the FETs. The FETs are turned on by drawing bias current through the biasing impedance to develop a voltage between the gates and sources of the FETs which exceeds the threshold voltage of the FETs. When the FETs are turned on, the arrangement can pass current through the two FETs in series in either of two opposite directions. In the absence of such bias current, the biasing impedance ensures that the FETs are off, so that the arrangement blocks current in both of the two opposite directions.
When the FETs are turned on, and current is passed through the FETs in series, a pn junction defined by the drain and substrate or bulk region of one of the FETs is forward biased. The forward bias is the product of the current passed by the FETs and the on-impedance of the FETs. If this product is too large, the forward biased pn junction can inject enough carriers into the substrate or bulk region to cause undesired latching.
To avoid this problem, the FETs must be made large enough to ensure that their on-impedance will not develop sufficient voltage to turn on the pn junction at the maximum current to be passed by the switching arrangement. For many applications, the FETs must be made so large that, where the switching arrangement is part of a monolithic integrated circuit, its area has a significant impact on the total size and therefore the cost of the integrated circuit. A FET switching arrangement which permits the use of smaller FETs for most applications would therefore be desirable.
Another known FET switching arrangement combines a diode bridge with a single FET. The diode bridge is used to ensure that current flows in the same direction through the FET when the FET is on, regardless of the direction of current flow between external terminals of the switching arrangement. The direction of current flow through the FET is arranged to ensure that the pn junction defined by the drain and the substrate or bulk region is never forward biased, so that latching is not a problem.
Unfortunately, the diode bridge is required to withstand the full voltage applied to the switching arrangement without passing current when the FET is off. High voltage diodes are needed to meet this requirement, and such high voltage diodes are not available in many of the semiconductor technologies in which FET switching arrangements may be implemented.
In some FET circuits, the problem of undesired carrier injection into the substrate or bulk region of the FETs is avoided by applying an appropriate DC bias to the substrate or bulk region to ensure that the pn junctions through which such injection could occur are never forward biased. The DC bias applied to the substrate or bulk region is referenced to fixed supply voltages which power the FET circuits.
Unfortunately, this approach is not readily applicable to FET switching arrangements which do not have fixed supply voltages limiting the range of voltages applied to the FETs.

FET bidirectional switching arrangements and methods for preventing pn junctions of FETs from being forward-biased


The present disclose relates to a lens unit. The lens unit includes a first lens and a second lens. The first lens includes a first light input surface, a first light output surface opposite to the first light input surface and a first side surface connected to the first light output surface. The first lens has a first refractive index. The second lens defines a cavity at a light input surface thereof for receiving the first lens. The second light output surface of the second lens contacts the first light output surface and the first side surface of the first lens. The second lens has a second refractive index which less than the first refractive index. The present disclose also relates to a light source module with the lens unit.

1. Technical Field
The disclosure relates to a lens unit and a light source module with the lens unit.
2. Discussion of Related Art
Light emitting diodes (LEDs) with many advantages, such as high luminosity, low operational voltage, low power consumption, compatibility with integrated circuits, faster switching, long term reliability, and environmental friendliness have promoted their wide use as a lighting source.
However, the conventional LED cannot have a wide illumination area even use with a diverging lens. The light having a large incidence angle on the light emerging face of the diverging lens, may be totally reflected backwardly into the diverging lens. Thus, the radiation angle of the light emitted out of the diverging lens is limited, generally less than 120 degrees. In other words, the light intensity dramatically decreases when the radiation angle exceeds 120 degrees.
Therefore, what is needed is a lens unit and a light source module with the lens which can overcome the described limitations.

Lens unit and light source module with same


A method for performing at least one jump in a program executed by a processor, including determining a result over several bits as an indicator that a desired condition has been complied with, the result corresponding to an operation taking into account at least one predetermined value and at least one current value; and calculating a jump address which is a function of the result.

1. Field of the Invention
The present invention generally relates to the implementation of instruction jumps in a program executed by a microprocessor. The present invention more specifically relates to jumps performed by a program implementing secret quantities which are desired to be made undetectable from a possible pirate.
2. Discussion of the Related Art
In most programs or algorithms executed by a microprocessor, conditional jumps, that is, steps during which the program selects the next instruction to be executed from among two different instructions, can be found. Such jumps are generally decided according to the state of a flag or condition bit. According to the state of the flag bit, the program execution carries on with one instruction or the other. At this time, the conditional jump intervenes to direct the program towards a different address.
Such an operation is fully satisfactory in many applications. However, in programs handling secret quantities or more generally implementing algorithms for which it is not desired for an unauthorized user to be able to modify the program sequencing, such jumps form particularly vulnerable points.
In particular, a widespread type of attack to deduce secret quantities from the execution of an algorithm, known as the fault injection attack, consists of forcing a trap in a program by introducing a disturbance (for example, on the processor supply), at strategic program execution positions. Such fault injections then enable discovering the handled secret quantities. For example, and in simplified fashion, if a conditional jump verifies the exactness of a key with respect to a pre-recorded key, the conditional jump to the authorized instructions must not occur if the right key is not introduced in a corresponding variable of the program. By presenting a wrong key and causing disturbances on the program execution (fault injection), a wrong (illicit) conditional jump resulting in the accepting of the wrong key will statistically occur. Now, it is enough for the jump to be authorized once to enable a pirate to exploit the processings performed by the algorithm and thus hack the program.
FIG. 1 very schematically illustrates an execution mode of a conventional jump in a program. Whatever the variables processed at input E, each time a test (block 1, IF) is provided in a program, the next instruction in the program development is different at least in its execution address. For example, if the test is negative (output state 0), the executed instruction often is the next instruction (block 2, NEXT). However, if the test is validated (output state 1), the program executes an instruction (block 3, JUMP) at another address @ in the program or in a sub-program. The two outputs may condition jumps on different addresses.
To protect the program execution against fault injections, two techniques are conventionally used.
FIG. 2 very schematically illustrates, in the form of blocks, a first technique for protecting the execution of a program against fault injections. This techniques consists of performing two executions (block 10, EXEC 1 and block 11, EXEC 2) of the same program in parallel, or shifted in time, and of comparing (BLOCK 12, COMP), the results provided by each of the executions to validate the correct execution of the program. Comparator 12, for example, provides a state bit VALID indicating that the results of the two executions are identical, thus validating the program execution with no fault injection. The used result indifferently is that of one or the other of the executions (for example, that of block 10).
A disadvantage of this technique is either that it requires two hardware program execution cells in the case of a parallel execution, or that it takes time since the program must be executed twice before a valid result can be taken into account.
A second known technique consists of calculating signatures of two executions in parallel of the same program for, here again, comparing the signatures with a pre-recorded signature or with each other. As in the case of FIG. 2, this requires two executions and thus two hardware cells, or twice as much time. Further, the integrated circuit executing the program must have the functions enabling calculation of such signatures.
An additional disadvantage of the two above-described conventional techniques is that they only enable a detection a posteriori.
A technical problem is that a program must have a reproducible execution, that is, that it must develop correctly in the absence of a piracy attempt. In other words, this technical problem is linked to the fact that the program and especially the conditional jumps must be provided in advance for a given operation of the program, which makes it sensitive to fault injection attacks.
Document WO-A-00/42511 discloses a jump system in a program, in which a jump address is a function of a test result taking into account a base address and a variable. This document aims at avoiding attacks based on power analysis of the integrated circuit executing the program. Such a solution is ineffective against fault injection attacks to which relates the present invention.

Protection of a program jump from fault injection by masking a memory address with a random number


A battery provided with one end of each lead element connected to the positive and negative electrode respectively is drawn out from the can body 3 through a space 6 formed at a surface part of said jointed flange section 32a, 32b and the area of the flange section around the drawing space is sealed by a resin bonding. The battery provided with a new structure which can solve the problems which may be generated in all fields, such as battery shape, attachment property, battery strength, productivity and so on in order to make a thin type battery.

This invention relates to a battery suitable for using for power supply of small electric devices such as pocket electric equipments, especially to a thin type battery.
As the battery used for the power supply of small electric devices, there have been used, for example cylindrical and square shaped ones. The cylindrical or square shaped battery is provided with a metal can body which is made into a cylindrical shape or a prismatic shape respectively by means of a deep drawing process.
On the other hand, for a battery used for small and portable electric devices such as personal information terminals and portable telephones, relatively thin shaped batteries have been used as follows.
1) Type of metal can made by a deep drawing process in which an opening thereof is engaged with a metal lid by welding as shown in Japanese publication (unexamined) No. 11-185820.
2) Type of combination a laminated battery with an outer case for decreasing the total thickness thereof, which battery is made of lamination of metal foils such as aluminum foils with resin as shown in Japanese publication (unexamined) No. 8-83596.
3) Type of a shallow metal can like a lunch box made by a shallow drawing process in which an opening thereof is engaged and welded with a metal lid as shown in Japanese publications (unexamined) Nos. 11-185820, 9-213286, 2001-167744 and 2001-250517.
Nowadays, due to spread of the portable information terminals and cellular phone, a request for small light-weight to electric devices becomes stronger and therefore the demand for making a thinner battery becomes stronger.
However, in case of using the Type 1), there is limitation as to a formable size made by the deep drawing process. For example, it is quite difficult or impossible for the present deep drawing process to make a battery having a thickness of less than 3 mm.
Further, in case of making it into less than 3 mm in thick, there are the following problems as to the deep drawing process.
A) The opening width of battery becomes too thin to insert the electrode therethrough into the battery can body as the battery becomes thinner.
B) The metal lid for sealing the opening of battery can is provided at attaching holes thereof with terminals through an insulating packing or gasket. When the opening width becomes narrow and the insulating packing becomes close to the opening edge, heating during a welding process of the metal lid to the metal can will tend to melt the insulating packing.
C) The deep drawing process needs wrought materials such as formable kinds of metal. But, such materials having a small hardness are not strong against expansion of the battery. Thereby, the materials having a light-weight and a good strength as well as a strong hardness can not be used in the deep drawing process.
At the present, therefore a desired thin type battery has to be made by using lamination of film material as shown in the above 2) where metal foils having a thickness of less than 100 μm are laminated with resin. As for the laminated film materials, there is such a problem that the materials do not have enough strength against sticking and folding motions.
In case of Type of the can 3) made by shallow drawn process as shown above, for example although the batteries shown in the Japanese publications can avoid the problems as mentioned in Type of the can 1) made by deep drawn process, there are the following problems.
In this case, as a method for welding the circumference edge of lid with the opening edge of metal can, there has been used one of the groups consisting of a laser welding, a resistance welding, an ultrasonic welding and so on. However, it is necessary to seal takeoffs for leads connected to positive and negative electrodes as well as outer case of the battery by a metal welding. Further, in this structure where the metal lid is electrically connected to the metal lid to the metal can, the sealing of takeoffs needs a complete insulating treatment. In this case, there is generally used a resin packing for caulking. The sealing made by caulking is not reliable to avoid invasion of the humidity and leakage of the electrolyte in comparison with the sealing made by the metal welding and resin fusing. Therefore, in case of Type 3) more than two processes are needed to get a good reliability for avoiding leakage of the electrolyte, resulting in a bad productivity, due to problems such as large number of the production control items and their complexity.
On the other hand, in case of Type 2) the outer case made of lamination films can be sealed by resin, through which lead elements, connected to electrodes accommodated in the battery, are drawn out therefrom. In this structure, the sealing of the battery can be made at the same time of sealing the terminal drawing section, thereby a good productivity can being improved. However, in addition to the weak point of battery strength as mentioned above, there are further problems as follows when a secondary battery is provided with a necessary protection circuit.
In this type of battery using lamination films, a part of the lead element is protruded from the outer case and the protection circuit connected to the lead element is positioned outside of the battery, so that the volume energy density will become low. Although there is a method of bending the protection circuit linked to the lead toward the battery side and arranging the protection circuit on the sealing portion with resin, it is very difficult to make a further space for arranging the protection circuit and also to keep the position precision of the protection circuit after bending the lead element, resulting in a bad productivity.


A modeling system provides a display of a computer system's configuration along with selected system metrics. An operator can change the configuration by using the display and display commands. Metrics representative of the performance of the computer system would then be determined for the changed configuration, and could presented along with the display of the new system configuration.

The present invention relates to the field of automatic performance analysis and capacity planning and, more specifically, to the field of automatic performance analysis and capacity planning of computer systems which have been modified in response to interactive operator input.
Performance analysis in computer systems is used to determine the effectiveness and efficiency of a computer system's management of its workloads. The term "workload" refers to processes running on a computer system. Different types of processes are often treated as different workloads. For example, word processing is often considered as one workload even though several computer system users are operating word processing programs. Similarly, spreadsheets could be considered as a distinct workload.
Each workload requires system resources, such as CPU (central processing unit) processing time or disk capacity. Performance analysis is designed to facilitate the management of such system resources.
In carrying out performance analysis, one must always measure some values for computer system and component parameters in order to determine efficiency and efficacy. The parameter being measured have been referred to as "metrics." Examples of metrics are the number of cache in a particular time period, or the length of a device's queue. Metrics are discussed more fully in U.S. Pat. No. 4,849,879 to Chinnaswamy et al., which is incorporated herein by reference.
The metrics reflect the performance of the computer system in a particular configuration. The term "configuration" is used to refer not only to the types and interconnection of physical components, but also to the distribution of the workloads among the components.
Most conventional methods of performance analysis and capacity planning involve presenting selected information in reports. The reports are usually tabular presentations of data. Usually several different kinds of reports are needed for analysis. For example, one report might indicate the system configuration in terms of components, another report might indicate the system configuration in terms of workload, and another report may list certain metrics of interest.
One performance analysis and capacity planning product which generates tabular reports is the DECcp or DEC Capacity Planner for VMS made available by Digital Equipment Corporation for use with certain VAX computers. This product collects, reduces, analyzes, models and reports data in a tabular format for purposes of computer system capacity planning. Another such product is the VAX Performance Advisor made available by Digital Equipment Corporation to provide information useful in analyzing the performance of certain VAX computers.
Although the tabular presentation of data may be acceptable for determining the performance of a computer system in one configuration, it does not lend itself well to analyzing the performance of the computer system if its configuration were modified. Such analysis is important in determining whether and how to reconfigure a system.
For example, if performance analysis indicated an overload or bottleneck condition in a computer system, the system should be tuned or reconfigured to alleviate such conditions. It is not always apparent, however, which tuning or reconfiguration is the most appropriate. Physical reconfiguration of a system without knowing whether that reconfiguration will be effective is both impractical and costly.
To avoid unnecessary or incorrect reconfiguration, system engineers try to construct a model based upon actual system parameters. In this way, modeling may be used to measure the impact of certain actions on system performance before physically reconfiguring a computer system.
Modeling can also be used in sales. If a modeling technique were not too cumbersome, salespeople could use it to determine whether additional components were needed for a particular customer, or whether a customer's problems or needs could be handled in other ways.
Conventional performance analysis systems, however, do not lend themselves well to such uses. A common means of performing modeling involves using the information gathered as part of the performance analysis to calculate the effect of reconfiguring a computer system. This is both time consuming and inaccurate.
Systems such as the DECcp system will perform certain automated calculations, however, the calculations are presented in a tabular format, which may again require the use of several sheets or tables to analyze results.
It is therefore desirable to provide a mechanism for performance analysis that allows for a more meaningful presentation of performance information.
Another desire is to provide an improved mechanism for changing the configurations of the computer system, at least in a virtual sense, to determine the effects of such changes.
An additional desire would be to provide an improved mechanism for presenting the effects of the changes in configuration in a manner which allows ready decision making.
Additional advantages of this invention will be set forth in part in the description which follows and in part will be obvious from that description, or may be learned by practice of this invention. The advantages of this invention may be realized and attained by means of the instrumentalities and combinations particularly pointed in the appended claims.

Dynamic computer system performance modeling interface


A clamping device comprises a driving cylinder, a buffering assembly, a first clamping member, and a second clamping member. The first clamping member and the second clamping member are mounted to the driving cylinder. The buffering assembly comprises a fixing member, a guiding rail, a guiding rod, and an elastic member. The fixing member comprises a first mounting portion and a second mounting portion. The first mounting portion defines a through hole. The guiding rail is mounted to the fixing member and located between the first mounting portion and the second mounting portion. The driving cylinder is mounted to the guiding rail. A first end of the guiding rod is movably received through the through hole, and a second end of the guiding rod is fixed to the driving cylinder. Opposite ends of the elastic member resist against the first mounting portion and the driving cylinder, respectively.

1. Technical Field
The present disclosure relates to clamping devices, and particularly to a clamping device capable of compensating for a tolerance of a workpiece.
2. Description of Related Art
In automatic assembly of electronic components, a clamping device may clamp a first workpiece to be assembled to a second workpiece. However, a tolerance or a deformation of the first or second workpiece may lead to a deviation of clamping and assembling of the first workpiece to the second workpiece.
Therefore, there is room for improvement in the art.

FU DING ELECTRONICAL TECHNOLOGY (JIASHAN) CO.,LTD.


A power conversion system, a controller for the same, and a method for controlling the same. The power conversion system includes a shutdown array and a power converter. The shutdown array includes multiple shutdown strings that are connected in parallel. Each of the multiple shutdown strings includes multiple shutdown devices, where outputs of the multiple shutdown devices are connected in series. An output terminal of the shutdown array is connected to an input terminal of the power converter. An input terminal of each of the multiple shutdown devices is connected to at least one direct-current power supply. The controller sends a shutdown instruction to each shutdown device of the shutdown array in response to receiving a rapid-shutdown command, controls the power converter to discharge an input capacitor of the power converter, and stops discharging the input capacitor in response to an input voltage of the power converter being reduced to a preset voltage.

In a distributed power generation system, multiple direct-current (DC) power supplies are connected in series or in parallel as a whole, to provide a DC input voltage for a power converter. The DC input voltage is converted into a required output voltage by the power converter. An overall output voltage of the multiple DC power supplies may be as high as several hundred volts or even thousands of volts. Hence, there is a risk of an electric shock.
A conventional solution for preventing an electric shock is to provide a shutdown device for each DC power supply. In a case that someone approaches, a controller sends a shutdown instruction to each shutdown device, so as to shut down the output of each DC power supply. Thereby, all connections among the DC power supplies are cut off, and the DC power supplies stop providing the DC input voltage for the power converter.
A large amount of electric charges remains stored in an input capacitor of the power converter after shutting down the output of each DC power supply. Hence, the risk of the electric shock still exists in a case that the electric charges in the input capacitor are not discharged in time.

Power conversion system, controller for the same, and method for controlling the same


A nonvolatile semiconductor storage device and writing method thereof are capable of concurrently executing a write operation and a verify operation of multi-value data into a plurality of memory cells and writing multi-value data at high speed. Latch circuits of Latch0 and Latch1 store an input multi-value data to be written into a memory cell selected by a bit line and a word line. Multi-value sense amplifiers read the multi-value data written in the memory cell. Based on the input multi-value data (latch nodes Q0#, Q1#) stored in the latch circuits of Latch0 and Latch1 and the multi-value data (sense nodes S0#, S1#) read from the memory cell by the multi-value sense amplifiers, a bit line voltage generating circuit applies a specified voltage for writing the input multi-value data into the memory cell to the bit line connected to the memory cell.

The present invention relates to a nonvolatile semiconductor storage device for writing parallel multi-value data into a plurality of memory cells.
The nonvolatile semiconductor storage devices have made a remarkable progress in recent years, and their storage capacities are rapidly increasing. Accordingly, as a method for increasing the storage capacity through the same manufacturing processes as those of the prior art, there is the method of increasing the number of bits of information that can be stored in one memory cell (i.e., providing the so-called multi-value structure). In this multi-value nonvolatile semiconductor storage device, the threshold voltage of each memory cell is controlled. In the above nonvolatile semiconductor storage device, four values (two bits per cell in terms of the amount of information) are stored into one memory cell, and the values are made to be "0, 0", "0, 1", "1, 0" and "1, 1" in descending order of the threshold voltage of the memory cell. Assuming that the data "0, 0" represents an erased state, then a write operation is executed by shifting the threshold voltage of the memory cell in this erased state to the lower threshold voltages in order of the data "0, 1", "1, 0" and "1, 1". Although there is also a nonvolatile semiconductor storage device wherein the threshold voltage of the memory cell from which data has been erased is lower than the threshold voltage of the memory cell into which data has been written, it is essentially the same.
As a nonvolatile semiconductor storage device for writing such multi-value data, there has been proposed one which independently operates a write operation and a verify operation in the order of, for example, "0, 1", "1, 0" and "1, 1" ("A 3.3V 128 Mb Multi-Level NAND Flash Memory for Mass Storage Applications" ISSCC96 DIGEST OF TECHNICAL PAPERS P32-P33).
However, the above nonvolatile semiconductor storage device has the following problems (1) through (4).
(1) Since the verify operation is executed every multi-value data, the time necessary for this verify operation is prolonged to be about three times that in the case of binary value when, for example, four-value data is stored into one memory cell.
(2) Since a word line voltage at the time of the write and verify operations must be varied in accordance with the threshold voltage of the multi-value data to be verified, a time for varying the word line voltage is necessary.
(3) Since the voltage applied to the bit line is constant regardless of the value of the multi-value data in the write stage and a voltage that ranges from a negative voltage of a small absolute value for the data "0, 1" to a negative voltage of a large absolute value for the data "1, 1" is applied to the word line, many write pulses are necessary.
(4) There is caused gate disturbance of the memory cells commonly connected to an identical word line.

Nonvolatile semiconductor storage device and writing method thereof


A card (which is displayed on a screen by the card application and is thus operated, and has a single function) is output to a display of an information processing device through a shell (an OS for controlling card application and a seal application), and a seal (a display associated with an action such as an output) can be placed on a part of the card. The seal placed on the card is written to a seal DB and the seal placed on the card is displayed in accordance with information of the seal DB when the card is to be output. The seal corresponds to a seal application depending on each type. When an object of the card having the seal placed thereon is coincident with a predetermined condition, the corresponding seal application is activated by the shell so that a predetermined action such as a notice or an output of a ring tone is executed.

[1. Field of the Invention]
The present invention relates to an information processing program, an information processing device and an information processing method which execute a predetermined action corresponding to a seal displayed on a card screen displayed on a display.
[2. Description of the Related Art]
Various functions such as a schedule control and a transmission/receipt of an electronic mail which are offered through a personal computer, a portable telephone, a PDA or the like are implemented by an application program which is compatible with each of the functions, for example, a scheduler, a mailer or the like. A large number of processes are executed in accordance with the application program through a predetermined input operation carried out by a user. However, there are also offered some processes to be automatically executed in accordance with the application program when a predetermined event is generated by causing the user to previously set some event as a trigger.
For example, there is disclosed an invention related to the technique for setting, as a trigger, an event in relation to distance information or position information which is detected by a device, traffic information or weather information which is received by the device, or the like. Then automatically displaying information corresponding to each event in a generation of the set event in addition to a function for setting, as a trigger, an event of an arrival of a predetermined date and time, thereby automatically giving a notice of a schedule when the date and time is reached in an application program (a scheduler) for a schedule control (for instance, see Patent Document 1: Japanese Laid-Open Patent Publication No. 2003-162512).
In another example of the application program, there is disclosed an invention related to the technique for setting, as a trigger, an event of an incoming mail from a predetermined transmitter and reproducing a ring tone set for every transmitter when the incoming mail arrives in an application program (a mailer) for receiving a mail such as a chat mail (for instance, see Patent Document 2: Japanese Laid-Open Patent Publication No. 2006-060431).
In the examples described in the Patent Documents 1 and 2, the event designated by a user (a condition related to a date and time, a position, traffic, weather or the like, an incoming mail from a predetermined transmitter, or the like) is set as a trigger for executing a predetermined action (a display of a notice or information, a reproduction of a ring tone or the like) in each of the application programs. However, it can be supposed that the methods are limited in the following respects.
First of all, the event set as the trigger for executing the predetermined action cannot be visually grasped by the user. For example, in the case in which a computer is not utilized but a notebook is used to control a schedule, a seal capable of distinguishing each event is put on a corresponding date and time portion of a calendar with respect to a date and time that a meeting or an appointment is planned, a memorial day or the like in such a manner that it is possible to visually recognize a date and time that the event is planned and the type of event. In the examples described in the Patent Documents 1 and 2, however, importance is attached to an object for giving a notice of an event or the like and there is no consideration for using an attainment of an object to visually grasp an event of which notice is set to be given, or the like.
Secondly, both an action which can be executed and an event which can be set to execute the action depend on the respective application programs. For this reason, it is impossible to flexibly set their combination. For example, an original sound effect is prepared for the action which can be executed. It is necessary to carry out setting for adding, as an action capable of being executed, a reproduction of the sound effect to an application program for a schedule control if the reproduction is to be utilized for a notice given when a predetermined date and time arrives and to an application program for a mail transmission/receipt if the same reproduction is to be utilized for giving a notice of an incoming mail from a predetermined transmitter, respectively.
In other words, there are restrictions that a user can only use a combination of an event and an action which are offered by each of the application programs, while there is attached a condition that a provider of the application program should offer, as a set, both a program for controlling an event and a program for executing an action.

Information processing program, information processing device and information processing method


A tape cartridge that is to be mounted on a tape printing device including a detecting portion for reading various types of information of the tape cartridge from a detected portion of the tape cartridge by applying detection light to the detected portion and capable of being attached to and detached from the tape printing device along a mounting direction, includes the detected portion disposed on a first wall which is formed along the mounting direction, and an engaging portion disposed on a second wall which is formed at a deep side of the mounting direction. The engaging portion is engaged with an engaged portion provided in a holder in which the detecting portion is disposed and performs positioning between the detecting portion and the detected portion via the holder.

1. Technical Field
The present invention relates to a tape cartridge to be attached in a detachable manner to a tape printing device.
2. Background Art
Conventionally, as a tape printing device (tape writer) in which the tape cartridge of this type is used, a tape printing device including a body case that houses various mechanisms, a cartridge mounting portion for detachably mounting the tape cartridge, and five photointerrupters that are arranged on an inner wall of the cartridge mounting portion in a line is known (see Japanese Patent No. 3247585).
The tape cartridge has a specification display seal for identifying the specification of a printing tape and strange printing ink in a side surface portion. On the other hand, five photointerrupters are disposed so as to face the specification display seal. Then, the five photointerrupters detect whether or not black ink is printed in five specification display portions formed in the specification display seal and identify the specification based on a detection result.


A discharge lamp lighting device includes a high frequency power supply for supplying high frequency power to the discharge lamp via a first impedance element, a DC power supply for applying DC voltage to the discharge lamp via a second impedance element, a dimming control circuit for carrying out a dimming of the discharge lamp by controlling the power supplied to the discharge lamp, a DC voltage detection circuit for detecting a DC component of the voltage applied to the discharge lamp, and an output correction unit for making a correction to the power supplied to the discharge lamp in accordance with a value detected by the DC voltage detection circuit. It can light the discharge lamp stably regardless of a variation in temperature.

A dimmable discharge lamp lighting device is disclosed in U.S. Pat. No. 5,170,099. This disclosure is directed to provide a discharge lamp lighting device that can stably light a discharge lamp even at a low light flux level of less than 20% of its rated light illumination flux level. The disclosed discharge lamp lighting device includes a low-pressure mercury arc discharge lamp; a high frequency power supply for supplying a high frequency power to the discharge lamp; a dimming control circuit for carrying out a dimming of the discharge lamp from an arc discharge zone to a glow discharge zone; and a DC power supply that supplies to the discharge lamp a DC power at a level capable of maintaining discharge upon a low light flux dimming, the DC power being superposed on the high frequency power.
The above configuration enables stable dimming control of the light of the discharge lamp even at a low illumination level, without being extinguished or darkened under a normal condition.
However, the above conventional device has problems in that the vapor pressure of mercury in the discharge lamp is dependent upon a temperature, and thus the performance thereof is susceptible to the variation of ambient temperature. Especially, a low ambient temperature generally induces an increase in an equivalent impedance of the discharge lamp, which in turn results in the decrease in the DC power that is supplied to the discharge lamp. Consequently, a light flux from the discharge lamp is reduced, and therefore a flickering or an extinguishment of the lamp may occur.
Another dimmable discharge lamp lighting device is disclosed in Japanese Patent No. 3293650, which includes an inverter circuit with variable output for lighting a discharge lamp having a filament; a power detection unit for detecting a voltage in response to an output power of the inverter circuit; an output comparing unit for comparing the voltage detected by the power detection unit and an output reference voltage; a lamp voltage detection unit for detecting a voltage of the discharge lamp; a lamp voltage comparing unit for determining whether a voltage detected by the lamp voltage detection unit is higher than a lamp reference voltage; and an offset unit, in case where the voltage detected by the lamp voltage detection unit is determined to be higher than the lamp reference voltage, for reducing the voltage detected by the power detection unit relatively to the output reference voltage, whereby the reduced voltage is compared with the output reference voltage by the output comparing unit. The above lamp lighting device further includes a control unit. In a normal case, the control unit controls the output power of the inverter circuit depending on an output of the output comparing unit to stabilize the output power of the inverter circuit according to a preset lighting condition of the discharge lamp. However, in case where the lamp voltage detected by the lamp voltage detection unit is determined to be higher than the lamp reference voltage, the control unit controls the output power of the inverter circuit depending on the output of the output comparing unit while relatively reducing the voltage detected by the power detection unit by the offset unit.
In this way, if the voltage of the discharge lamp increases to be higher than the lamp reference voltage, the voltage detected in response to the output power of the inverter circuit is corrected to be lower than the actually detected level, enabling the output power of the inverter circuit to be increased in comparison with a case where the lamp voltage is not higher than the lamp reference voltage, which in turn prevents the discharge lamp from being extinguished.
Since the output of the inverter circuit is increased in case the lamp voltage is higher than the lamp reference voltage, the above conventional dimmable discharge lamp lighting device is considered to be able to prevent the discharge lamp from being extinguished and flickered when a current-voltage characteristic of the discharge lamp is within a negative domain. However, when the optical output of the discharge lamp is lowered down to equal to or less than 10% of the rated level for example, the current-voltage characteristic of the discharge lamp goes into a positive domain. In this case, since a lamp voltage decreases in company with a decrease of a lamp current, the conventional dimmable discharge lamp still suffers from extinguishment and flickering problems.


Present embodiments include a control system for one or more battery cells. The control system includes a bi-stable relay configured to switch a state of the bi-stable relay upon receiving a control signal to electrically connect or electrically disconnect the one or more battery cells to a bus and to remain in the state after receiving the control signal. The control system includes a controller configured to be operatively coupled to the bi-stable relay and configured to send the control signal indicative of instructions to control operation of the bi-stable relay based on the state.

The present disclosure relates generally to the field of batteries and battery modules that use relays to selectively couple the battery to a bus.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
A vehicle that uses one or more battery systems for providing all or a portion of the motive power for the vehicle can be referred to as an xEV, where the term "xEV" is defined herein to include all of the following vehicles, or any variations or combinations thereof, that use electric power for all or a portion of their vehicular motive force. For example, xEVs include electric vehicles (EVs) that utilize electric power for all motive force. As will be appreciated by those skilled in the art, hybrid electric vehicles (HEVs), also considered xEVs, combine an internal combustion engine propulsion system and a battery-powered electric propulsion system, such as 48 Volt (V) or 130V systems. The term HEV may include any variation of a hybrid electric vehicle. For example, full hybrid systems (FHEVs) may provide motive and other electrical power to the vehicle using one or more electric motors, using only an internal combustion engine, or using both. In contrast, mild hybrid systems (MHEVs) disable the internal combustion engine when the vehicle is idling and utilize a battery system to continue powering the air conditioning unit, radio, or other electronics, as well as to restart the engine when propulsion is desired. The mild hybrid system may also apply some level of power assist, during acceleration for example, to supplement the internal combustion engine. Mild hybrids are typically 96V to 130V and recover braking energy through a belt or crank integrated starter generator. Further, a micro-hybrid electric vehicle (mHEV) also uses a "Stop-Start" system similar to the mild hybrids, but the micro-hybrid systems of a mHEV may or may not supply power assist to the internal combustion engine and operate at a voltage below 60V. For the purposes of the present discussion, it should be noted that mHEVs typically do not technically use electric power provided directly to the crankshaft or transmission for any portion of the motive force of the vehicle, but an mHEV may still be considered as an xEV since it does use electric power to supplement a vehicle's power needs when the vehicle is idling with internal combustion engine disabled and recovers braking energy through an integrated starter generator. In addition, a plug-in electric vehicle (PEV) is any vehicle that can be charged from an external source of electricity, such as wall sockets, and the energy stored in the rechargeable battery packs drives or contributes to drive the wheels. wheels. PEVs are a subcategory of EVs that include all-electric or battery electric vehicles (BEVs), plug-in hybrid electric vehicles (PHEVs), and electric vehicle conversions of hybrid electric vehicles and conventional internal combustion engine vehicles.
xEVs as described above may provide a number of advantages as compared to more traditional gas-powered vehicles using only internal combustion engines and traditional electrical systems, which are typically 12V systems powered by a lead acid battery. For example, xEVs may produce fewer undesirable emission products and may exhibit greater fuel efficiency as compared to traditional internal combustion vehicles and, in some cases, such xEVs may eliminate the use of gasoline entirely, as is the case of certain types of EVs or PEVs.
In addition to use in vehicles (e.g., cars, boats, trucks, motorcycles, airplanes), advances in battery technology and rechargeable batteries are more frequently being used it what may be referred to as stationary battery applications. Applications for stationary batteries, which are often used in backup or supplemental power generation, are becoming more widespread with improvements in rechargeable aspects of batteries and with the lowering of prices for such technology. For example, stationary batteries may be utilized for industrial and/or household applications. Such applications may include DC power plants, substations, back-up power generators, transmission distribution, solar power collection, and grid supply.
As technology continues to evolve, there is a need to provide power systems with more efficiency for such vehicles, stationary battery applications or systems, and other battery systems. Power systems may be used in a variety of applications to provide power to a load. For example, battery cells may be stored in a container and coupled to the load. The battery cells are charged to provide a power to the load. The less energy used in providing power to the load, the more efficient the power system.


A device for sealing a clearance between a ceiling frame and a filter frame placed on the ceiling frame. The ceiling frame includes closed tubes and has an upper wall formed with holes for holding the interior of the ceiling frame in communication with a groove formed in the bottom face of the filter frame. The interior of the ceiling frame is given a negative pressure by suction.

The present invention relates to a filter sealing device for sealing a clearance between a ceiling frame and filter frames placed thereon for use in clean rooms, for example, of semiconductor manufacturing plants, pharmaceutical plants and hospitals, biologically clean rooms, etc., and more particularly to a sealing device suitable for superhigh efficiency filters such as HEPA filters and ULPA filters.
The ceiling portion of such a clean room has a ceiling frame which comprises horizontal beams arranged lengthwise and crosswise and defining openings therebetween, and a plurality of filters arragned on the ceiling frame for the respective openings. Super-high efficiency filters such as those mentioned above are often used for clean rooms of higher grade.
While the filter is fixed to the ceiling frame by a filter frame placed thereon, it is necessary to prevent leakage of air through a clearance between the frames. Especially in the case of superhigh efficiency filters which offer great resistance and produce a great pressure difference, a great air leak will occur unless the clearance is sealed off reliably.
To preclude such leakage of air from between the ceiling frame and the filter, a sealing material is conventionally provided between the upper face of the ceiling frame and the lower edge of the filter frame as disclosed, for example, in Examined Japanese Utility Model Publication No. 31130/1990.
The sealing material is applied in situ, therefore requires labor and is likely to permit an air leak if applied improperly to result in impaired filtration. Moreover, the sealing material is likely to release a solvent gas and harden during use, failing to serve the desired sealing function.
Further when there arises a need to remove the filter from the ceiling frame during use for cleaning or replacement, the sealing material must be cut off by a troublesome procedure, and the cumbersome work need to be repeated again for the installation of filter.
Another problem is also encountered in that air is liable to leak from the beam joints of the ceiling frame.


A tactile sensation providing apparatus includes a touch sensor, a tactile sensation provider that provides a tactile sensation on a touch surface of the touch sensor, a proximity sensor that detects the approach of an object to the touch sensor, and a controller that starts driving of the tactile sensation provider in accordance with detection by the proximity sensor.

Devices that provide a tactile sensation when an object, such as a finger or a stylus, touches a touch sensor are known. Devices that accept input by an object approaching a touch sensor to within a certain distance without the object touching the touch sensor are also known, as in patent literature (PTL) 1, for example.

Tactile sensation providing apparatus and tactile sensation providing method


A hydrogen generating material of the present invention includes at least one metal material selected from aluminum and aluminum alloy. The metal material has a surface film that includes a metal phase containing aluminum in the metallic state and an inactive phase containing an oxide or hydroxide of aluminum. A method for producing the hydrogen generating material of the present invention includes pulverizing aluminum or aluminum alloy in a liquid containing water and an organic solvent. A method for producing hydrogen of the present invention includes producing hydrogen by a reaction between the hydrogen generating material of the present invention and water.

With the recent widespread use of cordless equipment such as a personal computer or portable telephone, secondary batteries used as a power source of cordless equipment are increasingly required to have a smaller size and higher capacity. At present, a lithium ion secondary battery that can achieve a small size, light weight, and high energy density is being put to practical use and growing in demand as a portable power source. However, depending on the type of cordless equipment to be used, the lithium ion secondary battery is not yet reliable enough to ensure a continuous available time.
Under these circumstances, a polymer electrolyte fuel cell has been studied as an example of a battery that may meet the above requirements. The polymer electrolyte fuel cell uses a polymer electrolyte membrane as an electrolyte, oxygen in the air as a positive active material, and a fuel (hydrogen, methanol, etc.) as a negative active material, and has attracted considerable attention because it is a battery that can be expected to have a higher energy density than a lithium ion secondary battery. Fuel cells can be used continuously as long as a fuel and oxygen are supplied. Although there are several candidates for fuels used for the fuel cells, the individual fuels have various problems, and a final decision has not been made yet.
For example, when a fuel cell uses hydrogen as a fuel, a method for supplying hydrogen stored in a high-pressure tank or hydrogen-storing alloy tank is employed to some extent. However, a fuel cell using such a tank is not suitable for a portable power source, since both the volume and the weight of the fuel cell are increased, and the energy density is reduced.
When a fuel cell uses a hydrocarbon fuel, another method for extracting hydrogen by reforming the hydrocarbon fuel may be employed. However, a fuel cell using hydrocarbon fuel requires a reformer and thus poses problems such as supply of heat to the reformer and thermal insulation. Therefore, this fuel cell is not suitable for a portable power source either.
Moreover, a direct methanol fuel cell, in which methanol is used as a fuel and reacts directly at the electrode, is miniaturized easily and expected to be a future portable power source. However, a direct methanol fuel cell causes a reduction in both voltage and energy density due to a crossover phenomenon in which methanol at the negative electrode passes through the solid electrolyte and reaches the positive electrode.
On the other hand, it is also known that hydrogen is generated by a chemical reaction at a low temperature of 100° C. or less and used as a fuel of a fuel cell (Patent Documents 1 to 5). These methods use a metal that reacts with water to produce hydrogen, such as aluminum, magnesium, silicon or zinc, as a hydrogen source.
Patent Document 1: U.S. Pat. No. 6,506,360
Patent Document 2: JP 2566248 B2
Patent Document 3: JP 2004-231466 A
Patent Document 4: JP 2001-31401 A
Patent Document 5: U.S. Pat. No. 6,582,676
Patent Documents 1 to 3 disclose techniques allowing aluminum to react with an alkali or acid. Although these techniques easily can produce hydrogen chemically, the equivalent weight of the alkali or acid corresponding to aluminum needs to be added, which in turn reduces the energy density because a large proportion of the material is other than the hydrogen source. Moreover, the reaction product (oxide or hydroxide) forms a film on the surface of the aluminum, so that water cannot come into contact with the aluminum inside the film. This may lead to a problem that the oxidation reaction stops while only at the surface of the aluminum.
Patent Document 4 is intended to avoid the above problem by removing the film mechanically from the metal surface. However, the device should have mechanical equipment for removal of the film and becomes larger.
In Patent Document 5, alumina is added as a catalyst to suppress the formation of a hydroxide film, and hydrogen is generated at low temperatures. However, it is not possible to generate hydrogen by using only a metal such as aluminum. Moreover, the addition of the catalyst can reduce the content of the metal (aluminum) that serves as a hydrogen source, thus reducing the amount of hydrogen generated.

Hydrogen generating material and method for producing the same, and method for producing hydrogen