For medicine, sports and cosmonautics, a method of biomechanotherapy massage and therapeutic action on a human body performed both by heat and light waves and by mechanical waves which are sequential and parallel combinations of longitudinal and transverse modulated solitary waves of length from 0.005 to 0.1 m propagating along the body with speed from 0.01 to 12 m/s, where the solitary waves are formed on the body due to an impulsive action of separate thermovibratodes interconnected with a controlled link and acting on a human body with a temperature from 0 to 90° C., a specific pressure from 0.5·105 to 4·105 Pa and a shear thrust from 0.1 to 100 N. The proposed method of biomechanotherapy allows to increase efficiency of the therapeutic and sports massage and to improve results of an integral treatment of various diseases. Wave biomechanotherapy increases 1.5–2 times the peripheral blood flow facilitating the work of the cardiovascular system, improving the rheological properties of blood, blood supply to all organs and the functional condition of these parameters. Wave biomechanotherapy actively stimulates the metabolism, accelerates rehabilitation processes in organs and tissues and increases drainage of decay products from a body in a natural way.

1. Field of the Invention
This invention relates to physical culture and sports, medicine, cosmonautics and can be used both for health-improving and therapeutic massage as well as for treatment of various diseases.
2. Discussion of Prior Art
U.S. Pat. No. 4,231,355 teaches a known method of pneumatic massage using shells and a harmonic progressing wave. This method provides an action of only a transverse mechanical wave propagating along a straight line, which does not agree with most of massage techniques performed by way of a curved path conditioned by, for example, blood and lymph flow of the massaged body part.
U.S.S.R. Inventor's Certificate 1795889 teaches a therapeutic massage using a progressing wave. This device produces only transverse mechanical waves propagating along a straight line on a limited number of anatomico-topographic body parts. Absence of heat waves, light waves, rarefaction waves, impulse displacement of pseudoboiling layer modules does not allow to effectively influence the lymph and blood flow. The known device cannot produce a modulated wave which is an important feature of a solitary wave due to use of modules of drivers to rotate discs. Starting, operation of the driver with the purpose to create chaotic motion of balls and shutdown of engines requires a significant amount of time, i.e. the process of a boiling layer production is inertial. In the "running wave" mode modules switch off for 5–10 sec, which corresponds to the wave propagation speed commensurable with a lymph flow velocity.
PCT International Publication WO/67693 teaches a method of massage that realizes only a mechanical progressing wave along the body in a lying position. To produce waves, four vibrators are used which are not positioned on one biomechanical unit, i.e. the wave length is significantly more than 0.1 m. Heat and light waves are absent. Mechanical impulse modulation parameters are the same for all vibration sources. Absence of a controlled connection between the vibratodes and large wave length do not allow a circular massage ensuring a body part clasping with force both stimulating blood flow and completely stopping it for a short period of time. Carrier frequency with this method does not correspond to the biomechanical resonance (5–20 Hz) and consequently cannot influence directly the blood flow in muscles.
FRG Patent Reference 39 05 517 C1 teaches a dampening, heating, vibrating, electrifying and freshening massage ball roller that does not ensure combinative effect of all acting factors, i.e. sequence of effects of heat, vibration and lighting with various time intervals. The known device uses a vibration drive that like all electric drives has a long response time and on-off time ratio equals to 2. Thus there is no possibility to program each mechanical impulse and to perform modulation of mechanical impulses in body reception mode. The device does not allow performing a circular massage, to synchronize phases of mechanical, heat and light impulses.
U.S.S.R. Inventor's Certificate 604211 teaches a method of wave therapy using cylindrical shells placed parallel to each other and pressed to a human body. Wave-like displacement of surface due to alternate shells filling and blowing-off provides for massage at a plane harmonic progressing wave synchronized with a pulse wave speed in extremities.
Lack of shear thrusts in this massage method precludes a stroking technique required to regulate musculocutaneous tonus in the process of treatment. The wave-like displacement with action modes are the same for all body parts and produces a harmonic progressing wave in relation to which a fast body adaptation takes place decreasing activity of the neuromuscular system, aimed at body rehabilitation while mechanical impulses are acting. This leads to a short duration of the treatment procedure (15–30 min) and the only controlled parameter changing for which it is possible to avoid adaptation is the wave speed. Thus there is no possibility to control treatment mode in a wide range. Another drawback of this known method is the impossibility to act with a wave on vibroreceptors and wave biomechanical processes in myofibrils. Also, this known method does not realize vacuumization waves, i.e. the waves with pressure less than 1.01·105 Pa.


A sense amplifier has a charge sharing compensator to eliminate wake-up delays in an output signal. The charge sharing compensator comprises a capacitor or a charge storing means to compensate for charges in a charge sharing path that has two different voltage potentials. The compensator also has a transistor for selecting a signal path to transfer charges from the capacitor, eliminating charge sharing in the bit line path of the sense amplifier. Another aspect of the present invention is a method for resolving charge sharing problems that comprises steps of choosing a proper value for a compensating capacitor, choosing a control signal for a charge sharing compensation means, and clamping down an input terminal of the sense amplifier.

Sense amplifiers are one of the most critical circuits in a periphery of memory devices. They are used to sense data information from an array of cells in a memory device. The sense amplifier's performance strongly affects both memory access time and overall function of the memory device. As with other integrated circuits, memory devices are required to become increasingly faster. Sense amplifiers are also required to become commensurately faster.
The sense amplifier detects a high or a low data value, differing by a small voltage, presents the value found in a proper level for a correct logic level representation outside the memory, and is quickly ready to repeat this read process for the next memory location. To do this, a sense amplifier must be able to detect a difference between a high and a low level in a storage element that may be several hundred millivolts. The sense amplifier must correctly detect small voltage differences without excessive depletion or injection of charge in the storage element being sensed so that the correct level is maintained in storage and successive read operations are started rapidly. The sense amplifier must be able to provide a large enough voltage level representation to the consuming logic for a proper result. The sense amplifier must supply this result with a small propagation delay to maintain quick memory access and high throughput. To provide high throughput, the memory device must be able to cycle quickly through these requirements each time a new memory location is read.
An input node of a sense amplifier is typically connected directly to a bit-line of a memory array, which may contain many memory cells. A total capacitance loading on the bit-line is very large. Such large capacitances result in slow input slew rates and increased signal propagation delay. Various circuit techniques have been used to reduce the signal swing on the bit-lines to achieve high-speed operation. These techniques commonly require a large DC bias current through the amplifying stages and thus are not suitable for applications requiring low stand-by DC current, which is the case in products such as battery operated consumer electronics applications. To reduce the overall energy consumed by a memory device, sense amplifiers can be conditionally turned on briefly when a content of a memory bit needs to be read out, remaining turned off otherwise, consuming zero DC current. This defines a low current operation mode, commonly referred to as Low Power Mode. Different design techniques, such as edge detection circuits, can be used to determine when to turn on the sense amplifiers. Usually, when the sense amplifier is turned off, the input node and the output node are coupled together to form a latch. This preserves the information from the last memory access. The formation of the latch places the input node at full CMOS levels. If the input node of the sense amplifier is directly coupled to the memory bit-line, which has heavy capacitive loading, the memory bit-line will also be forced to a full CMOS level. Upon subsequent memory accesses, if the content of a memory cell presents a different logic value than the previously accessed memory bit, a large voltage swing is seen on the bit-line before the sense amplifier can detect a correct logic level. This voltage swing is much larger than the voltage swing on the bit-line during normal sense amplifier operation. This larger voltage swing results in much larger propagation delays.
A prior art circuit technique isolates the heavily loaded bit-line from the sense amplifier input node during latching in Low Power Mode and only latches the sense amplifier input node to a CMOS level. This technique reduces the voltage swing seen on the bit-line when the sense amplifier wakes up. It can significantly reduce the Low Power Mode propagation delay. However, a charge-sharing path exists between the sense amplifier input node and bit-line in the prior art technique. Under certain conditions, the charge sharing path pumps up the bit-line voltage to a level significantly higher than its normal mode bias level and introduces significantly larger signal swing on the bit-line when the sense amplifier wakes up. As a consequence of a larger signal swing, the Low Power Mode signal propagation delay increases significantly. This delay decreases the effectiveness of the bit-line isolation technique.
FIGS. 1–4 illustrate an overview of a prior art sense amplifier having delay problems in the logic low signals.
With respect to FIG. 1, an exemplary embodiment of a schematic diagram of a sense amplifier 100, representative of the prior art, is shown. A memory cell 151 consists of a storage transistor 160 and a select transistor 155 connected in series. A memory cell array 165 is composed of many memory cells 151 with each select transistor 155 controlled by a separate word line 152. The memory cells 151 are connected in parallel to a bit-line 170. The bit-line 170 is connected to a sense amplifier input, sa_in 140, through a first NMOS transistor 150. The first NMOS transistor 150 is configured with a source connection to the bit-line 170, a drain connection to the sense amplifier input sa_in 140, and a gate connection to a signal Pd_lat# 115. The sense amplifier input, sa_in 140, connects to a first of four inverters 130 connected in series with the fourth inverter having an output connection to the output terminal sa_out 135. The output of the first inverter of four inverters 130 is connected to an input gate of a second NMOS transistor 125 with a source connection to sa_in 140 and a drain connection to the drain of a pull-up PMOS transistor 112. The second NMOS transistor provides feedback to the input of the sense amplifier 100 for level sensing. The source of the pull-up PMOS transistor 112 is connected to Vcc. The gate of the pull-up PMOS transistor 112 is connected to an input Pd 110 An output of the fourth inverter 130 is connected to the input of a transmission gate 138. An output of the transmission gate 138 forms a latching path when connected to sa_in 140. Pd_lat# 115 and a signal Pd_lat 120 control the latching path.
With reference to FIG. 2, a detailed schematic diagram of a sense amplifier 200 is illustrated. The sense amplifier 200 comprises a biasing circuit 202, a first inverter 220, a second inverter 240, a third inverter 260, a feedback latching path 280, and a bit-line path 290.
The biasing circuit 202 sets the bias voltage level on sa_in 140 in high power mode for the sense amplifier 200 and comprises a PMOS pull-up transistor 204 coupled in series to an NMOS transistor 206. A first input terminal (Pd) 210 is coupled to the gate of the PMOS pull-up transistor 204. The source of the PMOS pull-up transistor 204 is coupled to a power supply 212. The gate of the NMOS transistor 206 is coupled to an output terminal of the first inverter 220 in form of a feedback.
The first inverter 220 is, for example, a typical CMOS inverter with two pull-up PMOS transistors and a pull-down NMOS transistor. An input of the first inverter 220 is coupled to the bit-line path 290. An output of the first inverter 220 is coupled to an input of the second inverter 240 to form a buffer. As mentioned earlier, the output of the first inverter 220 is also coupled to an input (or the gate of the NMOS transistor 206) of the biasing circuit 202 to form a feedback therewith.
The second inverter 240 and the third inverter 260 are, for example, a typical CMOS inverter with a PMOS pull-up and an NMOS pull-down transistor. The output of the fourth inverter 265 forms an output terminal 286 (sa_out) of the sense amplifier 200.
The feedback latching path 280 is, for example, a transmission gate forming a latching path which is well-known to a person of ordinary skill in the art with a PMOS transistor and an NMOS transistor coupled together in parallel. Their sources are coupled together and to the output terminal 286, their drains are coupled together and to the bit-line path 290.
The bit-line path 290 has three input terminals, an NMOS switch 298, and a parasitic capacitor 292 associated with sa_in 295. The three input terminals are a second input terminal 294 (Pd_lat#), a third input terminal 296 (bitln), and sa_in 295. The drain of the NMOS switch 298 is coupled to the third input terminal 296 (bitln). The source of the NMOS switch 298 is coupled to the input terminal of the first inverter 220, to the drain of the feedback latching path 280, and to the source of the NMOS pull-down transistor 206 of the biasing circuit 202 to form the input sa_in 295 for the sense amplifier 200.
With further reference to FIG. 2, the modes of the sense amplifier 200 are determined by the following three input signals: the first input terminal (Pd) 210, the second input signal (Pd_lat#) 294, and the fourth input signal (Pd_lat) 299. These are control signals. In a high power mode, the first input signal (Pd) 210 stays LOW, the second input signal (Pd_lat#) 294 stays HIGH, and the fourth input signal (Pd_lat) 299 stays LOW. As a result, the PMOS pull-up transistor 204 is ON, raising the input sa_in 295 of the sense amplifier 200 to a bias voltage level. When the second input terminal 294 (Pd_lat#) is HIGH and the fourth input signal 299 is LOW, the feedback latching path 280 is OFF because its PMOS transistor and NMOS transistor are both OFF. Thus, the feedback latching path 280 isolates the output terminal 286 (sa_out) from the third input terminal 296 (bitln) of the sense amplifier 200.
In the high power mode, the voltage of the third input terminal 296 (bitln) varies from a logic LOW bias voltage (Vbias—Lo) to a logic HIGH bias voltage (Vbias—HIGH) to turn the inverters 220, 240, 260, and 265 ON or OFF respectively. Typically, the voltage swing between Vbias—LOW and Vbias—HIGH is about 200 mV. Under this condition, the third input terminal 296 (bitln) causes the NMOS switch 298 to bias at the triode region. As such, the NMOS switch 298 acts like a resistor. These bias levels are close to the trip point of the first inverter 220. Thus, in the high power mode, the sense amplifier 200 draws a considerable amount of current. The overall standby current is very high.
In the low power mode, the first input terminal 210 (Pd) and the fourth input terminal 299 (Pd_lat) normally stay HIGH and the second input terminal 294 (Pd_lat#) stays LOW. As a result, the biasing path 202 is OFF, isolating the third input terminal 296 (bitln) from the input sa_in 295 of the sense amplifier 200. When the biasing path 202 is disabled and the feed back latching path 280 is enabled, a latch is formed. Because each node is either at voltage supply Vcc or ground, the standby current in the low power mode is very low.
FIG. 3 shows a timing diagram of a plurality of control signals 300 operating the prior art sense amplifier of FIG. 1. Commencing in a latching phase 310, the signal Pd 110 is high and the conductive path to Vcc of pull-up PMOS transistor 112 is disabled. The signal Pd_lat 120 is high and Pd_lat# 115 is low. The signals Pd_lat 120 and Pd_lat# 115 in this condition will enable the latching path of the transmission gate 138, which connects sa_out 135 to sa_in 140, to make a latching condition. The low signal on Pd_lat# 115 applied to the gate of the first NMOS transistor 150, will isolate the memory cell array 165 from sa_in 140. In this latching phase 310, the latching path is enabled and the sense amplifier is disabled. This set of conditions defines the Low Power Mode.
When a memory location is to be read, a sensing phase 320 is entered. The sensing phase 320 is initiated by the word line 152 going to a high level for a memory cell 151 being selected, causing a sensing transition 340 to the sensing phase 320. The sensing transition 340 is defined by the input Pd 110 transitioning from high to low, the signal Pd_lat# 115 changing from low to high, and the signal Pd_lat 120 changing from high to low. Pd_lat 120 at a low level and Pd_lat# 115 at a high level will turn off the latching path from sa_out 135 to sa_in 140. Pd 110 being low will enable the pull-up PMOS transistor 112 to conduct and provide a bias to the sense amplifier input sa_in 140. A high level on Pd_lat# 115 is applied to the gate of the first NMOS transistor 150, making a coupling path from the memory cell array 165 to sa_in 140. The memory cell 151 selected is connected to the bit-line 170 through the activation of the select transistor 155. The contents of the selected memory cell are available to be coupled to the sense amplifier input sa_in 140 through the first NMOS transistor 150. In this phase, the latching path is disabled and the sense amplifier is enabled.
When the sensing phase 320 is concluded, a latching transition 345 is initiated by control logic (not shown). This transition is marked by the signal Pd 110 changing from low to high, the signal Pd_lat# 115 changing from high to low, and the signal Pd_lat 120 changing from low to high. In this phase the sense amplifier 100 is disabled and the latching path is active.
FIG. 3 also illustrates the timing diagram of these prior art control signals during a wake-up event 302. The sense amplifier 200 awakens by related signals that cause any separate word line 152 (FIG. 1) to change state. The change in state of these signals produces short pulses in the control signals. Graph 302 represents either input signals or feedback signals that change state from HIGH to LOW or vice versa. This causes the signal at the first input terminal 210 (Pd) to go LOW, creating a pulse 304. It also causes the signal at the second input terminal 294 (Pd_lat#) to become HIGH, representing pulse 306. Finally, the fourth signal 299 (Pd_lat) responds by having a pulse 308.
These pulses 304, 306, and 308 are about 20 ns in duration. During the short pulses, the first input terminal 210 (Pd) and the fourth input terminal 299 (Pd_lat) go LOW, and the fourth input signal 299 (Pd_lat#) goes HIGH. During these pulses, the sense amplifier 200 is enabled and the feedback latching path 280 is OFF. The sense amplifier 200 goes into the high power mode. That is, the sense amplifier 200 evaluates the possible new voltage levels created by the changes on input or feedback signals and responds to these changes. Once the pulse is over, the updated information is latched and stored until a next input or feedback transition.
During an initial sense phase 320, for a memory bit storing a logic high, a Vbias—HIGH voltage is present on the bit-line. After the sense amplifier switches to latch phase 310 after the wake up window expires, the bit-line node is isolated from the sa_in node. If we neglect the leakage current from the bit-line to ground, the bit-line holds the Vbias—HIGH voltage due to its electrical capacitance. The sa_in node is coupled to sa_out node because the formation of a latching connection during the latch phase 310. During the latch phase 310 a logic one, at a full CMOS level, is present at sa_in. In this case, a Vcc voltage level is present on sa_in. The second time the sense amplifier switches from latch phase 310 to sense phase 320 transistor 298 in FIG. 2 turns on since Pd_latch# goes to high during the sense phase 320. This couples sa_in and the bit-line together. At the onset of coupling, sa_in has a Vcc level stored on its associated parasitic capacitor 292. The bit-line node has a Vbias—HIGH level stored in its associated capacitance. Since Vcc usually is much higher than Vbias—HIGH, the charge in each capacitor redistributes to reach an equilibrium voltage. This process will conclude when there is no potential difference between these two nodes. The total amount of charge remains the same under the law of charge conservation. The final equilibrium voltage on the bit-line during the second sense high is higher than the original Vbias—HIGH voltage. In the subsequent latch phase 310, the higher voltage level is preserved on the bit-line, while sa_in is coupled back to Vcc due to the latching action. With a third sensing cycle, charge redistribution occurs again if the new bit-line voltage is lower than Vcc−VT; where VT is the threshold voltage of transistor 298. As a result, the bit-line goes to a level even higher voltage than the second time.
With regard to FIG. 4, continuing sensing phase events, pump the bit-line voltage even higher. If there are enough sensing cycles, the bit-line voltage level will eventually reach a saturated level at Vcc−VT. At this stage, even thought there is still a potential difference between sa_in and the bit-line node, the transistor 298 cannot be turned on to establish a conducting path to redistribute the charge. Because the third input terminal 296 (bitln) is pumped to a voltage level higher than a normal bit-line high bias voltage level, the following sensing logic low speed gets slowed down drastically. Normally, the voltage of bit-line path 290 only travels from about 100 mV to 200 mV to sense a logic LOW. Now it has to travel more than 2 volts to finally reach the voltage level for a sense amp to recognize a logic LOW. Because of the heavy loading on the bit-line path 290, it takes significantly more time to sense a logic LOW. This type of delay causes both functional failure and the failure to meet TPD specification.
What is needed is a circuit technique that reduces the effects of charge pumping events and achieves high-speed operation in the Low Power Mode.

Sense amplifier for reduced sense delay in low power mode


Disclosed herein is a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon. The mounting structure of a circuit board having a multi-layered ceramic capacitor thereon, in which a dielectric layer on which inner electrodes are disposed is stacked and external electrode terminals connecting the inner electrodes in parallel are disposed on both ends thereof, wherein the inner electrodes of the multi-layered ceramic capacitor and the circuit board are disposed so as to be a horizontal direction to connect the external electrode terminals with a land on the circuit board by a conductive material and a ratio of a bonding area ASOLEDER of the conductive material to the area AMLCC of the external electrode terminals AMLCC is set to be less than 1.4, thereby remarkably reducing the vibration noise.

1. Technical Field
The present invention relates to a mounting structure and a mounting method of a circuit board having a multi-layered ceramic capacitor thereon, and more particular, to a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon capable of remarkably reducing vibration noise of the multi-layered ceramic capacitor by forming on a surface of the circuit board a land having the multi-layered ceramic capacitor mounted thereon and connecting the land with external electrode terminals of the multi-layered ceramic capacitor by a conductive material while setting a ration of a bonding area of the conductive material to be less than 1.4 as compared with an area of the external electrode terminal of the multi-layered ceramic capacitor.
2. Description of the Related Art
Generally, a multi-layered ceramic capacitor (MLCC) is a chip type capacitor that is mounted on a printed circuit board of various electronic products such as mobile communication terminals, notebooks, computers, personal digital assistants (PDAs), or the like, and plays an important role of charging or discharging electricity and has various sizes and stacked shapes according to usage and capacitance.
In addition, the multi-layered ceramic capacitor has a structure in which inner electrodes having different polarities are alternately stacked between a plurality of dielectric layers.
The multi-layered ceramic capacitor has been prevalently used as parts of various electronic devices due to advantages such as miniaturization, large capacitance, and easiness of mounting.
As a ceramic material forming a laminate of the multi-layered ceramic capacitor, a ferroelectric material such as barium titanate having a relatively higher dielectric constant is generally used. Since the ferroelectric material has piezoelectricity and electrostriction, when electric field is applied to the ferroelectric material, stress and mechanical deformation are shown as vibrations, which are transferred from the electrode terminal of the multi-layered ceramic capacitor to the board side.
That is, when AC voltage is applied to the multi-layered ceramic capacitor, stresses Fx, Fy, and Fz are applied to a main body of the multi-layered ceramic capacitor device in each direction of X, Y, and Z, which results in generating vibrations. The vibrations are transferred from the electrode terminal to the entire board which is an acoustic radiation surface, thereby generating noise, that is, vibrating sound.
The vibrating sound approximately corresponds to vibrating sound of an audible frequency (20 to 20,000 Hz) which may include a compass that gives a person an unpleasant feeling. Therefore, a need exists for a solution to the above problem.
Recently, in order to solve the problems due to the above-mentioned vibrating sound, various technologies, such as a technology of preventing vibrations due to an elastic deformation in the external terminal of the multi-layered ceramic capacitor, a technology of introducing separate parts for reducing generation of noise by suppressing propagation of vibrations generated due to piezoelectricity and electrostriction, a technology of forming board holes around the multi-layered ceramic capacitor mounted so as to suppress the vibrations of the board, or the like, has been disclosed, which require separate processes and are insufficient in a vibration prevention effect compared with the complexity of processes.
Meanwhile, as the multi-layered ceramic capacitor, there is a multi-layered ceramic capacitor having the substantially same width and thickness. In the case of the multi-layered ceramic capacitor having the substantially same width and thickness, when the multi-layered ceramic capacitor is mounted on the printed circuit board since directivity of inner conductors of the multi-layered ceramic capacitor cannot be recognized from the outside of the multi-layered ceramic capacitor, the multi-layered ceramic capacitors are mounted on the printed circuit board, regardless of the directivity of the inner conductors.
The differences in characteristics of the multi-layered ceramic capacitor are generated according to the direction of the inner conductors of the multi-layered ceramic capacitor mounted on the printed circuit board. In particular, the large difference in vibration noise characteristics due to the piezoelectricity of the multi-layered ceramic capacitor is shown.
In particular, it is found from the recent experiment results that the mounting direction of the multi-layered ceramic capacitor and the amount of a conductive material connecting the external electrode terminals of the multi-layered ceramic capacitor with the land are correlated with each other, which has a large effect on the vibration noise characteristics.
In particular, a need exists for a mounting structure and a mounting method capable of mounting the inner electrode surface of the multi-layered ceramic capacitor so as to be horizontal with the surface of the printed circuit board and remarkably reducing the vibration noises of the multi-layered ceramic capacitor by the ratio of the bonding area of the conductive material connecting the external electrode terminals of the multi-layered ceramic capacitor with the land to the external electrode terminal.

Mounting structure of circuit board having multi-layered ceramic capacitor thereon


A method for automatic construction of 2D statistical shape models for the lung regions in chest radiographic images comprising: providing a radiographic image of the chest region of an individual; by performing a manual contour tracing, extracting the lung region shape instances from the chest radiographic image; by using a shape alignment algorithm, aligning all shape instances as closely as possible to a pre-defined template shape; and generating a statistical model shape of the lung regions by principle component analysis using the aligned shape instances.

The use of shape as an anatomical object property is a rapidly increasing portion of research in the field of medical image analysis. Shape representations and shape models have been used in connection with segmentation of medical images, diagnosis, and motion analysis. Among different types of shape models, Active Shape Models (ASMs) have been frequently applied and proven a powerful tool for characterizing objects and segmenting medical images. In order to construct such models, sets of labeled training images are required. The labels in the training sets consist of landmark points defining the correspondences between similar structures in each image across the set. Manual definition of landmarks on 2D shapes has proven to be both time-consuming and error prone. To reduce the burden, semi-automatic systems have been developed. In these systems, a model is built from the current set of examples, and used to search the next image. The user can edit the result where necessary, then add the example to the training set. Though this can considerably reduce the time and effort required, labeling large sets of examples is still labor intensive.
Because of the importance of landmark labeling, a few attempts have been made to automate the shape alignment/average process. For example, Lorenz and Krahnstover automatically locate candidates for landmarks via a metric for points of high curvature, Lorenz C., Krahnstove N. Generation of point-based 3D statistical shape models for anatomical objects. CVIU, vol. 77 no. 2, February 2000, pp. 175-191. Davatzikos et al. used curvature registration on contours produced by an active contour approach, (C. Davatzikos, M. Vaillant, S. M. Resnich, J. L. Prince, S. Letovsky, and R. N. Bryan, A Computerized Approach for Morphological Analysis of the Corpus Callosum, J. Computer Assisted Tomography vol. 20, 1996, pp. 88-97). Duncan et al. (J. Duncan, R. L. Owen, L. H. Staib, and F. Anandan, Measurement of non-rigid motion using contour shape descriptors, in IEEE Conference on Computer Vision and Pattern Recognition, 1991, pp. 318-324). And Kambhamettu et al, (C. Kambhamettu and D. B. Goldgof, Point correspondence recovery in non-rigid motion, IEEE Conference on Computer Vision and Pattern Recognition, 1992, pp. 545-561), propose methods of correspondence based on the minimization of a cost function that involves the difference in the curvature of two boundaries. However, as pointed out by several studies, curvature is a rigid invariant of shape and its applicability is limited in case of nonlinear shape distortions. In addition, it is hard to find sufficient high curvature points on lung contours.
Hill et al. employed a sparse polygonal approximation to one of two boundaries which is transformed onto the other boundary via an optimization scheme, (A. Hill, C. J. Taylor, and A. D. Brett, A Framework for Automatic Landmark Identification Using a New Method of Nonrigid Correspondence, IEEE Trans. Pattern Analysis and Machine Intelligence, vol. 22, no. 3, 2000, pp. 241-251). The polygonal matching is based on an assumption that arc path-lengths between consecutive points are equal. This assumption may be violated in case of severe shape difference and is especially difficult to satisfy in polygonal approximation of lung shape contours.
As a result, the prior art does not fit the lung shape modeling very well, therefore there exists a need for a method for automatically constructing 2D statistical shape model of lung regions in chest radio graphs.

Method for automatic construction of 2D statistical shape model for the lung regions


A method and an apparatus for operating directly with the program code of a process for determining the gradients of process variables of interest with respect to process parameters. Each process will contain one or more process variable declarations wherein each process variable declaration defines a process variable. There will also be one or more process function assignments associated with each process variable, wherein each process function assignment assigns a value to the associated process variable. One or more gradient variables will be introduced into the process for each process variable of interest, wherein each gradient variable corresponds to and represents the partial derivative, or gradient, of the process variable of interest with respect to a parameter whose value affects the value of the process variable of interest. One or more gradient function assignments will then be inserted into the process for each occurrence of a process function assignment associated with a process variable of interest. Each gradient function assignment will correspond to one of the gradient variables corresponding to the process variable of interest and will assign a value to the gradient variable.

A process may be broadly defined as a set of operations performed on some input to provide a desired result. Examples of such would be a spreadsheet, a database management system, a financial prediction program, a communications network control system, or a design simulation, which operates on data representing financial information, communications requirements or information describing a system or device being simulated. Other examples include a process controlling an industrial or chemical process which accepts data representing operation of the industrial or chemical process to provide outputs controlling the process. The present most common implementation of such a process is as a program executed by a processing unit such as a central processing unit or a microprocessor, wherein program defines and controls the set of operations comprising the process.
Such program implemented processes accept input data in the form of input variables, also referred to as parameters, and perform a set of operations with the input parameters and variables generated internally to the process to determine the value of other variables which represent quantities of interest to a user of the process. It is often useful in such processes to be able to determine the rate and direction of change, or gradient, of variables of interest to the user of the process with respect to selected other variables of the process, such as input parameters which are controllable by the user. The information regarding the gradients of the variables of interest may then be used to vary the input parameters in a manner to drive the results generated by the process to a value or values selected as optimum.
The prior art has evolved a number of ways in which to control processes by controlling the input parameters to the process. One approach was "trial and error" wherein the user conducted a number of runs of the process with different values of input parameter to approximate the rate of change of the outputs with respect to the inputs. This approach is very time consuming and provides only approximations to the actual rate of change of outputs with respect to inputs, not an exact value. In addition, this approach is seldom applicable to control processes which operate in "real time", such as processes used to control industrial or chemical processes or, for example, the flight of an aircraft, as it is generally impossible to re-run the process under the same conditions and with the same input parameters.
Another approach is commonly referred to as "perturbation analysis" and generally requires the creation of a mathematical model of a gradient determination process and the running of a simulation of the mathematical model on a computer system to approximate the process. This approach is acknowledged as useful only in a very limited range of processes, such as simple processes simulating simple systems or devices, as the mathematical models quite rapidly become very complex as the complexity of the process increases. This approach requires the creation of a different mathematical model for each type of process to be simulated, and usually for each individual process to be simulated. In addition, this approach involves at least tow levels of abstraction from the actual process, the first in creating a mathematical model of the process, and a second in analyzing the mathematical model of the process to determine a mathematical model of the gradient determination process. The gradient determination process must then be implemented as a computer program. As a result, it is difficult to ensure that the results of the gradient determination process accurately or adequately represent the gradients of the actual process.
"Likelihood ratios" is yet another approach and is similar in most respects to perturbation analysis but applies to a different class of problems and uses sequences of uniform random numbers to drive the simulation.
Yet another approach is referred to as response surface methodology and is essentially a mathematically modelled version of the earlier "trial and error" approach. In response surface methodology the processes is executed a number of times with different input parameters, a greatly simplified mathematical model or expression is created to define a "surface" on which the results lie for each execution of the process, the extreme points on the surface are determined from the mathematical model of the surface. In addition to all of the disadvantages of the "trial and error" method, this approach has the disadvantages that it again does not reflect the operation of the process for all possible input parameters, so that there is substantial uncertainty as to whether the model derived actually represents the actual process, as well as further uncertainties arising from assumptions about the smoothness, or granularity of the surface, which is function of both the model and the number of reiterations of the process. Also, it is very difficult in this approach, as in all of the mathematical modelling approaches, to determine the amount and direction in which to vary the input parameters for successive reiterations of the process modelling when there are a large number of parameters.
Finally, there are at present certain applications programs, such as spreadsheets, which provide a facility for approximating the rate of change of a variable of interest with respect to an input parameter by using a very simplified algebraic model of the spreadsheet processes defined by the user to provide an "educated guess" version of the old "trial and error" method.
The present invention provides a solution to these and other problems of the prior art.

Apparatus and method for determining gradients of process variables


A method for promoting the passage of elementary particles at or through a potential barrier comprising providing a potential barrier having a geometrical shape for causing de Broglie interference between said elementary particles is disclosed. In another embodiment, the invention provides an elementary particle-emitting surface having a series of indents. The depth of the indents is chosen so that the probability wave of the elementary particle reflected from the bottom of the indent interferes destructively with the probability wave of the elementary particle reflected from the surface. This results in the increase of tunneling through the potential barrier. When the elementary particle is an electron, then electrons tunnel through the potential barrier, thereby leading to a reduction in the effective work function of the surface. In further embodiments, the invention provides vacuum diode devices, including a vacuum diode heat pump, a thermionic converter and a photoelectric converter, in which either or both of the electrodes in these devices utilize said elementary particle-emitting surface. In yet further embodiments, the invention provides devices in which the separation of the surfaces in such devices is controlled by piezo-electric positioning elements. A further embodiment provides a method for making an elementary particle-emitting surface having a series of indents.

The present invention is concerned with methods for promoting the transfer of elementary particles across a potential energy barrier.
In Edelson""s disclosure, filed Mar. 7, 1995, titled xe2x80x9cElectrostatic Heat Pump Device and Methodxe2x80x9d, Ser. No. 08/401,038, now abandoned, assigned to the same assignee as the present invention and incorporated herein by reference in its entirety, two porous electrodes were separated by a porous insulating material to form an electrostatic heat pump. In said device, evaporation and ionization of a working fluid in an electric field provided the heat pumping capacity. The use of electrons as the working fluid is disclosed in that application. In Edelson""s subsequent disclosure, filed Jul. 5, 1995, titled xe2x80x9cMethod and Apparatus for Vacuum Diode Heat Pumpxe2x80x9d, Ser. No. 08/498,199, now U.S Pat No. 6,089,316 assigned to the same assignee as the present invention, an improved device and method for the use of electrons as the working fluid in a heat pumping device is disclosed. In this invention, a vacuum diode is constructed using a low work function cathode.
In Edelson""s further subsequent disclosure, filed Dec. 15, 1995, titled xe2x80x9cMethod and Apparatus for Improved Vacuum Diode Heat Pumpxe2x80x9d, U.S. Pat. No. 5,722,242, assigned to the same assignee as the present invention and incorporated herein by reference in its entirety, the work function of the anode was specified as being lower than the work function of the cathode in order to optimize efficient operation.
In a yet further subsequent disclosure, filed Dec. 27, 1995, titled xe2x80x9cMethod and Apparatus for a Vacuum Diode Heat Pump With Thin Film Ablated Diamond Field Emissionxe2x80x9d, Ser. No. 08/580,282, now abandoned assigned to the same assignee as the present invention and incorporated herein by reference in its entirety, Cox and Edelson disclose an improvement to the Vacuum Diode Heat Pump, wherein a particular material and means of construction was disclosed to further improve upon previous methods and devices.
The Vacuum Diode at the heart of Edelson""s Vacuum Diode Heat Pump may also be used as a thermionic generator: the differences between the two devices being in the operation of the diode, the types and quantities of external energy applied to it, and the provisions made for drawing off, in the instance of the thermionic converter, an electrical current, and in the instance of the Vacuum Diode Heat Pump, energy in the form of heat.
In Cox""s disclosure, filed Mar. 6, 1996, titled xe2x80x9cMethod and Apparatus for a Vacuum Thermionic Converter with Thin Film Carbonaceous Field Emissionxe2x80x9d, Ser. No. 08/610,599, now abandoned, assigned to the same assignee as the present invention and incorporated herein by reference in its entirety, a Vacuum Diode is constructed in which the electrodes of the Vacuum Diode are coated with a thin film of diamond-like carbonaceous material. A Vacuum Thermionic Converter is optimized for the most efficient generation of electricity by utilizing a cathode and anode of very low work function. The relationship of the work functions of cathode and anode are shown to be optimized when the cathode work function is the minimum value required to maintain current density saturation at the desired temperature, while the anode""s work function is as low as possible, and in any case lower than the cathode""s work function. When this relationship is obtained, the efficiency of the original device is improved.
Many attempts have been made to find materials with low work function for use as cathodes for vacuum diodes and thermionic energy converters. Currently most research is in the field of cathodes for vacuum tubes. Research in thermionic converter technology is less intensive because of the difficulties of increasing thermionic emission of electrons from the flat surface, where field emission effect can not be applied. The practical importance of thermionic energy conversion is rapidly increasing due to increased needs for alternative energy sources. The most effective way of decreasing work function known today is the use of alkaline metal vapors, particularly cesium, and coating the emitter surface with oxide thin films. Use of Cs vapor is not without technical problems, and thin film coated cathodes generally show short lifetimes.
The thermotunnel converter is a means of converting heat into electricity which uses no moving parts. It has characteristics in common with both thermionic and thermoelectric converters. Electron transport occurs via quantum mechanical tunneling between electrodes at different temperatures. This is a quantum mechanical concept whereby an electron is found on the opposite side of a potential energy barrier. This is because a wave determines the probability of where a particle will be, and when that probability wave encounters an energy barrier most of the wave will be reflected back, but a small portion of it will xe2x80x98leakxe2x80x99 into the barrier. If the barrier is small enough, the wave that leaked through will continue on the other side of it. Even though the particle does not have enough energy to get over the barrier, there is still a small probability that it can xe2x80x98tunnelxe2x80x99 through it.
The thermotunneling converter concept was disclosed in U.S. Pat. No. 3,169,200 to Huffman. In a later paper entitled xe2x80x9cPreliminary Investigations of a Thermotunnel Converterxe2x80x9d, [23rd Intersociety Energy Conversion Engineering Conference vol. 1, pp. 573-579 (1988)] Huffman and Haq disclose chemically spaced graphite layers in which cesium is intercalated in highly orientated pyrolitic graphite to form a multiplicity of thermotunneling converters in electrical and thermal series. In addition they teach that the concept of thermotunneling converter was never accomplished because of the impossibility of fabricating devices having electrode spacings of less than 10 xcexcm. The current invention addresses this shortcoming by utilizing a piezo-electric, electrostrictive or magnetostrictive element to control the separation of the electrodes so that thermotunneling between them occurs.
A further shortcoming of the devices described by Huffman is thermal conduction between the layers of the converter, which greatly reduces the overall efficiency of these thermotunnelling converters.
In Edelson""s application filed 12th May 1997, titled xe2x80x9cMethod and Apparatus for Photoelectric Generation of Electricityxe2x80x9d, Ser. No. 08/854,302, now U.S. Pat. No. 5,973,259, assigned to the same assignee as the present invention and incorporated herein by reference, is described a Photoelectric Generator having close spaced electrodes separated by a vacuum. Photons impinging on the emitter cause electrons to be emitted as a consequence of the photoelectric effect. These electrons move to the collector as a result of excess energy from the photon: part of the photon energy is used escaping from the metal and the remainder is conserved as kinetic energy moving the electron. This means that the lower the work function of the emitter, the lower the energy required by the photons to cause electron emission. A greater proportion of photons will therefore cause photo-emission and the electron current will be higher. The collector work function governs how much of this energy is dissipated as heat: up to a point, the lower the collector work function, the more efficient the device. However there is a minimum value for the collector work function: thermionic emission from the collector will become a problem at elevated temperatures if the collector work function is too low.
Collected electrons return via an external circuit to the cathode, thereby powering a load. One or both of the electrodes are formed as a thin film on a transparent material, which permits light to enter the device. A solar concentrator is not required, and the device operates efficiently at ambient temperature.
It is well known from Quantum Mechanics that elementary particles have wave properties as well as corpuscular properties. The density of probability of finding an elementary particle at a given location is where |"psgr"|2 where "psgr" is a complex wave function and has form of the de Broglie wave:
"psgr"=A exp[(xe2x88x92i2xcfx80/h)(Etxe2x88x92pr)]xe2x80x83xe2x80x83(1)
Here "psgr" is wave function; h is Planck""s constant; E is energy of particle; p is impulse or momentum of particle; r is a vector connecting initial and final locations; t is time.
There are well known fundamental relationships between the parameters of this probability wave and the energy and impulse of the particle:
E is electron energy and p=(h/2xcfx80)kxe2x80x83xe2x80x83(2)
Here k is the wave number of probability wave. The de Broglie wavelength is given by:
xcex=2xcfx80/kxe2x80x83xe2x80x83(3)
If time, t, is set to 0, the space distribution of the probability wave may be obtained. Substituting (2) into (1) gives:
"psgr"=A exp(ikr)xe2x80x83xe2x80x83(4)
FIG. 1 shows an elementary particle wave moving from left to right perpendicular to a surface 7 dividing two domains. The surface is associated with a potential barrier, which means the potential energy of the particle changes as it passes through it.
Incident wave 1 A exp(ikx) moving towards the border will mainly reflect back as reflected wave 3 xcex2A exp(xe2x88x92ikx), and only a small part leaks through the surface to give transmitted wave 5 xcex1(x)A exp(ik""x) (xcex2≈1 greater than  greater than xcex1). This is the well-known effect known as quantum mechanical tunneling. The elementary particle will pass the potential energy barrier with a low probability, depending on the potential energy barrier height.
Usagawa in U.S. Pat. No. 5,233,205 discloses a novel semiconductor surface in which interaction between carriers such as electrons and holes in a mesoscopic region and the potential field in the mesoscopic region leads to such effects as quantum interference and resonance, with the result that output intensity may be changed. Shimizu in U.S. Pat. No. 5,521,735 discloses a novel wave combining and/or branching device and Aharanov-Bohm type quantum interference devices which have no curved waveguide, but utilize double quantum well structures.
Mori in U.S. Pat. No. 5,247,223 discloses a quantum interference semiconductor device having a cathode, an anode and a gate mounted in vacuum. Phase differences among the plurality of electron waves emitted from the cathode are controlled by the gate to give a quantum interference device operating as an AB type transistor.
Other quantum interference devices are also disclosed by Ugajin in U.S. Pat. No. 5,332,952 and Tong in U.S. Pat. No. 5,371,388.
In their U.S. patent application Ser. No. 08/924,910 filed Sep. 8, 1997, now abandoned, and Continuation in Part application Ser. No. 08/481,803 filed Aug. 31, 1998, assigned to the same assignee as the present invention and incorporated herein by reference in its entirety, Tavkhelidze and Edelson describe diode devices in which the separation of the electrodes is effected using piezo-electric positioning elements. They also teach a method for fabricating electrodes in which imperfections on one are exactly mirrored in the other, which allows electrode to be positioned very closely together.
Broadly the present invention is a method for enhancing the passage of elementary particles through a potential energy barrier utilizing interference of de Broglie waves to increase the probability of emission. This represents an improvement over all the aforementioned technologies.
In one embodiment, the invention provides an elementary particle-emitting surface having a series of indentations or protrusions. The depth of the indents (or height of the protrusions) is chosen so that the probability wave of the elementary particle reflected from the bottom of the indent interferes destructively with the probability wave of the elementary particle reflected from the surface. This results in a reduction of reflecting probability and as a consequence the probability of tunneling through the potential barrier to an adjacent surface is increased.
In another embodiment, the adjacent surface is absent. In this case, the energy spectrum of electrons becomes modified such that electrons may not tunnel out into the vacuum. This results in an increase in the Fermi level with a consequent reduction in apparent work function. The result is a surface which can be used in virtually any cathode application, including electronic circuits, antennas, imaging, amplifiers, flat-panel displays (FEDs), and all cold-cathode applications including cathode ray tubes.
In a further embodiment, the probability wave extends beyond the barrier, allowing electrons to be pumped into vacuum with a suitably applied voltage to give enhanced field effect emission.
In further embodiments, the invention provides vacuum diode devices, including a vacuum diode heat pump, a thermionic converter and a photoelectric converter, in which either or both of the electrodes in these devices utilize said elementary particle-emitting surface.
In yet further embodiments, the invention provides devices in which the separation of the surfaces in such devices is controlled by piezo-electric positioning elements.
A further embodiment provides a method for making an elementary particle-emitting surface having a series of indentations or protrusions.
Objects of the present invention are, therefore, to provide new and improved methods and apparatus for particle emission, having one or more of the following capabilities, features, and/or characteristics:
An object of the present invention is to provide a method for promoting transfer of elementary particles across a potential barrier, comprising providing a surface on which the potential barrier appears having a geometrical shape for causing de Broglie interference between said elementary particles.
An advantage of the present invention is that destructive interference between the waves of emitted particles may be created, which allows for an increase in particle emission.
A further object of the present invention is to provide an elementary particle-emitting surface having a geometrical shape for causing de Broglie interference.
An advantage of the present invention is that thermionic emission is greatly enhanced and becomes an extremely practical technology.
An object of the present invention is to provide a surface having a series of indentations (or protrusions), the depth of which is chosen so that the probability wave of the elementary particle reflected from the bottom of the indent interferes destructively with the probability wave of the elementary particle reflected from the surface.
An advantage of the present invention is that the effective work function of the material comprising the surface is reduced.

Method for increasing emission through a potential barrier


A heat exchanger in which a header and tank construction comprises separate header and tank portions which are used in combination to form a heat exchanger unit. End caps for the header and tank construction and baffles to form partitions or chambers within the header and tank construction are inserted in grooves formed in the separate header and/or tank portion(s). The heat exchanger assembly comprises spaced combined header and tank constructions between which extend a plurality of tubes which are inserted in slots in the header portions. An area of the header portion can have a plurality of center portions and slots between adjacent center portions for the tubular elements. The apexes of each center portion between the tubular element slots have a flattened area and there are side portions running downward from the center portion apex flats which also are substantially flattened.

Heat exchangers which employ two spaced header and tank constructions and wherein generally paralleled, open ended tubes interconnect the header and tank constructions and are in fluid communication with the interior of the header and tank constructions are known. Plate or serpentine fins can be disposed across the tubes between the header and tank constructions. These heat exchangers can be used in vehicular radiators and air conditioner condensers, evaporators and the like.
Structural improvements in such heat exchangers are desired to enhance the ease of manufacture and reduce the cost of manufacture and manpower while maintaining or improving durability and reliability. A round tube (1 pc) is always lighter. Lighter and more effective heat exchangers especially for vehicular radiators and air conditioners are sought after advantages.


A transcutaneous non-invasive device and method for measuring bilirubin levels is provided. The device and method utilize optical, electrical, and mechanical means in communication with processing means to calculate the serum bilirubin concentration. Blanching pressure is applied to the tissue, whose thickness is measured. The level of bilirubin is calculated from the thickness of the tissue and the detected and measured values of radiation transmitted through the living tissue.

Jaundice is fairly common among newborn infants, and is presumably a consequence of metabolic and physiological adjustments after birth. Often, the jaundice disappears within a fairly short period of time. In many cases the jaundice is detected early and treated effectively thus curing the infant within a fairly short period of time. When an infant is jaundiced the serum bilirubin normally rises to a high level. In extreme cases, a brain-damaging condition known as kernicterus can occur, leading to significant lifelong disability. In other extreme cases the jaundice can progress severely and even lead to death. Jaundice is usually diagnosed by an invasive blood test in which blood sample is usually taken from the heel. While this blood test is considered to be safe, obtaining the blood sample is an uncomfortable invasive procedure for a newborn infant.
U.S. Pat. No. 4,267,844 by Yamanishi relates to an electro-optical medical instrument provided for measuring non-invasively the presence of bilirubin in skin tissue. The instrument in this publication utilizes a source of flash light and optical means to provide a beam of light to illuminate the skin tissue. A portion of the reflected light is collected and separated by optical means to two components: One, having a central wavelength of 455 nm, which is known as being highly absorbed by bilirubin in skin tissue; And another having a wavelength greater than 500 nm, which absorption by the bilirubin in the skin tissue is low. These optical signals are measured by photoelectric transducers, the electrical output of which is amplified, and then used to compute a bilirubin indication by means of a logarithmic converter. User obtained calibration is called upon to convert the bilirubin indication to serum bilirubin concentration.
U.S. Pat. No. 6,064,898 by Aldrich relates to a non-invasive blood component analyzer using spectrophotometry. The analyzer in this publication utilizes measurements of transmitted light having various wavelengths selected in accordance with the blood components of interest. The parameters used to derive the blood components are each given by the difference between the systolic and diastolic values of the relevant measured signal. The visible wavelengths mentioned are 420 nm, 548 nm, 506 nm, 521 nm, 569 nm, and 586 nm. The first two are proposed for the measurement of bilirubin concentration in skin tissue.
Another non-invasive bilirubin measuring instrument is described in U.S. Pat. No. 5,792,049, by Eppstein, in which the reflectance of skin tissue is measured at several visible and near infra-red wavelengths. The measured values of reflectance are utilized to arrive at an estimate of the serum bilirubin concentration. For calibrating the instrument, the reflectance of a calibration target is measured at these same wavelengths
It is an object of the present invention to provide a method and means for applying non-invasive measurements for detecting the bilirubin level in a subject. It is a further object of the present invention to provide a method and means for applying non-invasive measurements for detecting the bilirubin level in a subject in a fast and simple manner.
Other objects and advantages of the present invention will become apparent as the description proceeds.
It is noted that the embodiments exemplified in the figures are not intended to be in scale and are in diagram form to facilitate ease of understanding and description.

Non-invasive device and method for measuring bilirubin levels


A clamp arrangement includes a pair of brackets adapted to be clamped on opposing sides of the wooden post to encapsulate a fractured portion, each bracket is made from an integral sheet of metal cut and pressed to define a longitudinal hemispherical chamber and a pair of longitudinal flanges extended out from each, the longitudinal hemispherical chamber having an upper end wherein a lip is supported in the lateral extension by a multitude of pressed out ribs such that when the clamp arrangement is required to be driven into the ground about the wooden post, the lip provides a support location for an impact tool to drive the clamp arrangement into the ground.

Wooden posts, the kinds one often equates with those that could be seen across vineyards and orchards play a significant part in maintaining the overall support and integrity of the interconnecting wire and/or trellis that is supporting the plantations thereon.
In many instances when the post becomes damaged this wiring needs to be disengaged and removed, the post replaced or repaired to then have the troublesome task of again re-tensioning the wire and/or trellis along a particular column or row.
Quite often the wooden post is damaged towards the base of the post and even in some instances underground.
It would be particularly advantageous if it was possible to almost insitu repair the damaged post rather than having to dig the post out to then replace with an undamaged post, and most importantly by being able to repair the post insitu not have to disengage the interconnecting wire and/or trellis.
As disclosed in the U.S. Pat. No. 985,605 for well over 100 years people have relied upon clamping arrangements to repair broken posts which for the most part include two brackets configured to come together on opposing sides such that their general shape will encapsulate the post and provide the necessary support.
As also shown in U.S. Pat. No. 985,605 these kinds of brackets can be positioned around the base of the wooden post both immediately above and below the ground.
In order to drive the brackets into the ground rather than having to dig out the post, brackets have been hitherto designed that include sharpened or arrowed ends on the bracket and so forth to which when impact is made on the top of the bracket this drives the fastened brackets into the ground.
However, in order to adequately absorb this impact to drive the brackets into the ground, the brackets themselves are often quite thick and made of reinforced material with various sections of the brackets forged or cast together due to their required thickness in being able to provide a location in which an impact tool can engage the bracket in order to drive into the ground and also allowing the bracket to be of a requisite strength so that it doesn't collapse, break or shatter upon such impact.
As would be expected therefore these kinds of clamping arrangements which require the ability to be impacted so as to be driven into the ground are expensive to manufacture, by their very nature heavy and cumbersome to handle, and require significant storage and transportation considerations.
As the person skilled in the art would realise in any field of technology costs and efficiencies are paramount. The repair of damaged posts in vineyards and orchards often involves the contractors or in-house maintenance personnel being required to repair many posts at a certain time of the year when growing and harvesting of the plant would make that time available.
Therefore, if repairing of damaged posts involved a repairer taking out into the field heavy, expensive and difficult to arrange brackets this will make their task all that more inefficient and uneconomical.
Still further if the clamping arrangement requires the brackets to be of increased thickness in order to provide a location and structural integrity to absorb the applied impact forces as the brackets are driven into the ground, it also then becomes a much more difficult task to first fasten the brackets together about the post and also given the thickness and weight of the brackets are significant greater effort and tooling is going to be required in order to drive such a clamp arrangement into the ground.
Accordingly, it is an object of this invention to provide a clamp arrangement for supporting a fractured portion of a wooden post wherein a portion of the clamp arrangement is required to be driven into the ground so that the post can be repaired in position with all the relevant wires and/or trellis attached so that no disturbance to the plantation supported thereon needs to be taken into consideration.

Clamps for repairing posts and methods and/or arrangements for repairing such posts with said clamps


A charging and disinfecting tray for a vehicle is disclosed. The charging and disinfecting tray comprises a wireless charger for charging an electronic device and a lighting apparatus. The lighting apparatus comprises a disinfecting apparatus, which incorporates at least one photoluminescent indicator. A controller is in communication with the wireless charger and the lighting apparatus and is operable to control the photoluminescent indicator by initiating a sterilization operation with the disinfecting apparatus.

Portable electronic devices have become an integral part of daily life. However, recent studies have shown that such devices can transmit infections, which may lead to various illnesses and dermatological issues. The disclosure provides for an illuminated charging bin utilizing photoluminescent materials to generate ambient light to notify a passenger of a status of at least a disinfection status of a device.

Photoluminescent disinfecting and charging bin


Systems and methods for monitoring voice and SMS communication exchanged over a UMTS network is described wherein a technique for quickly testing different Count-C values, until the correct value is ascertained is used. The Count-C parameter consists of a HyperFrame Number (HFN) and the system iteratively attempts to decrypt the packets using a series of candidate HFNs. For each of these candidate HFNs, and for each of the packets, the system produces a candidate Count-C by appending the sequence number (SN). The system then uses the candidate Count-C to calculate a candidate keystream block. Subsequently, the system uses the candidate keystream blocks to decrypt the packets, and then tests whether the packets were correctly decrypted. If the system deems the decryption successful, the system stops iterating through the candidate HFNs, and uses the candidate HFN that correctly decrypted the packets to decrypt subsequent packets in the communication session.

In cellular communication, a client device (or "client") exchanges communication with a Radio Network Controller (RNC) of a cellular network, via a base station controlled by the RNC. "Downlink" communication refers to communication passed by the RNC to the client, while "uplink" communication refers to communication passed by the client to the RNC.
The Universal Mobile Telecommunications System (UMTS) is a third-generation ("3G") system for cellular networks that employs sophisticated encryption. In UMTS networks, communication may occur over various physical channels and/or sub-channels. Each physical channel or sub-channel may include various transport channels and/or sub-channels, each of which, in turn, may include various logical channels and/or sub-channels. Each logical channel or sub-channel may operate in the Radio Link Control (RLC) Acknowledged Mode (AM), the RLC Unacknowledged Mode (UM), or the RLC Transparent Mode (TM).
To encrypt a particular packet of communication prior to transmitting the packet, the client or RNC uses a keystream block that is a function of five parameters: (i) the length of the packet, (ii) the "direction" of the packet, which has a value of 0 (for uplink packets) or 1 (for downlink packets), (iii) a five-bit identifier of the logical channel (or sub-channel), known as the "bearer channel," through which the packet is to be passed, (iv) a 32-bit ciphering sequence number known as "Count-C," and (v) a ciphering key known as "CK." To decrypt the packet, the receiving party uses the same keystream block that was used to encrypt the packet.
To start a communication session with a particular client, the RNC passes, e.g., over the common Forward Access Channel (FACH), an unencrypted Radio Resource Control (RRC) connection setup packet. This packet specifies the client, and also specifies a physical channel known as a Dedicated Control Channel (DCCH). The client, upon receiving this packet, then tunes to the specified DCCH. Subsequently, after the passing of any other relevant communication (such as a location update from the client), encrypted communication may be passed over the DCCH. (Communication may be passed in parallel over multiple logical channels of the DCCH.) For example, Short Message Service (SMS) communication may be passed over an RLC AM logical channel. As another example, to begin voice communication, the RNC may pass, over the DCCH, a "radio bearer setup" message that specifies one or more channels over which the voice communication will be passed. The client may then tune to the specified channels, and the voice communication may then be passed, encrypted, over these channels.
In RLC AM and RLC UM, the Count-C parameter consists of a HyperFrame Number (HFN) followed by a sequence number (SN). In RLC AM, the HFN consists of 20 bits, while the SN consists of 12 bits; in RLC UM, the HFN consists of 25 bits, while the SN consists of 7 bits. For each logical channel that is opened, the HFN and SN are initialized to respective initial values. In particular, in RLC AM, the HFN is initialized to a 20-bit START parameter that is passed from the client to the RNC; in RLC UM, the initial value of HFN is derived from START by padding START with five trailing zeros. Following the opening of the channel, the SN, which is specified in each packet, is incremented for each packet passed over the channel. After the SN reaches its maximum value (e.g., 127 for a 7-bit SN), the SN is reset to its initial value, and the HFN is incremented.
In RLC TM, the Count-C parameter consists of a 24-bit HFN followed by an 8-bit connection frame number (CFN). For each RLC TM channel, the initial value of HFN is derived from START by padding START with four trailing zeros. The CFN is derived separately for each packet from a system frame number (SFN), which is broadcast by the base station via which the communication is passed and is incremented periodically. After the CFN reaches its maximum value of 255, the CFN is reset, and the HFN is incremented.
In some cases, a security or law-enforcement agency may wish to monitor communication exchanged over a UMTS network. This is challenging, however, due to the sophisticated encryption employed by UMTS.
US Patent Application Publication 2016/0182460 describes a method in a receiver, including receiving from a transmitter a sequence of communication packets, which carry data encrypted with an encryption scheme. The encryption scheme depends on a counter value that is incremented independently by each of the transmitter and the receiver. Attempts are made to decrypt the data of a received packet multiple times using different, respective counter values, to produce multiple respective decrypted outputs. A decrypted output in which the data has been decrypted correctly is identified, the counter value is corrected, and the data of the received packet is recovered from the identified decrypted output.
U.S. Pat. No. 9,385,865 describes a method including, in a mobile communication terminal, receiving a signal, which carries media content that has been encrypted after being compressed in accordance with a compression protocol having a plurality of predefined configurations. Each configuration specifies a respective compression mode of the compression protocol. The received signal is decrypted, and one or more parameters that define a configuration of the compression protocol that was used for compressing the media content are determined from the decrypted signal. An absence of match is detected when the determined one or more parameters do not match any of the plurality of predetermined configurations of the compression protocol. An error in decrypting the received signal is identified based on detecting the absence of a match.
US Patent Application Publication 2016/0269900, whose disclosure is incorporated herein by reference, describes a monitoring system that monitors authentication sessions both on the air interface between the terminals and the network, and on at least one wired network-side interface between network-side elements of the network. The monitoring system constructs a database of sets of network-side authentication parameters using network-side monitoring. Each set of network-side authentication parameters originates from a respective authentication session and is associated with the International Mobile Station Identity (IMSI) of the terminal involved in the session. In order to start decrypting the traffic of a given terminal, the system obtains the off-air authentication parameters of that terminal using off-air monitoring, and finds an entry in the database that matches the air-interface authentication parameters. From the combination of correlated network-side and off-air authentication parameters, the processor is able to extract the parameters needed for decryption.

System and method for decrypting communication over a UMTS network


A heat sink clip (30) includes an elongated resilient main body (31) with two spaced barbs (315) at a first end thereof, a first locking member (33) coupled with a second end of the main body and a moveable second locking member (32) movably coupled with the first end of the main body. The barbs each vertically extend and include a neck (3151) connecting with the main body and a locking end (3152) at a free end thereof. The moveable second locking member includes an operating portion (321) and a locking leg (322) defining two connecting slots (323) therein. Each of the connecting slots includes a longitudinally narrow portion (3231) and a longitudinally wide portion (3232) beside the narrow portion. The barbs enter the connecting slots through the wide portions and the necks are received in the narrow portions.

1. Field of the Disclosure
The disclosure generally relates to clips, and particularly to a clip used for securing a heat sink to an electronic component.
2. Description of Related Art
It is well-known that heat is generated by electronic components such as central processing units (CPUs) of computers. If the generated heat is not rapidly and efficiently removed, the electronic component may overheat and the performance thereof may be significantly degraded. Generally, a heat dissipation device such as a heat sink is attached to the electronic component for a cooling purpose.
In order to attach the heat sink to the electronic component, a fastening device such as a clip is generally required. For example, US Patent Application Publication No. 2007/0139891A1 discloses a heat sink clip used for securing a heat sink to a CPU which is mounted on a circuit board. The heat sink clip includes a spring member having an elongated main body, a second locking leg, an actuating member and an assisting member. A connecting portion is at one end of the main body and a first locking leg extends from the other end of the main body. The second locking leg is coupled to the connecting portion of the main body. The actuating member connects pivotally with the second locking leg. The assisting member is located between the actuating member and the connecting portion of the main body of the spring member. The actuating member forms a handle portion at one end thereof and a round rotating portion at the other end thereof. The rotating portion includes a plurality of teeth formed on a circumferential surface thereof. The assisting member includes a wedged main body and forms an inclined top surface at a top of the wedged main body. The assisting member further forms a plurality of teeth on the inclined top surface thereof for engaging the corresponding teeth of the actuating member. In operation, the actuating member is rotated to move the second locking leg from a released position to an abutting position, to impel the heat sink toward the CPU. The heat sink clip can be easily operated by hand, without requiring undue force. However, numerous components are required, and assembly is complex.
What is needed, therefore, is a heat sink clip for securing a heat sink to an electronic component which overcomes the described limitations.

Fu Zhun Precision Insdustry (Shen Zhen) Co., Ltd.


A broadband capacitively-loaded tunable antenna, and device there for is provided. The device comprises: an antenna feed; a first radiating arm connected to the antenna feed; a second radiating arm capacitively coupled to the first radiating arm; an adjustable reactance device connecting the second radiating arm to one or more of a ground and a third radiating arm; and, a processor in communication with the adjustable reactance device, the processor configured to adjust a reactance of the adjustable reactance device to tune a resonance frequency of a combination of the second radiating arm, the adjustable reactance device, and, when present, the third radiating arm.

Current mobile electronic devices, such as smartphones, tablets and the like, generally have different antennas implemented to support different types of wireless protocols and/or to cover different frequency ranges. For example, LTE (Long Term Evolution) bands, GSM (Global System for Mobile Communications) bands, UMTS (Universal Mobile Telecommunications System) bands, and/or WLAN (wireless local area network) bands, cover frequency ranges from 700-960 MHz, 1710-2170 MHz, and 2500-2700 MHz and the specific channels within these bands can vary from region to region necessitating the use of different antennas for each region in similar models of devices. This can complicate both resourcing and managing the different antennas for devices in each region.

Broadband capacitively-loaded tunable antenna


A label holder for displaying information-containing non-adhesive labels on a C-channel at the front of a merchandise shelf in a supermarket or the like. The label holder may be a co-extrusion of an opaque body panel and a transparent cover resiliently connected along their lower edges to define a label-receiving pocket therebetween or it may simply have opposing U-shaped channels defined by upper and lower lips to receive and retain the label. A pair of upwardly and rearwardly extending leg members are integral with the body panel. One of the leg members underlies and extends behind the lower flange member of the C-channel and the other leg member overlies and extends in front of the lower flange member. The leg members terminate in gripping elements biased toward each other to grippingly engage therebetween the front and rear surfaces of the central portion of the C-channel. An upper lip may be provided on the body panel to engage behind the upper flange member of the C-channel and/or a rearwardly and downwardly depending flexible locking finger may be provided on the overlying leg member to engage behind the lower flange member of the C-channel.

Steel merchandise shelves commonly found in supermarkets and the like generally provide a generally C-shaped price channel along the front edge. Where such shelves are formed without a channel, plastic fittings can be added to the shelves to provide such channels. Price channels have upper and lower flange members along their edges and can be used to accommodate snap-in labels or label or sign holders adapted to receive and display non-adhesive paper or plastic labels or signs containing magnetic inventory bar coding or printed pricing or other such information for the consumer. Alternatively, adhesive-backed labels can be affixed directly to the front surface of the C-channel. While adhesive-backed labels may be secured to surfaces of varying dimensions, they are difficult to remove or replace when different merchandise is to be displayed on the shelf, and generally leave behind an unsightly adhesive residue. The cost of such labels is not only higher because of the adhesive, the labor costs associated with removing and replacing such labels significantly increases the overall expense of such systems.
Non-adhesive labels are less expensive to manufacture; additionally, they can generally be installed and removed much more readily. Moreover, the appearance of shelving provided with label holders adapted to removably receive non-adhesive labels is dramatically improved.
Depending upon the type of shelving, the price channel configuration may be different. Although the size of most price channels are fairly standard, no two shelves are exactly alike. Thus, the height of the channel formed between the upper and lower flange members may vary because of manufacturing tolerances, even on different shelves of the same shelf system.
Various attachments are currently on the market for adapting a C-channel to removably receive and display non-adhesive information-containing labels to a consumer. In most versions, one or more rearwardly extending flexible legs are provided with portions designed to snap into the upper and lower flanges of the C-channel. While such attachments may provide only upper and lower channels to receive and retain a paper or plastic label, much like the C-channel on the shelf, they commonly include a main body or backing panel and a hingedly attached transparent cover which together define a pocket between them for reception of the non-adhesive label. In some circumstances, a transparent label cover can be snapped directly onto a C-channel over the lower edge, providing a pocket for a non-adhesive label between the cover and the C-channel itself.
While each of the foregoing systems are useful, they each have limited application and one or more disadvantages. For example, while the label holders with rearwardly extending legs can accommodate C-channels of somewhat varying dimensions, they still must fit between and engage both the upper and lower flange elements limiting their versatility.
The snap-on covers rely heavily on their ability to mount on and pivot about the lower edge of a price channel placing great stress on the connection, particularly if the design of the shelf is somewhat unusual or if the lower edge of the channel is bent. Moreover, since the covers must be transparent in order for the information on the label to be viewed therethrough, any unsightly portion of the C-channel not hidden by a label is visible to passersby.

Label holder for attachment to price channel


There is provided a sidewall closeout area assembly for an aircraft. The assembly includes a raceway with a first end to attach to a sidewall assembly, a second end to attach to aircraft floor structure(s), and a raceway body with first access opening(s) providing access to one or more of, a crown area and an underfloor area, for conductive elements routed along the raceway. The assembly further includes a raceway cover removably coupled to the raceway and having second access opening(s) providing access to the cabin and to an overfloor area in the cabin for the conductive elements. The assembly further includes a closeout area formed between the raceway body and the raceway cover, to house and protect the conductive elements. The assembly facilitates accessibility to the conductive elements, and provides a routing path for the conductive elements that does not need to be reconfigured for different aircraft cabin layouts.

Aircraft, such as commercial aircraft, have sidewall panels located in an interior of an aircraft passenger cabin. Such sidewall panels are designed to cover an aircraft frame and walls, as well as to cover aircraft insulation, ducting, and conductive elements, such as electrical runs, for example, wiring and cables, and systems transport elements, for example, air lines and water lines, which are located along the length of the aircraft passenger cabin.
In addition, electrical runs including power, data, in-flight entertainment (IFE), lighting, and other seat systems, are typically routed from behind sidewall panels or from under the floor to the seats in the aircraft passenger cabin. Such electrical runs may be installed in conduits that are attached by adhesive, or other attachment means, to the aircraft floor. These conduits are typically covered with floor coverings, such as carpet or mats, which may cause bumps and discontinuities in the floor coverings. Moreover, such floor coverings may require additional seams for breakout locations for the electrical runs. Further, secondary shielding layers may need to be installed around the electrical runs to avoid damage from potential contact sources, such as passengers or carry-on freight. However, such secondary shielding layers may be heavy and add unwanted weight to the aircraft. Also, with reconfigurable palletized seats, which have large metallic structures that are bolted to the floor of the aircraft passenger cabin, when such palletized seats are reconfigured, complex conduit or raceway layouts must be designed to avoid the large metallic structures.
Electrical runs may also be routed through the crown and through the floor of the aircraft passenger cabin to connect to main electrical runs in the crown and underfloor areas. However, electrical runs routed through the floor typically require that floor penetrations be made through the floor area under the seats in the aircraft passenger cabin. Such routing of the electrical runs through the floor may cause variation in floor panels, may cause holes in the floor, and may cause floor covering protrusions. Moreover, when the seats are reconfigured or installed in the aircraft passenger cabin, such electrical runs routed in the underfloor area and in the crown area may be difficult to access or to modify without interference through existing aircraft structures.
Known electrical run routing assemblies and systems exist that provide a flat floor by using channels. However, such known electrical run routing assemblies and systems may still result in floor panel variability and penetrations through the floor, and such channels may become an obstacle during production operations, when parts and tools need to be transported within the aircraft passenger cabin.
Further, known electrical run routing systems and methods in the aircraft passenger cabin may result in numerous variable configurations and layouts that may be difficult to manage and difficult to install. Moreover, the extensive time and effort for installation using such known electrical run routing systems and methods may present ergonomic issues for installers.
Accordingly, there is a need in the art for an assembly, system, and method for routing conductive elements in aircraft passenger cabins that eliminate variability in design and installation, that allow for accessibility and easy installation and routing without interference through aircraft structures, that allow for rapid reconfiguration of seats in the aircraft passenger cabin, that have aesthetic benefits, that eliminate possible damage to the electrical runs, that reduce cost and weight, and that provide advantages over known assemblies, systems, and methods.

Sidewall closeout area assembly, system, and method for routing conductive elements in an aircraft


In one implementation, a non-transitory computer-readable storage medium stores program instructions computer-executable on a computer to perform operations. The operations include obtaining first content representing a physical environment in which an electronic device is located using an image sensor of the electronic device. A physical feature corresponding to a physical object in the physical environment is detected using the first content. A feature descriptor corresponding to a physical parameter of the physical feature is determined using the first content. Second content representing a computer generated reality (CGR) environment is generated based on the feature descriptor and presented on a display of the electronic device.

Various electronic devices exist, such as head-mound devices (also known as headsets and HMDs), with displays that present users with experiences in which they may be fully immersed in a surrounding physical environment, fully immersed in a virtual reality environment comprising virtual objects, or anywhere in between. These devices often generate experiences utilizing pre-canned (or fixed) content to represent a CGR environment. When presented on a display of an electronic device, that pre-canned content provides the same experience regardless of the physical environment in which the electronic device is physically located.

Techniques for locating virtual objects relative to real physical objects


A method of manufacturing a transistor and a structure thereof, wherein a very shallow region having a high dopant concentration of germanium is implanted into a channel region of a transistor at a low energy level, forming an amorphous germanium implantation region in a top surface of the workpiece, and forming a crystalline germanium implantation region beneath the amorphous germanium implantation region. The workpiece is annealed using a low-temperature anneal to convert the amorphous germanium region to a crystalline state while preventing a substantial amount of diffusion of germanium further into the workpiece, also removing damage to the workpiece caused by the implantation process. The resulting structure includes a crystalline germanium implantation region at the top surface of a channel, comprising a depth below the top surface of the workpiece of about 120 Å or less. The transistor has increased mobility and a reduced effective oxide thickness (EOT).

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. A transistor is an element that is utilized extensively in semiconductor devices. There may be millions of transistors on a single integrated circuit (IC), for example. A common type of transistor used in semiconductor device fabrication is a metal oxide semiconductor field effect transistor (MOSFET).
The gate dielectric for MOSFET devices has in the past typically comprised silicon dioxide, which typically has a dielectric constant of 3.9. However, as devices are scaled down in size, using silicon dioxide for a gate dielectric becomes a problem because of gate leakage current, which can degrade device performance. Therefore, there is a trend in the industry towards the development of the use of high dielectric constant (k) materials for use as the gate dielectric in MOSFET devices. The term "high k materials" as used herein refers to a dielectric material having a dielectric constant of 4.0 or greater.
High k gate dielectric development has been identified as one of the future challenges in the 2003 edition of International Technology Roadmap for Semiconductors (ITRS), incorporated herein by reference, which identifies the technological challenges and needs facing the semiconductor industry over the next 15 years. For low power logic (for portable electronic applications, for example), it is important to use devices having low leakage current, in order to extend battery life. Gate leakage current must be controlled in low power applications, as well as sub-threshold leakage, junction leakage, and band-to-band tunneling. For high performance (namely, high speed) applications, it is important to have a low sheet resistance and a minimal effective gate oxide thickness.
To fully realize the benefits of transistor scaling, the gate oxide thickness needs to be scaled down to less than 2 nm. However, the resulting gate leakage current makes the use of such thin oxides impractical in many device applications where low standby power consumption is required. For this reason, the gate oxide dielectric material will eventually be replaced by an alternative dielectric material that has a higher dielectric constant. However, device performance using high k dielectric materials tends to suffer from trapped charge in the dielectric layer, which deteriorates the mobility, making the drive current lower than in transistors having silicon dioxide gate oxides, thus reducing the speed and performance of transistors having high k gate dielectric materials.
FIG. 1 shows a cross-sectional view of a prior art semiconductor device 100 comprising a transistor with a high k gate dielectric material. The semiconductor device 100 includes field oxide regions 104 formed in a workpiece 102. The transistor includes a source S and a drain D that are separated by a channel region C. The transistor includes a gate dielectric 108 that comprises a high k insulating material. A gate 110 is formed over the gate dielectric 108, as shown.
After the gate 110 is formed, the source region S and drain region D are lightly doped, e.g., by a lightly doped drain (LDD) implant, to form extension regions 120 of the source S and drain D. Insulating spacers 112 are then formed along the sidewalls of the gate 110 and gate dielectric 108, and a source/drain implant is performed on exposed surfaces of the workpiece 102, followed by a high temperature thermal anneal, typically at temperatures of about 1000 to 1050° C., to form the source S and drain D.
A problem with the prior art semiconductor device 100 shown in FIG. 1 is that an interfacial oxide 114 is formed between the workpiece 102 and the high k dielectric 108, and an interfacial oxide 116 is formed between the high k dielectric 108 and the gate 110. The interfacial oxides 114 and 116 form because the workpiece 102 typically comprises silicon, which has a strong tendency to form silicon dioxide (SiO2) in the presence of oxygen, during the deposition of the high k gate dielectric 108, for example, forming interfacial oxide 114. Likewise, the gate 110 often comprises polysilicon, which also tends to form an interfacial oxide 116 comprising SiO2 on the top surface of the high k gate dielectric 108.
The source S and drain D regions of the semiconductor device 100 may be made to extend deeper within the workpiece 102 by implanting ions of a dopant species, and annealing the workpiece 102 to cause diffusion of the dopant deep within the workpiece 102, forming the source S and drain D regions. Another problem with the prior art structure 100 is that the high temperature anneal processes used to form the source S and drain D tend to degrade the dielectric constant of the high k gate dielectric 108. In particular, when exposed to a high temperature treatment, the interfacial oxides 114 and 116 become thicker, increasing the effective oxide thickness (EOT) 118 evaluated electrically from the entire gate stack (the interfacial oxide 114, high k dielectric 108 and interfacial oxide 116) of the semiconductor device 100. Thus, by using a high k dielectric material for the gate dielectric 108, it can be difficult to decrease the gate dielectric 108 thickness to a dimension required for the transistor design, as devices 100 are scaled down in size.
Therefore, what is needed in the art is a transistor design and fabrication method having a high k dielectric material, wherein the effective gate dielectric thickness is reduced.
Another challenge in the scaling of transistors is increasing the mobility in the channel region, which increases the speed of the device. Thus, what is also needed in the art is a transistor design and fabrication method wherein mobility in the channel region is increased.

Transistor with shallow germanium implantation region in channel