A composition consisting of a mixture of a silicone polymer having the formula ##STR1## having a viscosity of 350-30,000 centistokes, and a polyoxyalkylene siloxane copolymer having a viscosity of fifteen hundred centistokes at 25.degree. C.

This invention relates to a composition which is a mixture of a silicone polymer and a silicon polymer which is useful as a cosmetic raw material because of its water dispersibility.
The use of silicones as cosmetic raw materials is well documented as are their benefits. One hindrance to the use of silicones in person care products for application to the skin and hair is their limited solubility in water and other polar media frequently encountered in the cosmetic market. One solution has been to incorporate silicones by means of sometimes complex emulsion techniques which often require expensive equipment and high shear. Thus, a need exists for water dispersible silicones and silicones which have increased water solubility and water compatibility.
In U.S. Pat. No. 4,846,982 issued Jul. 11, 1989, there is disclosed a three component system including a silicone polymer, a silicone copolymer, and a quaternary ammonium compound, which is taught to be useful as a conditioner in fabric care applications.
In accordance with the present invention, it has been unexpectedly discovered that when only the silicon polymer and the silicon copolymer are combined together, that the two components form homogeneous mixtures which can be further diluted with water to form shelf stable products without emulsification. This benefit increases the value of the silicones as cosmetic raw materials.


A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuO2 layer formed on a surface of the damascene pattern and an Al deposit-inhibiting layer formed on a portion of the RuO2 layer in both-side upper portion of the damascene pattern; and a wiring metal layer including Al formed on the diffusion barrier layer by MOCVD method in order to fill the damascene pattern.

The present invention relates to a metal wiring of a semiconductor device, and more particularly, to a metal wiring in a semiconductor device by forming an Al layer without creating voids therein by controlling the Al-growth characteristics, and a method for forming the same.
For highly integrated semiconductor devices, high-speed is an increasingly important requirement, and therefore memory cells are formed in a stacked structure. Moreover, the metal wiring used for carrying electric signals to the cells is also formed in a multi-layer structure. The metal wiring having the multi-layer structure provides advantageous design flexibility and allows more leeway in setting the margins for the wiring resistance, the current capacitance, etc.
Aluminum (Al) is widely used as a material for the metal wiring in a highly integrated semiconductor device, for its superior electrical conductivity and forming efficiency when applied in a fabrication process. The Al is used as a diffusion barrier layer, since it can ensure electric characteristics of the semiconductor device.
Hereinafter, a method is described for forming the metal wiring in a semiconductor device according to prior art, which uses Al as the material of a metal wiring referring to FIG. 1.
A first oxide layer 140 and a second oxide layer 160 are sequentially formed over the semiconductor substrate 100 on which a conductive patterns 110 and a interlayer insulating layer 120 are formed. Until the conductive patterns 110 is exposed, the first oxide layer 140 and the second oxide layer 160 are etched so as to form via-holes 171 defining via contact regions and trenches 172 defining metal wiring regions, thereby forming dual-type damascene pattern 170 including the via-holes 171 and the trenches 172.
A diffusion barrier layer 180 is formed on the second oxide layer 160 including the damascene pattern 170. Herein, the diffusion barrier layer 180 is formed as a stacked layer composed of a Ti layer 181 and a TiN layer 182. Al is filled in the damascene pattern 170 on which the diffusion barrier layer 180 is formed, thereby forming via contacts 193 within the via-holes 171 and the metal wirings 194 composed of Al layer within the trenches 172.
As described above according to prior art, upon forming the metal wiring using Al, the diffusion barrier layer 180 is used for preventing the electric characteristics from being degraded due to high bonding force with the oxide layer and movement and diffusion of electrons from the metal wiring. The diffusion barrier layer 180 is formed by using the Ti layer 181 and the TiN layer 182 or a stacked layer of both.
Meanwhile, as the design rule of the semiconductor device decrease, the line width of the via-hole 193 and the trench 194 would also decrease. However, if the stacked layer of the Ti layer 181 and the TiN 182 layer is formed as the diffusion barrier layer 180 on the surface of the via-hole 193 and the trench 194 at the time that the line width of the via-hole 193 and the trench 194 decreases, the margin of the line width of the via-hole 193 and the trench 194 also decreases.
This type of margin reduction of the line-width of the via-hole 193 and the trench 194 caused by the diffusion barrier layer 180 formed as the stacked layer of the Ti layer 181 and the TiN layer 182 causes overhang when depositing Al in the via-hole 193 and the trench 194 to form metal wiring. As a result, Al is not entirely filled in the via-hole 193 and the trench 194, and therefore voids are often generated within the via-hole 193 and the trench 194.
If the voids are generated on lower portion of the via-hole 193 and the trench 194 due to reduction in the line-width of the via-hole 193 and the trench 194, it causes errors in operational characteristics of the semiconductor device or decrease the total yield of the semiconductor device.

Metal wire for a semiconductor device formed with a metal layer without voids therein and a method for forming the same


Novel compounds are provided which are inhibitors of MTP and thus are useful for lowering serum lipids and treating atherosclerosis and related diseases, and have the structure ##STR1## including pharmaceutically acceptable salts thereof, or prodrug esters thereof,. A is ##STR2## where Z is N or CH, or where Z is ##STR3## or CH.sub.2 when --- is a single bond; Q is (1)--O--;. (2)--S--; or ##STR4## B is: ##STR5## and wherein L.sup.1, R, R.sup.1, R.sup.3, R.sup.3 ', R.sup.3a, R.sup.3b, R.sup.4, R.sup.4 ', R.sup.5, R.sup.5a, X, ##STR6## are as defined herein.

The microsomal triglyceride transfer protein (MTP) catalyzes the transport of triglyceride (TG), cholesteryl ester (CE), and phosphatidylcholine (PC) between small unilamellar vesicles (SUV). Wetterau & Zilversmit, Chem. Phys. Lipids 38, 205--22 (1985). When transfer rates are expressed as the percent of the donor lipid transferred per time, MTP expresses a distinct preference for neutral lipid transport (TG and CE), relative to phospholipid transport. The protein from bovine liver has been isolated and characterized. Wetterau & Zilversmit, Chem. Phys. Lipids 38, 205-22 (1985). Polyacrylamide gel electrophoresis (PAGE) analysis of the purified protein suggests that the transfer protein is a complex of two subunits of apparent molecular weights 58,000 and 88,000, since a single band was present when purified MTP was electrophoresed under nondenaturing condition, while two bands of apparent molecular weights 58,000 and 88,000 were identified when electrophoresis was performed in the presence of sodium dodecyl sulfate (SDS). These two polypeptides are hereinafter referred to as 58 kDa and 88 kDa, respectively, or the 58 kDa and the 88 kDa component of MTP, respectively, or the low molecular weight subunit and the high molecular weight subunit of MTP, respectively.
Characterization of the 58,000 molecular weight component of bovine MTP indicates that it is the previously characterized multifunctional protein, protein disulfide isomerase (PDI). Wetterau et al., J. Biol. Chem. 265, 9800-7 (1990). The presence of PDI in the transfer protein is supported by evidence showing that (1) the amino terminal 25 amino acids of the bovine 58,000 kDa component of MTP is identical to that of bovine PDI, and (2) disulfide isomerase activity was expressed by bovine MTP following the dissociation of the 58 kDa-88 kDa protein complex. In addition, antibodies raised against bovine PDI, a protein which by itself has no TG transfer activity, were able to immunoprecipitate bovine TG transfer activity from a solution containing purified bovine MTP.
PDI normally plays a role in the folding and assembly of newly synthesized disulfide bonded proteins within the lumen of the endoplasmic reticulum. Bulleid & Freedman, Nature 335, 649-51 (1988). It catalyzes the proper pairing of cysteine residues into disulfide bonds, thus catalyzing the proper folding of disulfide bonded proteins. In addition, PDI has been reported to be identical to the beta subunit of human prolyl 4-hydroxylase. Koivu et al., J. Biol. Chem. 262, 6447-9 (1987). The role of PDI in the bovine transfer protein is not clear. It does appear to be an essential component of the transfer protein as dissociation of PDI from the 88 kDa component of bovine MTP by either low concentrations of a denaturant (guanidine HCl), a chaotropic agent (sodium perchlorate), or a nondenaturing detergent (octyl glucoside) results in a loss of transfer activity. Wetterau et al., Biochemistry 30, 9728-35 (1991). Isolated bovine PDI has no apparent lipid transfer activity, suggesting that either the 88 kDa polypeptide is the transfer protein or that it confers transfer activity to the protein complex.
The tissue and subcellular distribution of MTP activity in rats has been investigated. Wetterau & Zilversmit, Biochem. Biophys. Acta 875, 610-7 (1986). Lipid transfer activity was found in liver and intestine. Little or no transfer activity was found in plasma, brain, heart, or kidney. Within the liver, MTP was a soluble protein located within the lumen of the microsomal fraction. Approximately equal concentrations were found in the smooth and rough microsomes.
Abetalipoproteinemia is an autosomal recessive disease characterized by a virtual absence of plasma lipoproteins which contain apolipoprotein B (apoB). Kane & Havel in The Metabolic Basis of Inherited Disease, Sixth edition, 1139-64 (1989). Plasma TG levels may be as low as a few mg/dL, and they fail to rise after fat ingestion. Plasma cholesterol levels are often only 20-45 mg/dL. These abnormalities are the result of a genetic defect in the assembly and/or secretion of very low density lipoproteins (VLDL) in the liver and chylomicrons in the intestine. The molecular basis for this defect has not been previously determined. In subjects examined, triglyceride, phospholipid, and cholesterol synthesis appear normal. At autopsy, subjects are free of atherosclerosis. Schaefer et al., Clin. Chem. 34, B9-12 (1988). A link between the apoB gene and abetalipoproteinemia has been excluded in several families. Talmud et al., J. Clin. Invest. 82, 1803-6 (1988) and Huang et al., Am. J. Hum. Genet. 46, 1141-8 (1990).
Subjects with abetalipoproteinemia are afflicted with numerous maladies. Kane & Havel, supra. Subjects have fat malabsorption and TG accumulation in their enterocytes and hepatocytes. Due to the absence of TG-rich plasma lipoproteins, there is a defect in the transport of fat-soluble vitamins such as vitamin E. This results in acanthocytosis of erythrocytes, spinocerebellar ataxia with degeneration of the fasciculus cuneatus and gracilis, peripheral neuropathy, degenerative pigmentary retinopathy, and ceroid myopathy. Treatment of abetalipoproteinemic subjects includes dietary restriction of fat intake and dietary supplementation with vitamins A, E and K.
In vitro, MTP catalyzes the transport of lipid molecules between phospholipid membranes. Presumably, it plays a similar role in vivo, and thus plays some role in lipid metabolism. The subcellular (lumen of the microsomal fraction) and tissue distribution (liver and intestine) of MTP have led to speculation that it plays a role in the assembly of plasma lipoproteins, as these are the sites of plasma lipoprotein assembly. Wetterau & Zilversmit, Biochem. Biophys. Acta 857, 610-7 (1986). The ability of MTP to catalyze the transport of TG between membranes is consistent with this hypothesis, and suggests that MTP may catalyze the transport of TG from its site of synthesis in the endoplasmic reticulum (ER) membrane to nascent lipoprotein particles within the lumen of the ER.
Olofsson and colleagues have studied lipoprotein assembly in HepG2 cells. Bostrom et al., J. Biol. Chem. 263, 4434-42 (1988). Their results suggest small precursor lipoproteins become larger with time. This would be consistent with the addition or transfer of lipid molecules to nascent lipoproteins as they are assembled. MTP may play a role in this process. In support of this hypothesis, Howell and Palade, J. Cell Biol. 92, 833-45 (1982), isolated nascent lipoproteins from the hepatic Golgi fraction of rat liver. There was a spectrum of sizes of particles present with varying lipid and protein compositions. Particles of high density lipoprotein (HDL) density, yet containing apoB, were found. Higgins and Hutson, J. Lipid Res. 25, 1295-1305 (1984), reported lipoproteins isolated from Golgi were consistently larger than those from the endoplasmic reticulum, again suggesting the assembly of lipoproteins is a progressive event. However, there is no direct evidence in the prior art demonstrating that MTP plays a role in lipid metabolism or the assembly of plasma lipoprotein.
Recent reports (Science, Vol. 258, page 999, 1992; D. Sharp et al, Nature, Vol. 365, page 65, 1993) demonstrate that the defect causing abetalipoproteinemia is in the MTP gene, and as a result, the MTP protein. Individuals with abetalipoproteinemia have no MTP activity, as a result of mutations in the MTP gene, some of which have been characterized. These results indicate that MTP is required for the synthesis of apoB containing lipoproteins, such as VLDL, the precursor to LDL. It therefore follows that inhibitors of MTP would inhibit the synthesis of VLDL and LDL, thereby lowering VLDL levels, LDL levels, cholesterol levels, and triglyceride levels in animals and man.
Canadian Patent Application No. 2,091,102 published Mar. 2, 1994 (corresponding to U.S. application Ser. No. 117,362, filed Sep. 3, 1993 (file DC21b)) which is incorporated herein by reference), reports MTP inhibitors which also block the production of apoB containing lipoproteins in a human hepatic cell line (HepG2 cells). This provides further support for the proposal that an MTP inhibitor would lower apoB containing lipoprotein and lipid levels in vivo. This Canadian patent application discloses a method for identifying the MTP inhibitors ##STR7## which has the name 2-[1-(3,3-diphenylpropyl)-4-piperidinyl]-2,3-dihydro-3-oxo-1H-isoindole hydrochloride and ##STR8## which has the name 1-[3-(6-fluoro-1-tetralanyl)-methyl]-4-O-methoxyphenyl piperazine.
EP 0643057Al published Mar. 15, 1995, discloses MTP inhibitors of the structure ##STR9## where X is: CHR.sup.8, ##STR10## R.sup.8, R.sup.9 and R.sup.10 are independently hydrogen, alkyl, alkenyl, alkynyl, aryl, arylalkyl, heteroaryl, heteroarylalkyl, cycloalkyl, or cycloalkylalkyl;
Y is --(CH.sub.2).sub.m -- or ##STR11## where m is 2 or 3; R.sup.1 is alkyl, alkenyl, alkynyl, aryl, heteroaryl, arylalkyl (wherein alkyl has at least 2 carbons), diarylalkyl, arylalkenyl, diarylalkenyl, arylalkynyl, diarylalkynyl, diarylalkylaryl, heteroarylalkyl (wherein alkyl has at least 2 carbons), cycloalkyl, or cycloalkylalkyl (wherein alkyl has at least 2 carbons); all of the aforementioned R.sup.1 groups being optionally substituted through available carbon atoms with 1, 2, or 3 groups selected from halo, haloalkyl, alkyl, alkenyl, alkoxy, aryloxy, aryl, arylalkyl, alkylmercapto, arylmercapto, cycloalkyl, cycloalkylalkyl, heteroaryl, fluorenyl, heteroarylalkyl, hydroxy or oxo; or
R.sup.1 is a group of the structure ##STR12## R.sup.11 is a bond, alkylene, alkenylene or alkynylene of up to 6 carbon atoms, arylene (for example ##STR13## or mixed arylene-alkylene (for example ##STR14## where n is 1 to 6; PA1 or R.sup.1 is ##STR16## wherein R.sup.19 is aryl or heteroaryl; R.sup.20 is aryl or heteroaryl; PA1 R.sup.2, R.sup.3, R.sup.4 are independently hydrogen, halo, alkyl, haloalkyl, alkenyl, alkoxy, aryloxy, aryl, arylalkyl, alkylmercapto, arylmercapto, cycloalkyl, cycloalkylalkyl, heteroaryl, heteroarylalkyl, hydroxy or haloalkyl; PA1 R.sup.5 is alkyl of at least 2 carbons, alkenyl, alkynyl, aryl, heteroaryl, arylalkyl, heteroarylalkyl, cycloalkyl, cycloalkylalkyl, polycycloalkyl, polycycloalkylalkyl, cycloalkenyl, cycloalkenylalkyl, polycycloalkenyl, polycycloalkenylalkyl, heteroarylcarbonyl, all of the R.sup.5 and R.sup.6 substituents being optionally substituted through available carbon atoms with 1, 2, or 3 groups selected from hydrogen, halo, alkyl, haloalkyl, alkoxy, haloalkoxy, alkenyl, alkynyl, cycloalkyl, cycloalkylalkyl, cycloheteroalkyl, cycloheteroalkylalkyl, aryl, heteroaryl, arylalkyl, arylcycloalkyl, arylalkynyl, aryloxy, aryloxyalkyl, arylalkoxy, arylazo, heteroaryloxo, heteroarylalkyl, heteroarylalkenyl, heteroaryloxy, hydroxy, nitro, cyano, amino, substituted amino (wherein the amino includes 1 or 2 substituents which are alkyl, or aryl or any of the other aryl compounds mentioned in the definitions), thiol, alkylthio, arylthio, heteroarylthio, arylthioalkyl, alkylcarbonyl, arylcarbonyl, arylaminocarbonyl, alkoxycarbonyl, aminocarbonyl, alkynylaminocarbonyl, alkylaminocarbonyl, alkenylaminocarbonyl, alkylcarbonyloxy, arylcarbonyloxy, alkylcarbonylamino, arylcarbonylamino, arylsulfinyl, arylsulfinylalkyl, arylsulfonyl, alkylsulfonyl, arylsulfonylamino; with the proviso that when R.sup.5 is CH.sub.3, R.sup.6 is not H; and where R.sup.5 is phenyl, the phenyl preferably includes an ortho hydrophobic substituent such as alkyl, haloalkyl, aryl, aryloxy or arylalkyl; PA1 R.sup.6 is hydrogen or C.sub.1 -C.sub.4 alkyl or C.sub.1 -C.sub.4 alkenyl; PA1 R.sup.7 is alkyl, aryl or arylalkyl wherein alkyl or the alkyl portion is optionally substituted with oxo; and PA1 including pharmaceutically acceptable salts and anions thereof. PA1 Y is --(CH.sub.2).sub.m -- or ##STR20## wherein m is 2 or 3; R.sup.1 is alkyl, alkenyl, alkynyl, aryl, heteroaryl, arylalkyl wherein alkyl has at least 2 carbons, diarylalkyl, arylalkenyl, diarylalkenyl, arylalkynyl, diarylalkynyl, diarylalkylaryl, heteroarylalkyl wherein alkyl has at least 2 carbons, cycloalkyl, or cycloalkylalkyl wherein alkyl has at least 2 carbons, all optionally substituted through available carbon atoms with 1, 2, 3 or 4 groups selected from halo, haloalkyl, alkyl, alkenyl, alkoxy, aryloxy, aryl, arylalkyl, alkylmercapto, arylmercapto, cycloalkyl, cycloalkylalkyl, heteroaryl, fluorenyl, heteroarylalkyl, hydroxy or oxo; PA1 or R.sup.1 is a fluorenyl-type group of the structure ##STR21## or R.sup.1 is an indenyl-type group of the structure ##STR22## Z.sup.1 and Z.sup.2 are the same or different and are independently a bond, O, S, ##STR23## with the proviso that with respect to B, at least one of Z.sup.1 and Z.sup.2 will be other than a bond; R.sup.11 is a bond, alkylene, alkenylene or alkynylene of up to 10 carbon atoms; arylene or mixed arylene-alkylene; R.sup.12 is hydrogen, alkyl, alkenyl, aryl, haloalkyl, trihaloalkyl, trihaloalkylalkyl, heteroaryl, heteroarylalkyl, arylalkyl, arylalkenyl, cycloalkyl, aryloxy, alkoxy, arylalkoxy or cycloalkylalkyl, with the provisos that PA1 or R.sup.1 is a group of the structure ##STR25## wherein p is 1 to 8 and R.sup.17 and R.sup.18 are each independently H, alkyl, alkenyl, aryl, arylalkyl, heteroaryl, heteroarylalkyl, cycloalkyl or cycloalkylalkyl at least one of R.sup.17 and R.sup.18 being other than H; PA1 or R.sup.1 is a group of the structure ##STR26## wherein R.sup.19 is aryl or heteroaryl; R.sup.20 is aryl or heteroaryl; PA1 R.sup.2, R.sup.3, R.sup.4 are independently hydrogen, halo, alkyl, alkenyl, alkoxy, aryloxy, aryl, arylalkyl, alkylmercapto, arylmercapto, cycloalkyl, cycloalkylalkyl, heteroaryl, heteroarylalkyl, hydroxy or haloalkyl; PA1 R.sup.5 is independently alkyl, alkenyl, alkynyl, aryl, alkoxy, aryloxy, arylalkoxy, heteroaryl, arylalkyl, heteroarylalkyl, cycloalkyl, cycloalkylalkyl, polycycloalkyl, polycycloalkylalkyl, cycloalkenyl, cycloheteroalkyl, heteroaryloxy, cycloalkenylalkyl, polycycloalkenyl, polycycloalkenylalkyl, heteroarylcarbonyl, amino, alkylamino, arylamino, heteroarylamino, cycloalkyloxy, cycloalkylamino, all optionally substituted through available carbon atoms with 1, 2, 3 or 4 groups selected from hydrogen, halo, alkyl, haloalkyl, alkoxy, haloalkoxy, alkenyl, alkynyl, cycloalkyl, cycloalkylalkyl, cycloheteroalkyl, cycloheteroalkylalkyl, aryl, heteroaryl, arylalkyl, arylcycloalkyl, arylalkenyl, arylalkynyl, aryloxy, aryloxyalkyl, arylalkoxy, arylazo, heteroaryloxo, heteroarylalkyl, heteroarylalkenyl, heteroaryloxy, hydroxy, nitro, cyano, amino, substituted amino, thiol, alkylthio, arylthio, heteroarylthio, arylthioalkyl, alkylcarbonyl, arylcarbonyl, arylaminocarbonyl, alkoxycarbonyl, aminocarbonyl, alkynylaminocarbonyl, alkylaminocarbonyl, alkenylaminocarbonyl, alkylcarbonyloxy, arylcarbonyloxy, alkylcarbonylamino, arylcarbonylamino, arylsulfinyl, arylsulfinylalkyl, arylsulfonyl, alkylsulfonyl, arylsulfonylamino, heteroarylcarbonylamino, heteroarylsulfinyl, heteroarylthio, heteroarylsulfonyl, alkylsulfinyl; PA1 R.sup.6 is hydrogen or C.sub.1 -C.sub.4 alkyl or C.sub.1 -C.sub.4 alkenyl; all optionally substituted with 1, 2, 3 or 4 groups which may independently be any of the substituents listed in the definition of R.sup.5 set out above; PA1 R.sup.7 is alkyl, aryl or arylalkyl wherein alkyl by itself or as part of arylalkyl is optionally substituted with oxo ##STR27## are the same or different and are independently selected from heteroaryl containing 5- or 6-ring members; and PA1 X.sup.1 and X.sup.2 are independently selected from H or halo; PA1 x is an integer from 2 to 6; PA1 R.sup.5 is heteroaryl, aryl, heterocycloalkyl or PA1 A is (1) a bond; PA1 B is a fluorenyl-type group of the structure: ##STR34## B is an indenyl-type group of the structure ##STR35## R.sup.x is H, alkyl or aryl; R.sup.1 is alkyl, alkenyl, alkynyl, alkoxyl, (alkyl or aryl).sub.3 Si (where each alkyl or aryl group is independent), cycloalkyl, cycloalkenyl, substituted alkylamino, substituted arylalkylamino, aryl, arylalkyl, arylamino, aryloxy, heteroaryl, heteroarylamino, heteroaryloxy, arylsulfonylamino, heteroarylsulfonylamino, arylthio, arylsulfinyl, arylsulfonyl, alkylthio, alkylsulfinyl, alkylsulfonyl, heteroarylthio, heteroarylsulfinyl, heteroarylsulfonyl, --PO(R.sup.13) (R.sup.14), (where R.sup.13 and R.sup.14 are independently alkyl, aryl, alkoxy, aryloxy, heteroaryl, heteroarylalkyl, heteroaryloxy, heteroarylalkoxy, cycloheteroalkyl, cycloheteroalkylalkyl, cycloheteroalkoxy, or cycloheteroalkylalkoxy); R.sup.1 can also be aminocarbonyl (where the amino may optionally be substituted with one or two aryl, alkyl or heteroaryl groups); cyano, 1,1-(alkoxyl or aryloxy).sub.2 alkyl (where the two aryl or alkyl substituents can be independently defined, or linked to one another to form a ring, such as 1,3-dioxane or 1,3-dioxolane, connected to L.sup.1 (or L.sup.2 in the case of R.sup.2) at the 2-position); 1,3-dioxane or 1,3-dioxolane connected to L.sup.1 (or L.sup.2 in the case of R.sup.2) at the 4-position. PA1 R.sup.2 is the same or different from R.sup.1 and is independently any of the groups set out for R.sup.1, H, polyhaloalkyl (such as CF.sub.3 CH.sub.2, CF.sub.3 CF.sub.2 CH.sub.2 or CF.sub.3) or cycloheteroalkyl, and may be substituted with one to four of any of the groups defined for R.sup.3, or any of the substituents preferred for R.sup.1. PA1 L.sup.1 is a linking group containing from 1 to 10 carbons in a linear chain (including alkylene, alkenylene or alkynylene), which may contain, within the linking chain any of the following: one or two alkenes, one or two alkynes, an oxygen, an amino group optionally substituted with alkyl or aryl, an oxo group; and may be substituted with one to five alkyl or halo groups (preferably F). PA1 L.sup.2 may be the same or different from L.sup.1 and may independently be any of the L.sup.1 groups set out above or a singe bond. PA1 R.sup.3, R.sup.3 ', R.sup.4 and R.sup.4 ' may be the same or different and are independently selected from H, halogen, CF.sub.3, haloalkyl, hydroxy, alkoxy, alkyl, aryl, alkenyl, alkenyloxy, alkynyl, alkynyloxy, alkanoyl, nitro, amino, thiol, alkylthio, alkylsulfinyl, alkylsulfonyl, carboxy, alkoxycarbonyl, aminocarbonyl, alkylcarbonyloxy, alkylcarbonylamino, cycloheteroalkyl, cycloheteroalkylalkyl, cyano, Ar, Ar-alkyl, ArO, Ar-amino, Ar-thio, Ar-sulfinyl, Ar-sulfonyl, Ar-carbonyl, Ar-carbonyloxy or Ar-carbonylamino, wherein Ar is aryl or heteroaryl and Ar may optionally include 1, 2 or 3 additional rings fused to Ar; PA1 R.sup.3a and R.sup.3b are the same or different and are independently any of the R.sup.3 groups except hydroxy, nitro, amino or thio; ##STR36## are the same or different and independently represent a 5 or 6 membered heteroaryl ring which may contain 1, 2, 3 or 4 heteroatoms in the ring which are independently N, S or O; and including N-oxides. PA1 X (in the fluorenyl type ring) is a bond, or is one of the following groups: ##STR37## wherein Y is O, N--R.sup.6 or S; PA1 n' is 0, 1 or 2; PA1 R.sup.7 and R.sup.8 are the same or different and are independently H, alkyl, aryl, halogen, --O--R.sup.12, or PA1 R.sup.7 and R.sup.8 together can be oxygen to form a ketone; PA1 R.sup.9, R.sup.10, R.sup.9' and R.sup.10 ' are the same or different and are independently H, lower alkyl, aryl or --O--R.sup.11 ; PA1 R.sup.9 " and R.sup.10 " are the same or different and are independently H, lower alkyl, aryl, halogen or --O---R.sup.11 ; PA1 R.sup.11 is alky or aryl; PA1 R.sup.12 is H, alkyl or aryl. PA1 (a) when R.sup.1 is unsubstituted alkyl or unsubstituted arylalkyl, L.sup.1 cannot contain amino; PA1 (b) when R.sup.1 is alkyl, L.sup.1 cannot contain amino and oxo in adjacent positions (to form an amido group); PA1 (c) when R.sup.2 L.sup.2 A-- is H.sub.2 N--, R.sup.1 L.sup.1 cannot contain amino; PA1 (d) when R.sup.1 is cyano, L.sup.1 must have more than 2 carbons; PA1 (e) R.sup.1 L.sup.1 must contain at least 3 carbons. PA1 R is H, alkyl, alkoxy, alkenyl, alkynyl, aryl, halo, heteroaryl, cycloheteroalkyl, heteroarylalkyl, cycloalkyl or cycloalkenyl, with the proviso that R cannot be alkoxy or halo when --- is a single bond; PA1 B is a fluorenyl-type group of the structure: ##STR42## B is an indenyl-type group of the structure ##STR43## R.sup.1 is alkyl, alkenyl, alkynyl, alkoxyl, (alkyl or aryl).sub.3 Si (where each alkyl or aryl group is independent), cycloalkyl, cycloalkenyl, substituted alkylamino, substituted arylalkylamino, aryl, arylalkyl, arylamino, aryloxy, hydroxy, amino, heteroaryl, heteroarylamino, heteroaryloxy, arylsulfonylamino, heteroarylsulfonylamino, arylthio, arylsulfinyl, arylsulfonyl, alkylthio, alkylsulfinyl, alkylsulfonyl, heteroarylthio, heteroarylsulfinyl, heteroarylsulfonyl, cycloheteroalkyl, cycloheteroalkylalkyl, --PO(R.sup.13) (R.sup.14), (where R.sup.13 and R.sup.14 are independently alkyl, aryl, alkoxy, aryloxy, heteroaryl, heteroarylalkyl, heteroaryloxy, heteroarylalkoxy, cycloheteroalkyl, cycloheteroalkylalkyl, cycloheteroalkoxy, or cycloheteroalkylalkoxy); R.sup.1 can also be carbonylamino or aminocarbonyl (where the amino may optionally be substituted with one or two aryl, alkyl or heteroaryl groups); cyano, 1,1-(alkoxyl or aryloxy).sub.2 alkyl (where the two aryl or alkyl substituents can be independently defined, or linked to one another to form a ring, such as 1,3-dioxane or 1,3-dioxolane, connected to L.sup.1 at the 2, 4, 5, or 6 position). PA1 R.sup.1 may be substituted with the following preferred substituents: alkylcarbonylamino, cycloalkylcarbonylamino, arylcarbonylamino, heteroarylcarbonylamino, alkoxycarbonylamino, aryloxycarbonylamino, heteroaryloxylcarbonylamino, uriedo (where the uriedo nitrogens may be substituted with alkyl, aryl or heteroaryl), heterocyclylcarbonylamino (where the heterocycle is connected to the carbonyl group via a nitrogen or carbon atom), alkylsulfonylamino, arylsulfonylamino, heteroarylsulfonylamino, ##STR44## where J is: CHR.sup.23, ##STR45## R.sup.23, R.sup.24 and R.sup.25 are independently hydrogen, alkyl, alkenyl, alkynyl, aryl, arylalkyl, heteroaryl, heteroarylalkyl, cycloalkyl, or cycloalkylalkyl; PA1 L.sup.1 is a linking group containing from 1 to 10 carbons in a linear chain (including alkylene, alkenylene or alkynylene), which may contain, within the linking chain any of the following: one or two alkenes, one or two alkynes, an oxygen, an amino group optionally substituted with alkyl or aryl, an oxo group; and may be substituted with one to five alkyl or halo groups (preferably F). PA1 R.sup.3, R.sup.3 ', R.sup.4 and R.sup.4 ' may be the same or different and are independently selected from H, halogen, CF.sub.3, haloalkyl, hydroxy, alkoxy, alkyl, aryl, alkenyl, alkenyloxy, alkynyl, alkynyloxy, alkanoyl, nitro, amino, thiol, alkylthio, alkylsulfinyl, alkylsulfonyl, carboxy, alkoxycarbonyl, aminocarbonyl, alkylcarbonyloxy, alkylcarbonylamino, cycloheteroalkyl, cycloheteroalkylalkyl, cyano, Ar, Ar-alkyl, ArO, Ar-amino, Ar-thio, Ar-sulfinyl, Ar-sulfonyl, Ar-carbonyl, Ar-carbonyloxy or Ar-carbonylamino, wherein Ar is aryl or heteroaryl and Ar may optionally include 1, 2 or 3 additional rings fused to Ar; PA1 R.sup.3a and R.sup.3b are the same or different and are independently any of the R.sup.3 groups; ##STR46## are the same or different and independently represent a 5 or 6 membered heteroaryl ring which may contain 1, 2, 3 or 4 heteroatoms in the ring which are independently N, S or O; and including N-oxides. PA1 X (in the fluorenyl type ring) is a bond, or is one of the following groups: ##STR47## wherein Y is O, N--R.sup.6 or S; PA1 n is 0, 1 or 2; PA1 R.sup.7 and R.sup.8 are the same or different and are independently H, alkyl, aryl, halogen, --O--R.sup.12, or PA1 R.sup.7 and R.sup.8 together can be oxygen to form a ketone; PA1 R.sup.9, R.sup.10, R.sup.9 and R.sup.10 are the same or different and are independently H, lower alkyl, aryl or -O-Rll; PA1 R.sup.9 " and R.sup.10 " are the same or different and are independently H, lower alkyl, aryl, halogen or --O--R.sup.11 ; PA1 R.sup.11 is alky or aryl; PA1 R.sup.12 is H, alkyl or aryl. PA1 R.sup.1 is aryl, phenyl, heteroaryl, imidazolyl, cycloheteroalkyl, pyridyl, cyclohexyl, PO(R.sup.13) (R.sup.14), heteroarylthio, benzthiazole-2-thio, benzimidazolyl, indolyl, imidazole-2-thio, alkyl, alkenyl or 1,3-dioxan-2-yl, wherein each of the above is optionally substituted; PA1 L.sup.1 is a chain containing 1 to 5 atoms in a linear chain; and A is ##STR78## where Q is S or N-alkyl and R is H or alkyl. PA1 (1) bovine liver microsomes, PA1 (2) HepG.sub.2 cells (human hepatoma cells) or PA1 (3) recombinant human MTP expressed in baculovirus.
R.sup.12 is hydrogen, alkyl, alkenyl, aryl, heteroaryl, haloalkyl, arylalkyl, arylalkenyl, cycloalkyl, aryloxy, alkoxy, arylalkoxy, heteroarylalkyl or cycloalkylalkyl;
Z is a bond, O, S, N-alkyl, N-aryl, or alkylene or alkenylene of from 1 to 5 carbon atoms; PA2 R.sup.13, R.sup.14, R.sup.15, and R.sup.16 are independently hydrogen, alkyl, halo, haloalkyl, aryl, cycloalkyl, cycloheteroalkyl, alkenyl, alkynyl, hydroxy, alkoxy, nitro, amino, thio, alkylsulfonyl, arylsulfonyl, alkylthio, arylthio, carboxy, aminocarbonyl, alkylcarbonyloxy, alkylcarbonylamino, arylalkyl, heteroaryl, heteroarylalkyl, or aryloxy; PA2 or R.sup.1 is ##STR15## wherein p is 1 to 8 and R.sup.17 and R.sup.18 are each independently H, alkyl, alkenyl, aryl, arylalkyl, heteroaryl, heteroarylalkyl, cycloalkyl or cycloalkylalkyl, at least one of R.sup.17 and R.sup.18 being other than H; PA2 R.sup.21 is H, alkyl, aryl, alkylaryl, arylalkyl, aryloxy, arylalkoxy, heteroaryl, heteroarylalkyl, heteroarylalkoxy, cycloalkyl, cycloalkylalkyl or cycloalkylalkoxy; PA2 (1) when R.sup.12 is H, aryloxy, alkoxy or arylalkoxy, then Z.sup.2 is ##STR24## or a bond and (2) when Z.sup.2 is a bond, R.sup.12 cannot be heteroaryl or heteroarylalkyl; PA2 Z is bond, O, S, N-alkyl, N-aryl, or alkylene or alkenylene from 1 to 5 carbon atoms; R.sup.13, R.sup.14, R.sup.15, and R.sup.16 are independently hydrogen, alkyl, halo, haloalkyl, aryl, cycloalkyl, cycloheteroalkyl, alkenyl, alkynyl, hydroxy, alkoxy, nitro, amino, thio, alkylsulfonyl, arylsulfonyl, alkylthio, arylthio, aminocarbonyl, alkylcarbonyloxy, arylcarbonylamino, alkylcarbonylamino, arylalkyl, heteroaryl, heteroarylalkyl or aryloxy; PA2 R.sup.15a and R.sup.16a are independently hydrogen, alkyl, halo, haloalkyl, aryl, cycloalkyl, cycloheteroalkyl, alkenyl, alkynyl, alkoxy, alkylsulfonyl, arylsulfonyl, alkylthio, arylthio, aminocarbonyl, alkylcarbonyloxy, arylcarbonylamino, alkylcarbonylamino, arylalkyl, heteroaryl, heteroarylalkyl, or aryloxy; PA2 R.sup.21 is H, alkyl, aryl, alkylaryl, arylalkyl, aryloxy, arylalkoxy, heteroaryl, heteroarylalkyl, heteroarylalkoxy, cycloalkyl, cycloalkylalkyl or cycloalkylalkoxy; PA2 N-oxides ##STR28## thereof; and pharmaceutically acceptable salts thereof; with the provisos that where in the first formula X is CH.sub.2, and R.sup.2, R.sup.3 and R.sup.4 are each H, then R.sup.1 will be other than 3,3-diphenylpropyl, and in the fifth formula, where one of R.sup.2, R.sup.3 and R.sup.4 is 6-fluoro, and the others are H, R.sup.7 will be other than 4-(2-methoxyphenyl). PA2 (2) --O--; or PA2 (3) ##STR33## where R.sup.5 is H or lower alkyl or R.sup.5 together with R.sup.2 forms a carbocyclic or heterocyclic ring system containing 4 to 8 members in the ring. PA2 (2) --S--; or PA2 (3) ##STR41## where R.sup.5 and R.sup.5a are the same or different and are H, lower alkyl, aryl, heteroaryl or cycloalkyl; PA2 R.sup.20, R.sup.21, R.sup.22 are independently hydrogen, halo, alkyl, alkenyl, alkoxy, aryloxy, aryl, arylalkyl, alkylmercapto, arylmercapto, cycloalkyl, cycloalkylalkyl, heteroaryl, heteroarylalkyl, hydroxy or haloalkyl; and these preferred substituents may either be directly attached to R.sup.1, or attached via an alkylene chain at an open position. PA2 R is H or alkyl such as methyl; PA2 L.sup.1 is alkylene of 2-5 carbons in the chain; and PA2 R.sup.1 is ##STR82##
In the formula I compounds, where X is CH.sub.2 and R.sup.2 R.sup.3 and R.sup.4 are each H, R.sup.1 will be other than 3,3-diphenylpropyl.
In the formula III compounds, where one of R.sup.2, R.sup.3 and R.sup.4 is 6-fluoro, and the others are H, R.sup.7 will be other than 4-O-methoxyphenyl.
U.S. application Ser. No. 472,067, filed Jun. 6, 1995 (file DC21e) discloses compounds of the structure ##STR17## where Q is ##STR18## X is: CHR.sup.8, ##STR19## R.sup.8, R.sup.9 and R.sup.10 are independently hydrogen, alkyl, alkenyl, alkynyl, aryl, arylalkyl, heteroaryl, heteroarylalkyl, cycloalkyl, or cycloalkylalkyl;
U.S. application Ser. No. 548,811, filed Jan. 11, 1996 (file DC21h), discloses compounds having the structure ##STR29## including the piperidine N-oxide thereof or a pharmaceutically acceptable salt thereof, wherein Z is a bond, O or S;
cycloalkyl, each R.sup.5 group being optionally substituted with 1, 2, 3 or 4 substituents which may be the same or different.
U.S. Provisional Application Ser. No. 60/017,253, filed May 10, 1996 (file HX82*) discloses compounds which are inhibitors of MTP and have the structure ##STR30## where W is H, H or O; and X, Q, R.sup.1, R.sup.2, R.sup.3, R.sup.4, R.sup.5 and R.sup.6 are essentially as defined in U.S. application Ser. No. 10 472,067 (file DC21e).
U.S. Provisional Application Ser. No. 60/017,254, filed May 10, 1996 (file HX84*) discloses compounds which are inhibitors of MTP and have the structure ##STR31## where n is 0 or 1 and X, Q, R.sup.1, R.sup.2, R.sup.3, R.sup.4, R.sup.5 and R.sup.6 are essentially as defined in U.S. application Ser. No. 20 472,067 (file DC21e).
U.S. Provisional Application Ser. No. 60/017,224 (file HX79a*) filed May 7, 1996, discloses compounds which are inhibitors of MTP and have the structure ##STR32## including pharmaceutically acceptable salts thereof, wherein q is 0, 1 or 2;
The R.sup.1 group may have from one to four substituents, which can be any of the R.sup.3 groups or R.sup.1 groups, and certain preferred R.sup.1 substituents as disclosed.
R.sup.6 is H, lower alkyl, aryl, --C(O)--R.sup.11 or --C(O)--O--R.sup.11 ;
The following provisos apply to formula I compounds:
With respect to compounds of the invention IA and IB, R.sup.2 L.sup.2 cannot have an Oor N atom directly attached to S=(O).sub.q or CR.sup.x (OH), and for IA, R.sup.2 L.sup.2 cannot be H.
With respect to compounds of the invention I, IA and IB, where R.sup.1 is cycloheteroalkyl, R.sup.1 is exclusive of 1-piperidinyl, 1-pyrrolidinyl, 1-azetidinyl or 1-(2-oxo-pyrrolidinyl).

Heterocyclic inhibitors of microsomal triglyceride transfer protein and method


An apparatus and system are disclosed for cooling of heat producing components. The apparatus may include a mounting plate rigidly connected with a top surface of a circuit board, the mounting plate positioned above a heat producing circuit board component, and a heat sink having first and second ends. The heat sink is configured to interface with the mounting plate in order to provide a downward force on the heat producing circuit board component. The apparatus also includes at least one bellows device coupling a heat transfer tip with the first end of the heat sink, wherein the bellows device is configured to transfer the downward force from the mounting plate to a top surface of the heat producing component and maintain the heat transfer tip in compliance with the plane of the top surface of the heat producing component. The system includes a circuit board, a plurality of heat producing circuit board components, and the described apparatus.

1. Field of the Invention
This invention relates to removing excess heat from a component and more particularly relates to removing excess heat from a circuit board component by conducting heat to an area with excess cooling capacity.
2. Description of the Related Art
In computers with limited space requirements, cooling of components is a critical part of the design. Component cooling is balanced with other design constraints such as space requirements and connectivity requirements. As a result, a heat sensitive component, such as a hard drive or processor, may be located such that cooling of the component is compromised. A heat sensitive component may be, but is not limited to, any component that would benefit by removing heat beyond the heat removed through typical convection or forced air cooling.
A heat sensitive component with inadequate cooling may run less efficiently. A heat sensitive component with inadequate cooling may also fail prematurely. Premature component failure and inefficient operation reduce the reliability and marketability of a computer and may result in reduced profits for the computer seller.
Typical methods of cooling using forced air or convection may not adequately cool heat sensitive components. Forced air cooling using directional channels or vanes may not be effective due to space constraints or cost. Adding more cooling through larger fans or additional fans may not be an effective solution due to long-term energy costs, reduced reliability, noise considerations, or the like.
Adding a heat sink to a heat sensitive component may not be possible due to space constraints. Adding a heat sink to a heat sensitive component also may not be effective if the heat sensitive component is located where cooling capacity is not adequate to make the addition of a heat sink effective.
The above mentioned problems associated with cooling a heat sensitive component are compounded in computers or other electronic equipment with extreme space constraints such as rack-mounted blade servers, lap-top computers, and the like. In addition, low energy use constraints in computers such as lap-top computers makes solving cooling problems for heat sensitive components through increased fan size or additional fans an unattractive solution.
Another solution to the problem of cooling heat producing components is the use of a heat pipe. Heat pipes are simple mechanical devices that transfer heat from one point to another. Typically heat pipes include a sealed heat chamber that contains a vaporizable fluid. As a heat producing component heats the heat pipe, the fluid vaporizes, releasing heat from the surface of the fluid. The vaporized fluid moves to a separate area where the heat is transferred to a cooling device such as a heat sink. The vapor cools, condenses, and gravity pulls the condensed vapor back to the heat source.
Heat pipes have proven to be a very effective method of cooling heat producing components on a circuit board. Heat pipes are especially effective with central processing units (CPUs) and graphics processing units (GPUs). A factor in the efficiency of the heat pipe is the ability to provide a sufficient downward force on a heat transfer tip that engages the heat producing component. In order to transfer heat effectively, the heat transfer tip must maintain contact with the heat producing component. The downward force ensures sufficient contact.
Generally, the downward force is provided by a plurality of fastening mechanisms, such as screws, that couple the heat pipe to the circuit board. One problem that arises, however, is introduced by the fastening mechanisms and causes the heat transfer tip to not fully engage the heat producing component. Often times, one fastening mechanisms is attached with more torque than another causing the heat transfer tip to not maintain a parallel relationship with the heat producing component, but rather have a gap. Because air is a horrible conductor of heat, this gap greatly reduces the efficiency of the heat pipe.
From the foregoing discussion, it should be apparent that a need exists for an apparatus and system to conduct heat from a heat producing component to an area in a computer with excess cooling capacity. Beneficially, such an apparatus and system would maintain sufficient contact of the heat transfer tip and the heat producing component.

Apparatus and system for cooling heat producing components

International Business Machines Corporation


A unibody heater module is disclosed having an end cap and a base, wherein the base of the heater canister is filled with a solid-state reaction mixture. Twist-to-activate heater starting functionality is embedded directly into the unibody heater module. A reactive starting pellet is embedded into the upper surface of the compacted solid-state reaction mix. The plunger head of a firing pin passing through the center of an internal metal spacer is held a small distance away from the upper surface of the starting pellet. When the user activated CUI is rotated, the base of a cam pushes on one end of a firing pin protruding through a small hole in the end cap of the unibody heater module. The opposite end of the plunger plunges into the starter pellet so as to initiate heater activation in response to operation of the CUI by the user.

Modular Compact heating elements that assemble into containers to heat food and beverage contents are well known in the art and have been disclosed in various patents, including patents issued to one or more of the inventors named in the present application, including, for example, U.S. Pat. No. 8,864,924 titled "Solid-State Thermite Composition Based Heating Device;" U.S. Pat. No. 9,055,841 titled "Package Heating Apparatus;" U.S. Pat. No. 8,555,870 titled "Package Heating Device and Chemical Compositions for Use Therewith;" U.S. Pat. No. 9,500,389 titled "Thermally Regulated Self Heating Containers;" and U.S. Pat. No. 10,058,209 titled "High Efficiency Self-Heating Containers."
The heater elements described in the prior art efficiently store chemical energy in contained solid state chemical reactants and are simply activated by a user to promptly release thermal energy. The thermal energy is transmitted through the wall of an immediately adjacent container to uniformly heat the interior contents. Passive thermal safety mechanisms may be incorporated into the heaters to provide for additional consumer safety.
Various forms of heater module construction, and means of integrating the heaters into functional packaging have been described. For example, U.S. Pat. No. 10,058,209 "High Efficiency Self-Heating Containers," describes a comprehensive self-heating package solution suitable for heating standard two-piece beverage containers configured to be compatible with the multi-faceted needs of fillers, brands, and consumers.
There is a need, however, for a combined unibody heater module that into fitted into a heater housing tube, such that each of these components have mating alignment features that assure a specific preferred relative orientation. Modular components such as this would allow the self-heating functionality to be alternatively integrated into either the lid or the base of a self-heating beverage container package, with a suitable consumer user interface then applied.


A relay is provided that has a base, connecting elements, a magnet system with a coil, a core arranged within the coil, an L-shaped yoke, and a plate-shaped armature, wherein the axis of the coil extends parallel to the first yoke leg, and a second yoke leg is connected to the first end of the core farthest from the base, and wherein the armature is pivoted on the first yoke leg and forms a working air gap with a second end of the core facing the base. A contact system has a contact spring that is fastened to the armature and carries a movable contact, and at least one fixed contact carrier that carries a fixed contact and is anchored in the base. The open end of the first yoke leg is supported on the upper surface of the base with two fork-shaped end sections, while the open end of the second yoke leg is likewise supported on the upper surface of the base by a yoke support parallel to the first yoke leg. The armature is pivoted on a pivot edge formed between the two end sections of the first yoke leg and is fastened to the outer side of the first yoke leg facing away from the coil via a return spring which engages between the end sections.

1. Field of the Invention
The present invention relates to an electromagnetic relay having a base in which connecting elements are anchored, a magnet system with a coil, a core arranged in the coil, an L-shaped yoke, and a plate-shaped armature. A first yoke leg is arranged essentially parallel to a coil axis and a second yoke leg is connected to a first end of the core. The armature is pivoted on the first yoke leg and forms a working air gap with the second end of the core. The relay further includes a contact system with a contact spring that carries a movable contact and is fastened to the armature, as well as at least one fixed contact carrier that carries a fixed contact and is anchored in the base.
2. Description of the Background Art
Conventional relays of this type are distinguished by compact construction and are used, e.g., to switch large currents, as for example in low-voltage circuits in automobiles and the like. In known relays of this type, it is frequently only possible through great effort to securely fasten the magnet system to the base and set the return force of the return spring.


A logic circuit is provided with a first differential transistor pair (Q1, Q2) operable in response to a data signal input thereto; a current source for supplying a current to the first differential transistor pair (Q1, Q2); a first transistor (Q5) connected between a common emitter of the first differential transistor pair (Q1, Q2) and the current source, and operable in response to a clock signal input thereto; and a first potential stabilizing circuit (30a) connected to a first junction between the common emitter of the first differential transistor pair (Q1, Q2) and a collector of the first transistor (Q5), for stabilizing a potential at said first junction.

Latch circuits are used as basic component circuits of logic circuits in many semiconductor integrated circuits. An arrangement of a conventional latch circuit will be described below.
FIG. 1 is a diagram showing an arrangement of a conventional latch circuit. The latch circuit shown in FIG. 1 is used in applications which require high-speed operation. In the description which follows, bipolar transistors are used as active devices.
As shown in FIG. 1, the latch circuit generally employs a differential logic circuit comprising differential transistor pairs (hereinafter simply referred to as "differential pairs") for reading and holding data, a differential transistor pair for being supplied with a clock signal and serving to switch currents supplied to the differential transistor pairs in a higher stage, and a transistor as a constant-current source in a lower stage. The circuit arrangement will hereinafter be described in detail below.
The latch circuit has first differential pair (Q1, Q2) for reading a data signal, second differential pair (Q3, Q4) for holding the data signal, third differential pair (Q5, Q6) connected to common emitter point P1 of the first differential pair and common emitter point P2 of the second differential pair, for being supplied with complementary clock signals, and transistor Q7 serving as a constant-current source.
Reference characters 1a, 1b represent data input terminals to which the data signal is supplied and which are connected to the bases of first differential pair Q1, Q2. Reference characters 2a, 2b represent clock input terminals to which the clock signal is supplied and which are connected to the bases of third differential pair Q5, Q6. Reference characters 3a, 3b represent data output terminals for outputting a data signal, which are connected respectively to collectors of first differential pair Q1, Q2 and respectively collectors of second differential pair Q3, Q4. Data output terminals 3a, 3b are connected respectively to the bases of second differential pair Q3, Q4. Reference character 5 represents a high-potential power supply terminal for being supplied with potential Vcc. The collectors of first differential pair Q1, Q2 are connected to high-potential power supply terminal 5 respectively through resistors R1, R2. Reference character 6 represents a low-potential power supply terminal for being supplied with potential Vee. Transistor Q7 has an emitter connected to low-potential power supply terminal 6.
A master-slave flip-flop circuit employing the latch circuit shown in FIG. 1 will be described below. An example of the master-slave flip-flop circuit is shown in FIG. 4 of JP-A No. H05-48402.
FIG. 2 shows an example of the master-slave flip-flop circuit employing the conventional latch circuit shown in FIG. 1. Those parts of the master-slave flip-flop circuit which are identical to those of the latch circuit shown in FIG. 1 are denoted by identical reference characters.
As shown in FIG. 2, a master circuit has the latch circuit shown in FIG. 1 and transistors Q15, Q16. The collector of transistor Q1 of the first differential pair and the collector of transistor Q3 of the second differential pair are connected to the base of transistor Q15. The collector of transistor Q2 of the first differential pair and the collector of transistor Q4 of the second differential pair are connected to the base of transistor Q16. Transistors Q15, Q16 have respective collectors connected to high-potential power supply terminal 5, and respective emitters connected to low-potential power supply terminal 6 through respective resistors R7, R8. Junction 4a between transistor Q15 and resistor R7 is connected to the base of transistor Q4 of the second differential pair, and junction 4b between transistor Q16 and resistor R8 is connected to the base of transistor Q3 of the second differential pair. Junctions 4a, 4b serve as data output terminals of the master circuit. Transistor Q7 has an emitter connected to low-potential power supply terminal 6 through resistor R3.
A slave circuit is of an arrangement identical to the master circuit. As shown in FIG. 2, the slave circuit has fourth differential pair (Q8, Q9) for reading a data signal, fifth differential pair (Q10, Q11) for holding the data signal, sixth differential pair (Q12, Q13) connected to common emitter point P3 of the fourth differential pair and common emitter point P4 of the fifth differential pair, for being supplied with complementary clock signals, transistor Q14 serving as a constant-current source, and transistors Q17, Q18.
The collector of transistor Q8 of the fourth differential pair and the collector of transistor Q10 of the fifth differential pair are connected to the base of transistor Q17. The collector of transistor Q9 of the fourth differential pair and the collector of transistor Q11 of the fifth differential pair are connected to the base of transistor Q18. Transistors Q17, Q18 have respective collectors connected to high-potential power supply terminal 5, and respective emitters connected to low-potential power supply terminal 6 through respective resistors R9, R10.
A junction between transistor Q17 and resistor R9 and a junction between transistor Q18 and resistor R10 are connected respectively to data output terminals 3a, 3b of the slave circuit. Data output terminals 3a, 3b are connected to the respective bases of transistors Q10, Q11 of the fifth differential pair. Junctions 4a, 4b of the master circuit serve as data input terminals of the slave circuit and are connected to the respective bases of transistors Q8, Q9 of the fourth differential pair. Data output terminals 3a, 3b and data output terminals 4a, 4b serve as the output terminals of flip-flop circuit sections.
Operation of the master-slave flip-flop is the same operation of the conventional master-slave flip-flop and will not be described below.

Logic circuit for use in a latch circuit and a data reading circuit or the like which includes such a latch circuit


Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. In other aspects, ESD circuitry is provided at corners of the IC layout and optionally within selected I/O slots. Decap circuitry is provided at an outer edge of the IC layout and is scalable in order to meet different requirements.

Field of the Invention
The present invention relates to I/O circuitry for integrated circuits.
State of the Art
Complex integrated circuits are often I/O-limited, meaning that the die size is increased beyond what would otherwise be required in order to accommodate the required number of I/Os. For integrated circuits generally, and especially I/O-limited integrated circuits, design of the I/O portion of the integrated circuit is often laborious and time-consuming. At the same time, short product design cycles call for short integrated circuit design cycles. Reducing design time and labor for integrated circuits, including complex, I/O limited integrated circuits, requires new approaches.
FIG. 1 shows a top view of the layout of a portion 300 of I/O circuitry of an example IC die, according to the prior art. I/O circuitry 300 could run along any edge of the periphery of an IC die. The I/O circuitry 300 uses two concentric rows of bond pads, i.e., inner pad row 1 and outer pad row 2. The pad placements along the peripheral edge are offset between the two rows. During the wire bonding process, all pads along the outer row 2 are typically wire bonded before any bond pads on inner row 1 are wire bonded (or vice versa). This arrangement enables I/O pads to be packed more densely without exceeding the capabilities (minimum pad pitch) of wire bonding equipment.
Bond pads in FIG. 1 include signal bond pads (SIG) 201 and power/ground bond pads. Power/ground bond pads in turn include power bond pads (VCC CORE) 204 for a core logic portion of the integrated circuit, ground bond pads (VSS CORE) 205 for the core logic portion of the integrated circuit, power bond pads (VCC I/O) 202 for the I/O portion of the integrated circuit, and ground bond pads (VSS I/O) 203 for the I/O portion of the integrated circuit. Each of the foregoing pads is coupled to a corresponding one of I/O cells 130, including differentiated signal I/O cells (SIG I/O) 211, core logic power I/O cells (VCC CORE) 214, core logic ground cells (VSS CORE) 215, I/O power cells (VCC I/O) 212, and I/O ground cells (VSS I/O) 213. A primary function of the four power/ground cells 130 is to provide electrostatic discharge (ESD) protection to the associated power/ground pads and supply power and ground to a group of I/O cells (SIG I/O) 211.
Each of the cells 130 occupies an I/O slot, the I/O slots being spaced apart according to a specified pitch. For a complex integrated circuit, roughly 30% of the I/O pads will typically be power/ground pads, and a corresponding proportion of the cells 130 will be power/ground cells.

Flexible, space-efficient I/O circuitry for integrated circuits


A terminal connection portion has a plate shape extending in an axial direction and has a constant width dimension. A terminal front end edge thereof has a convex shape at a front end side in the axial direction and has a circular-arc shape with a radius from 0.5 times to 0.8 times the width dimension, and is arranged in the center between a first pad side edge and a second pad side edge, on an electrode pad. A brazing material portion has a form spreading to a front end side in the axial direction away from the terminal connection portion. A brazing material front end edge which is a front end edge of the brazing material portion has a convex and circular-arc shape at the front end side in the axial direction, and is configured to be apart from a pad front end edge.

1. Field of the Invention
The present invention relates to a ceramic heater and a gas sensor including the same.
2. Description of the Related Art
A gas sensor has been known which is attached to an exhaust pipe of vehicles, for example, and detects specific gas components contained in a detected gas such as an exhaust gas. A specific form of the gas sensor, for example, includes a detecting element detecting specific gas components in the detected gas and extending in an axial direction, and a ceramic heater heating the detecting element (for example, refer to JP-A-2010-120840).
In JP-A-2010-120840 and JP-A-2011-247657, the ceramic heater has a bar shape extending in an axial direction and includes a ceramic base body having a heater element in its interior, an electrode pad disposed on a surface of the ceramic base body and conductive with the heater element, a heater terminal member electrically connected to an external circuit, and a brazing material portion (bonding portion) bonding a terminal connection portion of the heater terminal member and the electrode pad.
In addition, in JP-A-2010-120840 and JP-A-2011-247657, the gas sensor includes an inner terminal member (contact terminal member) which is electrically connected to an inner electrode disposed in the detecting element and has a negative potential relative to the electrode pad. The contact terminal member contacts and holds the ceramic base body at a front end side thereof in the axial direction away from the electrode pad.
3. Problems to be Solved by the Invention
In the gas sensor disclosed in JP-A-2010-120840, the brazing material portion reaches the front end edge of the electrode pad. Thus, if atmospheric moisture deposits on the surface of the brazing material portion and the ceramic base body, migration may occur on the surface of the ceramic base body. In this case, metal contained in the brazing material is caused to move from the brazing material portion to the contact terminal member (portion coming into contact with the ceramic base body). As a result, a short circuit may arise between the brazing material portion and the contact terminal member.
In addition, in the gas sensor disclosed in JP-A-2011-247657, the terminal connection portion of the heater terminal member has a plate shape extending in the axial direction having a constant width dimension, and the front end edge thereof (front end edge of the terminal) has a linear shape (straight line orthogonal to the axis). In the case of using the terminal connection portion having this form, in a step of bonding the electrode pad and the terminal connection portion using the brazing material, the brazing material is wetly spread from the front end edge of the terminal to the front end side in the axial direction. However, a degree of wet spreading at one side is sometimes larger than at the other side, between a first pad side edge of the electrode pad (one of two pad side edges extending parallel to the axial direction) and a second pad side edge (the other of the above-described pad side edges). Consequently, the brazing material is likely to reach the front end edge of the electrode pad at one side. Therefore, as described above, migration may occur in which metal contained in the brazing material is caused to move and thereby a short circuit may arise between the brazing material portion and the contact terminal member.
In particular, when using a brazing material containing Ag, migration is likely to occur between the brazing material portion and the contact terminal member.


An on-chip split transaction system bus having separate address and data portions is provided. The system bus contains separate address and data buses for initiating and tracking out-of-order transactions on either or both of the address or data portions of the bus. The system bus provides communication via a bus interface that includes split transaction tracking and control to establish transaction ID""s for each transaction initiated by the bus interface, and to determine whether data appearing on the data portion of the system bus is associated with one of its pending transactions. The bus interface also contains flow control logic to determine whether devices that are to be read from, or written to, by the bus interface, have resources (buffers) available to respond to the transactions. If the resources are available, the flow control logic allows the transactions to proceed, and adjusts its counters to reflect the use of the resources. If the resources are not available, the flow control logic causes the transactions to wait until the resources become available.

This invention relates in general to the field of computer architecture, and more specifically to an on-chip system bus to allow communication between multiple on-chip devices.
A system bus in a computing system provides a communication channel between computing devices, such as microprocessors, and other devices such as memory, keyboard, monitor, video controllers, sound generation devices, etc. The system bus typically includes data paths for memory addresses, data, and control information. In some instances, a processor multiplexes (i.e., shares) address and data information over the same signal lines, albeit at different times. That is, a processor sends address information out over the address/data pins during a first time period and later uses the same address/data pins to send or receive data. Alternatively, many processors utilize separate signal lines for address and data information.
To better understand what a system bus is as well as the importance of bus interface standards, a general overview of the operation of a typical system bus is provided. Following that, a brief summary of modern system buses is given. Finally, an introduction to some of the needs that are not yet addressed by modern system buses is presented.
In operation, a microprocessor communicates with memory when it needs to fetch an instruction. During execution of that instruction, the microprocessor might be required to read data from memory, or from another external device such as an input/output (I/O) port. And, upon completion of the instruction, the microprocessor might be required to write data to memory, or to another external device. A typical scenario for accessing the memory to obtain the instruction and the data would be similar to the following:
1. The microprocessor presents a memory address for an instruction on the address lines of the system bus, and provides control information on the control lines of the system bus to indicate that the operation is a read.
2. In response to the address and control information being placed on the system bus, the memory places the instruction on the data lines of the system bus, which are then read by the microprocessor. The data is typically placed on the data lines N cycles after the address information has been placed on the address lines, where N is a positive integer and varies depending on the speed of the memory.
3. During execution of the instruction, if data is required, a memory address for the data is placed on the address lines of the system bus, and control information is placed on the control lines of the system bus to indicate a read.
4. Again, the memory places data corresponding to the memory address on the data lines of the system bus.
5. If the instruction needs to write to memory, the memory address for the write is placed on the address lines of the system bus, and control information is placed on the control lines to indicate a write.
6. N cycles after the memory address is presented, the data to be written is placed by the microprocessor on the data lines of the system bus. The memory uses the memory address presented in step 5, and places the data on the data lines into memory at that address.
One skilled in the art will appreciate from the above that the system bus provides the necessary physical interface between a computing device, and other devices (such as memory) that are external to it. The physical interface for a given system bus is typically defined in terms of the number of signal lines allocated to address, data, and control information, as well as the electrical characteristics of each of the signal lines. That is, typical system buses may provide anywhere from 20 address lines (for accessing up to 1 million different memory addresses), up to 32 address lines (for accessing up to 4 billion different memory addresses), or more. In addition, the size of the data portion of the system bus may vary from 8-bits in width, up to 128 bits in width, or more. One skilled in the art will also appreciate that the wider the data width, the more information can be transferred at the same time.
From an electrical standpoint, system buses typically operate in the range of 0 volts to 5 volts, although other ranges are possible. Furthermore, particular bus interfaces define for each signal line on the bus, what logical state is meant for a particular voltage level. For example, the bus interface defines whether a logical 1 is provided by a voltage level of 5 volts, 0 volts (active low), or something else.
A system bus interface also provides the protocol necessary for communicating between devices. That is, the protocol defines when address, data, and control signals must appear on the system bus, in relation to each other. For example, in the illustration presented above, address information appears in parallel with control information. At some time later, data information is presented by the microprocessor, or is provided by memory.
A system bus protocol may also define how long signals must appear on the system bus. For example, a system bus protocol might require that address information appear on the bus for at least 2 clock cycles. And, the protocol might require that data must appear on the bus later than 2 cycles after the address information is removed. One skilled in the art will appreciate that such protocol definitions are specific to particular types of system buses.
With the above general background on system buses, a brief overview will now be provided for modern system bus interfaces.
The most common system bus interface in the world today is the Industry Standard Architecture (ISA) bus. In 1984, with the introduction of the Intel 80286 microprocessor, a new bus was required that could utilize the full 16-bit data bus of that processor. IBM decided to develop a new bus interface that could accept the data width of the 80286, and allow them to add more address and control signals to the previously designed PC bus. However, to allow the bus to remain backward compatible with devices designed for the PC bus, compromises were made. The resultant ISA bus was therefore something of a hybrid, offering advantages of increased speed (8 megahertz), increased data lines (16-bit), and increased address lines (24-bit), as well as additional interrupt and control lines, while at the same time separating the additional lines on a supplementary connector. This allowed legacy expansion cards with 8-bit data interface to be used, while adding additional data and address pins on the supplementary connector. The result was an 8-MHz bus clock, with a 16-bit data path, and 24 address lines to address 16 megabytes of memory. However, the number of I/O ports was still limited to 1,024 due to compatibility concerns with PC bus expansion boards.
As processor speeds increased, Intel separated the processor from the ISA bus to allow faster communication between the processor and memory, while still providing communication with slower ISA devices. The processor bus that is presently offered is referred to as either the host bus, or the Pentium bus. A typical implementation of the Pentium bus provides address, data and control signals between a processor and a memory controller, and operates at approximately 100 MHz. Also attached to this host bus is a chip, or chip-set that provides an interface between the host bus, and slower buses such as PCI and ISA. For a more thorough discussion of various PC bus architectures, the reader is directed to http://www.pcguide.com/ref/mbsys/buses/index.htm.
In each of the above-mentioned buses, the protocol associted with performing a read or write is essentially the same. That is, a processor first places address and control information on the host bus. At some later time, data is presented on the data lines of the bus, either by the processor (if the transaction is a write), or by memory (if the transaction is a read). In environments where there is only 1 device capable of initiating bus activity (a uni-master environment), such a protocol is generally sufficient. However, in environments where multiple processors compete for access to shared devices, arbitration is needed to assign time on the bus to the multiple processors.
For example, if there are two processors on a host bus, both competing for access to memory, typical systems provide an arbitration protocol between the devices to establish which one has the right to begin. On the Pentium bus, a processor requests access to the bus by asserting a xe2x80x9cbus requestxe2x80x9d signal. If the processor receives a xe2x80x9cgrantxe2x80x9d signal either from another processor, or from an external arbitration device, then it begins a transaction by placing address and control information on the bus. When it receives (or writes) data on the bus, it relinquishes control of the bus to the next processor. If another processor required access to the bus during the transaction, it would have to wait until the entire transaction (including the address and data portions of the transaction) completed. In many situations, it is undesirable to deny a processor access to a bus pending completion of an entire transaction by another processor.
One solution to this problem has been to separate the address and data bus portions of the system bus, and to provide separate arbitration for gaining access to each of the buses. For example, rather than requesting access (or master) of the system bus, a first processor may request access to the address bus. If the address bus is available, the first processor can present address information on the address lines, even though a second processor is bus master of the data bus. Access to the data bus by the first processor operates in a similar fashion.
Thus, by separating arbitration for accessing the address bus from that of the data bus, multiple masters are allowed to utilize portions of the system bus simultaneously. An example of an environment that provides for such split address and data buses is the system bus for the PowerPC 603, manufactured by Motorola.
One skilled in the art should appreciate that when the address and data portions of a bus are separate, and are shared by multiple bus masters, a system must be developed for associating a data transaction with an address transaction. That is, if the address and data buses are truly separate, data may appear on the data bus many clock cycles after the address information was presented. In fact, in buses having split transactions, it is possible for two or more masters to present address information on the address bus long before data appears in response to the first address. In such an environment, it is essential to associate data on the data bus with either its associated address, or with a particular transaction.
In one environment, a transaction ID has been developed to tag all requests with a particular ID. When any data is presented on the data bus, the ID associated with the transaction is also placed on the data bus. This allows any processor on the bus to know whether the data being presented is associated with one of its outstanding transactions, and if so, which one. An example of using transaction ID""s to track multiple transactions in a split address/data bus environment is the R10000 microprocessor developed by Silicon Graphics, Inc. (now known as xe2x80x9cSGIxe2x80x9d).
Each of the above-described buses utilizes a protocol that establishes communication between a processor, and devices that are external to it. However, with modern improvements in fabrication technology, it is now possible to place some of the devices that have heretofore been external to the processor, on the same piece of silicon as the processor. This is most commonly seen in the embedded microprocessor world where devices such as SRAM, memory control, serial connectivity, etc., are fabricated on the same silicon as the processing device. However, in such embedded processors, the communication between the processing device, and the other devices on the chip, is typically accomplished via a proprietary interface between the processing device and those devices. That is, the interface between the devices and the core processor is specific to a particular implementation, rather than a universal interface for which other devices may be designed. As more and more devices are being incorporated onto the same silicon, it is becoming important to develop a scalable on-chip interface to allow communication between the different on-chip devices.
The above provides a general understanding of the progression of system buses, from multiplexed address/data lines in a single master environment, to on-chip proprietary interfaces. However, existing on-chip buses are designed for low-end systems that do not have high performance needs. In addition, the existing on-chip buses are not scalable.
Therefore, what is needed is an on-chip system bus interface that prescribes a uniform protocol for allowing computing devices to be designed, whether they are in a single master or multi-master environment. That is, the system bus interface must be scalable, to support low-bandwidth single processor solutions, to high-bandwidth multiple processor solutions.
Further, what is needed is an on-chip system bus interface that is flexible. That is, a system bus is needed that simultaneously supports multiple devices having varying bandwidth requirements. The system bus must be capable of supporting both real-time and non-real-time data demands.
Moreover, since on-chip embedded systems tend to span a wide range of complexity, from low-end solutions such as a cell phone, to high-end solutions such as a set-top box, the bus interface must enable different implementations of varying complexity.
The present invention provides an innovative on-chip system bus and bus interface that separates the address and data portions of transactions on a split transaction bus. By separating the address and data portions of a transaction and presenting them on separate buses, multiple transactions, by either a single master, or multiple masters, can exist concurrently, without requiring that a first transaction be completed before beginning a second transaction. Such separation of transactions on a split transaction bus also allows for out-of-order completion of transactions.
In an embodiment of the present invention, an on-chip system bus includes a bus interface for interfacing a master device to a slave via the system bus. The master device includes split transaction tracking and control, and flow control logic. The split transaction tracking and control establishes transaction ID""s for transactions to be present ed on the system bus where the transactions have split address and data portions. The transaction ID""s have master device ID""s and transaction tags for uniquely identifying all pending transactions on the system bus. The transaction ID""s are presented on the system bus commensurate with presentation of an address. Devices responding with data provide the associated transaction ID along with the data. The flow control logic determines whether devices that are being read from, or written to, by transactions, have adequate resources (buffers) to respond to the transactions. If the flow control logic determines that adequate resources are available, the transactions are presented to the system bus. If the flow control logic determines that adequate resources are not available, the transactions are held until the resources become available. By providing such flow control, there is no need to retry any transactions resulting from inadequate resources.
In another aspect, the present invention provides a computer program product on a computer useable medium. Within the medium are a first computer readable program code and a second computer readable program code. The first code provides split transaction tracking and control to establish transaction ID""s for transactions to be presented on an on-chip system bus having address and data buses. The second code provides flow control logic to determine whether devices being read from, or written to, by the transactions, have buffers currently available to respond to the transactions.
Other features and advantages of the present invention will become apparent upon study of the remaining portions of the specification and drawings.


A memory device includes a counter suitable for counting the number of times that a periodic wave is enabled and generating a code, one or more memory banks each including a plurality of word lines, and one or more measurement blocks corresponding to the memory banks, respectively, and suitable for measuring an active period of an activated word line in a corresponding memory bank among the memory banks, wherein each of the measurement blocks measures the active period of the activated word line based on a first value of the code at an activation starting point of the corresponding memory bank and a current value of the code.

1. Field
Exemplary embodiments of the present invention relate to a memory device.
2. Description of the Related Art
A memory includes a plurality of memory cells. Each memory cell of a memory includes a transistor serving as a switch and a capacitor storing a charge, which represents data. Data is distinguished between a logic high level (logic value '1') and a logic low level (logic value '0') depending on whether there is a charge in a capacitor of a memory cell, in other words, whether the terminal voltage level of the capacitor is high or low.
Data is stored by way of charges accumulated in the capacitor and there is no loss of the stored data or the accumulated charges in theory. However, because of current leakage in the PN junction of a MOS transistor, the initial charge accumulated in the capacitor may disappear, and consequently the data stored in the memory cell may be lost. To prevent data loss, the data stored in the memory cell is read and the charge has to be recharged based on the read data periodically before the stored data is lost, which is called a refresh operation. The refresh operation makes the memory retain the stored data without data loss.
FIG. 1 is a circuit diagram illustrating a portion of a cell array included in a memory device to describe a word line disturbance phenomenon. In FIG. 1, BL represents a bit line.
Referring to FIG. 1, three word lines WLK−1, WLK, and WLK+1 are arranged in parallel in the cell array. The word line WLK with notation "HIGH_ACT" is an activated word line. The word lines WLK−1 and WLK+1 are disposed adjacent to the word line WLK. Also, memory cells CELL_K−1, CELL_K, and CELL_K+1 are coupled to the word lines WLK−1, WLK, and WLK+1, respectively. The memory cells CELL_K−1, CELL_K and CELL_K+1 include cell transistors TR_K−1, TR_K, and TR_K+1 and cell capacitors CAP_K−1, CAP_K, and CAP_K+1, respectively.
When the word line WLK is activated, voltages of the word lines WLK−1 and WLK+1 fluctuate due to a coupling effect between the word line WLK and the word lines WLK−1 and WLK+1, thereby affecting the amount of charge stored in the cell capacitors CAP_K−1 and CAP_K+1 of the word lines WLK−1 and WLK+1, which is referred to as word line disturbance. In other words, the probability of data loss of the memory cells CELL_K−1 and CELL_K+1 corresponding to the neighboring word lines WLK−1 and WLK+1 of the active word line WLK increases, which may become more severe as the active word line WLK is activated for a longer period.

Memory device with advanced refresh scheme


A method and communication device for processing data for transmission from the communication device to a second communication device is provided. It is detected that the data comprises an attachment. An address of a copy of the attachment is determined, the attachment present on a storage device external to the communication devices. An address of the copy of the attachment is substituted in the data such that the copy is retrievable at the second communication device via the address. The data is then transmitted to the second communication device.

Transmission of data between communication devices can require large amounts of bandwidth, especially if the data includes large attachments, such as images, videos, audio files, or documents. Such bandwidth can be costly, especially when the transmission occurs over wireless networks. This can occur, for example, when the communication device which originates the transmission includes a wireless communication device and/or a mobile communication device (laptop, cell phone, PDA, wireless modem, etc.). Furthermore, on wireless networks, the process of transmitting data is generally slow relative to wired networks. Hence, resources at an originating wireless communication device can be occupied with the transmitting process at the expense of other processes, often to the extent that the communication device can appear frozen until the transmission is complete. When transmitting data using a mobile communication device, operation of a radio is required. Such operation is power intensive and reduces the operational time of the mobile communication device due to reduction in power stored at the battery.
Furthermore, communication devices which receive transmitted data can have limits on the size of attachments which can be accepted, and data which has attachments that are of a size larger than the limit can be rejected, sometimes without the knowledge of a user of the receiving communication device.

Method and communication device for processing data for transmission from the communication device to a second communication device


A light guide bar includes a light guide member and a light scattering member. The light guide member defines a cutout. The light guide member includes a first end surface, a second end surface, and a circumferential surface interconnected between the first end surface and the second end surface. The cutout is defined in the circumferential surface and passes through the first end surface and the second end surface. The light scattering member is received in the cutout and scatters light back to the light guide member. The light scattering member and the light guide member cooperatively form a complete cylinder, and a thickness of the light scattering member is less than a radius of the light guide member.

1. Technical Field
The present disclosure relates to light guide technologies, and particularly to a light guide bar and a light emitting device having the light guide bar.
2. Description of Related Art
A light guide element, such as a light guide plate, is used to disperse light emitted from linear light sources, such as cold cathode ray tubes, or from point sources, such as light emitting diodes (LEDs). However, the light guide plate is substantially flat and cannot be used in many situations.
Therefore, it is desirable to provide a light guide bar and a light emitting device having the light guide bar to overcome or at least alleviate the above-mentioned problems.

Light guide bar and light emitting device


This application relates to an apparatus and method for treating effluent. The effluent may be derived, for example, from an upstream secondary treatment plant. The apparatus employs a plenum positionable within a fluid-impervious container. The plenum includes a fluid filter portion containing a hydrophilic material, such as peat, capable of transporting effluent by capillary action and a fluid collection portion for receiving effluent from the upstream effluent source. The apparatus also includes a fluid wicking conduit containing hydrophilic material for wicking effluent from the fluid collection portion. The fluid wicking conduit may be configured so that any appreciable amount of effluent introduced into the apparatus will be wicked even if the amount is substantially less than the fluid holding capacity of the fluid collection portion of the plenum. This enables the apparatus to operate substantially continuously and passively so long as some effluent is resident in the plenum. At the same time, the fluid holding capacity of the fluid collection portion can be sized to accommodate periodic surges in effluent flow. The apparatus may further include a dispersal mound of soil and vascular aquatic plants covering or adjacent to the plenum. The invention functions as a vegetative tertiary filter.

Various types of septic systems employing peat are known in the prior art. Most prior art peat filtration devices load the effluent from the top of the filter, and allow it to drain down through the peat in order to effect filtration of the effluent. For example, Boyd et al. (U.S. Pat. No. 5,049,265) entitled "Effluent Treatment System" discloses a system for secondarily treating wastewater through a peat filter in which liquid waste from a septic tank is pumped onto the top of a treatment medium consisting of peat. The effluent is collected at the bottom of the peat filter. The system incorporates peat-based organic fibrous material having a relatively low absorptive capacity to promote drainage, and also uses an effluent distribution system to distribute effluent over the filter medium.
Festa et al. (U.S. Pat. No. 6,620,321) entitled "Biofilter System and Method For Treating Wastewater" describes a similar system in which effluent is pumped onto the filter from the top through sacks containing filtering material (often peat), and is allowed to drain out the bottom.
Albert (U.S. Pat. No. 6,506,298) entitled "Biofiltering System for Treating Wastewater Effluent" describes a method for treating effluent that allows continuous treatment. The effluent flows onto the top of a peat layer via a fluid flow regulator, and is permitted to drain into the ground below. A fluid flow regulator and distribution system disposed upstream from the peat ensures that the wastewater flows through the peat bed at a rate no greater than the peat bed biofiltering capacity.
Many effluent treatment systems which incorporate the use of plants are also know in the prior art. Simmering et al. (U.S. Pat. No. 5,690,827) entitled "Sewage Treatment System Using Peat and a Constructed Wetland" discloses a three-stage method of sewage treatment consisting of primary settling, passing the effluent through a peat filter, and then passing the filtered effluent through a sub-surface constructed wetland. In this method, the plants are used as a separate stage of treatment following passage through the peat filter.
Winters (WO 98/21153) entitled "Device for Cleaning Polluted Water" describes a method for treating water in a mobile container filled with multiple layers, including porous layers at the bottom of the container, a layer of peat, and then a layer of sand above the peat. The method includes the use of plants for purification, particularly reeds. The container is mobile so that it may be easily replaced. Effluent is pumped into a layer of sand near the top of the reservoir, and is collected by a discharge pipe located in the base of the container. The container is flooded to a certain level to create an appropriate ground water level to promote the activity of microorganisms at the interface between wet and dry soil.
Rambeck (WO 99/32406) entitled "Improved Effluent Treatment System" describes a two-stage treatment system, to treat both solid and liquid portions of effluent. The treatment is provided by gravel in layers, with microorganisms in the gravel, and plants. Solids are retained on top of the filter body, to be transformed into a soil-peat structure, while the liquid percolates through the filter for purification.
Wolverton (U.S. Pat. No. 4,415,450) entitled "Method for Treating Wastewater Using Microorganisms and Vascular Aquatic Plants" describes a system in which supernatant from a settling tank is pumped into the bottom of a container filled with rocks, pea gravel, and vascular aquatic plants for treatment. Effluent is purified by flowing upward through the tank, during which time it is subject to processing by anaerobic and facultative microorganisrns, and the roots of at least one vascular aquatic plant.
While numerous effluent treatment systems are known in the prior art employing peat or vascular plants, they are not specifically sized and configured for tertiary effluent treatment or to accommodate both periodic surges in effluent flow and periods of low flow. Domestic wastewater production is typically uneven, with peak flows in the morning and early evening. Conventional treatment systems are typically under loaded for most of the day and overloaded for brief periods. Additionally, secondary treatment alone is insufficient to remove microcontaminants and nutrients. The need has therefore arisen for an improved tertiary filter system employing peat or other peat-like organic or synthetic materials which can operate continuously and passively, even during periods of low effluent inflow.

Tertiary filter septic system and method


Intermediate resolution-enhancement state layouts are generated based upon an original non-resolution enhanced layout of an integrated circuit and an associated resolution-enhanced layout. The intermediate resolution-enhancement state layout includes fragments corresponding to parts of the original layout and biases associated with the fragments, where the biases indicate distances between the fragments and the resolution-enhanced layout. The fragments are also assigned attributes such as fragment type, fragment location, and biases. The intermediate resolution-enhancement state layouts can be combined to generate the layout for a full chip IC. Two or more intermediate resolution-enhancement state layouts are assembled and are locally reconverged to adjust the resolution enhancement associated with the intermediate resolution-enhancement state layouts and obtain the intermediate resolution-enhancement state layouts for the full IC.

While conventional resolution-enhancement technologies (RET), such as optical proximity correction (OPC), are widely applied in advanced design-to-manufacturing processes in order to improve manufacturability and yield of integrated circuit layouts, such resolution enhancements are difficult to verify and the verification results do not necessarily translate to systematic methods of correcting RET/OPC. Furthermore, conventional RET/OPC cannot be applied incrementally or reconfigured selectively, due to proximity and hierarchical interactions of the enhancements. This resulted in "one shot" RET/OPC operations to an entire circuit layout, followed by a verification step, wherein a negative verification result necessitated adjustment to the RET/OPC settings and a reapplication of the full set of adjusted RET/OPC operations to the entire circuit layout. This approach is inefficient and time-consuming. The conventional approach presents a further disadvantage in that it prohibits the application of RET/OPC to standard cells and intellectual property (IP) cores in a way that allows such layouts to be reused as well as characterized early in the design flow.
Accordingly, a fundamentally new approach to RET/OPC is needed, allowing incremental, selective and locally reconfigurable applications of RET/OPC early in the design flow.

Intermediate layout for resolution enhancement in semiconductor fabrication


A pump having a rotary portion which compels the movement of a fluid by peristaltic compression of resilient tubing containing the fluid includes a roller assembly having at least one roller mounted in the rotary portion of the pump for contact with the resilient tubing. The roller has a range of rotation in contact with the tubing during pump operation. A roller control mechanism is adapted and constructed to stop the roller at a single, predetermined location on the tubing when the pump operation is stopped.

Peristaltic pumps are used in a variety of applications in which it is desirable to convey fluid in accurately controllable quantities. Peristaltic pumps typically include a rotary portion which compels the movement of a fluid by peristaltic compression of resilient tubing containing the fluid against an arcuate rigid surface known as a pump occlusion. The roller/occlusion intersection area is typically known as the "working area" of the pump.
Imaging systems using inkjet printing have become widely known, and are often implemented using thermal inkjet technology. Such technology forms characters and images on a medium, such as paper, by expelling droplets of ink in a controlled fashion so that the droplets land on the medium. The printer, itself, can be conceptualized as a mechanism for moving and placing the medium in a position such that the ink droplets can be placed on the medium, a printing cartridge which controls the flow of ink and expels droplets of ink to the medium, and appropriate hardware and software to position the medium and expel droplets so that a desired graphic is formed on the medium. A conventional print cartridge for an inkjet type printer comprises an ink containment device and an ink-expelling apparatus, commonly known as a printhead, which heats and expels ink droplets in a controlled fashion.
In some inkjet type printers, a peristaltic pump head is used to drive multiple, resilient tubes to convey ink between the containment device and the printhead. In some pump applications, flow control is achieved simply by turning the pump off. In applications requiring more precise flow control, a valve mechanism is typically provided downstream of the pump outlet to selectively permit or prevent the flow of ink from the pump.
Whether or not a separate control valve is provided, the rollers of the peristaltic pump stop at random positions. During repeated starting and stopping of pump operation, the rollers will have stopped at positions along the entire arc of the roller/occlusion intersection, causing repeated flattening and permanent deformation of the flow area of the peristaltic tubes in the working area of the pump. Over the life of the pump, tube deformation can become so severe that it significantly alters the volumetric flow rate for a given pump motor RPM.
There are two principal remedies for severe peristaltic tube deformation. The most common solution is tube replacement, which requires removal, disassembly, repair, and replacement of the entire pump. One alternative to tube replacement is the provision of a mechanism to pull open the flattened tube. Unfortunately, pulling mechanisms are relatively complex and expensive.
It can be seen from the foregoing that the need exists for a simple, inexpensive, arrangement for reducing the effect of tube flattening in peristaltic pumps.

Peristaltic pump with roller pinch valve control

Hewlett-Packard Development Company, L.P.