A barcode scanner comprises a compensating light source, an image capturing module and a processor. The compensating light source is used to emit a compensating light. The image capturing module is used to capture an original image including an object and to capture a second image under the compensating light. The processor is coupled with the compensating light source and the image capturing module. The processor generates a depth information of the object according to the original image, controls intensity of the compensating light according to the depth information, controls the image capturing module to capture a second image when the compensating light source emits the compensating light, obtains a target information corresponding to a target object according to the depth information, obtains a target image by mapping the target information onto the second image, locates a barcode and analyzes an information of the barcode according to the target image.

1. Field of the Invention
The present invention relates to a barcode scanner and an operational method of the barcode scanner, and more particularly, to a barcode scanner for detecting depth information of an object and an operational method thereof.
2. Description of the Prior Art
A barcode is a figure identification code which is arranged according to a specific encoding rule for presenting certain messages. One-dimensional barcodes, such as EAN-8, are composed of a plurality of parallel black stripes with different widths. Two-dimensional barcodes, such as the Quick Response code (QR code), are rectangular figures composed of a plurality of black rectangles, and three corners of the rectangular figure include specific positioning marks to facilitate reading. Since a barcode can be used to identify manufacturing country, product's name, manufacturing date and manufacturer's name of a product, sender's and recipient's mailing addresses, book category number or date, etc., it is therefore widely applied in many fields.
When one desires to transform a barcode into meaningful information via a barcode scanner, he or she needs to hold the barcode scanner towards the object with the barcode so as to capture an original image which includes the object. The barcode scanner then locates the barcode's location and analyzes the information recorded in the barcode. Since the barcode presents recorded information via specific arrangement of the black figures and the spaces, it would be difficult to scan a barcode if the environment surrounding the object is not uniform in brightness when the object is scanned. To avoid such situations, the barcode scanner may emit compensating light via a compensating light source to compensate the insufficient environmental lighting. When the barcode scanner is too close to the scanned object, however, most of the compensating light, if not all, is reflected from the object that it is difficult to identify the barcode.
When a barcode scanner is included as part of a Point of Sale (POS) system, since the barcode scanner may be used in a large warehouse with a complicated environment, the original image captured by the barcode scanner may include more than one object. Under such circumstances, it would be more difficult for the barcode scanner to locate the position of the barcode and would take more time to complete the scanning process. Furthermore, because the scanned object is not in a uniformed shape, the one-dimensional or two-dimensional barcode may be disposed on a curved surface of an object and thus distorted. It would be difficult to decode the barcode information transformed from the original image.
Thus, it is important to solve the problems resulted from reflection of compensating lights from objects, barcode images with complicated backgrounds, and barcode image distortion due to uneven object surfaces on which a barcode is disposed.

Barcode scanner and operational method of the same


Novel substituted pyrazolo-rings fused to nitrogen containing heterocyclic rings having the following formula ##STR1## in which at least one of Y, Z or W is N or N-O and the remainder of Y, Z or W is C-R wherein the variables are as defined in the specification; and agriculturally acceptable salts thereof.

This invention relates to novel substituted pyrazolo-rings fused to nitrogen containing heterocyclic rings having the following formula: ##STR2## in which at least one of Y, Z or W is N or N-O and the remainder of Y, Z or W is C-R wherein
R is hydrogen; halogen; nitro; cyano; alkyl; alkoxyalkyl acetoxymethyl; hydroxymethyl; haloalkyl; formyl; alkylcarbonyl; carboxy and its salts; COO alkyl; azido (N.sub.3); amino; substituted amino wherein the substituents are alkyl, alkoxy, hydroxy, formyl, alkylcarbonyl, alkoxycarbonylalkyloxy, alkoxycarbonylalkylthio, alkoxycarbonylalkylidenecarbonyl, hydroxycarbonylalkoxy, hydroxycarbonylthio, cyanoalkoxy, hydroxycarbonylalkyledinecarbonyl, alkylsulfonyl, haloalkylsulfonyl, aminocarbonyl, (di)alkylaminocarbonyl, alkoxycarbonyl, alkoxyalkyl, hydroxycarbonylalkyl, alkoxycarbonylalkyl, and amino; carboxyamido; substituted carboxyamido wherein said substituents can be selected from alkyl, alkylsulfonyl, and haloalkylsulfonyl; sulfonamido wherein the N is substituted with hydrogen and/or alkyl; VR.sup.6 wherein V is O and S(O).sub.m and R.sup.6 is selected from the group hydrogen, alkyl, haloalkyl, cyanoalkyl, alkoxycarbonylalkyl, hydroxycarbonylalkyl and aminocarbonylalkyl wherein the N is substituted with hydrogen and/or alkyl;
m is 0 to 2; PA1 R.sup.1 is hydrogen and halogen; PA1 R.sup.2 is hydrogen, nitro, halogen, cyano, alkylthio, alkylsulfinyl, alkylsulfonyl, and alkoxy; PA1 R.sup.3 is halogen, haloalkyl, cyano, alkylthio, alkylsulfinyl, and alkylsulfonyl; PA1 R.sup.4 is hydrogen and halogen; PA1 X is N or C-R.sup.5 ; PA1 wherein R.sup.5 is hydrogen, haloalkyl, halogen, cyano, nitro, alkythio, alkylsulfinyl, alkylsulfonyl, and alkoxy; and PA1 agriculturally acceptable salts thereof.


A subsea wellhead assembly includes a production tree and a tubing hanger assembly having a tubing hanger and an orientation adapter. A passage is formed through a side wall of the orientation adapter for porting communication from within a main bore of the wellhead assembly. When the tubing hanger assembly lands in the wellhead, a key on the orientation adapter engages a helical profile on an inner surface of the main bore and rotates the orientation adapter so that the passage registers with a passage in the tree. Fluid and electricity communicates through the registered passages. Examples of connectors between the respective passages include spheriseal connectors and electrical wet connects.

1. Field of Invention
The invention relates generally to a wellhead assembly for use subsea, and having wellhead components that align during assembly to register passages in the respective components.
2. Description of Prior Art
Subsea wellbores are formed from the seafloor into subterranean formations lying underneath. Systems for producing oil and gas from subsea wellbores typically include a subsea wellhead assembly set over an opening to the wellbore. Subsea wellheads usually include a high pressure wellhead housing supported in a low pressure wellhead housing and secured to conductor casing that extends downward past the wellbore opening. Wells are generally lined with one or more casing strings coaxially inserted through, and significantly deeper than, the conductor casing. The casing strings are typically suspended from casing hangers landed in the wellhead housing. One or more tubing strings are usually provided within the innermost casing string; that among other things are used for conveying well fluid produced from the underlying formations. The produced well fluid is typically controlled by a production tree mounted on the upper end of the wellhead housing. The production tree, which is a large, heavy assembly, is generally equipped with a number of valves and controls mounted thereon. One of the largest challenges when running and installing tubing hangers in wellheads is ensuring correct orientation to ensure proper communication with downhole equipment, and to prevent damaging the couplers and seals between the production tree and tubing hanger during installation of the production tree. Several systems have been previously employed to achieve orientation, which consume valuable rig resources.
Some subsea wellhead assemblies include a tubing hanger spool that lands on an upper end of the high pressure housing. The tubing hanger is supported within the tubing hanger spool, and can be landed therein prior to or after the production tree mounts to the upper end of the tubing hanger spool. Difficulties are typically encountered when landing the tubing hanger in the tubing spool and ensuring the tubing hanger is properly oriented so that axial passages in the tubing hanger and production are aligned.

Orientation adapter for use with a tubing hanger


Provided is an automobile operation apparatus and method designed for detecting failure of a drive gear selector of an automatic transmission having a normal mode constituted by P, R, N and D gears, and a sport mode. The automobile operation apparatus includes up/down switches for shifting a gear of the automatic transmission up or down when a gearshift lever is shifted from the normal mode to the sport mode, a detection means for detecting whether the gearshift lever is shifted to the sport mode, and a control means for controlling a D gear operation at the up/down switches when the D gear is abnormal and the detection means detects a mode change. Therefore, an automobile can be driven, even when a D gear for forward driving malfunctions, by a virtual drive mode switch that is equivalent to the D gear in an emergency.

1. Field of the Invention
The present invention relates to an automobile operation apparatus and method designed for detecting failure of a drive gear selector of an automatic transmission, and more particularly, to an automobile operation apparatus and method capable of operating an automobile having a sport mode when a drive gear of the automobile malfunctions.
2. Description of the Related Art
In general, some automatic transmission vehicles include P, R, N, D, 2 and L gears, and other automatic transmission vehicles include an automatic transmission having a normal mode constituted by P, R, N and D gears and a sport mode manually operated by a gearshift lever.
The automatic transmission having the sport mode includes P, R, N and D gears and up/down switches such as + and − switches. A driver may automatically drive the automobile in a state in which a gearshift lever is in the D gear as a forward shift, or manually drive the automobile by moving the gearshift lever to the sport mode and operating the up(+) or down(−) switch step by step to vary the speed of the automobile.
In the manual gearshift of the automatic transmission, an inhibitor switch detects a shift gear position of the gearshift lever to control a shift pattern appropriate to the P, R, N and D gears, and determines whether a selector switch is in the sport mode or the normal mode in the D gear.
The automatic transmission including the sport mode, as shown in FIG. 1, includes a gearshift lever having a down switch 11 for downshifting, an up switch 12 for upshifting, and a selection switch 13 for detecting whether the sport mode is selected or not.
In addition, a cluster 14 detects the current shift gear to transmit it to a transmission control unit (TCU) 16.
In the sport mode vehicle, gear signals input into the TCU 16 correspond to P, R, N and D gears. In the D gear, an inhibitor switch 15 does not immediately input a D gear signal to the TCU 16 but first determines whether a sport mode selection switch 13 installed between the TCU 16 and the inhibitor switch 15 is switched to a normal mode or sport mode of the D gear.
In the automobile having the sport mode, when there is no signal for P, R, N and D gears and the sport mode selection switch 13 is ON, the TCU 16 determines that the switch 13 is in the sport mode.
In addition, when the inhibitor switch 15 is normal and the sport mode selection switch 13 malfunctions, or when a signal line between the inhibitor switch 15 and the sport mode selection switch 13 is cut such that a selected mode is not input into the TCU 16, the TCU 14 performs determination according to control logic.
When a state in which a signal from the inhibitor switch 15 is not detected, or a plurality of signals are simultaneously detected the control logic allows the TCU 16 to perform control depending on a signal just before the state. Further, after the above state reverts to the normal state, the TCU 16 performs control on the basis of the detection signal.
Therefore, when it is determined that the sport mode selection switch 13 malfunctions according to malfunction determination conditions of the inhibitor switch 15, since control just before the above state is performed, control depending on any one of the P, R, N and D gears is performed.
Meanwhile, Document 1 discloses a "Method for Controlling Automatic Transmission During Fault of Sports Mode Select Switch for Vehicle," which is shown in FIG. 2.
As shown in FIG. 2, in the method for controlling an automatic transmission during fault of a sports mode select switch for an automobile, while the automobile is moving or stopped, a driver shifts a gearshift lever to a "D" gear and selects a normal mode or a sport mode.
That is, when the gearshift lever is positioned at the "D" gear, the inhibitor switch transmits a "D" gear selection signal to a TCU, and then the select switch is operated to select a normal mode or a sport mode.
When the driver selects the sport mode, the TCU checks whether one of up/down switches is input.
In addition, when it is checked that one of the up/down switches is input, the TCU allows entry into the sport mode such that the driver shifts the gearshift lever up/down. Further, the entry into the sport mode is allowed even though a "D" gear inhibitor switch signal of the gearshift lever is not input. At this time, when P, R and N inhibitor switch signals are input for a certain time, the TCU blocks entry into the sport mode and maintains the normal mode.
In the "D" gear, when the select switch is positioned at the sport mode and the up/down switches are simultaneously input, the TCT determines that the up/down switches are malfunctioning and blocks entry into the sport mode.
That is, entry inhibition conditions of the sport mode are set to the case that the up/down switches are simultaneously input for a certain time in the sport mode, and the case that the up/down switches are input for a certain time while the inhibitor switch signals of the P, R and N gears are input.
In the failure determination control logic, when the driver selects the sport mode and turns on the up/down switches upon failure of the inhibitor switch, the TCU checks the P, R and N inhibitor switch signals. When there is no signal input, the TCU determines that the gearshift lever is positioned at the "D" gear, enters the sport mode, and maintains a normal running state.
In addition, when any one of the up/down switches malfunctions, a sport mode signal of the select switch and signals of the up/down switches are simultaneously input. In this case, the TCU determines that the up/down switches are malfunctioning, blocks entry into the sport mode, and maintains the normal mode.
Further, Document 2 discloses a "Breakdown Control Method When Sports Mode Selection of Automobile Automatic Transmission," which is shown in FIG. 3.
As shown in FIG. 3, in the breakdown control method when a sports mode selection of an automobile automatic transmission, a TCU resets a timer to determine whether the sport mode is operating normally, and the timer continuously counts a time from a reset point (ST20).
In addition, the TCU determines whether a P gear signal detected and transmitted by an inhibitor switch is input (ST21), and the TCU determines whether a gear signal of the inhibitor switch corresponds to one of P, R, N and D gears or the sport mode (ST22 to ST25).
In steps ST21 to ST25, when at least one gear signal is input from the inhibitor switch, the TCU determines that the inhibitor switch is operating normally and stops failure determination.
Meanwhile, in steps ST21 to ST25, when no gear signal is input from the inhibitor switch, the TCU determines whether there is a signal applied from an up switch or a down switch.
An upshift signal and a downshift signal are applied from the up switch and the down switch, respectively (ST26).
When neither of the upshift signal and the downshift signal is input in step S26, the TCU determines whether the time counted by the timer exceeds a set threshold time (ST27).
When it is determined that the counted time of the timer exceeds the thresholdl time, the TCU returns to step ST21 to repeatedly determine whether a gear signal of the inhibitor switch is output (ST27).
As described above, the threshold time is set to designate a minimum reference time for determining no signal detection of the inhibitor switch.
In addition, when the counted time of the timer exceeds the threshold time in step ST27, the TCU performs gearshift control depending on a prior gearshift stage corresponding to a gear signal last detected by the inhibitor switch (ST28).
Meanwhile, when at least one of the upshift signal or the downshift signal is applied in step ST26, the TCU determines that the gearshift is a first speed to perform gearshift control (ST29).
Further, when the first speed control is performed in step S29, the TCU determines whether the upshift signal or the downshift signal is continuously input by acceleration or deceleration of the driver (ST30).
When the upshift signal or the downshift signal is input in step ST30, the TCU performs gearshift control according to a regular shift pattern (ST31).
However, in the conventional automatic transmission including the sport mode, contact failure of the inhibitor switch and the gearshift lever makes it impossible to drive the automobile. When tension of a cable connected to the gearshift lever is loosened or cut, the gearshift lever cannot be shifted and the automobile becomes undrivable.
In addition, under the condition that a signal from any one of the P, R, N and D gears of the inhibitor switch is not detected, the automobile can be driven by determining that the gearshift lever is positioned at a first speed on the basis of a signal detected from any one gear of the up/down switches of the sport mode. However, when a signal from any one gear of the inhibitor switch is detected, the automobile is disabled. In addition, when only the D gear of the sport mode malfunctions upon signal detection from any one gear, the automobile may be disabled.
Meanwhile, in the technology described in Document 2, when the inhibitor switch signal of the D gear is not detected, the automobile can be driven after the gearshift lever is positioned at the sport mode and then any one signal of the up/down switch of the sport mode is detected. Therefore, when a signal from the D gear and the up/down switches of the sport mode is not detected, the automobile may be disabled.    [Document 1] Korean Patent Laid-open Publication No. 2002-49231 (Jun. 26, 2002)    [Document 2] Korean Patent Laid-open Publication No. 2007-62010 (Jun. 15, 2007)

Automobile operation apparatus and method designed for failure of drive gear of automatic transmission


A packaged radio frequency transistor amplifier includes a package housing, an RF transistor amplifier die that is mounted within the package housing, a first capacitor die that is mounted within the package housing, an input leadframe that extends through the package housing to electrically connect to a gate terminal of the RF transistor amplifier die, and an output leadframe that extends through the package housing to electrically connect to a drain terminal of the RF transistor amplifier die. The output leadframe includes an output pad region, an output lead that extends outside of the package housing, and a first arm that extends from one of the output pad region and the output lead to be adjacent the first capacitor die.

Electrical circuits requiring high power handling capability while operating at high frequencies, such as R-band (0.5-1 GHz), S-band (3 GHz), X-band (10 GHz), Ku-band (12-18 GHz), K-band (18-27 GHz), Ka-band (27-40 GHz) and V-band (40-75 GHz) have become more prevalent. In particular, there is now high demand for RF transistor amplifiers that are used to amplify RF signals at frequencies of, for example, 500 MHz and higher (including microwave frequencies) for cellular telephone, radar and other applications. These RF transistor amplifiers often need to exhibit high reliability, good linearity and handle high output power levels.
Most RF transistor amplifiers are implemented in silicon or wide bandgap semiconductor materials, such as silicon carbide ("SiC") and Group III nitride materials. As used herein, the term "Group III nitride" refers to those semiconducting compounds formed between nitrogen and the elements in Group III of the periodic table, usually aluminum (Al), gallium (Ga), and/or indium (In). The term also refers to ternary and quaternary compounds, such as AlGaN and AlInGaN. These compounds have empirical formulas in which one mole of nitrogen is combined with a total of one mole of the Group III elements.
Silicon-based RF transistor amplifiers are typically implemented using laterally diffused metal oxide semiconductor ("LDMOS") transistors. Silicon LDMOS RF transistor amplifiers can exhibit high levels of linearity and may be relatively inexpensive to fabricate. Group III nitride-based RF transistor amplifiers are typically implemented as High Electron Mobility Transistors ("HEMT") and are primarily used in applications requiring high power and/or high frequency operation where LDMOS RF transistor amplifiers may have inherent performance limitations.
RF transistor amplifiers may include one or more amplification stages, with each stage typically implemented as a transistor amplifier. In order to increase the output power and current handling capabilities, RF transistor amplifiers are typically implemented in a "unit cell" configuration in which a large number of individual "unit cell" transistors are arranged electrically in parallel. An RF transistor amplifier may be implemented as a single integrated circuit chip or "die," or may include a plurality of dies. When multiple RF transistor amplifier die are used, they may be connected in series and/or in parallel.
RF transistor amplifiers often include matching circuits, such as (1) impedance matching circuits that are designed to improve the impedance match (for RF signals at the fundamental operating frequency of the amplifier) between the RF transistor amplifier die and transmission lines connected thereto and (2) harmonic termination circuits that are designed to at least partly terminate harmonics that may be generated during device operation, such as second and third order harmonics. The RF transistor amplifier die(s) as well as the impedance matching and harmonic termination circuits may be enclosed in a package. Electrical leads may extend from the package that are used to electrically connect the RF transistor amplifier to external circuit elements such as input and output RF transmission lines and bias voltage sources.
As noted above, Group III nitride-based RF transistor amplifiers are often used in high power and/or high frequency applications. Typically, high levels of heat are generated within a Group III nitride-based RF transistor amplifier die during operation. If the RF transistor amplifier die becomes too hot, its performance (e.g., output power, efficiency, linearity, gain, etc.) may deteriorate and/or the RF transistor amplifier die may be damaged. As such, Group III nitride-based RF transistor amplifiers are typically mounted in packages that may be optimized for heat removal.
FIGS. 1A through 1D schematically illustrate a conventional packaged RF transistor amplifier 1. In particular, FIG. 1A is a schematic top view of the packaged RF transistor amplifier 1 with the walls and lid of the package omitted to show the circuit elements forming the RF transistor amplifier. FIG. 1B is a cross-sectional view of the complete packaged RF transistor amplifier 1 (i.e., the walls and lid are included in FIG. 1B). The cross-section of FIG. 1B is taken along line 1B-1B of FIG. 1A. FIG. 1C is a schematic plan view of an RF transistor amplifier die that is included in the packaged RF transistor amplifier 1 of FIGS. 1A-1B. Finally, FIG. 1D is an equivalent circuit diagram of the RF transistor amplifier 1.
As shown in FIGS. 1A-1B, the RF transistor amplifier 1 comprises a package 10 and a plurality of circuit components that are mounted within the package 10. The package 10 includes a submount 12, walls 14, a lid 16, an input leadframe 20 and an output leadframe 30. The submount 12 may comprise, for example, a metal block. The submount 12 may provide an electrical connection to ground, and may also serve as a heat dissipation structure that dissipates heat that is generated in an RF transistor amplifier die that is mounted within the package 10. The submount 12, walls 14 and lid 16 form a package housing 18. The input leadframe 20 and the output leadframe 30 extend through respective walls of the package housing 18. The walls 14 and lid 16 may be formed of a ceramic material. The submount 12, walls 14 and lid 16 may define a cavity, so that package 10 is often referred to as an open cavity package. The input leadframe 20 may comprise an input pad 22 that is within the package housing 18 and an input lead 24 that extends from the input pad 22 through a front wall 14-1 of the package housing 18. The output leadframe 30 may comprise an output pad 32 that is within the package housing 18 and an output lead 34 that extends from the output pad 32 through a rear wall 14-2 of the package housing 18.
The circuit components that are mounted within the package 10 include an RF transistor amplifier die 40, an input impedance matching capacitor die 54, an input harmonic termination capacitor die 64, and an output impedance matching capacitor die 74. The three capacitor die 54, 64, 74 are part of an input impedance matching circuit 50, an input harmonic termination circuit 60, and an output impedance matching circuit 70, respectively. The die 40, 54, 64, 74 are mounted on the submount 12. Each die 40, 54, 64, 74 may have a terminal on its bottom side that is electrically connected to the submount 12 by, for example, a conductive die attach material (not shown). The RF transistor amplifier die 40 includes a gate terminal 42 which acts as the RF input to the RF transistor amplifier die 40 and a drain terminal 44 that acts as an RF output for the RF transistor amplifier die 40. The RF transistor amplifier die 40 further includes a source terminal 46 (FIG. 1B) that is on the bottom side of the die 40. FIG. 1C is a plan view of the RF transistor amplifier die 40 illustrating the gate terminal 42 and the drain terminal 44, each of which may be implemented as metal pads on a top surface of the RF transistor amplifier die 40. A protective insulating layer or pattern 48 may cover the rest of the top surface of the RF transistor amplifier die 40.
As shown in FIGS. 1A-1B, the input impedance matching circuit 50 includes a set of first bond wires 52, the input impedance matching capacitor die 54 and a set of second bond wires 56. Proximate ends of the first bond wires 52 are coupled to the input pad 22 of input leadframe 20 and distal ends of the first bond wires 52 are coupled to the first electrode of a capacitor (or a set of capacitors) included in the input impedance matching capacitor die 54. The second electrode of the capacitor included in the input impedance matching capacitor die 54 is mounted on the bottom side of the input impedance matching capacitor die 54 so that it is electrically connected to the submount 12. The submount 12 may be electrically coupled to electrical ground. The second bond wires 56 extend between the first electrode of the capacitor included in the input impedance matching capacitor die 54 and the gate terminal 42 of RF transistor amplifier die 40. The second bond wires 56 pass over the harmonic termination capacitor die 64.
The harmonic termination circuit 60 includes a set of third bond wires 62 and the harmonic termination capacitor die 64. The third bond wires 62 are coupled between the gate terminal 42 of RF transistor amplifier die 40 and a first electrode of the capacitor (or set of capacitors) included in the harmonic termination capacitor die 64. The second electrode of the capacitor included in the first harmonic termination die 64 is mounted on the bottom side of the harmonic termination capacitor die 64 to be electrically connected to the submount 12 (which, again, provides an electrical connection to ground).
A set of fourth bond wires 46 extend between the drain terminal 44 of RF amplifier die 40 and the output pad 32 of the output leadframe 30. The fourth bond wires 66 pass over the output impedance matching capacitor die 74.
The output impedance matching circuit 70 comprises a set of fifth bond wires 72 and the output impedance matching capacitor die 74. Distal ends of the fifth bond wires 72 are coupled to the output pad 32 of the output leadframe 30, and proximate ends of the fifth bond wires are coupled to the first electrode of a capacitor (or a set of capacitors) included in the output impedance matching capacitor die 74. The second electrode of the capacitor included in the output impedance matching capacitor die 74 is mounted on the bottom side of the output impedance matching capacitor die 74 to be electrically connected to the submount 12 (which, again, provides an electrical connection to ground).
FIG. 1D is an equivalent circuit diagram of the RF transistor amplifier 1. As shown in FIG. 1D, RF signals that are to be amplified may be input to RF transistor amplifier 1 through the input lead 20. The set of first bond wires 52 acts as a series inductance L1 between the input lead 20 and a node N1, which is the first electrode of the input impedance matching capacitor die 54. The second electrode of the input impedance matching capacitor die 54 is coupled to ground through submount 12 to form a shunt capacitance C1. The set of second bond wires 56 acts as a series inductance L2 between node N1 and the gate terminal 42 of the RF transistor amplifier die 40. The set of third bond wires 62 acts as an inductance L3 and the harmonic termination capacitor die 64 forms a capacitance C2. The inductance L3 and the capacitance C2 are coupled are coupled in series between gate terminal 42 of the RF transistor amplifier die 40 and electrical ground, forming the shunt input harmonic termination circuit 60.
The drain terminal 44 of RF transistor amplifier die 40 is connected by the set of fourth bond wires 46 to the output pad 32 of the output leadframe 30. The fourth set of bond wires 46 thus acts as a series inductance L4. The amplified RF signals output at the drain terminal 44 are output from RF transistor amplifier 1 through the output lead 34 of output leadframe 30. The set of fifth bond wires 72 acts as an inductance L5 and the output impedance matching capacitor die 74 forms a capacitance C3. The inductance L5 and the capacitance C3 are coupled in series between the output leadframe 30 and electrical ground, forming the shunt output impedance matching circuit 70.
FIGS. 1A-1B illustrate a so-called open-cavity packaged RF transistor amplifier. FIG. 1E is a schematic cross-sectional view of a conventional packaged RF transistor amplifier 1A that replaces the ceramic walls 14 and lid 16 of RF transistor amplifier 1 with a plastic overmold package 10A that includes a submount 12, a plastic overmold 18A.

Radio frequency transistor amplifiers having leadframes with integrated shunt inductors and/or direct current voltage source inputs


An information processing apparatus wherein a plurality of operating systems operate on a single processor and a framework (shared object) enabling reliable and quick sharing of correct information between the plurality of operating systems is provided. The apparatus has a function the plurality of operating systems can create, register and refer to the shared object which provides an interface for registration and reference of information. The shared object is operated so that, while one of the operating systems is registering information or referring thereto, the other operating system is inhibited from registering the information and referring thereto. When one operating system finished the registration or reference of the information, one operating system informs the other operating system of the fact.

The present invention relates to a technique for sharing information between a plurality of operating systems in an information processing apparatus which can have the plurality of operating systems and can switchingly operate one of the operating systems.
In an ordinary information processing apparatus, a single operating system (OS) is operated to perform resource schedule management in such a manner that the apparatus can manage such resources such as a processor, a memory and input/output devices which form the information processing apparatus for efficient operation of the resources.
There are various types of operating systems which are excellent in operations such as user interface, multimedia, communications, etc. and excellent in real time processing. For the purpose of obtaining such features, there is a demand of a single processor which can execute a plurality of operating systems.
As a mechanism for operating a plurality of operating systems on a single processor, there is disclosed a virtual machine system (Volume. 11 in OS Series, VM, Kyouritsu Publishing, written by Seio Okazaki) which is implemented in a large scale computer. In the virtual machine system, a virtual machine control program occupies, manages and virtualizes all hardware to form a virtual machine. A controller forming a part of the virtual machine virtualizes a physical memory, input/output unit device, external interrupt, etc.
Meanwhile, as a technique for offering an interface of a plurality of operating systems with a single processor, a micro-kernel exists. In the case of the micro-kernel, an operating system server, which provides functions of the operating systems to a user, is formed on the micro-kernel. The user utilizes computer resources via the server. When a server is provided for each of the operating systems, the user can enjoy provision of various operating system environments.
In a car navigation, on the other hand, site information such as restaurant information is previously stored in a storage such as a CD-ROM or DVD-ROM so that the site information can be read out from such a storage and displayed on a map.
In an environment wherein a plurality of operating systems are operated on a single processor, the operating systems are operated autonomously each other so that application software or programs mounted to the respective operating systems are operated individually and asynchronously. Among the types of application programs operating on the operating systems, however, there may exist some application program which can realize its function by exchanging information with the other application program in synchronism with each other. In such a case, a mechanism is required by which the application program can share information on the respective operating systems or can be synchronized thereon. To this end, there are suggested a shared memory which provides a memory zone capable of being referred to by respective operating systems, and a message communication technique for realizing communication between respective operating systems.
When such a shared memory is used to share information between the plurality of operating systems for their cooperative operation, however, there occur problems which follow.
That is, while the application program on one of the operating systems is registering information in the shared memory, if an OS context change-over takes place to change the current operating system to another operating system, then the application program on the changed operating system refers to the incorrect information being rewritten in the shared memory.
Further, when the application program of one operating system registered information in the shared memory or changed information in the shared memory, the application program of another operating system cannot immediately recognize it. For example, even when the updating of the information is monitored through polling, the application program cannot recognize it in a time shorter than a polling interval time. In this case, in addition, periodical information updating must be judged, which results in an increased load of the processor.
Furthermore, in the case where a communication message is used to share information between a plurality of operating systems for their linkage operation, if the application programs of the respective operating systems do not know previously addresses of a shared memory having information to be shared or interface information such as task ID's of the respective application tasks, then there occurs a problem that information exchange is impossible.
When an environment, wherein a plurality of operating systems are operated on a single processor, is applied to a position information display device such as a navigation device, it is required for the application program of each of the operating systems to perform its processing operation with use of the latest position information. For this reason, the display device is remarkably affected by the aforementioned problem.
In the prior art, further, when it is desired to newly add an application program utilizing information shared between a plurality of operating systems in an already-developed system environment, the newly-added application program requires modification of existing application programs, with the result that the number of developing steps and a development period are increased.

This patent is subject to a terminal disclaimer.

Information processing apparatus with multiple operating systems


Scattered light is detected radiometrically in a photolithography system. A photodetector makes direct measurements of scatter at points in the line or plane of illumination, and a generalized scatter function is derived from these measured data.

This invention relates to radiometric scatter measuring.
In a typical optical lithographic (also called photolithographic) process, as illustrated in FIG. 1, within an optical lithography tool 500 an image is copied from a reticle (mask) 100 onto a wafer 200 by projecting light 350 from a light source 300 through an illumination slot (frame) 150 over the patterned reticle 100, through precision optics (lenses) 400, onto the wafer 200. The wafer 200 has first been coated with a photoresist material (also called resist) that responds to light exposure in a specific, predictable way, e.g., by being made more or less soluble to a developer liquid upon illumination by light of a particular wavelength for a certain duration, under proper conditions.
In the ideal photolithographic process illustrated by FIG. 1, the imaged light 350 creates only an image on the wafer 200 that perfectly corresponds to the image or pattern of the reticle 100. In real-world photolithographic processes, however, as illustrated by FIG. 2, scattered light 370 (sometimes also known as flare or stray light) can, among other things, reduce the potential precision or efficiency of the system by reducing image contrast and process tolerances. The level of scatter can vary from system to system, within a single system, and over time.
The lithographic measurement of scattered light is commonly expressed as the percentage of open frame light intensity (i.e., the intensity of light near the surface of wafer 200 when reticle 100 is omitted or is transparent) measured in shadowed areas. One lithographic method of measuring scatter, described by Kirk, involves gradually increasing the light intensity (dose) over an opaque reticle feature until the image of the opaque feature formed in positive photoresist becomes fully developer-soluble. In other words, the opaque feature""s image (which would not develop away in an ideal system) is subjected to scattered light to the point that it does develop away.
One opaque feature commonly used with this method is a 2 xcexcm-wide isolated line in a clear field. This method requires observation of the dose in the clear surrounding area when the photoresist there develops away, followed by observation of the dose step when the image of the opaque line develops away. The scatter measurement is commonly expressed as a percentage, dividing the dose to clear the surrounding resist (Eo) by the dose to clear the line (Do). The larger the line""s width, the further the light has to scatter to clear all the resist.
Measuring scatter as a function of feature size in this way has been a popular method for determining the scatter distributionxe2x80x94also called the point spread function (PSF)xe2x80x94of a photolithography system at relatively short ranges of spread (i.e., scatter at relatively short distances in the x-y plane from the light source). A second, similar lithographic scatter measurement method also described by Kirk is based on observing the receding edge of a photoresist image of an opaque reticle feature as the dose is increased and the edge recedes into the dark region of the image.
These lithographic scatter measurement methods already in use involve the measurement of Do along the length of the illumination slot, to track the changes in value. These methods can be tedious, time-consuming, and resource-intensive. Moreover, potential sources of error or imprecision in such measurement methods include the variation of Eo within a wafer and from wafer to wafer, the discrete dose increments used during testing, and human variability and error in the visual inspection steps of the process. In addition, photoresist-generated lens contamination can change the level and shape of the scatter PSF over time, and these effects can be overlooked by the standard lithographic measurement methods that use only one feature size, such as a 2 xcexcm isolated line.


The present invention relates to the field of electrically erasable and programmable nonvolatile semiconductor memories (EEPROM) and, in particular, to contactless array configurations that are used for the practical and efficient implementation of a particular type of memory transistor. Such a memory transistor allows fast 5V-only programming by the use of an enhanced source-side injection mechanism. This concept requires a program gate in the field oxide region which serves to capacitively couple a high voltage to the floating gates. Thus, a very high injection current is established during programming. This additional program gate, however, increases the cell area considerably. The present disclosure shows a contactless 5V-only Flash EEPROM array configuration that relies on shared program lines in order to minimize the area overhead that is caused by this program gate. Furthermore, a memory array with shared wordlines is presented which further enhances the density achievable.

1. Field of the Invention
The invention relates to the field of electrically erasable, programmable read-only-memory ("EEPROM") devices and, particularly, to an efficient contactless array configuration for the implementation of memory cells that rely on source-side injection for fast programming. Even more particularly, the invention relates to a contactless array configuration with shared program gates for erasable and programmable semiconductor memories based on enhanced hot-electron injection cells.
2. Field of the Prior Art
Recently, Flash EEPROM memories have gained substantial interest as the best solution for electrically-rewritable high-density nonvolatile data storage. These semiconductor memories combine the high integration density and high programming speed of EPROMs with the higher functionality of EEPROMs by offering electrical in-circuit erasability. Typically, Flash memories are distinguished from "classical" EEPROMs by their block (or sector) erase scheme. That is, in a Flash memory the byte-selective erasability of EEPROMs is sacrificed for the sake of a higher integration density. The possibility exist, however, to divide the memory in different sectors which can be erased separately.
At first, Flash memory was introduced for replacing EPROMs and battery-backed Random Access Memories ("RAMs") in measuring equipment (calibration, trimming, data storage), tuners and TV sets (programmable channel selection), and in microcomputers (microcode updates). On the other hand, new applications have arisen, such as solid-state disks for small computers and Personal Digital Assistants ("PDAs"), program storage for Digital Signal Processing ("DSP") chips and for portable equipment, smart cards, automotive applications (such as fuel injection control and Automatic Braking Systems ("ABS systems")) and neural networks. Additionally, a trend has arisen to integrate logic and nonvolatile memory on the same chip: the so-called embedded memories which require a compromise between performance, density and processing complexity.
Generally, as described below, three main classes of Flash memories can be identified.
The first class uses conventional channel hot-electron injection at the drain junction as a fast but power-consuming programming mechanism. Erasure is achieved by Fowler-Nordheim injection from the floating gate towards the source junction. See FIG. 1. The main advantage of this cell is the small area, which makes it well-suited for high density applications (so-called bulk memory). The main disadvantages are the high processing complexity and the high power consumption (in order to compensate for the intrinsically low programming efficiency), and the presence of major reliability problems (overerase, soft-write and short-channel effects, drain disturb), which compromise the scalability of this memory concept. On the other hand, the conventional NOR array configuration (see FIG. 2)--which is commonly used for this type of memory--requires 1/2 contact per bit. This is a yield limiting factor at the considered ever-increasing densities (currently 16 Megabit). A contactless version of such an array has also been proposed, however, at the expense of a complicated bitline segmentation scheme and a lower programming and read-out speed.
The second class uses bi-directional Fowler-Nordheim tunneling and is essentially derived from conventional FLOTOX EEPROMs (see FIG. 3). The main advantage is the very low power consumption which is required for Fowler-Nordheim programming. Therefore, the programming voltages can be generated on-chip, and operation from a single supply voltage is obtained. The main disadvantages are the very high voltages (20V) to be switched on-chip and the corresponding reliability issues (oxide defects, junction breakdown), the large transistor area, and the low programming speed. A smaller area can, however, be achieved by increasing the processing complexity and by reducing the gate coupling coefficient at the expense of even higher programming voltages. A typical high-density configuration for these memories is the NAND configuration (see FIG. 4), which suffers from a very high access time in the order of microseconds.
Faster programming can be achieved by using page-mode programming techniques, which, however, complicate circuit design. Finally, the scalability of this concept is highly questionable, especially because of the limitations with respect to tunnel oxide scaling.
The third class of Flash memory transistors emerged only a few years ago and was meant to combine the advantages of the previous two classes. Although entirely different transistor structures have been proposed, they all aimed at increased programming efficiency. The High Injection Metal-Oxide-Semiconductor (or HIMOS) transistor, which is described in co-pending applications having Ser. Nos. 08/275,016 and 08/080,225, belongs to this last category and, more specifically, it combines a low development entry cost with the remarkable features of the enhanced injection mechanism, yielding a low-cost, single-supply voltage, fast-programmable Flash memory technology, which requires only moderate voltages on-chip, and which shows a high immunity with respect to soft-write, overerase, short-channel and drain disturb effects. See FIG. 5. The triple-gate structure and the specific operation modes of this cell allow the implementation into a dense contactless array which partially compensates for the somewhat larger transistor area. This renders the HIMOS transistor into an attractive candidate for medium-density, cost-effective Flash EEPROM applications.
Once a transistor concept has been defined in a given process technology, it has to be designed in such a way that a practical memory organization is obtained. Moreover, the transistor properties have to be exploited in order to optimize the density of the resulting memory array, taking into account the main circuit-related parameters, such as disturb conditions, read-out current, and capacitive and resistive loads for the periphery circuits. Therefore, the basic layout of the transistor depends strongly on how different transistors are to be interconnected in a circuit. This is where the term "memory cell" comes in: the memory cell, as opposed to transistor, is the practical layout of the transistor which is repeatedly copied through mirroring or translation along its symmetry axes in order to produce the full memory array.
The advantages of optimizing memory cells for contactless arrays in EPROM and EEPROM memories have long been recognized. Esquivel et al., "High Density Contactless, Self Aligned EPROM Cell Array Technology", IEDM 1986, describe the principle in a conventional EPROM array, while Gill et al., "A 5 Volt Contactless Array 256K Bit Flash EEPROM Technology", IEDM 1988, describe a similar contactless array for Flash memories.
It is also well known that asymmetrical Flash memory transistors, which often use source-side injection as a programming mechanism, are well-suited for the implementation in contactless arrays. U.S. Pat. No. 5,212,541, issued May 18, 1993 to Bergemont, discloses such a contactless array for cells programmed through source-side injection. However, the coupling line which is mentioned in Bergemont's patent is provided for every separate row in the array, which causes a considerable overhead with respect to the density of the array. Furthermore, when referring to FIG. 6 in the Bergemont patent, it is noted that all cells are oriented in the same direction, which implies a virtual ground array configuration. Therefore, the Bergemont configuration is incorrect, since the source line cannot be shared between adjacent cells in a row without alternating the position of the source and drain junctions of the memory cells along each row.
U.S. Pat. No. 5,280,446, issued Jan. 18, 1994 to Ma et al., and U.S. Pat. No. 5,284,784, issued Feb. 8, 1994 to Manley, both disclose other examples of a contactless array for source-side injection cells. These configurations, however, also provide a separate control line for every column or row, respectively. The area overhead caused by these configurations can be largely relaxed by the use of an additional polysilicon layer, however, at the expense of using a complicated triple polysilicon technology.
The present invention substantially circumvents these drawbacks by introducing a shared program line scheme, which substantially reduces the area overhead caused by the program gates of the memory cells without adding additional processing steps. The concept of using a contactless array for the HIMOS cell described in co-pending applications Ser. Nos. 08/275,016 and 08/080,225 is mentioned in these applications at page 15, lines 26-35. In the present application, however, this concept is further refined and optimized to produce a practical array organization.

Contactless array configuration for semiconductor memories

Interuniversitair Micro-Elektronica Centrum vzw


Center-to-center spacings (L.sub.1, L.sub.2, L.sub.3, L.sub.4, . . . ) of adjacent holes (5) in a hole chain (6) are set to values not less than five times a Blech length. This setting causes two parameters (MTF and .sigma.) of a logarithmic normal distribution used as a failure distribution for EM lifetime prediction to be constant independently of the center-to-center spacings, permitting stable EM lifetime prediction of the hole chain. Further, setting the length of each of extension interconnect wires (2) to a value not greater than the Blech length prevents voids from being created in the extension interconnect wires (2).

1. Field of the Invention
The present invention relates to a device for evaluating the reliability of interconnect wires for use in semiconductor devices and, more particularly, to a reliability evaluation technique suitable for lifetime evaluation of interconnect wires due to electromigration (referred to hereinafter as EM) failures.
2. Description of the Background Art
Conventionally, an evaluation TEG (test element group) is widely used for evaluating the reliability of holes such as contact holes and via holes used for interconnection of semiconductor devices. The TEG is constructed such that a hole chain, a pad, and an extension interconnect wire for connecting the pad and the hole chain are formed on an Si substrate.
The conventional evaluation TEG, however, has a situation in which it is difficult to say that the structures of the hole chain and extension interconnect wire are sufficiently optimized for a failure mode. This creates voids resulting from the EM in portions which are not to be evaluated such as a portion of the extension interconnect wire and a portion adjacent a hole connected to the extension interconnect wire portion, not in a portion of the hole chain which is desired to be evaluated, resulting in interconnect wire failure. For example, a hole-to-hole spacing of the hole chain which is as short as several micrometers might result in creation of voids in a portion of the extension interconnect wire provided for establishing a connection between one end of the hole chain and the pad, not in a portion of the hole chain, and accordingly the occurrence of the EM failure.
The voids in the portion which is not to be evaluated cause the EM lifetime of the hole chain to be overestimated or underestimated. It is hence necessary to prevent the creation of such voids.
The predicted value of the EM failure lifetime varies in some cases depending on the establishment of the structure of the hole chain itself. This causes difficulty in stable prediction of the EM lifetime.
Due to these various factors, the reliability evaluation in an EM failure mode using the conventional evaluation TEG fails to exactly predict the EM lifetime.
The above described problems are considered to result from the fact that the structure of the interconnect wires has not been optimized for the evaluation in the EM failure mode. Thus, similar problems are considered to arise in evaluation in other failure modes when a test structure is not optimized in relation to the modes.

Device for evaluating reliability of interconnect wires


Novel catalysts, substantially free of Cu and Zn, useful for the reformation of methanol and steam into H2 for use in hydrogen fuel cells and their use are described herein.

Methanol is an excellent hydrogen and energy source for fuel cells. Methanol's utility derives from its relative ease of storage and transportation as well as the relative ease with which it can be converted to H2 using a reformation reactor. In the reformation reactor, hydrogen is produced from methanol using a metal catalyzed steam reformation process. According to the chemistry of the reaction, and under appropriate conditions, methanol and water are reacted to form hydrogen and carbon dioxide.CH3OH+H2O→CO2+3H2  (1)
One drawback of the reformation process is the formation of by-product CO through a pathway distinct from hydrogen production. This by-product of the reformation process must be removed or "scrubbed" from the product H2 prior to introduction into a given fuel cell. Typically, this scrubbing process is achieved through water gas shift reaction. Alternatively, CO may be separated using a Pd or Pd alloy membrane. Pd and Pd alloy membranes, though, require high operating temperatures to be effective; thus, the reformer must be operated at a higher temperature, typically at about 400° C. Such high temperatures, however, require catalysts having excellent durability given that high temperature frequently adversely affects catalyst life.
The utilities of currently available catalyst are affected by these limitations. For example, commercially available copper-zinc catalysts (CuO—ZnO/Al2O3) cannot be used at temperatures above 250° C. due to sintering and deactivation. What is more, these catalysts need to be reduced prior to use in a reformer. A further limitation of copper-zinc catalysts is that they are pyrophoric, creating handling and storage issues.
Various attempts to improve CuO—ZnO catalyst formulations have been described in for example U.S. Pat. No. 6,576,217, as well as U.S. Patent Publication Nos. 2002/0051747, 2002/0169075, and 2004/0006915. The various improvements proposed in the noted documents include introduction of Zr, Al, Ce, or rare earth elements to the copper-zinc formulation.
Substitution of different elements for either Zn or Cu have also been proposed. For example, in U.S. Patent Publication No. 2004/0006915, a catalyst containing ZnO and chromium oxide but not copper oxide was disclosed for use for methanol steam reforming. Other modifications to copper-zinc catalysts include the substitution of Pd for Zn, as discussed in JP Application No. 2002263499; the substitution of Ag for Cu as discussed in JP Application No. 2003154270; the substitution of Cr for Cu as discussed in JP Application No. 2003160304; and the substitution of SiO2 for Zn as discussed in JP Application No. 2008043884. These formulations, however, have not resolved the inherent limitations present in Zn, Cu, or CuZn derived catalysts.
Recently, a non-CuZn base-metal catalyst, alumina supported FeCoNi, was described in U.S. Patent Publication No. 2007/0294942. This catalyst, however, requires expensive organometallic complexes and template molecules to achieve the desired crystal size, thus limiting its utility. Moreover, like copper-zinc catalysts, this base-metal based catalyst is prone to deactivation at high temperatures.
Various other Zn based methanol reformation catalysts are known. For example, U.S. Pat. No. 4,613,584 describes the utility and the formation of PdZn and PtZn alloys for methanol steam reforming. See also Iwasa et al., Applied Catalysis A: General, 1995, 125(1): 145-157 as well as U.S. Pat. No. 6,413,449.
PdZnZr based catalysts are described in U.S. Patent Publication No. 2001/0021469, while Pd/Pt—CuZn catalysts are described in U.S. Patent Publication No. 2002/0039965. These catalyst, though, also suffer from deactivation. For example, deactivations of alumina supported PdZn catalysts have been reported at 285° C. (see Pfeifer et al, Applied Catalysis A: General, 270 (1-2), 165-175, 2004) and even at 250° C. (see Kim, T., et al, Journal of Power Sources, 2006, 155, (2), 231-238). PdZnZr catalyst is further plagued by the potential leaching of Zn during the reforming process. The leached Zn may damage any separation membrane present, as well as the fuel cell itself.
Other known alloys suitable for methanol steam reformation include ZrCu, ZrAu, HfCu, ZrCo, and YNi. Despite their utility, these catalysts are difficult to prepare and require melting metal salt precursors. See e.g., U.S. Pat. No. 5,635,439.
Pd—Ga, Pd—In, Pt—Ga and Pt—In catalysts (Iwasa, Catalyst Letter 54, 1998, 119-123) as well as Pt—Ce/Fe/La— supported on alumina (U.S. Patent Publication No. 2007/0183968) have likewise been shown to be active for methanol steam reforming. These catalysts, too, require melting metal precursors or multi-step processes involving pre-reduction of Pt followed by sequential loading of other metals.
Thus, although the art describes many catalysts useful for methanol steam reformation, each of the variously known catalysts has at least one characteristic that renders the catalyst less than suitable for large-scale commercial use.
In view of the forgoing, it is an objective of the present disclosure to provide new catalyst formulations and processes for making these catalysts, that alleviate many or all of the failures of currently available methanol steam reforming catalysts. In particular, it is an objective of the present disclosure to provide air-stable catalysts for the reformation of methanol that operate continuously at at least about 350° C. and that are easily prepared without the need for melting or pre-reduction.


A semiconductor product includes a substrate having a substrate surface. A plurality of wordlines are arranged at a distance from one another and running along a first direction. A plurality of conductive contact structures are provided between the wordlines. The product also includes a plurality of filling structures. Each filling structure separates from one another two respective contact structures arranged between two respective wordlines. The two respective contact structures are arranged at a distance from one another in the first direction. In the preferred embodiment, the contact structures have a top side provided at a distance from the substrate surface and extends to the substrate surface. The contact structures at the substrate surface have a width along the first direction that is larger than a width of the top sides of the contact structures along the first direction.

Such a semiconductor product may be, for instance, a flash memory product comprising a plurality of memory cells like NROM (nitride read only memory) or alternative kinds of non-volatile memory cells (like floating gate cells). In a flash memory product, the memory cells are programmable individually selectively to the respective other memory cells. When information is deleted, all memory cells of the same particular sector are commonly deleted at the same time. The memory cells of the respective sector may be later reprogrammed individually.
The memory cells of a flash memory are arranged in a virtual ground array or in other array architectures. Each memory cell is connected to two respective bitlines running parallel to one another. In a virtual ground array each bitline is connected to memory cells arranged on opposed sides of the bitline. Connection between the bitlines and the memory cells is provided by contact structures that comprise first contacts called "local interconnect". The local interconnects are arranged in rows extending perpendicular to the direction of the bitlines. In a direction parallel to the bitlines, a bitline is connected to one respective local interconnect of every other row of local interconnects. Furthermore, in every other row, the local interconnects have a lateral offset relative to the lateral positions of the local interconnects of the other rows of local interconnects. Each bitline is connected to local interconnects of every other row (for instance of a first, third, fifth, etc., row) whereas the bitline is passing over memory cells of a second, fourth, sixth, etc., row of local interconnects without being connected to the local interconnects of the second, fourth and sixth rows.
In a virtual ground array, the bitlines are connected to the memory cells via contact structures that, according to prior art, comprise a first contact called "local interconnect". The local interconnects are contact hole fillings provided in a dielectric layer above a substrate. The local interconnects are wide via contacts having a main extension in a first lateral direction perpendicular to the direction of the bitlines. They serve to connect two line-shaped active areas to a bitline. The active areas are doped regions providing the source/drain regions and the channel regions and, in a virtual ground array, are formed in lines or stripes separated from one another by trench isolation fillings like shallow trench isolations (STI). The trench isolation fillings as well as the active areas are formed line-shaped seen from top view on the semiconductor substrate. When the bitlines are formed, they are positioned such that they are running parallel to the active areas but are, for instance, located at same lateral positions as the shallow trench isolation fillings, that is at centered lateral positions between two respective adjacent line-shaped active areas.
The local interconnects contacts, in direction perpendicular to the active areas, extend beyond the bitlines on opposed sides of the respective bitline. In particular, the local interconnects extend to the active areas next to the bitline positioned on opposed sides of the bitline. Typically, a local interconnect has a width being approximately three times the width of the bitline since the width of the active areas and the width of the trench isolation fillings between the active areas correspond to one another.
In order to connect the bitline to the local interconnects, which are much wider than the bitlines, bitline contacts (the "contacts to interconnect") are formed according to prior art. To this end, a dielectric layer is deposited and via contact holes are etched in the dielectric layer so as to expose a portion of an upper surface of the local interconnects. The contact holes in the second dielectric layer are then filled with conductive material. By planarizing the conductive material, the contacts to interconnect are formed. Subsequently, the bitlines are formed.
In the process of manufacturing the semiconductor product, a substrate is provided and a plurality of line-shaped active areas as well as a plurality of line-shaped trench isolation fillings disposed between respective two active areas are formed in the substrate. Subsequently, a layer stack comprising a bottom oxide layer, a charge-trapping layer like a silicon nitride layer, and a top oxide layer are deposited. Wordlines are then formed by depositing one or more conductive layers and a cap nitride layer for forming gate stacks. These layers are then pattered thereby forming a plurality of wordlines. Sidewall spacers are then formed on sidewalls of the wordlines in a conventional manner.
Thereby a plurality of wordlines arranged at a distance from one another and running, at least in a region of the substrate surface, along a first direction, are provided. In spaces left between respective two wordlines the contact structures (the local interconnects) are to be formed thereafter. Conventionally, a dielectric layer is deposited and etched so as to form a plurality of filling structures filling one respective longitudinal space between two respective wordlines. Furthermore, in a conventional process these longitudinal filling structures are patterned along the first direction, thereby etching a plurality of trenches at those positions where the contact structures (the local interconnects) are to be formed. Each trench extends through the complete thickness of the respective filling structure down to the substrate surface. Thereafter, conductive material is deposited and an upper position thereof is etched, thereby forming a plurality of contact structures in the trenches within the filling structures.
Thereby a semiconductor product is provided that comprises contact structures filled in vias, which vias are confined, on opposed sides along the first direction, by sidewalls of respective two portions of the filling structure (which portions have been separated from one another during trench etching). Along the second direction, the contact structures are confined by respective two wordlines (that is, by their spacers).
Each contact structure formed in this way contacts two active areas arranged at a distance from one another along the first direction. Typically, the width of the active area corresponds to the width of the trench isolation filling provided therebetween. The width of the contact structure in the first direction accordingly is approximately three times the width of an active area or of a trench isolation filling, along the first direction.
However, the exact value of the width of the contact structure along the first direction, that is in direction parallel to the main extension of the wordlines between which the contact structures are provided, varies with the vertical position within the contact structure. In particular, the width of the contact structure along the first direction, measured at the top side of the contact structure, usually is larger than the width of the contact structure along the first direction, measured at a bottom side of the contact structure. Conventionally, the width of the contact structure (that is its extension in the first direction) increases with increasing distance from the substrate surface. In a cross-sectional view the shape of the contact structure corresponds to a trapezium having its long base at the top side of the contact structure and having its short base on the substrate surface.
This shape of the contact structures result from the circumstance that the contact structures are etched into dielectric filling structures filling the spaces between the wordlines. Etching of the trenches to be filled with the contact structures is performed by dry etching, for instance by reactive ion etching. Due to the typical etching profile of this anisotropic etching technique, at the top side of the insulating filling structures the trenches are slightly wider than at the bottom of the insulating filling structures (that is on the substrate surface). The reason therefor is that the duration of contact between the etching component and the etched sidewall of the remaining portions of the insulating filling structure decreases with increasing depth of the trench.
Due to conventional lithographic patterning, microelectronic structures have lateral dimensions corresponding to the critical dimension. The magnitude of the critical dimension depends on the wavelength used for the specific technology of lithography. However, with a predefined critical dimension the lateral extensions of the microelectronic structures are defined.
In semiconductor manufacturing the risk of lateral misalignment occurs. Since a mask for etching the trenches in the dielectric filling structures may be misaligned along the first direction relative to the active areas, the trenches to be filled with the contact structures may be offset in the first direction with respect to the active areas to be contacted. Depending on the extent of such lateral offset, the contact interface surface between one of the two active areas to be contacted and the contact structure is less, in the first direction, than the critical dimension whereas the contact structure extends beyond the other active area in the first direction. Accordingly, any lateral offset in the first direction bears the risk of increased contact resistance between the contact structure (the local interconnect) and one of the two active areas to be contacted.
Furthermore, due to the sloped sidewalls of the contact structures seen in cross-sectional view parallel to the worldlines, the width of the contact structures, measured at the substrate surface along the first direction, is actually smaller than three times the critical dimension (at the top side the width of the contact structures exceed a magnitude of three times the critical dimension). Accordingly, even in the absence of any lateral offset in the first direction, the contact interface surface between the contact structure and each active area is smaller in the first direction than the critical dimension. Thereby the contact resistance between the active areas and the contact structures (the local interconnects) is further increased.

Method of forming contacts using auxiliary structures


An air conditioner with a direction changing device enabling safe handling of condensed water without causing reduction in direction changing capacity in a cooling-mode operation is provided. The air conditioner comprises a main body, air conditioning members provided in the main body for achieving a function of conditioning the air, an outlet grille located in a front side of the main body for directing air from inside the main body to outside the main body and a lateral flap placed in an opening of the outlet grille for changing the direction of air in the lateral direction. A part of the lateral flap is held by a mounting shaft. The lateral flap can be pivotally moved in the lateral direction about the mounting shaft. A convex portion is provided in a downwind end of the lateral flap. When the end portion of the lateral flap is moved either in the right or left direction, condensed water adhered to the lateral flap is gathered at the convex portion, then the condensed water gathered at the convex portion is transferred to a wall of the outlet grille, and flows out of a room through the main body of air conditioner.

In an air direction changing device of a conventional air conditioner, an end surface of a lateral flap provided in an outlet grille is cut off for handling condensed water during a cooling-mode operation.
A conventional direction changing device is described below by referring to the drawings.
As shown in FIG. 8, a vertical flap ill is located in an opening of an outlet grille 102 in an air conditioner 110, and a plurality of lateral flaps 101 linked with each other in an upwind side by a linking bridge are provided. As shown in FIG. 9, an end portion 104 located in the downwind side of a mounting shaft 103 of the lateral flap 101 is cut off for handling condensed water 106 during a cooling-mode operation.
However, with the conventional lateral flap 101 of such shape, when the lateral flap 101 is moved in the lateral direction during a cooling-mode operation, condensed water 106 is condensed in a surface of the lateral flap 101, as shown in FIG. 9. If the condensed water 106 drops outside from the opening of outlet grille, the condensed water 106 falls inside a room where the air conditioner 110 is placed. In order to solve this problem, the end portion 104 of lateral flap 101 in a downwind side of the mounting shaft 103, provided in a lower part of the outlet grille 102, is cut off. In this manner, the condensed water 106 adhered to the lateral flap 101 is guided toward the mounting shaft 103, moves along a lower portion of the outlet grille 102, and flows into a water collecting groove 108 in a front frame 107. However, this design incurs operating deficiencies because the lateral flap 101 is reduced in capacity of direction change, which is a primary function it should achieve, if a cut-off amount of the end portion 104 is significant. Also, if a cut-off amount of the end portion 104 is insignificant, the condensed water 106 falls inside a room.
It is an object of the present invention to solve these problems, and provide a lateral direction changing device for safely handling condensed water without reducing the direction changing capacity in a cooling-mode operation.
It is another object of the invention to provide a lateral direction changing device assuring no reduction in direction changing capacity in any operating mode of an air conditioner.

Matsushita Electric Industrial Co., Ltd.


A smart structure or an electronic package is formed by thermal spraying utilizing a plurality of masks positioned and removed over a work surface in accordance with a predetermined sequence. The masks correspond to cross sections normal to a centerline through the structure. Masks are placed above a work surface and sprayed with either at least one primary material to form at least one electronic component and a complementary material. In this manner, layers of material form a block of deposition material and complementary material. Then, the complementary material which serves as a support structure during forming may be removed.

There are numerous structures known as smart structures which contain electronic components that produce an electrical signal when stimulated. These components could be strain gauges, switches, thermocouples or other electronic devices. Conventionally, these components have been attached to an existing structure rather than being fabricated in place at the same time the surrounding structure is made.
Electronic packages are another structure in which electronic components are surrounded by another material. Electronic components ranging from an individual integrated circuit chip to an array of interconnected chips have been packaged in protective containers. These containers are often designed to provide more than weather proofing. They may include shielding from electro magnetic interferences, thermal cooling and shock absorption. Blocks of styrofoam having cavities into which electronic devices and components are placed are commonly used today. Plastic encapsulation is another means for protectively packaging electronic components.
Many electronic packages are designed so as never to be opened. In these packages conductors are provided to interconnect the electronic components. An external connector in the package allows one to utilize the package components. Sometimes sensors have been provided in these packages.
Traditionally, the art has first formed the electronic components, interconnected them on a board and placed this system in a housing which may then be filled with a nonconductive material. Each of these steps is performed independently and final assembly involves mechanical connections between boards and the system housing. This manufacturing approach limits packaging density, performance, reliability and shape and requires several assembly steps.
At one time circuit boards were made by hand wiring components mounted on a board. In addition to being a slow process, this manufacturing approach had performance, reliability, shape and size limitations. Many of these problems were overcome by printing processes for circuit boards. In this process one or more layers of material were deposited on a substrate and then circuitry and other features were formed by etching. This printing process, however, is useful for only a limited number of materials and cannot be used for forming several different materials in a single layer.
The prior art contains several other methods for creating objects by the incremental material build up of thin layers. However, such techniques have been used primarily for products other than electrical components. These processes include lamination, selective laser sintering, ballistic particle manufacturing, three-dimensional printing, stereolithography and near net thermal spraying. Lamination involves the simple process of cutting layers of a selected material and then bonding those layers together. The layers may be pre-cut to shapes corresponding to a cross section through the article to be created. Alternatively, standard shapes of material can be stacked and bonded together. Then, the assembled structure is cut or machined to produce the desired shape. In U.S. Pat. No. 4,752,352, Michael Feygin proposes a computer controlled method and apparatus for forming a laminated object. He provides a supply station, a work station for forming a material into a plurality of layers for lamination, an assembly station for stacking the layers in sequence into a three-dimensional object, a station for bonding the laminations to complete the formation of the three-dimensional object and a control station. In his patent, Mr. Feygin discloses a method in which the laminations are cut from a roll of material lifted, stacked and bonded under the direction of a computerized controller. The layers are bonded together by adhesive or brazing. This and other lamination techniques have significant disadvantages. The bond between layers is critical and limits the strength of the object. Moreover, lamination is suitable for only those materials which can be formed into thin layers which can be bonded together.
In laser sintering, a laser is used to cure a starting material into a certain configuration according to the manner in which the laser is applied to that material. Stereolithography is a more recent yet similar process which creates plastic prototype models directly from a vat of liquid photocurable polymer by selectively solidifying it with a scanning laser beam. An example of this method is described in European Patent 322 257. Both of these methods require a substantial amount of curable raw material. In both cases the laser must be carefully controlled to achieve the desired shape. In some applications, the laser typically does not fully cure each cross section. Rather, the laser cures the boundary of a section and then cures an internal structure or honeycomb that traps the uncured fluid. Thereafter, the article must be subjected to final curing under separate ultraviolet lights or heat treatment. Additional post processing, such as careful sanding and grinding, is required for making smooth, accurate surfaces.
In ballistic powder metallurgy beams of particles are directed to the coordinates of a three-dimensional object in a three-dimensional coordinate system. A physical origination seed to which the particulate matter is attracted is required. The process may use a beam of particles directed to the origination seed which builds the particles upward from that seed. Alternatively, one can use an energy beam which attracts the particulate matter already in the environment to the seed or another coordinate. Such a system is disclosed by William E. Masters in U.S. Pat. No. 4,665,492. This method cannot be used to make objects having undercuts therein without creating support structures at the same time. Normally, the support structures are created with the particle beam during the creation of the object. Such support structures must be removed by cutting, grinding or machining. Furthermore, the art has only been able to reliably deposit wax with this method. The usefulness of this method for other materials has not and possibly cannot be established.
Three-dimensional printing is another technique similar to ballistic powder metallurgy. One variation of this technique creates layers of particles to produce a three-dimensional image in much the same manner that an ink jet printer produces two-dimensional images. The technique relies upon thermal shock or drop on demand material delivery techniques. A thermal shock technique forms a particle by vaporizing a small area of the fluid directly behind the nozzle. The drop on demand nozzle includes a piezo electric element to constrict the cavity thereby forcing a drop past the nozzle plate. In both instances the material is directed to a work surface in a manner to build up the article. This technique can only be used for certain kinds of materials.
In another variation of three-dimensional printing a series of two dimensional layers are created by adding a layer of powder on top of a work surface The powdered layer is selectively joined where the part is be formed by ink jet printing of a binder material The work surface is then lowered and another layer of powder is spread out and selectively joined. The layering process is repeated until the part is completely printed. Following a heat treatment the unbonded powder is removed leaving the fabricated part. Although this technique has been proposed for metal, ceramic and plastic materials, it is limited to those materials to which a reliable binder can be applied.
The art has attempted to make objects by spraying layers of metal on a substrate. Problems have occurred in that the layers have tended to camber and possibly to peel apart from the substrate. Therefore, one must have a release agent or compatible substrate.
None of the just described incremental material layer build up techniques have been successfully used to make packaged electronic components or smart structures.
There is a need for a method to manufacture electronic packaging systems and smart structures by incremental build-up of material. The method and apparatus should be capable of producing articles having undercuts and irregular shapes.

Electronic packages and smart structures formed by thermal spray deposition


Apparatus and methods for regulating delivery of electrical energy to a lighting load are disclosed. An electrical waveform is received from a source of electrical energy. An integration value is generated based on a square of an amplitude of the received waveform. Electrical energy is delivered to the load until the integration value exceeds a threshold value. Thereafter, the delivery of electrical energy to the load is discontinued.

FIG. 1 depicts a typical dimmer circuit 10 comprising a source of alternating-current (AC) power, or power supply, 12, a dimmer 14, and a load 16. The load 16 may be a lamp set comprising one or more lamps adapted to be connected between the hot and neutral terminals of a standard source of AC power. The lamp set may include one or more incandescent lamps and/or other loads such as electronic low voltage (ELV) or magnetic low voltage (MLV) loads, for example.
The power supply 12 supplies an AC waveform to the dimmer 14. The dimmer 14 regulates the delivery of electrical energy from the power supply 12 to the load 16. The dimmer may include a controllably conductive device 18 and a control circuit 20. The controllably conductive device 18 may include an input 22 adapted to be coupled to the power supply 12, an output 24 adapted to be coupled to the load 16, and a control input 26. The control circuit 20 may have an input 28 coupled to the input 22 of the controllably conductive device 18 and an output 30 coupled to the control input 26 of the controllably conductive device 18.
A typical, AC, phase-control dimmer regulates the amount of energy supplied to the load 16 by conducting for some portion of each half-cycle of the AC waveform, and not conducting for the remainder of the half-cycle. Because the dimmer 14 is in series with the load 16, the longer the dimmer 14 conducts, the more energy will be delivered to the load 16. Where the load 16 is a lamp set, the more energy delivered to the load, the greater the light intensity level of the lamp set. In a typical dimming scenario, a user may adjust a control to set the light intensity level of the lamp set to a desired light intensity level. The portion of each half-cycle for which the dimmer conducts is based on the selected light intensity level.
The controllably conductive device 18 may include a solid state switching device, which may include one or more triacs, which may be thyristors or similar control devices. Conventional light dimming circuits typically use triacs to control the conduction of line current through a load, allowing a predetermined conduction time, and control the average electrical power to the light. One technique for controlling the average electrical power is forward phase control. In forward phase control, a switching device, which may include a triac, for example, is turned on at some point within each AC line voltage half cycle and remains on until the next current zero crossing. Forward phase control is often used to control energy to a resistive or inductive load, which may include, for example, a magnetic lighting transformer.
Because a triac device can only be selectively turned on, a power-switching device, such as a field effect transistor (FET), a MOSFET (metal oxide semiconductor FET), or an insulated gate bipolar transistor (IGBT), for example, may be used for each half cycle of AC line input when turn-off phase is to be selectable. In reverse phase control, the switch is turned on at a voltage zero crossing of the AC line voltage and turned off at some point within each half cycle of the AC line current. A zero-crossing is defined as the time at which the voltage equals zero at the beginning of each half-cycle. Reverse phase control is often used to control energy to a capacitive load, which may include for example, an electronic transformer connected low voltage lamp.
The switching device may have a control or "gate" input 26 that is connected to a gate drive circuit, such as an FET drive circuit, for example. Control inputs on the gate input render the switching device conductive or non-conductive, which in turn controls the energy supplied to the load. FET drive circuitry typically provides control inputs to the switching device in response to command signals from a microcontroller. FET protection circuitry may also be provided. Such circuitry is well known and need not be described herein.
The microcontroller may be any processing device such as a programmable logic device (PLD), a microprocessor, or an application specific integrated circuit (ASIC), for example. Power to the microcontroller may be supplied by a power supply. A memory, such as an EEPROM, for example, may also be provided.
Inputs to the microcontroller may be received from a zero-crossing detector. The zero-crossing detector determines the zero-crossing points of the input AC waveform from the AC power supply 12. The microcontroller sets up gate control signals to operate the switching device to provide voltage from the AC power supply 12 to the load 16 at predetermined times relative to the zero-crossing points of the AC waveform. The zero-crossing detector may be a conventional zero-crossing detector, and need not be described here in further detail. In addition, the timing of transition firing pulses relative to the zero crossings of the AC waveform is also known, and need not be described further.
FIGS. 2A and 2B depict example prior-art dimmed waveforms. Shown in FIG. 2A is a single-frequency AC waveform having an amplitude profile v1(t) during a first half-cycle TH and an amplitude profile v2(t) during a second half-cycle TH. The absolute value of peak amplitude during each half cycle is A. Thus, the AC waveform delivered to the dimmer is the same for both half-cycles. Because the dimmer conducts for the same amount of time, tC, each half-cycle, tH, the amount of energy delivered to the load during the second half-cycle will be the same as the amount of energy delivered during the first half-cycle. Though this is usually acceptable, amplitude changes in the AC waveform may cause fluctuations in the amount of energy actually delivered to the load from half-cycle to half-cycle (e.g., the light level may fluctuate).
Shown in FIG. 2B, is a single-frequency AC waveform having an amplitude profile v1(t) during a first half-cycle TH and an amplitude profile v2(t) during a second half-cycle TH, wherein the absolute value of peak amplitude during the first half cycle is A1 and the absolute value of peak amplitude during the second half cycle is A2. As shown, the absolute value of peak amplitude, A2, of the waveform during the second half-cycle is different from (e.g., lower than) the absolute value of peak amplitude, A1, during the first half-cycle. Because the dimmer conducts for same amount of time, tC, each half-cycle, the amount of energy delivered to the load during second half-cycle is different from (e.g., less than) the amount of energy delivered to the load during the first half-cycle. Hence, given a constant dimmer-conduction time, tC, during each half-cycle, TH, the root-mean-square voltage delivered to the load will change as the amplitude of the AC waveform changes.
In certain installations, such as cruise ships or other such marine vessels, for example, other loads may be driven from the same power source that drives the lighting. For example, a ship's engines may be driven by the same power source that drives the ship's lighting. As energy is delivered to the engines, the voltage waveform delivered to the lighting is often corrupted. Sometimes, the waveform varies wildly between one half-cycle and the next.
In such an installation, if the lighting is dimmed using a technique that provides for delivering electrical energy to the lighting for a fixed amount of time each half-cycle, the variations in the waveform result in varying amounts of energy being delivered to the load every half-cycle. Consequently, the lighting flickers. Such a condition is undesirable.
It would be desirable, therefore, if apparatus and methods were available to deliver roughly the same amount of energy every half-cycle, regardless of variations in the amplitude of the AC waveform from half-cycle to half-cycle.