A method and apparatus exercise a battery of an implantable medical device by determining whether a film is disposed on a portion of an electrode of a battery, discharging the battery a sufficient amount to reduce the film, and optimizing energy used during exercising the battery. The apparatus includes a battery having an electrode that develops a resistive film and a low deformation rate capacitor capable of storing a charge from the battery, the capacitor requiring few or no periodic discharges of the battery for reformation. The energy from the battery is periodically discharged into the low deformation-rate capacitor to reduce film buildup on the electrode.

Medical devices are used to treat patients suffering from a variety of conditions. Examples include implantable medical devices (IMDs) such as implantable pacemakers and ICDs, which are electronic medical devices monitoring the electrical activity of the heart and, when necessary, providing therapeutic electrical stimulation to one or more of the heart chambers. For example, a pacemaker senses an arrhythmia episode (i.e., a disturbance in heart rhythm) and provides appropriate therapeutic electrical stimulation pulses, at a controlled rate, to selected chambers of the heart in order to terminate the arrhythmia and restore the proper heart rhythm. The types of arrhythmias detected and corrected by pacemakers include bradycardia, which are unusually slow heart rates, and tachycardia, which are unusually fast heart rates.
Medical devices such as ICDs also detect arrhythmias and provide appropriate electrical stimulation pulses to selected chambers of the heart to correct the abnormal heart rate and/or rhythm. In contrast to pacemakers, however, an ICD can also deliver much stronger and less frequent pulses of therapeutic electrical stimulation (e.g., cardioversion and/or defibrillation therapy). This is because ICDs are generally designed to terminate episodes of cardiac fibrillation (e.g., episodes of rapid, unsynchronized quivering of one or more heart chambers) and severe tachycardia (e.g., very rapid but relatively coordinated contractions of the heart). To correct such arrhythmias, an ICD delivers a low, moderate, and/or high-energy electrical therapy to the heart.
The typical defibrillator or cardioverter includes a set of electrical leads, which extend from a sealed housing into operative contact with a portion of a heart. Within the housing are a battery for supplying power, one or more capacitors coupled to the battery and adapted to rapidly deliver bursts of electric energy via the leads to the heart, and monitoring circuitry for monitoring cardiac activity and determining when, where, and what electrical therapy to withhold or apply. The monitoring circuitry generally includes a microprocessor and a computer readable memory medium storing instructions not only dictating how the microprocessor answers therapy questions, but also controlling certain device maintenance functions, such as maintenance of the capacitors in the device.
With respect to ICDs, typically at least two capacitors are electrically coupled to the heart. One type of capacitor adapted for use in conjunction with an ICD includes aluminum electrolytic capacitors, although other types have been used as well. This type of capacitor usually includes sheets of aluminum foil and electrolyte-impregnated separator material. Each strip of aluminum foil is covered with an aluminum oxide, which insulates the foils from the electrolyte in the paper. One maintenance issue with aluminum electrolytic capacitors concerns the degradation of their charging efficiency after long periods of inactivity. The degraded charging efficiency, which stems from instability of the aluminum oxide in the liquid electrolyte, ultimately requires the battery to progressively expend more and more energy to charge the capacitors prior to delivering cardioversion or defibrillation therapy.
Thus, to repair this oxide degradation, microprocessors are typically programmed to reform the degraded (or deformed) aluminum oxide. The capacitor reform process typically involves at least one capacitor charge-discharge cycle. For example, an aluminum capacitor is typically rapidly charged and held at or near a rated or maximum-energy voltage (the voltage corresponding to maximum energy) for a time period (e.g., on the order of less than about one minute), before being discharged internally through a non-therapeutic load. In some cases, the maximum-energy voltage is allowed to leak off slowly rather than being maintained; in others, it is allowed to leak off (or droop) for 60 seconds and discharged through a non-therapeutic load; and in still other cases, the voltage is alternately held for five seconds and drooped for 10 seconds over a total period of 30 seconds, before being discharged through a non-therapeutic load. These periodic charge-hold-discharge (or charge-hold-droop-discharge) cycles for capacitor maintenance are referred to as "reforming." Unfortunately, reforming aluminum electrolytic capacitors tends to reduce battery life.
The aluminum electrolytic capacitors used in early ICDs exhibited relatively low energy density (<2 J/cc) and therefore contributed a large amount to the overall device volume. To decrease capacitor and ICD volume, medical device designers, suppliers and manufacturers developed implantable wet-tantalum capacitors. In addition to having a higher energy density (>4 J/cc) such capacitors exhibit a slightly lower rate of de-formation, and therefore require less energy to effectively reform the oxide layer of the capacitor. More recently, wet-tantalum capacitors that require very little or no reformation have been developed. To wit, non-provisional U.S. patent application Ser. No. 10/448,594 filed 30 May 2003 and entitled, "WET TANTALUM CAPACITOR USABLE WITHOUT REFORMATION AND MEDICAL DEVICES FOR USE THEREWITH" and non-provisional U.S. patent application Ser. No. 10/431,356 filed 7 May 2003 entitled, "WET TANTALUM REFORMATION METHOD AND APPARATUS" are directed to such subject matters, and the contents of each are hereby entirely incorporated by reference herein.
While substantially eliminating the need for capacitor reformation, these low or non-reformation capacitors may contribute to energy-management issues within an ICD. For example, capacitors not requiring reformation can cause the ICD battery to operate without a high current pulse for a long period of time (e.g., months to years). Most implantable device batteries are comprised of Li/SVO (lithium/silver vanadium oxide), a lithium anode, and a silver vanadium oxide cathode. When there is an extended period between high voltage therapies or other high current events, the battery can develop a deleterious resistive film on the surfaces of an anode disposed within the battery. First, the lithium anode forms its own passive film by reaction with electrolyte. This film, commonly referred to as the solid electrolyte interface (SEI), is typically harmless since it comprises an electrically conductive film. However, the SEI film can increase in thickness over time, and thus contribute increased electrical resistance to the operative circuitry of an ICD.
Second, the SVO material also forms a film on the lithium surface. This is equally undesirable as it results in further increases in film thickness and in electrical resistance over time. Generally, these problems are resolved during the reformation process or as a result of one or more high current pulses, during which the resistive film will dissipate (or "slough off") thus providing a fresh lithium surface.
However, if an IMD uses a capacitor that does not require reformation, then over time the above-mentioned SEI films can be expected to only increase in size and electrical resistance. If this occurs, subsequent high-current pulses will suffer from "voltage delay" due to the increased resistance of the films. Voltage delay occurs when the highly resistive SEI film causes the voltage delivered during a high current pulse to be lower than a desired magnitude (e.g., less energy than that which would be delivered in the absence of resistive SEI film). This voltage delay will occur until the film sloughs off the lithium. Voltage delay is undesirable in that it causes the battery to take longer to charge the capacitor and reduces battery life. For example, if the battery voltage is lower during the high current pulse, it is delivering less energy per unit time. Therefore, it takes more charge out of the battery to provide the pulse and it takes longer to charge the capacitor. This problem is exacerbated the longer the battery goes without a capacitor reformation or a high current pulse.
Another problem is created if the battery voltage is too low. In most ICDs there is a minimum voltage or a voltage floor representing the voltage necessary to continue to power the ICD circuitry while the capacitor is being charged. Generally, if the battery voltage drops below this voltage floor, a power-on-reset (POR) can occur where the ICD will suspend any therapy currently in progress. To combat this problem ICDs will generally implement a safety feature, which prevents the battery voltage from dropping below the voltage floor by lowering the current drawn from the battery when the battery voltage approaches the voltage floor. However, by drawing less current from the battery the process of charging the capacitor is lengthened. This is undesirable as it is commonly accepted that the odds of survival or recovery from a potentially lethal arrthymia such as ventricular fibrillation (VF) decrease significantly as the amount of time taken to deliver a cardiac therapy to terminate an episode of VF increases. A voltage delay may exacerbate this problem in two ways. First, the voltage delay would increase the time required to charge the capacitor by reducing available battery power. Second, a voltage delay may cause the battery voltage to drop below the voltage floor thus initiating the POR safety feature, further reducing available battery power and increasing capacitor charge time. This could potentially prevent an appropriate therapy from even being administered as some devices will either cease charging, or deliver a reduced energy after a predetermined charge interval.
Yet another potential adverse impact of voltage delay is reduced device longevity. Typically ICDs are designed to declare the Elective Replacement Indicator (ERI) when the background voltage of the battery (voltage in the absence of capacitor charging) reaches a predetermined level. However, most devices incorporate a secondary mechanism for declaring ERI when the capacitor charge time reaches a predetermined, excessively high level. In the event that voltage delay results in such an excessively long charge time, these devices will trigger the ERI well before battery depletion, significantly reducing the longevity of the ICD. Therefore, a voltage delay not only delays the delivery of a cardiac therapy it also has an impact on the overall device operation.
In prior ICDs the energy required to reform the capacitor was much greater than that required to remove the anode film from the battery, and therefore dominated any increase in capacitor charge time. Furthermore, the need to frequently reform the capacitor provided the required periodic conditioning of the battery necessary to minimize the effects of voltage-delay. However, now that capacitors needing little to no reformation have been developed, the potential exists for voltage-delay to become substantial, resulting in extended capacitor charge times when long periods of time pass between capacitor charging or other high current drain events driven by the battery. Changing trends within the industry may further exacerbate this. As ICDs have evolved, detection algorithms and therapies have become more sophisticated. As a result, devices are more frequently treating potentially fatal arrhythmias with alternative low-energy therapies (e.g., so-called anti-tachycardia pacing or "ATP"), thereby dramatically reducing the number of high-energy therapies being administered. In addition, indications for ICD implantation have been expanded to include patients who are expected to require only very few high-energy cardioversion or defibrillation therapies over the life of the device.

Apparatus and method for exercising a battery for an implantable medical device


A system and method for the manipulation of nanofibers using electrostatic forces. The nanofibers may be provided in a liquid medium, and the nanofibers may be nano-scale (i.e. measured in nanometers). The process is sensitive to the charge properties of the nanofibers (charge could be inherent to material or the charge can be induced into the material through electrochemical means), and therefore may be used to sort or classify particles. The nanofibers may also be aligned according to electrical fields, and thus anisotropic effect exploited. Devices produced may be conductors, semiconductors, active electronic devices, electron emitters, and the like. The nanofibers may be modified after deposition, for example to remove charge-influencing coatings to further enhance their performance, to enhance their adhesion to polymers for use as composite materials or result in the adhesion of the material at the proper location on a variety of different surfaces.

Nanofibers are a class of materials that have a variety of uses. These include: fillers for composite materials; electron emitters in vacuum devices; semiconductors, having properties suitable for high performance transistors (better than silicon, gallium-arsenide and other material); structural composites; etc. Typical production methods produce heterogeneous mixtures comprised of superfluous material, conductive and semi-conductive (quasi-insulative) fibers, and a large variability in fiber diameter and length. These materials can be long and highly anisotropic in shape and can be very difficult to handle in a dry state.
Some materials of interest are carbon nanotubes (CNT's). This includes single and multi walled varieties ("species") as well as conductive ("metallic") and semiconductive species and also extends to other conducting and semiconducting nanowires and nanofibers.
For example CNT's are grown from the gaseous phase in processes generally called chemical vapor deposition (CVD) and variations thereof. Other manufacturing techniques include the ARC method and laser ablation. Once produced these nanotubes are very small when compared to other particulate matter used in the electronics, structural composite, medical, pharmaceutical manufacturing today. It may be instructive to consider that a "large" single walled CNT may be 10 microns long by 2 nm diameter. By comparison, a "small" dry toner particle for a standard copy machine is usually 8 to 10 microns average diameter, and quite spherical. Recently, high quality color electrostatic printing machines like the NextPress 2100 have started to use "smaller" toner particle of approximately 5 micron diameter which are quite difficult to handle in the dry state and must be suitably coated in order to facilitate handling. When working with very small particles it is often desirable to disperse the particles in a liquid media.
Most of the techniques used to manufacture these nano-materials result in an agglomeration of material. For instance when growing CNT's, one often finds single and/or multi walled species coexisting with other materials such as amorphous carbon, carbon nano-particles and other material. In order to use CNT's for various potential commercial applications it is necessary to separate the various species from one another and to separate those species possessing different characteristics (e.g. electrochemical properties, magnitude of conductivity etc). The process of separation is often referred to as purification. Current purification techniques have only achieved limited success. CNT's have a wide range of properties that make them versatile material for numerous commercial applications. For example CNTs: are excellent conductors; conducting electricity better than copper; conducting heat better than diamonds. They are 100 times stronger than steel at 1/16 the weight and have carrier mobilities 100 times greater than silicon—resulting in better high frequency transistors for electronic parts. They also have desirable magnetic properties. In order to take full advantage of these various properties it becomes important to separate one species of CNT from the other.
Some of the major hurdles confronting the industry are; how to separate conductive (metallic) from semi conductive species, and how to manipulate, align and accurately place these materials in a cost effective manner, particularly given their small size and acicular geometry (0.7 nanometer×1-50 micron). While some manipulation and placement techniques have achieved modest success, there are very few (if any) scalable techniques that have resulted in the ability to align and accurately place one or more nanofibers and/or CNT in an orderly manner at a target location. Current placement techniques include mechanical manipulation via "nano-tweezers", printing inks via ink jet systems, and dispensing small drops of the nano-material contained in a liquid through pipettes. Most of these techniques have demonstrated at best satisfactory results, are generally expensive, difficult to scale, and/or have performance limitations, for example.
Given the wide range of properties, CNTs are being considered for numerous commercial and industrial applications. CNT related discoveries have spurred other work in semi-conducting nanowires. Nano-wire species of various types can yield superior electronic performance to that of bulk, single crystal material. This has led to the desire to understand and classify these materials as well as discover new ways to manufacture, process, and manipulate them. For example for high performance transistor manufacture and other applications requiring high performance semiconducting parts, nanowires comprised CNT's and other compounds such as Cadmium selenide, Indium arsenide/phosphide, Gallium Indium Phosphide, Gallium Arsenide, Gallium Nitride, and Silicon Carbide among other compounds as well as pure Silicon are applicable to the techniques which we intend to describe.
Another issue that confronts industry is the ability to print useful electrically conductive materials. In general printable conductive inks offer insufficient conductivity while nano powder inks offer insufficient thicknesses to be commercially usefully. For example conductive traces produced with silver filled resin inks produce structures which have about 5% of the conductivity of traces made of equivalent solid metal (e.g. etched aluminum or copper foil). Nano particle inks can achieve 20% to 30% of the conductivity of comparable solid metals but the traces are very thin often less than 500 nanometers in thickness and require a sintering step typically at temperatures of 150 C for approximately 30 minutes. Neither of these solutions would produce sufficient conductivity for most electrical applications. Hybrid circuit technology (e.g. silver filled glasses) can achieve acceptable conductivity but thermal processing often occurring at temperatures ranging from 500 C to 900 C make this technology unsuitable for many different types of substrates.
See, U.S. Pat. No. 6,781,612, and NIP-19 Conference Publication entitled—"Electrostatic Printing of Functional Toner Materials for Electronic Manufacturing Applications", IS&T NIP Conf, New Orleans, October 2003, expressly incorporated herein by reference.
U.S. Pat. No. 6,781,612 teaches that typical range of toner bath conductivity is of the order 10 to 100 pico mho/cm (10+11 to 10+10 Ω·cm resistivity), and up to 169 pico mho/cm (18 hertz test that measures back and forth flow of electrons, ions, and charged toner particles). A typical toner base is Isopar® G, though Isopar® H and L are also employed. ISOPAR® is the brand name of Exxon for eight grades of high-purity isoparaffinic solvents with narrow boiling ranges.

System and method for the manipulation, classification sorting, purification, placement, and alignment of nano fibers using electrostatic forces and electrographic techniques


A system and method relates to displaying a vehicle surrounding with an adjustable point of view, including at least one sensor device on the vehicle, a processor, and a display. The sensor device is configured to measure distances to objects of the vehicle surrounding. In addition, the processor is configured to generate a three-dimensional environment map based on the measured distances of the sensor device. Further, the display is configured to display the three-dimensional environment map having an adjustable point of view based on a particular driving situation.

A vehicle generally has a number of zones around the vehicle that are not visible to a driver either by direct line of sight or by the use of mirrors. During various driving situations, however, it may be necessary for a driver to view these zones in order to identify potential obstructions or obstacles, such as other vehicles, pedestrians, street signs or posts, and many other possible obstructions or obstacles.
In order to improve the visibility of particular zones around the vehicle, one or more cameras may be installed in order to view the vehicle surrounding. The images captured by the cameras of these systems are typically viewable on a display installed in the instrument panel of the vehicle. Then, the driver may have a better understanding of zones around the vehicle that are hidden from direct view or view by the use of mirrors.
Often, however, the images captured by the cameras of these systems have an unnatural appearance that may be difficult for a driver to understand. For example, cameras installed around a vehicle may utilize wide angle optics. Although these wide angle optics may allow the cameras to capture a larger area of the vehicle surrounding, they may also create distortion in the images. Thus, a driver may have difficulty understanding the vehicle surrounding or judging distances to objects in the images of the vehicle surrounding because of the distortion. For example, FIG. 2 shows a representative drawing of a typical point of view from a rear view camera system using wide angle optics while driving a driven vehicle 8 on a roadway 9. As can be seen from FIG. 2, the image of the rear view shows the roadway 9 and a following vehicle 10 behind the driven vehicle 8. However, this image is highly distorted, making it difficult to accurately judge distances to objects within the image.
In addition, cameras may be mounted at locations around the vehicle that are not intuitive to a driver. Thus, a driver may have difficulty understanding the perspective of the images or judging distances to objects in the images of the vehicle surrounding because of the unexpected mounting locations of the cameras.
For example, when reversing into a parking spot, a driver viewing an image from a rearward facing camera using wide angle optics may have difficulty understanding the perspective of the image or judging the distances to obstacles, such as pillars, other vehicles, and curbs, due to distortion and/or unexpected mounting locations of the cameras.
Further, FIG. 3 shows a representative drawing of a typical point of view from a side view camera system using wide angle optics while performing a parallel parking operation of a driven vehicle 8. As can be seen from FIG. 3, the image of the side view shows a parallel parking spot 11, a sidewalk curb 12, and a parked vehicle 13 behind the driven vehicle 8. However, this image is highly distorted, making it difficult to accurately judge distances to objects within the image.
In order to minimize the effects of unusual points of view, systems having cameras may also include sensors installed in various locations. These sensors may provide additional information to aid a driver in understanding the images captured by the cameras. For example, the additional sensors may measure distances to objects in the captured images.
Other systems may utilize cameras with wide angle optics but display only portions of the images to reduce the confusing effects of wide angle fields of view. In addition, some systems may indicate to a driver the measured distances graphically and numerically, such as by the use of labeled graphic lines superimposed on the images, so that a driver may better judge distances to objects in the images.
Japanese Published Patent Application No. 2001-224013 describes a drive support system that visually displays distance information between a vehicle and an obstacle. The visual display may be from a manually-specified perspective to easily view the relative positions of the vehicle and the obstacle. In addition, the obstacle may be color-coded based on the distance to the vehicle, in order to further visually display the distance information.
German Published Patent Application No. 10 2005 002 636 describes a system that combines video data and distance data by a coordinate transformation from a camera coordinate system to a distance coordinate system, such that the video data and distance data are aligned in a single coordinate system.
U.S. Patent Application Publication No. 2003/0088361 describes a system including an image-measured distance detection device for detecting distance data, and a laser-measured distance detection device for detecting distance data. In addition, a three-dimensional object recognition means recognizes an object in front of the vehicle based on the distance data from both the image-measured distance detection device and the laser-measured distance detection device.
German Published Patent Application No. 31 06 100 describes an obstacle warning device in which the obstacles are color coded depending upon the obstacle distance or obstacle speed.
U.S. Patent Application Publication No. 2003/0035050 describes a driving assistance display apparatus for displaying an image from a wide angle camera on a single screen so that a driver can intuitively understand the image. In this regard, the display apparatus splits the single screen into a plurality of sub-screens corresponding to inner faces of a polyhedron.
U.S. Patent Application Publication No. 2002/0181803 describes a perspective projection image creation system including an optical system, an imaging section, an image transformation section, a scale model creation section, an image combining section, and a display section. In addition, the image transformation section transforms the image data to a perspective projection having a projection center at a focal point of a hyperboloidal mirror of the optical system. Further, a first omnidirectional vision sensor is positioned at the right front of the car, and a second omnidirectional vision sensor is positioned at the left rear of the car.
U.S. Patent Application Publication No. 2006/0088190 describes a driving support system including a plurality of image taking devices that take images of areas around a vehicle. Then, an image processing unit performs a predetermined coordinate transformation to produce a virtual image viewed from a virtual viewpoint.
U.S. Patent Application Publication No. 2007/0003108 describes an image display device having plural cameras for capturing plural images. Then, the image display device forms a bird's eye view showing the vehicle surroundings. Further, a driver may select a view of one of the plural cameras. In addition, a contactable region may be flickered or highlighted based on the distance or approaching speed of the obstacle.
Japanese Published Patent Application No. 2004-274114 describes an image display apparatus that displays a viewpoint-converted image. The apparatus may also display a warning line, or other alarm display, based on a distance to an obstacle.

System and method for displaying a 3D vehicle surrounding with adjustable point of view including a distance sensor


A hierarchical control for an integrated voltage regulator may include a voltage regulator circuit with a plurality of parallel voltage cells, with each of the cells having a plurality of phases of interleaved voltage converters, and a feedback control associated with the cells to set identical current references for the phases. A multi-rail embodiment has a plurality of parallel voltage regulator circuits each with a plurality of parallel voltage cells, with each of the cells having a plurality of phases of interleaved voltage converters, and a feedback control associated with the circuits to sense parameters of the circuits and set identical parameter references for the phases.

A voltage regulator (VR) circuit generates a voltage rail at a rated voltage and current. It consists of several voltage regulator cells that function in parallel. Each of these cells further comprises several interleaved phases of DC-DC converters. There is a feedback control topology associated with each of these cells.
Such a common VR topology senses the load current and sets identical current references for all the phases within the cell. It also generates the delayed duty cycles for each of these phases required for interleaved operation. Conventionally, each of these cells in a circuit is implemented to share the load current equally. This results in a power efficiency that is a strong function of the load, resulting in low efficiency under low load conditions. Maximum efficiency is achieved at a certain load condition and any other load condition results in low power efficiency.
Attempts to improve efficiency in isolated power supply modules over a broader range of load conditions, such as by switching cells on and off, has proven to be of limited benefit. Such power supply modules (cells) must be discretely implemented and are limited to a few in number. Control requires the use of fast analog ICs since the number of power supply units operated in parallel is less. In integrated implementation, several tens of VR cells may need to operate in parallel. Extending such an implementation to an IVR application is not practical Lacking in the prior art is a simple power circuit with a hierarchical control for improving efficiency and optimizing performance under all load conditions in an integrated VR of many cells.
Although the drawings and following description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly.

Hierarchical control for an integrated voltage regulator


A self-propelled wheelchair (1, 101) comprising a frame (2, 102) supporting a seat (3, 103), two drive wheels (5, 105) mounted to the front of the frame, a prime mover mounted to the frame so as to drive the two drive wheels. The wheelchair having at least one castor wheel (7, 107) mounted to the rear of the frame and pivotal about a substantially vertical axis (Y), the frame being height adjustable in such a manner that when the frame is lowered, the seat is simultaneously tilted backwardly. The frame is provided with an anchoring mechanism (116) which allows the wheelchair to be releasably anchored to an anchoring element (119) secured to the floor.

There are many different types of wheelchairs available to handicapped persons who desire mobility and the ability to use motor vehicles. By providing handicapped persons with wheelchairs that can be loaded into a vehicle, they can experience a high degree of mobility and independence. Those handicapped persons who are able to operate wheelchairs usually have the ability to operate vehicles as well, but have great difficulty in entering and exiting vehicles.
There have been many prior art wheelchairs and apparatus for lifting them into and out of automobiles while the handicapped persons remain seated thereon during the movement of the wheelchairs. One such known wheelchair lifting apparatus is shown in U.S. Pat. No. 5,466,111 which discloses a height adjustable wheelchair which is lifted into a vehicle by an apparatus fitted to a side entry door of a vehicle. The vehicle has the driver's seat removed such that the wheelchair sits in front of the steering wheel and locked into place on the floor of the vehicle. There are many other types of wheelchair arrangements which allow a wheelchair to be secured at the driving position however they suffer from a number of disadvantages. They are either difficult to load into vehicles and the seats are not suited to the height and angle requirements of that expected when positioned in the vehicle. In recent times flat floor vans have been modified for use by disabled persons. In order to enter the van a disabled person within a wheelchair generally enters from the rear access door. As the van typically has a substantially flat floor the disabled person is able to manoeuvre the wheelchair to the appropriate driving position near the steering wheel. The wheelchair is typically locked into position by a locking mechanism fitted to the floor of the van. A problem associated with such arrangements is that in order to accommodate the wheelchair, such a van must be of the type that has a relatively high roof. Such vans are typically used for commercial applications and are sometimes not desirable as a passenger vehicle. In recent times a number of vans have come onto the market which have a medium to low roof. Whilst these vans have rear access and a substantially flat floor which is suitable to receive an electric wheelchair, the low to medium height roof makes it difficult for a disabled person to enter the vehicle and then safely drive the vehicle with enough clearance between their head and the roof.
The present invention seeks to provide a wheelchair which has height and seat adjustability to suit the wheelchair for use with various sorts of vehicles.


Disclosed are devices, systems and methods employing a directional antenna with a single rotational degree of freedom and using multiple signal-quality measurements to define best orientation with respect to a remote communication point and to align the antenna along the highest-signal-quality path. This simplifies alignment upon installation and facilitates higher signal levels, resulting in more reliable communication and higher data throughput.

Field: The present disclosure relates in general to an antenna and, in particular, to devices and methods for orienting a directional antenna array.
As wireless communications proceed toward realization of next-generation wireless communications infrastructure, millimeter-wave (mmW) and near-millimeter-wave frequencies will play a foundational role in 5G systems because of the massive bandwidth available to support high data rates and greater throughput demanded by end users.
Compared to lower frequency bands currently in use, a major drawback associated with these high frequencies is high propagation loss (which results in shorter travel distance), poor building penetration, as well as environmental and atmospheric absorption which may further limit travel distance and communications integrity. Such systems require a greater number of base stations to cover a given area as well as numerous high-gain customer premises equipment (CPE) antennas to ensure reliable, high data-rate communications.
However, the extremely short wavelengths of millimeter-wave signals make it feasible for very small antennas to concentrate signals into highly-focused beams with enough gain to overcome propagation losses. The highly focused beams associated with these systems make the already-formidable effort associated with achieving accurate alignment of antennas that much more difficult. What is needed are easily-aligned antenna systems along with alignment methods that together reduce the time, difficulty and overall costs associated with installation and alignment.


A hopper having a passage through which a medicine can be passed downward is provided. A part of a lower portion of the hopper is a deformable portion having flexibility, and the deformable portion is deformable so as to open and close the passage. According to this configuration, the deformable portion that is a part of the hopper is deformed to open and close the passage. Thus, there is no portion such as an opening and closing plate on which the medicine remains, thereby preventing a gap in which the medicine remains from being formed in the hopper, and preventing the medicine from easily remaining in the hopper.

A medicine dispensing and packing apparatus mounts therein a medicine supply apparatus. The medicine supply apparatus includes a hopper. The hopper has a passage through which a flowable medicine such as a powder medicine or a pill can be passed downward (for example, Patent Document 1).
The hopper described in Patent Document 1 includes a supply container that can once store a supplied medicine such as a powder medicine. A lower end of the supply container is open. The supply container includes an opening and closing plate, which can close or open an open portion, supported by a hinge. The medicine can be taken out from the supply container by moving the opening and closing plate.

Hopper and medicine supply apparatus including the same


A phase shift mask comprises a transparent substrate having a patterned opaque material layer formed thereupon to form a non-transmissive region of the transparent substrate and an adjoining transmissive region of the transparent substrate. A pit is formed within the transmissive region of the transparent substrate. The pit has a stepped sidewall such as to provide the phase shift mask with enhanced optical performance. The phase shift mask may be fabricated employing a self aligned method.

1. Field of the Invention
The invention relates generally to photomasks employed for fabricating microelectronic products. More particularly, the invention relates to phase shift photomasks employed for fabricating microelectronic products.
2. Description of the Related Art
Microelectronic products are formed incident to successive photolithographic processes that are employed for forming microelectronic devices and patterned microelectronic structures over microelectronic substrates.
The successive photolithographic processes employ photomasks for purposes of exposing blanket photoresist layers when forming patterned photoresist layers. In turn, the patterned photoresist layers are employed for forming the microelectronic devices and patterned microelectronic structures. Of the types of photomasks that may be employed when fabricating microelectronic products, phase shift photomasks are particularly desirable insofar as phase shift photomasks employ photoexposure light phase shifting such as to provide enhanced resolution of photoexposure light and thus enhanced resolution of patterned photoresist layers. Of the types of phase shift photomasks that may be employed when fabricating microelectronic products, alternating phase shift photomasks are common. Alternating phase shift photomasks are related to conventional photomasks that employ a patterned opaque material layer upon a transparent substrate to provide alternating transmissive regions and non-transmissive regions of the transparent substrate. However, alternating phase shift photomasks also employ a pit within alternating transmissive regions of the transparent substrate separated by the patterned opaque material layer. The pit is typically formed of a depth to provide a 180 degree phase shift of a photoexposure light beam for adjacent transmissive regions when employing the phase shift photomask.
While alternating phase shift photomasks are common and highly desirable in the microelectronic product fabrication art, they are nonetheless not entirely without problems. In that regard, while alternating phase shift photomasks do provide enhanced resolution of photoexposure light, they nonetheless also often provide the enhanced resolution with attendant optical asperities, such as ghost images.
It is thus desirable to provide phase shift photomasks with enhanced optical performance. The invention is directed towards the foregoing object.

Multi-step phase shift mask and methods for fabrication thereof

Taiwan Semiconductor Manufacturing Co., Ltd


A computer system includes a plurality of processor modules coupled to a system bus with each of said processor modules including a processor interfaced to the system bus. The processor module has a backup cache memory and tag store. An index bus is coupled between the processor and the backup cache and backup cache tag store with said bus carrying only an index portion of a memory address to said backup cache and said tag store. A duplicate tag store is coupled to an interface with the duplicate tag memory including means for storing duplicate tag addresses and duplicate tag valid, shared and dirty bits. The duplicate tag store and the separate index bus provide higher performance from the processor by minimizing external interrupts to the processor to check on cache status and also allows other processors access to the processor's duplicate tag while the processor is processing other transactions.

This invention relates generally to computer systems and, more particularly, to computer systems with a cache memory.
As it is known in the art, modern computer systems use various technologies and architectural features to achieve high performance operation. High performance capabilities can be achieved in computer systems which employ several computer central processing units (i.e., CPUs or processors) arranged on modules in a multiprocessor system configuration. In addition to CPU modules, such a multiprocessor system also includes several I/O modules and memory modules, all coupled to one another by a system bus. The CPUs generally perform co-operative or parallel processing as well as multi-tasking operations for execution of several applications running simultaneously, to provide dramatically improved processing performance. The capabilities of the overall system can be also enhanced by providing a cache memory for each one of the CPUs in the computer system.
A cache memory is a relatively small, yet relatively fast memory arranged in close physical proximity to a processor. Cache memory is generally used to store a subset of the information stored in the main memory or disk. The cache memory generally includes a store to store the actual data as well as a tag store to store tag addresses. The tag store also includes status bits of the cache blocks such as valid and shared.
Use of a cache memory is based on a principle that when a processor accesses a location in memory, there is a high probability that the processor will continue to access memory locations surrounding the accessed location for at least a certain period of time. With cache memory a preselected data block from the relatively slow access time main memory is fetched and stored in the relatively fast access cache memory. Accordingly, as long as the processor continues to access data from the cache memory, the overall speed of operation of the processor is maintained at a level significantly higher than would be possible if the processor had to arbitrate for control of the system bus and then perform a memory READ or WRITE operation, with the main memory module, for each data access.
The capabilities of the multiprocessor computer system can be further enhanced by sharing main memory among the CPUs and by operating the system bus in accordance with a SNOOPING bus protocol.
In shared memory multiprocessor systems, it is necessary that the system store a single, correct copy of data being processed by the various processors of the system. Thus, when a processor writes to a particular data item stored in its cache, that copy of the data item becomes the latest correct copy of the data item. The corresponding data item stored in main memory, as well as copies of the data item stored in other caches in the system, becomes outdated or invalid.
In a write back cache scheme, where a processor writes to it's cache, the data item in main memory is not updated until the processor requires the corresponding cache location to store another data item. Accordingly, the cached data item that has been modified by the processor write operation remains the latest copy of the data item until the main memory is updated. In order to maintain coherence, it is, therefore, necessary to implement a scheme to monitor READ and WRITE transactions on the system bus and insure that modified data is delivered from a processors's cache and the tag status bits are modified accordingly.
One technique uses the well known SNOOPING bus protocol. The SNOOPING bus protocol provides coherency between the various cache memories and the main memory of the computer system by monitoring the system bus for bus activity involving addresses of data items that are currently stored in the processor's cache.
Status bits i.e. valid and share are maintained in tag stores associated with each cache to indicate the status of each data item currently stored in the cache.
One possible status bit associated with a particular data item is a VALID bit. The VALID bit identifies if the cache entry has a copy of a valid data item in it, i.e., the stored data item is coherent with the latest version of the data item, as may have been written by one of the processors of the computer system.
Another possible status bit associated with a particular data item is a SHARED bit. The SHARED bit identifies if more than one cache in the system contains a copy of the data item. A cache element will transition into this state if a different processor caches the same data item. That is, if when SNOOPING on the system bus, a first interface determines that another cache on the bus is allocating a location for a data item that is already stored in the cache associated with the first interface, the first interface notifies the other interface by asserting a SHARED signal on the system bus, signaling the second interface to allocate the location in the shared state. When this occurs the first interface will also update the state of its copy of the data item to indicate that it is now in the shared state.
Another possible status bit associated with a particular data item stored in a cache memory can be what is generally called a DIRTY bit. A cache entry is dirty if the data item held in that entry has been updated more recently than main memory. Thus, when a processor WRITES to a location in its cache, it sets the DIRTY bit to indicate that it is now the latest copy of the data item.
Also, in such a multiprocessor computer systems, for every command/address that some other processor module sends across the system bus, the present processor module would have to look up that address in its primary cache, find out if its in there and determine what action to take in response to the command/address.
To minimize this additional cache lookup activity, one or more duplicate tag (DTAG) stores are provided for each processor module. The tag store mentioned above contains information for use in conjunction with its associated cache memory under control of its processor. The tag information in the DTAG cache on the other hand is for use in conjunction with the system bus.
In prior art systems the DTAG store stored the shared and valid bits but not the dirty bit. Therefore, during system bus transactions the present processor module would look up the address in its DTAG to find out if the address is stored in its cache and determine what action to take in response to the command/address coming along the system bus.
Since there is a cache Tag store which can be associated with a primary or backup cache and a DTAG store, it is the goal of the system that each concurrently contain the same information. However, because of time delays in the system processes there may be a time delay between an update of the Status bit in the DTAG cache and the update of the Status bit in the primary cache.
Therefore, the overall system protocol uses the DTAG cache lookup to determine the actual state of a cache entry. As such, the DTAG status becomes the overall system's "Point of Coherency".
One problem with this approach is that since the duplicate tag store contained only the valid and shared bits, when other processors need to determine whether the present cache contains the most recent copy of the data it must first access the dirty bit which is stored in the tag store associated with the processor or a backup cache. Accordingly, the interface can not directly provide this information. This causes the processor to be continually interrupted and thus affects system performance.

System interface protocol with optional module cache


A method, non-transitory computer readable medium and apparatus for correcting a timestamp in a multi-lane communication link with a skew are disclosed. For example, the method receives a data packet, a time stamp for the data packet and a fill level for a lane of the multi-lane communication link carrying the data packet, calculates a corrected timestamp for the data packet and replaces the time stamp for the data packet with the corrected timestamp.

As digital communication links become increasingly faster, many technical difficulties arise. One of the factors limiting the speed of a communication channel is the property of the physical electrical link, which is usually constrained by the latest electrical and integrated circuit technology to be significantly less than the desired aggregate communication speed. Therefore, it is common practice to employ a number of parallel physical communication lanes to achieve a greater aggregate logical link speed. This is known as Multi-Lane Distribution (MLD).
A problem then arises as to how the number of physical communication lanes may be re-combined when the individual high-speed lanes have been impaired by various means during their propagation from a transmitter to a receiver. The arrival time difference of the various individual lanes needs to be corrected so that the individual bits may be correctly re-assembled into the prescribed order corresponding to the aggregate link prior to transmission. For example, the bits arriving on individual lanes may have skewed arrival times due to different lengths of wire or printed circuit board (PCB) trace. The slightly different timestamps can potentially cause variation in a slave clock.
An additional problem occurs when logical lanes are multiplexed over various different types of physical lanes, e.g., electrical lanes or optical lanes. As a logical lane moves from one physical lane to another (electrical or optical), the delay of that logical lane changes since the logical lane is constrained by the delay of the physical lane that the logical lane happens to be carried on.

Timestamp correction in a multi-lane communication link with skew


Processing techniques for enhancing execution of programs written in a logic-oriented programming language such as PROLOG are disclosed. The techniques are particularly useful for programs having class predicates and subclass predicates which are definitive of a class/subclass hierarchy, such as the case with PROLOG's application in object-oriented programming systems, expert systems, object-oriented databases, object-oriented deductive databases, knowledge representations, etc. The techniques ensure that searching within the type hierarchy takes precedence over searching of instances of types. Important to accomplishing this function is the pre-assigning of ranks to predicates and clauses within the program to be processed. Query processing on the program is then based upon the pre-assigned predicate and clause rankings. In particular, novel rules are substituted for conventional predicate and clause selection rules of PROLOG interpreters such that predicates and clauses are preferably processed in order of ranking. In addition, certain query processing simplification steps are introduced. The net effect is a technique which eliminates redundant and unnecessary searching at the instance level by taking advantage of information available in the type lattice.

1. Field of the Invention
This invention relates generally to electronic digital computing and, more particularly, to a processing technique for executing queries in presence of type hierarchies using a logic-oriented language such as PROLOG, i.e., programs written in a programming language referred to in the art as PROLOG (PROgramming in LOGic).
2. Description of the Prior Art
A PROLOG program is written as a sequence of clauses. For example, a clause is written as follows to describe that Mary likes vegetables: EQU Likes(Mary,X).rarw.Vegetables(X). (1)
In a clause, .rarw.(or :--) is a logic symbol and the expressions on both sides of a logic symbol are called predicates. The words exemplified by "likes" and "vegetables" are referred to herein as predicate names. The word "Mary" and letter "X" are called arguments. A letter argument, e.g. "X", is a variable argument, and a word argument such as "Mary", is a constant argument.
Each predicate defines a relationship and includes a predicate name and a sequence of one or more arguments. The lefthand side of the logic symbol is called a head and the righthand side a body. A clause may have only the head. A clause having both a head and the body is called a rule, while a clause having only the head is called a fact (or an instance of predicate).
The predicate of the head and the predicate of the body are herein referred to as head predicate and body predicate, respectively. The head of a regular or a declaratory clause consists of only one head predicate, while the body of a regular or an interrogatory clause consists of one or more body predicates. When a body consists of N predicates, a comma is interposed between adjacent ones of the body predicates as follows: EQU Predicate(H).rarw.Predicate(1), . . . , Predicate(N). (2)
In clause (2), "Predicate(H)" represents a head predicate while "Predicate(1)" through "Predicate(N)" represent body predicates, N in number. The comma used between the body predicates is a logic symbol which means AND. Stated otherwise, the event represented by the head predicate is true only when all events represented by "Predicate(1)" through "Predicate(N)" hold. Let it be assumed that there is another clause in addition to clause (1) such that: EQU Vegetables(carrots). (3)
The sequence of clauses (1) and (3) represents the syllogistic deduction that Mary likes carrots.
As with most programming languages, it is possible to execute a PROLOG program on a conventional computer. Moreover, high-grade machinery is known in the art which is capable of processing various programming languages such as PROLOG. Also, dedicated PROLOG program processors are known, e.g., reference U.S. Pat. No. 4,546,432, by Umemura et al., entitled "PROLOG processing system."
Often, a class/subclass hierarchy (also referred to herein as a type hierarchy) is defined by a program to be processed. In such a hierarchy, there are typically one or more common nodes within the lattice. However, by definition, there are necessarily a smaller number of classes (types) in a particular program than there are objects (instances) in the search space. In PROLOG, a program representable as a type lattice is said to contain both type predicates and predicate instances. A type predicate comprises a predicate representative of a class of defined constants, while a predicate instance is a predicate with all arguments bound to constants (i.e., a fact).
Conventional PROLOG program processing utilizes certain predicate selection and clause selection strategies which almost always result in searching at the predicate instance level when query processing. However, in the presence of type hierarchies, searching type predicates before searching all predicate instances can result in enormous savings of query processing time. The present invention is directed to certain novel techniques for implementing such a concept.
Of the known prior art references, only the technique described by Kaci et al. in an article entitled "Logic and Inheritance," Proceedings of ACM SIGPLAN-SIGACT Conference on Principles of Programming Languages, discusses type lattice processing in a logic programming language. The approach described therein incorporates a processing of a type hierarchy during the unification (herein called matching) process. However, there is no mention of insuring that type predicates are processed before instance level searching occurs. Thus, the present invention is believed to offer a superior approach in terms of reducing search space.

Query optimization by type lattices in object-oriented logic programs and deductive databases

International Business Machines Corporation


A metal powder having a BET specific surface area of 5 to 250 m2/g is obtained by contacting and mixing together a gas of a metal chloride (metal source gas) and a reducing gas (e.g., hydrogen gas) that have been separately heated so as to instantaneously form fine metal particles based on the gas phase reduction reaction thereof, and collecting the fine metal particles from the gas stream after the reaction.

At present, metal powders comprising fine metal particles and having large specific surface areas have been used or have been proposed for their use in a variety of applications, such as electrode materials for capacitors, lithium ion batteries, etc.
As the method of producing metal powders comprising such fine metal particles and having large specific surface areas, there has been known a method of depositing a metal in a liquid containing a metal source substance (called either a wet type method or a hydrothermal method).
When it is attempted to recover the particles of not larger than one micron relying on the wet type method, however, an extended period of time is required, the yield is low and, therefore, the cost becomes very high. According to a method of obtaining a metal powder of fine particles by utilizing a plasma, on the other hand, the cost of the equipment becomes very high, and the metal powder that is obtained becomes, eventually, very expensive. Therefore, this method is not suited for being carried out on an industrial scale, either.
There has also been known a method of decomposing a metal source substance by generating a plasma in the gaseous phase. For instance, Example 1 of a patent document 1 describes the production of an Si powder having an average primary particle size of about 60 nm by introducing a silicon (Si) source material (Si powder of a size of microns) into an argon plasma to vaporize it followed by cooling.
With the method of utilizing the plasma, however, it is difficult to obtain a metal powder having a small oxygen content. As will also be obvious from the disclosure of the above patent document 1, an Ar gas is usually used as the inert gas of a plasma source, and means is employed for feeding a metal source into the Ar plasma. Usually, however, the Ar gas unavoidably contains oxygen in an amount of about 100 ppm, and it is impossible to prevent oxygen from being mixed into the metal powder that is obtained.
Therefore, when it is attempted to produce the metal powder by the above method, there remains a problem in that the metal is oxidized in the reactor during the reaction for forming the particles. Specifically, the silicon powder tends to be very easily oxidized as compared to other metal powders. Despite of using the Ar gas of a very high purity, therefore, the silicon powder is covered with an oxide layer of not less than 5 nm in very short periods of time as soon as the particles thereof are exposed to the air though the oxygen content thereof is still low at the outlet of the reactor. Here, being caused by the generation of heat due to oxidation, the silicon powder could be self-ignited and explode. Therefore, the finely granular silicon has been regarded to be a very dangerous inflammable solid substance.
For instance, the Si powder obtained in Example 1 of the patent document 1 contains oxygen in an amount of 2.8% by mass. Here, presuming that the silicon particles have a surface area of 30 m2/g and that oxygen is all present on the surfaces, it could be simply calculated to be that the oxide layer has a thickness of about 1.2 nm. It is, therefore, estimated that the surfaces of the particles are still very highly active. That is, the silicon is a substance that can be oxidized very easily. Therefore, the surfaces thereof could be oxidized at one time as soon as they are brought into contact with the air, and could be instantaneously covered with the oxide layer of about 5 nm in the dry air. As the thickness of the oxide layer reaches about 5 nm, oxygen is supplied less from the exterior. Therefore, the oxidation reaction on the surface gradually decreases and the oxide layer ceases to grow after about 10 nm under a condition of room temperature and dry state. If the environment contains much water, however, the oxide layer could become thicker and could grow to several hundreds of nanometers.
The present inventors have analyzed typical silicon particles having a specific surface area of 22 m2/g prepared by the plasma method and placed in the market, and discovered that the silicon particles contained oxygen at a concentration of 18%, which could then be calculated to be capable of forming an oxide layer in a thickness (apparent oxide layer thickness) of 8 nm. The particles of this kind are not likely to explode despite they are exposed to the air, and have been placed in the market as relatively safe particles though they can be still regarded to be inflammable solid substance.
As a method, without relying upon the oxidation, of inactivating the silicon particles that are produced by using the plasma pulses and whose surfaces are very active and dangerous, there is a method of introducing methane or ethylene into a reactor to react it with the silicon particles after the step of forming the silicon particles. This method inactivates the silicon particles by covering the surfaces thereof with carbon, and is effective in securing safety, but is not desired for the applications where importance is given to the activity of the particles. When used as an active material for a lithium-ion battery, for example, a very strong Si—C wall could not only impair the flow of ions but also robs the Si atoms of their activity.
As a method of producing metals such as silicon, etc., there has been known a so-called gas phase reduction method. For example, a patent document 2 is disclosing a method of producing metal silicon based on the gas phase reduction by using a silicon chloride as a silicon source and a hydrogen gas as a reducing gas.
According to this method or a similar CVD method (chemical vapor phase deposition method), however, the chloride can be reduced but the film grows on the metal surfaces repetitively, and the product is obtained in the form of large solid bodies. Therefore, the metal particles are little nucleated and, therefore, the above method is not applied to the production of a metal powder that comprises fine particles. In fact, the patent document 2 is depositing the metal silicon on the wall surface of the reactor and is melting it to fall down so as to obtain the metal silicon.
As a similar technology, further, a patent document 3 proposes a method of producing fine silicon particles by gasifying metal zinc, mixing and stirring a zinc gas and silicon tetrachloride, and flowing the mixture thereof turbulently in a tube maintained at 1050° C. to 1250° C.
This technology, too, is capable of producing the silicon particles. If the silicon tetrachloride and zinc are fed in gaseous forms, however, the volumes of the gases decrease conspicuously before and after the reaction, and the pressure in the system becomes negative. To compensate for this defect and to maintain a balance in the pressure between the inlet port and the exit port, therefore, the patent document 3 carries out the operation batchwise, or carries out the operation continuously by feeding the silicon tetrachloride in the liquid form and maintaining a balance in the pressure in the process. Here, to produce the particles (having a minimal unit of several nanometers to several tens of nanometers) having large surface areas, the particles must be grown without spending extended periods of time and the formation of the particles must be terminated instantaneously. In the continuous method which reduces the zinc, however, the silicon tetrachloride must be fed in the liquid form. Therefore, the temperature of the silicon tetrachloride is gradually elevated while heating and stirring the mixed gas to let the particles grow. This method, therefore, is not capable of forming the particles having sufficiently large surface areas. Besides, the silicon produced by this method contains zinc as an unavoidable impurity, which is not desirable.
There has also been known a method of forming a fine silicon powder by the thermal decomposition by using, as a starting material, a low-boiling self-decomposing gas containing silicon. However, easily decomposing gases such as monosilane and monochlorosilane much contain molecules that work to increase stickiness among the particles of SiH2 and SiH3 on the surfaces. Therefore, the silicon particles that have grown join together easily and grow into large particles. Therefore, what are obtained are large particles having sizes of about several hundreds of nanometers. As a result, it is not possible to obtain a powder having a large specific surface area.


A process, apparatus, and system for evaluating a projected cache size implement and manage one or more projected cache lists that each contains directory entries corresponding to a projected cache size. The projected cache size may be either smaller or larger than the actual size of a cache installed in a computer system. Using the projected cache list entries, performance statistics such as cache hit ratio and average access time are tracked for each list. The process, apparatus, and system may calculate performance parameters that describe the performance specific to the actual cache list and each projected cache list. The resulting performance statistics may be used to formulate an optimization parameter to be communicated to a user or an administrator application.

1. Field of the Invention
The present invention relates to the field of data caching within computer systems and more particularly to the field of projected cache structures used to evaluate performance of a cache.
2. Description of Related Art
Cache memory is widely employed in contemporary computer systems. Cache memory is a type of fast-access memory that is typically used to buffer certain information for rapid access that is permanently stored in slower-access memory, such as a magnetic disk or other direct access storage device (DASD). Since cache memory can be substantially more expensive than magnetic disk storage having the same storage capacity, most computer systems have a relatively limited amount of cache memory.
To maximize the efficient use of cache memory, most systems implement a caching strategy that manages the type of data stored in the cache memory and the format in which the data is stored. One commonly employed caching strategy is a least-recently-used (LRU) replacement strategy in which a double-linked list of cache entries is created to identify the data content stored in the cache. This LRU cache list may contain multiple entries that are arranged in order of how recently a data set has been requested by a user or application. At the beginning of the list is the most recently used (MRU) entry. At the end of the list is the least recently used (LRU) entry.
Each time data is requested by a user or application, the system determines if the requested data is stored in the cache. A variety of ways exist to perform full or partial reviews of the cached data. If the requested data is stored and located in the cache memory, the system returns a cache hit and makes the requested data available. The cache list entry corresponding to the requested data may be repositioned at the MRU location. The remaining cache list entries are sequentially demoted. If the requested data is not located or found in the cache memory, the system returns a cache miss, retrieves the requested data in the DASD or other memory, and copies the requested data to the cache list. The retrieved data is generally copied to the MRU location of the cache list and the remaining cache list entries are demoted, with the LRU entry being pushed out of the LRU directory list.
One goal of cache management systems is to implement a caching strategy that maintains a high hit ratio and a corresponding low average data access time for data requests. However, currently no mechanism or process exists that is capable of determining how simulating a projected cache size, different from an actual cache size, might affect the cache performance for a given system. Currently, in order to determine how a different cache size might impact the performance of a cache subsystem or a computer system, the actual cache size must be physically altered either by removing existing cache or adding additional cache.
The prior art does set forth limited proposals that may impact the performance of a given cache, but nothing addresses the performance of a projected cache size. One method set forth in the prior art is to allocate certain portions of actual cache memory to multiple applications that are requesting data at approximately the same time. This implementation addresses the performance of an installed cache, but does not reach the potential impact of a projected cache size.
The prior art also discusses employing a cache arbiter that monitors the cache demands and balances such demands with other demands for processor storage. The arbiter dynamically alters the size of cache available to a given application through the utilization of expanded storage resources. The objective of this method is to dynamically utilize expanded storage resources in order to maximize the system throughput. Nevertheless, this implementation does not address the potential impact on cache performance of a projected cache size.
The prior art further addresses the possibility of implementing cache statistics in order to predict cache hit rates and determine the best data candidates for caching. Still further, the prior art sets forth a method for compressing some or all of the data stored in cache memory in order to make additional cache resources available for storing additional data content. Once again, while these prior art conceptions attempt to address the performance of actual cache memory in a computer system, they do not reach the potential performance impact of a projected cache size.
Consequently, what is needed is a process, apparatus, and system that are configured to monitor cache performance statistics, such as cache hit ratios and average access times, associated with a projected cache size without the space overhead of a physically larger cache. Beneficially, such a process, apparatus, and system would be further configured to compare projected performance parameters to actual performance parameters and communicate an optimization parameter to a user or administrator application.

System, apparatus, and process for evaluating projected cache sizes

International Business Machines Corporation


A method for maintaining network lifetime of a wireless network in wireless communication system, the network including a plurality of device nodes. Selected ones of the wireless nodes have assigned roles in the wireless network. To improve and maintain network lifetime the method includes determining a below threshold operating condition of a first sensor node assigned to a first role and re-assigning the first role to another second node in said network. In other aspects of the invention a method, system and a computer program for carrying out the method are described.

Industrial control systems, process control systems, distributed control systems and the like in process industries often comprise both hard wired data networks and wireless data networks. Process industries can include branches of industry such as pulp and paper, pharmaceuticals, food production, oil and gas extraction, production, processing and the like. Wireless sensor networks are used to communicate measurements and some control data between wireless field devices such as sensors and the industrial control system. Wireless sensors are most often battery powered.
Service life for a battery-powered wireless sensor depends on power use. Service life for a wireless sensor network also depends therefore on power use by individual wireless sensors. The radio receiver/transmitter of a wireless sensor typically consumes most power while sending a transmission, and power while listening for transmissions, and almost no power during an inactive state. Conventionally wireless sensors in a WSN are configured to use little or no energy during inactive periods, also called a sleep state, conserving energy for a limited number of periods for listening for signals and/or for transmitting a signal.
An industrial installation may contain hundreds or thousands of tiny electronic devices, able to sense the environment, compute simple tasks, communicate with each other, and form larger wireless mesh sensor networks (WSN). Information gathered by the sensors (e.g. temperature, humidity etc.) is transmitted in a multi hop fashion via direct neighbors (mesh network) to a control system. With methods such as self configuration and self organization the network reacts to node failures and disconnected nodes due to exhausted battery energy.
Due to the required small size of nodes as well as the strongly constrained battery capacity one major requirement in WSNs is to distribute the networks services in an efficient manner. The long-term strategy of that is to extend the lifetime of the network to a maximum. In more detail the overall sensor network services need to be kept up as long as possible with the same high reliability and expected determinism.
WSNs must provide a variety of discrete services with different resource requirements. Moreover different services have also a different consumption of battery energy, meaning there are very high energy consuming tasks and less energy consuming tasks. Also the position of the nodes has influence on this energy consumption, whereas a node in the middle of a network, and many neighbours, with an aggregation functionality will certainly consume more power than a node with an aggregation role with only few neighbours at the border. Some functionality needs only be performed by a subset of nodes at any specific time. Such functionality can be for instance aggregation (aggregator service needed), cluster routing (gateway service needed), localization (reference nodes with known position needed). In the end the number of different roles needed can vary depending on the application. We define such subsets of node functionalities as roles, and the nodes performing the roles will be called role nodes.
The energy demand of a role varies significantly for different roles. Typically, the role nodes consume incomparably more energy than the other sensor nodes due to more complex calculations and higher communication efforts needed. The role nodes must provide high availability and cannot sleep as long and as frequently as the other nodes. This makes them more vulnerable to battery exhaustion. A rapid exhaustion of role nodes quickly limits or blocks the operation and functionality of the whole network.
A patent application US20090111532 entitled Method and system for power-based control of an ad hoc wireless communications network, and assigned to Nokia Corporation, describes a method, system and program code to implement a wireless network having a plurality of devices in which one of the devices coordinates wireless communications between the devices. The description describes node condition in terms of battery level and aim to coordinate devices to optimize for communication across a network. Application US20050059420, same title, same assignee, also describes coordination in a network relative to node power level.
A patent U.S. Pat. No. 6,901,275, entitled Communication system, and communication device and communication method for use in the communication system, assigned to Toshiba Corp., describes a system aimed at preventing (the network) from concentrating communication on one terminal, thereby avoiding an increase in power consumption and thereby prolonging the network configuration time when forming a network by a plurality of devices. However, the consideration of network life is limited to a parameter for node battery power and the network structure is limited to the situation of a single Master with many slaves.
WO2008/141719, entitled Energy-driven cluster aggregation point re-election in a wireless sensor network, assigned to University College Dublin, describes a sensor network comprising a plurality of nodes arranged to communicate wirelessly with one another, at least some of the nodes being arranged to operate as an aggregation point for the network, in which the aggregation point communicates data between other nodes of the network and externally of the network. However only one function or role, that of data aggregation, is considered here and the operative extension of network lifetime is limited to being based on node battery power alone.
Patent application US20090141653, entitled Enhancement of node connectivity in a wireless communications network with changing topology via adaptive role changing, assigned to BAE Systems Information, describes a process and system for enhancing connectivity among nodes of a wireless communications network by adapting to changes in the network topology. Nodes of the network are configured to operate according to either (i) an ad hoc protocol wherein a given node assumes a role of a mesh node capable of connecting with other like-configured nodes, or (ii) a point-to-multipoint protocol wherein the given node assumes a role of either a base station, or a subscriber station being served by another node which is assuming the role of a base station. A determination is made as to whether each node should operate according to the ad hoc protocol or the point-to-multipoint protocol, in order to maintain an optimum state of connectivity among all nodes of the network. The roles described are only mesh node, base station etc., so they are limited to network properties.
U.S. 2005/033816 A1 discloses a terminal device and method for use in a media access communication system. Terminal devices store statistical information related to interference from an external communication system, and notify the stored statistical information to a master station. The master station is arranged to determine if one of the terminal devices is a candidate station for a master station capability handover destination based collected statistical information.
U.S. 2005/059420 A1 discloses a method and system for implementing a wireless network having a plurality of devices in which one of the devices coordinates wireless communication between the devices. The method and system evaluates device parameters of one or more of the plurality of devices, and determines a coordinator from the plurality of devices based on at least the available power source characteristics such as an available power source capacity, for one or more of the plurality of devices, wherein the coordinator is adapted to coordinate wireless communication between the devices in the wireless network.
EP 2 134 041 A1 discloses a wireless sensor network having a plurality of mobile sensor nodes. In the wireless sensor network a sink is provided and re-positioned as required by assigning the role of sink to one of the mobile sensors at a time.
However, the lifetime of a wireless network may also be affected by factors other than a power level of a node battery. When one of certain other operating conditions of one or more wireless nodes falls below an operating threshold, forming what is described here as a bad condition such as; bit error rate (BER), low memory availability, imprecise position, reduced available bandwidth, incomplete or unsuccessfully finished self test, un-validated node (in terms of security), bad location, high EMI noise in the environment, old software revision, bad connectivity (too few neighbouring nodes) bad or deteriorated antenna direction, then the maintenance of the wireless network may be compromised.
There are generally many different wireless protocols in use in industry. This includes proprietary protocols, open protocols and networks with more than one type of protocol operating in the same broadcast/reception area. Such protocols include for example Bluetooth and ZigBee. Two other examples of a wireless standard in use in industry are called ISA100 also including version ISA 100.11a, for wireless sensing in industrial automation applications, and WirelessHART. WirelessHART is a standard that was developed to be compatible with older HART standards for communication between industrial devices.

Method for reassigning the role of a wireless node in a wireless network


A method for transferring guest physical memory from a source host to a destination host during live migration of a virtual machine (VM) involves (a) transmitting pages of the guest physical memory from the source host to the destination host over a network connection, (b) transferring state information from the source host to the destination host, (c) while performance benefits regarding continued access to the guest physical memory on the source host persist, using the transferred state information to run the VM on the destination host in place of running the VM on the source host, and (d) while the VM is running on the destination host, writing pages of the guest physical memory from the source host to a shared datastore such that the destination host can retrieve the written guest physical pages from the shared datastore.

In the world of virtualization infrastructure, the term, "live migration" refers to the migration of a virtual machine (VM) from a source host computer to a destination host computer. Each host computer is a physical machine that may reside in a common datacenter or distinct datacenters. On each host, virtualization software includes hardware resource management software, which allocates physical resources to running VMs on the host and emulation software which provide instances of virtual hardware devices, such as storage devices, network devices, etc., that are interacted with by the guest system software, i.e., the software executing "within" each VM. Virtualization software running on each host also cooperates to perform the live migration.
Exemplary implementations of live migration of VMs are described in detail in U.S. Pat. No. 7,484,208 which issued on Jan. 27, 2009, and U.S. Pat. No. 7,680,919, which issued on Mar. 16, 2010. These two patents are expressly incorporated by reference herein. However, in general terms, one key aspect of performing live migration is copying the state of the VM from the source host to the destination host in a manner that allows minimal or insignificant disruption of the VM's execution at the time of the transfer from the source to the destination. A challenging component of this state information to be transferred is the contents of the guest physical memory. A VM's guest physical memory comprise those pages of machine memory (i.e., actual physical memory residing in the host) that are mapped or allocated to the VM being migrated. The guest physical memory address space is treated by the guest system software (e.g., the guest operating system) as actual physical memory, but is of course mapped by the virtualization software to physical pages of machine memory. The main reason it is challenging to transfer the guest physical memory to the destination computer in a live migration is because the VM is allowed to continue to execute during the transfer, and therefore continues to update the guest physical memory as the guest physical memory is being copied or transferred.
To copy guest physical memory to a destination host while the VM is executing, an iterative pre-copy scheme may be used, as described in detail in the patents incorporated by reference above. In general terms, the guest physical memory pages are iteratively copied to the destination host prior to execution of the migrating VM on the destination host. This involves multiple copying operations beginning with copying the entire contents of the guest physical memory to the destination host, then repeatedly copying the pages dirtied (i.e., written to by the VM) since the previous copy operation. Provided the bandwidth for transmitting the copied pages between the source and destination hosts exceed changes to the guest physical memory pages caused by the VM, the pre-copy process will eventually converge to a very small set of pages that can then be successfully copied to the destination host along with other VM state information after stunning (pausing execution of) the VM on the source host so the VM can then be resumed on the destination host with minimal or insignificant interruption.
In some situations, e.g., in cases where the pre-copy technique described above cannot converge, the execution of the VM is transferred to the destination host even before all of the guest physical memory pages of the VM are copied to the destination host. As the VM runs on the destination host, and encounters pages that it lacks, but remain present on the source host, the VM demand faults those pages over the network from the source host. This process is called "resume during page-in" or RDPI, and enables the system to guarantee transparent migration success, even for VMs having large working sets of memory pages which have not been pre-copied.
During this period of RDPI, the failure domain of the VM is extended because the VM's memory exists both on the source host and the destination host. For example, if the source host or the destination host crashes during RDPI, the VM needs to be terminated. The same is true when there is a network failure.

Robust live migration using shared filesystem