A method includes receiving, by a library instrumented into an application executable by a computing device, a message indicating modification(s) that should be performed to user interface component(s) able to be rendered by the application on a display of the computing device. The user interface component(s) are modified to create modified user interface component(s). The modified user interface component(s) are caused to be rendered on the display. Another method includes accessing a description of user interface component(s) for an application executable on a computing device, wherein the user interface component(s) are able to be rendered by the application on a display of the computing device. A developer is allowed to modify information concerning the user interface component(s). Message(s) are formed to allow modification(s) and corresponding user interface component(s) to be determined and the message(s) are sent to computing device(s) having the application. Apparatus, software, and computer program products are disclosed.

This invention relates generally to applications executed on computer systems and, more specifically, relates to transparently adapting user interfaces (UIs) for those applications.
This section is intended to provide a background or context to the invention disclosed below. The description herein may include concepts that could be pursued, but are not necessarily ones that have been previously conceived, implemented or described. Therefore, unless otherwise explicitly indicated herein, what is described in this section is not prior art to the description in this application and is not admitted to be prior art by inclusion in this section.
Mobile applications and mobile application market places offer opportunity for developers to quickly release software in to a global market. After an application is deployed comes the challenge of managing the software through its application lifecycle. Managing and updating applications once deployed is a continual challenge for developers and product owners.
To alleviate this challenge, mobile application development has quickly adopted Web technologies as an attempt to directly address this post release management problem, for example, by hosting the client code on the server. This allows applications targeted for mobile devices to quickly update and deploy a new application layout as well as take advantage of "write once, run everywhere".
Another class of mobile application called Hybrid takes this approach one step further. Hybrid applications typically architect the application using a native container alongside a Web view to provide the presentation. The hybrid application lets the application access a native Software Development Kit (SDK) as well for functionality such as a camera, a Global Positioning System (GPS), and file storage.
These two approaches to mobile development cover most use cases. However, they have the drawback of providing a low fidelity user experience.
Native applications, on the other hand, provide an appropriate user experience for the device. Typically, a mobile platform offers a native Application Programming Interface (API) for developing applications targeted to run on the platform. This API defines the look and feel of the platform as well as the operating services that applications are allowed to access. Other web based approaches just approximate this look and feel the best they can using a markup language, and typically the end result is not very good.
Thus, it would be beneficial to improve the look and feel of applications while easing management and updating of the applications.

System, method and apparatus for transparently enabling software applications with adaptive user interfaces


Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer.

The present invention disclosed herein relates to methods of manufacturing nitride semiconductor devices, and more particularly, to methods of manufacturing ultra-thin nitride semiconductor devices.
A GaN-based compound semiconductor, which is a direct-transition-type semiconductor, allows emission of light of a wide range of wavelengths, e.g., from visible rays to ultraviolet rays. Compared to typical GaAs- or InP-based compound semiconductors, the GaN-based compound semiconductor has excellent properties such as high thermal/chemical stability, high electron mobility, high saturated electron velocity, and large energy bandgap. Due to such properties, GaN-based compound semiconductors are widely applied to the fields where the use of typical compound semiconductors is limited. For example, the GaN-based compound semiconductors are applied to optical devices such as visible light-emitting diodes (LEDs) and laser diodes (LDs) and electronic devices used in next-generation wireless communication or satellite communication systems required to have high power and high frequency characteristics. In particular, a nitride semiconductor (AlxInyGa1-x-yN) including aluminum (Al) is a next-generation nitride semiconductor material that may be used to manufacture a light-emitting device for the entire wavelength range of ultraviolet rays due to a high energy bandgap characteristic (3.4 eV-6.2 eV) of the nitride semiconductor. Furthermore, in the case where the nitride semiconductor forms a heterostructure (AlGaN/GaN, InAlN/GaN) together with GaN, an electronic device may be manufactured using a two-dimensional electron gas (2DEG) layer.
Various researches have been conducted to improve breakdown voltage characteristics of power semiconductor devices having a GaN-on-Si structure for which a bulk silicon substrate is used as a handle wafer. However, it has not been reported that GaN-based power semiconductor devices having a breakdown voltage of 600 V or higher have been commercialized. It may be important to develop a technology for manufacturing GaN-based power semiconductor devices having a high breakdown voltage so as to improve the GaN-based power semiconductor devices over Si- or SiC-based power semiconductor devices.
Furthermore, it is required to develop a technology for developing GaN-based power semiconductor devices having excellent electrical performance at a high temperature without being degraded in terms of electrical characteristics under a thermal environment, and having high breakdown voltage and improved characteristics of forward high current.

Methods of manufacturing nitride semiconductor devices

ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE


Disclosed herein are teleconferencing devices having remote access monitoring and control functions, and network systems and methods including and using the same. Also disclosed herein are methods for interacting with teleconferencing devices over an HTTP or other network service utilizing a persistent network connection and systems which implement the methods. Also disclosed are systems that permit clients to select which types of information to be updated in real-time to conserve bandwidth. Detailed information on various example embodiments of the inventions are provided in the Detailed Description below, and the inventions are defined by the appended claims.

The claimed systems and methods relate generally to control and monitoring of teleconferencing devices over a network, and more particularly to teleconferencing systems that provide a network service connectable by clients to monitor teleconference states in real-time and provide a client executable object that can select informational types provided by the network service.
Teleconferencing systems in the past have typically included a teleconferencing device controlling various audio input and output devices, and have normally included a local console for control of the device and teleconferences. As time has passed, it has become desirable to hide the electronics from the conferees, presenting only input and output devices such as speakers and microphones. Additionally, some conferees do not wish to operate or to be trained in the operation of a teleconferencing device, and would prefer that a technician control and/or monitor conferences. It has been desired to locate the technician away from the area of the conference, which requires a remote connection to the teleconferencing device and/or equipment.

System and method for real-time feedback with conservative network usage in a teleconferencing system


The present invention relates to a system for installing a length of cable through a wall. Thus, the system of the present invention can be used to route a television, telephone or computer cable through an existing wall. The system employs an electric drill and associated drill bit. Over the drill bit a routing tool is adapted to be fitted into and secured to the drill chuck of the drill. In use, both the drill bit and tool are secured to the drill. In the preferred embodiment, the drill bit is long enough to extend beyond the end of the tool. Next, the drill is used to cut a hole into a wall. Once through the wall the drill bit can be removed from the tool and the tool can be left within the wall. Any type of cable can now be positioned through the tool within the wall. Lastly, the routing tool can be removed from the other side of the wall and used again elsewhere.

1. Field of the Invention
The present invention relates to a system for installing a length of cable through a wall and more particularly pertains to such a system which employs an electric drill.
2. Description of the Prior Art
The use of a drill bits is known in the prior art. More specifically, drill bits are known to consist basically of familiar, expected and obvious structural configurations, notwithstanding the myriad of designs encompassed by the crowded prior art which have been developed for the fulfillment of countless objectives and requirements.
By way of example, U.S. Pat. No. 5,096,341 to Despres illustrates a hole saw and drive. U.S. Pat. No. 5,447,400 to Seymour discloses a wall penetrator fitting. U.S. Pat. No. 4,760,643 to Juma discloses a hole saw apparatus. U.S. Pat. No. 3,880,546 to Segal discloses a hole saw assembly. U.S. Pat. No. 4,072,441 to LaPointe discloses a hole saw apparatus. Lastly, U.S. Design Pat. Nos. 300,404 to Lauer and 303,118 to Cox disclose hole saw designs.
In this respect, the system of the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of installing a length of television, telephone or computer cable through a wall.
Therefore, it can be appreciated that there exists a continuing need for improved methods of installing computer cables and the like. In this regard, the present invention substantially fulfills this need.

System for installing a length of cable within a wall


The present invention provides a method for improving the tolerance of a plant to an abiotic stress and a method for promoting growing of a plant, comprising a nucleotide sequence encoding the AtSRP (Arabidopsis thaliana stress related protein) of a plant. The present nucleotide sequence is involved in abiotic stress tolerance such as drought, low-temperature and salt stresses of plants. Therefore, the overexpressing transgenic plants have excellent tolerances to these abiotic stresses, whereby they may be useful as novel functional crops which are affected by climates and environments of the cultivated areas. In addition, where the plants are transformed with the present nucleotide sequence, the growth abilities of the transgenic plants are remarkably enhanced, whereby they may effectively used for cultivating the plants with novel function of rapid growing, and biomass.

1. Field of the Invention
The present invention relates to a gene implicated in abiotic stress tolerance and growth promotion and a method for improving abiotic stress tolerance and promoting growing of transformed plants with the same.
2. Description of the Related Art
Due to their sessile nature, higher plants are constantly faced with various adverse environmental factors, including drought, high salt, heavy metals, cold, heat shock, and ozone, during their whole life span. These abiotic stresses are a limiting factor for the growth and development of crop plants. Water deficiency causes dramatic reduction of crop production globally, and the decreasing availability of fresh water may pose a future threat to humans and higher plants. Plants have cellular and genetic defense mechanisms to enhance their tolerance to transient and long-term water shortages by triggering signaling network pathways and inducing stress-responsive genes (Shinozaki and Yamaguchi-Shinozaki, 2007). However, for stress tolerance or sensitivity, our knowledge concerning the biological functions of stress-related genes in higher plants is still rudimentary. Therefore, it is important to study the functions of stress responsive genes to increase the productivity of crop plants.
Plants have diverse defense strategies to reinforce their tolerance against unfavorable conditions by triggering signaling network pathways and inducing the stress-responsive genes. The present inventors have found that three AtSRP (Arabidopsis thaliana stress related protein) genes which encode homologs to the small rubber particle protein (SRPP) in rubber trees (Hevea brasiliensis) were rapidly induced by dehydration in Arabidopsis thaliana. Natural rubber is cis-1,4-polyisoprene produced through mevalonate pathway in cytosolic fractions (latex) of latex vessel tissues (Oh et al. 1999; Sookmark et al. 2002; Kim et al. 2004; Chow et al. 2007). Since Arabidopsis thaliana does not produce natural rubber, it was unexpected that the Arabidopsis thaliana water stress-induced genes shared sequence homology with rubber biosynthetic genes.
SRPP, originally known as a latex allergen, is a protein tightly bound on a small rubber particle in the latex of rubber trees (Hevea brasiliensis).
Bark tissue of rubber trees is constantly stripped, which is known as a tapping process, to collect rubber latex. Therefore, plugging of latex vessels is essential for rubber trees to prevent the loss of their cytoplasmic components, such as primary metabolites, and to prevent pathogen infection of the latex vessel tissues (Wititsuwannakul et al., 2008b). In the process of latex vessel plugging, hevein or Hevea latex lectin (HLL) interacts with rubber particle (RP) protein to form a rubber latex coagulum (Gidrol et al., 1994; Wititsuwannakul et al., 2008a). Recently, SRPP was purified as an RP glycoprotein that bound HLL and was, therefore, termed HLL-binding protein (HLLBP) (Wititsuwannakul et al., 2008c). Interaction between an N-acetylglucosamine moiety in SRPP and HLL may modulate the degree of latex coagulation in response to tapping and mechanical wounding.
However, roles of the SRPP associated with abiotic stresses such as drought, high salt and cold have been not known yet.
Throughout this application, various publications and patents are referred and citations are provided in parentheses. The disclosures of these publications and patents in their entities are hereby incorporated by references into this application in order to fully describe this invention and the state of the art to which this invention pertains.

Gene implicated in abiotic stress tolerance and growth accelerating and use thereof

INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY


An image sensor is provided. The image sensor comprises a readout circuitry, interconnections, a first image sensing device, and a second image sensing device. The readout circuitry is disposed on a first substrate. The interconnections comprise a first interconnection and a second interconnection on the first substrate to be electrically connected to the readout circuitry. The first image sensing device is disposed over the first interconnection. The second image sensing device is disposed over the first image sensing device and electrically connected to the second interconnection.

The present disclosure relates to an image sensor and a method for manufacturing the same.
An image sensor is a semiconductor device for converting an optical image into an electric signal. The image sensor may be roughly classified into a charge coupled device (CCD) image sensor and a complementary metal oxide semiconductor (CMOS) image sensor (CIS).
During the fabrication of image sensors, a photodiode may be formed in a substrate using ion implantation. As the size of a photodiode is reduced for the purpose of increasing the number of pixels without increasing chip size, the area of a light receiving portion is also reduced, thereby resulting in a reduction in image quality.
Also, since a stack height does not reduce as much as the reduction in the area of the light receiving portion, the number o f photons incident to the light receiving portion is also reduced due to diffraction of light called Airy disk.
As an alternative to overcome this limitation, an attempt of forming a photodiode using amorphous silicon (Si), or forming a readout circuitry in a silicon (Si) substrate using a method such as wafer-to-wafer bonding, and forming a photodiode on and/or over the readout circuitry has been made (referred to as a three-dimensional (3D) image sensor). The photodiode is connected with the readout circuitry through a metal interconnection.
On the other hand, while the demand on CIS having a wide dynamic range that can simultaneously express blight light and dark light increases, products that can meet the demand are deficient. In particular, products for a 3D image sensor that can sense an infrared ray as well as a visible ray are necessary.
Since both the source and the drain at the sides of the transfer transistor are usually heavily doped with N-type impurities, a charge sharing phenomenon occurs. When the charge sharing phenomenon occurs, the sensitivity of an output image is reduced and an image error may be generated. Also, because a photo charge does not readily move between the photodiode and the readout circuitry, a dark current is generated and/or saturation and sensitivity is reduced.

Image sensor and method for manufacturing the same


The pesent invention discloses a memory module and a signal line arrangement method thereof. The memory module includes memory chips mounted on both sidees in a mirror form; and a printed circuit board (PCB) having same signal applying contact pads arranged on both sodes which same signal applying balls of the memory chips contact in the mirror form, wherein a via is formed at a location close to the same signal applying contact pad of one side among the same signal applying contact pads arranged on both sides in the mirror form, the via connecting the other side to the signal line of one side, and a signal transmitted from the other side is connected to a contact junction, the contact junction is connected to the same signal applying contact pad of the other side, the contact junction is connected to the via of the other side, and the via of one side is connected to the same signal applying contact pad of one side.

1. Field of the Invention
The present invention relates to a memory module and, more particularly, to a memory module having memory chips on both sides thereof and a signal line arrangement method thereof.
2. Description of the Related Art
A memory module generally includes a printed circuit board (PCB) and memory chips. The memory chips mounted on the PCB can be arranged on both sides of the PCB in a mirrored configuration. That is, a same signal applying ball (pin) of each memory chip mounted on both sides of the PCB can be arranged on both sides of the PCB in a mirror form.
A conventional signal line arrangement method includes forming a via passing through a central location of pads in contact with the same signal applying balls (pins) of memory chips on both sides of the PCB in a mirrored configuration, and connecting a signal line to a same signal applying ball of one side from the via and connecting a signal line to the same signal applying ball of the other side from the via.
However, this method has a spatial limitation to arranging signal lines arranged around the via since the via has to be located at a center of the pads to which the same signal applying balls (pins) arranged on both sides of the PCB in a mirror form contact. Further, since a time for a signal to pass through the via is not considered, signal transmission times spent for a signal to be transmitted to the pads which the same signal applying balls (pins) arranged on both sides in a mirror form contact can differ, and thus if a signal which operates at a high frequency is transmitted, signal distortion can occur.
Another conventional signal line arrangement method of the memory module is to arrange the via at a location close to one of the pads which the same signal applying balls (pins) contact according to the arrangement of signal lines arranged around the via without forming the via on the central location of the pads which the same signal applying balls (pins) arranged in the mirror form contact. Here, signal lines arranged on both sides are same in length of from the via to the same signal applying balls (pins). That is, in order to make equal a length of the signal line from the via to the pad which is arranged on one side of the PCB and the same signal applying balls (pins) contact and a length of the signal line from the via to the pad which is arranged on the other side of the PCB and the same signal applying balls (pins) contact, one signal line is arranged in a straight line from, and the other signal line is arranged in a bent form.
Thus, this method has an advantage in that signals can be transmitted at the same time point since the signal lines are the same in length from the via to the same signal applying balls arranged on both sides of the PCB and is also efficient in arranging the signal lines around the via. However, a length of the signal line from via to the pad can become lengthy because the via is arranged at a location close to one of the pads which the same signal applying balls (pins) contact. Thus, this method has a limitation in that it is not conductive to transmit a high-frequency signal, like the first method for arranging the via at the central location of the same signal applying balls (pins) described above. Similar to the first method, since a time to pass through the via is not considered, signal distortion can occur when the high-frequency signal is transmitted, because signal transmission times for a signal to be transmitted to the pads in contact with the same signal applying balls (pins) arranged on both sides of the PCB in a mirrored configuration can differ.

Memory module and signal line arrangement method thereof


In a container for a roll of a light-sensitive strip material having a core on which the light-sensitive strip material is coiled to form a roll, an opening for drawing out the light-sensitive strip material and a teremp cloth provided on the above opening for shielding from light, wherein a filling layer formed of polyolefin copolymer resin usable as the adhesive layer for fixing the teremp cloth on the container body is provided at the ground fabric of the teremp cloth, and/or a multilayer coextruded film is laminated under the ground fabric of the teremp cloth, and the multilayer coextruded film has a tensile strength of more than 500 g/15 mm width and comprises an adhesive layer of an ethylene copolymer resin having a comonomer content of 5 to 36 % for fixing said teremp cloth on the container body and a thermoplastic resin base layer having a melting point of higher than the ethylene copolymer resin adhesive layer by 10.degree. C. or more and a Young's modulus of more than 15 kg/mm.sup.2.. In this container, the filling material does not so deeply permeate into pile yarns, even though the ground fabric is not so dense. Adhesion of pile yarn dust hardly occurs, and troubles in exposure and development caused by the pile yarn dust are solved. By incorporating the multilayer coextruded film, the thickness of the adhesive layer for fixing teremp cloth on the container body is made uniform and various problems caused by non-uniformity in the thickness of the adhesive layer are solved.

1. Field of the Invention
This invention relates to a container for a roll of a light-sensitive strip material such as a photographic roll film or a roll of photographic paper. More particularly, this invention relates to a lightproof container having an opening for drawing out the light-sensitive strip material where teremp cloth is provided.
2. Description of Prior Art
As the container for a roll of a light-sensitive strip material, various types have been disclosed in U.S. Pat. No. 4,148,395, U.S. Pat. No. 4,179,028, U.S. Pat. No. 4,239,164, U.S. Pat. No. 4,272,035, U.S. Pat. No. 4,291,802, U.S. Pat. No. 4,398,814, U.S. Pat. No. 4,403,845, Japanese Patent KOKAI No. 60-156058, Japanese Patent KOKOKU No. 59-36736 and Japanese Utility Model KOKOKU No. 56-16608.
Generally, a light-shielding member is provided at the drawing out part of a container for a light-sensitive strip material in order to prevent the inner light-sensitive strip material from being exposed to the light leaked from the drawing out part. Various light-shielding members are known, and among these, the light-shielding members mainly composed of cloth are called teremp cloth.
An example of conventional teremp cloth disclosed in Japanese Utility Model KOKOKU No. 46-20539 is shown in FIG. 19. This teremp cloth was composed of a woven ground fabric 1 and coreless pile yarn 4 woven thereinto. The ground fabric 1 was formed by weaving the warp 2 and the woof 3 like shown in FIG. 20. The above coreless pile yarn was formed from a soft raw yarn such as viscose yarn or acetate yarn by crimp processing, and the ground fabric 1 was impregnated with an adhesive material 5 for filling in order to fix the pile yarn 4. Generally, such a teremp cloth was manufactured first by weaving the warp 2 and the woof 3 together with entangling pile warp yarn 4 therein to form double velvet and then by cutting the loop.
However, in the case of the conventional teremp cloth as shown in FIG. 19, fraying or falling out of pile yarn occurs during the manufacture of the teremp cloth and drawing out or in the light-sensitive strip material. Dust from the pile yarn adheres to the surface of the light-sensitive material, and causes trouble in exposure and development. In addition, it is necessary to arrange the orientation of pile yarn so as to prevent meander movement of the light-sensitive material during its drawing out. It is also a problem that its manufacture process is complicated and manufacturing cost is expensive. Particularly, in the case of the container for a roll of photographic color printing paper capable of loading in a light room, adhesion of pile yarn dust is a serious problem under high temperature and high humidity conditions because of increasing adhesion of the gelatin layer.
A filling material solution was impregnated into the ground fabric 1, and dried to form a filling layer 5 which fixed the pile yarn 4 to the ground fabric 1. A heat-sealable adhesive layer 6 was coated on the filling layer 5, and the teremp cloth was stuck on the drawing out opening of container body 7.
In such a conventional teremp cloth, the weaving yarn of ground fabric must be thickened in order not to impregnate the filling material solution deeply into the pile yarn in the coating process of the filling material solution. As a result, a velvet cloth made of a large quantity of yarn was employed as the teremp cloth, though it was expensive. Besides, the thickness of the adhesive layer 6 varied according to the irregularity of the ground fabric, impregnation rate of adhesive, ununiformity in weaving yarn arrangement of the ground fabric or the like, and various problems occurred caused by the variation of the adhesive layer thickness, such as unstable adhesive strength to container body 7, significant non-uniformity in light-shielding in the case of an adhesive containing a light-shielding material, generation of furrows on ground fabric 1, wrinkling and the like. In the case of coating a hot-melt adhesive layer, similar problems occurred.

Container for light-sensitive strip materials having improved light sealing means


A ferrule sleeve includes a sleeve body, where the sleeve body is shaped in a V and includes a V-shaped groove that runs a length of a first side of the sleeve body. The ferrule sleeve further includes a sleeve cover, having a flat, rectangular shape, which fits into an opening of the V-shaped groove of the sleeve body. The ferrule sleeve further includes a cover spring that fits into the opening of the V-shaped groove of the sleeve body adjacent the spring cover, wherein the sleeve cover and the cover spring, when a first cylindrical ferrule is inserted within the V-shaped groove act to hold the first cylindrical ferrule within the V-shaped groove and prevent the first cylindrical ferrule from rotating, or from moving in a longitudinal.

Fiber connectors permit cables that contain optic fibers to be connected with one another via a separable interface that allows for easy disconnection and reconnection of the cables. When fiber connectors are mated with one another, the optic fibers in each cable should be aligned with one another to facilitate optical transmission between the optic fibers. To minimize losses associated with the mated fiber connectors, it is important that the fiber connectors provide accurate fiber alignment (i.e., core-to-core alignment of the fiber media) and that the ferrule end faces of each fiber connector be precisely shaped such that optimum physical contact can be maintained between each mated fiber pair.


A medium for optical recording is disclosed, from which recorded information is reproduced by a laser beam. The medium includes a disk board having a recording surface, and multiple pits in the recording surface. The pits are included in cells having equal size and varying pit-occupancy rates dependent on the recording information, the pit-occupancy rate being the ratio of area of the pit to area of the corresponding cell. The depths H of the pits, the wavelength λ of the laser beam, and the refractive index n of the board are related as, λ/6n<H<λ/4n.

In recent years and continuing, an optical-recording medium such as a Compact Disk (CD) with a recording capacity of 0.65 Gigabytes and a Digital Video Disk (DVD) with a recording capacity of 4.7 Gigabytes is becoming increasingly common as means for storing video information, voice information, or data on a computer. Moreover, at the present, there is an increasing demand for further improvement in recording density and for increased capacity.
As means for increasing the recording density of such optical-recording media, in an optical information processing apparatus which performs writing to or reading from the optical-recording media a set of information, increasing the Numerical Apeture (NA) of an objective lens or shortening the wavelength of an optical source so as to reduce the diameter of a light spot formed on the optical-recording media by light beams condensed by the objective lens is effective.
Thus, for example, while the Numerical Apeture of the objective lens is set as 0.50 and the wavelength of the optical source as 780 nm for a "CD-type optical-recording medium", the NA of the objective lens is set as 0.65 and the wavelength of the optical source as 660 nm for a "DVD-type optical-recording medium" with a greater recording density. Moreover, in order to respond to the demand for further improvement in the recording density and increased capacity, further increasing of the Numerical Apeture of the objective lens above 0.65, or further shortening of the wavelength of the optical source below 660 nm is called for. As for such large-capacity optical-recording media and optical information processing apparatuses, there are systems proposed which establish the need for achieving the increased capacity using an optical source in the blue-wavelength domain (refer to Non-Patent Document 1, for example.)
However, there is a problem in which, as the NA of the objective lens is increased, or the wavelength of the optical source is shortened, the margin for various changes in the optical-recording medium is reduced. For example, there is a problem in which a coma generated by a tilt in the optical-recording medium becomes large. Generating of the coma leads to a degrading of the beam spot formed on an information-recording surface in the optical-recording medium, preventing normal operations of recording and reproduction. The coma generated by the tilt in the optical recording medium is generally given by the equation below:W31=((n2−1)/(2n3))×(d×NA3×θ/λ)
Herein, n represents the refractive index of a transparent board in the optical recording medium, d the thickness of the transparent base board, NA the Numerical Apeture (NA) of the objective lens, λ the wavelength of the optical source, and θ the amount of the tilt. It may be understood from the equation that the shorter the wavelength and the higher the NA, the bigger the coma. Similarly, as a spherical aberration generated by a difference in the thickness of the board in the optical recording medium is proportional to the 4th power of NA, the Numerical Apeture, and to the (−1)th power of λ, the wavelength, the shorter the wavelength and the higher the NA, the bigger the spherical aberration.
Thus, as another proposal, a multi-level recording and reproduction method of controlling the signal levels in pits formed on the optical recording medium is being proposed. In other words, in a related-art optical recording medium, reading of a signal is performed by using a change in the amount of light reflected dependent upon the presence or absence of pits when scanning over the optical recording medium with a laser light for reading. The multi-level recording and reproduction method, as described in Patent Document 1, which performs the reading of the signal by using the change in the amount of light reflected dependent upon a combination of pit depth and pit width; and the multi-level recording and reproduction method, as described in Patent Document 2, which performs the reading by using the change in the pit depth and the pit width, and an offset in the pit position, are also being proposed.
Furthermore, in Patent Document 3, concerning a method of recording multi-level information using a recording mark occupancy rate method, in a case of a concavo-convex-shaped phase pit, a setting of an optical-channel depth of the phase pit as λ/4 so as to make a signal gain of a Radio-frequency (Rf) signal maximal is described.
Patent Document 1
JP58-215735A
Patent Document 2
JP07-121881A
Patent Document 3
JP2002-157734A
Patent Document 4
JP04-030094A
Non-Patent Document 1
Hiroshi Ogawa, "Next Generation Optical Disc", Proceedings of the ISOM, pp. 6-7, 2001
However, as described in the Patent Documents 1 and 2, the efficiency of producing the optical recording medium in which multi-level data are recorded using the pit depth and the pit width becomes very low.
FIG. 14 and FIG. 15 illustrate a manufacturing process of a reproduction-only optical recording medium in which a binary signal comprising a low-level and a high-level is recorded in related-art CD-type and DVD-type pits. The known manufacturing process comprises the steps of laser cutting (S1), developing (S2), stamper production (S3), and replication (S4). In other words, first, as illustrated in FIG. 15A, using an optical beam 100, a portion to be the pit 1 on a resist surface 102 of a glass board 101 is exposed to the depth where the optical beam 100 falls upon the glass board 101, the developing is performed as illustrated in FIG. 15B, a stamper master 103 is produced based on the developed originally-recorded board as illustrated in FIG. 15C. Then, using the stamper master 103, according to a known replication process, reproduction-only optical recording media 104 are manufactured in large quantities. The number 105 represents a groove, while 106 represents a land.
In the related-art manufacturing process, there is a need to control exposure of the glass board 101 so as to comprise pits having a plurality of depths. However, in such a case, the bottom loses smoothness (surface curvature or surface roughness is produced). Moreover, it is empirically understood that there are problems such that a change in the depth is very sensitive to a change in the exposure so as to make the controlling difficult. While depth modulation is theoretically enabled by changing the exposure, due to such reasons, in a related-art optical recording medium for CD reproduction or a related-art optical recording medium for DVD reproduction, the exposing of the glass board so as to record the signal which corresponds to a pit-length modulation is not performed.
Moreover, as another problem to be solved by the present invention, there is a method of generating a tracking-error signal. In other words, the method of generating the tracking-error signal which has been adopted by the optical recording medium for CD reproduction and the optical recording medium for DVD reproduction is not suitable for such shortened wavelength, increased NA, increased density or speed using such methods as the multi-level recording method. Also it is a method by which it is difficult to achieve compatibility with a recording-type optical recording medium. In other words, a Differential Push-Pull method (referred to as the DPP method below) is applied to the optical recording medium for CD reproduction, while a Differential Phase-Detection method (referred to as the DPD method below) is applied to the optical recording medium for DVD reproduction. Below, the respective methods are described.
The Differential Push-Pull method (or the DPP method) is described. Generating the tracking-error signal by the DPP method comprises using a grating on a main track and its neighboring track, a main beam M1 spot, and first and second sub-beam S1 and S2 spots.
Referring to FIG. 16 which illustrates a related-art optical pickup (an optical element of an optical information processing apparatus), a beam output from a semiconductor laser 110 is collimated at a collimator lens 111 so as to be diffracted at a grating 112 for branching into zeroth-order and ± first-order diffracted lights. Then, such branched lights, at the object lens 113, are condensed so as to illuminate an optical recording medium 114. Then, as illustrated in FIG. 17, the main beam M1 spot comprising the zeroth-order diffracted light is formed over a main track T, and the first and the second subbeam S1 and S2 spots comprising the ± first-order diffracted lights, respectively, precede and follow relative to the main beam M1 spot so as to be formed in a radial direction of the optical recording medium 114 with a separation distance from each other of ±½ track pitch.
The main beam M1 and the first and the second subbeams S1 and S2 reflected at the optical recording medium 114 so as to be passed through the object lens 113 are deflected from the illuminated light beam at a beam splitter 115 so as to be received at receiving optics 117 via a detector lens 116. The receiving optics 117, as illustrated in FIG. 17, comprises a first optical detector 118a which receives the main beam M1, and a second optical detector 118b and a third optical detector and 118c which respectively receive the first and the second subbeams S1 and S2. Each of the first through third optical detectors 118a through 118c independently converts the beam photoelectrically, using two plates partitioned in the radial direction of the optical recording medium 114.
The signals detected at the first through third optical detectors 118a, 118b, and 118c are respectively input to first through third differential amplifiers 119, 120, and 121 so as to be output as first through third push-pull signals. A first amplifier 122 amplifies to a predetermined gain G1 the third push-pull signal, while a second amplifier 123 amplifies to a predetermined gain G2 a signal summing a signal output from the first amplifier 122 and the second push-pull signal. A fourth differential amplifier 124 takes the difference between a signal input from the second amplifier 123, and the first push-pull signal, based on the main beam M1, input from the first differential amplifier 119. Then, the gains G1 and G2 of the first and the second amplifiers 122 and 123 are determined by taking into account intensities of the main beam M1 and the first and the second beams S1 and S2.
While there is no particular problem in adopting the DPP method for the reproduction-type optical recording medium, in a case of adopting the method for operating the recording-type optical recording medium using the optical pickup apparatus having such configuration, problems as described below arise. In other words, as for the beam output from the optical source 110 diffracted at the grating 112 into three beams M1, S1, and S2 so as to be used, there are problems as follows:
(1) The optical efficiency of the main beam M1 decreases so as to make its use for recording difficult. Moreover, an application requiring increased speed becomes difficult.
(2) Moreover, at the time of the recording, a signal recorded on a neighboring track may be erased by the first and the second subbeams S1 and S2.
Next, the Differential Phase-Detection method (the DPD method) is described. In the DVD reproduction-type optical recording medium, a method called the Differential Phase-Detection method, or DPD method is adopted as a method for obtaining the tracking-error signal. This method uses a change, at the time a beam spot illuminating an optical recording medium passes over the pit, of an image (a diffraction pattern) of the pit on the receiving optics due to an offset, from the center of the pit, of the beam spot, the receiving optics being arranged so as to comprise areas, partitioned in the longitudinal direction of the track, of the image of the pit. The way of changing the output signal level, in response to the amount of light received at the respective areas, differs depending upon the direction and magnitude of the offset, from the center of the pit, of the beam spot. The tracking-error signal indicating the direction and the magnitude of the offset of the beam spot is obtained by binarizing the output of the receiving optics to predetermined levels so as to compare the phases of the binarized signal, and to examine which changed earlier and the time difference (phase difference) of the changing in the level.
FIG. 18A through FIG. 20B illustrate variations of distribution patterns (far-field images) of intensities of the amount of light reflected, received at the optical receiving areas a, b, c, and d of the quad-partitioned receiving optical sensors 133 at the time a beam spot 121 passes over information pits 132, a set of FIG. 18A, FIG. 19A, and FIG. 20A and a set of FIG. 18B, FIG. 19B, and FIG. 20B respectively representing the positional relationships between the beam spot 121 and the information pits 132, and the far-field images of the amount of light reflected when the beam spot 121 passes over the information pits 132. At the time the beam spot 121 is over an information track of the recording medium, the far-field image is in even brightness. In a case of the beam spot 121 passing over the center of the information pits 132, as illustrated in FIG. 19A and FIG. 19B, the far-field image changes while keeping bilateral symmetry. Moreover, as illustrated in FIG. 18A, FIG. 18B, FIG. 20A, and FIG. 20B, in a case of the beam spot 121 passing over with an offset from the center of the information pits 132, the bilateral symmetry in the far-field image is lost, causing the time difference (the phase difference) in the way of the change, and in a case of the beam spot 121 passing over the right-hand side of the center of the information pits 132, as illustrated in FIG. 18B, changing so as to rotate clockwise, while conversely in a case of the beam spot 121 passing over the left-hand side of the center of the information pits 132, as illustrated in FIG. 20B, changing so as to rotate counterclockwise. Such changes in the pattern become clearer with the beam spot 121 comprising the offset from the center of the information pits 132. Hereby, performing a conversion of the amount of light to an electrical signal so as to detect the time difference makes it possible to obtain the tracking-error signal as illustrated in FIG. 21.
By subtracting the tracking-error signal, as in FIG. 18A through FIG. 20B from the sum of the output signal levels corresponding to the amounts of reflected light received at the optical receiving areas a, b, c, and d, positioned diagonally from one another, of the quad-partitioned optical receiving sensors 133, the difference among the signal levels as described above becomes zero, representing a state referred to as an on-track state in which the beam spot 121 is right above the track. On the other hand, as the beam spot 121 is separated from the information pits, in response to the amount of light, the symmetry of the distribution of the intensities in the far-field image is lost so that the tracking-error signal is generated.
However, in a large-capacity optical recording medium where the beam diameter is greater than the pit diameter, in a case such that multiple edges exist in a beam (referring to FIG. 6A), the DPD method can not be used as multiple diffraction patterns mix with one another.
Moreover, while the DPD method is used for the DVD reproduction-type medium, for a DVD recording-type optical recording medium, the DPP method and a push-pull method are used so that there is a need to switch, between the recording-type and the reproduction-type, the method of generating the tracking-error signal.
Furthermore, in a case of using the recording mark occupancy rate method as described in Patent Document 3, as the optical-channel depth of the phase pit is set to be λ/4, obtaining the push-pull signal is almost impossible so as not to be able to apply the push-pull method in detecting the tracking-error signal.

Optical recording medium having relationship between pit depths, wavelength and refractive index


A cylinder head cover, particularly for covering a cylinder head of an internal combustion engine, having a plurality of functional elements such as an oil filling connection and at least one oil separation device mounted thereon. The cylinder head cover is formed by a bottom shell and a top shell, with the functional elements each being formed from two segments. One segment is integrally arranged on the bottom shell, and the second segment is integrally arranged on the top shell. The two shells are interconnected by communicating sealing contours. Essential functional parts of the oil separation device are provided on the bottom shell and on the top shell. Preferably the functional elements include a cyclone which separates entrained oil from gases in the cylinder head cover and includes a cup arranged on the bottom shell and an immersion tube arranged on the top shell.

The present invention relates to a cylinder head cover, in particular for covering the cylinder head of an internal combustion engine, having a plurality of functional parts such as an oil separator mounted thereon.
Cylinder head covers serve to seal off the cylinder head space from the outside of the engine. As a result of operation of the internal combustion engine, blow-by gases from the combustion process and oil droplets from the lubricant system of the engine are present inside the cylinder head. These quantities of gas and liquid present in the cylinder head space are usually passed through separating devices and returned to the intake area and/or the oil circuit. Such separating devices for separating the oil components of the crankcase gas are usually mounted in the immediate vicinity of the cylinder head cover or, ideally, they are integrated into the cylinder head cover.
Stegmaier et al, U.S. Pat. No. 6,725,849 (=DE 101 27 819) describes a cylinder head cover including a preliminary separating device, a cyclone separating device, a fine separating device and a valve device arranged on it in a cascade. The functional elements mentioned above are individually arranged side by side in immediate proximity on the bottom shell of the cylinder head cover. All the functional elements are covered by a housing half-shell. The housing half-shell provides a sealed cover relative to the ambient environment and furthermore does not have any function in the separation process. One disadvantage of this is that a high level of design complexity and a complex manufacturing technology are required to manufacture the individual functional elements, and there is also a high expenditure for materials.


Banknote serial number processing method and apparatus having a serial number recording step where images of serial numbers associated with to-be-newly recorded banknotes are subjected to image recognition. Image recognition is followed by a conversion step involving a conversion of the image recognized serial numbers to digital data inclusive of digital serial number data and bundle codes. There is also a comparison step which includes a comparing of digital data produced in the conversion step with read-in or provided serial number data, with the provided serial number data being derived from a database containing serial number data of non-counterfeit banknotes which represent banknotes unlawfully obtained by a third party. Comparison hits trigger an alarm and/or forwarding of information, while non-comparison hit banknotes are forwarded to memory with associated bundle coding.

Violent crime such as robbery of bank and cash convey vehicle, although occurring at low rate, causes physical and psychological traumas to the victims involved and result in social hazards, due to their severe violation and danger. Kidnapping and extortion are other type of crime, i.e. extorting gigantic amount of money by imposing threats upon the lives of the hostage. To prevent such crimes the Nation has taken measures of many kinds, such as social security integrated controls, strengthening of police force and equipping special cash transport vehicles, etc. However, these measures only increase criminals' difficulties in committing crimes, while the these types of problems are far from being rooted out and preventions are not erected. The ultimate objective of violent crimes of bank robbery, cash vehicle robbery or kidnapping is to obtain a huge amount of banknote, usually more than tens of thousands, even millions of dollars, where the money the criminals robbed is in bundles. Counterfeit money detectors and banknote counting devices with fake banknote detection function in prior art can identify the counterfeit notes, but they can do nothings about the bundled genuine cash robbed.

Banknote serial number processing method and its device


A scanning system and an image display method are provided, the method including: implementing a scanning process to obtain scanning data; converting the scanning data into image data; implementing an identification process and a segmentation process to the image data to obtain position and direction information of an interventional device; and calculating a first set of imaging parameters corresponding to a first image display mode based on the obtained position and direction information of the interventional device, and implementing real-time image display based on the first set of imaging parameters. Position and direction of interventional devices may be determined accurately. Further, multiple display modes are available, which may provide an accurate and full range image display.

Nowadays, scanning systems like computed tomography (CT) systems, magnetic resonance imaging (MRI) systems, and the like, are widely used in medical industry. Currently, scanning systems can be utilized in interventional therapy processes. For example, repeated scanning processes may be performed by using a CT system. Images obtained from the repeated scanning processes may be reconstructed and then be presented on a display device. Doctors can position an interventional device, such as a puncture needle, based on the CT image(s), so as to conduct an interventional therapy process.
In practical treatment processes, an interventional device, for example, a puncture needle, may have different directions depending on various positions and morphologies of different lesions. However, CT images are presented along an axial direction which may not be parallel with the puncture needle. As a result, the position and direction of the puncture needle can' be accurately controlled. Besides, in current techniques, projections of the puncture needle on other planes are not presented. Therefore, the relative position of the target lesion and the puncture needle may not be displayed clearly. Image display techniques with improved accuracy and a full range illustration are needed to facilitate medical treatments.

Scanning system and image display method

SHENYANG NEUSOFT MEDICAL SYSTEMS CO., LTD.


A system and method for deploying software is disclosed. In one embodiment, information regarding software components and their interactions, deliverables and deployment descriptors, hardware topology, layer information, and database information are all captured in a model. The model in then used to install the software on a particular machine. In another embodiment, an organizational structure is used to create an access map, and access rights to the installed software are generated and enforced.

Large software systems are normally divided into multiple subsystems that are developed as individual components. Interactions between these subsystems and/or components must be properly depicted in order to provide for smooth deployment. Moreover, in multi-layered systems, individual components of the application have their equivalent parts deployed over multiple layers. For example, components might be distributed across databases in a resource manager layer. Information about the deployment of parts of each component must be known in other layers so as to have accessibility within and across components for each layer and across layers.
Normally component interactions and deployment are depicted using Unified Modeling Language (UML) diagrams and deployment is done manually. Because of this, for multi-layered applications, topology selection becomes a most problematic task for application deployment. Various factors like security, performance, throughput, scalability, availability, maintainability and session management should be considered during the review of requirements so as to formulate the topology selection criteria.
A related issue, hardware sizing, is sometimes arrived at after making an estimate about the size of the applications and the appropriate topology selection. In contrast, there may be situations where topology selection is already constrained by the existing hardware. While fine-tuning the live applications for factors such as those mentioned above, a trial and error approach to arrive at a final optimal solution is unavoidable. When the number of users increases, it is necessary to add extra server instances to cater to the increased user requests and also to load balance across the machines.
In a multi tier system, it is possible to deploy software artifacts of different layers in a multitude of permutations and combinations. This is compounded by the fact that the hardware platform can be distributed with each platform catering to a subset of the user groups. One example in which this is required is with large organizations that are located across the globe. By contrast, for small organizations, there is a need to deploy the application in a minimum mode configuration with all layers resident on the same physical hardware. During deployment, the application architecture in terms of component interaction, the organizational structure in terms of functions performed in different organization units, as well as the hardware topology in terms of servers hosting different layers, must all be balanced and correct for the proper functioning of the application. The use of manual systems to deploy such complex applications with a lot of interdependencies is fraught with dangers (such as missed elements), and do not explicitly formalize software deployment and roll out.
Additionally, current practices and tools for software deployment deal with only the technical aspects of deploying software onto the respective hardware structures, and the administration of access specifications to business functions and users is disjoint. Moreover, when there is a reorganization and consequent redeployment, existing practices are cumbersome and are dependent on detailed manual documentation of deployment maps. The current set of technologies and distributed processing schemes make the task even tougher.

Flexible deployment of software applications


A method and apparatus for evaluating an object having a wrinkle. Energy is sent into the object at a plurality of locations using an array of transmitting elements. Reflected energy is received at an array of receiving elements in response to a portion of the energy being reflected off a plurality of layers in the object. A three-dimensional model of the wrinkle in the object is created based on the reflected energy received at the array of receiving elements.

1. Field
The present disclosure relates generally to wrinkles in composite objects and, in particular, to evaluating the wrinkles in composite objects. Still more particularly, the present disclosure relates to a method and apparatus for generating three-dimensional data about a wrinkle in a composite object using an ultrasonic inspection system.
2. Background
A composite object may be comprised of multiple layers. These layers are oftentimes referred to as composite plies. In some cases, a wrinkle may form within a composite object. The wrinkle may be formed by a ridge, a furrow, and/or a crease in one or more layers of a portion of the composite object. A wrinkle in a composite object may reduce one or more of the mechanical properties of the composite object. For example, without limitation, a wrinkle may reduce the stiffness of a composite object at or near the location of the wrinkle.
Different types of inspection systems may be used to detect wrinkles in composite objects. For example, an ultrasonic inspection system may be used to identify a wrinkle in a composite object. However, some currently available ultrasonic inspection systems may be unable to quantify certain properties about a wrinkle in a composite object. As one illustrative example, some currently available ultrasonic inspection systems may be unable to measure the actual shape or size of a wrinkle. In particular, these ultrasonic inspection systems may be unable to measure the shape or size of a wrinkle in three dimensions.
The shape and size of a wrinkle in a composite object may determine how the wrinkle affects the mechanical properties of the composite object. When the shape and size of a wrinkle in a composite object cannot be quantified, the wrinkle may need to be assumed a "worst-case" scenario. The composite object may then need to be discarded or reworked even if the wrinkle actually has a shape and size within selected tolerances. Therefore, it would be desirable to have a method and apparatus that take into account at least some of the issues discussed above, as well as other possible issues.

Quantification of wrinkles in composite objects


A reset power down mode designating signal and first and second write protect signals are provided to a control circuit. According to the states of these external control signals, the status of unconditional inhibition, unconditional permission, and lock bit (LB) dependency for the protect status of data rewrite is set for each memory block group of a memory array. Therefore, the write protect status can be set in a flexible manner for a nonvolatile semiconductor memory device.

1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a nonvolatile semiconductor memory device having a protect feature against data rewriting. More particularly, the present invention relates to a structure for setting a protection mode on data programming and erasure.
2. Description of the Background Art
A semiconductor memory device is advantageous over a memory device that uses a magnetic disc as a storage medium by virtue of its small size, lightweight, and high speed access, and has a wider application. A nonvolatile semiconductor memory device that stores information in a nonvolatile manner is known as one such semiconductor memory device. This nonvolatile semiconductor memory device has the stored information retained even when the power is turned off. It is used as a program memory or data memory in equipments such as a portable information terminal that employs a battery as the power source. A well known example of a nonvolatile semiconductor memory device is a flash EEPROM (electrically erasable and programmable read only memory: referred to as flash memory hereinafter) having a memory cell formed of one transistor, and that allows increase in integration density and collective erasure of data in a certain address range.
It is premised that information is stored in a nonvolatile manner in the nonvolatile semiconductor memory device such as a flash memory. It is therefore necessary to prevent the nonvolatile data from being rewritten by erroneous programming and erasure. Particularly in the case where the nonvolatile semiconductor memory device is used as a program memory, the stored data must be reliably retained, and any erroneous programming and erasure had to be obviated. For the purpose of preventing erroneous programming and erasure, a "write protect" feature is provided in a nonvolatile semiconductor memory device such as a flash memory. This write protect feature allows a user to apply a lock for any programming and erasing operation on a certain data region (memory block) that should not be written or erased. The write protect feature prevents erroneous programming and erasure on a memory block basis. Here, the term "write" is used as including the erasure step of erasing a memory cell data and the programming step of actually writing data into an erased memory cell.
FIG. 13 schematically shows a structure of the portion related to the writing/erasing operation of a conventional nonvolatile semiconductor memory device. Referring to FIG. 13, a nonvolatile semiconductor memory device includes a memory array 100 having a plurality of nonvolatile memory cells for storing information in a nonvolatile manner, and a protect control data storage region 102 for storing information indicating inhibition/permission of writing and erasure of a nonvolatile memory cell in memory array 100.
Memory array 100 is divided into a plurality of memory blocks 100a-100n. Erasure is carried out block by block.
Protect control data storage region 102 includes a plurality of lock bit storage units 102a-102n provided corresponding to memory blocks 100a-100n, respectively. Lock bit storage units 102a-102n store lock bits LBa-LBn, respectively, indicating inhibition/permission of writing and erasing with respect to corresponding memory blocks 100a-100n. The values of lock bits LBa-LBn indicate whether programming/erasure of memory blocks 100a-100n is allowed or not. Therefore, the writing/erasing operation can be inhibited on a block-by-block basis.
The conventional nonvolatile semiconductor memory device further includes a program/erasure control circuit 103 receiving a chip enable signal /CE, a reset power down mode signal /RP, a write protect signal /WP and a block address signal for controlling the programming/erasing operation of a memory block specified by the block address signal according to lock bits LBa-LBn stored in protect control data storage region 102, and a program/erase circuit 105 for carrying out erasure/programming on a memory block (or page) specified by the address signal under control of program/erasure control circuit 103.
Program/erasure control circuit 103 determines whether a write/erase operation mode is specified or not according to the states of reset power down mode signal /RP and write protect signal /WP when chip enable signal /CE is active. If a write/erase operation is specified, a lock bit LB (LBa-LBn) is read out from the lock bit storage unit provided corresponding to the memory block that is specified by the block address signal, whereby inhibition/permission of write/erasure with respect to the addressed memory block is determined. When a write/erasure operation is permitted, program/erasure control circuit 103 generates a voltage required for programming/erasing and provides the generated voltage to program/erasure circuit 104.
Program/erasure circuit 104 includes an X decoder and a Y decoder that selects a block and a memory cell in memory array 100 according to an address signal.
In the conventional nonvolatile semiconductor memory device, the write protect feature that provides protection with respect to writing and erasing operations has these operations controlled according to reset power down mode signal /RP, write protect signal /WP, and the state of lock bit LB read out from the addressed memory block.
As shown in FIG. 14, memory array 100 is divided into a plurality of regions 100br, 100pr, and 100mr, each including at least one memory block. The nonvolatile semiconductor memory device stores program and data. Allocation of memory blocks to each storage region is determined according to the attribute (or type) of the stored data. In FIG. 14, memory array 100 is divided into a boot block region 100br for storing a boot code and the like that is required at the time of initialization when the power is turned on, a parameter block region 100pr for storing numeric parameters such as a telephone number and identification number that is uniquely used by a manufacturer and a personal user, and a main block region 100mr for storing data that is to be rewritten arbitrarily during actual usage. In the array division structure shown in FIG. 14, a write protect feature as shown in FIG. 15 is implemented according to external control signals /RP and /WP and the lock bit as described below.
(i) When reset power down mode signal /RP is set to a boosted level HH that is higher than the voltage level of a logical high level (H level) in a normal operation mode, writing or erasure can be carried out on all memory blocks 100a-100n in memory array 100 regardless of the state of write protect signal /WP and the value of lock bit LB. The value of lock bit LB can also be rewritten. The writing/erasure of the data in memory array 100 and the writing/erasure (rewriting) of lock bit LB are specified by a command.
(ii) When reset power down mode signal /RP and write protect signal /WP are both set at an H level, writing and erasing can be carried out on boot block region 100br, parameter block region 100pr and main block region 100mr regardless of the value of lock bit LB. Also, writing/erasure can be carried out on lock bit LB.
(iii) When reset power down mode signal /RP is at an H level and write protect signal /WP is at a logical low level (L level) of the ground voltage, writing/erasure is inhibited/permitted according to the value of a corresponding lock bit LB provided for respective memory blocks 100a-100n. When the value of lock bit LB indicates a lock state, writing and erasure on the corresponding memory block is inhibited. When the value of lock bit LB indicates an unlock state, writing and erasing can be carried on the corresponding memory block. Also, the value of lock bit LB can be rewritten.
(iv) When reset power down mode signal /RP is at an L level, the nonvolatile semiconductor memory device is set to a power down mode, so that internal operation is inhibited. In this power down mode, the nonvolatile semiconductor memory device attains a standby state, so that consumed current is reduced. Under this circumstance, no rewriting of the stored information should occur. Data rewriting (including writing and erasing) of all the memory cells in boot block region 100br, parameter block region 100pr and main block region 100mr in memory array 100 is inhibited regardless of the value of lock bit LB. Similarly, the value of lock bit LB also cannot be rewritten.
The usage of lock bit LB allows the writing and erasing operation to be inhibited/permitted (lock/unlock) by every memory block. The stored data can be prevented from being rewritten by erroneous erasure and programming. Thus, the required data can be reliably retained.
Inhibition/permission of writing and erasing on a memory block basis can be specified by lock bit LB. The validity/invalidity of lock bit LB, i.e., whether writing or erasing is to be carried out independent of the value of lock bit LB, can be set by externally applied control signals, namely reset power down signal /RP and write protect signal /WP. Under the above-described conventional lock control for providing the control of inhibition/permission of writing and erasing, the lock control status is determined in common to all the block regions of the boot block region, the parameter block region, and the main block region according to external control signals /RP and /WP. More specifically, there are three states of (i) permitting writing and erasing on all memory cells of memory array 100 regardless of the value of lock bit LB; (ii) determine inhibition/permission according to lock bit LB; and (iii) inhibiting writing and erasing regardless of the value of lock bit LB. In boot block region 100br of memory array 100, the boot program code for initializing the system (equipment: an entire equipment incorporating the nonvolatile semiconductor memory device) when the power is turned on and the control program code required for an interruption process and the like are stored. Reset power down mode signal /RP is set to an HH level when the information required for the nonvolatile semiconductor memory device (referred to as "data" hereinafter including both the code and data) is to be written. This setting is implemented by the manufacturer. In general, reset power down mode signal /RP will not be set to an HH level by a general user (HH level corresponds to a voltage of a further higher level than the normal H level).
Specific numeric parameters such as the identification number, time information and the like for the nonvolatile semiconductor memory device are stored in parameter block region 100pr. Additionally, information depending on the application such as the identification number of a personal user, the password number of an IC card, for example, the telephone number of a portable telephone, or the telephone number and address data for implementing the memorandum feature of a portable information terminal are stored in parameter block region 100pr. In main block region 100mr, audio information for realizing an answer telephone function, and image information of a digital camera and the like according to its application are stored, which can be constantly used and rewritten by the general user. The stored data includes data that must not be rewritten and data that may be rewritten.
However, in the conventional nonvolatile semiconductor memory device shown in FIG. 15, there is a possibility of erroneous writing and erasing where data that should not be rewritten is erroneously altered since inhibition/permission of writing and erasing is set in common to all the memory blocks in memory array 100 when used by the general user. For example, when signals /RP and /WP are both set at an H level, writing/erasing can be carried out on each region of memory array 100. Therefore, the data in all the memory blocks can be rewritten. In this case, there is a possibility of erroneous writing/erasing since the write protect feature is disabled. When signals /RP and /WP are set to an H level and an L level, respectively, the inhibition/permission of writing/erasing is controlled according to the value of lock bit LB. However, the value of lock bit LB can be modified. This means that there is a possibility of erroneous writing/erasing when an erroneous value of lock bit LB is set since control of inhibition/permission of writing/erasing is carried out according to the set value of lock bit LB.
In order to ensure that the numeric parameter once set in the parameter block region is not rewritten during the usage by a general user, it is preferable to control writing/erasing according to the value of lock bit LB as to the writing/erasing operation on a memory block in main block region 100mr while setting a lock state for parameter block region 100pr. However such lock control cannot be realized in the conventional nonvolatile semiconductor memory device shown in FIG. 15.
Furthermore, when a programming or erasing operation is carried out, inhibition of rewriting the value of lock bit LB cannot be specified. There is a possibility of setting lock bit LB for another memory block to an unlock state, which will result in erroneous writing/erasure.
Thus, it was difficult to prevent erroneous writing/erasing reliably when the lock status is set using a reset power down mode signal /RP and a write protect signal /WP.

Semiconductor memory device having data protection feature


A linear ball bearing mounting flange, which is provided on at least one end of an outer cylinder of a linear ball bearing and is used for mounting the linear ball bearing on a machine or apparatus. The flange includes a flange-shaped structure having a thick wall and provided separately from the outer cylinder. The flange-shaped structure has an annular recess extending from one end surface of the flange-shaped structure along the inner peripheral surface thereof; a peripheral wall on the inner peripheral side of the recess, which has a jagged structure in which projections and recesses are alternately arranged along the circumferential direction; and a claw projecting inward from the inner peripheral wall, which is formed at the leading end of each of the projecting portions of the jagged structure. When the flange is inserted around the outer cylinder of the linear ball bearing, the claws are locked in a claw insertion hole provided in the outer cylinder. Such a linear ball bearing mounting flange, which can be simply, easily mounted on the outer cylinder of the linear ball bearing, can be manufactured at a low cost.

1. Field of the Invention
The present invention relates to a linear ball bearing mounting flange, and a method of fabricating a linear ball bearing with a flange.
2. Description of the Prior Art
Linear ball bearings have been extensively used for industrial robots, measuring devices, medical devices, computer terminal devices, and the like. In general, such a linear ball bearing has an annular groove provided around an outer periphery of each end portion of an outer cylinder, as disclosed in Japanese Patent Laid-open No. Hei 3-14907, wherein the linear ball bearing is mounted on a machine or apparatus by inserting the outer cylinder in a hole formed in the machine or apparatus and fixedly inserting an elastic ring or the like in the annular groove. In recent years, however, linear ball bearings of a different type have come to be widely used, in which a flange for mounting the bearing on a machine or apparatus is previously provided around an outer cylinder, wherein the linear ball bearing is mounted on the machine or apparatus by means of the flange mounted on the end portion of the outer cylinder.
In fabrication of such a linear ball bearing with a flange, a flange has been mounted on an outer cylinder of the linear ball bearing by screwing or brazing.
FIG. 11(a) is a view illustrating a method of mounting a flange on an outer cylinder of a bearing by screwing, and FIG. 11(b) is an enlarged view of an essential portion in FIG. 11(a); and FIG. 12(a) is a view illustrating a method of mounting the flange on the outer cylinder of the bearing by brazing; and FIG. 12(b) is an enlarged view of an essential portion in FIG. 12(a). In these figures, reference numeral 1 indicates an outer cylinder of a linear ball bearing; 2 is a linear ball bearing mounting flange having mounting holes 2a; 11 is a screw portion between the flange 2 and the outer cylinder 1; and 12 is a brazing portion between the flange 2 and the outer cylinder 1.
The screw portion used for mounting the flange on the linear ball bearing is obtained by screwing a threaded portion 1a formed around the outer cylinder 1 of the linear ball bearing with a threaded portion 2b formed around the flange 2.
The mounting method by screwing, however, has the following problems that:
(1) since an end portion 1b of the outer cylinder 1 of the linear ball bearing is structurally thinned, it is possibly cracked; PA1 (2) the screw portion 11 is liable to be loosened when the linear ball bearing is applied with an impact force; and PA1 (3) when screwed around the outer cylinder, the flange is often bent, that is, the screwing angle of the flange cannot be kept constant, so that there occur variations in machining allowance in the step of machining the flanges at right angles, resulting in the poor productivity. PA1 (1) since the outer cylinder 1 is press-fitted in the flange 2, the inside diameter of the flange 2 and the outside diameter of the outer cylinder 1 must be finished at high accuracies respectively, resulting in the increased cost of each product; PA1 (2) since being heat-treated together with the outer cylinder 1, the flange 2 is liable to be deformed, so that there occur variations in machining allowance in the step of machining the flanges at right angles, resulting in the poor productivity; and PA1 (3) the work for setting a brazing material in the brazing step must be performed for each product, resulting in poor productivity. PA1 (1) A linear ball bearing mounting flange, which is provided on at least one end of an outer cylinder of a linear ball bearing and is used for mounting the linear ball bearing on a machine or apparatus, the flange including: a flange-shaped structure having a thick wall and provided separately from the outer cylinder, the flange-shaped structure having an annular recess extending from one end surface of the flange-shaped structure along the inner peripheral surface thereof; a peripheral wall on the inner peripheral side of the recess, which has a jagged structure in which projections and recesses are alternately arranged along the circumferential direction; and a locking piece projecting inward from the inner peripheral wall, which is formed at the leading end of each of the projecting portions of the jagged structure. PA1 (2) In a linear ball bearing with a flange described in (1), the flange-shaped structure includes at least three pieces of the projecting portions. PA1 (3) In a linear ball bearing with a flange described in (1), the flange-shaped structure has a partially circular shape in a front view, in which two circular-arc portions are cut off from a circular shape by two straight lines parallel to each other. PA1 (4) In a linear ball bearing with a flange described in (1), (2) or (3), the flange-shaped structure is made from a synthetic resin. PA1 (5) A method of fabricating a linear ball bearing with a flange in which a flange is provided on at least one end of an outer cylinder of a linear ball bearing and is used for mounting the linear ball bearing on a machine or apparatus, including the steps of inserting the flange-shaped structure described in (1), (2) or (3) around an end portion of the outer cylinder and locking locking pieces of the flange-shaped structure in an annular groove provided around the outer cylinder. PA1 (6) A method of fabricating a linear ball bearing with a flange in which a flange is provided on at least one end of an outer cylinder of a linear ball bearing and is used for mounting the linear ball bearing on a machine or apparatus, including the steps of inserting the flange-shaped structure described in (1), (2) or (3) around an end portion of the outer cylinder, engaging locking pieces of the flange-shaped structure in an annular groove provided around the outer cylinder, and press-fitting a wedge-like member in the annular groove for reinforcing the locking of the locking pieces with the annular groove. PA1 (7) In a linear ball bearing described in (5) or (6), the flange-shaped structure is made from a synthetic resin.
To solve the above problems of the mounting method by screwing, the mounting method by brazing has been adopted; however, such a method has also the following problems that:
In general, the flange integrated with the outer cylinder of the linear ball bearing has other problems that the outer periphery of the linear ball bearing cannot be continuously ground because of the presence of the flange; the assembling direction is limited because of the presence of the flange, resulting in the degraded workability; and since the linear ball bearing integrated with the flange has a T-shape, it is difficult to align the linear ball bearings in line because of the unstable postures when being transferred between fabrication steps.

Method of fabricating a linear ball bearing with a flange


Techniques for routing and shielding signal lines to improve isolation between the signal lines are disclosed. In an exemplary design, an apparatus includes first, second, and third signal lines and a switch. The first, second, and third signal lines are configurable to carry first, second, and third signals, respectively. The switch is coupled between the second signal line and AC ground and is closed when the second signal line is not carrying the second signal. The second signal line isolates the first and third signal lines when the switch is closed. Adjacent signal lines are not active at the same time. A signal line may include positive and negative signal lines, which may have at least one cross over in order to cancel coupling between the positive and negative signal lines.

I. Field
The present disclosure relates generally to electronics, and more specifically to techniques for routing and shielding signal lines.
II. Background
An electronics device such as a wireless communication device or an integrated circuit (IC) may include various circuits to perform designed functions. These circuits are typically connected by signal lines via which various signals are passed between the circuits. The signal lines may also be referred to as routes, traces, interconnections, etc. Ideally, the circuits should be located close to each other so that the signal lines are as short as possible. Short signal lines may provide various advantages such as better signal quality of signals passed via the signal lines, less area to form the signal lines, etc. However, it is often not possible to maintain all signal lines short. Inevitably, some longer signal lines are required to connect some circuits located relatively far from each other. There may be coupling between signal lines, e.g., due to electro-magnetic coupling, capacitive coupling, etc. Hence, a signal may be sent on one signal line and may be coupled to one or more other signal lines. The signal may act as interference to other signals on other signal lines. It may be desirable to implement signal lines such that good isolation can be obtained.

Routing and shielding of signal lines to improve isolation


A passive element memory device is provided that includes memory cells comprised of a state change element in series with a steering element. Controlled pulse operations are used to perform resistance changes associated with set and reset operations in an array of memory cells. Selected memory cells in an array are switched to a target resistance state in one embodiment by applying a positive voltage pulse to selected first array lines while applying a negative voltage pulse to selected second array lines. An amplitude of voltage pulses can be increased while being applied to efficiently and safely switch the resistance of cells having different operating characteristics. The cells are subjected to reverse biases in embodiments to lower leakage currents and increase bandwidth. The amplitude and duration of voltage pulses are controlled, along with the current applied to selected memory cells in some embodiments. These controlled pulse-based operations can be used to set memory cells to a lower resistance state or reset memory cells to a higher resistance state in various embodiments.

1. Field of the Invention
Embodiments in accordance with the present disclosure are directed to integrated circuits containing non-volatile memory cell arrays and particularly those arrays incorporating passive element memory cells.
2. Description of the Related Art
Materials having a detectable level of change in state, such as a resistance or phase change, are used to form various types of non-volatile semiconductor based memory devices. For example, simple antifuses are used for binary data storage in one time field-programmable (OTP) memory arrays by assigning a lower resistance initial physical state of a memory cell to a first logical state such as logical '0,' and assigning a higher resistance physical state of the cell to a second logical state such as logical '1.' Some materials can have their resistance switched back in the direction of their initial resistance. These types of materials can be used to form re-writable memory cells. Multiple levels of detectable resistance in materials can further be used to form multi-state devices which may or may not be re-writable.
Materials having a memory effect such as a detectable level of resistance are often placed in series with a steering element to form a memory cell. Diodes or other devices having a non-linear conduction current are typically used as the steering element. The memory effect of the cell is often referred to as the state change element. In many implementations, a set of word lines and bit lines are arranged in a substantially perpendicular configuration with a memory cell at the intersection of each word line and bit line. Two-terminal memory cells can be constructed at the intersections with one terminal (e.g., terminal portion of the cell or separate layer of the cell) in contact with the conductor forming the respective word line and another terminal in contactor with the conductor forming the respective bit line. Such cells are sometimes referred to as passive element memory cells.
In some cases, bias conditions during read and write operations are an important consideration when implementing non-volatile memory arrays having passive element memory cells comprising switchable resistance materials or phase change materials as the state change element. High bias conditions applied to program these cells can restrict the endurance of the steering element. High leakage currents, program disturbances, read disturbances, etc. can pose difficulties when attempting to produce a memory device comprising one or more arrays of passive element memory cells that can be reliably fabricated, programmed, and read. Moreover, slight differences between individual memory cells can pose difficulty when attempting to program multiple cells individually or concurrently.

Systems for controlled pulse operations in non-volatile memory


Various embodiments disclosed herein that facilitate a dynamic self-backhaul reconnection using a radio resource control messaging. According to some embodiments, a system can comprise detecting a failure in a first backhaul communication link with a first node device, wherein the first node device is communicatively connected to a core network device of a core network, selecting a second node device, other than the first node device, that is communicatively connected to the core network device for establishment of a second backhaul communication link to replace the first backhaul communication link, and facilitating establishing a first connection with the second node device to provide an indication of the failure of the first backhaul communication link, to provide a confirmation that the second node device is available in connection with establishment of the second backhaul communication link, and to request to reserve resources to establish the second backhaul communication link with the second node device.

5th generation (5G) wireless systems represent a next major phase of mobile telecommunications standards beyond the current telecommunications standards of 4th generation (4G). In addition to faster peak Internet connection speeds, 5G planning aims at higher capacity than current 4G, allowing a higher number of mobile broadband users per area unit, and allowing consumption of higher or unlimited data quantities. This would enable a large portion of the population to stream high-definition media many hours per day with their mobile devices, when out of reach of wireless fidelity hotspots. 5G research and development also aims at improved support of machine-to-machine communication, also known as the Internet of things, aiming at lower cost, lower battery consumption, and lower latency than 4G equipment. 5G needs to support various applications including enhanced mobile broadband (eMBB), mission critical, and ultra-reliability and low latency (URLLC) applications is a key feature of the 5G network. High level of densification of small cells with millimeter wave (mmW) Transmit and Receive Point (TRP) and the self-backhaul capability are the technology advances of 5G to meet the bandwidth demand. To achieve high reliable 5G network, improving the transport availability of the mmW TRPs is critical.
The above-described background relating to facilitating a self-backhaul communication system, is merely intended to provide a contextual overview of some current issues, and is not intended to be exhaustive. Other contextual information may become further apparent upon review of the following detailed description.

Dynamic self-backhaul reconnection using an enhanced radio resource control messaging for 5G and other next generation networks


The pipe treatment apparatus rotates a pipe to be treated, from the pipe exterior. The apparatus provides easy adaptation to varied pipe lengths and pipe diameters. The blast nozzle delivers blast media to the pipe interior to clean and prepare the interior for coating. The spray head delivers various chosen coatings to the pipe interior. The blast nozzle and spray head are easily installed and removed. The trolley and telescopic member with c-channel, along with the longitudinal drive motor with drive roller propel either the blast nozzle or spray nozzle into, within, and out of the pipe, as the rotational motor and transverse rollers turn the pipe from the pipe exterior. The apparatus therefore provides a basic design with which pipe can be both cleaned and coated within.

Pipe is used to transport a variety of substances which partially include oil, gasses, and water. At least two significant concerns are present. The first concern is pipe longevity which is strongly related to what is carried within a pipe. Another is flow within the pipe, which relates to interior surface friction. These two concerns may dictate that pipe be internally cleaned and coated. Methods and equipment for performing both cleaning and coating tasks vary greatly. Few devices are capable of performing both tasks. Methods and equipment also differ in choices of whether to move the pipe around and longitudinally along equipment or to move the equipment within and along the length of the pipe. Rotating equipment for cleaning and coating pipe interior, within the pipe, requires many additional safeguards against invasion of such equipment, especially by blast media used to clean the pipe interior. Painting equipment is also subject to greater safeguards if the equipment must be rotated within the pipe.
And, rotating blast and painting equipment within the pipe is inherently more complex and expensive. Another problem encountered in cleaning and coating pipe interiors is the adaptation of equipment to a wide variety of pipe interior dimensions. Most devices are severely limited with respect to accommodating a plurality of widely diverse interior pipe diameters. Accommodating a wide diversity of pipe lengths is also problematic. An ideal apparatus for treating the interior of pipes should therefore both clean and coat the pipe interior. The ideal apparatus should be as basic as is possible and still provide automated operation. The ideal apparatus should rotate the pipe, and not the cleaning and painting equipment, thereby lending its design to a more basic level and the equipment used to less expensive provision and construction. The present apparatus provides these advantages.


An object detection system for detecting instances of an object in a digital image includes an image integrator and an object detector, which includes a classifier (classification function) and image scanner. The image integrator receives an input image and calculates an integral image representation of the input image. The image scanner scans the image in same sized subwindows. The object detector uses a cascade of homogenous classification functions or classifiers to classify the subwindows as to whether each subwindow is likely to contain an instance of the object. Each classifier evaluates one or more features of the object to determine the presence of such features in a subwindow that would indicate the likelihood of an instance of the object in the subwindow.

Computers perform processing of graphic images in a digital format (e.g., photographs, still images from videos, and so on). Often, the goal of this processing is to locate objects of interest (e.g., faces) in an image. Given enough processing time to process an image (typically using a digital processor), a computer is capable of detecting most or all well defined instances of an object in an image. One common goal for object detection is the detection of human faces, although computers can use object detection to detect various types of objects in an image. This process of detecting objects (e.g., faces) is useful for user interfaces, the scanning of image databases, in teleconferencing, electronic processing of photographs, and other suitable areas. The appearance of objects varies greatly across individuals, images, camera locations, and illuminations.
There are a number of existing methods for detecting objects (e.g., faces) in images. Most existing, prior art approaches for detecting objects (e.g., faces) in an image share a number of properties. First, for example, the conventional object detector uses a learning algorithm based on a training data set that contains many examples of face and non-face image patches (the smallest possible region that might contain a face—usually, a patch or subwindow 16×16 or 20×20 pixels). One such learning algorithm is based on conventional neural network approaches. In a learning phase based on a training data set, the learning algorithm constructs a classification function which can label patches as either face or non-face.
Finally, in a conventional approach, an object detector uses a scanning process to enumerate all possible patches (subwindows) within a given image. Each image contains many independent patches. Every unique location and scale in the image can yield an independent patch. In practice, a 320 pixel×240 pixel image can produce approximately 50,000 patches (the number of patches scales quadratically with the scale of the image). The classification function is run against all such patches to detect the possible presence of an instance of the object in the patch. When an object detector, through one or more classification functions, detects an object (e.g, a face), the object detector records the location and scale of the patch for later output (e.g., reporting to an end-user of the computer).
To detect an object in a patch, many conventional, prior-art approaches work directly with intensity values (grayscale degree of lightness or darkness) of the pixels of the patches. In one prior art approach, the object detection software uses wavelet functions, such as Haar Basis functions that evaluate boxes in a patch, to detect an object in a patch.

Method and system for object detection in digital images

Hewlett-Packard Development Company, L.P.