The present invention provides a trading keyboard that can be configured both physically and functionally according to a user's preferences. The trading keyboard preferably includes self-identifying key covers that can be physically arranged on any of the keyboard's key bases. Detection mechanisms included in the key bases detect the commands of the trading application associated with each self-identifying key cover. Therefore, the user may reposition the key covers on the keyboard according to the user's preferences, and yet retain the same functionality for the key covers. The user may also switch between keyboard modes that allow the keyboard to be functionally reconfigured. By selecting different modes, the user can chose between different keyboard mapping configurations that assign the functions of the trading application to the keys in different arrangements. The mode selection mechanism may also be used to select between different commands associated with a single key or key cover.

Trading keyboards are often used by financial professionals to enter and execute commands in a trading application. The financial professionals who use trading keyboards may use different keyboards extensively in their work and become accustomed to particular arrangements of the keys on the trading keyboards. The financial professionals may therefore develop different preferences for physical or functional arrangements of the keys. Therefore, a financial professional may be faced with an unfamiliar trading keyboard when, for example, using a different trading system or a change is made to the trading application implemented on a processor. Using an unfamiliar trading keyboard may lead to costly data entry mistakes by the financial professional. As a result, trades that were not intended may be processed and volumes of trading orders may be incorrectly executed. Conventional trading keyboards do not allow the financial professional to change the physical and/or functional arrangements of the keys therein.
Moreover, trading keyboards should accommodate all of the commands that may be associated with a trading application. However, if an individual key were assigned to each and every possible command, the trading keyboard would be large and unwieldy to use.
Therefore, there is a need for a trading keyboard in which the key arrangement may be physically configurable by a user.
There is also a need for a trading keyboard in which the key arrangement may be configurable by the user without implicating the trading application.
There is also a need for a trading keyboard in which the key arrangement is functionally configurable by the user such that each key of the keyboard may be associated with different commands in each configuration.

This patent is subject to a terminal disclaimer.


Heliostat devices are disclosed. A disclosed heliostat device comprises planar reflectors and their frame, an azimuth angle adjusting mechanism and an altitudinal angle adjusting mechanism, and a sunlight tracking sensor. This device can perform sun tracking and accurate projection in fixed direction, via the directed sensor mounted in the fixed projection direction to form multi-stage control sensors.

The heliostat is an important device frequently involved in the utilization of solar energy, and it is mainly used in lighting or thermal power generation with solar energy.
For instance, in thermal power generation with a tower using solar energy, the solar heat radiation is reflected by a number of heliostats to a solar receiver mounted on top of a high tower, to heat the medium to produce superheated steam, or to directly heat water in the heat collector to produce superheated steam, which then drives the turbo-generator set to generate electricity, thus converting solar energy into electrical energy. To enable the solar radiation to be reflected onto the fixed receiver by reflectors at all times during the day, a tracking mechanism must be provided for the reflectors. To control the tracking mechanism, two forms are mainly adopted nowadays, namely, programmed control and control by sensors. With programmed control, the movement of the dual-shaft tracking mechanism is controlled according to the calculated sun movement route. Programmed control has the shortcoming of accumulated error and high cost. With control by sensors, the movement of the tracking mechanism is controlled according to the incident sun radiation direction measured by the sensors. Control by sensors has the shortcomings that: (a) it cannot control the reflected light directly, (b) as there is mechanical error in precision that cannot be overcome, it is difficult to ensure accurate tracking and positioning by solely relying on the tracking sensors mounted on the tracking mechanism, and (c) it cannot realize stable and reliable control.


Various arrangements are directed to locating a television receiver. Multiple tuners of the television receiver may be simultaneously tuned to different television distribution satellites to receive timing signals. Using these timing signals, the location of the television receiver may be determined Based on a comparison between a stored, expected location of the television receiver and the determined location, the functionality of the television receiver may be adjusted.

Satellite television service allows for delivery of a large volume of content (e.g., television channels, on-demand content) to subscribers' locations via satellite. While use of a satellite-based distribution architecture avoids the need of a wired infrastructure, satellite-based broadcasts can increase the likelihood of subscription-based services being surreptitiously obtained. For example, a person providing a false address for use of a television receiver may allow the person to acquire services they would otherwise not be entitled to use at the television receiver.
For this reason and/or possibly others, it may be useful for a television receiver to be able to determine its own location.

Use of television satellite signals to determine location


A multilayer papermaker's press felt fabric comprising in combination a woven first fabric layer, typically a double layer fabric, has a cross machine direction pin seam. A second fabric layer is located on the paper side face of the first fabric layer, and a layer of needled batt is applied to the paper side face of the second layer binding the layers together. A flap comprising a short length of the second fabric layer with attached batt overlays the pin seam area in the first layer. The second layer comprises a plurality of relatively narrow strips, which are located with a lateral edge at a first cant angle of from more than 1° to less than 20° to the machine direction. A third layer, similar to the second layer, can be included on the machine side of the first layer; the strip widths, the cant angles, and the direction of the cant angle relative to the machine direction for each of the two strips need not be the same. The fabric is assembled using a spiral winding technique.

This invention relates to press felts, which are used in the press section of a paper making machine. In this part of the papermaking machine, the paper web, which may contain up to about 85% water, is passed between pairs of opposed rolls so that a large proportion of this water is literally squeezed out of the wet paper web. In this process, the wet paper web is supported by at least one, or conveyed between two opposed fabrics known as press felts. These press felts are generally constructed with a fabric base structure, which has layers of batt needled to at least one, and generally to both, of its surfaces. Several fabric constructions are used for the base fabric structure, including both single layer and double layer woven fabrics, and the fabrics can be woven either flat as a continuous run, or endless as a closed loop. Endless felts require that the press section be opened up to allow their installation. Seamed felts are open ended for installation and the ends are subsequently joined by seaming, for example with a pin seam, on the press section. In either case, in order to be able to install the finished fabric into a press section, it is often advantageous to make provision for a seam that can be closed during installation in the press section.
The seam is the most difficult part of the press fabric to make. For although it is relatively straight forward to create a press felt which will provide the required properties of adequate strength, adequate drainage, and lack of fabric marking, whether or not it can be used depends upon also being able to provide a seam in the fabric which has an adequate life in service, provides the required strength, provides the required drainage, and most importantly does not cause marking of the paper.
The most commonly used seam in press felts is a pin seam, in which monofilament yarns from each of the two ends of the fabric which are to be joined are woven back into the fabric ends to provide a set of small loops. The two fabric ends are joined by interdigitating the two sets of loops, and inserting a pintle across the width of the fabric. This form of seam is most often used in press felts based on double layer woven fabrics. Examples of such seams are shown in EP 0 294 951, U.S. Pat. No. 4,842,925 and U.S. Pat. No. 4,601,785.
These conventional press felts offer the benefits of ease of installation, and ease of seam assembly on the machine. But they have the disadvantages of being limited to applications which can tolerate at least some marking of the paper by the seam, and where the drainage requirements are modest. A further disadvantage is that the applied batt wears more rapidly in the seam area. An area of worn batt cover over the seam area increases the danger of marking, and also accelerates even more the rate of wear in the seam area. This leads to premature press felt failure due to either paper marking problems, or mechanical seam failure, or both.
Several proposals have been made to overcome these difficulties.
One that has been made is to use two woven fabric layers, rather than one, to provide what may be termed a laminated base structure. Fabrics of this type are shown in U.S. Pat. No. 3,086,276, wherein the fabric layers are disposed in a bias relationship, and in U.S. Pat. No. 3,657,068 in which a relatively fine and a relatively coarse fabric are disposed on each side of a layer of batt. An alternative fabric is shown in U.S. Pat. No. 5,110,672. In these references, the layers are laminated together by the batt which in the needling application process is forced into engagement with all of the layers. A problem common to all of these structures is that the cut fabric ends adjacent the seam tend to unravel, thus leaving the batt more or less unsupported in the most important area of the fabric. This leads to marking of the paper, and to premature seam failure.
Alternatively, it has been proposed to use a laminate structure, examples of which are described in U.S. Pat. No. 4,186780 and in U.S. Pat. No. 4,418,726, and to pin seam each of the fabrics in the laminate. Apart from the fact that this does not eliminate any of the difficulties attendant on a single pin seam, it further complicates installation, as there are now two seams to be closed, not one. Such an installation step is difficult, time consuming and defeats the original purpose of the seam, which is to provide ease of installation.
Another proposal is to provide what may be termed a "flap" of batt, which may be reinforced with a portion of the fabric base, that will overlay a conventional pin seam, preferably on the paper side of the fabric. Examples of this are described in CA 1,303,833 and EP 0 294 951 mentioned above. In each of these, in constructing the pin seam, a short flap of batt is provided which is attached to one of the ends to be joined and which is intended to cover the joint after the pin seam has been assembled. In U.S. Pat. No. 4,601,785 it is recommended to attach the batt flap by gluing or needling. In U.S. Pat. No. 4,842,925 it is recommended to use brittle or soluble yarns adjacent the seam. Either during or following the needling step to attach the batt these yarns are removed thus allowing the batt flap to be cut and placed in position. In EP 0 294 951 it is recommended to use an additional layer of machine direction yarns in the base fabric to reinforce the batt flap. Seams such as these are also difficult to assemble, and suffer from the disadvantage that the fabric in the flap supporting the batt also ends to unravel, thus leaving the batt unsupported which results in marking of the paper.

Multiaxial pin seamed papermaker's press felt


A low-sediment, low-tar, chlorine-free thermal process for preparing oil-soluble polyalkenyl derivatives of monounsaturated C.sub.3 -C.sub.10 monocarboxylic acid producing compounds and monounsaturated C.sub.4 -C.sub.10 dicarboxylic acid producing compounds is disclosed. The process involves reacting the mono- or dicarboxylic acid producing compound with a polyalkene at high temperature and under high inert gas partial pressure in the presence of a sediment-inhibiting amount of hydrocarbyl substituted sulfonic acid. The polyalkenyl derivatives are useful per se as additives in lubricating oils, functional fluids, and fuels and are also useful as intermediates in the preparation of other products (e.g., succinimides) useful as additives in lubricating oils, functional fluids, and fuels.

Polyalkenyl substituted mono- and dicarboxylic acid producing materials, most notably polyisobutenyl succinic acids and anhydrides, are known intermediates for the preparation of products useful as additives in lubricants, fuels, and functional fluids. In particular, succinamide and succinimide products produced by the reaction of monoamines or polyamines with polyalkenyl succinic anhydrides have been employed as ashless dispersants and detergent additives in lubricating oils and in fuels. Succinic esters produced by the reaction of monoalcohols or polyols with polyalkenyl succinic anhydrides have also been used as ashless dispersants and detergents.
Polyalkenyl substituted mono- and dicarboxylic acid producing materials have been prepared using a one-step chloro process in which a polyalkene and an unsaturated mono- or dicarboxylic acid producing compound are reacted at elevated temperature in the presence of chlorine. The polyalkenyl mono- or dicarboxylic acid materials have also been prepared using a two-step chloro process in which the polyalkene is chlorinated in the first step and the resulting chlorinated polyalkene is then reacted with the unsaturated mono- or dicarboxylic compound at elevated temperature. The one- and two-step chloro processes can produce polyalkenyl substituted mono- or dicarboxylic acid materials in relatively high yields and without the formation of substantial amounts of sediments and other undesirable byproducts. On the other hand, these products typically contain residual chlorine, and environmental concerns related to chlorine-containing materials make the use of the chloro processes undesirable.
The polyalkenyl substituted carboxylic materials can also be prepared by the direct thermal reaction of a polyalkene and an unsaturated mono- or dicarboxylic acid compound, often referred to in the art as the thermal ene process. While the thermal ene process has the advantage of avoiding the use of chlorine, the reaction tends to proceed only slowly and with low yields at reaction temperatures below about 150.degree. C. At higher reaction temperatures, the thermal ene process typically has better yields, but it also tends to produce significant amounts of a sediment byproduct which must be filtered from the final product prior to its use as an additive or intermediate. The process also tends to produce tars, which coat the reactor walls, necessitating frequent, time-consuming, and therefore costly clean-ups of the reactor vessel. These sediments and tars are believed to be due at least in part to the decomposition and/or polymerization of the unsaturated mono- or dicarboxylic acid compound, which has typically been maleic anhydride.
Additives can be employed in the thermal ene reaction in order to reduce the formation of tars and sediments. For example, U.S. Pat. No. 4,235,786 discloses that sediment formation in the ene reaction can be markedly reduced by the presence of a sediment-reducing amount of an oil-soluble strong organic acid. The patent discloses that the oil-soluble strong organic acid is preferably a C.sub.15 -C.sub.70 optimally C.sub.28 -C.sub.36 hydrocarbyl substituted sulfonic acid. Example 1 discloses that a polyisobutylene having a number average molecular weight ("M.sub.n ") of 900 was reacted with maleic anhydride at 235.degree. C. for 6 hours under a pressure maintained at about 150 kPa in the presence of an alkylated benzene sulfonic acid having M.sub.n of 500 and containing an average of about total 30 carbons. The resulting product had 0.2% sediment. The procedure of Example 1 was followed in Example 2 except that no sulfonic acid was present. The resulting product had 3.0% sediment, based upon which the patent discloses that it is apparent that the presence of about 0.13 wt.% of an acid reduced the sediment formation by 93%.
Improved thermal ene processes utilizing polyalkene reactants having a relatively high proportion of terminal double bonds have also been disclosed. Terminal double bonds, particularly terminal vinylidene bonds, in polyalkenes are recognized to be generally more reactive in the thermal ene process than internal double bonds. U.S. Pat. No. 4,152,499, for example, discloses that adduct formation between maleic anhydride and polyisobutene virtually only occurs between maleic anhydride and a terminal double bond. U.S. Pat. No. '499 further discloses that double bonds in the .beta. position are also capable of reacting to a certain degree, while virtually no reaction occurs at double bonds further removed from the chain ends. U.S. Pat. No. 4,086,251 discloses that terminal vinylidene is believed to be the most reactive of the terminal double bonds in polybutenes. Conventional polyisobutenes, formed by cationic polymerization using aluminum chloride catalysts such as AICI.sub.3, generally have a relatively low content of terminal double bonds. Polyisobutenes having a high content of terminal double bonds, so-called "reactive" polyisobutenes, have been achieved by BF.sub.3 -catalyzed polymerization of isobutene. Other polyalkenes having a high content of terminal double bonds (e.g., ethylene-.alpha.-olefin copolymers and .alpha.-olefin homo- and copolymers) have been disclosed to be prepared by polymerization of the corresponding monomers in the presence of metallocene catalyst systems.
The improved thermal ene processes utilizing these more reactive polyalkenes have been disclosed to provide products with low sediment and/or low tar. For example, U.S. Pat. No. 5,071,919 discloses a process for preparing substituted succinic acylating agents by reacting an acidic reactant such as maleic anhydride with a substantially aliphatic polymer comprised principally or entirely of polyisobutenes in a mole ratio of acidic reactant:polymer of at least 1:1, provided that at least 50% of the polyisobutene content of the polymer has terminal vinylidene end groups and the reaction is maintained under superatmospheric pressure during at least a substantial portion of the reaction period. The patent discloses that reaction product mixtures formed by this process contain little or no tars. Another example is U.S. Pat. No. 5,229,022 which discloses the thermal ene reaction of ethylene-.alpha.-olefin polymers having a high terminal ethenylidene (i.e., vinylidene) content with monounsaturated carboxylic reactants. The patent discloses that the ethylene-.alpha.-olefin polymers readily undergo thermal ene reactions under conditions in which the formation of sediment or other byproducts contributing to product haze is greatly minimized or avoided altogether. It is further disclosed that the resulting ene reaction product mixture can be employed, without filtering, centrifuging, clarification, phase separation or other conventional product purification treatments.
There is a continuing need for the development of improved thermal ene processes. In particular, while prior art processes employing tar suppressants and sediment inhibitors have reduced the amount of sediments and/or tars, they have not generally not eliminated their formation, particularly as applied to polyalkenes having a low content of terminal vinylidene polymer chains. Accordingly, the products resulting from these processes still typically require treatment to remove sediments and the reaction vessels must still be cleaned regularly to remove tars.

Process for preparing polyalkenyl substituted mono- and dicarboxylic acid producing materials (PT-1302)


A sound reproduction device of the present invention includes: a first loudspeaker; a second loudspeaker; a first loudspeaker drive section for driving the first and second loudspeakers, the first loudspeaker drive section drives the first and second loudspeakers at substantially the same phase in a first frequency band, and the first loudspeaker drive section drives the first and second loudspeakers at substantially inverse phase and substantially different amplitude levels in a second frequency band higher than the first frequency band.

1. Field of the Invention
The present invention relates to a sound reproduction device, and more particularly to a sound reproduction device which can be preferably used in a mobile terminal apparatus.
2. Description of the Related Art
In recent years, mobile terminal apparatuses, such as cellular phones, Personal Handy Phone Sets (PHS) and Personal Digital Assistants (PDA), have come to have an internet connection function, and therefore the mobile terminal apparatuses are becoming more multifunctional. For example, a mobile terminal apparatus having a function of downloading music data from a music distribution server via the internet so as to store the downloaded music data to a semiconductor memory in the mobile terminal apparatus and a function of reproducing the music data stored in the semiconductor memory is produced on a commercial basis.
In the case where music or a ringtone is represented as a two-channel signal, it is desirable that the number of output channels is equal to or more than two. However, in order to provide a plurality of loudspeakers to a mobile terminal apparatus, the plurality of loudspeakers must be positioned so as to be extremely close to each other. This is because a space in the mobile terminal apparatus is very limited.
Conventionally, a method for driving such a plurality of loudspeakers positioned extremely close to each other has not been considered. This is because only one loudspeaker is provided to a conventional mobile terminal apparatus and there is no assumption that a plurality of loudspeakers would be provided to the conventional mobile terminal apparatus.

Matsushita Electric Industrial Co., Ltd.


One aspect of the present disclosure relates to a backplane initiator for testing enclosure management controller. The backplane initiator includes: an initiator board and an initiator control application. The initiator board includes initiator controller, at least one SGPIO interface, at least one SMBus interface, and a first communication interface. The initiator controller is configured to transmit control commands and data according to enclosure management protocol through the SGPIO interface and the SMBus interface to an EMC. The initiator control application, when executed on a computing device having a second communication interface in communication with the first communication interface, is configured to establish a communication channel with the initiator controller through the first and second communication interfaces, and instruct the initiator controller to transmit a first control command and first control data according to enclosure management protocol through the SGPIO interface and the SMBus interface to the EMC.

In large scale computing systems, a backplane is used to mount a number of storage drives and network communication devices, such as Disk Arrays, redundant array of independent disks (RAID) Subsystems, Small Computer System Interface (SCSI) and Fiber Channel (FC) Disk Array or Switched Disk Array Servers, and Telecommunication Equipment. A host bus adapter (HBA) is used to facilitate the communication between a host computer and the backplane, and allows the host computer to monitor and manage the storage and network devices installed on the backplane. The HBA provides an operator with detailed information regarding the presence and status of mass storage devices and network devices, and provides facilities for generating visual indicators based upon backplane management data received from the HBA of the host computer. For instance, individual light-emitting diodes ("LEDs") may be driven by a backplane for displaying information regarding the activity, failure, rebuild status, and other information for each of the mass storage devices connected to the backplane. In order to provide these indicators and other types of functionality, a backplane typically provides connections for multiple mass storage devices, such as hard disk drives. The backplane also interfaces with an HBA and provides an interface through which the HBA may communicate with the mass storage devices. A backplane also may receive and transmit backplane management data to and from the HBA. Backplane management data is any data relating to the provision of backplane management services by a backplane.
Several different physical interfaces may be utilized to deliver backplane management data between an HBA and a backplane. For instance, some Serial Attached SCSI ("SAS")-compatible HBAs are equipped with a serial general purpose input/output interface ("SGPIO"). Some Serial Advanced Technology Attachment ("SATA")-compatible HBAs, on the other hand, utilize a control or management bus, such as the system management bus, to exchange backplane management data between the backplane and the HBA. For various reasons, some vendors have decided on some HBA models, to implement a backplane management protocol based on the SMBus, even for SAS HBAs, which could be for backward compatibility reasons with SATA backplanes.
The particular protocol utilized to transfer backplane management data between the backplane and the HBA may also vary from vendor to vendor. However, the most popular protocols used in the backplane management are: the SCSI Enclosure Services (or SES) utilizing the system management bus (or I2C bus), and the SGPIO protocol utilizing an SGPIO interface to exchange backplane management information between the HBA and the backplane.
Both software and hardware of newly developed enclosure management controller need to be tested for its compatibility with HBAs of various manufactures. In order to provide backplane solutions supporting the various physical interfaces for exchanging backplane management data, the various standard protocols for exchanging backplane management data, and the various manufacturer-specific protocols for exchanging backplane management data, it has previously been necessary to provide HBAs from various manufacturers, and configured for each particular combination of physical interface and protocol to ascertain the software and hardware of newly developed enclosure management controller (EMC) support standard SGPIO commands. However, providing a separate HBA for each combination of physical interface and protocol can be extremely cost-inefficient and time consuming. Conventionally, in order to ascertain compatibility with various vendors' HBA, many actual HBAs were ordered from various vendors to be tested with the new EMCs. But this process can be very costly and time consuming, because a large number of HBAs have to be ordered from various vendors and tested with the hardware and software of the new EMC. For example, it took about one and a half month to two months to test each HBA from one vendor.
Therefore, heretofore unaddressed needs still exist in the art to address the aforementioned deficiencies and inadequacies.

Techniques for testing enclosure management controller using backplane initiator


An exemplary switching power supply circuit (2) includes a power source (20), a pulse width modulation (PWM) circuit (21), a first switching circuit (22), a second switching circuit (23), a first transformer (25), and a second transformer (26). The first switching circuit includes a first transistor (221) and a second transistor (222). The second switching circuit includes a third transistor (231) and a fourth transistor (232). The first transformer includes a first primary winding (251) and a second primary winding (252), and the second transformer includes a third primary winding (261) and a fourth primary winding (262). The switching circuits are controlled by pulse signals from the PWM circuit. When the first and third transistors are switched on, the power source, the first primary winding, and the first transistor form a first closed loop. The power source, the third primary winding, and the third transistor form a second closed loop.

Switching power supply circuits are widely used in coordination with various portable and automated electronic devices and instruments such as LCDs. Referring to FIG. 2, a typical switching power supply circuit 1 includes a power source 10, a pulse width modulation (PWM) circuit 11, a first switching circuit 12, a second switching circuit 13, a first transformer 15, a second transformer 16, and two filter circuits 14.
Each filter circuit 14 includes a resistor 141 and a series capacitor 142. The PWM circuit 11 includes a first output 111 and a second output 112. The first switching circuit 12 includes a first transistor 121 and a second transistor 122. Source electrodes of the first transistor 121 and the second transistor 122 are connected to ground. Gate electrodes of the first transistor 121 and the second transistor 122 are connected to the first output 111. The first output 111 is configured to output pulse voltages to switch on and switch off the first transistor 121 and the second transistor 122. The first and second transistors 121, 122 are metal-oxide-semiconductor field-effect transistors (MOSFETs).
The second switching circuit 13 includes a third transistor 131 and a fourth transistor 132. Source electrodes of the third transistor 131 and the fourth transistor 132 are connected to ground. Gate electrodes of the third transistor 131 and the fourth transistor 132 are connected to the second output 112. The second output 112 is configured to output pulse voltages to switch on and switch off the third transistor 131 and the fourth transistor 132. The third and fourth transistors 131, 132 are MOSFETs.
The first transformer 15 includes a first primary winding 151, a second primary winding 152, and a first secondary winding 154. The first primary winding 151 and the second primary winding 152 have a first common terminal 153. The first common terminal 153 is connected to the power source 10, and is further connected to ground via the filter circuit 14. The first primary winding 151 further includes a first terminal (not labeled). The second primary winding 152 further includes a second terminal (not labeled).
The second transformer 16 includes a third primary winding 161, a fourth primary winding 162, and a second secondary winding 164. The third primary winding 161 and the fourth primary winding 162 have a second common terminal 163. The second common terminal 163 is connected to the power source 10, and is further connected to ground via the filter circuit 14. The third primary winding 161 further includes a third terminal (not labeled). The fourth primary winding 162 further includes a fourth terminal (not labeled).
The first terminal of the first transformer 15 and the third terminal of the second transformer 16 are connected to ground via a first capacitor (not labeled), and are further connected to drain electrodes of the first transistor 121 and the second transistor 122. The second terminal of the first transformer 15 and the fourth terminal of the second transformer 16 are connected to ground via a second capacitor (not labeled), and are further connected to drain electrodes of the third transistor 131 and the fourth transistor 132.
When the switching power supply circuit 1 works, the first output 111 and the second output 112 provide pulse voltages to the first and second switching circuits 12, 13 respectively. When the pulse voltage provided by the first output 111 is a high voltage, the pulse voltage provided by the second output 112 is a low voltage. That is, when the first transistor 121 and the second transistor 122 of the first switching circuit 12 are switched on, the third transistor 131 and the fourth transistor 132 of the second switching circuit 13 are switched off, and vice versa. Because the two transistors 121 and 122 of the first switching circuit 12 are simultaneously switched on, the two transistors 121 and 122 may be damaged or even destroyed by heat generated thereat after the two transistors 121 and 122 have been working for a long time. The two transistors 131 and 132 of the second switching circuit 13 have the same problem.
Furthermore, when the first switching circuit 12 is switched on, and the second switching circuit 13 is switched off, the power source 10, the first primary winding 151 and the first switching circuit 12 form a closed loop, and the power source 10, the third primary winding 161 and the first switching circuit 12 also form a closed loop. The first primary winding 151 and the third primary winding 161 are connected to ground in parallel via the first switching circuit 12. Thus, the parallel first and second primary windings 151, 161 electromagnetically interfere with each other. Therefore, the outputs of the first and second secondary windings 154, 164 are liable to be non-uniform and unstable.
Similarly, when the second switching circuit 13 is switched on, and the first switching circuit 12 is switched off, the power source 10, the second primary winding 152 and the second switching circuit 13 form a closed loop, and the power source 10, the fourth primary winding 162 and the second switching circuit 13 also form a closed loop. The second primary winding 152 and the fourth primary winding 162 are connected to ground in parallel via the second switching circuit 13. Thus, the parallel second and fourth primary windings 151, 161 electromagnetically interfere with each other. Therefore, the outputs of the first and second secondary windings 154, 164 are liable to be non-uniform and unstable.
In summary, due to the above-described factors, the reliability and quality of the switching power supply circuit 1 may be unsatisfactory.
What is needed, therefore, is a switching power supply circuit that can overcome the above-described deficiencies.

Switching power supply circuit having independent loops


Object: A method for preparing a lithographic printing plate directly from digital image signals with the use of a presensitized lithographic printing plate comprising a support having thereon a photosensitive layer and a light-shielding layer which can be removed imagewise with laser light is provided, wherein the light-shielding layer, which can be industrially produced readily at a moderate price can be removed sufficiently during a process of development without the need of removing a masking layer at an unexposed portion and adverse effect on a photosensitive layer.. Constitution: A lithographic printing plate can be obtained by making use of a presensitized lithographic printing plate comprising a support having thereon a photosensitive layer containing o-quinonediazide compound, photo-degradable or photo-polymerizable resin and water-soluble resin and a light-shielding layer containing an infrared absorbing material and a material capable of absorbing the photosensitive wavelength of the photosensitive layer and by a process comprising ablating imagewise the light-shielding layer with laser light, overall-exposing with a ray active to the photosensitive layer to cause photochemical change of the photosensitive layer in which the light-shielding layer has been removed by ablation (e.g., making alkali-soluble) and dissolving out the photosensitive layer at a non-imaging area.

A lithographic printing plate has been prepared by a conventional method comprising a process of exposing a transparent original (e.g., a negative or positive film) in contact with a printing plate such as an aluminum plate or zinc plate each coated thereon with a photosensitive layer and developing the exposed plate. A positive-working photosensitive lithographic printing plate, for example, comprises a hydrophilic support having thereon a photosensitive ink-affinity layer capable of being solubilized upon imagewise-exposure to an actinic ray, such as ultraviolet radiation. When exposed and developed with an alkaline developer, an imaging area (nonexposed portion) remains and a non-imaging area (exposed portion) is removed to expose the hydrophilic surface of the support. As a result, the non-imaging area is capable of retaining water and thereby it repulses ink. On the other hand, the area (imaging area) which has not been removed through development, is hydrophobic so that it repulses water and becomes ink-receptible. The difference between the hydrophilic nonimaging area and the hydrophobic imaging area is employed in common lithographic printing. In a negative-working photosensitive lithographic printing plate, on the contrary, a photosensitive layer in an exposed portion (imaging area) is hardened and a photosensitive layer in an unexposed portion (non-imaging area) is removed by a developer so that it can be used as a lithographic printing plate.
With regard to editing the composition of a printing material which is a process prior to the preparing process of the printing plate, computer typesetting systems (CTS) made up of a combination of an automatic typesetting machine and computer, electronic composing and DTP (Desk Top Publishing) have become popular with the spread of word processors and personal computers. The computer generated data thus-edited is usually prepared as an original forme of a photographic film. If a printing plate material is available which enables making the printing plate directly from the output data of a CTS or aother electronic edting device, it is possible to shorten the printing process and also save intermediate materials. As a technique in response to the direct plate-making, it has been reported that there has been developed a plate-making material using an organic semiconductor or silver salt photographic light sensitive material. However, as it still has defects such as needing a new processing step and the plate-life is insufficient, it has not yet become an acceptable substitute for pre-sensitized plates.
Thermal recording, in which an image canbe obtained directly through thermal energy of an input signal without developing and fixing, is a dry-processing system without intermediate chemical steps, therefore, it is broadly employed in facsimile and printers. Recently, there has been employed a thermal transfer recording system, in which thermal transfer recording can be accomplished by exposing a thermal transfer recording material to a laser beam which converts the laser beam to heat in the recording material. In this laser thermal-transfer recording system, the laser beam, used as energy supply can be condensed to such an extent that highly-resolution recording becomes feasible, leading to use in the printing of art works.
With respect to the image forming technique using lasers, there have been proposed applications for direct thermographic plate-making. In Japanese Patent examined No. 51-6568 is disclosed a technique, in which vapor-deposition coating of metal such as aluminum or copper, or a coating comprised of carbon black dispersed in an organic solvent-soluble binder is usable as an ablatable light-shielding layer.
However, in the case when a metal depositin coating is used as the ablatable light-shielding coating, it is problematic in that two wet-processing steps are required comprising removing a masking layer in an exposed portion and developing the photosensitive layer. Further, since a large apparatus for vapor-deposition is required for forming a vapor-deposited coating over a photosensitive layer on an industrial scale, it is difficult to provide it at a competitive low price. In cases when a coating of an organic solvent-soluble binder such as nitrocellulose is used as the ablatable light-shielding layer, on the other hand, the ablatable light-shielding layer can be coated using a technique similar to that of the photosensitive layer. However, while coating the shielding layer, the surface of the photosensitive layer is dissolved by an organic solvent contained in a coating solution and mixed with a part of the shielding layer, producing such problems that sensitivity of the photosensitive layer is likely to be decreased or printing stains are caused due to the incomplete removal of the shielding layer during development.
In view of the foregoing, the present invention was developed. Therefore, an object of the present invention is to provide a method of preparing a lithographic printing plate directly from a digital image signal without the use of any intermediate material in the plate-making process. Another object of the invention is to provide a technique for overcoming the above-described problems, so that, in a method for preparing a lithographic printing plate directly from a digital image signal, it is to provide a technique whereby an ablatable light-shielding layer can be readily formed at a low cost on an industrial scale, a process of removing only masking layer in an unexposed portion is not required, there is no adverse effect of the light-shielding layer on the photosensitive layer and any unablated portion of the light-shielding layer can be sufficiently removed during the developing process.

Presensitized lithographic printing plate and method for preparing lithographic printing plate


Example techniques are described for generating graphics content by assigning a first region of the graphics content to a first tile, assigning a second region of the graphics content to a second tile, determining, at the first tile and at a first resolution, a first set of samples of the graphics content for each pixel of multiple pixels associated with the first region, determining, at the second tile and at a second resolution that is lower than the first resolution, a second set of samples of the graphics content for each pixel of multiple pixels associated with the second region, downsampling the first set of samples into a combined set of samples, preserving samples of the second set of samples to generate a third set of samples with preserved samples, storing the combined set of samples, and storing the third set of samples with preserved samples.

An electronic device may execute a program to present graphics content on a display. For example, an electronic device may execute a virtual reality (VR) program or an augmented reality (AR) program.
In some applications, graphics presented at a display may be rendered at different resolutions in the same frame. For example, in a VR headset, the center of the frame (e.g., the region(s) intended to be in the user's foveal vision) may be rendered at a higher resolution and the remainder of the frame (e.g., the region(s) intended to be in the user's peripheral vision) may be rendered at a lower resolution. As an additional example, an electronic device may track a gaze of a user (e.g., using a sensor) to identify a graphics portion that will be in the user's foveal vision. If the electronic device determines that eye movement of the user follows a particular object presented at a display, the electronic device may render the region(s) of the object at a higher resolution and render other regions in lower resolution(s).

Preserving sample data in foveated rendering of graphics content


Enhanced is a data processing efficiency of a whole semiconductor integrated circuit. A multiplexer is provided on a main parallel data bus for transferring data between an internal device such as a CPU, a DRAM or the like and an external device. When the CPU cannot accept data from the external device, it sends a busy signal to an interface circuit. The interface circuit receives the busy signal and controls the multiplexer in such a manner that the data to be transmitted to the CPU are transferred to the DRAM. Thus, a data transfer rate of the semiconductor integrated circuit is enhanced.

1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit comprising an interface circuit for receiving and sending data from and to an external device connected to an outside of the semiconductor integrated circuit and a bus for transmitting the data from the interface circuit into the semiconductor integrated circuit, a semiconductor integrated circuit comprising a phase-locked loop (hereinafter referred to as a PLL circuit) for synchronizing an internal clock with an external clock at a high speed, and a semiconductor integrated circuit comprising a DRAM which is small-sized and can easily be tested.
2. Description of the Background Art
In a semiconductor integrated circuit, generally, one chip has a plurality of functions. In other words, a plurality of internal devices having different functions are integrated into the same chip so that the semiconductor integrated circuit is formed. FIG. 15 is a block diagram showing a structure of a semiconductor integrated circuit which is a so-called one-chip microcomputer. The one-chip microcomputer is also formed with a plurality of internal devices provided on one chip 1. On the chip 1 is provided a CPU 2 which includes a control circuit for interpreting and executing instructions and serves to perform arithmetic operation. Data such as instructions sent to the CPU 2 are given from internal and external devices provided on the inside and outside of the semiconductor integrated circuit, respectively. The external device is connected to an input-output pin 3. An interface circuit 4 acting as one of the internal devices is connected to the input-output pin 3. The interface circuit 4 serves to electrically and functionally match data transfer between the external device connected to the input-output pin 3 and the internal device of the semiconductor integrated circuit. More specifically, the interface circuit 4 controls data transfer on a boundary between the inside and outside of the semiconductor integrated circuit.
In order for the CPU 2 to execute instructions, the semiconductor integrated circuit should fetch data necessary for the CPU 2. A processing speed of the CPU 2 is limited. Therefore, data generated in the semiconductor integrated circuit and data given from the outside should be held by any internal device until the CPU 2 starts a processing. In order to efficiently transmit data from the internal device such as the CPU 2 to the external device, it is also necessary to hold the data temporarily. In general, a storage is provided in the semiconductor integrated circuit in order to hold data to be processed by the CPU 2 or data waiting to be processed by the CPU 2 and output to the outside. Examples of the storage provided in the semiconductor integrated circuit include a SRAM 5 for sending and receiving data at a maximum speed together with the CPU 2, a DRAM 6 acting as a main memory for storing large scale data required by the CPU 2 and for holding and storing image data and the like when performing an image processing, and a NVRAM 7 for storing a basic program and data and for storing individual programs necessary for application.
The above-mentioned internal devices include the storage such as the SRAM 5 and the CPU 2 in addition to the interface circuit 4. In thecase where plural kinds of internal devices other than the interface circuit 4 are provided, the semiconductor integrated circuit can employ an indirect control method in which two or more channels such as a channel for transferring data between the external device and the CPU 2 and a channel for transferring data between the external device and the storage are provided and the interface circuit 4 is caused to switch channels. Furthermore, the semiconductor integrated circuit can also employ a direct control method for directly inputting data from the external device to the CPU 2 and transferring the same data from the CPU 2 to the storage. In the indirect control method, a selector channel and a multiplex channel are used. The selector channel serves to transfer data at a time without breaking a physical connecting relationship between the channel and the interface circuit 4 until data transfer is completed. The multiplex channel serves to transfer data while switching the physical connecting relationship between the channel and the interface circuit 4 on a unit.
Referring to a multi-channel, the interface circuit 4 switches the channels. Therefore, the interface circuit 4 requires information for switching the channels.
In a multi-channel switching method according to the prior art, channels are switched every byte of data or are switched for each block of data by causing the data to have information about channel selection.
Some kinds of data are transmitted. Data which can immediately be executed by the CPU 2 are directly sent to the CPU 2. Data which should be rewritten to a main memory or stored once are transmitted to a storage side such as the DRAM 6. As a matter of course, some data should be transmitted to the CPU 2 and the storage at the same time. Some of the data transmitted to the DRAM 6 are used for a cache. Such data are stored in the SRAM 5 simultaneously.
The data to be processed by the CPU 2 and output from the CPU 2 include data to be exactly output to an external device in addition to data to be transferred to the SRAM 5 and the DRAM 6. In such a case, the prior art can also employ a method for causing the DRAM 6 to store all the data once, connecting the interface circuit 4 to the DRAM 6 by a multiplexer (not shown) and sending only data to be output from the DRAM 6 to the external device. A PLL circuit 8 which is also used in the semiconductor integrated circuit shown in FIG. 15 will be described below. The PLL circuit 8 is provided to synchronize an internal clock used in the semiconductor integrated circuit with an external clock sent from the outside of the semiconductor integrated circuit. Also in a system chip, the PLL circuit is used. Referring to the system chip, a clock is always set to a power down mode, a refresh mode or the like. Also in such a case, it is important to realize high-speed synchronization in order to increase a speed of operation of the semiconductor integrated circuit performed in response to the internal clock. The internal clock should be synchronized with the external clock to perform communication between the external device and the semiconductor integrated circuit.
As shown in FIG. 17, the PLL circuit according to the prior art includes a frequency phase comparator 30 for detecting differences in frequencies and phases, a charge pump 31 for causing a current to flow into or out for a period of time corresponding to a result of the detection performed by the frequency phase comparator 30, a loop filter 32 for eliminating high-frequency components and noises from an output of the charge pump 31 to obtain a DC voltage, and a ring oscillator 33 for generating an internal clock having a frequency corresponding to an output of the loop filter 32. In the PLL circuit according to the prior art, one frequency phase comparator performs two processes, that is, a frequency leading-in process for causing frequencies to approximate to each other in order to synchronize the internal clock with the external clock, and a phase synchronizing process for completing phase synchronization.
The semiconductor integrated circuit according to the prior art has the above-mentioned structure. Therefore, input data always arrives at a predetermined destination, and data transfer is terminated while the data cannot be accepted at the destination until the data can be accepted at the same destination. For this reason, it takes a lot of time to transfer the data As shown in FIG. 15, for example, data having destination information is sent from the external device to the interface circuit 4 through the input-output pin 3. If the CPU 2 indicates the destination information of the data, the interface circuit 4 connects the CPU 2 and the channel to transmit the data through the connected channel. If the CPU 2 is in a busy state of instruction processing or the like and cannot receive the data, the channel cannot be disconnected before data transmission is completed. Consequently, the data cannot be transferred efficiently.
FIG. 16 is a block diagram showing a structure of an expand version of a semiconductor integrated circuit which is more suitable for processing mass data than in FIG. 15. In the semiconductor integrated circuit having the expand version shown in FIG. 16, a chip size is naturally increased and capacities of a SRAM 5 and a DRAM 6 are enlarged. Furthermore, a ROM 9 to store basic programs and the like is provided in addition to a NVRAM 7. In the semiconductor integrated circuit having the expand version which transmits mass data, a transfer efficiency should be prevented from being deteriorated. Such a problem is more serious than in an ordinary semiconductor integrated circuit.
In the case where data is transmitted from an internal device to an external device, all the data necessary for the external device should be transferred to the internal device in advance if a channel connected to the same external device is fixed. Consequently, a local link for connecting the internal devices becomes complicated.
In a semiconductor integrated circuit comprising the PLL circuit according to the prior art, one frequency phase comparator performs the two processes, that is, the frequency leading-in process for causing frequencies to approximate to each other in order to synchronize an internal clock with an external clock and the phase synchronizing process for completing phase synchronization. For this reason, if a frequency leading-in range is set wide, a setting time is increased.
In a semiconductor integrated circuit comprising the DRAM according to the prior art, the DRAM occupies great parts of the area and consumed power. If the DRAM is enlarged, the area and the consumed power of the semiconductor integrated circuit are increased.
A test for the DRAM often requires a technique for simultaneously writing the same data to a plurality of memory cells. In such a case, generally, it has been proposed that a word line is selected and then the data are sequentially written to the memory cells or that a register is provided on a side of a memory cell array and the data are written to the register and then are written to the memory cells in the memory cell array in a batch. In these cases, the DRAM has an overhead of a write cycle during batch write of data for performing the test in a test mode. Therefore, the semiconductor integrated circuit cannot operate at a high speed.
A first aspect of the present invention is directed to a semiconductor integrated circuit comprising an interface circuit, a multiplexer, first and second internal devices connected to the interface circuit through the multiplexer, respectively, and an internal bus for transmitting data between the first and second internal devices without using the multiplexer, wherein the first internal device outputs a processing signal to the interface circuit if the first internal circuit cannot accept data to be given to the first internal device, which data is input from an external device to the interface circuit, and the interface circuit controls the multiplexer on the basis of the processing signal and transfers, to the second internal device, the data to be given to the first internal device.
A second aspect of the present invention is directed to a semiconductor integrated circuit comprising an interface circuit, a multiplexer, first and second internal devices connected to the interface circuit through the multiplexer, respectively, and an internal bus for transmitting data between the first and second internal devices without using the multiplexer, wherein if there are data to be output from the first internal device to an external device through the interface circuit and data to be output from the second internal device to the external device through the interface circuit, the interface circuit controls the multiplexer according to information about data transfer given from the first internal device to the interface circuit and alternately outputs, to the external device, the data to be output from the first internal device and the data to be output from the second internal device.
A third aspect of the present invention is directed to a phase-locked loop circuit comprising first current output means for dividing a frequency of an external clock by that of an internal clock to calculate a quotient as an integer or an inverse number of the integer and for generating a first current proportional to the quotient, second current output means for generating a second current based on a phase difference between the external clock and the internal clock, and an oscillator for controlling a frequency on the basis of a sum of the first and second currents to generate the internal clock.
A fourth aspect of the present invention is directed to the phase-locked loop circuit according to the third aspect of the present invention, wherein the first current output means has a ring oscillator for shifting a phase of the internal clock synchronously with transition of the external clock, and a half cycle of an output of the ring oscillator is compared with that of the external clock to calculate the quotient.
A fifth aspect of the present invention is directed to the phase-locked loop circuit according to the fourth aspect of the present invention, wherein the second current output means has a bi-directional shift ring formed by connecting, like a ring, a plurality of bi-directional shift registers for performing shift in a direction corresponding to a sign of the phase difference at a shift speed according to the sum of the first and second currents, and the second current is increased or decreased on the basis of the direction of shift of the bi-directional shift ring.
A sixth aspect of the present invention is directed to a semiconductor integrated circuit comprising a word line, first and second bit lines which are paired with each other, at least one of which is selectively connected to a memory cell by the word line, third and fourth bit lines provided corresponding to the first and second bit lines respectively and paired with each other, a first transistor connected between the first and third bit lines in series and on-off controlled in response to a first signal sent to a control electrode, a second transistor connected between the second and fourth bit lines in series and on-off controlled in response to the first signal sent to a control electrode, first and second power lines capable of supplying a first voltage and a second voltage different from the first voltage, and of being cut off from a power supply to be brought into a floating state, a third power line for supplying a third voltage between the first and second voltages, switching means for connecting the third power line to the third and fourth bit lines in response to an equalize signal, a third transistor having a first current electrode connected to the first power line, a second current electrode connected to the third bit line, and a control electrode connected to the fourth bit line, a fourth transistor having a first current electrode connected to the first power line, a second current electrode connected to the fourth bit line, and a control electrode connected to the third bit line, a fifth transistor having a first current electrode connected to the second power line, a second current electrode connected to the third bit line, and a control electrode connected to the second bit line, and a sixth transistor having a first current electrode connected to the second power line, a second current electrode connected to the fourth bit line, and a control electrode connected to the first bit line.
A seventh aspect of the present invention is directed to a semiconductor integrated circuit comprising a first transistor having a first current electrode connected to storage nodes of memory cells, a second current electrode and a control electrode, the first transistor being conducted when the control electrode is at xe2x80x9cHighxe2x80x9d level and being non-conducted when the control electrode is at xe2x80x9cLowxe2x80x9d level, a word line connected to the control electrode of the first transistor, a first bit line connected to the second current electrode of the first transistor, a second bit line provided corresponding to the first bit line, a second transistor having a first current electrode connected to the first bit line, a second current electrode connected to the second bit line and a control electrode to which a first signal is sent, the second transistor being conducted when the first signal is at the xe2x80x9cHighxe2x80x9d level and being non-conducted when the first signal is at the xe2x80x9cLowxe2x80x9d level, a power line, a third transistor having a first current electrode connected to the power line, a second current electrode connected to the second bit line and a control electrode to which a second signal is sent, the third transistor being conducted when the second signal is at the xe2x80x9cHighxe2x80x9d level and being non-conducted when the second signal is at the xe2x80x9cLowxe2x80x9d level, and a negative voltage generating circuit capable of being selectively connected to the power line and supplying, to the power line, a negative voltage which can cause the power line to have a voltage lower than the xe2x80x9cLowxe2x80x9d level and make the first to third transistors conducted.
An eighth aspect of the present invention is directed to a semiconductor integrated circuit comprising a word line and a first bit line connected to each other through a memory cell, a second bit line provided corresponding to the first bit line, a first transistor having a first current electrode connected to the first bit line, a second current electrode connected to the second bit line, and a control electrode to which a first signal is sent, the first transistor being conducted when the first signal has a first potential and being non-conducted when the first signal has a second potential, a second transistor having a first current electrode connected to the second bit line, a second current electrode and a control electrode to which a second signal is sent, a power line connected to the second current electrode of the second transistor, and a potential generating circuit capable of being selectively connected to the power line and giving, to the power line, a potential different from an intermediate potential between the first and second potentials by a value greater than a threshold value of the second transistor when the second bit line is cut off from the first bit line by the first transistor so that the second bit line and the second signal have the intermediate potential.
According to the first aspect of the present invention, also in the case where the first internal device cannot accept data, the data can be transferred to the second internal device and then given from the second internal device to the first internal device by using the internal bus. Therefore, a data transfer efficiency between the external device and the semiconductor integrated circuit can be enhanced, and the data can be transmitted precisely.
According to the second aspect of the present invention, channels are switched by the multiplexer on the basis of information sent from the first internal device, and the data output from the first internal device and the data output from the second internal device are linked together to form a series of data. Consequently, data transfer between the first and second internal devices can be omitted. Thus, a data processing rate can be enhanced.
According to the third aspect of the present invention, a ratio of a frequency of the external dock to that of the internal clock can range from xc2xd to 2 by the first current. Therefore, a phase difference comparison for setting a second current can be performed quickly. Consequently, a speed at which the internal clock is lead into the external clock can be enhanced.
According to the fourth aspect of the present invention, it is easy to calculate the ratio of the frequency of the external clock to that of the internal clock as an integer or an inverse number of the integer.
According to the fifth aspect of the present invention, the bi-directional shift ring is used, a shift speed of which is controlled depending on a frequency. Therefore, high precision can be kept with a high frequency.
According to the sixth aspect of the present invention, the third and fourth transistors can be used as an amplifier of a sense amplifier and a latch. Therefore, a size of the semiconductor integrated circuit can be reduced correspondingly.
According to the seventh aspect of the present invention, batch writing is performed with a negative voltage. Consequently, an overhead of a write cycle is eliminated so that the semiconductor integrated circuit can operate at a higher speed.
According to the eighth aspect of the present invention, when the bit line has a precharge potential, data can be written to memory cells connected to an intended word line in a batch by causing the bit line to have a high or low potential.
In order to solve the above-mentioned problems, it is an object of the present invention to cause an interface circuit to have a function of changing a destination according to information given from an internal device to the interface circuit and to transfer data to other internal devices when an internal device to which the data should be transmitted cannot receive the data, thus reducing an average time in which the interface circuit is connected to a channel every unit quantity of the data.
It is another object of the present invention to synchronize an external clock with an internal clock even if a frequency is greatly changed and to reduce a time for the synchronization, thus increasing an operating speed of a semiconductor integrated circuit.
It is yet another object of the present invention to reduce a size of the semiconductor integrated circuit by simplifying a DRAM.
It is a further object of the present invention to reduce a test time for the DRAM and to increase the operating speed of the semiconductor integrated circuit by eliminating an overhead of a write cycle during batch write of test data to the DRAM.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

Semiconductor memory with application of predetermined power line potentials


An apparatus and method of processing images in a digital camera and improving the quality of images produced by camera processing software. In low-light digital camera photography, a dark frame image is subtracted from an original picture image to form a resulting image. The resulting image formed from the dark frame subtraction is evaluated for negative and invalid pixel values. Each negative and invalid pixel value is replaced using a pixel replacement algorithm with appropriate positive values.

With the advent of commercial digital cameras, amateur photographers are able to experiment with the digital camera in situations with low light, such as evening or night sky pictures. Some of the best features of the commercial digital camera are that feedback is immediate and that photographers are unconstrained by a finite amount of film.
In low-light conditions, such as dawn, dusk, and night, amateur photographers can capture the dramatic effects of the unique play of light. This requires significantly long exposures which create some issues for digital cameras.
In contrast to traditional film cameras, which use film to capture pictures, digital cameras use electronic sensors such as a charge-coupled device (or CCD) or complementary metal-oxide semiconductor (or CMOS) devices to record all relevant information for each picture. Unlike film, which records visible light exactly as it strikes the film, the image sensor of the digital camera records raw data values where the range [0 . . . 4095] corresponds to quantized values of the light levels that strike the image sensor. This is the difference between analog in the traditional film camera, and the digital camera. In this situation, longer exposures are used to take high-resolution pictures in low-light, such as at dusk or night, or simply dark images.
When using long exposures, typically between 0.33 to 4 seconds or greater, depending on the sensor and ambient temperature, the image sensor reveals its inaccuracy. The image sensor records the data of the image through electrons collected via photoelectric conversion in each pixel. Unfortunately, some electrons build up in the pixel sites via other methods such as through metal impurities in the crystal structure and defects in the crystal lattice. In long-exposure night-sky pictures, these generated electrons produce images that resemble stars, and can substantially distort the image. Because this phenomenon is most noticeable under no-light conditions, these generated electrons are called "dark current."
The warmth of the image sensor chip directly influences the of electrons generated; the amount of dark current in each pixel approximately doubles for every 8° C. increase. The amount of dark current is directly related to each pixel site, mostly by levels of defects. Hence, there is a fixed pattern across a sensor at a given temperature and integration time.
When two pictures of pure darkness, such as two pictures with the shutter closed or two pictures taken with the lens cap on, are compared with each other, the pictures will be nearly identical, pixel-by-pixel, aside from low-level variations from other noise sources. Most importantly, the two pictures will have the same amount of dark current at exactly the same pixel sites. When it is known that dark current in a digital camera, dependent on the ambient temperature, is fixed or static and always occurs in the same pixel locations, then the effects of dark current can be easily minimized.
However, the effects of dark current are more complicated than this and cannot be corrected so easily. In a single pixel measured over time, the amount of dark current generated over several frames would follow a Poisson distribution. This variation or uncertainty is called "dark current shot noise." While the fixed pattern noise is easy to subtract, the shot noise is random and may leave noise in the image after subtraction. As the image sensor warms, more electrons are generated and the image recorded by the image sensor becomes noisier and more inaccurate.
Scientific digital cameras and professional astrophotographers use several different techniques to reduce dark current and dark shot noise. One technique to reduce the effects of dark current is to use cryogenic cooling systems. At very cold temperatures, the effects of dark current are almost entirely eliminated. However, rather than employing expensive cryogenic cooling systems on the consumer-grade digital camera, an easier and less expensive solution is currently employed.
Currently, the professional photographer using a digital camera to experiment with low-light photography will take a long-exposure picture and will, at approximately the same time, in order to record dark current of the camera at that ambient temperature, take another picture of darkness, i.e., with the shutter closed or the lens cap on the camera. This second image is called a "dark frame" or a "dark field." The first image consists of a scene plus noise, including dark current, and the second image consists of dark current shot noise. Using a standard image editor, the two images can be subtracted, and the resultant image is the scene with no dark current noise. A disadvantage of this technique is that images received from a digital camera are usually not raw data but instead are usually subject to lossy processing, storage, and compression algorithms. Thus, when two lossy images are processed by the photographer, such as when a dark frame is subtracted from a picture image, then the accuracy of the resulting image is reduced from that of an image produced from the raw data.
Another disadvantage of this technique is that it does not reduce dark shot noise. When, at any given pixel, because of dark shot noise, the output level of the dark frame has a higher value than the output from the actual image, the resulting value from the subtraction is negative. Currently, when the photo editing software used by the professional photographer encounters negative values of data for a scene, the software automatically returns the negative values to zero. This will create inaccurate black spots or speckles called "clipping artifacts" in a picture.
In a picture of a night sky at dusk, for example, a dark blue background has white points of light that can be identified as stars. However, some of these white points of light are actually instances of dark current shot noise. When a dark frame is subtracted from the picture, the white points at the pixels with dark current shot noise are removed. If the random noise of the picture and the dark frame is low, then the dark frame subtraction will yield an accurate picture. However, when the random noise of the picture and the dark frame are combined to induce clipping artifacts, then the picture of the night sky will contain black points in place of the white points of light. While these black points will not be mistaken for stars, they are inaccuracies that detract from the final image.
A dark shot reduction technique of professional astrophotographers is to take multiple dark frame images, usually more than five, average the images pixel-by-pixel, and then subtract the averaged dark frame from the picture to create an image with reduced dark shot noise. While effective, this requires multiple dark frames, which must be taken by the photographer. In addition, that average dark frame is only valid for a given exposure time and temperature, and limits the number of picture images that can be taken by filling the memory of the digital camera. For amateur photographers, a simpler technique that does not limit the number of possible pictures to be taken is required.
There is a need, then, for a camera that will employ dark frame subtraction of only one dark frame before further processing, recognize when the data for an image is negative, and, rather than set that value to zero and thereby introduce spatial noise as a result of dark shot noise, will use value replacement to correct the pixel in place of creating black spots in an image. Typically, pixel replacement algorithms involve using information from neighboring pixels.

Incorporating pixel replacement for negative values arising in dark frame subtraction

Hewlett-Packard Development Company, L.P.


A joint estimation and compensation method of RF imperfections in a LIE (Long Term Evolution) uplink system comprises steps: establishing a joint signal model with RF imperfections; according to the joint signal model, undertaking estimation and compensation of CFO, DC offset, multipath channel, IQ imbalance and shaping filter imbalance of a received signal; and using a frequency equalizer to equalize said received signal and determine modulation data. For reducing computational complexity, the present invention further converts the received signal from a time domain to a frequency domain to undertake frequency domain compensation. The present invention can indeed solve the problems of IQ imbalance, filter imbalance, DC offset, multipath channel and CFO and effectively estimate and compensate RF imperfections in the LTE uplink system.

Field of the Invention
The present invention relates to an estimation and compensation technology for overcoming RF imperfections, particularly to a joint estimation and compensation method of RF imperfections, such as IQ imbalance, shaping filter imbalance, DC offset, multipath channel and carrier offset, in an uplink system.
Description of the Related Art
Succeeding to HSPA (High Speed Packet Access), LTE (Long Term Evolution) is a wireless access standard proposed by 3GPP (3rd Generation Partnership Project) to achieve further higher transmission efficiency. ITU (International Telecommunication Union) has formally defined LTE as 4G in 2010. LTE can enhance network transmission capacity and speed and support higher requirement of wireless communication.
According to the LTE specification proposed by 3GPP, an uplink system uses SC-FDMA (Single Carrier Frequency Division Multiple Access) signals, and a downlink system uses OFDMA (Orthogonal Frequency Division Multiple Access) signals. The present invention is primarily involved with the technology of LTE uplink systems. Users of mobile devices often care about power consumption and price. Higher PAPR (Peak to Average Power Ratio) will cause high price and high power consumption. Therefore, the LTE standard adopts the low power consumption SC-FDMA technology for uplink systems.
In an LTE uplink system, RF impairments are likely to occur in the DAC/RF device of the transmitter or receiver, such as IQ (In-phase/Quadrature-phase) imbalance, shaping filter imbalance, and DC offset. In other words, the baseband transmitter generates complex baseband signals; the baseband signals are divided into real parts (I signals) and image parts (Q signals); the I signals and Q signals are processed by DAC and respectively multiplied by a cosine wave and a sine wave, which have an identical amplitude and an identical frequency but have a phase difference of exactly 90 degrees; then, the signals are carried by a radio frequency and transmitted. On receiving the signals, the receiver down-converts and demodulates the signals. However, mismatches are likely to occur between the oscillators respectively generating sinusoidal waves in the transmitter and the receiver, including magnitude mismatches, phase mismatches, and oscillation frequency mismatches. The magnitude mismatch is called the magnitude imbalance. While the phases lack complete orthogonality, the phenomenon is called the phase imbalance. The two imbalances are called the IQ imbalance in combination. On the other hand, the transmitter and receiver must use a shaping filter to decrease the bandwidth of signals so as to meet the demand of the system and reduce ISI (Inter-Symbol Interference). The Nyquist filter and the SRRC (Square Root Raise Cosine) filter are often used to shape the signals of the transmitter and the receiver. While the transmitter and the receiver respectively adopt different shaping filters, shaping filter imbalance may take place there between. The cheaper direct-conversion architecture is often used to reduce the cost. In such a case, a portion of the power of the local oscillator leaks to RF signals and mixes with the transmitted signals, which will cause IQ DC offset in the transmitter.
Besides, multipath propagation usually occurs in a wireless communication system because of refraction, diffraction or scattering in an indoor or outdoor environment. In such a case, the receiver will receive two or more signals from different paths in different delay time, which will cause ISI and degrade the performance. Further, while up- or down-conversion is undertaken between the transmitter and the receiver, incomplete synchronization of the oscillators will cause frequency offset. Furthermore, Doppler shift occurring in high speed movement will lead to CFO (Carrier Frequency Offset). CFO will seriously affect the SC-FDMA- or OFDMA-based system, not only interfering with wireless communication but also leading to ICI (Inter-Carrier Interference).
The signal imbalances, such as IQ imbalance, shaping filter imbalance, DC offset, multipath channel, and CFO, will lead to RF mismatch in an LTE uplink system. At present, most of the related technologies undertake estimation and compensation in the frequency domain. However, they do not apply to LTE uplink systems. So far, neither a joint estimation nor a joint compensation method has been published, not to mention a time-domain joint estimation and compensation method considering various RF attenuations.
Accordingly, the present invention proposes a joint estimation and compensation method of RF imperfection in an uplink system to overcome all the imperfections in LTE uplink systems.

Joint estimation and compensation method of RF imperfections in LTE uplink system


A modular computer chassis for both rack mounting and free standing use comprising a housing adapted for receipt of a plurality of computer modules in a secured array. The modules are selectively accessible only through a cover panel door which may be locked to secure the integrity of the array. The modules are mounted in the chassis on individual slides which afford alignment and stability in the assembly thereof. Additionally, the modularity affords interchangeability with rack-mounted systems for maximizing the efficiency of operation and the effectiveness of installation and service. Problems within the system can thus be addressed by removing and replacing individual modules in a configuration which affords reliability and easy access.

1. Technical Field of the Invention
The present invention relates to a computer chassis for free standing use or rack mounting and, more particularly, but not by way of limitation, to a computer chassis constructed with a modular mounting configuration for effecting ease and security in the installation or removal of components therein.
2. Description of Related Art
Early computer designs generally included a chassis with a plurality of individual components and assemblies mounted therein and connected to one another by means of wires, cables, brackets, nuts, bolts and the like. A major computer design advance occurred with the advent of printed circuit boards, integrated circuits and modular component assemblies. The printed circuit boards were, for example, formed of lightweight material and housed a myriad of components which were electrically interconnected with the component assemblies through wiring harnesses. The wiring harnesses and hard wire connections were subsequently replaced by technologically advanced connectors used for integrally coupling the individual components to each other and to other circuitry in the computer. Other advances, such as specially designed clips for minimizing electromagnetic interference (EMI), further enhanced the computers effectiveness and compatibility with other electronic systems.
In the design of electronic equipment, the use of connectors, modular components, and specialized hardware has permitted key components and printed circuit boards to be efficiently added and removed. Such ease in the addition and deletion of computer components and printed circuit boards has facilitated assembly repair, upgrade, and/or changes in functionality. Because the computers of today's complex business world may contain volumes of confidential information, one design aspect has always been security of the data stored in the computer system. Various chassis designs address such issues. For example, U.S. Pat. Nos. 5,154,456 and 5,162,976 (both assigned to the assignee of the present invention), teach security and locking systems for a computer chassis. Security of the disk drives and other computer components has thus been recognized as a valuable design aspect.
Computer reliability and serviceability are also valuable design aspects. Originally, a rule of practice in the maintenance of electrical circuitry, such as computer hardware, was that of always turning the power to the computer off before components or printed circuit boards were added or removed from the computer chassis or support frame. Recent innovations have addressed the desirability to insert and remove modular components and printed cards from electrical equipment, such as computer hardware, when the computer is electrically connected and operational, i.e. "hot." This is now possible for hot pluggable hard drives, and in these cases, the power may be disconnected from only the connector of the drive or modular component to be inserted and removed while allowing the adjacent components to remain "hot."
Removable computer components today include disc drives, drive cages, fans, power supplies, system I/O modules, processor boards, and other subassemblies. As referenced above, the removability of computer components allows for better overall serviceability of the computer system, which is a distinct advantage to both the user and the maintenance technician. A defective power supply in the main or central computer generally requires prompt replacement in order to limit downtime. It is for this reason that modular components and connectors facilitate prompt replacement and are thus popular in many computer designs. For example, U.S. Pat. Nos. 5,332,306 (Jul. 26, 1994) and 5,277,615 (Jan. 11, 1994), both assigned to the assignee of the present invention, teach disk drive mounting systems facilitating these removability features.
The modularity of computer systems is thus recognized as an important design consideration. As referenced above, modules can be removed and examined for operability or other purposes much easier than permanently mounted fixtures within a computer chassis. Because computers provide an integral part of most business operations, it is of utmost importance to maintain the reliability and integrity of the computer system. When the various elements of a computer can be easily removed in a modular form, they can also be replaced to maintain the operational status of the computer. They may also be replaced, however, to remove stored data. It is for this reason that information stored upon circuit boards or disk drives contained within the computer may need to be physically secured in such a way so as not to be readily available for access. Additionally, it is often important to know if any portion of a computer has been accessed or "tampered with" such as in those situations where sensitive data is maintained within some portion of the computer hardware.
The present invention provides such a security system by providing a modular computer chassis and associated specialized hardware specifically adapted for maximum efficiency and modularity with selectively restricted access thereto. Specialized EMI clips, printed circuit board card guides and locking systems are also provided to enhance these features. In this way, security and reliability are provided in a modular array capable of free standing or rack mount assembly.

Modular computer chassis interchangeable between stand alone and rack mounted states


The present invention provides a thermoplastic polyurethane composition which comprises an ethylene-vinyl alcohol copolymer and/or a polyamide, and a thermoplastic polyurethane, in which the retention of melt tension thereof, when kept in a molten state at 220° C. for 1 hour, determined by the following equation (1), is not less than 10%.Retention of melt tension (%)=[Melt tension after being kept in a molten state/Melt tension before being kept in a molten state]×100  (1)

1. Field of the Invention
The present invention relates to a thermoplastic polyurethane composition comprising a thermoplastic polyurethane and an ethylene-vinyl alcohol copolymer and/or a polyamide.
2. Description of the Related Art
A thermoplastic polyurethane has been widely used because it is excellent in various properties such as mechanical strength, flexibility, elastic recovery from strain and abrasion resistance. A film, a sheet, a belt, a hose, a tube and other various articles may be produced with a thermoplastic polyurethane by extrusion molding or injection molding.
An article, made of a thermoplastic polyurethane and having good gas barrier property, has been required. For example, multi-layered structures having a layer of a thermoplastic polyurethane and a layer of an ethylene-vinyl alcohol copolymer or a polyamide, each of which is known as a polymer having excellent gas barrier property, are proposed [see Japanese Patent Application Laid-open Nos. 22163/1983 (JPA 58-022163), 258341/1990 (JPA 2-258341), 5143/1991 (JPA 3-005143) and 110154/1998 (JPA 10-110154)].
A process for producing an article made of a thermoplastic polyurethane and an ethylene-vinyl alcohol copolymer or a polyamide inevitably causes a scrap such as(i) a lug of a film which is involved by co-extrusion process, (ii) trimmings which is involved by co-extrusion blow molding process and (iii) defective moldings. It is desirable to reuse such a scrap from the viewpoint of production cost and resource saving.
In addition, it is also desirable to recycle an article made of a thermoplastic polyurethane and an ethylene-vinyl alcohol copolymer or a polyamide.
Various attempts have been applied for the recycle of an article made of an ethylene-vinyl alcohol copolymer. For example, Japanese Patent Application Laid-open No. 195635/1995 (JPA 7-195635) discloses a method for the recycle of a multi-layered structure having a layer of an ethylene-vinyl alcohol copolymer and a layer of a polyolefin. Also, U.S. Pat. No. 6,294,602 and Japanese Patent Application Laid-open No. 248073/2000 (JPA 2000-248073) disclose a method for the recycle of an article made of a polymer composition comprising an ethylene-vinyl alcohol copolymer, a polyamide and a copolymer of an olefin and an unsaturated carboxylic acid. However, these documents are silent with a method for the recycle of an article made of an ethylene-vinyl alcohol copolymer and a thermoplastic polyurethane.
A thermoplastic polyurethane composition comprising a thermoplastic polyurethane and an ethylene-vinyl alcohol copolymer and/or a polyamide may be formulated by melting [i] an article made of a thermoplastic polyurethane and an ethylene-vinyl alcohol copolymer and/or a polyamide or [ii] a scrap involved by a process for producing an article made of a thermoplastic polyurethane and an ethylene-vinyl alcohol copolymer and/or a polyamide. However, in most cases, a combined use of a thermoplastic polyurethane and an ethylene-vinyl alcohol copolymer and/or a polyamide tends to cause gelation upon melt molding.
Japanese Patent Application Laid-open Nos. 206634/1990 (JPA 2-206634) and 255288/1991 (JPA 3-255288) disclose a uniform thermoplastic polyurethane composition, which can be formulated without gelation, comprising a thermoplastic polyurethane and an ethylene-vinyl alcohol copolymer having specific ethylene content. Japanese Patent Application Laid-open No. 324162/1995 (JPA 7-324162) also discloses a polymer composition comprising a thermoplastic polyurethane dispersed in a matrix of a polyamide. The present inventors have found that, even with such a uniform composition, gelation may proceed at a molten state to cause a reduction of melt tension of the composition, which leads to lesser processability upon extrusion molding or injection molding.

Thermoplastic polyurethane composition and process for producing the same

Abstract: The thermoplastic polyurethane composition of the present invention is excellent in production stability of a molded article, and can provide a molded article excellent in appearance because the progress of gelation thereof is suppressed even in a molten state.


A refractive index detector for use in fluid phase separation techniques such as liquid chromatography and capillary electrophoresis uses a laser beam incident on a capillary tube held in a fixture. The laser beam is refracted and reflected (backscattered) from the capillary tube surface and its contents back to a photodetector located adjacent to the laser source. Tilting of the capillary tube relative to the laser beam axis produces a diffraction pattern on the photodetector, allowing detection of refractive index. Other embodiments use a split incident laser beam part of which is incident on a reference photodetector, or use a split beam which is incident on two capillary tubes juxtaposed to one another. In this case a photodetector is provided for the portion of the beam reflected from each capillary tube. The system may also be used for detecting temperature and pressure of the fluid inside the capillary tubes.

1. Field of the Invention
This invention relates to detecting the refractive index of a fluid sample. More specifically, the invention relates to a method and device using a laser beam reflected from a capillary tube holding a fluid to determine the refractive index of the fluid.
2. Description of the Prior Art
It is known in the art (see FIG. 1) to measure refractive index using a beam 4 emitted from laser 6 which is focused by lens 8 on a micrometer diameter capillary tube 10 as described in "Simple Nanoliter Refractive Index Detector", Darryl J. Bornhop, et al., 58 Analytical Chemistry pg. 504 (1986), and incorporated by reference herein. Incident laser beam 4 is diffracted by capillary tube 10. Refractive index measurements are made by a photodetector (D1) 12 measuring the intensity of laser beam 13 transmitted through capillary tube 10. A reference beam 14 is provided from laser beam 4 by beam splitter 15, and reference beam 14 is detected by reference photodetector (D2) 16 to compensate for intensity drift by the laser 6 by an operational amplifier 17 which subtracts common-mode laser noise from the refracted light. A digital volt meter (DVM) 18 records the signal. Such devices are used to test small volume samples in the nanoliter range.
A refractive index detector such as this is one of the few universal optical detectors available for fluid samples. However, these detectors tend to be either very expensive to manufacture or difficult to adjust. Typically in these devices the laser beam is focused on the tube and passes through the tube to a detector which is on the far side of the tube from the laser source. This arrangement disadvantageously requires a lens to focus the laser beam off the center axis of the capillary tube and also requires a second reference beam from the same or a second laser. Thus this method requires careful optical alignment and is thus somewhat complex and relatively difficult to assemble. Also, it is difficult to use the prior art methods with a flow cell that has a thermal compensation feature such as an optical reference arm. Additionally the single pathlength limits the ultimate sensitivity of the device.

Laser-based refractive index detector using backscatter


A vehicle control unit kit is a plug-n-play OEM harness configured to interface with a given vehicle's OEM window switch connector. The device is configured to enable the given vehicle's power window master switch driver to operate all vehicle windows. The vehicle control unit additionally incorporates smart avoid anti-pinching programming.

A standard or optional accessory on many late model vehicles equipped with power windows is the automatic up/down or express feature. This feature allows the vehicle occupant to simply touch the window switch control one time to command the power window to travel all the way down or all the way up depending on the current position of the window and which switch (up or down) is pressed. Such an accessory is very useful and frees the user's hands for other needs.
However, such functionality is not available on all makes and models of vehicles and may not be available on all windows as it may be made available on only the driver's window. Other features such as control by a remote-control fob and/or object avoidance to prevent crushing of arms, fingers or other inadvertent objects in the windows path are often omitted or not available on certain model vehicles. Accordingly, there exists a need for a means by which an advanced vehicle power window functionality can be provided to all power windows via an aftermarket device. The development of the vehicle window control unit fulfills this need.