A reactor design and configuration and a process for the catalytic dehydration of propanol to propylene where the reactor train is comprised of a multi-stage single reactor vessel or multiple reactor vessels wherein each stage and/or vessel has different length, internal diameter, and volume than the other stages and/or vessels and in addition the stages and/or reactor vessels are connected in series or in parallel arrangement, preferably used with an improved means of introducing the propanol feedstock and a heat carrying inert gas to the improved reactor train.

1. Field of the Invention
This invention relates to a process for the selective catalytic dehydration of n-propanol or iso-propanol (collectively referred to as propanol) to propylene using an improved technology of reactor design and configuration, wherein the reactor train is comprised of a multi-stage single reactor vessel or multiple reactor vessels wherein each stage and/or vessel has different length, internal diameter, and volume than the other stages and/or vessels and in addition the stages and/or reactor vessels are connected in series or in parallel arrangement. Furthermore, this invention discloses an improved means of introducing the propanol feedstock and a heat carrying inert gas to the improved reactor train.
2. Related Information
Propylene is the second most important raw material in the petrochemicals industry after ethylene. It is the primary feedstock in such diverse materials as polypropylene, propylene oxide, propylene glycol, acrylonitrile, epychlorohydrin, etc. This petrochemical feedstock is primarily produced from petroleum resources by the steam cracking of petroleum-derived feedstocks such as heavy naphtha, ethane/propane, or gas condensates. The economics of these processes are greatly influenced by the supply, availability, and price of crude oil and natural gas. In addition, the cracking processes produce a large number of other valuable products and co-products such as ethylene, butylenes, and other hydrocarbons. which have to be recovered and may not be ignored and disposed of as waste. The economics of the propylene production by the steam cracking process thus requires that these co-products be separated and recovered at very high purity suitable for downstream chemicals and polymer applications. This would require very complex processing scheme, high capital investment, and large energy consumption to separate, purify, and provide storage for all the products so that the process can be economically justified. In addition, the success of the petroleum-derived propylene requires that all the by-products be marketed to their respective end users. If a user of propylene were interested in only producing propylene and no other products, the cracking route is not a viable and profitable option. Furthermore, the conventional steam cracking produces large quantities of CO2 (carbon) which is a main component of the greenhouse gas emission.
The dehydration of propanol is a simple and attractive potential route to propylene. Presently, there is no known commercial process for the catalytic dehydration of propanol. Recently, as the biofuels have attracted more attention globally, as prices of crude oil have increased and have become more unpredictable, and as petroleum supply sources have become more unstable and problematic, the propanol dehydration process is gaining interest as an alternative source for the production of chemical- or polymer-grade propylene. In addition, with the threat to the environment and limited resources in some parts of the world, the propanol dehydration process is being increasingly competitive with the traditional steam cracking process. Furthermore, the sources of raw materials for propanol supply are expanding with a resultant decrease in the cost of propanol manufacture thus making it an attractive option for propylene production.
The propanol dehydration reaction basically is characterized by the removal of a water molecule from propanol and as such is highly endothermic. A significant amount of heat (energy) is thus required to initiate and sustain the reactions to completion. Therefore, the choice of the reactor, its design, and configuration are critical aspects of managing the thermal events within the reactor and controlling the operating temperatures within the catalyst bed for an economical process.
Additionally, the economic production of propylene by this process largely depends on the high conversion of propanol feedstock to avoid recovery and recycle of any unreacted propanol. It also requires high selectivity and yield of the propylene product in order to avoid expensive separation and purification of the final product which is needed for chemicals and polymer applications. Furthermore, it is critical to limit the formation of by-products which will complicate the recovery and purification of the product and its downstream applications into high value added chemicals and polymers.
Unlike the ethanol dehydration process to ethylene which has been the subject of many patents and developments and which has been commercially practiced for many years, there have been very few patents and/or technical articles on the dehydration process of propanol to propylene. Recently, however, there has been some activity with several US patent applications having been filed. US patent application 2009/0259086 discloses an integrated process for the production of mono-olefin(s) from a feedstock comprising of at least one aliphatic paraffinic hydrocarbon. In particular, the disclosure claims a process wherein an alcohol stream containing a mixture of ethanol and propanol is dehydrated within a single reactor to the respective same carbon olefins and other by-products. The olefins thus produced are separated from the other by-products and a mixture of ethylene and propylene is produced as the primary product of the process. The disclosure only provides a general layout of a process for co-dehydrating a mixture of ethanol and propanol with no reference to the choice of the preferred reactor for the optimal temperature control required for the dehydration reactions. Neither does the reference disclose the preferred operating reactions required for an economical process which requires high conversion of the alcohols and high selectivity of the olefins products. The reference claims an operating conversion of ethanol and propanol of preferably between only 20 to 60% per pass, which would require a complex process scheme to recover the valuable alcohols and recycle to the dehydration reaction. Finally, there is not provided in this application any experimental results or evidence to support the claims.
US Patent Application 2009/0270668 discloses an invention for a process to co-produce ethylene and propylene from a mixture of ethanol and propanol feedstock. According to this application, the said feedstock is first processed in a purification column to separate the two alcohols. Following this separation, a parallel path is provided wherein each alcohol is separately dehydrated to its respective olefin. The olefins thus produced are then processed to separate them from the by-products and purified to produce the final ethylene and propylene products. The claimed process is very similar to the above US Patent Application 2009/0259086 with the exception that two dehydration paths are provided in this invention instead of a single integrated dehydration reactor in 2009/0259086 disclosure. Similar to the 2009/0259086, the present invention also does not provide any reference as to the choice of reactors preferred for conducting the endothermic dehydration reactions and the management of the temperatures within the individual reactor vessels. Neither does it provide the preferred operation conditions within the reactor vessels.
US Patent Application 2009/0281362, discloses a process where, unlike the above applications, propanol is the only alcohol feedstock and propylene is the only olefin product. According to this invention, pure propanol is dehydrated in the reactor vessel to propylene and other by-products. The product propylene is then separated from by-products and purified to the final product. There is provided no reference to the preferred choice of the reactor. This invention also does not specify the choice of the reactor and its configuration for optimum performance of the overall process.
In view of the above disclosures, the successful development of technology for propanol dehydration to propylene requires that a reactor design be developed consistent with the thermodynamics and kinetics of the dehydration reactions. Foremost, the reactions in this process are highly endothermic which require input of considerable amount of energy to derive the process. Therefore, supply of heat, the management of the thermal processes, and the reactor temperature control constitute important considerations for optimum performance. One aspect of the present invention is a reactor disclosure to address these issues.
With regard to alcohol dehydration reactors which have been proposed and developed in the past, several patents stand out. U.S. Pat. No. 4,134,926 discloses a fluidized bed reactor concept for the dehydration of ethanol to ethylene wherein a portion of the dehydration catalyst is continuously withdrawn from the reactor chamber and regenerated with air in a second fluid-bed regenerator. The hot regenerated catalyst is then mixed with fresh make-up catalyst and recycled back to the primary reactor to provide the endodermic heat of reaction. This reactor concept has not found commercial application due to the complexity of the process, the handling and recycle of large quantities of solid catalyst, and continuous replacement of the lost catalyst because of attrition.
U.S. Pat. No. 4,232,179 describes a reactor train invention in which multiple, adiabatic reactor vessels are connected in series and/or parallel arrangement for dehydration of ethanol to ethylene. This patent further teaches the use of a sensible heat carrying fluid such as steam mixed with the alcohol feedstock prior to feeding to individual reactors. Each reactor is packed with a solid catalyst. The energy required for the reactions is supplied by a fired heater wherein both alcohol feedstock and steam are heated to very high temperatures needed for the reactions to proceed to completion in each reactor stage. This feature, being similar to British patent 516,360, can also result in lower selectivity and yield of the primary product and the formation of problematic by-products. In addition, no distinction is made in this disclosure as to the relative sizes of each reactor and the catalyst bed within that reactor with respect to other reactors and/or catalyst beds which make up the reactor train.
U.S. Pat. No. 4,396,789 teaches an invention which is basically similar to U.S. Pat. No. 4,232,179 with the exception that the reactor train is designed to operate at a design pressure of between 20 and 40 atmospheres. The patent claims that such high pressure operation will simplify the purification of the crude olefin product during the subsequent cryogenic distillation to produce high quality olefin for downstream chemicals/polymer applications.
In all the above processes, the dehydration catalyst is subjected to carbonization and rapid fouling as a result of direct exposure of the alcohol to the high coil surface temperatures in the fired heater which serves as feed pre-heater. This practice would therefore require frequent regeneration of the catalyst bed thus requiring downtime, loss of production, and shortened catalyst life.
The specific goal of the present invention is to provide a novel, adiabatic reactor configuration and process to achieve the desired goals of the invention. Other objects and benefits of the present invention will become apparent from the following disclosure. Furthermore, it is an object of the present invention to utilize available streams already found within a production facility or derived from the operation of the process carried out in the reactor. In this regard, each of the stages within the reactor vessel is independently sized and the quantity of catalyst therein determined to take advantage of a stream from some other reactor or source within the facility or from other stages within the reactor to obtain the highest yield and selectivity from these disparate sources. It is a particular object of the present invention to design each stage of the reactor considering various sources which can used in the reaction at hand.

Process and reactor for dehydration of propanol to propylene


A head detecting apparatus, including a foreground extraction section for extracting a foreground region in which a person is captured from an input image; a first main axis computing section which includes a first moment computing section for computing a moment around a center of gravity of the foreground region and calculating a main axis of the foreground region based on the moment around the center of gravity of the foreground region; a head computing section for computing a head region included in the foreground region as a part thereof based on the main axis of the foreground region and a shape of the foreground region; and an ellipse determining section for determining an ellipse to be applied to a person's head based on a shape of the head region.

The present invention relates to a head detecting apparatus, a head detecting method, and a head detecting program. In particular, the present invention relates to a head detecting apparatus, a head detecting method, and a head detecting program which applies an ellipse to the head of person in an input image. With evolution of an image capturing apparatus and development of an image processing technique in recent years, it is desirable to automatically analyze and utilize moving images. There is a possibility that in techniques analyzing moving images, estimation of motion of an image-captured person is useful in many application fields such as a monitoring camera, a robot vision, or the like where human beings are involved. When estimating motion of a person, the movement of a head of a person including a face is extremely important information. Techniques for estimating motion of the head of a person by recognizing the head through analysis of a moving image are disclosed in some prior work as further detailed below.
A method for recognizing the head of moving object considered to be a person in a moving image by detecting a waist portion (i.e., concave portion) of the outline of the head has been proposed (for example, Y. Tian, et al., "Absolute Head Pose Estimation from Overhead Wide-Angle Cameras," Proceedings of the IEEE International Workshop on Analysis and Modeling of Faces and Gestures (AMFG '03), pp. 92-99, 2003). Also, methods for recognizing the head by matching a shape, and the like, have been proposed (for example, refer to Patent Document Japanese Unexamined Patent Publication (Kokai) No. 2002-157596 which discloses a method for performing real-time tracking of a face based on color distributions included in detected face patterns, and applying moving changes for face detection. Patent Document 2, Japanese Unexamined Patent Publication (Kokai) No. 2002-203239, discloses an algorithm for identifying a potential face based on detected face characteristics (eye, eyebrow, nose, and mouth). Patent Document 3, Japanese Unexamined Patent Publication No. 2002-203239 discloses face detection equipment including face similarity calculation means for computing similarity of face-likeness by comparison with face information stored in a storage section.
Also, Patent Document 4, Japanese Unexamined Patent Publication (Kokai) No. 2004-178229, discloses a man existence location detector which includes a segment-like vote section, which is a vote template modeling the shape of person's head and used to widen the detection range. Patent Document 5, Japanese Unexamined Patent Publication (Kokai) No. 2004-206656, discloses a detection device for stochastically calculating human body likeness by using the probability of a body part candidate's part-likeness, and the interrelation between parts. Patent Document 6, Japanese Unexamined Patent Publication (Kokai) No. 2004-53324, discloses a collision safety controller for automobiles which extracts a passenger's head based on a profile configuration of the passenger's head.
Patent Document 7, 8, 9, 10, 11, 12, 13, and 14, Japanese Unexamined Patent Publication (Kokai) No. H10-274516, Japanese Unexamined Patent Publication (Kokai) No. 2001-216518, Japanese Unexamined Patent Publication (Kokai) No. 2001-243466, Japanese Unexamined Patent Publication (Kokai) No. 2003-141541, Japanese Unexamined Patent Publication (Kokai) No. 2004-78778, Japanese Unexamined Patent Publication (Kokai) No. 2005-18654, Japanese Unexamined Patent Publication (Kokai) No. 2004-272933, Japanese Unexamined Patent Publication (Kokai) No. 2001-291108, respectively, disclose techniques for estimating motion of a head under the condition that a head or a face can be extracted. Patent Document 7 discloses a device for detecting the sense of face by detecting the center position of a face region akin to an ellipse, created by extracting description regions such as an eye, a nose, a mouth and the like.
Patent Documents 8 and 9 disclose devices which perform matching to templates of face images with different directions. Patent Document 10 discloses a device simultaneously displaying information regarding a face image at the time of registration and information regarding a face image being input at the time of recognition. Patent Document 11 discloses a driver monitoring device including determination means for determining the sense of the face based on the differences between images collected serially.
Patent Document 12 discloses a device for detecting a looking-aside condition by detecting optical flow. Patent Document 13 discloses a device for determining which sense of face matches most closely to the face in a monitor image, by preparing face images, such as a transverse-plane face, a leftward face, and a rightward face and by using canonical discriminant analysis. Patent Document 14 discloses an image processing device having database creation means storing average face images which are made from three-dimensional average face models and which correspond to various angles.
The method described in Non-patent Document 1 has a problem such that recognition of the head is difficult when accuracy of the extracted moving object is reduced because of the characteristics of the image or the background, since a waisted portion of the outline was not detected. For example, if the background includes colorful and complicated texture, since the outline of the moving object is not smooth but has lots of dents, it is difficult to determine the correct waisted portion of the outline by using this method. Also, for example, in the case in which both hands are put on the head, or in the case in which a person is wearing high collared clothes, dents appear in places other than the intended place, it is difficult to determine the correct waisted portion of the outline by using this method.
In the methods disclosed in Patent Document 1, 2, and 3, it takes a long time to match since there are many parameters. Also, in these methods, it is not possible to obtain stable matching results when the outline is not smooth. Also, in the methods disclosed in Patent Document 4, 5, and 6, it is difficult to recognize the head of a person when the outline is not smooth.
The devices disclosed in Patent Document 7, 8, 9, 10, and 11 are not capable of detecting motion of a head, in the case in which it is difficult to recognize each part of a face due to low resolution of the image, in the case in which a person's face is turned away from the image pick-up side of a camera by more than 90 degree, and the like.
With regard to the device for detecting optical flow described in Patent Document 12, it is possible to compute this when the moving image is obtained under good conditions, such as using an in-vehicle camera, however, it is not possible to compute this when the face is small, when characteristic parts such as eyes, a nose, and the like, cannot be extracted as the person is facing obliquely away from the image pick-up side, or when the background is colorful and its texture is complex, and the like.
In the devices disclosed in Patent Document 13 and 14, a problem about what angle of the interval the data should have arises when the data is prepared. When the interval of the angle is small, matching takes a long time, and when the angle of the interval is large, the accuracy of detection deteriorates. Also, incorrect detection occurs due to the difference between a prepared face image and an input face image. Furthermore, the matching accuracy also deteriorates when a person is wearing glasses, a hat, and the like. Furthermore, the matching accuracy with the prepared date deteriorates when the extracted moving object is rough due to the characteristics of the image and the background.
As described above, in the conventional techniques, accuracy of recognition of a head and estimation of motion of a head are not good if the contour is not smooth due to the deteriorated accuracy of extracting a person's image. For example, in the conventional techniques, under the condition in which a monitoring camera is installed in the store of retailer, the outline of a person can not be extracted since the background (shelves for goods) is colorful and its texture is complex.
It is therefore an object of the present invention to provide a head detecting device, a head detecting method, and a head detecting program which can solve the above-mentioned problems. The object is achieved by the combinations of characteristics of independent claims in the scope of claims. Dependent claims also regulate advantageous specific examples of the present invention.
The present invention provides a head detecting apparatus including a foreground extraction section for extracting a foreground region in which a person is captured, from an input image, a first main axis computing section for computing a main axis of the foreground region, a head computing section for computing a head region included in the foreground region as a part thereof based on the main axis of the foreground region and a shape of the foreground region, and an ellipse determining section for determining an ellipse to be applied to a person's head in the input image based on a shape of the head region; a head detecting method using the head detecting apparatus, and a head detecting program to cause a computer to function as the head detecting apparatus.
The concept of the present invention is not the enumeration of all the necessary characteristics of the present invention, but subcombinations of the characteristics thereof may be also accepted as the invention.
According to the present invention, an ellipse can be appropriately applied to a person's head regardless of the accuracy of an extracted foreground region.

Head detecting apparatus, head detecting method, and head detecting program

International Business Machines Corporation


A cooking apparatus includes a cooking surface and a wall depending from the cooking surface. The wall has an interior surface and an exterior surface opposite the interior surface. A handle is adjacent the exterior surface. The handle has a first surface adjacent the wall and a second surface opposite the first surface. A rivet is disposed through the interior surface, the exterior surface, and the first surface of the handle. The second surface of the handle is unpierced by the rivet. The rivet is bonded with a mating material.

1. Field of the Invention
This disclosure relates generally to cookware and, more particularly, to a method and apparatus for attaching a handle using self piercing rivets.
2. Description of the Related Art
Cooking apparatus or cookware typically includes a bottom wall and a depending sidewall that is attached to a handle. The bottom wall and sidewall are adapted to receive the food to be cooked. Heat can be conducted through the bottom wall and sidewall from a heat source, such as a stove or oven, to cook the food therein. The handle allows the user to move the cookware. The material of the handle may also allow the user to move the cookware when the cookware is in communication with the heat source.
The handle and sidewall made of dissimilar metals has presented challenges in connecting the handle to the sidewall in an easy to clean, inexpensive, secure manner. Methods of connecting the handle and sidewall typically require holes to be formed in a handle and sidewall prior to manually inserting a mechanical fastener that result in portions that protrude through the sidewall into the cooking area, which can form areas that trap food particles and/or are difficult to clean. Other methods of securing the handle to the sidewall such as welding typically require holes to be formed at least in a handle and can require an undesirably high amount of labor and cost and disassembly of the connection between the handle and sidewall to ensure a secure connection.
Accordingly, it has been determined by the present disclosure there is a need for a cookware that overcomes, alleviates, and/or mitigates one or more of the aforementioned and other deleterious effects of the prior art.

Method and apparatus for attaching a handle using self piercing rivets


An embedded mission avionics data link system is provided which allows an aircraft to receive, transmit, and process a variety of different types of information. The present system has the capability of generating and receiving video information for viewing by a pilot in the cockpit. The system also requests, receives and recognizes situation awareness data as well as mission update data and processes this information accordingly. Any video images received by the pilot either externally or internally may be annotated and either stored in memory or transmitted externally. The system allows multiple aircraft on a mission to stay in constant communication as to relative positions to each other and targets, provide up-to-date information as to the situation which exists at the target, and do this in a mostly automatic fashion which reduces the workload of the pilot and significantly enhance the mission capability.

When a modem military aircraft flies a mission it is oftentimes necessary to fly in concert with other aircraft. This synchronous flying requires extensive planning of a route with respect to known threats, satisfactory knowledge of the threat location, and information on the capabilities of the threat. The mission planning must also include the coordination of activities among the aircraft. In order to execute a complex mission against a dangerous target, it is important that there are two-way lines of communications between all the aircraft as well as between the aircraft and a ground station.
Many modem military aircraft are equipped with a digital map system which displays to the pilot the characteristics of the terrain around the aircraft, the location of the aircraft relative to the terrain, the flight path of the aircraft, and the location of the target relative to the aircraft. Other information displayed to the pilot may include the visibility of the aircraft relative to the target and possible flight paths for the aircraft to avoid detection by the threat. The disadvantage of a digital map system is that the map image is pre-processed and does not include dynamic elements of real-time mission scenes.
Currently, military aircraft are limited on the amount of information which is received and transmitted from other aircraft as well as from a ground station. These transmissions are mostly limited to voice communications. Limited means also exist to transmit some mission information to an aircraft. As currently configured, the voice communication and mission updates require two separate systems in order to process the different types of information. The need to operate two separate systems during a mission can be a burden on the flight crew. A system which provides for greater transmission and receipt capability of flight and mission information, would only be desirable in an aircraft data link if the use of these functions did not add significantly to the workload of the flight crew. The system would have to identify the types of information being received, automatically prioritize it, and compile it in a format for the flight crew to easily access on their in-cockpit display screens.
When a military aircraft is flying a mission within the vicinity of a threat, certain types of information can increase the likelihood of the success of the mission. The effectiveness of the flight crew would be enhanced by providing means for the aircraft to communicate in many different modes and provide constant updates of each other's position as well as other mission related data. There would also be an advantage to transferring video imagery information between aircraft. One example is where a scout ship flies on ahead of the rest of the aircraft to perform some kind of reconnaissance on a target. This scout ship can then transmit back to the other aircraft as well as a ground station real-time video imagery of the target to provide up to date conditions at the threat site. Another advantageous feature would be the ability to automatically, without significant attention from the pilot, transmit updated mission information among the aircraft as well as to a ground station.

Embedded mission avionics data link system


A semiconductor memory device and method are provided that enhance data output speed of a DRAM or the like by reducing the time difference between the data output operation from a preceding word line and the data output operation from a succeeding word line. The semiconductor memory device includes a memory cell array arranged with multiple memory cells having a corresponding word line and a corresponding bit line, a row decoder for decoding a row address to select and activate a word line of the memory cell array and a sense amplifier for sensing and amplifying the data in a memory cell coupled to the activated word line when the data is applied to the corresponding bit line. The semiconductor further includes first and second latches respectively storing data using the sense amplifier taken from a memory cell coupled to a preceding activated word line and a succeeding activated word line. A switching block controls the data path between the sense amplifier and the first latch, or the sense amplifier and the second latch and a column decoder selects and applies the data stored in the first or second latch to a data bus. A data bus sense amplifier amplifies the data applied to the data bus before transmitting it to a data output buffer.

1. Field of the Invention
The present invention relates to a semiconductor memory device and method, and in particular, to a semiconductor memory device and method with enhanced data output speed.
2. Background of the Related Art
Various types of semiconductor memory devices are used in a computer system or other program driving system. Common memory devices include DRAM and SRAM. SRAM is very fast but expensive because of a low degree of integration. Therefore, DRAM is generally used in personal computers where the relatively low price and low speed are acceptable.
FIG. 1 is a block diagram showing the structure of a semiconductor memory cell array and peripheral circuits of a related art DRAM. As shown in FIG. 1, a row decoder 11 decodes a row address to select and activate a word line of a memory cell array 12. When a word line of the memory cell array 12 is activated, a column decoder 14 decodes a column address to select a bit line of the memory cell array 12. Sense amplifier 13 sequentially senses and amplifies data in a memory cell connected to the activated word line and then transmits the data to a data output buffer (not shown) through a data bus sense amplifier 15.
FIG. 2 is a circuit diagram depicting a memory cell of the memory cell array 12. The general structure of the memory cell includes a transistor and a capacitor. As shown in FIG. 2, a memory cell MCI has a structure with a capacitor C1 connected between the drain of NMOS transistor Q1 and ground. The source of NMOS transistor Q1 is connected to bit line BIT and the gate to the word line WLn.
As shown in FIG. 2, another memory cell MC2 includes an NMOS transistor Q2 and a capacitor C2. The gate of NMOS transistor Q2 is connected to a word line WLn+1 and the source to a bit line /BIT. As described above, when the word line WLn is activated, the NMOS transistor Q1 is turned on. When the word line WLn+1 is activated, the NMOS transistor Q2 is turned on.
The capacitors C1 and C2 are charged or discharged in accordance with the logic value of data. For example, when the word lines WLn and WLn+1 are respectively activated in a data read mode, the data charged is discharged through the turned on NMOS transistors Q1 and Q2. The discharged data is applied to the bit lines BIT and /BIT so that the bit lines BIT and /BIT vary in voltage. If the capacitors are not charged, there is no change in the voltage of the bit lines BIT and /BIT.
The two bit lines BIT and /BIT are precharged with a voltage of VCC/2. When the NMOS transistors Q1 and Q2 of the memory cells MC1 and MC2 are turned on so that the data of the capacitors C1 and C2 are respectively transmitted to the bit lines BIT and /BIT, the sense amplifier 13 compares the voltage difference between the two bit lines BIT and /BIT, and amplifies the voltage difference.
Referring to FIGS. 1 to 3, the data read operation of the related art semiconductor memory device will now be described. FIG. 3 is a timing chart showing the read operation of a related art semiconductor memory device. The case data of "0" being stored in the memory cell will be described as an example.
FIG. 3(a) shows a row address strobe signal /RAS and FIG. 3(b) shows a column address strobe signal /CAS. FIG. 3(c) shows a write enable signal /WE and FIG. 3(d) shows a word line voltage. FIG. 3(e) shows voltages of a pair of bit lines BIT and /BIT. FIG. 3(f) shows a bit line selection signal CD transmitted from the column decoder 14.
The row address strobe signal /RAS indicates that the row address is input. The column address strobe signal /CAS indicates that the column address is input. The write enable signal /WE controls the read and write operations of the memory device. A high level of the write enable signal /WE causes the write operation and a low level causes the read operation.
Time t0 is a stand-by state of the timing charts of FIGS. 3(a)-3(f) where the voltage of the word line is low. As described with respect to FIG. 2, the two bit lines BIT and /BIT of the memory cell are pre-charged with the potential VCC/2 or half of the power voltage VCC.
At time t1, the two bit lines BIT and /BIT of FIG. 2 are in a floating state that is not affected by an outside environment. Accordingly, the two bit lines BIT and /BIT sustain the precharge potential VCC/2.
At time t2, the row decoder 11 decodes the row address transmitted from the outside to select word line (e.g., WLn). The row decoder 11 increases the voltage of the selected word line to the sum of the supply voltage VCC and a MOS transistor threshold voltage, Vt. In other words, the voltage level VCC+Vt, is a word line activation level that activates the word line (e.g., WLn).
The NMOS transistor Q1, whose gate is connected to the activated word line WLn, is turned on so that the data stored in the capacitor C1 is applied to the bit line BIT. As shown in FIG. 3, the data of the capacitor C1 is "0". The charges are applied to the bit line BIT in accordance with the data of the capacitor C1 so that the potential of the bit line BIT becomes a potential slightly lower or slightly higher than the precharge voltage VCC/2. The bit line /BIT sustains the precharge voltage VCC/2. Thus, the potential of a bit line to which a cell to be read is connected is changed and the bit line not connected to the cell to be read remains VCC/2. Accordingly, a specified potential difference exists between the two bit lines BIT and /BIT. The sense amplifier 13 is activated to amplify the potential difference between the bit lines BIT and /BIT between time point t3 and time point t4.
When the amplification by the sense amplifier 13 is achieved to some degree (e.g., between t5 and t6), the ground voltage VSS is applied to the bit line BIT and the supply voltage VCC is applied to the bit line /BIT. Thus, the voltage "0" or the potential of the ground voltage VSS is stored by the capacitor C1 through the NMOS transistor Q1, which is turned on by the high level voltage of the word line WLn. As the result, the data can be read and the refresh operation is performed (i.e., data is rewritten).
Such operations are executed when the data stored in the capacitor C1 is "0". If the data of the capacitor C1 is "1", the opposite operations are performed.
If the amplification operation of the sense amplifier 13 is achieved to some degree so the potential difference between the two bit lines BIT and /BIT exceeds the sum of the respective threshold voltages of usual PMOS and NMOS transistors or ".vertline.Vtn.vertline.+.vertline.Vtp", a signal of the bit line BIT corresponding to the bit line selection signal CD is transmitted to the data output buffer using the data bus sense amplifier 15 via a data bus.
The data from the bit line is transmitted to the data output buffer through a data bus, which is connected to the bit line. The respective data buses switch according to the column address transmitted from the column decoder 14.
The data bus sense amplifier 15 amplifies the data that is transmitted from the bit line to the data bus, before transmitting it to the data output buffer. When the data transmission is completed, the data bus is precharged.
At time point t7, the word line WLn is deactivated to sustain the data stored in the capacitor C1 (e.g., by the refresh operation previously described). At time t8, for succeeding data output operations, the two bit lines BIT and /BIT are equalized by the precharge voltage VCC/2. Thus, the bit lines BIT and /BIT are placed in the stand-by state.
The series of data output operations in a related art semiconductor memory device as described above are performed with the deactivation operation of the word line whose data output is completed, and the activation of another word line whose new data will be output.
Thus, after the data transmission is completed from the activated word line, the precharge voltage is applied to the respective bit lines. Further, another word line cannot be activated until the voltage of the word line is lowered to the ground potential. Accordingly, related art semiconductor memory devices, especially DRAM, have slow data output speeds.


A live video matching system provides a matching service between a video demander and a video provider. An orchestration module of the system dynamically adjusts live services provided by SDN edge devices according to network available resources. An SDN edge device of the system dynamically converts and integrates multiple video streams to generate a virtual channel based on results of matching within multiple requests for videos and provides live video channels for interested users.

As mobile networks are developed and smart phones are popular, network application services are important. Live video matching services, for example, have been provided by many mobile applications and web sites, which are implemented via the Peer-to-Peer (P2P) communication or the client-server architecture.
However, the Peer-to-Peer (P2P) communication may have heavy loading when numerous clients request live video services at the same time. In regard to the client-server architecture, video data streams are transmitted to the clients via a content delivery network server, which results in high latency and bandwidth bottlenecks.

NANNING FUGUI PRECISION INDUSTRIAL CO., LTD.


A method for checking an IC layout is used for checking the wire line width in the circuit layout. The IC includes at least a first metal layer having at least a wire, and the wire has a plurality of wire segments. The method includes the steps of checking the width of each wire segment, wherein if at least a narrow wire segment has a width smaller than a predetermined width, the narrow wire segment is removed; if there is at least a non-coupling wire segment not coupled to a voltage source in the remained wire segments, outputting the non-coupling wire and disposing a coupling wire to couple the non-coupling wire segment and the voltage source.

1. Field of the Invention
The invention relates in general to a method for checking an IC layout, and more particularly to a method for checking a wire layout causing high power wire resistance in the IC layout.
2. Description of the Related Art
FIG. 1 is a partially equivalent circuit diagram showing a conventional integrated circuit (IC). Referring to FIG. 1, the equivalent circuit 10 includes a voltage source 11, a plurality of equivalent wire resistors R11, R12, R13, R21, R22 and R23, and a plurality of device units 12, 13 and 14. Theoretically, the equivalent resistance of an ideal wire is zero in the circuit property. In fact, however, each wire has an equivalent resistance. If the electric currents flowing through the device units 12, 13 and 14 are I1, I2 and I3, respectively, because the equivalent wire resistors R11, R12 and R13 cause voltage drops and the equivalent wire resistors R21, R22 and R23 cause ground bounces, the voltages VG3 and V′G3 are represented in the following equations according to the ohm's law:VG3=V−R11(I1+I2+I3) −R12(I2+I3)−R13*I3  (1),andV′G3=R21(I1+I2+I3) +R22(I2+I3)+R23*I3  (2).
Thus, the operation voltage (the voltage drop across two ends) of the device unit 14 is not the ideal, voltage (VDD-GND), but is (VG3−V′G3), which is dropped by (R21+R11)(I1+I2+I3)+(R22+R12) (I2+I3)+(R23+R13)*I3. Hence, the larger the equivalent wire resistance is, the larger the voltage drop is. The large equivalent wire resistance may cause the timing problems' and the functional failures of the device unit. The above-mentioned problem becomes serious when the IC manufacturing technology is getting more and more advanced such that the line width is getting smaller and smaller, and the wire's equivalent resistance is getting larger and larger. Thus, the difference between the actual operation voltage of the device and the ideal operation voltage thereof is getting larger and larger.
Consequently, it is an important subject of the circuit layout to effectively reduce the wire's resistance.
However, When the IC layout is done according to the currently used IC CAD (computer aided design) software, there are no known objective and effective rules and methods to judge whether or not the circuit layout causes the wire resistance too high. Instead, the circuit layout engineer can only check the complicated circuit layout with his/her naked eyes according to his/her experience for the subjective assertion. Thus, the prior art method is time-consuming, laborious, inefficient, and ineffective.


High-voltage MOS transistors with a floated drain-side auxiliary gate are provided. The high-voltage MOS transistors include a source region and a drain region provided in a semiconductor substrate. A main gate electrode is disposed over the semiconductor substrate between the drain region and the source region. A lower drain-side auxiliary gate and an upper drain-side auxiliary gate are sequentially stacked over the semiconductor substrate between the main gate electrode and the drain region. The lower drain-side auxiliary gate is electrically insulated from the semiconductor substrate, the main gate electrode and the upper drain-side auxiliary gate. Methods of fabricating the high-voltage MOS transistors are also provided.

Nonvolatile memory devices include a plurality of nonvolatile memory cells and peripheral circuits for driving the nonvolatile memory cells. The nonvolatile memory cells may be programmed or erased using a high voltage of about 10 to 20 V. Also, data stored in the nonvolatile memory cells may be read using a low voltage of about 5 V or lower. Thus, the peripheral circuits may include high-voltage MOS transistors used in the program and erase operations as well as low-voltage MOS transistors used in the read operation. In general, each of the nonvolatile memory cells adopts a stacked gate structure. The stacked gate structure includes a floating gate, an inter-gate dielectric layer and a control gate electrode, which are sequentially stacked.
As the nonvolatile memory devices become more highly integrated, the nonvolatile memory cells have been scaled down in size. Nevertheless, there may be a limitation in reducing the equivalent oxide thickness of the inter-gate dielectric layer. As a result, if the nonvolatile memory cells are shrunk in order to increase the integration density of the nonvolatile memory devices, the coupling ratio of the nonvolatile memory cells is decreased to make it difficult to lower the program and erase voltages. Therefore, it is difficult to scale down the high-voltage MOS transistors since the high-voltage MOS transistors should be designed to have a breakdown voltage higher than the program and erase voltages. The program and erase voltages may be directly related to the drain breakdown voltages of the high-voltage MOS transistors.
FIG. 1 is a cross-sectional view illustrating a conventional high-voltage MOS transistor.
Referring to FIG. 1, an isolation layer 3 is provided in a predetermined region of a semiconductor substrate 1 to define a high-voltage active region 3a. A source region 12s and a drain region 12d are provided in both ends of the high-voltage active region 3 a, respectively. A high-voltage gate electrode 7 is disposed over the substrate 1 between the source and drain regions 12s and 12d, and a high-voltage gate insulating layer 5 is interposed between the high-voltage gate electrode 7 and the substrate 1. The drain region 12d may include a heavily doped drain region 11d spaced apart from the high-voltage gate electrode 7 and a drain extension 9d extending from the heavily doped drain region 11d to be adjacent to the high-voltage gate electrode 7. Similarly, the source region 12s may include a heavily doped source region 11s spaced apart from the high-voltage gate electrode 7 and a source extension 9s extending from the heavily doped source region 11s to be adjacent to the high-voltage gate electrode 7. The source and drain extensions 9s and 9d have an impurity concentration lower than that of the heavily doped source and drain regions 11s and 11d.
When the high-voltage MOS transistor shown in FIG. 1 is an NMOS transistor, the high-voltage MOS transistor may be turned off by grounding the high-voltage gate electrode 7, the source region 12s and the semiconductor substrate 1 and applying a positive drain voltage VD to the drain region 12d. In this case, if the drain voltage VD increases, the drain extension 9d may be depleted. In addition, if the drain voltage VD further increases, a gate electric field Eg between the high-voltage gate electrode 7 and the heavily doped drain region 11d increases. Increase of the gate electric field Eg may causes drain leakage current IL corresponding to a band-to-band tunneling current that flows through a junction region between the heavily doped drain region 11d and the substrate 1. The drain leakage current IL is referred to as a gate induced drain leakage (GIDL) current. The GIDL current should be suppressed in order to improve the drain breakdown voltage of the high-voltage MOS transistor.
The GIDL current may be generated due to a high electric field between the high-voltage gate electrode 7 and the heavily doped drain region 11d. Accordingly, there is a need to increase a distance D between the high-voltage gate electrode 7 and the heavily doped drain region 11d in order to increase the drain breakdown voltage of the high-voltage MOS transistor. However, if the distance D between the high-voltage gate electrode 7 and the heavily doped drain region 11d increases, the area occupied by the high-voltage MOS transistor may also increase to degrade the integration density of a semiconductor device.
A MOS transistor for suppressing the GIDL current is disclosed in Korean Patent No. 10-0436287 to Suh, entitled "Transistor of Semiconductor Device and Method of Fabricating the Same". According to Suh, first and second auxiliary electrodes are provided at both sides of a gate electrode of a transistor, respectively. The first auxiliary electrode overlaps a source region, and the second auxiliary electrode overlaps a drain region. The gate electrode and the second auxiliary electrode are connected to first and second voltage supply sources, respectively. When a negative voltage is applied to the gate electrode in order to turn off the transistor, a voltage of 0 V is applied to the second auxiliary electrode so that a GIDL current flowing through a junction of the drain region can be suppressed.

Nonvolatile memory devices including high-voltage MOS transistors with floated drain-side auxiliary gates and methods of fabricating the same


A multi-application transparent platform intercepts an incoming application file communicated from a source across a first TCP connection by terminating the first TCP connection on the multi-application transparent platform and supplying the application file to an application program. The application file is received onto the platform in the form of multiple incoming Ethernet frames. The application layer program analyzes the application file and identifies characteristics of the application file, such as virus content, that are not apparent in the individual Ethernet frames that carried the application file over the first TCP connection. The platform resends the application file over a second TCP connection in outgoing frames having the same IP addresses and Ethernet MAC addresses as the incoming frames. The platform can be inserted into a running network without reconfiguring devices on the network.

FIG. 1 (prior art) is a diagram of an internetwork 1 including two local area networks (LANs) 2 and 3 connected by the Internet 4. A client 5 on LAN 2 wishes to retrieve a webpage 6 from a web server 7 on LAN 3. The client 5 makes a request for the webpage 6 through a filtering firewall 8.
FIG. 2 (prior art) is a diagram showing the Ethernet/IP/TCP protocol messages used to set up the connection between client 5 and web server 7 and to send the webpage 6. Firewall 8 provides a level of security for messages entering LAN 2 by filtering out certain of those messages based upon the content of Ethernet frames. Firewall 8 is generally unable, however, to analyze application level data as a unit, such as executable files received in multiple messages and Ethernet frames.
FIG. 3 (prior art) is a diagram of an internetwork 20, also including LANs 2 and 3 and Internet 4. In order to analyze application level data passing into LAN 2, a classic proxy 21 is used to send messages from client 5 through a gateway 22 and out of LAN 2. Client 5 makes a request for the webpage 6 to the classic proxy 21 instead of directly to the web server 7. Classic proxy 21, in turn, makes a new request for web page 6 to web server 7 on behalf of client 5. Web server 7 returns webpage 6 to classic proxy 21. Classic proxy 21 forwards the webpage 6 to client 5. Because the complete application level data in the form of webpage 6 is received onto classic proxy 21, application level anti-virus software 23 executing on the classic proxy 21 can analyze application level data, such as a complete execute file, and not forward the data to client 5 if a virus is detected.
FIG. 4 (prior art) is a diagram showing the Ethernet/IP/TCP protocol messages used to retrieve the webpage 6 through classic proxy 21. FIG. 4 illustrates how a first TCP connection is established between client 5 and classic proxy 21. A second TCP connection is established between classic proxy 21 and web server 7. Inserting classic proxy 21 into LAN 2 involves reconfiguring client 5, and all other clients of LAN 2, to send their requests, for example, for webpage 6, to classic proxy 21. Moreover, messages from different clients appear all to come from the source IP address of classic proxy 21, as opposed to the individual source IP address of the relevant client. Reconfiguring each client requires a degree of networking skill and effort that makes this solution undesirable.
FIG. 5 (prior art) is a diagram of an internetwork 30, also including LANs 2 and 3 and Internet 4. A transparent proxy 31 is used instead of classic proxy 21. FIG. 6 (prior art) shows the Ethernet/IP/TCP protocol messages between client 5 and gateway 22. Less reconfiguration is involved when employing transparent proxy 31 than for classic proxy 21 because client 5 receives messages containing the source IP address of the gateway 22, instead of the source IP address of the transparent proxy 31. Client 5 can, therefore, return response messages to the gateway 22 without being reconfigured to send them through the transparent proxy 31.
Unfortunately, "transparent" proxy 31 is not transparent with respect to 48-bit Ethernet hardware addresses, also called MAC addresses. Consider the example where transparent proxy 31 is inserted into LAN 2 between client 5 and gateway 22. Client 5 requests webpage 6 from web server 7. Before the webpage 6 can be communicated, a first TCP connection must be established between web server 7 and transparent proxy 31, and a second TCP connection must be established between transparent proxy 31 and client 5. When Ethernet frames are received onto client 5 across the second TCP connection, they contain the source MAC address of the transparent proxy 31 and not the source MAC address of the gateway 22. Note in FIG. 6 (prior art) that messages 32 through 36 from the transparent proxy 31 to client 5 have source MAC addresses of the transparent proxy 31 (SMAC=NOPQ). This hinders client 5 from gathering the MAC addresses of other devices on LAN 2.
Moreover, the messages that gateway 22 receives from transparent proxy 31 include the source MAC address, as well as the source IP address, of the transparent proxy 31. Therefore, "transparent" proxy 31 is not transparent to web server 7. Web server 7 sees only the transparent proxy 31 and does not distinguish among messages from individual clients. Note in FIG. 6 that messages 37 through 41 have the source MAC address (JKLM) and the source IP address (10.0.0.3) of the transparent proxy 31. Thus, because the original sender of messages coming from transparent proxy 31 cannot be determined from the source IP and MAC addresses, customizing services towards individual clients is more difficult. Moreover, client 5, and the other clients on LAN 2, must still be reconfigured to some extent to send requests to the MAC address of the transparent proxy 31. Expertise and effort are therefore required to operate and maintain a LAN network where clients communicate through a proxy, even where the proxy is a so-called "transparent" proxy. This is undesirable.

Transparent bridge that terminates TCP connections


A knee prosthesis comprising a femoral component, a tibial component and a meniscal component therebetween, a stabilising peg extending from the tibial component through an elongated slot in the meniscal component and into an opening in the femoral component between a pair of condylar members thereof. The part of the peg extending through the slot allows the meniscal component to rotate and also to move linearly about the peg along one path, whilst the part of the peg in said opening engages cam surfaces on a projection between said condylar members as the knee is flexed, in use, and said linear movement of the meniscal component occurs.

1. Field of the Invention
This invention relates to a knee prosthesis for fitting to a patient as a replacement knee joint.
2. Prior Art
Modern total knee replacement involves the resurfacing of the femoral condyles with a metallic component, roughly approximating to the shape of the anatomical femoral condyles, and resurfacing the tibial plateau with a polyethylene component having a metallic base plate. Conformity between the polyethylene of the tibial component and the metallic femoral component has historically been a troublesome area. Ideally the femoral component should be congruent with the top of the tibial component in order to minimise polyethylene wear. The difficulty, however, is that the knee joint does not act as a fixed axis hinge. During normal movements of the knee, rotation of the femur upon the tibia occurs, and roll back of the femoral condyles upon the tibia occurs, particularly when the knee is flexed.
UK Patent No 1,534,263 discloses a knee joint device formed by a femoral component, a floating plastics material meniscal component, and a flat topped tibial component. This device allowed congruency between the femoral and meniscal components, but since the meniscal component was free to move antero-posteriorly and to rotate, rotational and sheer stresses were not generated at the tibial implant fixation interface and loosening did not occur. Moreover wear of the polyethylene was found to be low. However this device suffered from the disadvantage that under certain circumstances posterior or medio lateral dislocation could occur, with the meniscal component possibly being displaced into the synovium.
Whilst the device of UK Patent No 1,534,263 was generally concerned with a replacement joint to address unicompartmental disease (medial arthritis of the knee), where the cruciate ligaments and lateral compartment of the knee were left untouched, it is common practice to perform a total knee replacement, where the lateral component of the knee is also resurfaced and the anterior cruciate ligament or both cruciate ligaments are resected. A commonly employed total knee replacement is the Insall Burstein replacement in which both cruciate ligaments are resected and a posterior stabilised design of knee replacement is inserted. The provision of a bearing in the form of a cam mechanism between the femoral component and the polyethylene tibial component means that with increased flexion of the knee increased posterior translation of the femoral component upon the tibia occurs, partially simulating the normal kinematics of the knee. The cam mechanism replaces the function of the cruciate ligaments. However although the kinematics in terms of femoral roll back are adequately addressed, the bearing between the tibial and femoral components is incongruent, and therefore theoretically undesirable, resulting in high contact stress, leading to plastics wear.
Another type of total knee replacement involves retention of the posterior cruciate ligament, with a polyethylene meniscus, broadly congruent with the femoral component, being allowed to rotate and/or slide on a polished metal tibial plateau, thereby addressing both the issue of high contact stress and also tibial loosening. A disadvantage of this type of knee replacement relates to the function of the posterior cruciate ligament, with the anterior cruciate ligament resected. For the cruciate ligaments to act effectively, both the anterior and the posterior ligaments do have to be present in the knee, as they represent a four bar linkage between the femur and the tibia. It has been shown that isolated retention of the posterior cruciate ligament does not adequately allow the normal kinematics of the knee to occur. Accordingly upon flexion of the knee, instead of the normal posterior translation of the femur upon the tibia, the reverse is often found to occur, whereby the femoral component abnormally translates forwards on the tibia, with, in the worst case, posterior dislocation.
This has two undesirable side effects. Firstly the patello-femoral contact pressures are abnormally increased, thus increasing the potential for pain at the front of the knee, or loosening of the patellar component, or fracture of the patella. Secondly a patient with this abnormal anterior translation may not be capable of full flexion of the knee after replacement, as soft tissue impingement between the femur and the tibia posteriorly can occur when the normal femoral roll back in flexion does not happen.


An embodiment of the invention generally relates to an apparatus for deploying a segmented reflector antenna. The apparatus includes a plurality of segments that can be rigid or flexible where each segment is hinged to an adjacent segment on either longitudinal side. The apparatus also includes a base, a plurality of inner deployment beams, and a plurality of outer deployment beams. Each inner deployment beam connects an inner side of a respective segment to the base and having a folded position and an extended position. Each outer deployment beam connects an outside side of a respective segment to the base and has a folded position and an extended position. The plurality of segments in a hinged folded position in response to the plurality of inner deployment beams being in the folded position and the outer deployment beams being in the folded position.

Structures, e.g., conventional collapsible dish structures with flexible mesh or flexible surfaces, that can be folded during transit and deployed upon reaching their destination have been widely used, particularly in situations in which cargo space is limited or otherwise at a premium. Advantageously, collapsible structures may be stowed compactly in a vehicle while not in use, and then deployed to a desired configuration to perform a given application. Although the space-saving characteristics of collapsible structures benefit many applications, space applications in particular stand to benefit to a high degree due to the limited amount of cargo space onboard a spacecraft and the high cost of space travel.
Recent spacecraft applications have mandated the use of shorter wavelengths in the electromagnetic spectrum, as well as an increased interest in the collection and focusing of light waves in space, collapsible dish structures have been required to meet stringent requirements for surface smoothness and contour control to minimize scattering and improve antenna gain. These requirements have resulted in an increased dependence on the type of antenna, which utilize solid panels. These solid panel type antennas are more suitable for short and optical wavelengths as compared with mesh collapsible antenna designs.
Several approaches currently are used to address the transportation of deployable rigid antenna systems on a spacecraft. One conventional method of packaging includes hinging segments only on the inside edges of the segments. The segments are then stowed, alternately forward and aft, and then opened out to the final positions. Another example of a conventional method includes stacking the segments horizontally, either individually or in pairs, where the segments or the pairs are not fully connected at the edges. During deployment, the segments are swung into their respective final positions. Yet another conventional method of packaging involves stacking the segments vertically, either individually or in pairs, where the segments or the pairs are not fully connected together at the edges. During deployment, the segments are moved into their final positions.
These conventional methods of packaging segmented rigid reflectors suffer from complexity in the implementation of the packaging and result in inefficient use of the stowed volume, and problematic gaps between the deployed segments or between pairs of segments.

System and method for packaging and deploying a segmented reflector antenna

General Dynamics Advanced Information Systems, Inc.


A shock absorber formed of an inner tubular element telescopingly slidable within an outer tubular element. A piston is mounted on the inner tubular element and is provided with valving that permits adjustability of compression damping separate from rebound damping. Preferably, the piston slides within a glide tube substantially concentrically mounted within the outer tubular and having a highly finished surface along which the piston slides. A first chamber is formed within the glide tube a second chamber is formed between the outer tubular element and the glide tube. Valves are positioned between these first and second chambers to control compression flow and rebound flow separately and independently. A main compression spring is positioned external to and between the inner and outer tubular elements of the shock absorber, and acts to bias the tubular elements away from each other. A gas chamber positioned within the inner tubular element serves to assist the main compression spring in biasing the inner and outer tubular elements, and also acts as part of a volume compensation system when the shock absorber is compressed and expanded.

The present invention relates to the design and construction of high performance shock absorbers. More particularly, the present invention relates to a light-weight, adjustable twin tube shock absorber comprising an air-assisted, coil sprung suspension system that is hydraulically damped. The suspension system of the present invention is particularly suited for use in connection with a bicycle suspension system such as a rear bicycle wheel suspension assembly.
In the past, suspension systems in general have been used for many applications, including cushioning impacts, vibrations or other disturbances experienced by vehicles and machinery. Typical vehicles benefitting from the use of suspension systems include bicycles and motor-cycles. For example, bicycles have been developed with suspension systems for cushioning impacts or vibrations incurred when the bicycle is ridden over bumps, ruts, rocks, pot holes, or other obstacles. Typically, bicycle suspension systems have been configured for use in the front or rear bicycle fork, in the head tube that connects the front fork to the bicycle frame and handlebars, in the seat post, and in conjunction with a rear wheel swing-arm assembly, as well as in other locations.
Shock absorbers are commonly used with suspension systems to damp undesirable oscillations of the suspension system caused by irregularities of the road surface. A commonly used shock absorber is a hydraulic type which uses a piston and cylinder arrangement. Damping fluid in the cylinder is forced by the piston (which moves with the functioning of the suspension system) through narrow holes or valves. The resistance encountered as the fluid passes through the holes or valves damps the oscillations of the suspension system.
There is an ongoing need for improvements in the art of shock absorbers. For example, there is a need in shock absorbers, particularly those used in bicycle suspension applications, for reductions in weight and manufacturing costs. There is also a need for a high degree of adjustability of the damping capabilities and characteristics of shock absorbers. In particular, there is a need for a shock absorber in which the main compression spring used for supporting a load applied to the suspension system has a broad range of adjustability for adapting to a wide variety of load conditions. In addition, it is desirable to have a shock absorber with a high degree of compression and rebound damping adjustment capability, and particularly for such a shock absorber in which the compression and rebound damping characteristics are separately adjustable. Finally, there is a need for improvements of the kind previously described which result in a more rigid shock design.
It is therefore an object of the present invention to provide a shock absorber that permits a high degree of main compression spring adjustability.
It is another object of the present invention to provide a shock absorber having a damping system permitting a high degree of damping adjustability.
It is yet another object and to provide a shock absorber in which the compression and rebound damping characteristics are separately adjustable.
It is another object to provide a rigid shock absorber having low weight and manufacturing costs.


An optical path delimiter having a lens is disposed so as to be in contact with a transparent lid bonded to a surface of a solid-state image sensor, and is fixed without bonded. Further, the solid-state image sensor to which the transparent lid is bonded, the optical path delimiter disposed so as to be in contact with the transparent lid without bonded, a DSP serving as a signal processor, a circuit part and a wiring board are fixed by being sealed in a synthetic resin. Even when distortion occurs due to warpage, flexure or the like on a board where the solid-state image sensor is disposed, the accuracy of the alignment of the lens with respect to the solid-state image sensor never decreases. In addition, the solid-state image sensor or the signal processor is never damaged by an external shock.

The present invention relates to an optical device module incorporated in digital cameras, camera phones and the like and having a solid-state image sensor for photographing a subject, and a method of fabricating the optical device module.
A solid-state image sensor provided in digital cameras, digital video cameras, camera phones and the like is for capturing the subject to be photographed. The solid-state image sensor is integrated into a module together with a lens, an infrared intercepting material and a signal processor processing the electric signal converted from captured image by the image sensor, and is provided as an optical device module. In recent years, digital cameras, camera phones and the like incorporating the optical device module have been reduced in size, and the optical device module has also been reduced in size.
In the optical device module, it is necessary that the optical center of the image sensing area of the solid-state image sensor coincide with the optical center of the lens, and it is also necessary that the plane formed by the image sensing surface be orthogonal to the optical axis of the lens. When the accuracy of the alignment of the lens' axis with the sensor's center is low, a problem occurs such that focus cannot be achieved or that the image captured by the solid-state image sensor is dark. For this reason, an adjustment mechanism for adjusting focus is provided, and focus adjustment is performed after the optical device module is fabricated. However, the provision of the adjustment mechanism hinders the size reduction of the optical device module.
Japanese Patent Application Laid-Open No. 2000-125212 proposes an imaging module in which a semiconductor chip where a solid-state image sensor is formed is bonded onto a ceramic board, a frame material holding an infrared intercepting material is bonded onto the ceramic board so as to cover the semiconductor chip and a lens frame material holding a lens is bonded onto the ceramic board so as to cover the frame material. By bonding the semiconductor chip, the frame material and the lens frame material onto the same plane of the ceramic board, their alignment accuracy is improved.
Japanese Patent Application Laid-Open No. 2004-40287 proposes an image sensor module in which an image sensor chip is bonded onto a board, a housing holding a lens and an optical filter is bonded onto the board so as to cover the image sensor and the lens is pressed into the housing by a lens retainer that becomes elastically deformed. By fixing the lens in the housing by the lens retainer, the distance between the lens and the image sensor can be accurately defined.
Japanese Patent Application Laid-Open No. 2004-301938 proposes an optical device module in which a signal processor that processes signals outputted from a solid-state image sensor is bonded to a wiring board, the solid-state image sensor is bonded onto the signal processor, a transparent lid is bonded to a surface of the solid-state image sensor and a lens holder holding a lens is bonded to the transparent lid. Since the lens holder is bonded to the transparent lid bonded to the surface of the solid-state image sensor, the accuracy of the alignment of the lens with respect to the solid-state image sensor can be improved.

This patent is subject to a terminal disclaimer.

Image sensor module with optical path delimiter and accurate alignment


Disclosed is a mixer comprising: a switching circuit, having a first pair of differential signal nodes and a second pair of differential signal nodes, for switching according to a local oscillation signal; an amplifying stage circuit, for receiving an input signal and amplifying the input signal; a load circuit, for serving as the loading of the mixer and generating an output signal of the mixer; a common-mode feedback circuit, for receiving the output signal and generating a feedback signal according to the output signal; a first current source, for receiving the feedback signal and generating a first current according to the feedback signal; and a second current source, for receiving the feedback signal and generating a second current according to the feedback signal.

1. Field of the Invention
The present invention relates to a mixer, and more particularly, to a low noise mixer.
2. Description of the Prior Art
A mixer is an indispensable component for a wireless communication system. The mixer is mainly used for mixing a baseband signal and a local oscillator signal to generate an RF signal, or for mixing a RF signal and a local oscillator signal to generate a baseband signal. In U.S. Pat. No. 3,241,078, Gilbert discloses a conventional active mixer, now widely known as a Gilbert cell. Various improvements to the Gilbert cell are continuously proposed. The primary advantage of the Gilbert cell is the better signal gain at the output signal; however, the Gilbert cell has a serious problem with flicker noise. The flicker noise in a mixer or an oscillator may be transformed to phase noise thereby limiting the spectral purity.
One improvement to the Gilbert cell is a mixer with a common-mode feedback circuit, which is disclosed in U.S. Pat. No. 6,865,382. The common-mode feedback circuit can fix the DC voltage of the mixer output terminal at a predetermined working range. This kind of mixer can provide an adjustable gain. However, the common-mode circuit also generates flicker noise, such that the output signal of the mixer is disturbed. Another improvement to the Gilbert cell is a current-bleeding type mixer. The current-bleeding type mixer is disclosed in page 108, "5 GHz CMOS RF RECEIVER FRONT END CIRCUIT DESIGN" by Dr. Tang Gu Tsun, Department of Electrical Engineering, National Taiwan University, wherein the current-bleeding type mixer is used for decreasing the flicker noise come along with the Gilbert cell. Since the flicker noise is in proportion to the current passing through the switch circuit, the current-bleeding type mixer, therefore, provides an auxiliary current to decrease the current passing through the switch circuit, and as a result, alleviating the flicker noise. Additionally, different kinds of current-bleeding type mixers are further disclosed in U.S. Pat. No. 6,889,037, as well as in "Current-Reuse Bleeding Mixer," Electronics Letters, 13Apr. 2000, Vol. 36, No. 8, IEE 2000 by Lee and Choi. Also, a different kind of mixer structure is disclosed in U.S. Pat. No. 6,850,753.


The present invention is a semiconductor device having the semiconductor element obtained by cutting a semiconductor wafer with the electrode pad formed on one side along a scribe line, a semiconductor element protective layer on the semiconductor element which has a opening on the pad, a stress cushioning layer on the layer which has the opening on the pad, a lead wire portion reaching the layer from the electrode pad via the openings, external electrodes on the lead wire portion, and the conductor protective layer on the layers, the layer and the conductor protective layer forming the respective end faces on the end surface of the semiconductor element inside the scribe line and exposing the range from the end face of the end surface to the inside of the scribe line.

The present invention relates to a semiconductor device and to a method of method of manufacture thereof; and, more particularly, the invention relates to a semiconductor device in which a semiconductor element has at least a stress cushioning layer and a semiconductor protective layer, and the end faces of these layers are positioned inside the cutting scribe lines formed on a semiconductor wafer, and the range of the surface at the end of the semiconductor element from the end face to the inside of the scribe line is exposed.
Recently, there has been an increasing demand for miniaturization and high performance in various electronic elements; and, in association with this demand, there have also been requests for a semiconductor device using electronic elements capable of speeding up information processing, as well as high density packing and high density assembly of the electron elements. Namely, in correspondence with these requests, there have been changes in the general character of a semiconductor device from the pin insertion type to the surface mounting type so as to increase the mounting density; and order to provide a multi-pin configuration, various packages from a DIP (dual inline package) to a QFP (quad flat package) or a PGA (pin grid array) have been developed.
However, in the QFP type package, the connection lead wires for connecting with the mounting substrate are centralized in the peripheral part of the package and the connection lead wires themselves are thin and deformable, so that, as the number of pins increases, the mounting becomes more difficult. In the PGA type package, the terminals to be connected to the mounting substrate are thin and long and a considerable number of terminals are centralized, so that high speed processing of information is difficult from the viewpoint of characteristics; and, moreover, the PGA arrangement is of a pin insertion type, so that surface mounting is not available, and it is disadvantageous in a high density assembly.
Recently, to solve various problems concerning these packages and to realize a semiconductor capable of high speed processing of information, a BGA (ball grid array) package having a stress cushioning layer between the semiconductor element and the substrate on which a wiring circuit is formed and a bump electrode which is an external terminal on the mounting substrate surface side of the substrate with the wiring circuit has been developed, and the details thereof are disclosed in the specification of U.S. Pat. No. 5,148,265. In the package described in the specification of U.S. Pat. No. 5,148,265, since the terminals to be connected to the mounting substrate are ball-shaped solder terminals, the lead wires are free of deformation, unlike the QFP type; and, since the terminals are scattered over the entire mounting surface, the pitch between the terminals is large and surface mounting can be carried out easily. The bump electrode which is an external terminal is shorter in length than that of the PGA type, so that the inductance component is decreased, and the information processing speed is increased, and high speed processing of information is made possible.
On the other hand, recently, in association with wide spread use of portable information terminals, there is an increasing demand for miniaturization and high density assembly of a semiconductor device. Therefore, recently, a CSP (chip scale package) having a package size that is almost equal to the chip size has been developed; and, for example, various types of CSPs are disclosed in "Nikkei Microelement" (pp. 38-64) issued by Nikkei BP, Ltd. (February 1998). CSPs disclosed in this publication are manufactured in such a way that semiconductor elements cut into pieces are bonded onto a polyimide or ceramics substrate on which a wiring layer is formed, and then the wiring layer and semiconductor elements are electrically connected, such as by wire bonding, single point bonding, gang bonding, or bump bonding, and the connections are sealed with resin, after which external terminals such as solder bumps are formed thereon.
In Japanese Patent Application Laid-Open 9-232256 and Japanese Patent Application Laid-Open 10-27827, methods for mass-producing CSPs are disclosed. These manufacturing methods form bumps on a semiconductor wafer, electrically connect a wiring substrate via the bumps, seal the connections with resin, form external electrodes on the wiring substrate, and finally cut the semiconductor wafer into pieces, thus producing individual semiconductor devices. Furthermore, "Nikkei Microelement" (p. 164 to p. 167) issued by Nikkei BP, Ltd. (April 1998) discloses another manufacturing method for mass-producing CSPs. This manufacturing method forms bumps by plating on a semiconductor wafer, seals the part other than the bumps with resin, forms external electrodes in the bumps, then cuts the semiconductor wafer into pieces, thus producing individual semiconductor devices. In addition, Japanese Patent Application Laid-Open 10-92865 discloses a semiconductor device of a type in which a resin layer for cushioning stress is installed between external electrodes and semiconductor elements. Individual semiconductor devices are manufactured by processing units of semiconductor wafers in a batch and finally cutting each semiconductor wafer into pieces.
The aforementioned semiconductor devices (semiconductor package) of the type in which a plurality of resin layers and external electrodes are formed in units of semiconductor wafers in a batch, and then each semiconductor wafer is cut (diced) into pieces, has a constitution such that the interfaces of a plurality of resin layers sequentially formed on each semiconductor wafer are exposed on the end face of each semiconductor package, so that when a large mechanical stress is applied to the interfaces of the plurality of resin layers at the time of dicing of the semiconductor wafer, or when a large thermal stress is applied to the interfaces of the plurality of resin layers due to sudden temperature changes at the time of mounting of the semiconductor package, the stress is centralized to the interfaces between the semiconductor element exposed on the end face of the semiconductor package and the plurality of resin layers, so that one or more of the plurality of resin layers are peeled off and the semiconductor package may be damaged.
As mentioned above, such a known semiconductor device cannot always exhibit high reliability, and it is difficult to obtain a high manufacturing yield rate.
The present invention was developed in view of the foregoing technical background and is intended to provide a semiconductor device, and a method of manufacture thereof, having high reliability and a satisfactory manufacturing yield rate, such that the constituent part to which a concentrated stress is applied at the time of cutting of a semiconductor wafer and at the time of mounting of a semiconductor device is improved so as to withstand the stress, whereby the occurrences of damage of the semiconductor devices due to applied stress are greatly reduced.
To accomplish the above object, the semiconductor device of the present invention has semiconductor elements obtained by cutting a semiconductor wafer, having an integrated circuit and an electrode pad formed on one side thereof, along a cutting scribe line; a stress cushioning layer installed on the semiconductor elements; a lead wire portion extending from the electrode pad to the top of the stress cushioning layer through an opening formed in the stress cushioning layer on the electrode pad; external electrodes arranged on the lead wire portion on the top of the stress cushioning layer; and a conductor protective layer installed on the stress cushioning layer, excluding the external electrode arranged portion; and a conductor portion. The stress cushioning layer, lead wire portion, conductor protective layer, and external electrodes have a means for forming each end face on the end surface of the semiconductor elements inside the cutting scribe line and exposing the range from the end face on the end surface of the semiconductor elements to the inside of the scribe line.
To accomplish the above object, the semiconductor device of the present invention has semiconductor elements obtained by cutting a semiconductor wafer, having an integrated circuit and an electrode pad formed on one side thereof, along the cutting scribe line; a semiconductor element protective layer installed on the semiconductor elements; a stress cushioning layer installed on the semiconductor element protective layer; a first opening formed in the semiconductor element protective layer on the electrode pad; a second opening formed in the stress cushioning layer on the electrode pad; a lead wire portion extending to the top of the stress cushioning layer through the first opening and second opening, respectively, from the electrode pad; external electrodes arranged on the lead wire portion on the top of the stress cushioning layer; and a conductor protective layer installed on the stress cushioning layer, excluding the external electrode arranged portion, and on the conductor portion. The semiconductor element protective layer, stress cushioning layer, lead wire portion, conductor protective layer, and external electrodes have a means for forming each end face on the end surface of the semiconductor elements inside the cutting scribe line and exposing the range from the end face on the end surface of the semiconductor elements to the inside of the scribe line.
To accomplish the above object, the semiconductor device manufacturing method of the present invention has a first step of forming a plurality of semiconductor elements having an integrated circuit and an electrode pad on the circuit forming surface of a semiconductor wafer; a second step of forming a stress cushioning layer on a plurality of semiconductor elements; a third step of forming an opening in the electrode pad of the stress cushioning layer and forming a notch wider than the width of the scribe line in the stress cushioning layer on the cutting scribe line of the semiconductor wafer; a fourth step of forming a lead wire portion extending from the electrode pad to the stress cushioning layer via the opening; a fifth step of forming a conductor protective layer which covers the stress cushioning layer and lead wire portion and has an external electrode connection window portion on the lead wire portion and a notch at the position corresponding to the notch of the stress cushioning layer; a sixth step of forming an external electrode in the external electrode connection window portion; and a seventh step of cutting the semiconductor wafer along the cutting scribe line, thereby obtaining a plurality of semiconductor devices in minimum units.
To accomplish the above object, the semiconductor device manufacturing method of the present invention has a first step of forming a plurality of semiconductor elements having an integrated circuit and an electrode pad on the circuit forming surface of a semiconductor wafer; a second step of forming a semiconductor element protective layer on a plurality of semiconductor elements; a third step of forming a first opening in the electrode pad of the semiconductor element protective layer and forming a notch wider than the width of the scribe line in the semiconductor element protective layer on the cutting scribe line of the semiconductor wafer; a fourth step of forming a stress cushioning layer on the semiconductor element protective layer; a fifth step of forming a second opening in the electrode pad of the stress cushioning layer and forming a notch at the position corresponding to the notch of the semiconductor element protective layer in the stress cushioning layer on the cutting scribe line of the semiconductor wafer; a sixth step of forming a lead wire portion extending from the electrode pad to the stress cushioning layer via the first and second openings; a seventh step of forming a conductor protective layer, which covers the stress cushioning layer and lead wire portion and has an external electrode connection window portion on the lead wire portion and a notch at the position corresponding to the notch of the stress cushioning layer; an eighth step of forming an external electrode in the external electrode connection window portion; and a ninth step of cutting the semiconductor wafer along the cutting scribe line, thereby obtaining a plurality of semiconductor devices in minimum units.
According to each feature mentioned above, each end face of the stress cushioning layer and conductor protective layer, or each end face of the semiconductor element protective layer, stress cushioning layer, and conductor protective layer in the end face area of each semiconductor element, is formed so as to be positioned inside the semiconductor wafer cutting scribe line and exposed within the range from the end face of each semiconductor element to the inside of the scribe line, so that when a semiconductor wafer is to be cut along the semiconductor wafer cutting scribe line, the semiconductor wafer can be cut by surely recognizing the positioning marks located on the semiconductor wafer, whereby defective semiconductor packages due to a displacement of the cutting position of each obtained semiconductor device can be eliminated.
Further, according to each feature mentioned above, when each semiconductor device is to be obtained by cutting a semiconductor wafer, the cut portion of each semiconductor device is formed to have a single-layer structure only of a semiconductor element; and, even if mechanical stress is generated at the time of cutting of the semiconductor wafer, the mechanical stress is just applied to the single-layer structure, so that a plurality of resin layers will not be peeled off by the mechanical stress.
Furthermore, according to each feature mentioned above, when each semiconductor device is to be mounted, even if thermal stress is generated due to great changes in the environmental temperature and the thermal stress is applied to a plurality of resin layers, a large mechanical stress is not applied to the plurality of resin layers when the semiconductor wafer is cut, so that the plurality of resin layers are hardly damaged, with the result that none of the plurality of resin layers will be peeled off or very little peeling will occur due to thermal stress.
As mentioned above, according to each feature mentioned above, the semiconductor devices will not be damaged at all or very little damage will occur due to application of mechanical stress and thermal stress, so that the reliability of the semiconductor devices can be enhanced, and the production yield rate of the semiconductor devices can be increased.

Semiconductor device and manufacturing method thereof


The invention is a trailer hitch alignment device that synergistically combines a laser level with an alignment mounting bracket, where the bracket, using a fastening means, provides a base on a vehicle for affixing the laser level to a vehicle. The laser level provides a laser beam which projects a lighted image that is a guide for coupling the trailer to a fifth wheel hitch on the vehicle. The level provides a means for confirming that the trailer, the vehicle, and the coupled trailer and vehicle all have the proper weight distribution as evidenced by their angle.

1) Field of the Invention
The invention relates to a trailer hitch device, and more particularly to a trailer hitch alignments device for hitching a trailer to a vehicle fitted with a fifth wheel hitch, where the device is additionally a laser level.
2) Prior Art
U.S. Pat. No. 6,176,505 B1 to Capik et al. teaches an optically guided alignment system. The invention teaches a trailer hitch alignment apparatus having a pair of light sources that emit different color light beams. The patent teaches that a single light source 24 can be aligned with a target 32, and discusses this in col. 5, lines 3-10. Referring to FIG. 3, alternate positions are shown for light source 22 (not shown) and 24. The light source is located adjacent to the rear 48 of cab section 50 of a pickup truck. Colored light beams 18, 20 are directed at a target location 32 at a point, which offers the driver of the tow vehicle 10 an unobstructed view of the target location 32.
U.S. Pat. No. 6,252,497 B1 to Dupay et al. teaches a coupling alignment warning system (CAWS). The invention utilizes electronic circuit to analyze a laser beam directed from the back of the cab to a target onto the trailer 62. In its broadest sense the invention teaches, as shown in FIG. 3 and 4, and discussed in col. 7, line 65 to col. 8, line 10, a rugged enclosure 64 is mounted to a back wall 66 of towing unit 60, above the grease and contaminant area, so that light beam 15 emitted by a laser source 12, is directed generally perpendicular to wall 66 of towing unit 60. Further, rugged enclosure 64 is mounted at a height X defined by a top surface 84 of plate hitch 80 when hitch plate 80 is level and the axis beam emitted from the laser source 12 being mounted in rugged enclosure 64 as best shown in FIG. 3. Retro-reflective target 70 is mounted to a front vertical surface 68 of towed unit 62 at a height corresponding to the height X at which the rugged enclosure is installed. The rugged enclosure is the term employed in the patent to describe a laser mounted in a protective housing.
U.S. Pat. No. 6,592,230 B2 to Steven C. Dupay is a continuation-in-part of U.S. Pat. No. 6,252,497 B1 cited above. Illustrated in FIG. 6 and described in col. 10, lines 8-13 is a laser source 12 mounted in a rugged enclosure 64 aligned so that the laser light beam 15 strikes the center of a retro-reflective target 70.
U.S. Pat. No. 6,793,494 B2 to Varshneya et al. teaches a laser small arms transmitter that can be clamped to a barrel of a weapon such as an M17 rifle. The clamp is shown in FIGS. 1 and 4 and described in col. 5, line 61. Shafts 30 and 32 (FIG. 4) extend downwardly from the projections 24d and 24e. A clamp 34 (FIG. 3) has a pair of apertures 36 and 38 through which the shafts 30 and 32 extend, respectively. A bolt end 40 on the lower end of the shaft prevents the clamp from being completely removed.
While the prior art teaches the use of lasers to determine optical ranging, it fails to teach a relatively inexpensive device that can be quickly fitted to a vehicle, usually a pickup truck, having a fifth wheel hitch that is typically removable. Furthermore, the prior art does not teach a device that can have multiple functions, both on and off the pickup truck, where the functions are all incorporated into one device. Furthermore, the prior art does not teach a device that can be quickly removed from the vehicle, as it, like the fifth wheel, will not advantageously be permanently fixed to the vehicle. What is further needed is a device that is user friendly, and substantially requires little or no training.


A method for discontinuous reception and a device are provided. The method includes: a terminal device determines at least one target discontinuous reception (DRX) indication signal among multiple DRX indication signals and/or a time-frequency resource position occupied by the at least one target DRX indication signal, wherein the at least one target DRX indication signal is used for instructing the terminal device to perform a target behavior in one DRX cycle after receiving the at least one target DRX indication signal; and the terminal device detects a DRX indication signal sent by a network device according to the at least one target DRX indication signal and/or the time-frequency resource position occupied by the at least one target DRX indication signal.

In order to reduce power consumption of a terminal device, a Discontinuous Reception (DRX) transmission mechanism is introduced into a Long Term Evolution (LTE) system. When there is no data transmission, the terminal device may reduce the power consumption by stopping receiving a Physical Downlink Control Channel (PDCCH), thus improving usage time of a battery. A basic mechanism of DRX is to configure one DRX Cycle for a terminal device in a Radio Resource Control (RRC) Connected state. The DRX Cycle consists of On Duration and Opportunity for DRX: during the time of On Duration, the terminal device monitors and receives a PDCCH, while during the time of Opportunity for DRX, the terminal device does not receive a PDCCH to reduce power consumption.
Although a network side configures a terminal device with a DRX Cycle, the terminal device is only scheduled opportunistically during the periodic time of On Duration, and even when a service load of the terminal device is very low, the terminal device is scheduled only in a few DRX cycles. Therefore, it is unnecessary for the terminal device to monitor a PDCCH during the time of On Duration in all DRX Cycles, which will lead to unnecessary power consumption.
Therefore, it is needed to provide a method for discontinuous reception to reduce power consumption of a terminal device.

Method and device for discontinuous reception

GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.