This digital data reproducing apparatus is adapted to prevent reproduction errors of data, wherein a read gate opened when a fixed pattern in a header field for phase locking is detected is kept opened until the data reproduction in a data field is completed, whereby the phase locking in the data field is performed still in the same low-speed mode as when the PLL pull-in is completed in the header field, with the responding ability lowered to defects such as voids or the like in the phase locking pattern area in the data field.. This digital data reproducing apparatus is adapted to prevent reproduction errors, wherein, when a reproduced data in a data field is locked, a read gate is opened after a fixed pattern recorded for phase locking is surely detected, so that the phase locking is started in a high-speed mode, while avoiding erroneous operations of the PLL.

1. Field of the Invention
This invention generally relates to an apparatus for reproducing digital data from an optical disk having a pre-formatted header field and a data field for recording data, and more particularly, to a technique to improve the reproducing efficiency of the data field.
2. Description of Related Art
A recording format of an optical disk is regulated by ISO. FIG. 1 shows a format of one sector in an optical disk of continuous servo type regulated in accordance with the ISO standard. One sector has 746 bytes, the first 52 bytes being a pre-formatted leader field HD (hereinafter, byte will be abbreviated as B). Following the header field HD, there are formatted an ODF field of 1B without guide grooves, a flag field FLAG of 5B indicating whether or not the information is recorded in the subject sector and an ALPC field of 2B for trial recording. A GAP field having 3B is present both in front of and in the rear of the FLAG field. A data field DT of 665B is formatted succeeding the ALPC field.
The format of the 52B header field IID will be depicted. The first 5B is a sector mark SM indicative of the head of the sector. Subsequent to the sector mark SM are sequentially formatted a 12B fixed pattern VFO.sub.1 for pulling in by a PLL, a 1B address mark AM indicating that an address information ID is following, and the address information ID such as a track number, a sector number or the like and an error detection code CRC to indicate an error of the ID information. The ID information and CRC code are 5B in total. Thereafter, two units of 8B fixed pattern VFO.sub.2, a IB address mark AM, a 5B address information ID and error detection code CRC are successively formatted. A postamble PA is recorded 1B at the end of the header field HD. This postamble PA is provided to record several bits overflowing without being modulated when the data is modulated according to the (2,7) modulation rule. Therefore, without the postamble PA, the last 1B may possibly be unable to be modulated.
A 12B fixed pattern VFO.sub.3 is formatted at the head of the data field DT, followed by a 3B sync pattern SYNC and a 650B data area including user data DATA. A 15B BUFFER is provided subsequent to the data area as a margin in order to prevent the header field of a next sector from incorrectly being recorded to, due to deviations in the starting point of recording of the data field or a change in a rotation system.
The fixed patterns VFO.sub.1, VFO.sub.2 and VFO.sub.3 are respectively 12B, 8B and 12B, which are recorded by repetitions of "100" patterns since recording is arranged by a (2,7) modulation code in the whole area except for the sector mark SM, and it is the "100" pattern that generates "1" most frequently by the (2,7) modulation code.
FIG. 2 is a structural block diagram of a conventional digital data reproducing apparatus for reproducing data from an optical disk formatted according to the ISO standard of FIG. 1.
In FIG. 2, disk reproduction data DRD from an optical disk (not shown) is fed to an RG generation circuit 1 which generates a read gate signal RG to determine the reproduction term, and also to a PLL circuit 2 which synchronizes the phases of the DRD and a reproduction clock VCOCK when the read gate generation circuit is open. The phase of a reference clock 2FCK inputted to the PLL circuit 2 is synchronized with the reproduction clock VCOCK when the read gate generation circuit is closed. The reference clock 2FCK is supplied to the RG generation circuit 1, an HDG generation circuit 8 and a lock decision circuit 5 as well. A data read control signal DRC from a microcomputer 7 which will be described later, a data demodulation completion signal DMC from a data demodulation circuit 4, and an address detection completion signal ADC from an address detection circuit 3 are also inputted to the RG generation circuit 1. The RG generation circuit 1 generates the read gate signal RG based on the above-mentioned five input signals. Moreover, a header/data gate signal HDG is given from the HDG generation circuit 8 to the RG generation circuit 1, so that the fixed pattern VFO when the PLL operation is pulled into is distinguished. The header/data gate signal HDG becomes "1" in the header field HD and "0" in the data field DT. Meanwhile, the read gate signal RG is outputted such that it is always "1" in the header field, opening the read gate, whereas it becomes "1" at the reproduction time in the data field DT, thereby opening the read gate. The outputted read gate signal RG is sent to the PLL circuit 2, controlling the timing when the PLL operation is started or stopped. A high/low speed control signal HLC is fed to the PLL circuit 2 from the lock decision circuit 5, and therefore, the pull-in of the PLL operation up to the completion of locking can be switched between high or low speed by the PLL circuit 2. The PLL circuit 2 generates a sync data SD and the reproduction clock VCOCK to the address detection circuit 3, a data demodulation circuit 4 and the lock decision circuit 5.
The address detection circuit 3 detects the address information ID of the header field HD of the optical disk from the sync data SD, with outputting the address detection completion signal ADC. The data demodulation circuit 4 performs (2,7) demodulation on the sync data SD during the timing of the reproduction clock (according to the (2,7) demodulation rule) and outputs the demodulated data to the error correction circuit 6. When the data within one sector is demodulated, the data demodulation circuit also generates and outputs the data demodulation completion signal DMC. The lock decision circuit 5 detects whether or not the PLL circuit 2 locks from the phase difference between the sync data SD of the fixed pattern VFO stored in the header field HD and data field DT and, the reproduction clock VCOCK. When the PLL circuit 2 is in the unlocking state, the circuit 5 generates the high/low speed control signal HLC "0" to the circuit 2, or if the PLL circuit 2 is in the locking state, the circuit 5 generates the high/low speed control signal "1" to the circuit 2. The lock decision circuit 5 has a counter to be used when the PLL circuit 2 is unable to lock the reproduction clock VCOCK to the disk reproduction data DRD. This counter counts the number of reference clocks 2FCK. In the above case where the PLL circuit 2 is unable to lock the reproduction clock VCOCK, when the counter counts a preset number of clocks, the high/low speed control signal HLC of "1" is outputted. The error correction circuit 6 detects an error of the demodulated data, corrects the data with use of an error correction code according to a predetermined operation and then, outputs a reproduction data RD after the correction. At the same time if the correction is impossible, an error correction nullified detection signal ECN indicating the fact is outputted from the error correction circuit 6 to the microcomputer 7. In the case of the optical disk formatted as indicated in FIG. 1, the error correction circuit 6 can correct 8B at the maximum in the coding direction and can correct up to 40B continuously. The microcomputer 7, when receiving the error correction nullified detection signal ECN, outputs the data read control signal DRC to the RG generation circuit 1.
A counter is provided inside the HDG generation circuit 8. When the HDG generation circuit 8 receives the address detection completion signal ADC and reference clock 2FCK, it changes the header/data gate HDG from "1" to "0" at the inputting timing of the address detection completion signal ADC. Upon completion of counting of a predetermined number of clocks at the timing related to the rear end of the data field DT, the circuit 8 changes the header/data gate HDG from "0" to "1". The header field HD is distinguished from the data field DT by the header/data gate HDG.
FIG. 3 is a structural block diagram of the conventional RG generation circuit 1.
The disk reproduction data DRD is applied to a sector mark detection circuit 11 which detects the sector mark SM of the header field HD and to a header field VFO detection circuit 10 which detects fixed patterns VFO.sub.1, VFO.sub.2 of the header field HD. The reference clock 2FCK is given to the sector mark detection circuit 11, header field VFO detection circuit 10, a first counter 12 and a second counter 13.
The sector mark detection circuit 11 samples the disk reproduction data DRD with the timing when the reference clock 2FCK is outputted, detecting a low frequency pattern with which the sector mark SM is recorded (a pattern having continuous "1"s or "0"s), and outputting the sector mark detection signal SMD to the first counter 12 and a latch output to a selector 14b and the second counter 13 described later.
The first counter 12 determines the timing with which the read gate of the header field HD is opened. When the first counter 12 receives the sector mark detection signal SMD from the sector mark detection circuit 11, the counter starts counting the number of reference clocks 2FCK at that tune point. When the counter 12 finishes counting, it generates a first count completion signal CT1 to a selector 14a. To the header field VFO detection circuit 10 is applied the header/data gate signal HDG. The header field VFO detection circuit 10 samples the disk reproduction data DRD with the inputting timing of the reference clock 2FCK and detects the first fixed pattern VFO.sub.1 of the header field HD when the header/data gate signal HDG is "1", with outputting a VFO detection signal VFD to the selector 14a. The selector 14a in turn selects the first count completion signal CT1 or VFO detection signal VFD in accordance with the detecting result of the sector mark SM. In other words, when the sector mark SM is detected, the latch output of the sector mark detection signal SMD is retained "1" until the next sector mark SM is detected, whereby the selector 14a selects the first count completion signal CT1. The selected signal CT1 is sent to a set terminal of a flip-flop 15a. The flip-flop 15a is set with the outputting timing of the signal CT1 thereby turning a read gate signal RG.sub.1 to "1" and opening the read gate.
If the sector mark SM is riot detected and the latch output is "0", the selector 14a selects the VFO detection signal VFD, applying the same to the set terminal of the flip-flop 15a. Accordingly, the flip-flop 15a is set with the detecting timing of the signal VFD, turning the read gate signal RG.sub.1 to "1" and opening the read gate.
In the meantime, the timing when the read gate is closed, namely, when the flip-flop 15a is reset is the detecting timing of the address detection completion signal ADC. The read gate signal RG1 is turned "0" at this timing, thereby closing the read gate.
The second counter 13 counts the number of reference clocks 2FCK to determine the timing when the read gate of the data field DT is opened. A first and a second numbers of clocks are set by the latch output from the sector mark detection circuit 11. The number of clocks is started to be counted with the timing when the address detection completion signal ADC selected by the selector 14b or the sector mark detection signal SMD is inputted.
The selector 14b selects the sector mark detection signal SMD when receiving the general latch output of "1" from the sector mark detection circuit 11. The second counter 13, upon receipt of the sector mark detection signal SMD, starts to count the number of reference clocks 2FCK. When the first number of clocks is completely counted, a second count completion signal CT2 is outputted to a set terminal of a flip-flop 15b from the second counter 13. When the sector mark SM is riot detected (latch output "0"), the second counter 13 starts counting when it receives the address detection completion signal ADC. After the counter 13 finishes counting of the second number of clocks, it generates the second count completion signal CT2. The flip-flop 15b is set with the inputting timing of the second count completion signal CT2, turning a read gate signal RG.sub.2 of the data field DT to "1", with opening the read gate. The flip-flop 15b is reset by the data demodulation completion signal DMC, when the read gate signal RG.sub.2 is turned to "0" and the read gate is closed.
The read gate signal RG.sub.1 outputted from the flip-flop 15a is applied to one input terminal of an OR gate 17, while the read gate signal RG.sub.2 from the flip-flop 15b is given to the other input terminal of the OR gate 17. The output of the OR gate 7 is applied to the PLL circuit 2 as the read gate signal RG. A switch circuit 16 is controlled ON or OFF by the data read control signal DRC from the microcomputer 7. More specifically, the switch circuit 16 is turned ON when the data is read, thereby transmitting the read gate signal RG.sub.2.
Fig, 4 is a structural block diagram of the PLL circuit 2. When the optical disk is rotated, for example, at 24OO rpm, the frequency of the reference clock 2FCK is approximately 15 MHz. After the frequency of the reference clock 2FCK is divided by a 1/3 frequency divider 20 to have the waveform of about 5 MHz similar to the fixed pattern VFO of "100", the reference clock is inputted to one input terminal of a selector 21. The disk reproduction data DRD is inputted to the other input terminal of the selector 21. Moreover, the read gate signal RG is applied to a switch terminal of the selector. When the read gate signal RG is "1" and the read gate is opened, the disk reproduction data DRD is selected. An output of the selector 21 is sent to a phase comparator 22, a reference clock generation circuit 26 and a sync data generation circuit 27. In the phase comparator 22, outputs of the selector 21, the reference clock generation circuit 26 and a feedback output based on the reproduction clock VCOCK from a voltage control oscillator (VCO) 25 are compared, so that a difference signal of the pulse width corresponding to the phase difference is outputted to a charge pump 23. The charge pump 23 drives a current during the time of the pulse width of the difference signal, and charges or discharges a loop filter 24. The charge pump 23 is fed with the high/low speed control signal HLC. The control signal HLC is "0" to bring the high speed pull-in mode until the feedback output is locked to the disk reproduction data DRD. The control signal HLC becomes "1" after the feedback output is locked, thereby starting the low speed pull-in mode. In the high speed mode, the output current of the charge pump 23 is increased and a charging (discharging) time constant of the loop filter is made larger than in the low speed mode, thereby improving the control speed of the PLL operation and shortening the time before the output is locked. Accordingly, the reproduction clock VCOCK is pulled and locked in the disk reproduction data DRD at high speeds immediately after the read gate is opened consequent to a large phase difference. After the clock is locked, the responding property is lowered so that the apparatus is not so much sensitive to defects of the medium or jitters of the disk reproduction data DRD, thus avoiding unlooking.
The loop filter 24 converts and smooth the current signal charged or discharged from the charge pump 23 to a voltage signal, and sends the voltage signal to the voltage control oscillator (VCO) 25. The VCO 25 outputs the reproduction clock VCOCK of the frequency corresponding to the inputted voltage signal. The reproduction clock VCOCK becomes gradually synchronized with the disk reproduction data DRD in phase and finally locked.
The reproduction clock VCOCK is outputted to the address detection circuit 3, data demodulation circuit 4 and lock decision circuit 5. At the same time, the reproduction clock VCOCK is sent to the reference clock generation circuit 26 within the PLL circuit 2. When the read gate is closed, or when the read gate is opened and before locking is completed, the frequency of the reproduction clock VCOCK is divided into three in the reference clock generation circuit 26 and fed back to the phase comparator 22. When the read gate is opened and after locking is finished, the reproduction clock VCOCK within the "1" period of the disk reproduction data DRD is gated to be fed back to the phase comparator 22.
The reproduction clock VCOCK is fed also to the sync data generation circuit 27, where the waveform of the disk reproduction data DRD is shaped so that the approximate center of the pulses of the disk reproduction data DRD becomes a rise edge of the reproduction clock VCOCK. Thereafter, the disk reproduction clock VCOCK is outputted as the sync data SD.
The operation of the conventional digital data reproducing apparatus in the above structure will be depicted hereinafter. FIG. 5 is a timing chart of signal waveforms at each part of the RG generation circuit 1 at the data reproduction time. When the sector mark SM is detected, the sector mark detection signal SMD is changed from "1" to "0" for one cycle of the reference clock 2FCK (FIG. 5(a)). In consequence, the first counter 12 starts counting, and outputs the first count completion signal CT1 "0" (FIG. 5(b)). When the first count completion signal CT1 of "0" is outputted, the read gate signal RG.sub.1 is changed from "0" to "1" (FIG. 5(f)). As the address detection completion signal ADC showing the rear end of the header field HD is turned to "0" (FIG. 5(c)), the flip-flop 15a is reset, and the read gate signal RG.sub.1 becomes "0" from "1", whereby the read gate of the header field HD is closed (FIG. 5(f)). At this time, the header/data gate signal HDG is also changed to "0" from "1" to be closed (FIG. 5(j)). The header/data gate signal HDG is opened a predetermined time later after it is changed to "0".
Subsequently, the flip-flop 15b is set with the timing when the second count completion signal CT2 is outputted from the second counter 13 (FIG. 5(d)), and the read gate signal RG.sub.2 of the data field DT is changed from "0" to "1" (FIG. 5(g)). Accordingly, the read gate of the data field is opened until the data demodulation signal DMC of "0" is outputted (FIG. 5(e)). At this time, the switch 16 is turned ON by the data read control signal DRC of "1" from the microcomputer 7 (FIG. 5(i)), and two read gate signals RG.sub.1 and RG.sub.2 are inputted to the OR gate 17, and the read gate signal RD is outputted to the PLL circuit 2 (FIG. 5(h)).
FIG. 6 is a timing chart when the PLL circuit 2 in the data field DT is driven. A clock 2FCK/3 obtained by dividing the reference signal into three is selected by the selector 21 until the read gate signal RG becomes "1", and fed to the phase comparator 22 (FIG. 6(a)). Therefore, there is no phase difference detected between the clocks 2FCK/3 and VCOCK/3 after being locked. The output CP of the charge pump 23 is "0" and the output LF of the loop filter 24 is a reference value "0". The reference value mentioned above is an output value of the loop filter 24 when the oscillating frequency of the VCO 25 is equal to the frequency of the reference clock 2FCK. The PLL circuit 2 is designed so that the oscillating frequency of the VCO 25 is in the variable range of the frequency of the reference clock 2FCK.
When the read gate signal is turned from "0" to "1" (FIG. 6(d)), the selector 21 selects the disk reproduction data DRD. The phase comparator 22 detects the phase difference of the rise edge between the disk reproduction data DRD and clock VCOCK/3 obtained by dividing the frequency of the reproduction clock VCOCK into three, and outputs the output pulse PC of the pulse width corresponding to the phase difference (FIG. 6(e)). In this case, since the VCOCK/3 advances more in phase than the reproduction data, the charge pump 23 discharges the loop filter 24 by the current signal corresponding to the pulse width of the output pulse PC. The discharging time constant of the charge pump 23 is rendered large at this time because of the high speed pull-in mode. The current signal is converted and smoothed by the loop filter 24 to the voltage signal LF (FIG. 6(f)), and then applied to the VCO 25. The VCO 25 outputs the reproduction clock VCOCK of approximately 15 MHz corresponding to the voltage applied thereto. When the lock decision circuit 5 detects a predetermined number of fixed patterns VFO.sub.3 of "100", the circuit judges that the pull-in of the PLL is completed and the reproduction clock VCOCK is locked to the disk reproduction data DRD, outputting the high/low speed control signal HLC "1" to the charge pump 23. As a result, the low speed pull-in mode is started (FIG. 6(i)).
When it enters the low speed mode (locking is completed), the reproduction clock VCOCK is allowed to pass by the disk reproduction data DRD, and the phases of the reproduction clock VCOCK generated when the disk reproduction data is "1" and the disk reproduction data DRD are compared with each other. The charge pump 23 drives the loop filter by the current signal smaller than that in the high speed mode during the time of the pulse width of the pulse signal PC from the phase comparator 22. Accordingly, the responding property to the pulse signal PC from the phase comparator 22 is deteriorated.
In the conventional digital data reproducing apparatus of the above-described structure, when a part of the fixed pattern VFO.sub.3 for the pull-in of the PLL cannot be detected before the PLL circuit 2 completely locks the reproduction data, that is, in the high-speed pull-in mode due to the adhesion of foreign substances such as dusts or the like onto the fixed pattern VFO.sub.3 resulting in the loss of the reproduction data, all the reproduction outputs are turned "0", and therefore the phase comparator 22 outputs the pulse signal PC for driving the charge pump 23 and having the pulse width to turn the output to "1" until the rise edge of "1" of the fixed pattern VFO.sub.3 is detected. In consequence of this, the output, of the loop filter 24 is rapidly decreased, greatly disturbing the output VCOCK of the VCO 25 and erroneously driving the PLL circuit 2. In such case as above, it may be feared that the reproduction data in the data field be unable to be reproduced.
FIG. 7 is a timing chart showing the operation of the PLL circuit 2 in the data field DT when the fixed pattern VFO.sub.3 is missing. When the disk reproduction data DRD is impossible to be obtained due to the lost of the fixed pattern VFO.sub.3, no signal to be compared is inputted to the phased comparator 22 even though the read gate is opened, and the pulse width of the pulse signal PC of the phase comparator 22 becomes such a length as to enable detection of the disk reproduction data DRD. The charge pump 23 continues to discharge the electric field of the loop filter 24. In this case, since the output LF of the loop filter 24 exceeds the level indicated by a dot and line when it is locked in the disk reproduction data DRD, the frequency of the reproduction clock VCOCK of the VCO 25 is excessively low, thus disturbing the operation of the PLL circuit 2. At this time, although the lock decision circuit 5 forcibly changes the mode to the low speed pull-in mode before the sync pattern SYNC since the counter completes counting of the reference clocks 2FCK, the output LF of the loop filter 24 is beyond the level when the data is locked and therefore, the low speed mode cannot meet to the intention for locking, causing reproduction errors. If the errors are beyond the correction ability of the error correction circuit 6, the data is impossible to be reproduced.
The data in the header field HD can be presumed from the preceding and succeeding sectors even if the data is impossible to be reproduced. However, the data in the data field DT is different for every sector and the content thereof is unable to be detected from the sectors before and after the data field DT. Therefore, when the data is judged unable to be reproduced and reproductions are repeatedly tried, if the fact that the data is unable to be reproduced results from defects of the medium, e.g., voids etc., not from the adhesion of foreign obstacles to the fixed pattern of the data field DT, the repeated reproductions are turned in vain.


A highly active supported bimetallic nanocatalyst and its preparation method is disclosed. During the preparation, using an ion exchange or adsorption resin bearing basic functional groups as the support of the said catalyst, successively introducing the first metal precursor FeCl4− and the second metal precursor (PdCl42−, NiCl42− or CuCl42−) onto the resin through ion exchange process; then under the protection of nitrogen gas, simultaneously reducing the two metals with either NaBH4 or KBH4; washing the resulting material with deoxygenated water and drying it, and the said catalyst is therefore obtained. The supported bimetallic material is characteristic of independent distribution of the two metals within the support. The independently distributed structure of the two metals enhances the catalytic efficiency of the second metal and the catalytic stability.

After Wang and Zhang initially investigated the dechlorination effect of the nanosized zerovalent iron (nZVI) in treatment of organochlorine compounds in 1997 [Wang, C. B. and Zhang, W. X. "Synthesizing nanoscale iron particles for rapid and complete dechlorination of TCE and PCBs." Environmental Science & Technology 31.7 (1997): 154-2156.], the nanosized zerovalent iron, due to its large specific surface area and high reaction activity, has become a research focus in such fields as in situ groundwater remediation and treatment of sewage chloroorganics; in order to effectively reduce agglomeration of nanoparticles and control high head pressure, resin, membrane and activated carbon are adopted as the support for the nanomaterial; namely, the supported nZVI is more widely used in practical application. However, despite the general high activity of the supported nZVI, it presents low efficiency and incompleteness in degrading recalcitrant chloroorganics such as chlorobenzene and polychlorinated biphenyls (PCBs); besides, some products emerged during the degradation process present even higher toxicity (for example, when nZVI is utilized to reduce some organic halogens, the products may bear higher toxicity than the original pollutants and become even more difficult to be further degraded by iron). In order to further improve the reaction activity of the supported nZVI and to extend its service life, researchers introduce a second metal, for example, palladium (Pd), nickel (Ni), copper (Cu) and Platinum (Pt), onto the support; the loaded second metal on the surface of nZVI can engender satisfactory catalytic effect and high efficiency by accelerating the fuel cell reaction (with numerous microfuel cells being formed in the system) that facilitates nZVI losing electrons and lowers down the activation energy. Currently, the conventional method for preparing the supported bimetallic nanocatalyst goes as follows: first, adopting a reductive to reduce the high-valent iron into nanosized zerovalent iron and loading it on the support, then making use of the reducibility of the zerovalent iron and loading the ionic second metal on the support through reduction reaction. The second metal in the bimetallic nanocatalyst prepared with this method is loaded on the surface of the zerovalent iron through deposition process. As the catalytic reduction progresses, the iron on the support corrodes away, and the second metal loaded on the surface of the iron is also washed away, which consequently greatly lowers down the catalytic activity of the composite catalyst [Zhu, B. W. and Lim, T. T. 2007. "Catalytic Reduction of Chlorobenzenes with Pd/Fe Nanoparticles: Reactive Sites, Catalyst Stability, Particle Aging, and Regeneration." Environ. Sci. Technol 41 (2007): 7523-7529.].
In 2009, (China) Nanjing University successfully applied for two patents: "Nanocomposite Resin Loaded with Zerovalent Iron for Catalyst Degradation of Pollutants and the Preparation Method Thereof" (Application Number: 200910028413.X; Publication Number: CN101474560) and "Iron-loaded Bimetallic Nanocomposite Cation Exchange Resin and the Preparation Method Thereof" (Application Number: 200910028414; Publication Number: CN101497051A). The bimetallic materials mentioned in this two patents are prepared as follows: firstly, loading the iron precursor on the support and reducing the precursor with NaBH4 or KBH4; the supported nanosized zerovalent iron is therefore obtained; then, soaking the iron-loaded resin in the saline solution of a second metal so that the reducibility of zerovalent iron can be utilized to load the ionic second metal through reduction reaction. The two metals prepared in this way are interdependently distributed within the support in that the second metal deposits on the surface of the zerovalent iron and the two metals constitute a core-shell structure.
Currently, the conventional method for preparing the supported bimetallic nanocatalyst goes as follows: adopting firstly a reductive to reduce the high-valent iron into nanosized zerovalent iron and loading it on the support, then making use of the reducibility of the zerovalent iron and loading the ionic second metal on the support. The second metal of the bimetallic nanocatalyst prepared with this method is directly loaded on the surface of the zerovalent iron. As the catalytic reduction progresses, the iron on the support corrodes away, and the second metal loaded on the surface of the iron is also washed away, which consequently greatly lowers down the catalytic activity of the composite catalyst.
Up to present, there is not any documentation reporting a method that utilizes the ion exchange effect to load a second metal on the support and to realize independent distribution of the zerovalent iron and the second metal so that the catalytic stability of the material can be improved.

Supported bimetallic nanocomposite catalyst and the preparation method thereof

JIANGSU YONGTAI ENVIRONMENTAL SCIENCE AND TECHNOLOGY CO. LTD.


A method and apparatus for preventing splashing condensate from activating the safety pressure switch in a multi-poise condensing furnace includes removing the existing tubing connected to upper and lower pressure taps provided on the collector box of the furnace. T connectors and secondary tubing are then fastened to each of the pressure taps and the existing tubing reconnected to a corresponding T connector.

1. Field of the Invention
This invention relates in general to multi-poise condensing furnaces and, in particular, to a method and apparatus for preventing splashing condensate in the collector box of a multi-poise condensing furnace from activating a safety pressure switch connected to the collector box.
2. Discussion of the Background Art
The residential heating industry has benefitted with the advent of multi-poise condensing gas furnaces. These furnaces typically include a primary heat exchanger positioned adjacent a secondary or condensing heat exchanger. A blower provides circulating air flow over the heat exchangers to produce heated air that may be directed and channeled to a desired location. The design of the multi-poise condensing furnace is optimized so that the furnace may be installed with any one of four different physical orientations while being capable of operating properly and equally efficiently in any orientation. These four possible orientations include directing the circulating heated air exiting the furnace in either an upflow, downflow, horizontal-left, or horizontal-right direction.
Both the primary heat exchanger and the condensing heat exchanger include cells with channels formed therein to direct the flow of flue gas produced by combustion. These cells are positioned side by side in a parallel manner and are provided with a predetermined spacing to allow the blower air to flow around the cells. The blower air is heated by convection as it moves over the cells.
Gas is provided to the furnace by a gas manifold. Manifold orifices direct the gas into burners contained in a burner box and the gas is ignited as it exits the burners. The heated flue gas produced by combustion is then directed into the primary heat exchanger cells and induced to move therethrough. The channels provided in the primary heat exchanger cells eventually terminate at discharge ports. The discharge ports of the primary heat exchanger are typically aligned and secured in a first sheet metal panel.
The condensing heat exchanger of the multi-poise furnace is configured in a similar manner. A series of side by side condensing cells is provided. Each of these condensing cells has an inlet port for receiving the flue gas discharged from the primary heat exchanger and a pair of discharge ports. One of the pair of discharge ports being positioned below the other along the vertical when the furnace is installed with either the upflow or downflow orientation. When the furnace is installed with either a horizontal-left or horizontal-right flow orientation, the two discharge ports of each condensing cell are positioned side by side along the horizontal.
Proper functioning of condensing furnaces requires that the water vapor existing in the combustion products carried in the flue gas is condensed only in the condensing heat exchanger cells and not elsewhere within the furnace. Each condensing heat exchanger cell is designed to allow proper drainage out of at least one of the discharge ports in any one of the four possible installation orientations. In the upflow or downflow installations, the lower of the two discharge ports will function to drain the condensate formed within each cell, while both discharge ports of a given pair will function to drain the condensate from a respective cell when the furnace is installed with either the right-horizontal or left-horizontal flow orientations.
The collector box is positioned on the discharge side of the condensing heat exchanger. As noted above, condensate formed in the condensing cells will drain into the collector box. The collector box is provided with two drain taps so that the collector box may be properly drained of condensate. The drain taps are positioned in diagonally opposed corners of the rectangular front face of the box. In any one of the four possible installation orientations, one of the two drain taps will be positioned in the lower portion of the collector. Upon installation, this lower drain tap is connected by tubing to suitable drain piping including a trap. As the condensate level increases during the operation of the furnace, it will eventually reach the level of the lower drain tap and be removed through the tubing and trap into the drain.
During operating of the multi-poise condensing furnace, pressure within the channels of the heat exchanger cells and the collector box is increased above ambient by operation of an inducer mounted on the front of the collector box that induces flow of flue gas through the cells. Pressure within the channels and the box is also contributed to by combustion occurring at the inlet side of the primary heat exchanger.
A pressure switch is provided in the multi-poise condensing furnace to provide an added level of safety in operation of the furnace. This safety pressure switch is connected by tubing to one of two pressure taps provided on the front side of the collector box. The location of each of these pressure taps is proximate to a corresponding drain tap positioned along an arc between the horizontal and vertical of the ninety degree angle forming each of the diagonally opposed corners of the collector box. This location of the pressure taps is optimum because it places a pressure tap just slightly above the corresponding lower drain tap in any one of the four possible installation configurations. This particular position of the pressure tap is necessary so as to allow the safety switch to be activated shortly after the drain first becomes blocked.
The condensate drain piping or drain could become blocked by any one of a number of possible causes. In this blocked condition, condensate would continue to build up in the collector box as well as in the condensing heat exchanger in the event the furnace were to continue to operate. To avoid this possibility, a safety pressure switch, as described above, is connected to the pressure tap proximate to the lower drain tap. Thus, when the condensate level in the box raises above the drain tap because of some blockage, the condensate will shortly thereafter also block the pressure tap connected to the safety switch. The safety switch will detect this pressure drop in the line and then prevent further operation of the furnace until the blockage is cleared and proper drainage resumes.
In the typical installation, the upper pressure tap is fluidly connected to the upstream side of the drain trap. The pressure in the collector box is thus used to assist in forcing a steady flow of condensate through the drain piping to aid in preventing blockage in the drain. In some installations, it has been observed that splashing of condensate within the collector box near the lower pressure tap connected to the safety pressure switch will repeatedly activate and deactivate the switch thus turning the furnace off and on even though the furnace is experiencing proper drainage from the box. This nuisance splashing may be caused by vibration of the operating furnace or any one of a number of possible causes.

Method and apparatus for preventing splashing condensate from activating safety pressure switch in multi-poise condensing furnace


A light source has a rear glass substrate and a front glass substrate having a plate surface disposed in facing relation to a principal surface of the rear glass substrate. The plate surface of the front glass substrate is coated with a phosphor. A two-dimensional array of electron emitters is disposed on the principal surface of the rear glass substrate. A space defined between the rear glass substrate and the front glass substrate is filled with a gas. The gas may be an Hg (mercury) gas or an Xe (xenon) gas.

1. Field of the Invention
The present invention relates to a light source (including a planar light source) comprising electron emitters each having an upper electrode and a lower electrode that are disposed in an emitter.
2. Description of the Related Art
Recently, electron emitters having a drive electrode and a common electrode have been finding use in various applications such as field emission displays (FEDs) and backlight units. In an FED, a plurality of electron emitters are arranged in a two-dimensional array, and a plurality of phosphors are positioned in association with the respective electron emitters with a predetermined gap left therebetween.
Conventional electron emitters are disclosed in Japanese Laid-Open Patent Publication No. 1-311533, Japanese Laid-Open Patent Publication No. 7-147131, Japanese Laid-Open Patent Publication No. 2000-285801, Japanese Patent Publication No. 46-20944, and Japanese Patent Publication No. 44-26125, for example. All of these disclosed electron emitters are disadvantageous in that since no dielectric body is employed in the emitter, a forming process or a micromachining process is required between facing electrodes, a high voltage needs to be applied to emit electrons, and a panel fabrication process is complex and entails a high panel fabrication cost.
It has been considered to make an emitter of a dielectric material. However, various theories about the emission of electrons from a dielectric material have been presented in the documents: Yasuoka and Ishii, "Pulsed Electron Source Using a Ferroelectric Cathode", OYO BUTURI (A monthly publication of The Japan Society of Applied Physics), Vol. 68, No. 5, pp. 546–550 (1999), and Puchkarev, Victor F. and Mesyats, Gennady A., "On the Mechanism of Emission from the Ferroelectric Ceramic Cathode", Journal of Applied Physics, Vol. 78, No. 9, 1 November 1995, pp. 5633–5637.
In the conventional electron emitters described above, electrons that are restrained on the surface of a dielectric body, the interface between the dielectric body and an upper electrode, and the defective level in the dielectric body are discharged by an inversion of the polarization of the dielectric body. That is, if the polarization of the dielectric body is inverted, then the amount of emitted electrons is substantially constant, not dependent on the voltage level of an applied voltage pulse.
However, the conventional electron emitters are problematic in that the electron emission is not stable and can only be performed several tens of thousands times at most, and the electron emitters are not practical when used as light sources, for example.

This patent is subject to a terminal disclaimer.


A method of reducing an effective channel length of a lightly doped drain transistor (50), includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and implanting a drain region (58) of the substrate (56) with a sub-amorphous large tilt angle implant to thereby supply interstitials (62) at a location under the gate oxide (54). The method also includes forming a lightly doped drain extension region (66) in the drain region (58) of the substrate (56) and forming a drain (70) in the drain region (58) and forming a source extension region (67) and a source (72) in a source region (60) of the substrate (56). Lastly, the method includes thermally treating the substrate (56), wherein the interstitials (62) enhance a lateral diffusion (84) under the gate oxide (54) without substantially impacting a vertical diffusion (86) of the extension regions (66, 67), thereby reducing the effective channel length without an increase in a junction depth of the drain (70) and the drain extension region (66) or the source (72) and the source extension region (67).

Transistor devices make up one of the integral components of today's integrated circuits. Consequently, a reduction in the size of transistors (often called "scaling") is constantly being pursued. Prior art FIG. 1 is a fragmentary cross section diagram illustrating a conventional MOS type transistor 10. The transistor 10 consists of a conductive gate region 12 overlying a thin gate oxide 14 which overlies a substrate 16. The gate 12 and the gate oxide 14 are disposed between a drain region 18 and a source region 20 which are formed in the substrate 16 having a channel region 22 located therebetween which underlies the gate 12 and the gate oxide 14.
As the conventional transistor 10 is scaled into the sub-micron range to reduce its dimensions and thereby improve the transistor packing density on a chip, the transistor 10 begins to experience hot-carrier effects, as illustrated in prior art FIG. 2. These undesirable hot-carrier effects become more evident when the transistor 10 is scaled while maintaining the supply voltage constant or when the supply voltage is not reduced as rapidly as the structural features of the transistor.
The hot-carrier effects are due to an increase in the electrical field within the channel region 22. The increased electric field causes electrons in an inversion layer 26 to be accelerated (or "heated") to an extent that several different undesirable phenomena occur. As illustrated in prior art FIG. 2, the hot-carrier effects can include charge injection, substrate current and electron injection into the gate oxide 14. Perhaps the most crucial hot-carrier effect is the charge injection into the gate oxide 14 which damages the thin oxide and leads to a time-dependent degradation of various transistor characteristics such as the threshold voltage (V.sub.T), the linear transconductance (g.sub.m) and the saturation current (I.sub.DSAT).
One prior art solution which reduces the undesired hot-carrier effects of traditional transistor structures is the lightly doped drain (LDD) transistor 30, which is illustrated in prior art FIG. 3. The LDD transistor 30 includes the gate 12 and the gate oxide 14 formed in a conventional manner, wherein a lightly doped drain extension region 32 is formed adjacent to the drain region 18 between the drain region 18 and the channel 22. The lightly doped drain extension region 32 typically reduces the electric field near the channel region 22 by about 30-40 percent and thus the hot-carrier reliability of the transistor is greatly improved. The extension region 32 reduces the electric field by effectively dropping a portion of the drain voltage across the extension region 32.
As transistor designers continue to scale down the transistor device dimensions, the junction depths of the source and drain regions (as well as the lightly doped drain extension region) also need to be reduced (i.e., make the junctions more shallow). Junction depths must be reduced in conjunction with scaling in order to prevent short channel transistor effects such as punchthrough and threshold voltage shift. One conventional approach to reducing the junction depth is to reduce the implant energy used to form the junctions and reduce the diffusion of the junctions in the vertical direction. Reducing the effective channel length (to get higher drive current) using the conventional approach by enhanced lateral diffusion would be accompanied by deeper junctions leading to degradation of short channel effects. Thus, using the conventional approach for a fixed gate size, the channel length cannot be reduced using the prior art method since it would result in deeper junctions. A smaller channel length would, however, be a benefit as it would help to improve the drive current. Consequently, designers have been faced with the design trade-off of reducing junction depths (to reduce short channel effects) and having longer channel lengths (leading to reduced drive current) as the transistor size is reduced.
It is an object of the present invention to overcome the limitation of the prior art by providing a decrease in the effective channel length to thereby provide for a reduced transistor sizing without experiencing transistor degradation due to short channel effects associated with deeper junctions. In other words, it is an object of the present invention to overcome the limitation posed by the conventional design methods whereby the channel length for a given gate size cannot be reduced by providing deeper junctions, as that would lead to degradation of transistor performance.

Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion


A data transmission apparatus capable of transmitting input image data of a plurality of pages as one or more image files is disclosed. It is designated which page or pages are to be put into each image file. Such designation may be specified by a user. One or more image files are created in accordance with the designation. The created image files are transmitted, for example, using an E-mail or File Transfer Protocol.

1. Field of the Invention
The present invention relates generally to a data transmission system for transmitting input image data to a designated address, and more specifically to a data transmission system for transmitting multiple pages of image data in one or more image files.
2. Description of the Related Art
In conventional data transmission systems, when transmitting an input image, such as an image obtained by reading an original using a scanner, an image received from the outside, or the like, to a designated address, it is possible to convert the image into a designated image file format using a preset image conversion function, and transmit an image after conversion. For example, when transmitting images of a plurality of pages obtained by reading an original including a plurality of pages using a scanner, an image of each page is transmitted after being converted into an image file of an appropriate file format designated by a user. At that time, if the designated file format can have a plurality of pages within one file, all pages of the original are transmitted as one file. File formats capable of having a plurality of pages in one file include, for example, the TIFF (Tag Image File Format), the PDF (Portable Document Format), and the like.
For example, Japanese Patent Application Laid-Open (Kokai) No. 9-163064 (1997) describes an approach of outputting images of a plurality of pages obtained by reading an original by converting the images into one TIFF file.
If a selected file format can have a plurality of pages in one file as described above, since images of all read pages are transmitted as one file at a single transmission operation, no problem arises if this satisfies the user's intention. However, for example, such a transmission operation cannot deal with a case in which it is intended to transmit images on respective pages to the same address as separate files at a single processing. Accordingly, when transmitting images on respective pages to the same address as individual files, the user must form a plurality of files by dividing an original with a desired unit, and repeat the operation of transmitting each of the files to the same address, resulting in a troublesome operation.

Image transmission apparatus which transmits image data as an image file or a plurality of image files


Method and apparatus for controlling an epilation procedure in which a removal process is adaptively controlled for optimum removal prevention of scarring and minimizing sensation, and profiling RF power supplied as an inverse square of measured impedance based on a normalizing impedance.

1. Field of the Invention
This invention is an improvement over the invention disclosed and claimed in U.S. Pat. No. 4,550,728 to Runyon and Hower, and also relates to a high frequency probe type epilator.
This invention is concerned with an epilation procedure, and a control apparatus and a probeholder used in connection with the epilation procedure.
More particularly, the invention is concerned with precise control of intensity (power level) and timing and dynamic power control based on impedance variation. Variations in the depth of insertion and hair characteristics impact the initial impedance, and the application of power to the follicle results in dynamic impedance changes. The impedance is measured during the pulse and the power is compensated to minimize skin reaction and sensation to the patient.
The invention is also concerned with a novel probeholder.
2. Description of the Prior Act
The prior U.S. Pat. No. 4,550,728, while it also relates to an RF epilator procedure and is also concerned with safety controls, relied on open loop electrical circuit characteristics to select power setting. This resulted in non-linear power variations, as well as, uncontrolled response to variations in impedance during the pulse. The process of RF epilation is performed by inserting an insulated bulbous tipped probe into a follicle and applying a controlled burst of RF energy to the probe. The probe tip concentrates the energy at the germinative portion of the hair (dermal papilla) destroying the follicle's capacity to regenerate itself. Operators, based on their experience, select the timing and intensity of the RF power pulse to be applied. The actual pulse length will not exceed these settings. During the pulse the power delivered is based on the intensity setting selected by the operator as impacted by the inherent response of the circuit to variations of the impedance reflected to the power amplifier output. The impedance as seen at the probe tip varies throughout the duration as a function of skin characteristics, hair size and depth of penetration. During the pulse dynamic changes in the impedance occur as energy is applied to the tissue.
With the prior heretofore known probeholders, an operator using the probeholder became part of the RF load. Different operators presented a different load impedance to the circuit based on their own individual treatment technique. Specifically, as presently understood, the prior heretofore probeholder terminated the coaxial cable center conductor into a large brass tip which accepted the probe. The shield terminated where the center conductor connected to the end of the probeholder allowing RF energy to be coupled to the operator, as well as the patient.


Resistance of randomly dispersed and oxygen-starved lung tumor cells to chemo- and radiotherapy constitutes the vast majority recurrences and death from lung cancer. We use sickle cells derived from humans with sickle cell anemia to target oxygen-deprived tumor cells that persist and multiply after conventional treatment. Transfused sickle cells selectively occluded tumor microvessels and shut down blood flow to these oxygen-deprived pockets leading to tumor cell death and complete shrinkage of aggressive lung tumors. Combining the sickle cells with a vascular disrupting agents and radiation injure and narrow tumor blood vessels, amplified the scale of sickle cell-induced blood vessel closure and tumor cell killing. The strength of the tumor killing produced by this combination exceeded that of either agent alone or combined with conventional anti-angiogenics, chemotherapy or radiation. Combinatorial sickle cells-Combretastatin treatment thereby constitutes a major advance toward eradicating treatment-resistant tumor cells and reducing the frequency of lung cancer recurrence.

Hypoxic tumor niches and their underlying molecular axes have been a chief targets of molecular cancer therapeutics. Of paramount concern to investigators is that such niches are associated with resistance to conventional cancer treatment and their persistence is a major cause of tumor recurrence (Wilson W R, Hay M P. Nat Rev Cancer. 2011; 11(6):393-410). Under hypoxic conditions within tumors, conserved oxygen sensors activate hypoxia-inducible transcription factors and pro-angiogenic signals (Kerbel R S. N Engl J Med. 2008; 358(19):2039-2049.). The latter induce a disordered network of blood vessels resulting in cyclic or chronic deoxygenation (Pries A R, Nat Rev Cancer. 2010; 10(8):587-593). As tumor growth outscales neoangiogenesis, tumor cells rendered chronically hypoxic may survive, proliferate and become treatment resistant (Brunelle J K, Chandel N S, g Drug Resist Updat. 2010; 13(1-2):16-28).
The failure of conventional treatment has prompted a universal search for conceptually new tools and strategies to eradicate these treatment-resistant hypoxic tumor cell subpopulations. Anti-angiogenic agents that limit the tumor blood supply to these niches by targeting receptors on embryonic blood vessels usually lead to tumor regrowth by activation of alternate synthetic pathways, hypoxia inducible factors or tumor cells that evade the effect of therapy (Abdollahi A, Folkman J Drug Resist Updat. 2010; 13(1-2):16-28). Likewise, polymeric nanocarriers occlude only a fraction of mature tumor blood vessels and in the absence of hypoxia sensing systems fail to access oxygen deprived regions (Vasuri F, et al. World J Gastroenterol. 2014; 20(37):13538-13545). We therefore turned to the sickle erythrocyte (SSRBC) derived from a mutated erythroid lineage. These cells circulate freely and possess a unique hypoxia-sensing functionality which becomes operative under severely hypoxic conditions in low velocity microvessels (Manwani D, Frenette P S Blood. 2013; 122(24):3892-3898). SSRBCs are trapped in these vessels leading to HbS desaturation, polymerization and formation of tetrameric spicules rendering them rigid, adhesive and prone to vaso-occlusive aggregation (Ballas S K, Mohandas N. Microcirculation. 2004; 11(2):209-225). Intravital microscopy observations show that infused SSRBCs home to established tumor, form aggregates in tumor vessels and induce focal vessel closure. Together with pro-oxidants or oncogenic virus, SSRBCs also produce a therapeutic tumor growth delay but fail to produce complete tumor regressions (Terman D S, et al. PLoS One. 2013; 8(1):e52543).
In search of agents that could increase the efficiency and scale of SSRBC-mediated tumor killing, we turned to the vascular disruptant Combretastatin A4 (AVE8062 or CA-4). The latter is derived from the South African bush willow tree, Combretum caffrum. It binds to tumor endothelial β-tubulin subunits, inhibits microtubule formation and induces cytoskeletal alterations leading to vascular collapse, blood stasis, focal hypoxia, and ischemic tumor cell necrosis (Tozer G M et al., Nat Rev Cancer. 2005; 5(6):423-435). Despite these potent effects, CA-4 and its diphosphate derivative fail to eliminate viable tumor cells at the tumor rim resulting in rapid tumor regrowth (Siemann D W Cancer Treatment Rev. 2011; 37(1):63-74). Combining CA-4 with other therapeutics, such as radiation, cytotoxics, anti-angiogenics and biologics failed to the alleviate the peripheral tumor regrowth in murine tumor models (Siemann D W et al., Anticancer Res. 2008; 28(4B):2027-2031; Clémenson C et al., Crit Rev Oncol Hematol. 2013; 86(2):143-160)).
We hypothesized that CA-4's selective induction of tumor endothelial cell injury, blood stagnation, hypoxia could create a microvascular milieu wherein SSRBCs could efficiently deoxygenate, form microaggregates and induce a broad scale of tumor vessel closure and infarction. Such massive vaso-occlusion-infarction could not only encompass hypoxic niches, but also the treatment-resistant tumor rim. To this end, we introduce hypoxia-reactive SSRBCs as a new therapeutic whose physiologic adaptation to CA-4-induced tumor blood stasis and microvascular hypoxia results in an unprecedented scale of tumor microvessel closure and infarction that obliterates treatment-resistant hypoxic niches and the tumor rim. The SSRBCs-CA-4 regimen produced complete tumor regressions whereas each therapeutic alone or combined with conventional anti-angiogenics, cytotoxics or radiation resulted in tumor progression. Collectively, these findings provide conceptually new tools, mechanisms and strategies whereby drug-induced tumor endothelial remodeling licenses broad propagation of SSRBC-mediated vessel closure culminating in tumor eradication.

Compositions and methods for treatment of cancer


An apparatus is disclosed for an improved device for covering an aperture disposed on a horizontal surface. The cover has sidewalls, a top surface, and a lip which defines a cover opening within a sidewall. The improvement comprises a first and a second guide rail extending from the cover and disposed on opposed first and second sides of the cover opening. A slot is defined in the cover and disposed along a third side of the cover opening. A frame defines a screened window and includes fastener projections which extend outwardly from the frame. The frame is inserted within the slot with a first and a second side of the frame being guided by the first and second opposed guide rails. The fastener projections engage the lip of the cover opening for retaining the frame and the screened window within the cover opening.

1. Field of the Invention
This invention relates to a device for covering an aperture on a horizontal surface, and more specifically relates to a device for covering an air vent on a motor home or similar vehicle.
2. Information Disclosure Statement
Recreational and other vehicles contain air vent openings to facilitate the entry of fresh air into the vehicle. These openings are typically located on a top horizontal surface of the vehicle and have air vent caps overlying the air vent openings. The air vent caps generally pivot about a hinge on the front of the air vent cap to open toward the rear of the vehicle for venting the vehicle. The air vent cap allows for the entry of fresh air into the vehicle and allows for the escape of gasses from the vehicle. Unfortunately, these air vent openings also allow for the entry into the vehicle of liquid and solid matter along with the fresh air. To overcome this problem, the prior art developed air vent covers for mounting over the air vent open and the air vent cap to obstruct the flow of liquids and solids while allowing the flow of fresh air and gases between the outside and the interior of the vehicle.
The prior art discloses a variety of air vent cover improvements. In general, the prior art vent covers had sidewalls for supporting a top to provide sufficient clearance for the air vent cap to pivot into an open position. The top was frequently tapered toward the front to provide for a more aerodynamic surface. A grill was typically mounted in a rearward facing sidewall with the grill having louvers to deflect foreign matter such as rain from entering the interior of the air vent cover. A screen was secured to cover the grill to prevent small foreign objects such as insects, dust and the like from entering the interior of the air vent cover. The air vent cover was often of a one-piece construction being molded from plastic or other durable and weather resistant materials. The air vent cover was affixed to the roof of the vehicle by mechanical means such as a bracket molded into the air vent cover.
These air vent covers greatly enhanced the art of providing protection of the air vent for the interior of the vehicle from outside elements. However, the air vent covers of the prior art suffer from various shortcomings. The screen secured to the grill of the air vent cover was one of the more fragile components of the air vent cover thus requiring periodic maintenance. After the screen became dirty because of screen-sized particulate matter and insects striking and becoming lodged in the screen, it was necessary to periodically clean and repair the screen.
Repairing the screen in place involved climbing on top of the vehicle and making repairs in an inconvenient position. Moreover, since the screen was internal to the air vent cover, the grill substantially obscured the screen making the cleaning of the screen from the outside difficult or impossible. The grill inhibited the scrubbing or brushing of the screen from the outside. Also, spraying the screen with a hose from the outside is less effective than from the inside, since most of the particles were normally lodged on the outside of the screen.
Therefore the repair or cleaning of the screen was not a convenient task. A person must climb on top of the vehicle and the entire cover must be removed in order to work on the screen. During such removal, the air vent opening is exposed to the environment. In addition, the use of tools was normally required to complete the task. Another shortcoming of the prior art air vent cover was the failure to effectively prevent precipitation from being driven through the grill into the air vent and thus into the vehicle.
Therefore, it is an object of the present invention to provide an improved device for covering an air vent on a vehicle comprising a screen which can be removed without the need for climbing on top of the vehicle.
Another object of this invention is to provide an improved device for covering an air vent on a vehicle comprising a screen which can be removed from the inside of the vehicle.
Another object of this invention is to provide an improved device for covering an air vent on a vehicle comprising a screen which can be installed from the inside of the vehicle.
Another object of this invention is to provide an improved device for covering an air vent on a vehicle comprising a screen which can be removed and installed by hand without the need for tools.
Another object of this invention is to provide an improved device for covering an air vent on a vehicle comprising a screen which can be easily removed and reinstalled in areas of restricted movement or limited visibility.
Another object of this invention is to provide an improved device for covering an air vent on a vehicle comprising a screen which can be removed and washed from the inside of the vehicle.
Another object of this invention is to provide an improved device for covering an air vent on a vehicle comprising a grill which can effectively inhibit precipitation from being driven through the grill of the air vent cover into the vehicle.
The foregoing has outlined some of the more pertinent objects of the present invention. These objects should be construed as being merely illustrative of some of the more prominent features and applications of the invention. Many other beneficial results can be obtained by applying the disclosed invention in a different manner or modifying the invention within the scope of the invention. Accordingly other objects in a full understanding of the invention may be had by referring to the summary of the invention, the detailed description describing the preferred embodiment in addition to the scope of the invention defined by the claims taken in conjunction with the accompanying drawings.


A network connector includes an electrically insulative housing accommodating an output circuit board and an input circuit board, output terminals and input terminals respectively and electrically bonded to the output circuit board and the input circuit board, a filter capacitor electrically connected between the input circuit board and the output circuit board, an electrically insulative partition block mounted in the electrically insulative housing to keep the filter capacitor away from the input circuit board and the output circuit board and to avoid accidental electrical sparks between the input terminals and the filter capacitor, and a filter module having filter coils electrically bonded to the surface contacts at the output circuit board and the input circuit board by surface mount technology.

1. Field of the Invention
The present invention relates to network technology and more particularly, to a network connector, which has the lead wires of filter coils of a filter module thereof respectively bonded to respective surface contacts at an input circuit board and an output circuit board by surface mount technology, minimizing contact points, simplifying the manufacturing process, lowering the manufacturing cost and enhancing the electrical characteristics.
2. Description of the Related Art
Nowadays, following fast development of computer technology, computer data transmission speed has been greatly improved. Moreover, as network communication technologies develop rapidly and vigorously, it is possible for the people to transmit data, to hold a video conference, to book tickets, to play on-line games, and to inquire information and different application procedures through the internet. Nowadays, many people use the internet to achieve different works. In consequence, many kinds of network connectors have been created as communication means between a computer and an external network. Regular network connectors, for example, RJ-45 connectors, are commonly used for digital communication. During the use of a network connector, the problem of signal interference due to electromagnetic effect must be taken into account. The interference of noises may come from two sources, i.e., the interference of surrounding electromagnetic waves and the interference of internal noises. A network connector may produce high frequency waves to interfere with surrounding electronic devices. Further, the transmitting signal in a network connector may be interfered with noises produced by the external transmission line. In order to eliminate interference, a network connector may have a metal shield surrounded on the outside for protection against external electromagnetic waves and a filter module installed therein to eliminate internal noises, maintaining the quality of the signal being transmitted to the host for data processing.
Further, the cable of a network system may be directly arranged on the outside of the building and exposed to the weather. High voltage generated by thunder or lightning may be transmitted through the cable to the host computer or server of the network system, causing the host computer or server to burn out. When the electronic devices in an electronic apparatus are attacked by lightning surge, the electronic apparatus may fail, or may be damaged permanently. Therefore, network connectors commonly have high voltage capacitor and surge protector means installed therein for protection against high voltage surge.
FIGS. 7 and 8 illustrate a network connector according to the prior art. According to this prior art design, the network connector comprises a base block A, two sets of terminals A1; A4 arranged on left and right sides of the base block A, an accommodation space A0 defined in the base block A between the terminals A1; A4, a plurality of filter members B accommodated in the accommodation space A0, a circuit board A2 attached to the accommodation space A0 and having metal contacts A21 respectively bonded with the terminals A1, an electrically insulative housing A3 attached to the base block A, a back panel A31 attached to the rear side of the electrically insulative housing A3, a plurality of LEDs A32 mounted in the electrically insulative housing A3 and having lead-out wires A321 inserted through the back panel A31 to the outside, and a metal shield C surrounding the electrically insulative housing A3, the base block A and the back panel A31. The metal shield C defines an insertion hole C1 for insertion of an external electrical connector (electrical plug). The filter members B include one filter capacitor B2 and a plurality of filter coils B1. The filter capacitor B2 has two end pins B21 respectively extended from the two opposite ends thereof. One end pin B21 is bonded to the metal contacts A21 of the circuit board A2. The other end pin B21 is extended through the back panel A31 to the outside and connected to the metal shield C. The filter coils B1 of the filter members B are respectively wound round head ends A11 of the terminals A1. Further, the terminals A1 that are arranged on the left side of the base block A are positioned in the insertion hole C1 for the contact of the terminals of the inserted external electrical connector (electrical plug).
The assembly process of the aforesaid prior art network connector is complicated. During connection between the filter coils B1 and the terminals A1, the filter coils B1 must be respectively wound round the head ends A11 of the terminals A1, wasting much time and labor. Further, after bonding of the end pin B21 of the filter capacitor B2 and a plurality of filter coils B1 to the metal contacts A21 of the circuit board A2, no any isolation means is set between the end pin B21 of the filter capacitor B2 and the terminals A4. When the network connector receives an external high voltage, electrical sparks may be produced between the end pin B21 of the filter capacitor B2 and the terminals A4. Further, after extended through the back panel A31 to the outside of the electrically insulative housing A3, the end pin B21 of the filter capacitor B2 and the lead-out wires A321 of the LEDs A32 are not well shielded and isolated, and electrical sparks may be produced between the end pin B21 of the filter capacitor B2 and the lead-out wires A321 of the LEDs A32 accidentally. Therefore, the aforesaid prior art network connector has the drawbacks of complicated structure, high manufacturing cost and low voltage withstand strength.
Therefore, it is desirable to provide a network connector that eliminates the aforesaid problems.


An RTP payload format for VC-1 is described. The RTP payload format accommodates an RTP payload that can include one or more Access Units (AUs). An Access Unit can provide a complete frame of VC-1 information. Alternatively, a frame of VC-1 information can be fragmented among multiple Access Units. Each Access Unit includes an Access Unit header and an Access Unit payload. The RTP payload format incorporates various provisions for improving the efficiency and robustness in the processing of the VC-1 information, enabled, in part, by control information conveyed by the respective Access Unit headers of the Access Units.

Real-Time Transport Protocol (RTP) is a well known protocol for delivering media information (audio and video) over an IP network. The RTP protocol is described in fall in Schulzrinne et al., "RTP: A Transport Protocol for Real-Time Applications," STD 64, RFC 3550, July 2003. As broadly indicated in FIG. 1, an RTP packet 100 includes an RTP packet header 102 and an RTP payload 104. The RTP header 102 includes various well-known fields of metadata enumerated in FIG. 1. A device which receives the RTP packet uses the information in the RTP header 102 to govern the processing of the information within the payload 104.
RTP requires a separate so-called payload format for each codec. Well known codecs for processing media information include MPEG-2, H.264/MPEG-4 AVC, MP3, and so forth. The payload format specifies the precise manner in which RTP is used to encapsulate the codec data. In other words, a payload format is essentially a mapping specification, which describes in detail how the video or audio data is arranged inside the RTP packets. Each codec has unique complexities. Thus, the task of developing an RTP payload format for a codec raises a number of unique challenges.
The subject matter set forth herein describes an RTP payload format for the Video Codec 1 (VC-1) video codec. VC-1 has broad applicability, being suitable for low bit rate Internet streaming applications to HDTV broadcast and Digital Cinema applications with nearly lossless coding. More specifically, for instance, VC-1 is widely used for downloading and streaming of movies on the Internet, in the form of Windows Media Video 9 (WMV-9). VC-1 has also been adopted as a mandatory compression format for various high-definition DVD formats.
The VC-1 codec is described in "Proposed SMPTE Standard for Television: VC-1 Compressed Video Bitstream Format and Decoding Process," The Society of Motion Picture and Television Engineers, White Plains, N.Y., Aug. 23, 2005 (henceforth referred to as simply SMPTE 421M). The SMPTE 421M specification is incorporated by reference herein in its entirety.


An embodiment of the present invention provides a method of mitigating third order inter-modulation distortion in electronic circuits, comprising estimating an IP3 of the circuits using an empirical equation which includes at least one or more of the factors IP3˜IP3o−20 log Q+10 log F+10 log C−17.3 log k dBm and optimizing one or more of the factors such that the third order inter-modulation distortion is mitigated.

While the problem of calculating or measuring third order intermodulation distortion has been well studied and many references to the successful determination of such distortion can be found, the need exists for explicit design techniques that enable the selection of tunable capacitors and the design of circuit parameters for desired third order intermodulation distortion levels. In particular, a strong need exists for a method and apparatus capable of mitigating third order inter-modulation distortion in electronic circuits and systems incorporating voltage tunable capacitors

Method and apparatus capable of mitigating third order inter-modulation distortion in electronic circuits


An example lid assembly can include a lid and a slider. The lid can include a wall defining a recess. The slider can be configured to slide in the recess and can be configured to move between a closed position where the slider covers the opening to aid in preventing spilling of contents of the container and an opened position where the slider uncovers the opening such that the contents of the container can be consumed. The slider can be configured to be removable from the lid and can be replaced back on the lid. Additionally, the slider can be configured to lock into place on the recess in both the closed position and the opened position.

Beverage containers can be filled with hot or cold drinkable liquids, such as water, coffee, tea, soft drink, or alcoholic beverage, such as beer. These beverage containers can be made of a variety of materials such as stainless steel, glass, plastic, cardboard, or paper material. Lids may be provided on beverage containers to provide an opening for pouring out the contents of the beverage container. In certain instances, it can be desired to selectively close and store the container such that the contents of the container do not spill.

Closure and lid and method of forming closure and lid


The present invention relates to a method for generating a user profile in indexing/browsing of multimedia data and a multimedia browsing method using the same. The multimedia data browsing method is characterized in that: (a) constructing a user profile by incorporating a user-preferred application description scheme indicating a user-preferred multimedia browsing method or browsing criterion, wherein the browsing method or browsing criterion is described in different way according to a type of the multimedia data in terms of genre; (b) analyzing the user-preferred application description scheme and selecting a relevant application for implementing a user-preferred browsing; and (c) browsing corresponding multimedia data using the selected preferred application.

1. Field of the Invention
The present invention relates, to a method of generating a user profile for browsing of multimedia data and a multimedia browsing method using the same, and more particularly, to a content-based multimedia data indexing and browsing system in which a user-preferred browsing method is described in the user profile, and multimedia browsing based on user preference is provided using user-preferred browsing information contained in the user profile.
2. Description of the Background Art
In multimedia data indexing and browsing in the conventional art, there have been introduced techniques for variously displaying multimedia data based on user preference.
In internet shopping by using of a multimedia data indexing and browsing system based on user preference, there is a method of selecting only preferred items stored in an user profile by each user and displaying each product in a different way, not displaying all information items used in the internet shopping.
For example, in the case that some user mainly uses price and specification information, some user mainly uses design information, and some user mainly uses product information of a certain particular company in checking electronic products through the internet shopping, each user is given the above preferred information as its own user profile. In case that an user mainly uses price and specification in this preferred information, merely the information containing only price and specification is displayed to the user although other information such as photographs is provided by the user. And, in case of an user who prefers design information, design (photograph) information is mainly displayed. In this way, the information appropriate for the preference of each user is displayed.
In addition, there have been introduced techniques for providing a terminal desk-top interface such as a computer to an user in an user-desired form in a multimedia indexing and browsing system based on user preference in the conventional art.
In other words, the terminal desktop interface that the corresponding user prefers (or designates) is recorded in its user profile, and then the form of the interface stored in the corresponding user profile is provided to the user.
Besides, there have been techniques for supporting help information in the form that user prefers using the recorded usage pattern of user in another conventional art.
The above-mentioned techniques considering user preference (use pattern) in the conventional art all reflects partial user preference in the current restricted application.
Nowadays, the content description is described in the data for supporting the content-based multimedia indexing/browsing. In the case the various browsing method are possible, so if there is the information describing user preference, user can browse multimedia data in the preferred browsing method using preferred browser.
In other words, among a variety of browsers for performing content-based multimedia data indexing and browsing, there may be browsers that is particularly preferred, or browsers that is preferred by the type of multimedia data to the user. However, since the maintenance and management of such data is not achieved, the user cannot enjoy his or her right to various selection, but also must be satisfied with parts of the browsers restrictively provided in a given environment.

Method of generating user profile based on user preference and multimedia data browsing system using the same


A semiconductor device includes a semiconductor substrate provided with an active region including a gate forming area, a source forming area and a drain forming area. A recess is formed in the gate forming area. A gate is formed over the gate forming area that is formed with the recess and includes an insulation layer formed at an upper end portion of a side wall of the recess that is in contact with the source forming area. A source area and a drain area are formed in the active region on opposite sides of the gate.

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of reducing the effect of gate induced drain leakage (GIDL), and a method for manufacturing the same.
As high integration of a semiconductor device has continued to proceed, a channel length of a transistor has been shortened and an ion implantation concentration of source and drain areas has been increased. As a result of these changes, a short channel effect has became a serious problem in which a threshold voltage (Vt) is lowered as charge sharing between the source area and the drain area is increased. In addition, controllability of a gate is reduced. Also, a refresh property deteriorates due to an increase in junction leakage current that results from an increase in an electric field in the source area and the drain area. Therefore, conventional semiconductor devices with a planar channel offer limited capability for overcoming problems that result from high integration.
For this reason, research has been actively performed to fabricate a semiconductor device with a recess channel, which is capable of improving an effective channel length.
Hereinafter, a method for manufacturing a semiconductor device having a conventional recess channel will be briefly described.
After an isolation layer is formed in an isolation region of a semiconductor substrate having an active region including a gate forming area and the isolation region, a screen oxide layer is formed over an entire surface of the semiconductor substrate that is formed with the isolation layer. Ion implantation is performed to adjust a threshold voltage. An ion implantation of the source/drain is sequentially performed on the semiconductor substrate formed with the screen oxide layer. The screen oxide layer is then removed.
After a mask pattern that is used for exposing the gate forming area of the active region is formed over the ion implanted semiconductor substrate, the portion of the semiconductor substrate exposed by the mask pattern is etched to form a recess in the gate forming area of the active region. The mask pattern is then removed.
After a gate insulation layer is formed over the semiconductor substrate including the recess, a gate conductive layer is formed over the gate insulation layer to fill in the recess. The gate insulation layer is formed as an oxide layer and the gate conductive layer is formed as a laminated layer of a polysilicon layer and a tungsten layer. A hard mask layer made of a nitride layer is then formed over the gate conductive layer.
By patterning the hard mask layer, the gate conductive layer, and the gate insulation layer, a transistor having a recess channel is formed in the gate forming area that includes the recess.
A series of known follow up processes are sequentially performed, thereby completing formation of a semiconductor device having the recess channel.
Meanwhile, as aforementioned, as a cell size has been scaled down with high integration of the semiconductor device, a channel doping concentration has been excessively increased to maintain the threshold voltage at the same level. As a result, the refresh property deteriorates.
For this reason, in order to prevent deterioration of the refresh property, a method has been proposed to adjust the threshold voltage (Vt) by applying a P+ polysilicon layer instead of an N+ polysilicon layer.
When applying the P+ polysilicon layer instead of the N+ polysilicon layer, it is possible to significantly decrease the channel doping concentration. The threshold voltage can be ensured even with a low channel dose through a difference in band gap voltage of the semiconductor substrate made of silicon. Also, the refresh property can be improved.
However, in the case of applying the P+ polysilicon layer to the recess channel structure, a band gap is seriously bent due to a Fermi level difference, e.g., approximately 1.1V, between the source/drain area and the gate. As a result, a GIDL phenomenon results at an upper end portion of a side wall of the recess adjacent to the source area, which in turn increases the leakage current and deteriorates the refresh property.
In a GIDL phenomenon, current leaks in the form of an electric field and is concentrated into both edge portions where the gate and the semiconductor substrate contact each other. GIDL is a problem which should be addressed to improve device properties and reliability. Also, GIDL is a major factor in reducing a refresh time of the device.

Semiconductor device and a method for manufacturing the same


An automatic keypad lockout system automatically disables the keypad or other buttons of a personal electronic device (102, 202, 302, 402) when it is stored in an accessory (104, 204, 304, 404) and then automatically re-enables the keypad upon removal of the device from the accessory without effort by the user. Encoding and decoding is accomplished through a variety of devices including magnetic (100), electrical (200), optical (300, 400), and mechanical (500) implementations. The automatic keypad lockout system is extendable (600), (700), (800), and (900) to provide a unique identity (ID), to interchangeable accessories (604, 704, 804, 804). The unique ID is associated with a predetermined user configuration with which to configure the communication device (602, 702, 802, and 902).

Personal communication devices, such as cellular telephones, personal digital assistants (PDAs), pagers and two-way radios are often carried in an accessory, such as a body worn holster, for portability. Many of these devices have exposed keypads. In general, personal communication devices in their holsters are susceptible to key presses resulting in undesired operation. Such undesired operation can result in unwanted calls being placed, the device being inadvertently powered down, personal memory being removed, and other problems. Personal memory being removed results in the loss of personalized settings.
Phones with exposed keypads may allow the user to lock the keypad, but doing so typically requires multiple keystrokes to engage the lock and unlock feature. Given the usual number of keystrokes needed to perform this task, many users ignore or forget the lockout feature altogether. Furthermore, current technology provides no convenient or robust means for replacing the device's personalized settings once lost.
Reprogramming personal settings on a communication device can be impractical. Users are often forced to manually re-enter their personalized settings, which is very time consuming, or have the settings downloaded via a computer. The reprogramming of personal settings is not just an issue when the settings have been lost but also when multiple users want to share the same device. Swapping personalized settings, such as address book, preferred ring tone, speed dial numbers, etc., can be very cumbersome requiring inconvenient reprogramming of the settings as mentioned above.
Accordingly, there is a need to protect personalized settings in a communication device. A means of preventing loss of the personalized settings and facilitating the exchange of personalized settings amongst multiple users would be highly beneficial.

Automated user interface feature for a portable communication device


In one aspect, a method for aligning a component into a wind direction is provided. The component comprises a sensor which is located such that at least part of the sensor is exposed to the wind. A signal is measured based on the force acting on the sensor due to the wind, and the component is rotated depending on the measured signal. Additionally a sensor for determining misalignment of a component relative to a wind direction is provided. The sensor comprises at least one flat element and at least one tool or device for measuring the force acting on the flat element.

The alignment of, for example, horizontal axis wind turbines into a particular wind direction is crucial in order to avoid high structural loads and in order to produce optimal power. The wind direction is typically measured by use of a wind vane or by use of a sonic wind sensor.

Method for aligning a component into a wind direction and sensor for determining misalignment of a component relative to a wind direction


Disclosed is a rechargeable lithium ion battery including a positive electrode comprising a first current collector and a positive active material layer on the first current collector; a negative electrode comprising a second current collector and a negative active material layer on the second current collector; and an electrolyte comprising a non-aqueous organic solvent and a lithium salt. At least one of the first and the second current collectors includes a rigid polymer film with a metal deposited on the rigid polymer film.

Rechargeable lithium batteries, which are attractive as power sources for portable electronics, use organic electrolyte, and exhibit twice the discharge capacity of conventional batteries with alkaline aqueous solution electrolyte with higher energy density.
Positive active materials for the positive electrodes of rechargeable lithium batteries use lithium and transition metal-included oxides having a structure being capable of intercalating lithium. Examples include LiCoO2, LiMn2O4, and LiNi1-xCoxO2 (0<x<1). Negative active materials in a negative electrode use crystalline carbon, amorphous carbon, or a composite of carbon.
The positive electrode and the negative electrode are produced by mixing the active material, a binder and optionally a conductive agent to a composition in the form of slurry, and coating the composition on a current collector. The current collector generally uses aluminum for the positive electrode, and copper for the negative electrode.
Though a rechargeable lithium battery exhibits relatively high energy density and good cycle life characteristics, the rapid development in the corresponding electronics industries require still further improvements in the energy density and cycle life characteristics.


A communication device includes: T/D data generating means for generating T/D data according to a calendar; storage means for edittably storing T/D data regarding a beginning and an end of a specified time period; judgement means for judging whether the T/D data generated by the T/D date generating means is in the specified time period; T/D data changing means for changing the T/D data of the T/D generating means to T/D data according to the preset T/D data; wherein the T/D data regarding the beginning and the end of the specified time period is set or replaced with a data supplied via communication line from a certain communication center.

There are some countries in which the "Daylight Savings Time" was introduced and in such a country, a time adjustment is mandated twice a year to meet the time shift due to the Daylight Savings Time. During the Daylight Savings Time period in such a country, it is required to adjust the time/date information (i.e., Year/Month/Day/Time) of the communication device such as a facsimile machine from the time/date data based on the standard time to the time/date based on the Daylight Savings Time period.
In an ordinary case, such time adjustment due to the Daylight Savings Time (hereinafter referred to as "DST" for short) is carried out by the operator. In some other case, there exists a facsimile, representing the communication device of this invention, has a function to adjust the time change due to the DST. Such a facsimile has a data storage memory for storing time/date information of the DST including a beginning date of the DST and an end date of the DST and means for automatically changing the time/date information from the one according to the standard time of the particular region (or a country) to the time/date information according to DST period when the region enters to the DST period and automatically switch back to the time/date according to the standard time when the DST period ends.
In the former conventional communication device described in the above, the user has to manually adjust the time/date information of the device at the beginning of the DST period and the end of the period. Thus the adjustment itself by the user could be a cumbersome task and moreover if the user neglects such adjustment, the wrong time/date information appears on the display of the device.
Even with the latter mentioned facsimile device as a prior art technology having a function of automatic time adjustment due to the DST, if the device still has to rely on the user's input data including a beginning date of the DST and an end date of the DST, very similar problems as described will result.
If, however, the latter mentioned device stores in advance information regarding the beginning and the end of the DST period in all the regions and countries employing DST, needlessly large memory is required for storing the information as practically speaking only one set of data is needed for the facsimile machine; thus the rest of the stored data would never be used unless the machine was transferred to the other regions.

Communication device with time adjustment function


A circuit automatically changes the gain in a PLL for driving a motor of the type having a motor speed signal that indicates the speed of motor rotation. The circuit includes a phase detector for sensing a phase difference between the motor speed signal and a reference frequency and for producing an output signal of duration proportional to the sensed phase difference. A counter counts clock pulses throughout the duration of the output signal, and a motor driving circuit drives the motor in response to the count reached by the counter. A source of clock pulses provides clock signals at first and second frequencies, the second frequency being lower than the first frequency, and a lock range sense circuit produces a sense signal output that indicates when the PLL is within a predetermined phase difference range. A circuit responsive to the sense signal output selectively applies the first frequency to clock the counter when the PLL is within the predetermined phase difference range, and to apply the second frequency to clock the counter when the PLL is operating outside of the predetermined phase difference range.

1. Field of the Invention
This invention relates to improvements in circuitry and methods for operating a phase-locked loop (PLL), and more particularly to improvements in circuitry and methods for reducing the steady state error of the PLL and increasing the capture range of the PLL during convergence by automatically changing the gain of the phase detector.
2. Technical Background
This invention pertains to phase-locked loop circuits of the type that use a phase detector, an integrating filter, and a variable frequency feedback circuit to track accurately an input signal at a reference frequency. In a broad sense, the variable frequency circuit can be a voltage-controlled oscillator (VCO). However, in the embodiment illustrated herein, the variable frequency circuit includes a variable speed motor and a generator that produces a signal of frequency dependent upon the speed of the motor. A phase detector determines the phase of the variable frequency signal with respect to the reference frequency. The phase detector then generates a dc voltage signal, which may be filtered by the integrating filter, to control the variable frequency signal, for example, by controlling the frequency of a VCO or by controlling the speed of the motor. The voltage signal forces the VCO to compensate, or changes the speed of the motor, when the variable frequency drifts from the reference frequency.
Typically when a PLL begins operation, the variable frequency requires a certain time to converge to the frequency of the input signal, until "lock" occurs. When lock occurs, the variable frequency tracks the input signal, and the PLL circuit functions in a feedback mode to maintain the lock. As known in the art, a higher gain applied to the signal from the phase detector reduces the steady state operation error. On the other hand, a low gain applied to the phase detector output signal widens the lock, or capture, range.
What is needed is a circuit and method that will provide a lower gain when the phase error between the reference frequency and the variable frequency is large, during convergence, and a higher gain when the phase error is low, when lock has been, or is close to being, attained.

AGC with non-linear gain for PLL circuits