An apparatus and method for evaluating semiconductor structures and devices are provided. A method for evaluating at least one selected electrical property of a semiconductor device (201) in relation to a selected geometric dimension of the semiconductor device (201). The method further includes forming a plurality of semiconductor devices (201) on a substrate (202), the devices (201) having at least one geometric dimension, measuring the at least one electrical property of at least one of the semiconductor devices (201) using a scanning probe microscopy based technique, and determining a relationship between the measured electrical property and the selected geometric dimension of the semiconductor device (201). The method further includes evaluating at least one semiconductor fabrication process based upon the determined relationship.

This invention generally relates to the field of electronic devices. More specifically this invention relates to an apparatus and method for evaluating semiconductor structures and devices.
Advancements in the semiconductor industry have converged on developing submicron geometric devices for microelectronic circuits. Semiconductor fabrication processes, in their infancy, were sometimes plagued with fatal defectivity that inhibited the production of integrated circuits. As semiconductor fabrication processes became more advanced, the level and occurrence of defects in semiconductor devices have decreased. However, the reduction of semiconductor geometries to submicron levels has manifested inherent defect modes which may impact the performance of resulting semiconductor devices.
Silicon wafers provide a common substrate used to fabricate multiple semiconductor devices. As geometries for semiconductor devices are reduced, the inherent characteristics of the device""s materials such as silicon become a significant factor. Structural defects are one of the inherent problems facing the advancement of submicron semiconductor devices. Some structural defects negatively impact device performance and may effect, for example, leakage currents, carrier lifetimes, and gate oxide integrity.
There are several different classifications of structural and process defects that can occur in semiconductor devices. One defect that occurs in semiconductor processing is an area defect called grain boundaries. Grain boundaries occur when certain planes of atoms terminate from one process layer and a subsequent layer fills-in the region between the two grains. For example, when an oxide layer is deposed onto silicon, the atoms in the region of the boundary are displaced from their normal position. This displacement is generally confined to a region very close to the grain boundary. Thus, a semiconductor device having multiple process layers typically has several different material interfaces. As a result, any two layers may have an angle of misorientation that occurs during a single process. As grains of the layers form an intersection, certain rows of atoms within each layer""s lattice structure may not line up and extend their full length at the junction. This causes a dislocation between the two layers resulting in a grain boundary.
Another defect that occurs in semiconductors is caused by voids in the lattice material due to precipitates of extrinsic or intrinsic point defects. Precipitates are a complicated defect mode that include the formation of an intermediate crystal structure that later transforms into a final structure. The initially formed precipitate particle is called a nuclei and the transformation process is called a nucleation process. The nucleation process can occur in two ways, heterogeneous nucleation that occurs at a crystalline defect such as a dislocation, a grain boundary, or an impurity. The second process is homogenous nucleation, a random composition of the nuclei. In general, during a nucleation process, the more rapid diffusion of the semiconductor material, the more quickly precipitation occurs.
A bulk defect that occurs in one silicon crystal layer can be the cause of other crystalline defects as additional layers are grown. For example, the growth of oxygen precipitates in silicon occurs by the reaction of oxygen with silicon at the precipitate surface to form silicon dioxide. The volume change from silicon to silicon dioxide is almost two to one with silicon dioxide being the larger. Consequently, the lattice surrounding the silicon dioxide precipitate is subject to large compressions placing undue stress on the lattice and junction regions which can lead to a bulk defect within the lattice structure.
Therefore, as semiconductor device geometry""s become smaller, evaluating the effects of both intrinsic and extrinsic defects are critical in optimizing the performance of semiconductor devices and structures and associated fabrication processes.
In accordance with the present invention, an apparatus and methods are provided which substantially eliminates or reduces disadvantages and problems associated with prior device evaluation methods and apparatuses.
The present invention discloses a method for evaluating at least one selected electrical property of a semiconductor device in relation to a selected geometric dimension of the semiconductor device. The method includes forming a plurality of semiconductor devices on a substrate, the devices having at least one geometric dimension, measuring the at least one electrical property of at least one of the semiconductor devices using a scanning probe microscopy based technique, and determining a relationship between the measured electrical property and the selected geometric dimension of the semiconductor device. The method further includes evaluating at least one semiconductor fabrication process based upon the determined relationship.
More specifically, the method further includes measuring a topography of the semiconductor device using a scanning probe microscopy based technique.
More specifically, the method further includes measuring the topography in a region proximal to the measured electrical property.
The present invention also provides a method for evaluating a semiconductor device. The method includes providing the semiconductor device, measuring a first characteristic of the device using a first--scanning probe microscopy technique, and measuring an electrical property of the device using a second scanning probe microscopy technique. The method further includes determining variations in the semiconductor device based upon the measured first characteristic and the measured electrical property wherein the first characteristic and the electrical property are measured in a proximal region to one another.
More specifically, the method includes providing a semiconductor device with a selected geometric dimension of less than one micrometer.
More specifically, the method includes measuring the first characteristic and the electrical property simultaneously.
The present invention further provides a system for evaluating semiconductor devices. The system includes a processor, a storage medium operably coupled to the processor, a scanning probe microscopy device, operably coupled to the processor to evaluate semiconductor devices wherein the scanning probe microscopy includes a probe configured to measure at least one electrical property of the semiconductor device. The system further includes a program of instructions for evaluating a semiconductor device, the program of instructions including at least one instruction configured to measure the at least one electrical property and determining a relationship between the measured electrical property and at least one geometric dimension of the device.
More specifically, the system is configured to include a nanoscopic probe.

Apparatus and method for evaluating semiconductor structures and devices


The use of log marking (otherwise known as “coloring”) of sub-portions of a log that records actions (e.g., data operations) performed by a computing system. The log is composed of multiple sub-portions, such as virtual log files, which are successively added to the log as the log grows. For instance, the sub-portions may be virtual log files of the log. The principles described herein change the use of log marking depending on which sub-portion of the log is being marked. If the computing system fails, and recovery is needed, the recovery process can thus deterministically identify where the last written log record is.

Computing systems and associated networks have revolutionized the way human beings work, play, and communicate. Nearly every aspect of our lives is affected in some way by computing systems. The proliferation of networks has allowed computing systems to share data and communicate, vastly increasing information access. For this reason, the present age is often referred to as the "information age". Data systems, such as databases, play a particularly important role in storing, organizing, filtering, and querying against large amounts of data. Often, tasks performed on a computing system are logged. For instance, the data operations (reads, writes, checkpoints, transaction commits and aborts, and so forth) of a database system are typically logged, with each data operation having a log record.
When computing systems write to or read from a persisted store, they do so atomically at the block-level. That is, a block is either written, or not written. A typical block size for a computing system is 512 bytes or more recently 4096 bytes. When writing a block to a persisted log, the block often has multiple log records contained therein since a log record is typically much smaller than the size of a block. To distinguish the position of each log record within the block, the block is subdivided even further into slots, where each log record occupies a slot within the block. At a larger level, the log also typically includes multiple sub-portions that each include a large number of blocks. An example of such a sub-portion is a virtual log file.
Because data operations occur over a long period of time, virtual log files are added to the log as needed to accommodate further log records. Each log record is uniquely identified within that log typically using a log sequence number. A log sequence number for a log record that occupies a particular slot of a particular block of a particular virtual log file is often composed of a concatenation of the respective virtual log file identifier, the respective block identifier, and the respective slot identifier.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one exemplary technology area where some embodiments described herein may be practiced.

Log marking dependent on log sub-portion


A keyless entry system includes a transmitter and a receiver. The transmitter includes an operation switch, transmission means, and transmission control means. The receiver includes receiving means and determination means. The transmission control means generates operation information including a function code corresponding to the operation switch and a count value corresponding to the number of operations of the operation switch. The transmission means transmits the operation information using a plurality of radio signals in different frequency bands. The receiving means receives the plurality of radio signals and detects the operation information from the plurality of received radio signals. The determination means specifies the content of an instruction to the device based on the function code and the count value included in the operation information.

1. Field of the Invention
The present invention relates to a keyless entry system, and in particular, to a keyless entry system that can transmit operation information corresponding to multiple operations on the operation switch.
2. Description of the Related Art
In recent years, a keyless entry system that can perform a vehicle operation such as the locking and unlocking of the door of the vehicle, without using a mechanical key, using radio communication between a portable device carried by the user and an in-vehicle device mounted in the vehicle has come into wide use. The portable device used in such a keyless entry system needs to be small for convenience, and accordingly, the number of operation switches that can be placed in the portable device is limited. Therefore, for example, a keyless entry system that can select a plurality of vehicle operations according to the number of operations of the operation switch has been demanded. In such a keyless entry system, it has become necessary to reliably transmit operation information corresponding to an operation on the operation switch to the in-vehicle device even if the operation is performed multiple times.
As a technique for such a keyless entry system, a keyless entry system 100 disclosed in Japanese Unexamined Patent Application Publication No. 11-081764, a locking and unlocking device 200 (keyless entry system) disclosed in Japanese Unexamined Utility Model Registration Application Publication No. 2-91864, and the like have been proposed. FIG. 6 is an explanatory view showing the configuration of the keyless entry system 100 disclosed in Japanese Unexamined Patent Application Publication No. 11-081764. FIG. 7 is an explanatory view showing the configuration of the locking and unlocking device 200 disclosed in Japanese Unexamined Utility Model Registration Application Publication No. 2-91864.
As shown in FIG. 6, the keyless entry system 100 includes a transmitter 101 (portable device) and a receiver 102 (in-vehicle device). The transmitter 101 includes an operation switch 112, transmission means 113, and transmission control means 111. The operation switch 112 is a switch used when a user gives an instruction to use a function. The transmission means 113 includes an oscillation circuit 114, a modulation circuit 115, and a transmission antenna 116. The transmission means 113 converts a function code (operation information), which indicates the instruction content corresponding to the operation on the operation switch 112, to a remote control signal (radio signal) of the radio wave and transmits the remote control signal. The transmission control means 111 includes a microprocessor 118 and a RAM 119. The transmission control means 111 controls the transmission means 113. The receiver 102 receives the remote control signal transmitted from the transmitter 101 and operates a device 3, which is a keyless entry target, based on the instruction content of the function code included in the received remote control signal.
In the keyless entry system 100, when the operation switch is operated while the transmission processing is being performed by the transmission means 113, a function code corresponding to the operation under transmission processing is stored in transmission control means 111, and the stored function code is converted into a remote control signal to be transmitted by the transmission means 113 after the end of previous transmitting processing. In this manner, in the keyless entry system 100, even if an operation on the operation switch 112 is performed multiple times in a short period of time, it is possible to perform a process of transmitting the function code corresponding to the operation.
As shown in FIG. 7, the locking and unlocking device 200 includes key code transmission means 201 (portable device), a key code receiver 202 (in-vehicle device), and key code verification means 203. The key code transmission means 201 transmits a signal (radio signal) including predetermined key code information (operation information). The key code transmission means 201 transmits a key code multiple times at predetermined intervals. In addition, the frequency of the carrier that carries the key code thereon is controlled so as to be different each time of transmission.
The key code receiver 202 receives a signal transmitted by the key code transmission means 201. The key code verification means 203 compares the key code included in the signal received by the key code receiver 202 with a key code stored in advance, and outputs a locking and unlocking signal when both the key codes match each other.
Although there is no explanation regarding the operation switch in Japanese Unexamined Utility Model Registration Application Publication No. 2-91864, a key code corresponding to the operation on the operation switch can be transmitted by connecting the operation switch to the key code transmission means 201 of the locking and unlocking device 200.
In the keyless entry system 100 disclosed in Japanese Unexamined Patent Application Publication No. 11-081764, even if an operation on the operation switch 112 is performed multiple times in a short period of time, it is possible to perform a process of transmitting the function code corresponding to the operations. However, when the noise of the same frequency as a remote control signal is generated during transmission of the function code, communication between the transmitter 101 and the receiver 102 is interrupted, and accordingly, the receiver 102 cannot receive the remote control signal reliably. As a result, there has been a problem in that it is not possible to reliably transmit the function code. In addition, for example, when only the remote control signal corresponding to the first operation is transmitted despite having performed the operation on the operation switch 112 twice, there is a possibility that the device 3 will operate unlike the intention of the user.
On the other hand, in the locking and unlocking device 200 disclosed in Japanese Unexamined Utility Model Registration Application Publication No. 2-91864, even if the noise of the same frequency as one of the carriers is generated during transmission of the key code, it is possible to transmit the key code using carriers of other frequencies. In the locking and unlocking device 200, however, since the key code is transmitted multiple times at predetermined intervals, it takes time to transmit the key code. For this reason, when the operation on the operation switch is performed multiple times in a short period of time, there is a possibility that the key code may not be reliably transmitted.


Hand-held transmitting and/or receiving apparatus, including a housing made of electrically non-conductive material, an electric circuit positioned within the housing, an electrical ground plane positioned within the housing, an antenna resonator element extending approximately parallel to the ground plane and having a first free end and a second end electrically connected by a ground connector to the ground plane and an arrangement for connecting the ground plane and the resonator element to the electric circuit. The resonator element, the ground plane and the ground connector are positioned about and fixed to a dielectric body positioned inside the housing. This antenna is easily manufactured and reduces the influence of mechanical tolerances and mechanical and thermal influences on the electrical parameters of the antenna.

1. Field of the Invention
The invention relates to a hand-held transmitting and/or receiving apparatus including a housing made of an electrically non-conductive material, an electric circuit inside the housing, an electrical ground plane inside the housing made from non-conductive material, an antenna resonator element extending approximately parallel to the ground plane and having a first free end and a second end electrically connected by a ground connector to the ground plane and a device for connecting the ground plane and the resonant element to the electric circuit.
2. Description of the Prior Art
Hand held transmitting and receiving devices are well known. Such a device is disclosed in European Patent No. EP 0 484 454 B1 where an antenna resonant element has the form of an angled metal sheet of metal foil applied on the outside of a plastic housing. An electrical ground plane has the form of a shielding housing positioned inside the plastic housing which shielding housing contains the electric circuit. Between the shielding housing and the plastic housing and in the area of the antenna resonant element is an air gap. A grounding lead extends through a slit in the plastic housing and connects the angled leg of the L-shaped antenna resonant element to the shielding housing.
This apparatus has the disadvantage that it is difficult to form the slit in the plastic housing for the lead to extend through. Either the slit must be formed when forming the housing or the slit has to be cut after the housing is formed. Furthermore, it is difficult to provide the ground connector leading through the slit and to connect it to the antenna resonant element at one end and to the shielding housing inside the plastic housing at the other end.
An important electrical disadvantage of this known apparatus results from the air gap between the shielding housing and the plastic housing on which an antenna resonant element is fixed. The electrical parameters of the resonant element are influenced by this air gap. Since tolerances of the dimensions of this air gap and changes due to mechanical and thermal influences are unavoidable it is not possible to keep the electrical parameters of the antenna constant. This results in mismatching, standing waves on the feed line to the antenna and changes of the radiation pattern.


The present invention comprises a device and methods for dissolution or immersion testing and, in particular, a device and methods that improve the consistency of test results by limiting the ability of pharmaceutical or other dosage forms to move or reorient during testing.

In pharmaceutical and laboratory research and development, it is commonplace, during formulation development, stability determination, analytical method development, quality control, or otherwise, to ascertain the rate at which a solid dissolves under certain well-defined conditions and/or to predict how it will dissolve in the human system. By way of example, detailed procedures for conducting such testing and specifications for the apparatus employed therein are outlined in the publications of the American Pharmaceutical Association's Drug Standards Laboratory, the United States Pharmacopoeia ("USP") and the National Formulary. By way of further example, USP 25 <711> Dissolution, which is incorporated herein by reference, describes a test to determine compliance with the dissolution requirements that are stated in the individual monograph for a particular drug. The current USP specifies two alternative apparatuses to be used for the test.
Apparatus 1 (or type 1 apparatus) consists of a vessel made of glass or other inert transparent materials with one of the following dimensions and capacities: for a nominal capacity of 1 liter, the height is 160 mm to 210 mm and its inside diameter is 98 mm to 106 mm; for a nominal capacity of 2 liters, the height is 280 mm to 300 mm and its inside diameter is 98 mm to 106 mm; and for a nominal capacity of 4 liters, the height is 280 mm to 300 mm and its inside diameter is 145 mm to 155 mm. Its sides are flanged at the top. The apparatus further consists of a motor, a metallic drive shaft and a cylindrical basket. See FIG. 17. It is specified that the shaft and basket components of the stirring element are fabricated of stainless steel, type 316 or equivalent, to the specifications shown in FIG. 1 of the USP. It is further specified that the basket may be coated with a thin layer of gold.
Apparatus 2 (or type 2 apparatus) is essentially the same as apparatus 1 except that a paddle formed from a blade and a shaft is used as the stirring element rather than a basket. See FIG. 18. USP specifies as follows: the paddle conforms to the specifications shown in FIG. 2 thereof; the distance of 25±2 mm between the blade and the inside bottom of the vessel is maintained during the test; the metallic or suitably inert, rigid blade and shaft comprise a single entity; a suitable two-part detachable design may be used provided the assembly remains firmly engaged during the test; and the paddle blade and shaft may be coated with a suitable inert coating.
In testing, the dosage form is allowed to sink to the bottom of the vessel before rotation of the paddle is started. The USP further provides that a small, loose piece of non-reactive material such as a few turns of wire may be attached to dosage forms that would otherwise float and that other validated sinker devices may be used. Such devices may be formed of a material that is not easily corrodible by the dissolution medium, which may be acidic.
The testing procedure provided for in USP 25 <711> Dissolution is generally as follows. The stated volume of dissolution medium is placed in the vessel specified in the individual monograph for the drug being tested, the apparatus is assembled, and the medium is temperature equilibrated to 37° C.±0.5° C. (to approximate in vivo conditions). Thereafter, the dosage form is placed in the apparatus and the apparatus is operated at the rate specified in the individual monograph. Within the time interval specified, or at each of the stated times, a specimen is withdrawn from the vessel. Often the test is repeated in different vessels and/or with a second, third, or additional dosage form of the drug being tested.
Hence, it is known in the art to entrap dosage forms in a gold coated and/or stainless steel wire basket or in a few turns of non-corrosive wire. In addition, there are commercially available sinkers designed to hold a gelatin capsule in place in a USP 25 <711> Dissolution type 2 apparatus until it dissolves. Examples of commercially available capsule sinkers may be found at www.tabletdissolution.com. However, such devices are not designed to hold a tablet in a specific orientation during testing or to be used in conjunction with conventional dissolution baskets.
It is also known in the art to limit capsule movement during testing. Apparatus 7 of USP 25 <725> Drug Release teaches a holder designed for coated oral extended release tablets. See FIG. 19. Apparatus 7 specifies the use of a vertically reciprocating spring holder attached to a stainless steel tube and Sample Preparation A, USP 25 <724> Drug Release, allows for the use of a small nylon net bag at the end of a plastic rod. Such holders, however, have drawbacks. For example, the adhesive used to attach the tablets to the rod of the holder can compromise test results by affecting the rate-controlling coating and, thereby, the drug release profile. Additionally, such holders are not useful for tablets with a thin coating or shell because the coating or shell is likely to collapse and dump its content due to the upward and downward strokes of the holder during testing.
Finneran, U.S. Pat. No. 4,669,771, teaches a device for loosely holding a capsule during fluid immersion testing with a plurality of gripping fingers connected at one end which fingers surround a chamber to receive and retain a capsule. However, the device is not suitable for immersion testing of tablets. Fassihi, U.S. Pat. No. 5,412,979, teaches a disk that restrains a dosage form from floating to top of a fluid medium during testing using a vertical shaft and blade apparatus. However, the device is not designed to hold a dosage form in a specific orientation during testing or to be used in conjunction with a dissolution basket. In addition, it is known that differences in hydrodynamic effects corresponding to the relative position of test tablets in test vessels are likely to cause high variability in dissolution testing. See Study Highlights Flawed Dissolution Testing Procedure, Pharmaceutical Technology, October 2003, at 18–19.
The present invention provides a device and methods for immersion and dissolution testing whereby a tablet (by way of example, a controlled release tablet such as an osmotic tablet or matrix tablet) or capsule is held in a specific orientation or substantially fixed position during testing, which can advantageously provide test results that are more consistent between the different tablets (or capsules) and/or vessels used for the testing. For example, when a tablet begins to dissolve, the change in mass can result in a change in the orientation of the tablet either on the bottom of a dissolution vessel, or within a basket, if the movement of the tablet is not limited. A change in orientation of the tablet can result in variability of dissolution characteristics between different tablets of the particular drug being tested and/or vessels used for the testing.
The inventors have found the present invention is also well suited for use with tablets having a preformed passageway, e.g., laser drilled, such as an osmotic tablet with a semi-permeable membrane surrounding the tablet. If a tablet with a preformed passageway(s) reorients during dissolution testing, the test results may be altered if the reorientation interferes with diffusion of the medicament from the passageway(s). For example, if the tablet orients so that the passageway exit is at its bottom, the dissolved contents tend to "dump" out of the exit faster than if the exit is maintained at the top or side of the tablet. By maintaining the exit on the sides (if two exits) and/or on the side or top (if one exit), the contents are prevented from dumping, which allows a steadier rate of diffusion of the contents, including the active drug.
In addition, with respect to controlled-release dosage form tablets such as matrix tablets, the mass of the dosage form diminishes over time. Maintaining the orientation of such a tablet provides for a greater precision in results between different tablets of the particular drug being tested and/or vessels used for the testing.
The subject invention can also prevent tablets or capsules and their contents from sticking to the testing vessel. For example, as tablets dissolve, certain excipients, which may have adherent properties, can cause a tablet to adhere to the inner surface of the vessel. There is a high degree of variability in tablets that adhere to the vessel, which can also cause variability in dissolution between different tablets or capsules of the particular drug being tested and/or vessels used for the testing. By preventing such dosage form adhesion, the subject invention also can provide test results that are more accurate and/or consistent. The subject invention limits variability of location and orientation of tablets and capsules during dissolution testing, which also limits variation from vessel to vessel during testing.

Dosage form holder device and methods for immersion testing


Insulating layers of a redistribution layer of a semiconductor package may be formed as a polymer film having inorganic fillers formed therein. The inorganic fillers may trap reactive materials to inhibit and/or substantially prevent the metal conductors, such as chip pads of the semiconductor chip being packaged, from being damaged by the reactive material. As a result, the reliability and the durability of the semiconductor package may be improved.

Embodiments of the inventive concepts relate to a semiconductor package and a method of fabricating the same and, more particularly, to a semiconductor package including a redistribution layer and a method of fabricating the same.
Integrated circuit chips are typically provided with a semiconductor package so as to be suitably applied to circuit boards of electronic products or otherwise combined within an electronic system. In a general semiconductor package, an integrated circuit chip (or a semiconductor chip) may be mounted on a printed circuit board (PCB) and may be electrically connected to the PCB through bonding wires or bumps. Various researches for improving reliability and durability of semiconductor packages have been conducted with the development of an electronic industry.

Semiconductor package and method of fabricating the same


A sampled amplitude read channel is disclosed for disk storage systems which asynchronously samples an analog read signal, adaptively equalizes the resulting discrete time sample values according to a target partial response, extracts synchronous sample values through interpolated timing recovery, and detects digital data from the synchronous sample values using a Viterbi sequence detector. To increase the speed of the read channel, the FIR filters in the equalizer and interpolator are implemented according to a residue number system. Further, the residue number system implementation of the FIR filters uses "one-hot" encoding to decrease power dissipation.

Computer storage systems (such as optical, magnetic, and the like) record digital data onto the surface of a storage medium, which is typically in the form of a rotating magnetic or optical disc, by altering a surface characteristic of the disc. The digital data serves to modulate the operation of a write transducer (write head) which records binary sequences onto the disc in radially concentric or spiral tracks. In magnetic recording systems, for example, the digital data modulates the current in a write coil in order to record a series of magnetic flux transitions onto the surface of a magnetizable disc. And in optical recording systems, for example, the digital data may modulate the intensity of a laser beam in order to record a series of "pits" onto the surface of an optical disc. When reading this recorded data, a read transducer (read head), positioned in close proximity to the rotating disc, detects the alterations on the medium and generates a sequence of corresponding pulses in an analog read signal. These pulses are then detected and decoded by read channel circuitry in order to reproduce the digital sequence.
Detecting and decoding the pulses into a digital sequence can be performed by a simple peak detector in a conventional analog read channel or, as in more recent designs, by a discrete time sequence detector in a sampled amplitude read channel. Discrete time sequence detectors are preferred over simple analog pulse detectors because they compensate for intersymbol interference (ISI) and are less susceptible to channel noise. Consequently, discrete time sequence detectors increase the capacity and reliability of the storage system. There are several well known discrete time sequence detection methods including discrete time pulse detection (DPD), partial response (PR) with Viterbi detection, maximum likelihood sequence detection (MLSD), decision-feedback equalization (DFE), enhanced decision-feedback equalization (EDFE), and fixed-delay tree-search with decision-feedback (FDTS/DF).
In conventional peak detection schemes, analog circuitry, responsive to threshold crossing or derivative information, detects peaks in the continuous time analog signal generated by the read head. The analog read signal is "segmented" into bit cell periods and interpreted during these segments of time. The presence of a peak during the bit cell period is detected as a "1" bit, whereas the absence of a peak is detected as a "0" bit. The most common errors in detection occur when the bit cells are not correctly aligned with the analog pulse data. Timing recovery, then, adjusts the bit cell periods so that the peaks occur in the center of the bit cells on average in order to minimize detection errors. Since timing information is derived only when peaks are detected, the input data stream is normally run length limited (RLL) to limit the number of consecutive "0" bits.
As the pulses are packed closer together on the concentric data tracks in the effort to increase data density, detection errors can also occur due to intersymbol interference, a distortion in the read signal caused by closely spaced overlapping pulses. This interference can cause a peak to shift out of its bit cell, or its magnitude to decrease, resulting in a detection error. The ISI effect is reduced by decreasing the data density or by employing an encoding scheme that ensures a minimum number of "0" bits occur between "1" bits. For example, a (d,k) run length limited (RLL) code constrains to d the minimum number of "0" bits between "1" bits, and to k the maximum number of consecutive "0" bits. A typical (1,7) RLL 2/3 rate code encodes 8 bit data words into 12 bit codewords to satisfy the (1,7) constraint.
Sampled amplitude detection, such as partial response (PR) with Viterbi detection, allows for increased data density by compensating for intersymbol interference and the effect of channel noise. Unlike conventional peak detection systems, sampled amplitude recording detects digital data by interpreting, at discrete time instances, the actual value of the pulse data. To this end, the read channel comprises a sampling device for sampling the analog read signal, and a timing recovery circuit for synchronizing the samples to the baud rate (code bit rate). Before sampling the pulses, a variable gain amplifier adjusts the read signal's amplitude to a nominal value, and a low pass analog filter filters the read signal to attenuate aliasing noise. After sampling, a digital equalizer filter equalizes the sample values according to a desired partial response, and a discrete time sequence detector, such as a Viterbi detector, interprets the equalized sample values in context to determine a most likely sequence for the digital data (i.e., maximum likelihood sequence detection (MLSD)). MLSD takes into account the effect of ISI and channel noise in the detection algorithm, thereby decreasing the probability of a detection error. This increases the effective signal to noise ratio and, for a given (d,k) constraint, allows for significantly higher data density as compared to conventional analog peak detection read channels.
The application of sampled amplitude techniques to digital communication channels is well documented. See Y. Kabal and S. Pasupathy, "Partial Response Signaling", IEEE Trans. Commun. Tech., Vol. COM-23, pp.921-934, September 1975; and Edward A. Lee and David G. Messerschmitt, "Digital Communication", Kluwer Academic Publishers, Boston, 1990; and G. D. Forney, Jr., "The Viterbi Algorithm", Proc. IEEE, Vol. 61, pp. 268-278, March 1973.
Applying sampled amplitude techniques to magnetic storage systems is also well documented. See Roy D. Cideciyan, Francois Dolivo, Walter Hirt, and Wolfgang Schott, "A PRML System for Digital Magnetic Recording", IEEE Journal on Selected Areas in Communications, Vol. 10 No. 1, January 1992, pp.38-56; and Wood et al, "Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel", IEEE Trans. Commun., Vol. Com-34, No. 5, pp. 454-461, May 1986; and Coker Et al, "Implementation of PRML in a Rigid disc Drive", IEEE Trans. on Magnetics, Vol. 27, No. 6, November 1991; and Carley et al, "Adaptive Continous-Time Equalization Followed By FDTS/DF Sequence Detection", Digest of The Magnetic Recording Conference, August 15-17, 1994, pp. C3; and Moon et al, "Constrained-Complexity Equalizer Design for Fixed Delay Tree Search with Decision Feedback", IEEE Trans. on Magnetics, Vol. 30, No. 5, September 1994; and Abbott et al, "Timing Recovery For Adaptive Decision Feedback Equalization of The Magnetic Storage Channel", Globecom'90 IEEE Global Telecommunications Conference 1990, San Diego, Calif., November 1990, pp.1794-1799; and Abbott et al, "Performance of Digital Magnetic Recording with Equalization and Offtrack Interference", IEEE Transactions on Magnetics, Vol. 27, No. 1, January 1991; and Cioffi et al, "Adaptive Equalization in Magnetic-disc Storage Channels", IEEE Communication Magazine, February 1990; and Roger Wood, "Enhanced Decision Feedback Equalization", Intermag'90.
Similar to conventional peak detection systems, sampled amplitude detection requires timing recovery in order to correctly extract the digital sequence. Rather than process the continuous signal to align peaks to the center of bit cell periods as in peak detection systems, sampled amplitude systems synchronize the pulse samples to the baud rate. In conventional sampled amplitude read channels, timing recovery synchronizes a sampling clock by minimizing an error between the signal sample values and estimated sample values. A pulse detector or slicer determines the estimated sample values from the read signal samples. Even in the presence of ISI the sample values can be estimated and, together with the signal sample values, used to synchronize the sampling of the analog pulses in a decision-directed feedback system.
A phase-locked-loop (PLL) normally implements the timing recovery decision-directed feedback system. The PLL comprises a phase detector for generating a phase error based on the difference between the estimated samples and the read signal samples. A PLL loop filter filters the phase error, and the filtered phase error operates to synchronize the channel samples to the baud rate. Conventionally, the phase error adjusts the frequency of a sampling clock which is typically the output of a variable frequency oscillator (VFO). The output of the VFO controls a sampling device, such as an analog-to-digital (A/D) converter, to synchronize the sampling to the baud rate.
As mentioned above, sampled amplitude read channels also commonly employ a discrete time equalizer filter to equalize the sample values into a desired partial response (PR4, EPR4, EEPR4, etc.) before sequence detection. To this end, adaptive algorithms have been applied to compensate in real time for parameter variations in the recording system and across the disc radius. For example, U.S. Pat. No. 5,381,359 entitled "Adaptation and Training of Digital Finite Impulse Response Filter Within PRML Sampling Data Detection Channel", discloses an adaptive equalizer filter that operates according to a well known least mean square (LMS) algorithm, EQU W.sub.k+1 =W.sub.k -.mu..multidot.e.sub.k .multidot.X.sub.k,
where: W.sub.k represents a vector of filter coefficients; .mu. is a programmable gain; e.sub.k represents a sample error between the filter's actual output and a desired output; and X.sub.k represents a vector of sample values from the filter input. In other words, the LMS adaptive equalizer filter is a closed loop feedback system that attempts to minimize the mean squared error between an actual output of the filter and a desired output by continuously adjusting the filter's coefficients to achieve an optimum frequency response.
A problem associated with adaptive equalizer filters in sampled amplitude read channels is that the timing recovery and gain control loops can interfere with the adaptive feedback loop, thereby preventing the adaptive equalizer filter from converging to an optimal state. This non-convergence is manifested by the filter's phase and gain response drifting as it competes with the timing and gain control loops. An article by J. D. Coker et al. entitled "Implementation of PRML in a Rigid disc Drive", published in IEEE Transactions on Magnetics, vol. 27, No. 6, November 1991, suggests a three tap transversal filter comprising a fixed center tap and symmetric side taps in order to constrain the phase response of the equalizer filter except in terms of a fixed group delay. Constraining the phase response of the adaptive equalizer in this manner, however, is a very sub-optimal method for attenuating interference from the timing recovery and gain control loops. Furthermore, it significantly reduces control over the adaptive filter's phase response, thereby placing the burden of phase compensation on the analog equalizer.
Yet another problem associated with conventional equalizer filters is an inherent limitation on its order (i.e., the number of coefficients): because the adaptive equalizer is inside the timing recovery feedback loop, its order must be limited to minimize the associated transport delay. Compensating for the deficiencies of the discrete time equalizer requires filtering the analog read signal with a higher order analog equalizer prior to the timing recovery loop, which is undesirable.
Still another aspect of prior art sampled amplitude read channels addressed by the present invention is the overall computation speed and power dissipation of the components therein, particularly the FIR filters. Conventional FIR filters that operate according to a binary number system require more time and power to perform the compute intense multiplication and add operations necessary to filter a signal in discrete time. Minimizing power dissipation while maximizing throughput are significant design considerations, especially in portable applications and/or applications that require a high data transfer rate.
Thus, there is a need for a faster, more power efficient sampled amplitude read channel that overcomes the above problems associated with adaptive equalization and timing recovery.

Sampled amplitude read channel employing a residue number system FIR filter in an adaptive equalizer and in interpolated timing recovery


A communications cable management system includes a support structure and a door assembly. The door assembly includes at least two first latch structures and at least two second latch structures each selectively positionable in a latched position to secure the door body to the support structure. First and second actuators are operable by a user to selectively latch the latch structures such that a door body is secured in a closed position on the support structure, the door body can be removed from the support structure, the door body can be pivoted open about the first pivot axis, or the door body can be pivoted open about a second pivot axis.

Communications cable management systems are commonly used to route, arrange and manage connections with communications cables. Such communications cable management systems may include communications racks, cabinets or wall-mounted systems (such as terminal block panels and spacer brackets). Terminal block panels (which may also be referred to as patch panels, back panels, or cross-connects) are hardware devices used in the communication equipment industry to connect cables to terminal equipment contained within an environment (e.g., office suites, apartment buildings, etc.). The panels are typically available to accommodate 900 wire pair and 300 wire pair configurations and are often mounted to a wall situated within a closet in the equipment environment. Exemplary panels contain a securing surface that is affixed or fastened to the wall, and a mounting surface configured into a plurality of tangs upon which connecting devices such as connecting blocks are secured. The connecting blocks interface with data carrying cables, such as exterior cables that route data to and from the environment, to cables connected to, for example, terminal devices.
In some cases, two or more back panels are mounted in side-by-side, spaced apart arrangement. A spacer bracket is mounted in the space between the back panels. The spacer bracket may be secured to the wall and/or one or both of the back panels. The spacer bracket defines a cord trough through which cords may be routed for connecting connection blocks of one of the back panels with connection blocks of the other back panel. In some cases, a door panel is mounted on the spacer bracket to protect and hide the cords in the cord trough. According to one known construction available from Chatsworth Products, Inc., the door panel is secured to the spacer bracket by four plastic quarter turn fasteners located along each side edge of the door panel. The door panel can be removed by releasing (i.e., by turning to an open position) all four fasteners. Alternatively, the user may release the two fasteners on either side, and pivot the door panel about the other two plastic fasteners.

Door assemblies and communications cable management systems including the same


A system and method for messaging subscription management by subscribing a subscriber to a publisher, providing a broker brokering message flow between the publisher and the subscriber whereby the publisher publishes information to the broker which then forwards the information to the subscriber, and filtering messages whereby any messages not originating from the publisher are filtered out. The filtering may comprise modifying at the publisher a filter supplied by the subscriber and sending the modified filter to the broker, or may comprise modifying at the subscriber a filter and sending the modified filter to the broker.

This invention relates to subscription management in messaging systems.
Publish/Subscribe (or Event Notification) is a well-known messaging pattern where clients interested in information available from a source "subscribe" to the source. When information is available the source then "publishes" the information to the client (which is commonly and hereafter referred to as the "sink").
There are two common variants of this pattern:
a) The "direct" case, where the sink is registered directly with the source. In this pattern the subscriber identifies each source it is interested in, and then registers a separate subscription with each. It only receives messages from sources with which it has registered.
b) The "brokered" case, where the sink is registered with an intermediary "broker", not with the true source. The true source publishes information to the broker, which then forwards the information to the sink.
In the brokered case (b) the subscriber does not have to be aware of the identity or location of the true source (publisher), since it never interacts with it directly. The brokered case also has the characteristic that a sink registered against the broker will receive messages from any source (publisher) which is sending relevant messages to the broker. In some situations, this may be exactly what is wanted. However, in some applications (e.g., systems management) the sink might only be interested in messages from a particular set of sources. For example, the sink might be a monitoring application that only wants to monitor 3 out of a set of 60 similar resources.
The direct case (a) allows the sink to control exactly which source(s) it gets messages from. However it can result in a lot of logical connections (if there are m sources and n sinks, we have a total of n*m connections), and it requires each source to maintain a list of subscriptions and each source to distribute messages to multiple recipients.
A need therefore exists for a system and method for subscription management in a messaging system wherein the above mentioned disadvantage(s) may be alleviated.

System and method for subscription management in a messaging system

International Business Machines Corporation


A dual port memory 50 comprises two decoders 9a, 9b, and two sense amplifiers 14a, 14b, associated with a memory cell array 100. The dual port memory 50 can be accessed by a CPU 6 of the A system side and a CPU 7 of the B system side simultaneously. The occurrence of contention between the accesses of CPUs 6 and 7 with respect to the same memory cell is detected by an access contention detecting circuit 51. In response to contention detection, a control signal generating circuit 52 generates various control signals. The A port side and B port side of the dual port memory 50 each is provided with write data latches 53a, 53b, read data latches 54a, 54b, switches 55a-57b, select switches 58a, 58b, and tri-state buffers 59a and 59b, respectively, to perform arbitration all the time of access contention, in accordance with the control signal from control signal generating circuit 52.

1. Field of the Invention
The invention relates generally to a dual port memory comprising two input/output ports, and more particularly to a dual port memory such as one used in data transmission between two microprocessor systems.
2. Description of the Background Technology
FIG. 1 is a block diagram showing a general utilization configuration of a dual port memory. In the figure, a dual port memory 1 has two input/output ports (one is called A port, while the other is called B port hereinafter). A port is connected to an A system 3 via a system bus 2. B port is connected to a B system 5 via a system bus 4. The A system 3 and B system 5 may be any type of system that processes data. For example, in many cases, it is a microprocessor system that includes a CPU. The dual port memory 1 comprises an internal memory means. This memory means is capable of being accessed separately by A system 3 and B system 5.
The above dual port memory 1 is often used for data reception/transmission between A system 3 and B system 5. For example, where A system 3 and B system 5 operate asynchronously, it is difficult to perform data transmission directly between each system. By transmitting data via dual port memory 1, it is possible for each system to input/output data when necessary. Consequently, the throughput of the system will improve. Furthermore, the systems 3 and 5 operate together to allow for the development of a larger system.
There are two conventional access methods for the dual port memory, as will be described hereinafter.
FIG. 2A shows the first access method, in which an address data applied to A port from a CPU 6 of the A system (hereinafter called A port address data) and an address data applied to B port from a CPU 7 of the B system (hereinafter called B port address data) are multiplexed by an address multiplexer 8 to be applied to a decoder 9. The decoder 9 selects one memory cell of a memory cell array 10, in accordance with either A port address data or B port address, applied via address multiplexer 8. The memory cell array 10 has a plurality of memory cells arranged in a matrix manner along the row and column directions. Each row of memory cell 11 has one word line 12 arranged as shown in FIG. 2B. Also, each column of memory cell 11 has one bit line 13. A sense amplifier 14 is dividedly arranged by each bit line 13. Through this divided sense amplifier 14, write data is applied to bit line 13 from CPU 6 or 7, or data read out into bit line 13 is provided to CPU 6 or 7. The decoder 9 selectively activates one of the plurality of word lines 12 in accordance with the applied data. This causes a transfer gate transistor 15 of the selected row to attain a conductive state. Also, decoder 9 selectively enables one of the divided sense amplifiers 14 in accordance with the applied data. This causes the selected memory cell 11 to be connected to CPU 6 or 7 via the corresponding transfer gate transistor 15. As a result, the reading and writing of data, with respect to the selected memory cell 11, is possible.
The second access method is shown in FIG. 3A. A decoder 9a and a sense amplifier 14a for A port, and a decoder 9b and a sense amplifier 14b for B port are associated with a memory cell array 100. The A port address data from CPU 6 is applied to decoder 9a, while B port address data from CPU 7 is applied to decoder 9b. The memory cell array 100 has a plurality of memory cell arranged in a matrix manner along the row and column directions, similar to the memory cell array 10 of FIG. 2A. It should be noted that memory cell array 100 has two word lines 12a and 12b arranged for each row of memory cell 11, and also two bit lines 13a and 13b arranged for each column, as shown in FIG. 3B. Also, two transfer gate transistors 15a and 15b are provided for one memory cell 11. Word line 12a, bit line 13a, and transfer gate transistor 15a are associated with A port. Word line 12b, bit line 13b, and transfer gate transistor 15b are associated with B port. Thus, CPUs 6 and 7 can access, memory cell array 100 at the same time, because the dual port memory of FIG. 3A has the access systems of A port and B port in complete independence.
Since the dual port memory of FIG. 3A is capable of being accessed by CPUs 6 and 7 simultaneously, there will be some cases where access contention from both CPUs 6 and 7 occurs, with respect to the same memory cell. On such an occasion, the state as shown in FIG. 4 occurs in accordance with the type of access from CPUs 6 and 7. First, when read access contention occurs with respect to the same memory cell (the case of FIG. 4 (1)), the data read out from the selected memory cell is
normal Next, when read access and write access contention occurs with respect to the same memory cell (the cases of FIG. 4 (2), (3)), the data read out from the selected memory cell is indefinite (that is to say, whether normal or abnormal, the data cannot be identified), while the data written into the selected memory cell is normal. When contention of write access operation occurs with respect to the same memory cell (the case of FIG. 4 (4)), the data written into the selected memory cell is indefinite.
To solve the above access contention problems, an access contention arbitrating circuit, described hereinafter, was proposed to be provided internally or externally of the dual port memory. When access contention from the systems occurs, the access arbitrating circuit grants an access right to one of the systems, according to a predetermined priority, and temporary halts the access from the other systems. Afterwards, the temporarily halted access is started when a non-contention state is achieved.
FIG. 5 is a system configuration diagram of a dual port RAM incorporating an access arbitrating circuit such as the one disclosed in Japanese Patent Laying-Open No. 62-175992.
The dual port RAM, of FIG. 5 has an output data control circuit 20, and D type flipflops 21a and 21b provided as the access arbitrating circuit. The remaining structure is similar to that of the dual port memory of FIG. 3A, with the same reference numerals being used for the corresponding portions. The output data control circuit 20 is supplied with A port address data A(A) from CPU 6, B port address data A(B) from CPU 7, A port write signal WE (A), and B port write signal WE (B). The output data control circuit 20 generates output data control signals .phi.A and .phi.B in accordance with the applied address data and write signals. Output data control signal .phi.A is applied to D flipflop 21a. Output data control signal .phi.B is applied to D type flipflop 21b. D type flipflop 21a fetches and holds A port output data Dout (A), applied from sense amplifier 14a in response to output data control signal .phi.A. The Q output of D type flipflop 21a is applied to CPU 6 as A port external output data Dout (A)*. D type flipflop 21b fetches and holds B port output data Dout (B) from sense amplifier 14b, in response to output data control signal .phi.B. The Q output of D flipflop 21b is applied to CPU 7 as B port external output data Dout (B)*.
FIG. 6 shows a further detail of the output data control circuit 20 of FIG. 5. The output data control circuit 20 comprises exclusive logical sum gates 22.sub.0 -22.sub.n, OR gate 23, and NOR gates 24a, 24b. The exclusive logical sum gates 22.sub.0 -22.sub.n each detects whether the logic of each address signals A0 (A)-An (a) included in A port address data A (A) coincides with the logic of
each address signal A0 (B)-An (B) included in B port address data A (B). OR gate 23 detects whether A port address data A (A) coincides with B port address data A (B) as a whole, by taking the logical sum of the outputs of exclusive logical sum gates 22.sub.0 -22.sub.n. NOR gate 24a receives the output of OR gate 23 and B port write signal WE (B) to generate an output data control signal .phi.A for A port. NOR gate 24b receives the output of OR gate 23 and A port write signal WE (A) to generate an output data control signal .phi.B for B port.
FIG. 7 shows the detailed structure of the D type flipflop 21b of FIG. 5. D type flipflop 21b comprises an inverter 25, and NOR gates 26-29. NOR gates 28 and 29 form the data holding circuit, with each output thereof applied to one input end of the other NOR gates 29 or 28. B port output data Dout (B) from sense amplifier 14 is applied to one input end of NOR gate 26, as well as to one input end of NOR gate 27 via inverter 25. The output data control signal .phi.B from output data control circuit 20 is applied to each other input end of NOR gates 26 and 27. Each of the outputs of NOR gates 26 and 27 are applied to the other input end of NOR gates 28 and 29. NOR gates 26 and 27 determine whether to update the data held in the data holding circuit formed by NOR gates 28 and 29, in response to output data control signal .phi.B.
The structure of D type flipflop 21a is similar to that of the above mentioned D type flipflop 21b, except that the input signal and the output signal are different to those of the above mentioned D type flipflop 21b.
FIG. 8 shows the operation in the case of contention between write access of the A port side and read access of the B port side with respect to the same memory cell, in the conventional dual port RAM shown in FIGS. 5-7. The operation at the time of access contention in the above mentioned dual port RAM is described in reference to the timing chart of FIG. 8.
First, the coincidence of A ports address A (A) with B port address A (B) is detected by exclusive logical sum gates 22.sub.0 -22.sub.n, OR gate 23. This causes the output of OR gate 23 to attain the L level. Upon the start of write operation of the A port side, A port write signal WE (A) is brought to the L level, to turn output data control signal .phi.B to the H level in response thereto. As a result, D type flipflop 21b has the update operation of the holding data inhibited. Therefore, even though the stored data of the selected memory cell is overwritten by the write operation of the A port side, D type flipflop 21b continues to hold the old data (the data before update). Accordingly, external output data Dout (B) * of B port is held steady. Afterwards, when the write operation of the A port side terminates, A port write signal WE (A) is turned to the H level, with output data control signal .phi.B brought to the L level in response thereto. This cancels the inhibition of data update in D type flipflop 21b. Therefore, the holding data of D type flipflop 21b is updated by the output data Dout (B) of B port. That is to say, external output data Dout (B) * of B port is updated to a new data at this time.
In the dual port RAM of FIGS. 5-7, external output data Dout (B) * of B port is updated to a new data (the data newly written into the memory cell) after the termination of write operation of A port, when contention between write of the A port side and read access of the B port side occurs with respect to the same memory cell. Therefore, B system must queue for the fetching of the new data until the write access of A system is terminated. In general, when access contention occurs, a BUSY signal is sent to A system or B system from dual port RAM to hold the access operation of A system or B system on standby. (This is not disclosed in Japanese Patent Laying-Open No. 62-175992). In FIG. 8, the access operation of B system responds to a BUSY signal supplied from B port to be held on standby until the write operation of A system ends. FIG. 9 is a system structure diagram of a conventional multiport memory incorporating an access contention arbitrating circuit such as Japanese Patent Laying-Open No. 63-183678. A multiport memory 34 has three input/output ports, A port, B port, and C port, so that access is possible from three CPUs 31, 32 and 33 simultaneously. In multiport memory 34, address latches 35a, 35b, and 35c latch the address data provided from CPUs 31, 32, and 33, respectively. An address selector 36 selects the address data to be applied to a memory portion 37 from the address data held in address latches 35a-35c. Write data latches 38a, 38b, and 38c latch the write data provided from CPUs 31, 32, and 33, respectively. The write data latched by write data latches 38a, 38b, and 38c are provided to memory portion 37 via write data drivers 39a, 39b, and 39c, respectively. The data read out from memory portion 37 are provided to CPUs 31, 32 and 33 via data ports 40a, 40b, and 40c, respectively. A memory control portion 41 controls address latches 35a-35c, write data latches 38a-38c, data write drivers 39a-39c, data ports 40a-40c, and memory portion 37.
The operation of the conventional multiport memory of FIG. 9 will be explained. When access contention occurs from a plurality of CPUs, memory control portion 41 holds address data and write data in each of latches 35a-35c, 38a-38c, and performs write operation into memory portion 37 after the completion of the other access.
In the multiport memory of FIG. 9, if write access occurs successively from a CPU where a write access is already waiting in the multiport memory, the write access of that CPU will wait at the CPU side.
The aforementioned access arbitrating circuit used in conventional dual port memories or multiport memories may queue the access operation with respect to the system when access contention rises between systems. This results in a disadvantage, whereby the conventional dual port memory could be used only if a function that can cope with the access standby request from the dual port memory (a READY function for example) is provided. Another problem is that the application is limited to the industrial field where some standby time is allowed.
In a system where real time processing is always performed, operation must be realized at identical timing by all means. In such a system, if the timing of standby generation is not known, a dual port memory allowing the generation of such standby time could not be used, no matter how short the standby time.
Furthermore, microcomputers used in small size systems sometimes had a READY terminal (the terminal where standby request signal is applied) deleted, because an increase in the number of LSI terminals leads to increase in cost. In such a system, a dual port memory could not be used, even though it is effective for improving the throughput of the system.


Red, blue and green lasers respectively emit a plurality of red, blue and green laser beams having respective output powers. The beams are optically focused and collinearly arranged to form a composite beam which is swept by a pair of scan mirrors in a pattern of scan lines on a projection surface, each scan line having a number of pixels. A controller causes selected pixels to be illuminated, and rendered visible, by the composite beam to produce an image. A safety circuit detects a malfunction of at least one of the lasers and the scan mirrors, and deenergizes the at least one of the lasers and the scan mirrors upon detection of the malfunction.

1. Field of the Invention
The present invention generally relates to projecting a two-dimensional image of high quality, especially in color, using high power lasers and scan mirror drives, without exceeding governmental regulatory exposure limits on laser power, thereby enhancing viewer and bystander safety during image projection.
2. Description of the Related Art
It is generally known to project a two-dimensional image on a projection surface based on a pair of scan mirrors which oscillate by respective mirror drives over scan angles in mutually orthogonal directions to scan a laser beam over a raster pattern comprised of a plurality of scan lines. The image is created in the raster pattern by modulating a laser on and off at selected times, thereby illuminating selected pixels and not illuminating other pixels in each scan line. Color images can be obtained by modulating red, blue and green lasers and illuminating the selected pixels by superimposing one or more of the red, blue and green laser beams emitted by the respective lasers on a respective pixel to obtain a desired color.
The output power of each laser must be monitored for safety. Although the image brightness is enhanced when the output power of each laser is increased, government regulatory safety standards dictate the maximum power output of each laser for human safety. Each of the output powers of the red, blue and green laser beams must therefore be less than a maximum value. Some of these standards require that the output power of each laser does not exceed regulatory limits even when control circuitry that normally regulates the laser output power fails.
For example, an internal monitor photodiode inside the laser housing is normally operative for monitoring the laser output power. The monitor photodiode is part of a feedback circuit for maintaining the laser output power constant during operation. If the monitor photodiode were to fail, or to become electrically disconnected from the feedback circuit, then the feedback signal would be lost, and the feedback circuit would increase the laser output power, possibly to a level exceeding regulatory limits and compromise viewer and bystander safety.
The oscillation of each mirror must also be monitored for safety. For example, the scan angle of each mirror must be greater than a minimum value to insure that the drive for the respective mirror has not malfunctioned or stalled. This would cause the laser beams to dwell in an angular area smaller than the desired scan angle, or even remain stationary, and exceed the output power regulatory limits at that smaller angular area since the output power is more intense.

Arrangement for and method of projecting an image with safety circuitry


A copolymer is capable of being immobilized on a base material while maintaining a high antithrombotic property persistently without having to introduce heparin or an anticoagulant drug to the surface thereof. The copolymer includes monomer unit A, monomer unit B, and monomer unit C, wherein monomer unit C has a mole fraction of 0.5-40% with respect to the total amount of all constituent monomer units.

Medical materials and medical devices that come into contact with blood (for example, artificial kidneys, artificial lungs, artificial blood vessels, artificial valves, stents, stent grafts, catheters, thrombus capture devices, angioscopes, suture threads, blood circuits, tubes, cannulas, blood bags, and syringes) are required to have potent antithrombotic properties to prevent hypofunction due to coagulation of blood. Heretofore, to improve the antithrombotic properties of medical materials and medical devices, there has been employed a technique of imparting heparin or a heparin derivative as an anticoagulant drug to a surface of a base material.
An example of a reported method of imparting heparin or a heparin derivative to a surface of a base material is a method of immobilizing heparin or a heparin derivative by ionic bond with a positively charged cationic compound introduced onto a surface of a base material (Japanese Patent Nos. 4152075, 3497612 and 4273965).
Meanwhile, as a method of bonding an antithrombotic compound other than heparin or a heparin derivative to a surface of a base material, there has been reported a method of immobilizing a compound having antithrombin activation performance onto a surface of a base material (International Publication Nos. 2012/176861 and 2015/080176).
Moreover, there has also been reported a method of crosslinking and immobilizing a vinylpyrrolidone/vinyl acetate copolymer having platelet adhesion suppressing performance onto a surface of a base material made of a hollow fiber membrane by radiation irradiation in water (Japanese Patent Nos. 4888559 and 5857407).
The technique of imparting heparin or a heparin derivative to a surface of a base material as in JP '075, JP '612 and JP '965, however, cannot be used in patients with heparin-induced thrombocytopenia or patients with bleeding. Moreover, since heparin and heparin derivatives are animal-derived components, attention must be paid to administration and handling of such compounds.
In addition, the technique of imparting a compound having antithrombin activation performance to a surface of a base material described in WO '861 and WO '176 is difficult to use in patients with bleeding because it may be difficult to stop bleeding during the treatment if the compound elutes. Moreover, the compound having antithrombin activation performance is much more expensive than polymer compounds and the like because it is an anticoagulant drug.
The vinylpyrrolidone/vinyl acetate copolymer described in JP '559 and JP '407, when being used in a medical device that may be used for over a day in the body such as a stent or a catheter may cause thrombosis on a surface of a base material due to long-time use. In addition, the copolymer can be immobilized onto the surface of the base material only by crosslinking and immobilization through radiation irradiation. Therefore, the copolymer may not sufficiently exhibit antithrombotic properties due to three-dimensional crosslinking or modification thereof.
It could therefore be helpful to provide a copolymer that can be immobilized onto a base material while maintaining potent antithrombotic properties persistently without the need for introduction of heparin or an anticoagulant drug onto a surface of a base material, and a medical material containing the copolymer.

Copolymer and medical material containing the same


The present invention relates to a method of controllably conveying an object. The method comprises the steps of determining an intended conveying of the object, dividing, on the basis of a predefined profile for a second section (G) of the conveying, the intended conveying of the object into a first section (F) and a second section (G), conveying the object the first section (F), conveying the object the second section (G), and, during the second section (G) of the conveying of the object, registering an actual position of a predefined element linked to the object. The present invention further relates to an apparatus for reducing this method into practice.

It has long been known to produce food packages of different types from packaging laminates. One commercially viable method is to continuously unite the longitudinal edges of a web and thereby form the web into a tube which is thereafter filled and sealed and severed transversely of the longitudinal direction of the web so that a number of cushion-shaped individual packages are formed. Depending upon the mutual orientation of the transverse seals and depending upon subsequent final folding, these packages may be given different configurations. Examples of such configurations are the tetrahedral package which is marketed by Tetra Pak under the name Tetra Classic®. Another example of such a package is the brick-shaped package which is marketed by Tetra Pak under the name Tetra Brik®. This generic type of package is well-known both to persons skilled in the art and consumers and will not be described in greater detail here. The brief description, given by way of introduction, of the method of realising such packages is also well-known to a person skilled in the art and will not be described in greater detail either. Only those details of such a filling machine as are encompassed by the inventive concept as herein disclosed and an understanding thereof will be described in greater detail.
During the last decade, it has become increasingly common practice to provide, above all, the traditional, brick-shaped packages with different types of opening arrangements. One type of opening arrangement is described in EP 949 992 A1. This opening arrangement is realised in that a hole is punched through the packaging laminate, whereafter this hole is covered by an opening arrangement which is injection moulded straight over the hole. The injection moulding is put into effect in that a moulding tool is placed on either side of the packaging laminate so that the mould cavity formed by the moulding tools completely encloses the previously punched hole. By injecting hot, mouldable plastic into the entire mould cavity, the hole is sealed. This type of opening arrangement is normally formed with a weaker portion which extends about a greater part of the circumference of the opening arrangement so that a consumer may open the package by breaking a part of the opening arrangement along the weakening.
In order to realise such an opening arrangement, it is important to be able to place the hole punched in the web in the correct position in the injection moulding station. EP 1 110 867 A1 describes how it is possible to employ the hole as a reference point for positioning thereof in the injection moulding station. The traditional method prior to this was to employ some form of guide mark in order to position the packaging laminate web both before the punching operation and then before the injection moulding operation. One problem which may thereby occur is that a sum total is made of two error tolerances so that the opening arrangement is not injection moulded over the hole within its mutual tolerances. By measuring the position of the hole for positioning before the injection moulding, this tolerance accumulation chain has been eliminated.
EP 1 110 867 describes a set of three punches and three injection moulding stations where three mutually subsequent packaging blanks are punched simultaneously and three mutually subsequent packaging blanks are provided with opening arrangements by injection moulding simultaneously.
Recently, there has been an increasing demand for small packages, so-called portion packages, for example of the order of magnitude of 150 ml and upwards. One problem which has thereby occurred is that the distance between the hole positions of two mutually adjacent packaging blanks will be so slight that it is difficult to construct injection moulding units which can be positioned so close to one another. EP 1 249 399 describes how this problem has been solved by first punching, for example, every second packaging blank and thereafter indexing one step so that the other packaging blanks are punched. Once all packaging blanks which lie adjacent one another have been punched, a longer indexing is put into effect (for example five steps) so that all punched packaging blanks are conveyed past the punch units.
In connection with this type of indexing, with short and long index steps, it has nevertheless been possible to observe a difficulty in achieving an acceptable level of repeatability in the positioning. Above all, this problem has been observed at high machine speeds. The indexing principle described in EP 1 249 399 functions excellently, but for certain machine construction and certain speeds the idea needs to be further developed in order to be able to meet the requirements for correct positioning within very narrow positioning tolerances.

Method of controllably conveying an object and an apparatus for conveying a web


The fuel injector for a combustor of a gas turbine engine of the high shear design type is configured to include two swirlers with passages where the vanes in the inner swirler of the inner swirler in the passage which is closest to the centerline of the fuel nozzle includes a judiciously located twist and together with the proper flow ratio between the two swirl passages and the proper swirl angle of the flow stream in each of the passages provide an enhanced fuel injector with improved lean blowout and high altitude relight characteristics while assuring a stable recirculation region in the combustion zone.

As is well known in the gas turbine engine technology it is desirable to operate the combustor at optimum efficiency while achieving good lean blowout, altitude relight, void of smoke and pollutants while being able to increase the temperature of the hot gases while maintaining the integrity of the combustor liner as well as being cost effective. Scientists and engineers have been experimenting with the designs of the fuel nozzles for many years in attempts to maximize the efficacy of the combustor. This invention constitutes an improvement over the fuel nozzle described in U.S. Pat. No. 5,603,211 granted to Charles B. Graves, the inventor of this patent application, on Feb. 18, 1997 entitled "Outer Shear Layer Swirl Mixer For A Combustor" which is commonly assigned to United Technology Corporation. As disclosed in the U.S. Pat. No. 5,603,211, supra, the fuel nozzle includes a swirler design that includes three air swirling passages, namely, a center duct and two annular ducts located radially outward from the fuel injector. These passages include vanes for swirling the incoming air and are tailored to have significantly different swirl angles to yield low smoke production and high relight stability in high temperature rise combustors. In the construction of the fuel nozzle in the U.S. Pat. No. 5,603,211, supra, the high swirl passage was confined to the vicinity of the fuel injector and a counter-rotating annular passage surround it which provided both the features of a high swirl and low swirl device.
While this structure in the U.S. Pat. No. 5,603,211, supra, produced high swirl angles along the centerline and low swirl angles along the injector prefilmer, in evaluating this device certain disadvantages were noted. Namely, the mixing shear layer between the two counter-rotating passages appeared to impede the transport of the spray to the prefilmer, and in general, the less the amount of flow in the counter rotating passage the better the injector performed. It was also noted that the mixing of the passages produced a pressure loss which dictated that the vane areas needed to be increased to levels larger than what would normally be required in a standard high shear design.
In addition to the above-referred to patent there are a plethora of fuel nozzles that are disclosed in the prior art that include swirlers and injectors for combustors of gas turbine engines and all of which provide recirculation zones for stabilizing combustion. Examples of prior art fuel nozzles are disclosed in U.S. Pat. Nos. Re. 30,160 reissued in Nov. 27, 1979 and granted to Emory, Jr. et al entitled Smoke Reduction Combustion Chamber, U.S. Pat. No. 3,570,242 granted to Leonardi on Mar. 16, 1971, entitled Fuel Premixing For Smokeless Jet Engine Main Burner, U.S. Pat. No. 4,991,398 granted to Clark et al on Feb. 12, 1991 entitled Combustor Fuel Nozzle Arrangement all of which are commonly assigned to United Technologies Corporation, the assignee of this patent application. Additional patents of interests are U.S. Pat. No. 3,853,273 granted to Bahr et al on Dec. 10, 1974 entitled Axial Swirler Central Injection Carburator, U.S. Pat. No. 3,901,446 granted to Petreikis, Jr. on Aug. 26, 1975 entitled Induced Vortex Swirler, U.S. Pat. No. 4,194,358 granted to Stenger on Mar. 25, 1980 entitled Double Annular Combustor Configuration and U.S. Pat. No. 4,842,197 granted to Simon et al on Jun. 27, 1989 entitled Fuel Injection Apparatus And Associated Method.
I have found that I can provide a fuel nozzle having a fuel injector at the center, an inner swirl passage adjacent to the fuel injector and coaxial therewith and an annular swirl passage concentrically mounted relative to the inner passage and having the vanes in the inner swirl passage contoured with a discretely shaped twist which will not only duplicate the advantages of the structure disclosed in the U.S. Pat. No. 5,603,211, supra but will obviate the disadvantages thereof. Obviously, the elimination of the third passage will not only lessen the complexity of the design but also will reduce costs.

Radial inlet swirler with twisted vanes for fuel injector


An address signal storage circuit of a data repair controller is disclosed including: a level stabilizer for stabilizing a level of an input signal to a constant level by a level control signal applied from the exterior according to the connection and disconnection of a fuse; a control signal generator for generating first and second control signals by a signal stabilized from the level stabilizer; and a signal storage portion for generating either a signal of a constant level by the first control signal generated from the control signal generator after disabled by a driving control signal applied from the exterior, or an inversion signal of the signal generated when disabled by storing an address signal of a prescribed level by the first and second control signals after enabled by the driving control signal.

The present invention relates to an address signal storage circuit of a data repair controller. More particularly, the present invention relates to such an address signal storage circuit of a data repair controller which is disabled by an external control signal to reduce current dissipated during enabling when the data repair operation of a redundancy circuit is controlled to be disabled, and stably stores an address signal of a prescribed level according to the connection and disconnection of a fuse when the data repair operation of the redundancy circuit is controlled to be enabled.
Referring to FIG. 1, there is shown a prior art address signal storage circuit of a data repair controller. A level stabilizer 1 stabilizes an output signal level to a constant level by a level control signal LC applied from the exterior when a fuse is shorted. A control signal generator 2 generates control signals SWS1 and SWS2 for storing an address signal AD of a prescribed level by the output signal of the level stabilizer 1 according to the connection and disconnection of the fuse. A signal storage portion 3 stores the address signal AD of the prescribed level by the control signals SWS1 and SWS2 generated from the control signal generator 2.
The level stabilizer 1 includes PMOS transistors PM1 and PM2 having respective source electrodes commonly connected to a power voltage VCC terminal, respective gate electrodes respectively connected to the level control signal LC and the control signal SWS1 of the control signal generator 2 and respective drain electrodes commonly connected to one terminal of the fuse, and a PMOS condenser MC having drain and source electrodes commonly connected to the power voltage VCC terminal.
The control signal generator 2 includes an inverter I1 for generating the control signal SWS1 by inverting the output signal of the level stabilizer 1 according to the connection and disconnection of the fuse, and an inverter I2 for generating the control signal SWS2 by inverting the control signal SWS1 generated from the inverter I1.
The signal storage portion 3 has a transmission gate TG1 switched by the control signals SWS1 and SWS2 generated from the inverters I1 and I2 of the control signal generator 2 to generate the address signal AD of the prescribed level, and a transmission gate TG2 switched by the control signals SWS1 and SWS2 to generate an inverted address signal which has passed through an inverter I3.
Referring to FIG. 2, another prior art address storage circuit of the data repair controller is shown. Level stabilizers 10 and 20 stabilize an input signal level to a constant level when fuses FUSE1 and FUSE2 are in the connected state. A signal storage portion 30 generates a signal of a constant level irrespective of address input signals Ai and /Ai after disabled by signals stabilized by the level stabilizers 10 and 20 when the fuses FUSE1 and FUSE2 are in the connected state, and generates an inversion signal of the signal generated when disabled by storing the input address signal Ai of a prescribed level after enabled by an input signal when the connected state of the fuses FUSE1 and FUSE2 is different.
The level stabilizer 10 includes an NMOS transistor NM1 having a drain electrode connected to one terminal of the fuse FUSE1 and an input terminal of an inverter I10, a gate electrode connected to an output terminal of the inverter I10, and a source electrode connected to a ground voltage VSS terminal.
The level stabilizer 20 includes an NMOS transistor NM6 having a drain electrode connected to one terminal of the fuse FUSE2 and an input terminal of an inverter I11, a gate electrode connected to an output terminal of the inverter I11, and a source electrode connected to the ground voltage VSS terminal.
In the signal storage portion 30, a PMOS transistor PM1 has a source electrode commonly connected to the power voltage VCC terminal and the other terminals of the fuses FUSE1 and FUSE2, and a gate electrode connected to the drain electrode of the NMOS transistor NM1 of the level stabilizer 10. A PMOS transistor PM2 has a source electrode connected to a drain electrode of the PMOS transistor PM1, and a gate electrode connected to the address signal Ai. An NMOS transistor NM2 has a drain electrode commonly connected to a drain electrode of the PMOS transistor PM2 and an output signal OS, and a gate electrode connected to the inverted address signal /Ai. An NMOS transistor NM3 has a drain electrode connected to a source electrode of the NMOS transistor NM2, a gate electrode connected to the gate electrode of the PMOS transistor PM1, and a source electrode connected to the ground voltage VSS terminal. A PMOS transistor PM3 has a source electrode connected to the source electrode of the PMOS transistor PM1, and a gate electrode connected to the drain electrode of the NMOS transistor NM6 of the level stabilizer 20. A PMOS transistor PM4 has a source electrode connected to a drain electrode of the PMOS transistor PM3, and a gate electrode connected to the inverted address signal /Ai. An NMOS transistor NM4 has a drain electrode commonly connected to a drain electrode of the PMOS transistor PM4 and the output signal OS, and a gate electrode connected to the address signal Ai. An NMOS transistor NM5 has a drain electrode connected to a source electrode of the NMOS transistor NM4, a gate electrode connected to the gate electrode of the PMOS transistor PM3, and a source electrode connected to the ground voltage VSS terminal.
The operation of the address signal storage circuits of the data repair controller constructed in the above-mentioned way will now be described.
Referring again to FIG. 1, it is assumed that an output signal FOUT of the signal storage portion 3 should be set to logic "high" in order to control the data repair operation of a redundancy circuit (not shown) to be disabled. The fuse is externally controlled to a connected state.
Since the fuse is in the connected state, the ground voltage VSS is applied to the node N1 and the node N1 is set to logic "low". The inverter I1 of the control signal generator 2 generates the control signal SWS1 of logic "high", and the inverter I2 generates the control signal SWS2 of logic "low". The transmission gate TG1 of the signal storage portion 3 receives the control signal SWS2 of logic "low" generated from the inverter I2 and the control signal SWS1 of the logic "high" generated from the inverter I1 through PMOS and NMOS terminals, respectively. Therefore, the transmission gate TG1 is turned on and generates the input address signal AD of logic "high". Thus, the redundancy circuit is disabled by the address signal AD of logic "high" generated from the transmission gate TG1 of the signal storage portion 3. Consequently, in order to control the data repair operation of the redundancy circuit to be disabled, the signal storage portion 3 stores the address signal AD of logic "high".
On the other hand, in order to control the data repair operation of the redundancy circuit to be enabled, it is assumed that the output signal FOUT of the signal storage portion 3 should be set to logic "low". If the fuse is in the connected state, the transmission gate TG1 of the signal storage portion 3 is turned on by the control signals SWS1 and SWS2 generated from the control signal generator 2, as described above, and generates the input address signal AD of logic "low".
If the fuse is shorted, the node N1 is set to logic "high" by the PMOS transistors PM1 and PM2 and the PMOS condenser MC. The inverter I1 generates the control signal SWS1 of logic "low", and the inverter I2 generates the control signal SWS2 of logic "high". The transmission gate TG2 of the signal storage portion 3 receives through a PMOS terminal the control signal SWS1 of logic "low" generated from the inverter I1 and through an NMOS terminal the control signal SWS2 of logic "high" generated from the inverter I2. Therefore, the transmission gate TG2 is turned on and generates the output signal FOUT of logic "low" which inverts the address signal AD of logic "high" by the inverter I3.
Consequently, in order to control the data repair operation of the redundancy circuit to be disabled, the signal storage portion 3 stores the input address signal AD of logic "high" while the fuse is connected. In order to control the data repair operation of the redundancy circuit to be enabled, the signal storage portion 3 stores the input address signal AD of logic "low" while the fuse is connected, and stores the input address signal AD of logic "high" while the fuse is shorted.
Referring now to FIG. 2, in order to control the data repair operation of the redundancy circuit to be disabled, the fusses FUSE1 and FUSE2 are controlled to the connected state. Since the fuse FUSE1 is in the connected state, a node N1 is set to logic "high", and the logic "high" voltage across the node N1 is applied to the gate electrode of the NMOS transistor NM1 through the inverter I10. Therefore, the NMOS transistor NM1 is turned off and that node N1 is in the stabilized logic "high" voltage. Moreover, a node N2 is set to logic "high" since the fuse FUSE2 is in the connected state, and the logic "high" voltage across the node N2 is applied to the gate of the NMOS transistor NM6 through the inverter I11. Hence, the NMOS transistor NM6 is turned off and the that node N2 is in the stabilized logic "high" voltage.
The logic "high" voltages across the nodes N1 and N2 are applied to the gate electrodes of the NMOS transistors NM3 and NM5, respectively. The NMOS transistors NM3 and NM5 are turned on and the output signal OS is set to logic "low" irrespective of the input address signals Ai and /Ai. Thus, the redundancy circuit is disabled by the output signal of logic "low" generated from the signal storage portion 30.
In order to control the repair operation of the redundancy circuit to be enabled, if the fuse FUSE1 is shorted and the fuse FUSE2 is connected, the node N1 is set to logic "low" and the node N2 is set to logic "high". Then the signal storage portion 30 receives the logic "low" voltage across the node N1 and the logic "high" voltage across the node N2 and stores the input address signal Ai of logic "low", thereby generating the output signal OS of logic "high".
That is, the PMOS transistor PM1 and the NMOS transistor NM3 of the signal storage portion 30 receive the logic "low" voltage across the node N1 through the respective gate electrodes, and are turned on and turned off, respectively. The PMOS transistor PM2 and the NMOS transistor NM4 receive the address signal Ai of logic "low" through the respective gate electrodes, and are turned on and turned off, respectively. The NMOS transistor NM2 and the PMOS transistor PM4 receive the inverted address signal /Ai of logic "high" through the respective gate electrodes, and are turned on and turned off, respectively. The PMOS transistor PM3 and the NMOS transistor NM5 receive the logic "high" voltage across the node N2 through the respective gate electrodes, and are turned off and on, respectively. Therefore, the signal storage portion 30 generates the output signal OS of logic "high". The redundancy circuit is enabled by the output signal OS of logic "high" and carries out the data repair operation.
In order to control the repair operation of the redundancy circuit to be enabled, if the fuse FUSE1 is in the connected state and the fuse FUSE2 is in the shorted state, the node N1 is set to logic "high" and the node N2 is set to logic "low". Then the signal storage portion 30 receiving the logic "high" voltage across the node N1 and the logic "low" voltage across the node N2 stores the address signal Ai of logic "high" and generates the output signal OS of logic "high".
In more detail, the PMOS transistor PM1 and the NMOS transistor NM3 receiving the logic "high" voltage across the node N1 through the respective gate electrodes are turned off and turned on, respectively. The PMOS transistor PM2 and the NMOS transistor NM4 receiving the address signal Ai of logic "high" through the respective gate electrodes are turned off and turned on, respectively. The NMOS transistor NM2 and the PMOS transistor PM4 receiving the inverted address signal/Ai of logic "low" through the respective gate electrodes are turned off and turned on, respectively. The PMOS transistor PM3 and the NMOS transistor NM5 receiving the logic "low" voltage across the node N2 through the respective gate electrodes are turned on and turned off, respectively. Therefore, the output signal OS of logic "high" is generated.
As a result, in order to enable the data repair operation of the redundancy circuit, if the fuse FUSE1 is in the shorted state and the fuse FUSE2 is in the connected state, the address signal Ai of logic "low" is stored. If the fuse FUSE1 is in the connected state and the fuse FUSE2 is in the shorted state, the address signal Ai of logic "high" is stored.
However, since the prior art address storage circuit of the data repair controller should store the address signal of the prescribed level in order to control the data repair operation to be disabled, as shown in FIG. 1, the current is dissipated by such operation and the power consumption increases. Further, as shown in FIG. 2, since the address signal is stored using two fuses, the area occupied by the address storage circuit increases. If both fusses are shorted, since the logic "low" level across the shorted nodes is not stabilized, the address storage circuit operates unstably and another level stabilizer is needed.

Address signal storage circuit of data repair controller