One or more first sensors may be configured to sense seismic signals and one or more second sensors may be configured to sense electromagnetic crosstalk signals. The second sensors are not responsive to the seismic signals. The data from the first and second sensors may be recorded as first data and second data, respectively. The first data may be modified based on the second data to remove the electromagnetic crosstalk noise form the seismic data.

Geophysical surveys are used to investigate geological features under the surface of the Earth. For example, seismic surveys can be conducted acoustically, using one or more acoustic sources to transmit acoustic energy into the earth. The acoustic energy is reflected from boundaries of geological features in the Earth that have different acoustic impedances. Sensors can be used to detect the reflected acoustic energy, and a recording system coupled to the sensors can record data representing the detected acoustic energy. The data can be processed to identify potential subsurface structures. For example, the identified structures can aid in the location of hydrocarbons. Electromagnetic surveying can also be used in geophysical surveys. Electromagnetic surveys include imparting electromagnetic energy from an electromagnetic source and detecting the reflected electromagnetic energy with electromagnetic sensors.
Geophysical surveys include land-based surveys and marine surveys. The land-based surveys may include one or more explosive charges or vibrating devices as acoustic sources, or one or more electromagnetic sources, and various sensors located at known distances from the source(s). Marine surveys typically include an acoustic source such as air cannons or marine vibrators towed by a vessel, and/or an electromagnetic source towed by a vessel. The sensors can be towed by the vessel as well, for example in one or more towed streamers. Alternatively, or additionally, the sensors can be included in one or more cables or nodes that are anchored to the sea bottom or seabed.
The seismic sensors typically convert detected acoustic energy to electrical signals, and are subject to electromagnetic crosstalk noise. The noise is captured in the data from the sensors, and pollutes the signals indicating the detected acoustic energy. For example, switching equipment on and off during the survey can create noise on the power lines that supply the sensors and/or related electronics. In a marine environment, the intrusion of water into the enclosure that houses the electronics can create noise on the power lines, for example by creating intermittent low resistivity paths between the power lines. If both seismic surveying and electromagnetic surveying are performed at the same time, the electromagnetic source may impart electromagnetic noise in the seismic data as well. Traditionally, when crosstalk noise is detected during a geophysical survey, the survey is stopped until the problem can be corrected and the survey is restarted. Stopping and restarting the survey increases the expense of conducting the survey.
While embodiments described in this disclosure may be susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the embodiments to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the appended claims. The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description. As used throughout this application, the word "may" is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words "include", "including", and "includes" mean "including, but not limited to." As used herein, the terms "first," "second," etc. are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless specifically stated.
Within this disclosure, different entities (which may variously be referred to as "units," "circuits," other components, etc.) may be described or claimed as "configured" to perform one or more tasks or operations. This formulation—[entity] configured to [perform one or more tasks]—is used herein to refer to structure (i.e., something physical, such as an electronic circuit, a mechanical device, etc.). More specifically, this formulation is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure can be said to be "configured to" perform some task even if the structure is not currently being operated. A "clock circuit configured to generate an output clock signal" is intended to cover, for example, a circuit that performs this function during operation, even if the circuit in question is not currently being used (e.g., power is not connected to it). Thus, an entity described or recited as "configured to" perform some task refers to something physical, such as a device, circuit, memory storing program instructions executable to implement the task, etc. This phrase is not used herein to refer to something intangible. Similarly, various units/circuits/components may be described as performing a task or tasks, for convenience in the description. Such descriptions should be interpreted as including the phrase "configured to."
The term "configured to" is not intended to mean "configurable to." An unprogrammed FPGA, for example, would not be considered to be "configured to" perform some specific function, although it may be "configurable to" perform that function. After appropriate programming, the FPGA may then be said to be "configured" to perform that function.
As used herein, the term "based on" or "dependent on" is used to describe one or more factors that affect a determination. This term does not foreclose the possibility that additional factors may affect the determination. That is, a determination may be solely based on specified factors or based on the specified factors as well as other, unspecified factors. Consider the phrase "determine A based on B." This phrase specifies that B is a factor used to determine A or that affects the determination of A. This phrase does not foreclose that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover an embodiment in which A is determined based solely on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."
This specification includes references to various embodiments, to indicate that the present disclosure is not intended to refer to one particular implementation, but rather a range of embodiments that fall within the spirit of the present disclosure, including the appended claims. Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.
This specification may use the words "a" or "an" to refer to an element, or "the" to refer to the element. These words are not intended to mean that there is only one instance of the element. There may be more than one in various embodiments. Thus, "a", "an", and "the" should be interpreted to mean "one or more" unless expressly described as only one.

Removing electromagnetic crosstalk noise from seismic data


For maximizing creative play, a hand puppet kit includes a sock-like body member formed of a flexible material to have a hand receiving opening at one end thereof. The kit also includes a separate sheet of flexible material together with at least one pattern for creating a piece in a predetermined shape from the separate sheet of flexible material. With these features, the hand puppet kit further includes at least one portion of a hook and loop fastener to be secured to the piece.

Hand puppets are well known for encouraging creativity, for instance, by allowing children and adults to engage in roll playing and the like. Unfortunately, many prior art puppets, dolls, and stuffed toys often comprise a fixed character which fails to allow for any change in the various visual, physical and operational characteristics of the puppet. In this connection, these limitations are known to apply to all types of puppets, dolls and stuffed toys including hand puppets.
More recently, there have been suggested various puppets and dolls which allow the user to implement reconfigurations through changes of clothing or the addition of accessories. In fact, it has even been known to permit a change in facial features, but it seems that no hand puppet kit has ever been proposed which truly maximizes creative play opportunities.
Still additionally, hand puppets have conventionally been of limited use as children's toys apart from offering great amusement when animated on the hand. However, they otherwise are of little or no use, for instance, as a decorative item. More specifically, a hand puppet is generally considered as an open, empty and limp structure that is disappointing for other uses such as display or the like.
In view of the foregoing, it has remained to provide a hand puppet kit that truly maximizes creative play. It has also remained to provide such a kit which allows user interaction in the creation of ornamentation to change the character, appearance and/or shape of the puppet at will. Still additionally, it has remained to provide a hand puppet which is also capable of suitable self-supporting display.
The present invention is directed to overcoming one or more of the foregoing problems and achieving one or more of the resulting objects.

Ozite Company; Div. of Plastic Specialties & Tech. Inc.


A switching power supply unit includes an overcurrent protection circuit section and a latch-stop release signal output circuit section. The overcurrent protection circuit section performs an overcurrent protection operation for latching and stopping the switching operation of a main switch during an overcurrent state. The latch-stop release signal output circuit section outputs a signal, only in a predetermined latch-stop release period, for releasing the latch stop after a certain waiting time has elapsed from the time of the latch stop. This arrangement can virtually perform a hiccup-mode overcurrent protection operation at the time of overcurrent, and expands the scope of application of a switching power supply unit. Switching power supply circuits are interconnected by simultaneous starting connections. Switching controllers for the main switches are connected to match hiccup mode restart timings.

1. Field of the Invention
The present invention relates to a switching power supply unit having a function of protecting against output overcurrent.
2. Description of the Related Art
Typically, switching power supply units include a circuit having an overcurrent protection function for preventing load circuit components from being broken, emitting smoke, or being ignited due to output overcurrent during short-circuiting of a load. The switching power supply circuits for performing overcurrent protection are provided with a device for detecting overcurrent. Various circuit systems are known for detecting overcurrent. Examples include a system in which a current detection element, such as a current transformer or resistor, is inserted in an output current path to directly detect the output current. For an insulated switching power supply circuit having a transformer, there is a system in which a current detection element, such as a current transformer or resistor, is inserted into a primary switching current loop and the peak value of AC current thereof is observed to indirectly detect the output current. For a switching power supply having a large output impedance, there is a simple system in which the overcurrent state is determined when the output voltage drops even though the output voltage is stabilized by the duty ratio control of a switching element.
Various systems are known for providing a protection operation upon detection of output overcurrent. Examples include a system in which an output voltage is caused to drop by reducing the duty ratio of a switching element (an output voltage drop mode), a system in which output overcurrent is detected to latch and stop the switching operation at a certain time after the overcurrent detection (a latch-stop mode), and a system in which the operation and the stopping of the switching operation is repeated cyclically upon detection of output overcurrent (a hiccup or intermittent mode). Also available is a system in which the output voltage drop mode and the latch-stop mode or the hiccup mode are combined. In this case, when overcurrent is detected, the output voltage is instantaneously caused to drop, and in this state, when the overcurrent continues for a certain period of time or more, an overcurrent protection operation is performed in the latch-stop mode or the hiccup mode.
In addition, for an insulated switching power supply circuit using a synchronous rectifier for rectifying the output current, there is a problem in that, when overcurrent protection is performed in an output voltage drop mode during load short-circuiting, the power supply for driving the synchronous rectifier cannot be secured, thereby heating the synchronous rectifier Thus, an overcurrent protection operation may he performed by combining an output voltage drop mode with another synchronous rectifier protection mode.
An appropriate system is selected from among the various overcurrent protection systems described above and adopted depending on, for example, the application of a switching power supply unit. For example, in an application in which it is preferred that the switching power supply continues to stop in the period of time from the detection of the output overcurrent to the reset of a switching power supply circuit, the overcurrent protection may be performed by combining the output voltage drop mode and the latch-stop mode. In an application in which it is desired that the output voltage automatically recover when a load short-circuit state is eliminated, the overcurrent protection is performed by combining the output voltage drop mode and the hiccup mode.
A known approach for increasing the output power applied to a load is a parallel operation in which the input/output terminals of a plurality of switching power supply circuits are connected in parallel. Due to load short circuiting the switching power supply circuits, which are operated in parallel, also require protection against output overcurrent. In this case, it is preferable that the overcurrent protection operation be performed in a hiccup mode in the application described above, in which it is desired that the output voltage recover when a load short-circuit state is eliminated.
FIG. 5 shows exemplary waveforms of output currents and output voltages of two switching power supply circuits, α and β, from when a load short-circuiting occurs to when the load short-circuiting is eliminated and the switching power supply circuits return to a normal condition. The switching power supply circuits α and β are operated in parallel and perform hiccup-mode overcurrent protection. In FIG. 5, waveform a is the total output current of the two switching power supply circuit α and β, waveform b is the output current of the switching power supply circuit α, waveform c is the output current of the switching power supply circuit β, and waveform d is the total output voltage of both switching power supply circuits α and β.
In hiccup mode, typically, the time (waiting time) from the stopping of the switching operation after the flow of overcurrent until the restarting of the switching operation is set by a time-constant circuit. The capacitance, C, and resistance, R, of the time-constant circuit may vary due to variations in the components constituting the time-constant circuit. Consequently, the waiting time from the stopping of the circuit operation due to overcurrent to the restarting thereof can vary for each switching power supply circuit.
Suppose, as shown in FIG. 5, load short-circuiting occurs at time A due to the variations in the waiting time, and this results in an overcurrent state. In this case, two switching power circuits α and β, stop at substantially the same time, t1. Even though the switching power supply circuits are operated in parallel, one switching power supply circuit, α, may restart earlier than the other switching circuit, β, at time t2. After restarting, the switching power supply circuit, α, detecting the continuation of the overcurrent sate, stops again at time t3. Subsequently, the other switching power supply circuit, β, restarts at time t4, and similarly, upon detecting the continuation of the overcurrent state, stops again at time t5.
Suppose the load short-circuiting is eliminated at time B. In the same manner as described above, when one switching power supply circuit α restarts earlier than the other switching power supply circuit β at time t6, due to the variations of the waiting time, the switching power supply circuit α outputs a current corresponding to the current output by the two switching power supply circuits α and β which are operated in parallel. As a result, the switching power supply circuit α incorrectly determines that the output overcurrent state is still occurring, and stops again at time t7. Thereafter, the other switching power supply circuit β which has started, for example, at time t8 stops again for the same reason at time t9. Such a phenomenon continues until the restart timings of the two switching power supply circuits α and β, which are operated in parallel, happen to come closer and they restart at substantially the same time (timing C in FIG. 5).
In this manner, the deviation of the restart timings due to the difference between waiting times of the switching power supply circuits α and β, which are operated in parallel, causes a problem in that the switching power supply circuits α and β cannot return to a normal operation immediately even after load short-circuiting is eliminated.
In addition, when the output voltage returns at timing C but the restart timings of the switching power supply circuits α and β, which are operated in parallel, are somewhat deviated, for example, only the switching power supply circuit β that has restarted earlier starts in an overcurrent drop state. As a result, when the switching power supply circuits α and β return to a normal state, the waveform of the total output voltage thereof becomes a step-up and step-down form (refer to waveform d in FIG. 5). This causes a problem in that any electronic device that is connected as the load may malfunction.
Additionally, an appropriate operation mode for overcurrent protection varies depending on the application, as described above. For example, a latch-stop mode is suitable for an application in which it is preferred that a switching power supply circuit continue to stop in the period from the detection of an output overcurrent to the reset of the switching power supply circuit. A hiccup mode is suitable for an application in which it is desired that the output voltage automatically recover when a load short-circuit state is eliminated. Consequently, there is a problem in that switching power supply circuits designed for a latch-stop mode cannot be used in an application in which a hiccup mode is desired, i.e., in an application in which it is desired that the output voltage automatically recover when a load short-circuit state is eliminated.


An improved process for melt spinning a pigmented hexamethylene adipamide fiber from a melt blend of a polymer and a colored pigment wherein the polymer is a random interpolyamide or a block polymer having two different difunctional recurring amide-forming moieties other than those which form hexamethylene adipamide is disclosed along with pigmented hexamethylene adipamide polymer fibers having tenacities greater than 7.5 or even 8 grams per denier.

Nylon can be dyed with acid or cationic dyes to give colored yarns which may be used in fabrics or carpets. Recently, yarn producers have begun incorporating colored pigments into nylon yarns to improve their resistance to degrading and fading in ultraviolet light, to give improved resistance to chemicals and noxious fumes and to give permanent coloration which is not removed by washing. While some pigments can be mixed easily into the nylon without adversely affecting the filament spinning operation, most pigments--and particularly organics--cause some difficulties while being mixed into the nylon or in subsequent melt-spinning and drawing operations. In general, organic pigments tend to cross-link nylon, change its viscosity, form spherulites which weaken the fibers, and cause increased draw tension and filament breaks.
Ultraviolet light degrades nylon, and the degradation can be accelerated by the presence of some pigments. To avoid this, copper in various forms is often added to the polymer. The amount of copper which is effective in preventing degradation of the polymer by ultraviolet light also causes poor spinning performance. The combination of pigment and copper is still worse.
European Patent Publication No. 0373655 ("Anton et al."), published Jun. 20, 1990, and incorporated herein by reference, discloses processes for making stain-resistant, pigment-colored fibers with acceptable levels of spinning performance. Those processes involve forming a random nylon copolymer made with up to 4.0 weight percent of a cationic dye additive such as 5-sulfoisophthalic acid or its salts, adding up to 4.5 weight percent of a pigment concentrate to the copolymer, and melt-spinning the pigment/polymer blend. Certain pigments, however, remain very difficult to spin even using the copolymers disclosed therein.
While Anton et al. is directed primarily at pigment-colored fibers useful in carpet applications, there is also a demand for pigmented fibers suitable for use in certain industrial applications such as for parachute fabrics, life-jackets, and industrial sewing thread where high tenacity is required. Here too, however, the presence of pigment has made it difficult to draw the fibers, and consequently insufficient orientation is obtained to achieve tenacity levels greater than 7.5 grams per denier, which is a level that can be attained for non-pigmented nylon yarns.
Ways of reducing the impact of such pigments on nylon spinning and drawing performance would permit the use of a wider selection of colored pigments, both organic and inorganic, would enable fiber producers to offer a complete range of styling colors while reducing product deficiencies and operating difficulties, and would allow for the production of high tenacity pigmented nylon fibers.

Processing of pigmented nylon fibers using modified polymers


A liquid crystal display device includes a pixel having a first to nth (n is a natural number of 2 or more) subpixels and a circuit. To the circuit, N (N is a natural number of 2 or more) wirings for supplying a digital signal with N bits and first to nth wiring groups having M (M is a natural number of 2 or more) wirings for supplying M different voltages are electrically connected. The liquid crystal display device has a function of converting the digital signal into n analog signals by using the M voltages supplied to the first to nth wiring groups and inputting the n analog signals to first to nth subpixels. The first to nth subpixels each include an electrode for driving a liquid crystal element.

1. Field of the Invention
One embodiment of this invention relates to a display device or a driving method of the display device. In specific, one embodiment of this invention relates to a liquid crystal display device in which a pixel is divided into a plurality of subpixels and a driving method of the liquid crystal display device. Further, one embodiment of this invention relates to a liquid crystal display device or an electronic device including the liquid crystal display device in a display portion.
2. Description of the Related Art
Liquid crystal display devices are used for a variety of electronic products such as cell phones and television receiver and many research is conducted for further improvement in the quality.
While advantages of a liquid crystal display device are small size, light weight, and low power consumption compared to a CRT (cathode-ray tube) and, a problem of the liquid crystal display device is the narrow viewing angle. In recent years, many research about a multi domain method, that is, an alignment division method are made for improving viewing angle characteristics. For example, an MVA (multi-domain vertical alignment) mode which is a combination of a VA (vertical alignment) mode and a multi-domain mode, a PVA (patterned vertical alignment) mode, and the like can be given.
In addition, researches are made in which one pixel is divided into a plurality of subpixels and the alignment state of liquid crystals in each subpixel is made different so as to improve the viewing angle. However, since the pixel is divided into the plurality of subpixels, a plurality of signals needs to be input to one pixel. Therefore, the number of signals needed for driving a display device is increased. In view of this, research on conversion of a signal for one pixel into signals for respective subpixels is conducted (see Reference 1).    Reference 1: Japanese Published Patent Application No. 2007-226196

Display device, liquid crystal display device and electronic device including the same

SEMICONDUCTOR ENERGY LABORATORY CO., LTD.


In a package for mounting a semiconductor device and a bump, an interposer substrate has a first surface for mounting the semiconductor device. A wiring layer capable of being connected to the semiconductor device, a terminal connected to the wiring layer for mounting the bump, and a plating layer are formed on a second surface of the interposer substrate. The plating layer is connected to one of the terminal and the wiring layer. The plating layer is terminated within the interposer substrate.

1. Field of the Invention
The present invention relates to a package for mounting a semiconductor device (chip) and a solder bump, and its manufacturing method.
2. Description of the Related Art
Generally, when a semiconductor chip and solder bumps are mounted on terminals of a package by soldering or the like, it is impossible to mount the semiconductor chip and the solder bumps directly on the terminals, because the terminals are not made of rust proof material. Therefore, it is essential to electroplate Au or Ni/Au on the terminals before the semiconductor chip and the solder bumps are mounted.
In a prior art method for manufacturing a package for mounting a semiconductor device and a bump, an interposer substrate having a first surface for mounting the semiconductor device is prepared. Then, a conductive layer is formed on a second surface of the interposer substrate, and the conductive layer is patterned to form a wiring layer capable of being connected to the semiconductor device, a terminal connected to the wiring layer, and a plating layer connected to the terminal and terminated at an end of the package. Then, a mask layer having an opening exposing the terminal is coated, and the terminal is electroplated by supplying a current from the plating layer to the terminal (see: JP-A-5-95025 and JP-A-8-288422). This will be explained later in detail.
In the above-described prior art method, however, the plating layer is finally left. Therefore, when the operation frequency of this semiconductor chip is higher, the amount of signals reflected by the plating layer is increased. Also, the parasitic capacitance of the plating layer adversely affects signals from the semiconductor chip to the solder bump and vice versa.
It is an object of the present invention to provide a package and its manufacturing method capable of decreasing the amount of reflected signals and reducing the parasitic capacitance by plating layers.
According to the present invention, in a package for mounting a semiconductor device and a bump, an interposer substrate has a first surface for mounting the semiconductor device. A wiring layer capable of being connected to the semiconductor device, a terminal connected to the wiring layer for mounting the bump, and a plating layer are formed on a second surface of the interposer substrate. The plating layer is connected to one of the terminal and the wiring layer. The plating layer is terminated within the interposer substrate.
Also, in a method for manufacturing a package for mounting a semiconductor device and a bump, an interposer substrate having a first surface for mounting the semiconductor device is prepared. Then, a conductive layer is formed on a second surface of the interposer substrate, and the conductive layer is patterned to form a wiring layer capable of being connected to the semiconductor device, a terminal connected to the wiring layer, and a plating layer connected to the terminal or the wiring layer and terminated at an end of the package. Then, a mask layer having an opening exposing the terminal is coated, and the terminal is electroplated by supplying a current from the plating layer to the terminal. Finally, the plating layer is terminated within the package.

Package having terminated plating layer and its manufacturing method


An integrated semiconductor circuit includes a transistor and a strip conductor (11). The transistor includes a first (1) and a second source/drain region (2) and a gate electrode. The strip conductor (11) is electrically insulated from a semiconductor body at least by a gate dielectric and forms the gate electrode in the area of the transistor. The strip conductor (11) extends along a first direction (x) in the area of the transistor. The second source/drain region (2) is arranged offset with respect to the first source/drain region (1) in the first direction (x). The transistor thus formed has an inversion channel (K1) that only extends between two corner areas (1a, 2a) facing one another of the first and of the second source/drain region, i.e. is much narrower than in the case of a conventional transistor.

Semiconductor circuits are implemented, for example, as CMOS (complementary metal oxide semiconductor) circuits and have transistors produced in MOS technology that form inversion channels of electrons or holes underneath a strip conductor. In this arrangement, two source/drain regions are formed opposite one another on both sides of a strip conductor as implantation areas in a semiconductor substrate. The strip conductor is used as gate electrode in the area of the transistor and controls the formation or prevention of an inversion channel by means of its electrical potential. The inversion channel extends closely underneath the semiconductor surface in the semiconductor substrate, to be precise underneath a gate oxide layer between the facing sides of the two source/drain regions of the transistor. The width of the channel in this case extends over the width of both source/drain areas along the direction of the extent of the strip conductor. Usually, both the length of the channel and the width of the channel in each case correspond to the optical limit of resolution F which can be achieved with the lithographic exposure device used in each case.
The transistor described above can be used, in particular, as storage transistor in nonvolatile semiconductor memories. In this case, it has between the strip conductor and the semiconductor substrate a charge-storing layer which spatially binds electrical charges that are scattered into this layer during the formation of an inversion channel and, as a result, can store digital information. In such storage circuits, there is a requirement for techniques that reduce the storage density, i.e. the number of storable information items per unit of substrate area. The object of miniaturizing electrical circuits also presents itself in the case of logic circuits.

Integrated semiconductor circuit comprising a transistor and a strip conductor


A lamp adapter for receiving a lamp having a conductive threaded portion and an extension with a conductive contact electrically insulated from the conductive threaded portion. The lamp adapter has a body with a top portion and a bottom portion. The top portion has a socket with a threaded sleeve adapted to receive the threaded portion of the lamp, a first lead electrically connected to the threaded sleeve, a cavity located with respect to the threaded sleeve so as to receive the extension of the lamp when the lamp is threaded into the threaded sleeve, a metal contact arm located within the cavity so as to make electrical contact with the conductive contact of the lamp when the lamp is threaded into the threaded sleeve, and a second lead electrically connected to the metal contact arm. The bottom portion has a threaded portion suitable for threading into a mating lamp socket, the threaded portion being electrically insulated from the top portion. The lamp adapter includes a recess located within the cavity and a coil spring disposed with a lower portion within the recess and an upper portion above the recess and within the cavity, wherein the metal contact arm is located in cooperation with the coil spring so as to be biased thereon and make contact with the conductive contact of the lamp when the lamp is threaded into the threaded sleeve. The metal contact arm is located with the cavity so as not to make contact with a conductive electrical contact on a lamp not having an extension.

1. Field of the Invention
The present invention pertains generally to adapters for mogul base open fixture lamps.
2. Description of the Related Art
Metal halide lamps include a relatively centrally located arc tube situated within the confines of an outer glass bulb. These arc tubes are conventionally made of quartz and operate at extremely high temperatures and relatively high pressures. Under certain undesirable conditions, a system failure or internal factors will result in a safety hazard being created, whereby a violent shattering of the arc tube will send hot glass and lamp parts into contact with the bulb glass which, in turn, will break, releasing the hot glass and lamp parts into the surrounding environment. Under such conditions, there is an obvious risk of severe personal injury, fire and/or property damage.
For this reason, normally such conventional metal halide unshrouded lamps are supported within what are referred to as "enclosed" fixtures whose structure is designed to contain violently released hot glass and lamps parts. A cover lens is used in such fixtures. In addition, significant reductions in such potential violent failures can be achieved by replacing the lamp before the rated end of the life of the lamp. Another conventional manner in which such potential violent failures are reduced includes the user's periodically turning off the lamp to permit its cooling, so that upon relighting, a non-violent or less violent lamp failure is facilitated.
Recent developments in the field of low wattage metal halide lamp technology affects both lamps and lampholders. Manufacturers of metal halide lamps are selling lamps for use in what are referred to as "open" fixture, in which the lamp is mounted such that it is exposed during its use. In order to reduce or eliminate the risks associated with violent lamp failures in non-enclosed environments, a newer metal halide shrouded lamp has been developed in which a relatively thick shroud of quartz is situated intermediate the arc tube and the outer bulb glass such that, it the event of a violent lamp failure of the type described above, the shroud is intended to intercept and contain the hot glass and lamp parts which would otherwise impact and possibly break the bulb glass. The intended result is a less expensive and equally safe lamp and fixture combination suitable for indoor commercial lighting applications such as offices and retail spaces, as well as other environments.
To prevent the use of conventional unshrouded lamps intended to be used in an "enclosed" fixture in an "open" fixture, the newer shrouded lamp is provided with a different type of base so that the shrouded lamps intended for an open" fixture can be rapidly identified and separated from unshrouded lamps that must be used in an "enclosed" fixture.
There is a need for a device that allows the use of new shrouded lamps with existing "enclosed" fixtures.

Adapter for mogul base open fixture lamps


A gas separation module includes at least one inlet port, a plurality of outlet ports, and a plurality of hollow fiber membranes. Individual fibers have a feed end and a product end with a retentate interior side and a permeate exterior side. The module includes a feed tubesheet within the shell segregating the at least one inlet port and the permeate side of the fibers. The feed tubesheet includes a matrix and at least one segment joint. The segment joint separates segments of the feed tubesheet from one another. A formation method includes positioning a hollow fiber membrane material in association with at least one tubesheet segment joint and applying a matrix. The method includes forming a feed tubesheet from cured matrix and the segment joint and forming a plurality of hollow fiber membranes from the fiber material. The segment joint separates segments of the feed tubesheet from one another.

Known air separation modules (ASMs) are found in aircraft fuel tank flammability reduction systems. The ASM removes some oxygen from air to generate nitrogen-enriched air (NEA), which then flows into fuel tank ullage, a region in the tank that often contains evaporated fuel (i.e., fuel vapor). The NEA may reduce flammability of the fuel tank ullage. Federal Aviation Administration (FAA) regulations require that new and in-service transport aircraft include systems for enhancing the safety of aircraft fuel tanks. Unfortunately, ASMs have a service life that may be limited by reduced separation efficiency or failure of components in the ASM, requiring repair or replacement and causing corresponding aircraft downtime. Accordingly, increased reliability of air separation modules is desirable.

Gas separation modules and methods for forming


The invention relates to a perfected retractable needle safety syringe comprising a hollow cylinder, a needle holder, a needle and a piston with an operating stem, said stem exhibiting an axial hole wherein there are seated a retraction pre-loaded spring and an extractor element. The extractor element exhibits a recess or seat intended for interacting with the needle holder, and at the side opposite the needle holder, a projection or annular rib.

Retractable needle syringes are already known from former patents by the owner of the present application.
One of them is disclosed in Italian patent no. 1,248,456 and another one in Italian patent no. 1,288,237.
The solutions described in these patents, however, have construction and structural problems that make their construction particularly complex and expensive and, above all, do not always ensure a safe and regular operation due to such complexity.


A defect inspection apparatus which includes a pattern image obtaining unit obtaining a pattern image of a predetermined part by causing focusing control to be performed in order to achieve focus on the predetermined part within an observation object according to set focusing control parameters, a pattern image storing unit storing the pattern image, and a detecting unit detecting the presence/absence of an abnormal condition of a part to be inspected by making a comparison between the pattern image of a reference part within the observation object, and the pattern image of the part to be inspected within the observation object. The focusing control parameters, set when the pattern image of the part to be inspected is obtained, are determined based on sample information obtained when the pattern image of the reference part is obtained.

1. Field of the Invention
The present invention relates to a defect inspection apparatus of a chip comparison inspection method, which automatically detects a defect of a semiconductor wafer, and a defect inspection method.
2. Description of the Related Art
In recent years, wiring rules have been becoming minute with the innovation of semiconductor technology, and the demand for detecting a defective chip with high accuracy at high speed has been growing in a semiconductor wafer inspection apparatus.
Accompanying this, the automation of a semiconductor wafer inspection apparatus using a microscope has been advancing, and an AF (automatic focusing) function for automatically achieving focus on an observation object has become an essential function. The performance of the AF function included in such an apparatus plays a very important role in improvements in, so-called, an inspection throughput (inspection efficiency per unit time).
For example, an semiconductor wafer automatic defect inspection apparatus of a chip comparison inspection method makes a matching (pattern matching) between a pattern of a normal chip verified beforehand and that of a chip to be inspected by taking advantage of the fact that a number of identical pattern chips are aligned and formed on a semiconductor wafer. If the apparatus determines that the patterns mismatch, it judges that an abnormal condition occurs in the chip to be inspected, and analyzes the contents of the abnormal condition.
With this automatic defect inspection apparatus, the AF is executed respectively when the pattern image of the normal chip is recognized, and when the pattern image of the chip to be inspected is captured. Therefore, the apparatus requires an AF operation time by the amount of time of the AF. Additionally, if focusing accuracy is poor, and if the image of the normal chip or the chip to be inspected becomes, so-called, defocused, the apparatus can erroneously judge the normal chip as an abnormal chip when making the pattern matching.
In the meantime, as a technology for improving AF performance such as a focusing speed and focusing accuracy, for example, Japanese Patent Publication No. H06-165019 discloses an automatic focusing apparatus switching a calculation method of a defocusing amount used to determine the focusing of AF control according to the luminance of a sample. Furthermore, Japanese Patent Application Laid-open No. H11-84228 discloses an automatic focus adjustment apparatus switching an algorithm of AF control according to brightness, which is an observation condition.

Defect inspection apparatus and defect inspection method


The present disclosure relates to dispersible pharmaceutical compositions comprising N—((R)-2,3-dihydroxypropoxy)-3,4-difluoro-2-(2-fluoro-4-iodo-phenylamino)-benzamide, and, optionally, a pharmaceutically acceptable carrier.

Neurofibromatosis Type 1 ("NF1") is characterized by diverse, progressive cutaneous, neurological, skeletal and neoplastic manifestations with no standard drug treatment options available. Neurofibromas are benign peripheral nerve sheath tumors comprised of a mixture of Schwann cells, fibroblasts, perineurial cells, and mast cells and occur in 20 to 50% of NF1 patients (Tucker, et al. (2011) J. Histochem. Cytochem. 59(6):584-590). When a neurofibroma extends longitudinally along a nerve and involves multiple fascicles, it is classified as a plexiform neurofibroma (PN). Plexiform neurofibromas rarely regress spontaneously, and in many patients their growth is relentless. Plexiform neurofibromas represent a major cause of morbidity and disfigurement in individuals with NF1, and when symptomatic, are associated with increased mortality (Rasmussen, et al. (2001) Am. J. Hum. Genet. 68(5):1110-1118; Prada, et al. (2012) J. Pediat. 160(3):461-467). As tumor growth progresses, such lesions produce dysfunction, pain, and cosmetic disfigurement and can compress the airway or spinal cord. Furthermore, PNs have the potential to undergo malignant transformation producing malignant peripheral nerve sheath tumors (MPNSTs).
Previous longitudinal retrospective studies have demonstrated age dependent differences in plexiform neurofibromas, with high inverse correlation of PN growth to patient age (Dombi, et al. (2007) Neurology. 68(9):643-647; Nguyen, et al. (2012) Orphanet J. rare Dis. 7(75); Tucker, et al. (2008) Am. J. Med. Genet. 46:81-85). In a retrospective review, Tucker et al. analyzed serial MRIs of 34 patients (median 10 years of age, range 1 to 47 years) with a measurable PN for a median follow-up length of 6 years (range 1 to 15 years). This study observed that the difference between the initial and final two-dimensional estimated tumor size was significantly greater in younger individuals compared to older individuals; 3.2 cm2 vs 0.2 cm2, respectively (p=0.031). In addition, the growth rate of tumors in patients <10 years of age (0.7 cm2/year) was significantly greater than that of tumors in patients >10 years of age (0.03 cm2/year, p=0.014). Similarly, in an observational study of 49 patients 3 to 25 years of age (median 8.3 years), Dombi et al. observed that PN volume increased more rapidly than body weight over time (p=0.026). Furthermore, there was a tendency for patients younger than the median age of 8.3 years to have a greater increase in PN volume per year vs older children; 21.1% vs 8.4% volume change per year, respectively (p=0.001). This trend holds true when PN growth rate is expressed relative to the rate of increase in body size.
Based on the findings of Tucker and Dombi, Nguyen et al. conducted a retrospective study of 71 patients with an evaluable PN for a median follow-up of 2.2 years (range 1.1 to 4.9 years). The rate of growth of the individual tumors was inversely correlated with age at initial examination (Spearman's rho=−0.33, p<0.001), but not with the tumor volume on initial MRI examination. Also, tumors that grew more than 20% per year were significantly more frequent among children than among adults (p<0.001). In summation, findings from three independent retrospective reviews of PN volume clearly show that the growth rate of PNs in NF1 patients is inversely correlated with age, indicating discrete age dependent tumor differences and an unmet need in the pediatric population.
These observations suggest that the youngest patients could receive the greatest clinical benefit from therapy. However, the youngest potential patients with an urgent medical need for treatment may struggle to receive treatment due to the inability to swallow a whole capsule or tablet. Therefore, there is a need for an age-appropriate pediatric formulation that permits accurate dosing and enhanced adherence to optimize efficacy and safety in this population.
Moreover, any patient in need of treatment but who experiences difficulty swallowing ("dysphagia") would benefit from a non-capsule or tablet formulation which can be orally administered. Dysphagia can be caused by a variety of circumstances affecting one or more components of the swallowing process. These can include but are not limited to: physical damage to the tongue, pharynx, larynx, esophagus, or trachea caused by trauma, infection, proliferative disease; treatment for a such a condition; congenital anatomical defects such as cleft palate; underdevelopment at young age; weakening at old age; dementia, memory loss, or cognitive decline; or any condition which otherwise weakens or damages the muscles or nerves used in the swallowing process, such as Parkinson's disease, stroke, or nervous system disease.
N—((R)-2,3-dihydroxypropoxy)-3,4-difluoro-2-(2-fluoro-4-iodo-phenylamino)-benzamide ("mirdametinib", or "PD-0325901") is a small molecule drug which has been designed to inhibit mitogen-activated protein kinase kinase 1 ("MEK1") and mitogen-activated protein kinase kinase 2 ("MEK2"). MEK1 and MEK2 are proteins that play key roles in the mitogen-activated protein kinase ("MAPK") signaling pathway. The MAPK pathway is critical for cell survival and proliferation, and overactivation of this pathway has been shown to lead to tumor development and growth. Mirdametinib is a highly potent and specific allosteric non-ATP-competitive inhibitor of MEK1 and MEK2. By virtue of its mechanism of action, mirdametinib leads to significantly inhibited phosphorylation of the extracellular regulated MAP kinases ERK1 and ERK2, thereby leading to impaired growth of tumor cells both in vitro and in vivo. In addition, evidence indicates that inflammatory cytokine-induced increases in MEK/ERK activity contribute to the inflammation, pain, and tissue destruction associated with rheumatoid arthritis and other inflammatory diseases.
Crystal forms of N—((R)-2,3-dihydroxypropoxy)-3,4-difluoro-2-(2-fluoro-4-iodo-phenylamino)-benzamide have been described previously. WO2002/006213 describes crystalline Forms I and II, and is incorporated by reference. Form I is characterized by an XRPD containing peaks at one or more of 10.6, 13.7, 19.0, and 23.7 degrees 2θ; Form II is characterized by an XRPD containing peaks at 5.5 and/or 19.6 degrees 2θ. Form I is characterized by a melting point at about 117° C.-118° C., and Form II is characterized as melting at 89° C.-90° C., as determined by DSC.
U.S. Pat. No. 7,060,856 ("the '856 patent") describes a method of producing Form IV, and is incorporated by reference. The '856 patent indicates that the material produced by this method was greater than 90% Form IV (The '856 patent, Example 1). The '856 patent also states that the differential scanning calorimetry ("DSC") of the material produced shows an onset of melting at 110° C., as well as a small peak with an onset at 117° C., consistent with the material being a mixture of two forms. Compositions containing more than one polymorphic form are generally undesirable because of the potential of interconversion of one polymorphic form to another. Polymorphic interconversion can lead to differences in the effective dose or physical properties affecting processability of a drug, caused by differences in solubility or bioavailability.
There is a need for a dispersible formulation of N—((R)-2,3-dihydroxypropoxy)-3,4-difluoro-2-(2-fluoro-4-iodo-phenylamino)-benzamide which is safely administrable to patients who have difficulty swallowing full capsules or tablets (e.g., pediatric patients or patients suffering from dysphagia), for use in treatment of a tumor, a cancer, or a Rasopathy disorder. Given the apparent mixture of forms in previously disclosed Form IV, there is a need for dispersible formulations containing essentially pure Form IV of N—((R)-2,3-dihydroxypropoxy)-3,4-difluoro-2-(2-fluoro-4-iodo-phenylamino)-benzamide to limit polymorphic interconversion between forms which may affect solubility and bioavailability.

This patent is subject to a terminal disclaimer.

Dispersible formulations of N-((R)-2,3-dihydroxypropoly)-3,4-difluoro-2-(2-fluoro-4-iodo-phenylamino)-benzamide and uses thereof


A circuit of non-volatile memory which includes a plurality of memory units is disclosed. The memory unit comprises a first switch, a second switch, a data line, a voltage storage component, and a plurality of memory components connected in series. The first terminal of the first switch is coupled to the first voltage. The data line is coupled to the second terminal of the first switch. The first terminal of the voltage storage component is coupled to the data line, and the second terminal of the voltage storage component is coupled to the ground. The first terminal of the second switch is coupled the data line. In addition, the third terminal of each memory component is coupled to the first terminal of the next memory component, and the second terminal of the each memory component is coupled to second voltage.

1. Field of the Invention
This invention generally relates to a non-volatile memory, and especially to a program method and circuit of non-volatile memory, which utilizes a constant charge type for programming storage state.
2. Description of Related Art
FIG. 1 is a drawing, schematically showing a view of a conventional AG-AND type memory. As shown in FIG. 1, when a current Id flows from a terminal Vd to a terminal Vs, an AG-AND memory 100 can conveniently injects and stores electrons into a floating gate (FG) of the memory 100 to accomplish the programming storage action of the memory. The most difference between the AG-AND memory 100 and a common transistor is that the gate electrode terminal comprises two control terminals which are the terminal WL and the terminal AG, so that when the current Id from the terminal Vd to the terminal Vs will be conducted by the AG-AND memory 100, the voltages of two terminals WL and AG must be controlled at same time in order to perform the programming action at this time.
In a common manufacture process of the AG-AND memory 100, the current channel in the each AG-AND memory is different which is caused by manufacturing process, it means that the length and the width of the current channel in each of the AG-AND memory 100 is different when accomplishing the manufacture, so that the stored electric charge amount is also different when the electrons are injected into the terminal FG through the current Id. For example, when the channel length of the AG-AND memory 100 is longer, the necessary time of injection must be longer, whereas, when the channel length of the AG-AND memory 100 is shorter, the necessary time of injection is relatively shorter. But, when the time of injecting the current Id is too short, it can be caused that amount of the electrons stored in the terminal FG is not enough, therefore the correctness of the programming result of the AG-AND memory 100 at this time is affected.
Further, excepting the above mentioned problem, an initial threshold voltage Vt of the each AG-AND memory 100 can also affect the injection time of the current Id. When critical voltage Vt of the each AG-AND memory 100 is higher, the current Id is lower, therefore the amount of the electrons injected into the terminal FG of the AG-AND memory 100 is lower. Whereas, when initial threshold voltage Vt is too low, the amount of the electrons injected into the terminal FG of the AG-AND memory 100 is relatively higher. In order to solve and improve the problem, the only way is to adjust the programming time of the current Id in the each AG-AND memory 100, but the problem solving method is very complex and can not be accomplished easily.
FIG. 2 is a drawing, schematically showing a circuit of a conventional array type AG-AND memory. As shown in FIG.2, the array type AG-AND memory includes four data lines 201 to 207, the each data line includes two set AG-AND memory components 211 and 213. All of the above mentioned data lines are coupled to the same voltage source 220, and by the voltage source 220 the current Id is supplied to each of the data lines 201 to 213. Further, the current amount supplied by the voltage source 220 can be even distributed to each of the data lines.
Supposing that the gross current amount supplied by the conventional voltage source 220 is 1.2 mA, then the maximum current Id supplied to each of the data lines is 0.3 mA, the current Id can perform the storage program of electrons to one set of the AG-AND memory components in each of the data lines thereof. But, when supposing that, owing to a short-cut accident, a set leakage current Ie is generated at the terminals Vd and Vs of the AG-AND memory component 213b in the data line 201, the data line not only must originally supply the current Id for the AG-AND memory component 211a, but also have to supply a additional current for the leakage current Ie, therefore, though originally the current amount 0.3 mA can be even distributed to each of the data lines, because that the leakage current Ie is generated, the current amount, which all of the AG-AND memory components can be obtained, is changed which can cause a mistake to the data storing in the memories in the whole array circuit, of course the serious mistake is not expected by circuit designers.

Program method and circuit of non-volatile memory


A method for operating a sensor array of pixels which each generate a content corresponding to light incident thereon over an exposure period includes the following operations. The pixels are arranged into first and second regions and are reset such that the contents are cleared. The pixels are then exposed to receive light for a first exposure period. The exposure is then interrupted during which the content of each pixel in the first region is read. The pixels are then exposed to receive light for a second exposure period. The exposure is then interrupted during which the content of each pixel in the second region is read. The exposing and interrupting are performed without resetting the pixels such that the read content of each first region pixel depends on the first exposure period and the read content of each second region pixel depends on the first and second exposure periods.

1. Field of the Invention
The present invention relates to operating a photoelectric sensor array having photoelectric converter elements and a shutter for controlling the exposure of the converter elements.
2. Background Art
A photoelectric sensor array includes photoelectric converter elements. Each converter element generates an electric signal corresponding to the magnitude of light striking the converter element and the exposure time during which the light strikes converter element. Thus, each converter element forms a single image point or pixel. The converter elements are freely-addressable and readable. As such, the electric signal generated by any particular converter element can be read. Likewise, an electric signal corresponding to the electric signals generated by two or more of any particular converter elements can be generated and read. The exposure of any particular converter element to light striking the converter element may be controlled by a shutter.
Such a sensor array is used, for example, in camera systems in automotive applications that record images of an environment. The recorded images are reproduced, for example, by image analysis responses, or the image sequences are stored. An area of application for such a sensor array is automotive driver assistance systems having different goals such as track recognition or traffic signal recognition.
Typically, the converter elements of a sensor array are associated with groups. The groups of converter elements are allocated to respective imaging tasks. For instance, a first group of converter elements is to receive light from a first light source and a second group of converter elements is to receive light from a second light source. In turn, an electric signal corresponding to the electric signals generated by the first group of converter elements in response to the light from the first light source striking these converter elements is generated and read. Likewise, an electric signal corresponding to the electric signals generated by the second group of converter elements in response to the light from the second light source striking these converter elements is generated and read. As such, each group of converter elements is a targeted partial region or image region of the sensor array. These regions (i.e., regions of interest) are respectively allocated to one of a multiplicity of different tasks or functions. However, these regions may be allocated to different tasks even though the regions are to receive light from the same light source. In any event, in operation, the entire converter elements of the sensor array are reset after each reading process, i.e., the contents of all converter elements are cleared. A problem is that different image regions may sometimes have very different brightness values (i.e., very different electric signals) and this must be taken into consideration for the different functions handled by the image regions.
Known semiconductor sensors can separate the attainable signal deviation of a converter element (i.e., pixel) into partial sections of linear characteristic curves having different slopes. This enables higher order dynamics to be represented through the signal deviation of the pixel. These multiple segmented characteristic curves are valid for the entire image sensor, and limit the attainable signal deviation for each segment of the characteristic.

Method for operating of a photoelectric sensor array having exposure interruption time periods


A large bale loading, hauling and stacking apparatus that mounts on a production truck chassis. Loading is accomplished with a centrally located bale clamping mechanism that picks up a bale, rotates it approximately 180 degrees and deposits it on a manipulator that can selectively reorient the bale for selective placement on a load rack. A stack of bales is thus formed on the load rack and later deposited in the field.

The present invention relates generally to agricultural self-propelled bale handling machines, and more particularly to such a machine that loads, hauls and stacks big bales.
A large proportion of the resources and time of the agricultural industry is directed toward the production of feed for animals, and most specifically to the production of baled stem and leaf crops such as hay. The conventional process is to cut and condition the crop with a windrower, deposit it on the ground to dry, bale the crop when appropriately dry, and then position the bales in stacks for storage or transportation. High labor requirements and increasing costs of hand hauling have caused a growing number of commercial growers to abandon their small square bale operation for a large bale package, such as round bales, or large rectangular bales 3′×3′, 3′×4′, or 4′×4′ in cross-section. Commercial haulers prefer large square bales over small square bales because they can drive into a field and be loaded for a cross-country trip in less than an hour. Large rectangular bales are loaded onto flat-bed trucks or semi-trailers directly in the field at about 20 tons per man-hour. It is these large bales that have become increasingly popular over the last several years, and to which this invention is most concerned.
While a pull-type machine could be designed and built to accomplish the desired tasks of loading, hauling and stacking large rectangular bales, it is most practical to develop a self-propelled unit, using a generally available truck cab and chassis as the source of motive and hydraulic power. Some mechanical devices for loading, hauling and stacking these large rectangular bales have been developed, however, they are unable to stack high enough, do not have the capability to lay various tie tiers, may greatly overload the front axle of the unit, and may not have adequate traction on rolling or wet terrain while loading.
Therefore, there is a need in the art for a convenient and automated system for loading a significant number of large bales onto a vehicle, with the option of tie tiers, hauling them relatively long distances, and stacking the bales in a stable manner.


A system and method is provided for implementing a dynamic form using file data retrieved from an external file source. An application executing on a server computer is responsive to a form request received from a user system computer to transform the retrieved file data into a format that includes new input elements. Unique namespaces are assigned to each of the new input elements, and the requested form and transformed file data are transmitted to the user system. The application is configured to create new XML file data that is mapped to the original XML file data in response to a user of the user system inputting data into the form. The new XML file data is compared to the original XML file data to identify missing elements. Missing elements are inserted into the new XML file data, and the new XML file data is stored in a memory.

The Internet is being used more and more by businesses, organizations, and institutions to provide web sites that allow interested parties to purchase goods and/or to participate in services remotely. In fact, the entire process of purchasing goods and selecting services is completed using a personal computer or other computing device that is connected to a communication network, such as the Internet.
Typically, web sites provide electronic documents, such as electronic forms ("forms"), that allow a user to view products or services and to select and/or designate products or services for purchase. Such forms are commonly defined using a hypertext markup language ("HTML"), which has been developed for desktop computers and fast and stable wired networks and/or for wireless computing devices connected to a wired network. Web browsing applications that are executable on desktop computers typically support extended HTML features, such as frames, cascading style sheets ("CSS"), and active content, such as, for example, JavaScript® or Java®, as well as other proprietary extensions.
HTML includes various input elements that are used to define entry fields in a form, such as a data input field. Each of the various input elements is assigned a name attribute to distinguish it from another input element. The user inputs data into the input fields of the form or changes data displayed in the input fields of the form. The input values are "submitted" to a Uniform Resource Locator ("URL") associated with the web site. The data routed to the URL consists of name/value pairs such that the name of each input element is used to identify the values entered in the corresponding input field of the form.
The data displayed in the input fields on some forms is hard coded into the HTML. Such forms are often referred to as "static" because they have a fixed layout that includes fields, text and graphics. In contrast, "dynamic" forms retrieve data from an external data source, such as a relational database or an eXtensible Markup Language ("XML") file that is called by the HTML, and the user can change the appearance of "dynamic" forms. Unfortunately, however, when a form is created using an eXtensible Stylesheet Language Transform (XSLT) using data from an XML file as the external data source, the user cannot update/save data modifications to external data source from which the original data was retrieved.

System and method for implementing dynamic forms


The present invention relates to the use of Collismycin and derivatives thereof as inhibitors of oxidative stress in cells and their use for the preparation of medicaments for the treatment of oxidative stress-induced diseases or conditions, especially neurodegenerative diseases, such as Alzheimer's Disease and Parkinson's Disease.

Alzheimer's disease (AD) and Parkinson's disease (PD) are the most frequent progressive neurodegenerative diseases affecting millions of people in the world. Because a significant percentage of patients share common clinical and pathological features from both entities, this seems to indicate the existence of a common pathological mechanism. Based on in vitro and in situ data, an unified molecular oxidative stress model induced by dopamine (DA), 6-hydroxydopamine (6-OHDA); 5,6 & 5,7-dihydrytryptamine (5,6 & 5,7 MT); amyloid beta 25-35 (Aβ25-35), and metals [e.g. iron (Fe2+), copper (Cu2+), zinc (Zn2+), manganese (Mn2+)] has been widely proposed as a possible explanation of neural loss in AD/PD overlapping cases. This hypothesis might contribute to a better understanding of the pathophysiology cascades of both disorders, and also support the notion that oxidative stress generated by H2O2 represent an essential molecule of intracellular signalization leading to cell death.
Therefore, an interesting approach for developing new pharmaceutical compounds for treating neurodegenerative diseases may be designing compounds which inhibit cellular oxidative stress. Reactive oxygen species (ROS), such as oxygen radical superoxide (O2) or hydrogen peroxide (H2O2), are produced during normal metabolic processes and perform several useful functions (Reactive oxygen species and the central nervous system, Halliwell B., J Neurochem.; 1992, 59 859: 1609-1623). Cells are provided with several mechanisms to control levels of these oxidative agents, for instance, superoxide dismutase (SOD), glutathione or vitamin E. In normal physiological conditions, a balance between ROS and these anti-oxidative mechanisms exists. An excessive production of ROS and a loss of efficiency of the anti-oxidative defences can lead to pathological conditions in cells and provoke tissue damage. This event seems to occur more dramatically in neurons, because of their high rate of metabolic activity, and thus seems to be related to a series of degenerative processes, diseases and syndromes, for example, Alzheimer's Disease, Parkinson's Disease, amyotrophic lateral sclerosis (ALS) and schizophrenia (Glutathione, oxidative stress and neurodegeneration, Schulz et al., Eur. J. Biochem.; 2000, 267. 4904-4911). Also other diseases or pathological conditions have been related to oxidative stress, such as Huntington's Disease (Oxidative damage in Himtington's disease, Segovia J. and Perez-Severiano F, Methods Mol. Biol; 2004; 207: 321-334), brain injuries, such as stroke and ischemia, (Oxidative Stress in the Context of Acute Cerebrovascular Stroke, El Kossi et al., Stroke; 2000; 31: 1889-1892), diabetes (Oxidative stress as a therapeutic target in diabetes: revisiting the controversy, Wiernsperger N F, Diabetes Metab.; 2003; 29, 579-85), multiple sclerosis (The role of oxidative stress in the pathogenesis of multiple sclerosis: the need for effective antioxidant therapy, Gilgun-Sherki Y. et al., J. Neurol: 2004; 251 (3): 261-8), epilepsy (Oxidative injury in epilepsy: potential for antioxidant therapy?, Costello D. J. and Delanty N., Expert. Rev. Neurother.; 2004; 4(3): 541-553), atherosclerosis (The oxidative stress hypothesis of atherogenesis, Iuliano L., Lipids; 2001; 36 suppl: S41-44), Friedreich's Ataxia (Oxidative stress mitochondrial dysfuntion and cellular stress response in Friedreich's ataxia, Calabrese et al., J. Neurol. Sci.; 2005) and heart failure (Oxygen, oxidative stress, hypoxia and heart failure, Giordano F. J., J. Clinic. Invest.; 2005; 115 (3): 500-508). Treatments that lead to an enhancement of the anti-oxidative mechanisms may slow the progression of some of the mentioned diseases.
Collismycins are 2,2′-bypiridine molecules which have been isolated from Streptomyces species. Several kinds of these molecules were firstly isolated by Gomi et al. (Novel Antibiotics SF2738A, B and C and their analogues produced by Streptomyces sp., Gomi et al., J. Antibiot., 1994, 47:1385-1394) from a culture of Streptomyces sp. SF2738, and their structure was described by spectral analyses and chemical conversion. Biological activities of different types of collismycins were also studied and, among them, specially Collismycin A was described to be endowed with antibiotic activity against some bacteria and a wide range of fungi. This antifungal activity against some species, such as, Saccharomyces cerevisiae and Candida albicans, has been demonstrated by Stadler et al. (Antifungal Actinomycete Metabolites Discovered in a Differential Cell-Based Screening Using a Recombinant TOPO1 Deletion Mutant Strain, Stadler et al., Arch. Pharm. Med. Chem., 2001, 334: 143-147). Two yeast strains, a wild type (ScAL 141) and a recombinant topoisomerase 1 (TOPO1) deletion mutant (ScAL 143), were used for the screening of compounds produced by actinomycetes strains WS 1410 and BS 1465. They were also used to test the biological activities of collismycins, among other compounds, with the activity of camptothecin as a reference. Results show that the mechanism of action of collismycins is not based on the inhibition of topoisomerase 1, because collismycins are active against both wild type and mutant yeast strains.
Cytotoxicity is another biological activity that has been described for some collismycins. This property was also demonstrated by Gomi et al. (see above) in a study of the cytotoxic ability of these molecules on P388 murine leukaemia cells. In JP5078322 Collismycin is related to the use of Collismycins A and B as antitumoral substances, useful as carcinostatic agents, for parenteral or oral administration. A lot of other patent publications refer to the use of Collismycins A and B in combination with other antitumoral agents. This is the case, for example, of WO02/053138, which discloses the use of incensole and/or furanogermacrens, derivatives, metabolites and precursors thereof in the treatment of neoplasia, particularly resistant neoplasia and immune dysregulatory disorders. These compounds may be administered alone or in combination with conventional chemotherapeutic, anti-viral, anti-parasite agents, radiation and/or surgery. The listed chemotherapeutic agents include Collismycins A and B.
Another biological activity of collismycins was described by Shindo et al. in 1994 (Collismycins A and B. novel non-steroidal inhibitors of dexamethasone-glucocorticoid receptor binding, Shindo et al., J. Antibiot., 1994, 47: 1072-1074). It was suggested that Collismycin A and its isomer B could have an anti-inflammatory activity inhibiting the dexamethasone-glucocorticoid receptor binding, although no complementary results to this study seem to have been published.
A synthesis of Collismycin A has been described by Trecourt et al. in 1998 (First Synthesis of Cacrulomycin E and Collismycins A and C. A New Synthesis of Caerulomycin A, Trecourt et al. J. Org. Chem., 1998, 63:2892-2897) starting from 2,2-bipyridine N-oxide. Functionalization at C-4 and C-6 through different pathways leads to 6-bromo-4-methoxy-2,2′-bipyridines; a subsequent metalation reaction introduces a methylthio moiety at C-5. In a last step of the synthesis pathway, Br at C-6 is substituted by a formyl group which reacts with hydroxylamine to provide Collismycin A. This document is herewith incorporated by reference into the present application.
In particular, Collismycin A presents the following structure:
and Collismycin B:

Some other 2,2′-bipyridine compounds with structures close to that of Collismycin have been described in the literature.
Some examples are: Pyrisulfoxin-A (N. Tsuge et al., J. Antibiot. 52 (1999) 505-7)
Caerulomycin-B; Cerulomycin-B
Caerulomycin-C; Cerulomycin-C
Caerulomycin; Caerulomycin-A; Cerulomycin

Use of collismycin and derivatives thereof as oxidative stress inhibitors


A digital camera module includes an image capture device mounted on a flexible circuit substrate. In one embodiment of the digital camera module, the image capture device is mounted directly (e.g., by an adhesive) on the flexible circuit substrate. A stiffener (e.g., a piece of circuit board material) is mounted to the back of the flexible circuit substrate to support wire bonding of the image capture device onto the flexible circuit substrate and/or to support the mounting of additional components (e.g., a lens housing).

1. Field of the Invention
This invention relates generally to electronic devices, and more particularly to a device for mounting an image sensor. Even more particularly, the invention relates to a device for mounting an image sensor on a flexible substrate such as a flexible printed circuit (FPC).
2. Description of the Background Art
Unlike traditional cameras that use film to capture and store an image, digital cameras use various solid-state devices collectively referred to as image capture devices. These small silicon chips contain millions of photosensitive diodes called photosites. When the shutter (mechanical or electrical) is open, each photosite records the intensity or brightness of the incident light by accumulating a charge; the more light, the higher the charge. The brightness recorded by each photosite is then stored as a value indicative of the brightness and/or color for a corresponding pixel of the captured image. The brightness/color values can then be used to set the colors and brightness of dots on a display screen or ink on a printed page to reconstruct the image.
Image capture devices are mounted within digital cameras so as to be aligned with a lens and an opening in the camera body. The silicon chip (die) itself is typically mounted onto a ceramic leadless chip carrier (CLCC), which in turn is mounted on a printed circuit board (PCB). The CLCC is made of a ceramic material which can withstand high temperatures to withstand the soldering of electrical connections. It does not have leads but has one set of contact pads around it's perimeter for making electrical connections to the PCB via a reflow solder process and another set of contact pads or lead frame for making electrical connections (e.g., via wire bonding) with the die. During the mounting process, the contact pads of the CLCC are connected (e.g., via soldering) to electrical plated pads of the PCB. A lens is then mounted to the PCB over the die and CLCC. Finally, the PCB is mounted in a fixed position within the camera, so that the lens aligns with an opening in the camera.
The devices and assembly methods of the prior art have several disadvantages in both the manufacturing process and the quality of the device. Alignment of the image capture device with the opening in the camera can be difficult, particularly in small cameras (e.g., cameras in mobile telephones). Because multiple devices are mounted on the PCB, the tolerances accumulate to reduce the precision with which the image capture device can be aligned with the opening. Additionally, PCBs typically include other components (e.g., keypad, etc.) that must be aligned with other openings, further complicating the alignment problem.
FIG. 1 illustrates one example of a prior art solution to the above-described alignment problem. In this particular embodiment, a camera device 100 includes an independent camera module 102, which is flexibly coupled to a main PCB 108. Independent camera module 102 includes a PCB 106 that supports a CLCC 104, which in turn supports a die 114. PCB 106 is connected to a main PCB 108 via a flexible electrical circuit 120 that transfers data/power between the independent camera module PCB 102 and main PCB 108. The FPC 120 decouples the physical alignment of independent camera module 102 and main PCB 108.
Although the device of FIG. 1 helps alleviate the alignment problem, it creates other disadvantages. For example, camera module 100 requires more components than the previously described embodiment, such as FPC 120 and an additional PCB 106. Further, the additional components require additional assembly steps. The cost of the additional components and the additional assembly steps increase the overall cost of the product.
Note also that camera module 100 includes an increased number of electrical connections and, therefore, has an increased number of points of possible failure. In particular, camera module 100 includes at least four sets of electrical connections. A first set of electrical connections 112 exist between die 114 and CLCC 104. A second set of electrical connections 113 exist between CLCC 104 and PCB 106. A third set of electrical connections (inside connector 136) exist between PCB 106 and FPC 120. Finally, a fourth set of electrical connections (inside connector 138) exist between FPC 120 and main PCB 108. The increased number of electrical connections, and thus the increased number of points of possible failure, decreases the overall reliability of the product.
What is needed, therefore, is a device that helps alleviate the alignment problem, yet requires fewer components than prior art solutions. What is also needed is a device that helps alleviate the alignment problem, yet includes fewer electrical connections (e.g., solder points, etc.), and thus fewer points of possible failure, as compared to the prior art solutions. What is also needed is a device that requires fewer manufacturing steps and/or a shorter assembly time as compared to the prior art.

System and method for mounting an image capture device on a flexible substrate


A double-sided organic electro-luminescent device. The device comprises a substrate having a first pixel region and a second pixel region adjacent thereto. First and second organic light-emitting diodes are disposed in the first and second pixel regions, respectively, in which the light-emitting direction of the first organic light-emitting diode is opposite that of the second organic light-emitting diode. First and second thin film transistors are disposed in the second pixel region, in which the first thin film transistor is electrically connected to the first organic light-emitting diode and the second thin film transistor is electrically connected to the second organic light-emitting diode.

1. Field of the Invention
The invention relates to a flat panel display (FPD), and in particular to an organic electro-luminescent device with prolonged lifetime.
2. Description of the Related Art
Organic electro-luminescent devices or organic light-emitting diodes (OLEDs) are active lighting devices using organic materials. Compared with conventional inorganic LEDs, OLEDs can be easily fabricated on a large substrate by forming an amorphous silicon layer thereon. Additionally, displays utilizing OLEDs require no backlight module, whereby the manufacturing process is simpler and costs are reduced. OLED technology is highly developed and can be employed in small panels such as those in personal digital assistants (PDAs) or digital cameras.
The organic electro-luminescent device typically comprises an anode, a cathode, and an organic light emissive layer disposed therebetween. The organic light emissive layer may comprise a hole transport layer (HTL) adjacent to the anode, an electron transport layer (ETL) adjacent to the cathode and an electro-luminescent layer interposed therebetween. When an electrical potential difference is applied between the anode and the cathode, electrons are injected into the electron transport layer from the cathode and pass through the electron transport layer and the electro-luminescent layer. At the same time, holes are injected into the hole transport layer from the anode and pass therethrough. The injected electrons and holes are recombined at the interface of the electro-luminescent layer and the hole transport layer, releasing energy as light.
Generally, organic electro-luminescent devices are applied in electronic products with a single-sided display. With the progress of electronic products, however, double-sided display has become required for many products, such as collapsible mobile phones. FIG. 3 is a plane view of a conventional double-sided organic electro-luminescent device. The organic electro-luminescent device 10 includes a substrate 11 having two adjacent pixel regions 12 and 14. A bottom-emitting OLED 16 and a thin film transistor 20 are disposed in the pixel region 12. A top-emitting OLED 18 and another thin film transistor 22 are disposed in another pixel region 14. The thin film transistor 20 is electrically connected to the OLED 16 and the thin film transistor 22 is electrically connected to the OLED 18.
However, in order to provide double-sided light emission, a single pixel region in the organic electro-luminescent device 10 must be divided into two pixel regions 12 and 14, thus the aperture ratio (AR) of the device 10 is reduced and in particular to the pixel region 12 that includes the bottom-emitting OLED 16. In order to maintain brightness of the organic electro-luminescent device 10, power consumption must be increased, thus reducing lifetime.

Double-sided organic electro-luminescent device


An air bag module (20) including: an inflator (200) for providing inflation gas; a bracket assembly (100) having an integral spring portion for resiliently biasing the inflator toward a retained position.

The present invention relates generally to air bags and more particularly to an improved apparatus and methodology for fabricating and assembling an air bag module.
The illustrated embodiment of the invention identifies a side air bag module; however, the present invention can be implemented with other types of air bag modules, such as curtain, passenger and driver.
It is an object of the present invention to provide an air bag module having fewer parts and an improved bracket with a reactive or spring-like portion.
Accordingly the invention comprises: an air bag module 20 comprising: an inflator 200 for providing inflation gas; a bracket assembly 100 comprising an integral spring portion for resiliently biasing the inflator toward a retained position.
Many other objects and purposes of the invention will be clear from the following detailed description of the drawings.

Air bag module including improved inflator retainer assembly


A processor that executes an instruction stream having at least one compressed register field allows for smaller programs and greater processing speed. The instructions have at least one n-bit register number field and at least one m-bit register code field, where n is less than m. The n-bit register number field is capable of designating any register in a set of working registers. The m-bit register code field is capable of designating any register of a subset of the working registers. The m-bit register code may designate a source or destination register of the current instruction, a source or destination register of the last instruction, or a destination register of the second to last instruction. An instruction fetch section of the processor fetches the instruction words from memory. As part of the instruction decoding process, the m-bit register code field is passed to a register designation code conversion, or register mapping, section where the m-bit register code is converted into an n-bit register number. Various embodiments of the register mapping section include: (1) a fixed mapping such that identical inputs always cause identical outputs; (2) a conversion table in which all or part of the table's content may be updated by execution of either a special or regular instruction.

1. Field of the Invention:
The present invention relates to a data processing device which has a plurality of working registers, and, in particular, to a data processing device which employs a stored program method.
2. Description of the Related Art:
A data processing device having a plurality of general registers called working registers can be characterized by the number of register operands which one instruction can designate. For instance, in a conventional RISC architecture, three registers can be designated with a typical operation instruction. Two of them are used as a source register for supplying two values to be added in an addition instruction, and the other one is used as a destination register for storing the operation result. This method is referred to as a "three register operand" method.
As an example of this method, the format of an instruction for operation among registers according to an MIPS architecture is shown in FIG. 1. The MIPS architecture is disclosed in "A quantative approach for design, realization and evaluation of a computer architecture" by David A. Patterson, John L. Hennessy (published by Nikkei BP in December 1992). In the MIPS architecture, machine code is of a 32-bit fixed length, and an instruction for operation among registers consists of the following fields: (from the MSB side) an instruction operation code 201 for indicating the type of instruction; a first source register number 202 for indicating a register which contains a first source operand; a second source register number 203 for indicating a register which contains a second source operand; a destination register number 204 for indicating a register which stores an operation result; a short constant 205 for indicating a small constant needed by some instructions; and an extension instruction operation code 206 that is an extension of an instruction operation code needed by some instructions. Note that bracketed numbers following respective field names in the drawing indicate the number of bits constituting respective fields.
As another example of the prior art, Cold RISC architecture has recently been made available. The Cold RISC architecture uses a shorter instruction achieved by reducing the code size of a basic instruction to thereby compress a program area. As a design example of such an architecture is Hitachi single-chip RISC microcomputer SH 7000 series, the format of an instruction for operation among registers used therein is shown in FIG. 2. In the SH7000 architecture, machine code is of a 16-bit fixed length, and an instruction for operation among registers consists of the following fields: (from the MSB side) a first instruction operation code 301 for indicating the type of instruction; a source register number 302 for indicating a register which contains a second source operand used in an operation; a destination register number 303 for indicating a register which stores an operation result, and contains a first source operand used in an operation; and a second instruction operation code 304 for indicating, in cooperation with the first instruction operation code, the type of instruction.
This method is significantly different from the above MIPS architecture in that one of the source operands needed in a binomial operation is extracted from the destination register. This method is referred to as a binomial register operand method.
A recently available processor employs a method to process instructions by overlapping them like a pipeline architecture, an adaptable construction thereof being shown in FIG. 3.
In the drawing, an instruction fetch section 401 receives the next instruction to be executed from an instruction cache 406 and outputs the obtained machine code to an instruction decode section 402. The instruction will be processed through the following procedure.
The instruction decode section 402 first separates the machine code into fields according to the type of instruction, and then extracts the following: an instruction operation code 411 for indicating the type of an operation to be processed, the immediate data 412 that is a constant operand embedded in the machine code, a first source register number 413, a second source register number 414, and a destination register number 415. Then, data of the registers in a register file 403 designated by the first and second source register numbers are read.
When the instruction operation code instructs execution of an operation such as an addition or subtraction operation, an operation execution section 404 executes the instructed operation according to the content read from source registers, so that the operation result 419 is stored in the register designated by the destination register number.
When the instruction operation code instructs storage in a memory, the operation execution section 404 computes a data memory address 416, so that data is written into a data cache 407 using the data memory address and write data 417.
When the instruction operation code instructs load from a memory, data is read from the data cache using the data memory address 416 generated by the operation execution section 404, so that the read data 419 is written into the register designated by the destination register number.
If the instruction cache or the data cache does not have a target machine code or data, machine code or data is transmitted from an external memory to the cache via an external memory interface 408.
The three register operand method is characterized in that it requires fewer execution instructions compared to the two register operand method. This is because an operation result always overwrites a source operand stored in one of the registers in the two register operand method. If data stored in a register is referred to by a plurality of instructions, the data may have to be copied to another register before executing operations. Taking as an example a function which executes a binomial operation using registers rs1 and rs2, and stores the operation result in a register rd will be described. In the case of the three register operand method, this function can be executed through one instruction, whereas it cannot using the two register operand method. In order to execute this function in the two register operand method, two instructions are necessary, namely, 1) an instruction for copying data in a register rs1 into a register rd, and 2) an instruction for executing a binomial operation op, for data in the registers rd and rs2 and storing the operation result in the register rd.
As described above, the three register operand method is effective in reducing the number of instructions, that is, the number of cycles to execute a program. However, this conventional method involves many problems in view of reduction of a program size because it causes a longer instruction length for each individual instruction.
Meanwhile, in the Cold RISC architecture, wherein a 16-bit machine code, for instance, is employed as a reference instruction to thereby reduce a program size, it is difficult to designate three registers as operands with a only single 16-bit instruction. In the case where sixteen general registers are provided, for instance, a 12-bit field is necessary to designate three registers as operands, which leaves only a 4-bit field available. However, it is difficult to store encoded data regarding the type of instruction or operation in the 4-bit field.

Processor for executing an instructions stream where instruction have both a compressed and an uncompressed register field


An apparatus for removing surface irregularities from a flat workpiece includes one or more abrading assemblies through which the workpiece passes sequentially. Each abrading assembly has a lower contact assembly and an upper contact assembly. The upper contact assembly is precisely spaced above the lower contact assembly in opposing parallel relation to the lower assembly. The lower and upper contact assemblies reciprocate in opposing directions to provide abrading action to the workpiece.

Masks are used at various stages in semiconductor processing and packaging to form patterns on various types of substrates. For instance, masks of various materials (e.g. metal, quartz etc.), sizes and types may be used in conjunction with photosensitive materials to expose and form semiconductor devices in a semiconductor substrate. Masks may be used to form interconnections between semiconductor devices. Additionally, masks are commonly used to form interconnection patterns used to connect integrated circuits to packaging substrates. For example, masks are commonly used to form controlled collapse chip contacts ("C4") on semiconductor wafers for making connection between an integrated circuit chip and a ceramic substrate.
Defects on the surface of a mask can arise during mask fabrication or subsequent handling. Such defects generally take the form of non-planar areas (e.g. "high spots") or other irregularities on the generally flat surface of the mask. The defects can cause a variety of problems. For example, if the "high spot" flakes off the mask and lodges in the surface of a semiconductor wafer, it may cause an immediate or future accidental electrical short, particularly if the mask is metal. Or, a defect may scratch the wafer, resulting in physical damage that can also be manifested by functional or reliability failures. In addition, non-planar masks (e.g. masks which do not have a uniform thickness across their surface area) can cause inaccuracies in patterning.
Because of the difficulties created by defects on the mask surface, great care is taken to avoid or minimize the occurrence of the defects. Masks are carried in protective containers designed to avoid damage to the masks and are carefully inspected after fabrication and after each use to identify defects so that the defective masks are not used to process semiconductor wafers. While this practice helps to avoid the defective masks from contaminating or otherwise damaging wafers, it results in unacceptable waste of the defective masks. What is needed is a method to repair the defective masks, so that they may be re-used without causing damage or contamination to the underlying substrate to be processed.

Apparatus for removing surface irregularities from a flat workpiece

International Business Machines Corporation