A method of producing a polymer-clay nanocomposite comprises providing a supply of polymer-clay mixture, exfoliating the mixture through solid-state shear pulverization in the presence of cooling sufficient to maintain the extruded mixture in the solid state during the pulverization, and discharging the resulting exfoliated mixture. The invention is also directed to a method of producing a polymer hybrid nanocomposite, wherein a component is dispersed throughout a polymer matrix by solid-state shear pulverization of a polymer mixed with the second component.

The subject of polymer hybrid composites based on layered inorganic compounds such as clays has been the subject of intense industrial and academic study for more than a decade. Polymer materials may be filled with several inorganic, synthetic and/or natural minerals in order to increase properties like heat resistance, mechanical strength and impact resistance. However, there is little or no interaction between the two mixed components. In order to increase interaction between the polymer and reinforcing material, the dimensions of the reinforcing elements on a molecular level must be decreased.
Layered silicates or clays are one material class of reinforcing elements on a nano-scale. Such elements have dimensions of the order of one billionth of a meter, or one nanometer. Such a composite is called a nanocomposite. There are many types of nanocomposites, whereby the defining characteristic is that the reinforcing component has the dimensions mentioned above.
The most heavily researched type of nanocomposite uses layered mineral clays as the reinforcing component. Polymer-clay nanocomposite materials have attracted a great deal of attention because they provide enhanced mechanical and thermal properties as compared to conventional materials. Specifically, these hybrid composites exhibit increased tensile strength, modulus, and heat distortion resistance, as compared with a pure polymer. The composites also have lower water sensitivity, reduced permeability to gases, and a similar thermal coefficient of expansion. Further, it has been found that nanocomposites impart a level of flame retardance and UV resistance not present in the pure polymer component. Because of these enhanced properties, such nanocomposites are useful in the electronics, automobile, aircraft, and aerospace industries, among others.
The type of clay, the purity of the clay, and the choice of clay pre-treatment are all controllable variables that influence the nature and properties of the final nanocomposite. Many clays are aluminosilicates, which have a sheet-like or layered structure, and consist of silica SiO4 tetrahedra bonded to alumina AlO6 octahedra in a variety of ways. A 2:1 ratio of the tetrahedra to the octahedra results in smectite clays, the most common of which is montmorillonite. Smectite clays are clays that can be swollen with small molecules. Other metals such as magnesium may replace the aluminum in the crystal structure.
Montmorillonite clay is the most common type of clay used for nanocomposite formation. Montmorillonite naturally forms stacks of plate-like structures, or platelets. Each platelet is less than 10 Angstroms thick, but over 200 times that in width. The spaces between these platelets are called gallery spaces. Each platelet is composed of silicon oxide and aluminum oxide. Under the proper conditions, the gallery spaces can be swollen and filled with monomer, oligomer, or polymer. Specifically, a swelling of the gallery spaces increases the distance between platelets in the stacks. Clay platelets swollen with polymer are said to be intercalated. If the clay swells so much that it is no longer organized into stacks, it is said to be completely exfoliated.
In addition to montmorillonite clay, other types of clay may also be used, including hectorites, which contain very small platelets, and synthetic clays. Synthetic clays can be produced in a very pure form and can carry a positive charge on the platelets, in contrast to the negative charge found in montmorillonites.
Depending on the precise chemical composition of the clay, the layers generally bear a charge on the surface and edges of the platelets. This charge is balanced by counter-ions, which reside in part in the gallery spaces between the layers. Thus, the stacks of clay platelets are held tightly together by electrostatic forces. Because of the charged nature of pure clay, the clay is generally highly hydrophilic. For example, montmorillonite is naturally hydrophillic. This makes pure clay poorly suited to mixing and interacting with most polymer matrices. As such, a necessary prerequisite for successful formation of polymer-clay nanocomposites is the alteration of the clay polarity to make the clay organophilic. An organophilic clay can be produced from a normally hydrophilic clay by ion exchange with an organic cation such as an alkylammonium ion. The particular pre-treatment process used may have an effect on the formation of the nanocomposite product formed. Such pre-treatment processes are well known in the art.
As noted above, a nanocomposite may be in the form of an intercalated or exfoliated hybrid. In an intercalate hybrid, the polymer component is inserted between the clay layers or platelets such that the gallery spaces are expanded, but the platelets still bear a well-defined spatial relationship to each other. In an exfoliated hybrid, the layers or platelets comprising the clay stacks have been completely separated and the individual platelets are distributed throughout the polymer matrix. Various factors affect this delamination of the clay stacks, including the exchange capacity of the clay, the polarity of the reaction medium and the chemical nature of the interlayer cations (e.g. onium ions).
Levels of exfoliation may be determined by an x-ray scattering test. An absence of scattering peaks at a characteristic scattering angle indicates high levels of exfoliation. Conversely, a large scattering peak indicates decreased (or poor) exfoliation. The scattering angle is inversely correlated with interlayer or gallery spacing. Specifically, scattering angle (theta) is linearly proportional to l/d, where d equals interlayer spacing. Therefore, the level of exfoliation is measured by analyzing the level of scattering intensity at the expected scattering angle (based on the interlayer spacing). Thus, the interlayer or gallery spacing is a function of the particular clay. Complete exfoliation, wherein all stacks are delaminated into single platelets surrounded by polymer, may not be required to attain optimal nanocomposite properties. However, substantial exfoliation is generally desired in order to attain the above noted enhanced properties in the resulting product. Substantial or high levels of exfoliation is defined herein as an exfoliation level that lacks any significant scattering peak in an x-ray scattering test.
In addition to an x-ray scattering test, electron microscopy can provide a pictorial perspective of the exfoliation level in a nanocomposite. However, it is does not provide as quantitative a measure of the exfoliation level of the entire sample compared to an x-ray scattering test. Dispersion of the clay or other reinforcing material throughout the polymer matrix may also be seen with electron microscopy. Generally, a consistent dispersal of the reinforcing material is desirable, wherein the reinforcing material is not clumped in certain areas of the matrix.
Various attempts have been made to produce a substantially exfoliated nanocomposite. The most successful method has been in situ polymerization, wherein a monomer is polymerized in situ to give the corresponding polymer-clay nanocomposite. In the late 1980's and early 1990's, researchers from Toyota™'s Central Research and Development Laboratories demonstrated an in situ polymerization method of monomer to nylon, producing nylon-6 (a clay-nylon hybrid). Montmorillonite clay was exchanged with an acid, replacing the cations on the clay surface and swelling the clay. The modified clay was dispersed in the polar monomer, epsilon-caprolactam, which was then polymerized into the polymer commonly known as nylon-6.
Such in situ polymerization methods rely on chemical processes to achieve the desired exfoliated product, and there success has been limited. A polar monomer can intercalate between clay sheets, and polymerization leads to exfoliation. However, these chemical methods have not been successful for other polymer components, particularly nonpolar polymers. Certain polymers, such as polypropylene, require a much more complicated synthetic approach than other monomers, such as those involved in producing nylon-6. As such, polypropylene nanocomposites, or other such polymers, have not been produced by in situ polymerization (i.e. polymerizing propylene in the presence of clay).
Attempts to produce well-exfoliated polymer-clay nanocomposites by non-chemical methods (e.g. melt blending or solution blending of polymer-clay systems) have not been successful. Twin-screw extrusion of polymer-clay mixtures has not yielded well-exfoliated clays in the polymer, though it has resulted in relatively good polymer-clay contact. Twin-screw extrusion, or melt extrusion, is well known in the art, wherein a mixture or compound is processed through a twin-screw extruder or compounder, or an intensive mixer, such as a Farrel Continuous Mixer™.
In addition to melt-extrusion, the method of solid-state shear pulverization has been developed for preparing polymer materials, as disclosed in U.S. Pat. No. 5,814,673 to Khait and U.S. Pat. No. 6,180,685 also to Khait, the disclosures of which are incorporated herein by reference. As disclosed in the Khait patents, a chemical change to a polymer material is effected by application of mechanical energy through solid-state shear pulverization in the presence of cooling sufficient to maintain the material in the solid state during pulverization. However, the Khait patents do not disclose or suggest a method of producing highly exfoliated polymer-clay nanocomposites.
The present invention is directed to a method of producing highly exfoliated polymer-clay nanocomposites through a non-chemical process, whereby the resulting product exhibits a high level of exfoliation and dispersion. The polymer-clay nanocomposites produced therefrom may be used in a wide variety of applications, including barrier films for reduced permeability, and applications requiring a polymer with improved solvent resistance, reduced flammability, increased strength and/or hardness, light weight, and resistance to heat distortion. Industrial applications for such nanocomposites include, inter alia, the automotive, aircraft and aerospace industries.

Method of producing an exfoliated polymer-clay nanocomposite through solid-state shear pulverization


An integrated circuit device includes a data buffer, coupled to an external connector, providing a data signal on the external connector. A test buffer, coupled to the data buffer, receives the data signal and provides a testing output signal to a delay circuit. The delay circuit receives the testing output signal at a first clock rate internal to the integrated circuit device and compares test data in the testing output signal to expected test signal values. The delay circuit provides a result to an external connector at a second clock rate that is slower than the first clock rate.

1. Field of the Invention
The present invention relates generally to electrical devices and, more particularly, to the testing of integrated circuit devices.
2. Related Art
Semiconductor or integrated circuit devices have continually evolved to provide improvements such as miniaturization, reduced power consumption, reduced cost, and increased speed. One consequence of the rapidly increasing speed (e.g., increasing data rate) of semiconductor devices is that adequate testing of the semiconductor devices becomes difficult and expensive. For example, integrated circuits now routinely operate at data rates above 100 MHz. For testing purposes, such data rates may require expensive, specialized automated test equipment.
When data rates reach or exceed 400 MHz, current commercially available automated test equipment may fail to detect the data with sufficient accuracy in order to perform the desired testing. In particular, during testing, signal parameters such as voltage, current, and timing or skew must be precisely controlled and monitored, for example, using currently employed techniques and systems, such as special load boards and handler designs. As data rates continue to increase, these currently employed techniques and systems, taken alone, will not be adequate to perform high-speed testing. As a result, there is a need for improved methods and techniques for testing integrated circuit devices.

This patent is subject to a terminal disclaimer.


A manufacturing method of a resistive random access storage unit, includes: forming a resistance layer on a first metal layer having a flat surface; forming a passivation layer on the resistance layer; performing an etching process to obtain a plurality of basic units, a basic unit comprising a first metal layer, a resistance layer, and a passivation layer, which are laminated sequentially; depositing a insulating dielectric layer, and flattening the insulating dielectric layer; etching the insulating dielectric layer and the passivation layer to form contacting holes corresponded to the basic units; filling metal wires in the contacting holes; forming a second metal layer. According to the above method, a uniformly distributed resistance can be formed on a whole wafer.

With the development of technology, a capacity, an energy consumption, and a accessing speed of the conventional NAND flash memory have reached bottlenecks.
A resistive random access memory (RRAM) is a new non-volatile random access memory. Its principle is to use a resistance mutation of a special metal oxide near a threshold voltage to represent 0 and 1 of a storage unit. RRAM has characteristics of larger capacity, lower energy consumption and faster accessing speed.
A basic storage unit of the RRAM includes two metal layers and a resistance layer sandwiched between the two metal layers. Conventionally, the resistance layer is made of WOx. A manufacturing process is compatible with a conventional MOS process. The manufacturing process includes: filling a tungsten plug on a base metal, grinding and oxidizing the tungsten metal, then forming a metal layer.
However, there are problems in the manufacturing process, which leads to an uneven distribution of resistance on the wafer.

Method for manufacturing resistive random access storage unit


A resource searching device includes a requirement acquisition unit configured to acquire resource requirement information including resource requirements for a plurality of resources, the resources being related to a deployment request of a plurality of received resources and being related to devices or connections between the devices; a calculation unit configured to refer to system configuration information including information on the resources related to devices and connections between the devices in an information processing system to be managed, and to calculate fulfillment rate information including a fulfillment rate for each of the resources that satisfy the resource requirements; and a searching unit configured to search for a plurality of resources corresponding to the deployment request of the plurality of resources by sequentially selecting the resources that satisfy the resource requirements on the basis of the fulfillment rate information and the connections between the devices in the deployment request.

In a large-scale data center represented by the cloud, it is taken into consideration that which usable resource is to be allocated for a service deployment request from a user. Such resource allocation is taken into consideration both in the case of a single data center and in the case of a plurality of data centers.
Conventionally, resources have mainly been deployed by a virtual machine (VM: Virtual Machine) unit. That is, for a resource request of "needing a number X of VMs having a certain kind of performance and loaded with a certain kind of software", a server (group) that satisfies the request is searched and a resource is allocated.
However, in recent years, requests for resource deployment by a service unit are increasing. That is, not only (virtual) apparatuses such as a server and a storage configuring a service but also topology of a network connecting the apparatuses are taken into consideration to allocate a resource. As one of technologies of deployment by such a service unit, there is a system which allows resource selection satisfying restrictions for interacting operations for a request of a correlated resource group by a resource requester.

Resource searching device and computer readable recording medium storing resource searching program


A chip-type semiconductor light-emitting device includes a substrate (2). An LED element (1) is mounted on a pad (3a) formed in one (3) of a pair of electrodes (3, 4) formed on the substrate (2). A reflector (6) is formed with an aperture (6c) defined by a slant surface (6Z) and opened to the outside to accommodate therein the LED element (1). Translucent resin is filled in the aperture (6c). The slant surface (6Z) has a plurality of reflection surfaces (P, Q) formed continuous thickness-wise of the reflector, which are selected in inclination angle relative to the substrate (2) such that light is reflected to the immediate upward at respective mid-slopes of the reflection surfaces.

This invention relates to chip-type semiconductor light-emitting devices and, more particularly, to a chip-type semiconductor light-emitting device improved in brightness at a center of the radiation surface by the reflector.
Conventionally, there have been known a variety of chip-type semiconductor light-emitting devices using light-emitting diode (LED) elements as light-emitting sources. FIG. 11 and FIG. 12 show one example of such devices. FIG. 11 is a plan view showing a state that an LED element is mounted on a substrate. In FIG. 11, a pair of electrodes 3 and 4 are formed of a conductive material on a surface of the substrate 2.
The substrate 2 is formed, at opposite ends, with semicircular cutouts 2a and 2b on which conductive films, such as plating layers, are formed extending to a backside of the substrate 2 and electrically connected to the pair of electrodes 3 and 4 formed on the surface of the substrate 2. A rectangular pad 3a is formed in one electrode 3 so that an LED element 1 is mounted by die-bonding on the pad 3a. The LED element 1 is electrically connected to the other electrode 4 through wire bonding of a metal wire 5.
An opaque-resin reflector is provided on the substrate 2 mounted with the LED element 1. A translucent resin is filled into an aperture formed in the reflector, thereby forming a chip-type semiconductor light-emitting device. FIG. 12 is a sectional view showing, on a XIIxe2x80x94XII section in FIG. 11, a chip-type semiconductor light-emitting device formed as above.
In FIG. 12, 6 is an opaque-resin reflector having a slant surface 6X that is inclined at an acute angle xcex81 relative to the substrate 2. An aperture 6a is formed encompassed by the slant surface 6X and opening to an outside. The reflector 6 is formed by injection-molding, for example, a white liquid-crystal polymer.
The reflector 6 is rested on the substrate 2 and then an LED element 1 is mounted in the aperture 6a encompassed by the slant surface 6X and penetrating vertically through thereof. Next, a translucent resin 7, such as an epoxy resin, is filled to encapsulate the LED element 1 and metal wire 5 thus forming a chip-type semiconductor light-emitting device 20. The chip-type semiconductor light-emitting device 20 is to be surface-mounted on a printed-circuit board. Electrical connection is to be made between the conductive films formed in the backside of the substrate 2 through the semicircular cutouts 2a and 2b and a circuit pattern on the printed-circuit board.
By forming the slant surface 6X in the reflector 6, the output light of the LED element 1 is reflected upon the slant surface 6X and radiated toward the front of the chip-type semiconductor light-emitting device 20. Due to this, light emission efficiency is improved in the chip-type semiconductor light-emitting device.
In this example, the aperture 6a of the reflector 6 is formed rectangular as viewed from the above.
FIG. 13 and FIG. 14 show another conventional example of a chip-type semiconductor light-emitting device. FIG. 13 is a schematic perspective view showing, by partial projection. FIG. 14 is a sectional view showing a XIVxe2x80x94XIV section in FIG. 13. The same parts as or corresponding elements to those of FIG. 11 and FIG. 12 are denoted by the same difference numerals. In the FIG. 13 example, cutouts are formed in an elongate-hole form at opposite ends of the substrate 2. The elongate-hole cutouts are formed with conductive films, such as plating layers, extending to the backside of the substrate. The pair of electrodes 3 and 4 are respectively connected to the conductive films.
Inside the reflector 6, a slant surface 6Y is provided inclining at an acute angle xcex8 relative to the substrate 2, to thereby form an inverted-conical aperture 6b that is encompassed by the slant surface 6Y and vertically penetrating through the reflector. In the chip-type semiconductor light-emitting device 30 shown in FIG. 13 and FIG. 14, the output light of the LED element 1 is reflected upon the slant surface 6Y toward the front, improving light emission efficiency. Also, in the example of FIG. 13, the aperture 6b of the reflector 6 is formed circular as viewed from the above.
In this manner, the conventional chip-type semiconductor light-emitting device has a reflector having a slant surface vertically penetrating through the reflector so that the output light of the LED element is reflected by the reflector, thereby improving light emission efficiency.
However, in the conventional chip-type semiconductor light-emitting device, because the angle of the reflector slant surface is set at a constant angle, there is a problem that the output-light center brightness cannot be taken high.
Also, the reflector separately manufactured by injection-molding is attached to the substrate mounted with an LED element. Consequently, where there occurs positional deviation in die-bonding an LED onto the substrate, the LED element and the reflector are impossible to realign with each other, resulting in a problem with center-brightness change.
Therefore, it is a primary object of the present invention to provide a novel chip-type semiconductor light-emitting device.
Another object of the invention is to provide a chip-type semiconductor light-emitting device capable of improving radiation center brightness.
Another object of the invention is to provide a chip-type semiconductor light-emitting device capable of reducing change or variation in center brightness even if there is positional deviation of the LED element relative to the substrate.
A chip-type semiconductor light-emitting device according to the present invention comprises: a substrate; a semiconductor light-emitting element mounted on the substrate; and a reflector having an aperture having a slant surface in an inner wall thereof and to be rested on the substrate in a manner encompassing the semiconductor light emitting element by the slant surface, the slant surface including first and second reflection surfaces having respective first and second inclination angles and continuing thickness-wise of the reflector but different from each other, the first and second inclination angles being respectively set to reflect light from the semiconductor light-emitting element toward the immediate upward at thickness-wise center regions of the first and second reflection surfaces of the reflector.
The output light from the light-emission center of the semiconductor light-emitting element is reflected by the first reflection surface. At this time, the light reflected at a center region of the first reflection surface travels toward the immediately upward with respect to the surface of the substrate. Similarly, the output light from the light emitting element is reflected by the second surface. The reflection light at a center region of the second reflection surface travels toward immediate upward with respect to the surface of the substrate. Accordingly, the reflection light in the same direction due to a plurality of reflection surface is collected together. This increases the quantity of reflection light travelling toward a center axis of the radiation surface and improves center brightness. Also, because reflection toward the immediate upward can be made at the respective center regions of the first and second reflection surfaces, even if there occur positional deviation upon mounting the semiconductor light emitting element on the substrate, reflection light toward the immediate upward is available in the upper or lower areas of the first reflection surface and/or the second reflection surface with respect to the center area thereof, thereby reducing the variation in center brightness.
Incidentally, in a preferred embodiment, the first reflection surface is formed at a thickness-wise lower side of the reflector and the second reflection surface is formed at a thickness-wise upper side, the second inclination angle being greater as compared to the first inclination angle. If the first inclination angle be set greater than the second inclination angle, no output light reaches the area of the second reflection surface close to the first reflection surface from the semiconductor light emitting element due to blockage by the first reflection surface. This reduces the quantity of the output light reflected by the second reflection surface. Contrary to this, by setting the second inclination angle greater than the first reflection angle, there will not occur such partial shield in the output light hence further improving light emission efficiency.
Incidentally, a shape of the aperture as viewed from above can be selected as an arbitrary form, such as a circular form, a rectangular form or an oval form.
The above described objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


A software-based computer method for limiting the lifetime of an electronic credit card transaction that makes the transmitted credit card information useless when a configurable time limit expires. The method is designed to provide protection for electronic transactions that require use of an identifying key such as a credit card number, with or without an additional unique identifier comprising a sequence of alphanumeric values, such as a PIN, for the purpose of initiating a transaction. The method provides protection by the addition of a transaction-initiated date/time stamp which is included as part of the transmitted transaction information and provides the basis for limiting the amount of time the transaction is valid.

Credit cards are commonly used over the public Internet to purchase goods and services. The information required to initiate a transaction consists of a credit card number, an expiration date for the card, a cardholder's billing address and the card holder's name as shown on the card. All of the information made available to support a credit card transaction may become known to a third party who is then in a position to use the same without the consent or knowledge of the cardholder. The fact that the credit card information can be re-used by a third party without the consent or knowledge of the card holder creates a problem for both the cardholder and the institution that issued the credit card.


A hub-bearing assembly for agricultural use having a rolling bearing, a housing, a closing cap and an axial retention feature. The roller bearing includes an outer ring, at least one inner ring, at least a row of rolling bodies and a sealing device. The housing includes an almost annular cylindrical shape, the housing at one end forming a radial flange, containing the rolling bearing and being in direct contact with the bearing outer ring. The closing cap is assembled on the housing at the opposite end with respect to the end, where the housing forms the flange. It is noted that the cap is cup shaped. The axial retention feature is located along an external surface of the outer ring. The retention feature is located opposed to the axial sliding of the outer ring with respect to the housing.

In agriculture, devices are known in the shape of either smooth or toothed disc. By rotating due to land contact, such discs are able to dig groove on the land, to execute operations like ploughing, seeding, fertilizer spreading and other similar operations.
Usually, such discs are assembled side by side to correspondent shafts, which embossed protrude from the frame of an agricultural machine. Each disc is rotatable assembled, by means of a hub-bearing assembly, which comprises one or two radially inner rings, stationary, the inner rings steadily fixed to a central shaft, which embossed protrudes from an arm of the frame of an agricultural machine. The hub-bearing assembly also comprises a radially outer ring and a double row of balls, which is interposed between the outer ring and the inner rings. The inner rings, and consequently the bearing, are axially locked against the shoulder of the shaft, due to the tightening of a sleeve or a nut, which is screwed at a free end of the shaft. The outer ring can be contained in a housing, which is in one piece with an external radial flange, for assembling the disc. The housing is covered by a closing cap, which can be press-fit into the housing or screwed on it.
The housing, surrounding the outer ring, is normally made of plastic material and can be co-molded on the outer ring, according to a known technology. After co-molding, the cooling of the plastic material causes a dimensional reduction of the housing and, consequently, a radial interference between the radially inner surface of the housing and the radially external surface of the bearing outer ring.
Such hub-bearing assemblies are well known and have been disclosed in several documents, for example U.S. Pat. No. 3,083,972 A and US 2007/074879 A1.
Unfortunately, the radial interference between housing and outer ring is not enough, to let the assembly be suitable for all prescribed applications. At the same time, solutions aimed to improve the grip between metal and plastic (for example, creating a plurality of grooves all along the ring external surface, inside which the liquid plastic of the housing to be co-molded can flow) are part of non-conventional hub-bearing assemblies, which are more expensive.
Example of retention means to improve the grip between housing and ring are shown in GB 1520341 A, U.S. Pat. No. 6,106,156 A, DE 10347361 A, DE 19713333 A1, DE 19860345 A1, US 2005/105840 A1.


At least one sidewall panel of a pizza box blank is provided with at least one removable punch-out section. For disposing of the assembled (inter-folded) pizza box, the punch-out section is removed, and the assembled box is folded in half to diminish a major dimension thereof. Additionally, a series of weakening lines are provided which allow the punched out sidewall panel to deform inwardly, into the assembled box, for further facilitating easy folding for disposal in a trash receptacle.

Take-out pizza is typically contained in a cardboard box. The pizza box is often constructed of a single, flat piece ("blank") of cardboard that has been pre-stressed along a matrix of fold lines, and is assembled (inter-folded) into a box structure by folding various panels, sidewalls, flaps and tabs of the blank along these fold lines and inserting the tabs into slits made in the cardboard. The resulting box (container) is relatively long and wide (major dimensions), nominally square (on the order of twelve to twenty inches in each of the length and width dimensions) to contain a round pizza, and has a relatively shallow depth (minor dimension, on the order of one and three-quarter inches). The resulting container structure is very rigid so that it can maintain its box structure shape, so that it can be carried by its edges, and so that multiple containers (pizza boxes) can be stacked one atop the other without deformation.
The sidewall panels of the box are initially somewhat flexible, depending upon the (paper) stock used for the box blank. However, when the blank is inter-folded, or assembled into a box structure, the sidewall panels, especially the rear sidewall panel connecting the top "lid" panel to the bottom "tray" panel, become rather rigid structural members. In essence, the sidewalls of the container form "trusses".
An assembled pizza box is relatively large (e.g., 12-20 inches) when compared with an opening in a trash receptacle (container). Hence, it is difficult to fit the assembled pizza box into the trash receptacle, since the "major" dimensions (length and width) of the box usually exceed the size of the opening in the trash receptacle. And, after the pizza box is deposited into the trash receptacle, it usually takes up an inordinate amount of space therein, seriously adversely affecting the remaining space in the trash receptacle for other garbage.
One way of making a pizza box fit more easily into a trash receptacle is to fold the box at least once (lengthwise or widthwise) so that it is only half of its original, assembled size (i.e., one of the "major" dimensions is reduced by half). However, the inherent structural rigidity of the assembled (inter-folded) pizza box makes it rather difficult to fold in half. This is especially true when the box is formed from a corrugated cardboard blank.
In order to fold the assembled box in half, it is usually necessary to grasp opposing edges of the box and fold the box about a stationary point, such as one's knee, the edge of a table, or the like. This is a terrible nuisance, especially when the box has become contaminated with excess foodstuff, such as oil, from the pizza.
It is also possible to cut the assembled pizza box into smaller pieces, so that each piece fits easily into the opening of a trash receptacle. This is better than folding in that many small pieces can be formed, but is worse than folding in that excess foodstuff within the box is no longer contained.
What is needed is a pizza box that is easy to fold or otherwise deform into a smaller size (or into several smaller size pieces) for easy disposal thereof in a trash receptacle having an opening smaller than the length or width dimension of the assembled pizza box.
U.S. Pat. No. 4,984,734 discloses a stackable articulated carton tray for flat food products, especially pizza pies. The patent discloses "panels", "fold edges", "sidewalls" and interlocking "flaps".
U.S. Pat. No. 4,979,667 discloses a pizza "tray" and "lid", prepared from a single "blank" of "paperboard" or the like.
U.S. Pat. No. 4,960,238 discloses a 2-Piece Pizza Box with cut-out corners. The cut-out corner sections provide for inward flexibility of the tray sidewalls when a cover panel is fitted over the tray panel.
U.S. Pat. No. 4,944,452 discloses a multiple pizza container formed of a single double-sided corrugated blank including a matrix of "score" and "fold" lines to enable interfolding of the blank.
U.S. Pat. Nos. 4,567,341, 4,476,989, 4,360,107, 4,058,214, 3,650,383, Des. 292,176 and Des. 274,889 disclose additional pizza boxes and containers.
These references are cited, generally, as indicative of the state of the art in pizza boxes, and for establishing a lexicon of commonly-used terminology. None of the above-referenced pizza boxes and containers appear to provide means for deforming or otherwise altering an assembled box having relatively large dimensions for easy disposal in a trash receptacle having a relatively smaller opening.

Foldable, easily-disposable pizza box, and methods of making and using same


A photovoltaic module frame, a photovoltaic support assembly and a photovoltaic module are provided. The photovoltaic module frame includes an installation part. The top of the installation part is provided with at least one meshing structure for meshing with the bottom of a press block. By providing a meshing structure on the top of the installation part, the meshing structure is meshed with the bottom of the press block to increase the contact area between the installation part of the photovoltaic module frame and the bottom of the press block, thereby increasing the meshing force, and preventing the photovoltaic module frame from separating from the press block especially when the wind is strong.

With the rapid development of solar photovoltaic cell and module technologies, the demand for high-efficiency photovoltaic modules is becoming more and more urgent. Increasing the cell size and expanding the module have become the market trends. The increase in module size is becoming more and more challenging for the installation of modules and the mechanical performance of resistance to extreme weather such as strong wind and heavy snow, therefore the safety risk during the operation of the power station may increase accordingly. Correspondingly, there is higher demand for the bearing capacity of the module frame.
Referring to FIG. 1, in the related art, the horizontal structure of a top of an installation part 11′ of a photovoltaic module frame 1′ is relatively short, with a downward arc structure having a certain angle, such a structure has a smooth surface and has a certain radian downward. The contact area between the press block 2′ and the top of the photovoltaic module frame 1′ is small, and the meshing force therebetween is not sufficient. When the wind is strong, the module photovoltaic module frame 1′ is easily separated from the press block 2′, causing the module to fall off and get damaged, and thereby bringing potential risks.

Photovoltaic module frame, photovoltaic support assembly and photovoltaic module


A firearm with dual-acting safety mechanism in one embodiment includes a slide movably carried by a frame, hammer, sear operable to hold the hammer in and release it from a cocked position, and firing mechanism including a trigger and trigger bar which collectively operate to actuate the sear to release the hammer. The safety mechanism includes right and left actuator levers coupled together and cooperating with a safety rocker. The safety rocker is operably interfaced with the trigger bar and pivotably movable between two positions. Moving either actuation lever to activate the safety mechanism rotates the safety rocker which simultaneously both blocks the trigger bar from movement and displaces the trigger bar to disengage the sear which can no longer be actuated via a trigger pull. In one embodiment, the safety mechanism is further operable to lock the slide in the closed breech position when the safety is activated.

The present invention generally relates to firearms, and more particularly to user-actuated safety mechanisms for firearms.
Manual safeties for firearms are intended to reduce the chance of accidental discharge by disabling fire control components in the event a user fails to exercise proper firearm handling procedures. This can be achieved in numerous ways to block various components of the trigger-actuated firing mechanism. Many safeties act to disable only a single aspect of the firing mechanism.
Improvements in safeties are desired.


An internal voltage generating circuit of a semiconductor device includes a first voltage driver configured to pull up an internal voltage terminal during a period where a level of the internal voltage terminal is lower than a target level, and a second voltage driver configured to pull up the internal voltage terminal during a predefined time in each period corresponding to a frequency of an external clock.

The present invention relates to a semiconductor device, and more particularly, to an internal voltage generating circuit for generating an internal voltage that is maintained at a stable voltage level, regardless of a frequency variation of an external clock.
Most semiconductor devices, e.g., dynamic random access memory (DRAM), include an internal voltage generating circuit inside a chip to generate internal voltages necessary for operations of internal circuits. The internal voltage generating circuit generates internal voltages of various levels by using an external power supply voltage (VDD) and a ground voltage (VSS).
The generation of the internal voltages includes an operation of generating a reference voltage and an operation of charge-pumping or down-converting the generated reference voltage.
Examples of a representative internal voltage generated using the charge pumping operation include a high voltage (VPP) and a back bias voltage (VBB), and examples of a representative internal voltage generated using the down-converting operation include a core voltage (VCORE).
The high voltage (VPP) is a voltage higher than an external power supply voltage (VDD). Upon access to a memory cell, the high voltage (VPP) is applied to a word line connected to a gate of a cell transistor in order to compensate loss of cell data, which is caused by a threshold voltage (Vth) of the cell transistor.
The back bias voltage (VBB) is a voltage lower than an external ground voltage (VSS). The back bias voltage (VBB) reduces the variation of the threshold voltage (Vth) of the cell transistor, which is caused by a body effect, thereby improving the operation stability of the cell transistor and reducing a channel leakage current generated at the cell transistor.
The core voltage (VCORE) is a voltage lower than an external power supply voltage (VDD) and higher than a ground voltage (VSS). The core voltage (VCORE) reduces power that is necessary to maintain a voltage level of data stored in a memory cell, and is used for stable operation of the cell transistor.
The internal voltage generating circuit generating the internal voltages (VPP, VBB and VCORE) is designed to operate with a predetermined deviation value within an operating voltage region and an operating temperature range of the semiconductor memory device.
FIG. 1 is a block diagram of a conventional internal voltage generating circuit.
Referring to FIG. 1, the conventional internal voltage generating circuit for generating an internal voltage VINT includes a bandgap reference voltage generator 140, an internal voltage detector 100, and an internal voltage driver 120. The bandgap reference voltage generator 140 generates a reference voltage VREF_INT that is constantly maintained at a target level, regardless of variation of process, voltage and temperature (PVT) of the semiconductor device. The internal voltage detector 100 detects a level of an internal voltage (VINT) terminal, based on the target level of the reference voltage VREF_INT, to generate an internal voltage detection signal VINT_DET. The internal voltage driver 120 pulls up the internal voltage terminal in response to the internal voltage detection signal VINT_DET.
The internal voltage VINT generated through the above-described processes is input to an internal circuit 160 and enables the internal circuit 160 to perform its internal operation.
Specifically, the internal voltage detector 100 activates the internal voltage detection signal VINT_DET when the level of the internal voltage terminal is lower than the reference voltage VREF_INT that is constantly maintained at the target level, regardless of PVT variation. On the other hand, the internal voltage detector 100 deactivates the internal voltage detection signal VINT_DET when the level of the internal voltage terminal is higher than the reference voltage VREF_INT.
The internal voltage driver 120 pulls up the internal voltage terminal with a predefined drivability when the internal voltage detection signal VINT_DET is in the activated state.
In summary, the internal voltage detector 100 and the internal voltage driver 120 detect the phenomenon that the level of the internal voltage terminal is lowered due to the operation of the internal circuit 160, and make the internal voltage terminal have the target level of the reference voltage VREF_INT.
With respect to the internal voltage terminal, the internal circuit 160 is a current load that is variously variable. That is, the internal circuit 160 may vary the level of the internal voltage VINT when its internal operation is performed according to the operation mode of the semiconductor device.
For example, the internal circuit 160 uses a large amount of the internal voltage VINT in the read/write operation, that is, when the data input/output operations are performed. Thus, reduction in the level of the internal voltage terminal is relatively large. On the other hand, the internal circuit 160 hardly uses the internal voltage VINT in the power-down mode where the data input/output operations are not performed. Thus, reduction in the level of the internal voltage VINT is relatively small.
Therefore, the level of the internal voltage terminal repetitively rises and falls above and below the target level of the reference voltage VREF_INT according to the operations of the internal voltage detector 100, the internal voltage driver 120, and the internal circuit 160.
When the level variation width of the internal voltage terminal, centering on the level of the reference voltage VREF_INT, does not exceed the predefined level width, the operation of the semiconductor device may not be greatly affected.
However, when the level variation width of the internal voltage terminal, centering on the level of the reference voltage VREF_INT, exceeds the predefined level width, the operation of the semiconductor device may not operate normally.
To solve this problem, the level variation width of the internal voltage terminal should be controlled such that it falls within the predefined level width.
To this end, the operating speed of the internal voltage detector 100 has been increased relatively faster. That is, the internal voltage detector 100 detects the level of the internal voltage terminal more frequently during the same time. In this way, the level variation width of the reference voltage terminal, centering on the level of the reference voltage VREF_INT, can fall within the predefined level width.
For example, if the internal voltage detector 100 detects the level variation of the internal voltage terminal relatively frequently, it can detect the level of the level of the internal voltage terminal relatively fast even when it rapidly falls, and operate the internal voltage driver 120. It can prevent the level of the internal voltage terminal from further falling at the moment when the internal voltage driver 120 starts to operate, and it increases the level of the internal voltage terminal. Therefore, it is possible to reduce the level falling width of the internal voltage terminal, centering on the level of the reference voltage VREF_INT.
Likewise, if the internal voltage detector 100 detects the level variation of the internal voltage INT terminal relatively frequently, the rapid rise of the level of the internal voltage terminal due to the operation of the internal voltage driver 120 can be detected relatively fast. Therefore, the operation of the internal voltage driver 120 can be stopped. At the moment when the operation of the internal voltage driver 120 is stopped, the level of the internal voltage terminal does not further rise and immediately falls. Consequently, the level rise width of the internal voltage terminal, centering on the reference voltage VREF_INT, can be reduced.
However, a predetermined amount of current is consumed whenever the internal voltage detector 100 detects the level of the internal voltage terminal. Thus, an amount of current relatively increases when the internal voltage detector 100 detects the level of the internal voltage terminal relatively frequently. If the operating speed of the internal voltage detector 100 increases, an amount of current consumed in the semiconductor device will considerably increase.
In addition, despite the fact that the case where the level of the internal voltage terminal slowly changes occurs more often than the case where the level of the internal voltage terminal rapidly changes, it is unreasonable to increase the operating speed of the internal voltage detector 100 in order for preparing for the case where the level of the internal voltage terminal rapidly changes.
This means that increasing the operating speed of the internal voltage detector 100 is allowed to some extent. Increasing the operating speed of the internal voltage detector 100 in order to prevent the rapid level variation of the internal voltage terminal has the tradeoff relationship with increase in an amount of current consumed in the internal voltage detector 100. To solve the two problems at a time, the designer must find the level variation width of the internal voltage terminal having a relatively low error probability through various test operations, and design the semiconductor device such that it performs the operation of properly maintaining the operating speed of the internal voltage detector 100 so that the semiconductor device can operate normally without greatly increasing the current consumption.
Meanwhile, the level of the power supply voltage VDD supplied to the semiconductor device is gradually lowered and the operating speed of the semiconductor device is gradually increasing.
The fast operating speed of the semiconductor device means that the frequency of the external clock applied to the semiconductor device is high. That is, as the frequency of the external clock is increasing, the semiconductor device can operate at higher speed.
Also, the high-speed operation of the semiconductor device as the frequency of the external clock increases means that the internal circuit 160 of the semiconductor device will use the internal voltage VINT much more. That is, it means that the level of the internal voltage terminal may change more rapidly.
Due to the increased frequency of the external clock, the level of the internal voltage terminal changes more rapidly. Even though the internal voltage detector 100 and the internal voltage driver 120 operate at the typical speed, it is impossible to prevent the phenomenon that the level of the internal voltage terminal rises and falls centering on the level of the internal voltage terminal.
That is, it is impossible to prevent the increase in the level variation width of the internal voltage terminal, which is caused by the increased frequency of the external clock, at the operating speed of the internal voltage detector 100 where its error probability is low and its current consumption is not greatly increased. Therefore, the semiconductor device cannot operate normally, increasing the error probability.
Increasing the operating speed of the internal voltage detector 100 without any preparation will cause the above-described problem that an amount of current consumed in the semiconductor device is increased too much.
Therefore, whenever the operating speed of the semiconductor device changes, that is, when the frequency of the external clock applied to the semiconductor device changes, the designer must again find the level variation width of the internal voltage terminal having a relatively low error probability through test operations, and design the semiconductor device such that it performs the operation of properly maintaining the operating speed of the internal voltage detector 100 so that the semiconductor device can operate normally without greatly increasing the current consumption.

Internal voltage generating circuit of semiconductor device


A multilayer ceramic capacitor includes a ceramic body, and external electrodes on opposite side surfaces of the ceramic body. The ceramic body includes an inner layer portion including a plurality of ceramic layers, and first and second internal electrodes each arranged at interfaces between the ceramic layers defining the inner layer portion, and also includes outer layer portions arranged on an upper surface and a lower surface of the inner layer portion. The ceramic layers defining the inner layer portion include as a main component a perovskite-type compound containing Ba and Ti. The amount of Mg contained in the ceramic layers defining the inner layer portion preferably is 0 to about 0.4 part by mole per 100 parts by mole of Ti, for example. The thickness of the ceramic layers defining the inner layer portion preferably is not more than about 0.55 μm, for example.

1. Field of the Invention
The present invention relates to a multilayer ceramic capacitor.
2. Description of the Related Art
In recent years, with the decreasing size and increasing performance of electronic components, a size reduction and an increased capacitance are required in multilayer ceramic capacitors. Such a multilayer ceramic capacitor includes, for example, a ceramic body with a rectangular parallelepiped shape, in which ceramic layers defining an inner layer portion and internal electrodes are laminated alternately, and ceramic layers defining an outer layer portion are arranged on upper and lower surfaces of the laminated body, and also includes external electrodes formed on opposite end surfaces of the ceramic body.
In order to achieve a size reduction and an increased capacity in the multilayer ceramic capacitor, it is necessary to reduce the thickness and increase the lamination density of the ceramic layers defining the inner layer portion (dielectric ceramic layers) and the internal electrodes as much as possible. However, in a multilayer ceramic capacitor in which the dielectric ceramic layers and the internal electrodes have been reduced in thickness and increased in lamination density, if the thickness of the dielectric ceramic layers is further reduced, the insulation resistance between internal electrodes will decrease, leading to reduced reliability. It has therefore been difficult to achieve a smaller thickness and a higher lamination density while ensuring reliability.
Japanese Patent No. 3,334,607 discloses a dielectric ceramic composition for forming a dielectric ceramic layer, for use in a multilayer ceramic capacitor that takes into account the insulation resistance of a dielectric ceramic layer having a reduced thickness between internal electrodes. In a ceramic body in which internal electrodes and dielectric ceramic layers containing barium titanate as a main component are laminated alternately, the dielectric ceramic composition has the composition represented by the formula: {BaO} mTiO2+αR2O3+βBaZrO3+γMgO+gMnO, where R2O3 is at least one selected from Eu2O3, Gd2O3, Tb2O3, Dy2O3, Ho2O3, Er2O3, Tm2O3, and Yb2O3;
and α, β, γ, and g each represent a molar ratio, and are in the following ranges: 0.001≦α≦0.06; 0.005≦β≦0.06; 0.001<γ≦0.12; 0.001<g≦0.12; γ+g≦0.13; and 1.000<m≦1.035.
However, with the dielectric ceramic composition forming the dielectric ceramic layers in the multilayer ceramic capacitor described in Japanese Patent No. 3,334,607, the reliability significantly decreases in the case of a multilayer ceramic capacitor including regions of dielectric ceramic layers with a reduced thickness (not more than 0.55 μm).


A decoding apparatus and a decoding method are capable of minimizing degradation of the quality of images and sounds when a synchronous signal error occurs. The decoding apparatus includes a frame counter for receiving a bit stream, a synchronous pattern detector, a data error check unit, a synchronous detector, and a frame error determination unit. A synchronous detection error occurrence signal produced by the synchronous detector is not output to an external error processing circuit but is directly transmitted to the frame error determination unit. Even when the timing of an output synchronous pattern detection signal from the synchronous pattern detector and the timing of an output frame position signal from the frame counter do not match each other and a frame synchronous abnormality occurs, if the data itself is normal then decoding processing is executed without performing any error correction processing.

1. Field of the Invention
The present invention relates to a decoding apparatus and a decoding method and, more particularly, to a decoding apparatus which functions as a bit stream decoding means in transmission and storage systems for compressed and non-compressed signals of sounds and images.
2. Description of the Prior Art
One example of a conventional decoding apparatus of this sort is shown in a block diagram of FIG. 1. As shown in FIG. 1, this conventional apparatus comprises a frame counter 31 for receiving a bit stream 101, a synchronous pattern detector 32, a data error check unit 33, a synchronous detector 34, and a frame error determination unit 35. FIG. 2 shows the structure of a unit frame of a bit stream to be decoded by this decoding apparatus. This unit frame consists of a synchronous pattern 201, data 202 and 204, and an error check pattern 203. The synchronous pattern 201 functions as a synchronous position detection pattern for maintaining frame synchronization. The data 202 and 204 are formed by compressing image data or sound data. The error check pattern 203 is used to check whether image data or sound data present in that unit frame has an error. Referring to FIG. 2, the data 204 of an immediately preceding unit frame connects to the synchronous pattern 201 of the next unit frame. In bit stream transmission, data encapsulated in these unit frames is continuously transmitted.
Referring to FIG. 1, the bit stream 101 with the frame structure shown in FIG. 2 is input at an input terminal 36 to the frame counter 31, the synchronous pattern detector 32, and the data error check unit 33. The synchronous pattern detector 32 detects the synchronous pattern 201 arranged at the head of the unit frame and outputs a synchronous pattern detection signal 104 to the frame counter 31 and the synchronous detector 34. Upon receiving this synchronous pattern detection signal 104, the frame counter 31 starts counting and performs the count operation for each unit frame of the input bit stream from the input terminal 36. Also, the frame counter 31 outputs a frame position signal 102 to the synchronous detector 34. If the timing of the frame position signal 102 transmitted to the synchronous detector 34 matches the timing of the synchronous pattern 201, which is contained in the synchronous pattern detection signal 104 and arranged at the head of the next unit frame, this indicates a normal synchronous state in which the synchronous pattern 201 in the unit frame is present in a normal synchronous position.
The synchronous detector 34 receives the frame position signal 102 supplied from the frame counter 31 and the synchronous pattern 201 in the next frame contained in the synchronous pattern detection signal 104 supplied from the synchronous pattern detector 32. If the timings of the frame position signal 102 and the synchronous pattern 201 in the next unit frame match each other, the synchronous detector 34 outputs a predetermined synchronous detection signal 103 to the frame counter 31 and the data error check unit 33. The frame counter 31 is initialized by this synchronous detection signal 103. Thereafter, as long as normal frames are continuously input, a series of synchronous detection operations as described above are repeatedly executed. If the timings of the frame position signal 102 and the synchronous pattern 201 in the next unit frame do not match each other, the synchronous detector 34 determines that some abnormality has occurred in the detection of the synchronous pattern, and outputs a synchronous detection error occurrence signal 106 to an external error processing circuit (not shown). The data error check unit 33 performs error check detection by referring to the error check pattern 203 in the unit frame of the bit stream. If an error is detected, the data error check unit 33 outputs a data error occurrence signal 105 to the frame error determination unit 35. When receiving this data error occurrence signal 105, the frame error determination unit 35 determines that an abnormality has occurred in the data in the frame, and outputs a frame error occurrence signal 107 to the error processing circuit (not shown).
In a normal decoding process, irrespective of whether the synchronous detection error occurrence signal 106 or the frame error occurrence signal 107 is output, it is determined that an abnormality has occurred in the data in the corresponding frame, and error processing is performed.
As a method of avoiding synchronous error detection for a bit stream input, a conventional technique proposed in Japanese Unexamined Patent Publication No. 60-246065 will be described next. In the method described in this proposal, if the synchronous signal has an error, another error detecting means locates and corrects the error. The gist of the contents of this conventional correction operation is as follows.
That is, an input synchronous signal from an input terminal is applied to a shift register by clocks. The shift register outputs the signal to a predetermined synchronous pattern coincidence circuit. If the synchronous signal has no error and exists in a correct position, an output terminal outputs a signal indicating that the synchronous signal is detected. Upon receiving the signal, a CRC arithmetic circuit is reset. Also, if data has no error, a CRC check terminal outputs a desired signal. An error flag signal is previously attached to the synchronous signal and applied from the input terminal to the shift register. If an error exists, correction processing is performed using the output from a circuit which is counting a signal in which the corresponding synchronous signal is detected. Therefore, if the synchronous signal pattern is entirely correct, synchronous detection can be performed only by using this pattern. If an error pattern with an error flag is present in a synchronous signal, detection is performed by taking account of the position from a CRC code. This prevents erroneous detection of a synchronous signal.
In the conventional decoding apparatus shown in FIG. 1, a synchronous signal is usually added to the head of a unit frame of a transmission bit stream, and a general approach is to allow the synchronous detector of the decoding apparatus to establish synchronization of that frame. However, if an error is generated in the synchronous signal due to, e.g., transmission, a synchronous error is produced by this error. Consequently, no frame decoding is performed, and error correction processing such as interpolation or muting is performed instead. This unavoidably degrades the quality of images and sounds.
Also, the following is a drawback of the method proposed in Japanese Unexamined Patent Publication No. 60-246065 in which in order to prevent synchronous error detection, an error flag is added to a synchronous signal, and the synchronous signal is corrected on the basis of an error position found by the error flag to thereby avoid synchronous error detection. That is, in the processing of particularly signal compression systems such as MPEG, the compression rate is improved by, e.g., decreasing the rate of a transmission system or reducing the storage capacity of a storage system. Consequently, it is practically very difficult to add redundant error detection data, which can locate an error position, to a transmission bit stream. Accordingly, one can only use a means of adding data capable of detecting only occurrence of an error. Under these circumstances, it is impossible to satisfactorily correct the synchronous signal position even with the application of the technique proposed in Japanese Unexamined Patent Publication No. 60-246065.

Bitstream decoding apparatus with reduced error correction processing and decoding method


A touch panel includes a light-transmissible, piezoelectric substrate having a first surface and a second surface opposite to the first surface of the piezoelectric substrate, a first light transmissible, resistor layer provided on the first surface of the substrate, and a second light transmissible, resistor layer provided on the second surface of the substrate. A portion of the piezoelectric substrate, upon being pressed, has an electric resistance locally decreasing. The touch panel, even having a simple construction, can avoid reflections of external light and suppress a Newton's ring.

As electronic apparatuses have had multi-functions, the apparatuses employ light-transmissible touch panels mounted on screens of displays, such as liquid crystal displays, of the apparatuses. A touch panel is simply manipulated by a user to allow him/her to view and select a character, an icon, and a symbol displayed on the screen with a finger or a dedicated pen for activating desired functions.
A conventional touch panel disclosed in Japanese Patent Laid-Open Publication No. 7-169367 will be explained. FIG. 5 is a cross sectional view of the conventional touch panel. A light transmissible upper resistor layer 3 made of, for example, indium tin oxide is provided on the lower surface of an upper substrate 1 made of light transmissible film. Similarly, a light transmissible lower resistor layer 4 made of, for example, indium tin oxide is provided on the upper surface of a lower substrate 2 made of light transmissible film. Plural dot spacers 5 made of insulating resin are provided at equal intervals on the upper surface of the lower resistor layer 4. A pair of upper electrodes (not shown) are provided on both ends of the upper resistor layer 3 while a pair of lower electrodes (not shown) are provided on both ends of the lower resistor layer 4 and extend in a direction orthogonal to the upper electrodes. The upper substrate 1 is bonded at its outer edge to the upper end of a frame-shaped spacer 6 by an adhesive layer (not shown) provided on the uppermost surface of the spacer 6. The lower substrate 2 has an outer rim bonded to the lower end of the spacer 6 by an adhesive layer (not shown) provided on the lower surface of the spacer 6. This arrangement allows the upper resistor layer 3 to face the lower resistor layer 4 at a predetermined space 7 between the layers.
The touch panel is mounted to a screen of a display, such as a liquid crystal display, and the upper and lower electrodes are connected to a control circuit (not shown) in an electronic apparatus.
A user presses the upper substrate 1 with a finger or a touch pen while viewing the screen of the display through the touch panel. The upper substrate 1 accordingly deflects and causes a pressed portion of the upper resistor layer 3 to contact the lower resistor layer 4. The control circuit supplies voltages to the upper and lower electrodes and measures a voltage ratio between the electrodes so as to determine the position of the pressed portion. The control circuit activates various functions of the electronic apparatus circuit according to the detected position.
The conventional touch panel is however constructed with a number of components, such as the upper substrate 1, the upper resistor layer 3, the space 7, the lower resistor layer 4, and the lower substrate 2. These components reflect external light at upper and lower surfaces of the components, thus reducing transparency. This disturbs the user's view of the display through the touch panel.
The space 7 may generate an optical interference pattern, such as a Newton's ring. The Newton's ring may be reduced by filling the space 7 with silicone oil or the like, however, this process increases the overall number of processes for manufacturing the touch panel, and thus makes the touch panel expensive.

Touch panel and input device including the same


Speech recognition with a speaker-independent speech recognition method is possible for voice signals newly added by a user using the computer unit. Imaging of the voice signal onto stored phoneme feature vectors is implemented for each voice signal to be newly incorporated. A number of possibilities of imaging are compared to one another and the best phoneme representation of the imaging is employed as phoneme presentation for the new word. The voice signal is then stored in a user memory with the phoneme presentation.

The present invention is generally related to the field of speech recognition. Two fundamentally different approaches for recognizing spoken language have been previously known in the field of speech recognition. A first principle is based on speaker independent speech recognition. A vocabulary composed exclusively of fabricationally defined individual words is thereby employed in the speech recognition. A computer unit for speech recognition that is based on this principle as well as the corresponding method for speaker-independent speech recognition are generally known from, for example, G. Ruske, Automatische Spracherkennung, Oldenbourg Verlag, 2nd ed., ISBN 3-48622794-7, pp. 172-195, 1992. This approach is based, for example, on a phoneme recognition, combined with a hidden markov modeling. First, feature vectors are derived from a digitalized voice signal dictated by a user. These feature vectors continue the information of the voice signal that is important for the speech recognition. The identified feature vectors are subsequently compared to prototype feature vectors typical of the phoneme segments. These prototype feature vectors may be stored, for example, in ROM (Read-Only-Memory) provided for this purpose.
Since only one memory location for the phonetic presentation of this word is provided for each word of the vocabulary to be recognized, the total memory requirement for the speaker-independent speech recognition is mainly defined by the memory capacity of the ROM. The results of the aforementioned comparison operations are then combined with one another in a search to determine the spoken word with highest probability from the predetermined vocabulary. In this approach, the vocabulary must be stored with the prototype feature vectors in the form of phonemes of the respective language. Due to the nature of speaker-independent speech recognition based on a phoneme recognition, the recognition of a user-defined part of the vocabulary can only be realized given the pre-condition of the availability of a phonetic notation of each word to be incorporated into the vocabulary that is input by the users.
For this reason, this approach harbors the disadvantage that an additional outlay is established for the user in the phonetic presentation of each user-defined part of the vocabulary. This also leads to ergonomic disadvantages of this approach.
Further, the considerable costs of an additionally required human-machined interface in the form of a keyboard is considered a substantial disadvantage of this approach. Due to the necessity that the user himself must implement the division of the respective new work into phonemes, this approach is also very susceptible to error.
A second approach is based on speaker-dependent speech recognition. This approach is based on a whole-word comparison between a dictated, digitalized voice signal and speech seminars (templates) dictated during a training phase and stored for speaker-dependent speech recognition. One means for the implementation of speaker-dependent speech recognition, as well as an example of this approach, is known from K. Zutnkler, Spracherkennung mit Hidden-Markov Modellen unter Nutzung von unterscheidungsrelevanten Markmalen, Dissertation Technical University Munchen, pp. 22-25, 1991.
A considerable disadvantage of this approach may be seen in the necessity of static storage of the stored speech samples (templates). A training phase is required to be repeated over and over again at the beginning of each "speech recognition session" that cannot be imputed to a user. The requirement for static RAM memory space caused as a result thereof is proportional to the plurality of stored templates per vocabulary word, to the plurality of user-defined vocabulary words, and to the plurality of users for whom the speaker-dependent speech recognition must be capable of being operated at the same time. Beginning with a certain value combination for the aforementioned parameters, not only does the memory capacity of the static memory become greater than given a means with speaker-independent speech recognition, but an increase in the dissipated power that impedes power-saving operation is additionally caused due to the static storing.
A further disadvantage of this approach may be seen in the considerable manufacturing costs that, in particular, are incurred because of the unfavorable area relationships of a static RAM memory to a ROM memory.
It is also known from an article entitled "Product Overview--Advance Information, DVC Advanced Voice Command Processor," in DSP Communications, Inc., Cupertino, Calif., 1995, to implement the algorithms for speaker-independent speech recognition and for speaker dependent speech recognition on a plurality of chips. This known computer unit comprises a special processor bearing the type designation DVC 306, a micro controller and a plurality of memory chips having a total of up to 16 megabits of S-RAM capacity.
This known computer unit for speech recognition has a number of considerable disadvantages. Due to the employment of both the algorithms for speaker-independent speech recognition as well as the algorithms for speaker-dependent speech recognition, a plurality of algorithms must be implemented in a ROM memory.
Further, the disadvantages of the speaker-dependent algorithms, for example, the high speed for static RAM memory and the substantial costs of manufacturing connected therewith, are still present in this implementation.
What is referred to as a Viterbi algorithm is also known from G. Ruske, Automatische Spracherkennung, Oldenbourg Verlag, 2nd ed., ISBN 3-48622794-7, pp. 172-195, 1992. Also, the method of dynamic programming (FP algorithm) is likewise known from G. Ruske, Automatische Spracherkennung, Oldenbourg Verlag, 2nd ed., ISBN 3-48622794-7, pp. 172-195, 1992.

Computer unit for speech recognition and method for computer-supported imaging of a digitalized voice signal onto phonemes


A speaker includes a casing, a sound emitting portion, a conductive coil received in the casing, and a circuit board. The casing includes a side wall. The sound emitting portion received in the casing includes a diaphragm including a first end fixed to the casing and an opposite second end. The conductive coil includes a front end fixed to the side wall, and a rear end fixedly connected to the second end of the diaphragm. The circuit board includes an audio processing module, a charging module and a controlling module. The audio processing module is configured for receiving an audio signal and controlling the conductive coil to vibrate in response to the received audio signal. The charging module is configured for electrifying the conductive coil using alternating current. The controlling unit is configured for selectively connecting the conductive coil to the audio processing module electrically or to the charging module.

1. Technical Field
The present disclosure relates to speakers, and particularly, to a speaker and a wireless charging system using the same.
2. Description of Related Art
Most portable electronic devices such as cellular phones, or laptop computers, are powered by rechargeable batteries. To charge the batteries, a charger is connected to a connector on the outer shell of the typical portable electronic device.
Repetitious plugging and unplugging of the charger with the connector of the portable electronic device degrades both the charger and the portable electronic device connector. Therefore, a wireless charging system has been proposed.
Because most of these portable electronic devices are also used to listen to music, an external speaker is typically connected to these electronic devices. Thus, both the charger and the speaker need to be provided to charge and to listen to the audio sounds from the electronic devices. This is an inconvenience.
Therefore, what is needed is to provide a speaker and a wireless charging system using the speaker.

Speaker and wireless charging system using same

Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd.


A linear electric field ion mass spectrometer having an evacuated enclosure with means for generating a linear electric field located in the evacuated enclosure and means for injecting a sample material into the linear electric field. A source of pulsed ionizing radiation injects ionizing radiation into the linear electric field to ionize atoms or molecules of the sample material, and timing means determine the time elapsed between ionization of atoms or molecules and arrival of an ion out of the ionized atoms or molecules at a predetermined position.

Mass spectrometers are used extensively in the scientific community to measure and analyze the chemical compositions of substances. In general, a mass spectrometer is made up of a source of ions that are used to ionize neutral atoms or molecules from a solid, liquid or gaseous substance, a mass analyzer that separates the ions in space or time according to their mass or their mass-per-charge ratio, and a detector. Several variations of mass spectrometers are available, such as magnetic sector mass spectrometers, quadrupole mass spectrometers, and time-of-flight mass spectrometers.
All citations to publications contained within this application effectively include those publications herein for all purposes.
The magnetic sector mass spectrometer uses a magnetic field or combined magnetic and electrostatic fields to measure the ion mass-per-charge ratio. In one type of magnetic sector geometry, {see A. O. Nier, A Mass Spectrometer for Isotope and Gas Analysis, Review of Scientific Instruments, Vol. 18, No. 6, June 1947, p. 398; L. Holmlid, Mass Dispersion and Mass Resolution in Crossed Homogeneous Electric and Magnetic Fields: The Wien Velocity Filter as a Mass Spectrometer, International Journal of Mass Spectrometry and Ion Physics, Vol. 17 (1975) p. 403} only one mass-per-charge species is detected at any one time, so the magnetic field strength and, if present, the electric field strength must be varied in order to obtain a mass spectrum comprising multiple mass-per-charge species. Major limitations on this type of mass spectrometer are the high mass of the magnet and the time that is required to scan the entire mass range one mass at a time.
Another type of magnetic sector mass spectrometer creates a monoenergetic beam of ions, which are spatially dispersed according to mass-per-charge ratio, and which are focused onto an imaging plate. While this type of spectrometer can detect multiple mass-per-charge species can be detected simultaneously, the poor spatial resolution it provides limits its use to a narrow mass range.
Quadrupole mass spectrometers utilize a mass filter having dynamic electric fields between four electrodes. These fields are tailored to allow only one mass-per-charge ion to pass through the filter at a time. Major limitations of quadrupole mass spectrometers are the high mass of mass of the required magnet and the time required to scan the entire mass range one mass at a time.
Time-of-flight mass spectrometers (TOFMS) can detect ions over a wide mass range simultaneously {see W. C. Wiley and I. H. McLaren, Time-of-Flight Mass Spectrometer with Improved Resolution, Rev. Sci. Instrum., Vol. 26, No. 12, Dec. 1955, p. 1150. Mass spectra are derived by measuring the times for individual ions to traverse a known distance through an electrostatic field free region. In general, the mass of an ion is derived in TOFMS by measurement or knowledge of the energy, E, of an ion, measurement of the time, t1, that an ion passes a fixed point in space, P1, and measurement of the later time, t2, that the ion passes a second point, P2, in space located a distance, d, from P1. Using a ion beam of known energy-per-charge E/q, the time-of-flight (TOF) of the ion is tTOF=t2−t1, and by the ion speed is v=d/tTOF. Since E=0.5 mv2, the ion mass-per-charge m/q is represented by the following equation:
                              m          q                =                                            2                                            Et                TOF                2                                                    qd              2                                .                            10
The mass-per-charge resolution, commonly referred to as the mass resolving power of a mass spectrometer, is defined as:
                                                        Δ                                                                                m                /                q                                                    m              /              q                                =                                                    Δ                                                                                E                            E                        +                          2                                                              Δ                                                                                t                    TOF                                                                    t                  TOF                                                      +                          2                                                              Δ                                                                                d                                d                                                    ,                    11      where ΔE, ΔtTOF, and Δd are the uncertainties in the knowledge or measurement of the ion's energy, E, time-of-flight, tTOF, and distance of travel, d, respectively, in conventional time-of-flight spectrometers.
In a gated TOFMS in which a narrow bunch of ions is periodically injected into the drift region, uncertainty in tTOF may result, for example, from ambiguity in the exact time that an ion entered the drift region due to the finite time, Δt1, that the gate is "open," i.e. Δt1≈ΔtTOF. The ratio of ΔtTOF/tTOF can be minimized by decreasing ΔtTOF, for example, by decreasing the time the gate is "open." This ratio can also be minimized by increasing tTOF, for example, by increasing the distance, d, that an ion travels in the drift region. Often, a reflectron device is used to increase the distance of travel without increasing the physical size of the drift region.
Uncertainty in the distance of travel, d, can arise if the ion beam has a slight angular divergence so that ions travel slightly different paths, and, therefore, slightly different distances to the detector. The ratio of Δd/d can be minimized by employing a long drift region, a small detector, and a highly collimated ion beam.
The uncertainty in the ion energy, E, may result from the initial spread of energies ΔE of ions emitted from the ion source. Therefore, ions are typically accelerated to an energy E that is much greater than ΔE.
A further limitation of conventional mass spectrometry lies in the fact that the source of ions is a separate component from the time-of-flight section of a spectrometer, and it requires significant resources. First, most ion sources are inherently inefficient, so that few atoms or molecules of a gaseous sample are ionized, thereby requiring a large volume of sample and, in order to maintain a proper vacuum, a large vacuum pumping capacity. Second, the ion source typically generates a continuous ion beam that is gated periodically, creating an inefficient condition in which sample material and electrical energy are wasted during the time the gate is "closed." Third, ions have to be transported from the ion source to the time-of-flight section, requiring, among other things, electrostatic acceleration, steering and focusing. Fourth, typical ion sources introduce a significant spread in energy of the ions so that the ions must be substantially accelerated to minimize the effect of this energy spread on the mass resolving power. Finally, having an ion source separate from the drift region creates an apparatus having large mass and volume.
Still another problem with conventional time-of-flight mass spectrometers is that ions must be localized in space at time t1 in order to minimize Δd and, therefore, minimize the mass resolving power. Typically, time t1 corresponds to the time that the ion is located at the entrance to the drift region.
In summary, the limitations on conventional TOFMS include a mass resolving power dependent on the energy spread of the ions emitted from the ion source; the uncertainty in the distance of travel of the ion in its flight path; the problems associated with an ion source that is separate from the drift region; and the need to localize ions in space at time t1. The present invention provides an apparatus that overcomes these limitations and provides more accurate data.

Linear electric field time-of-flight ion mass spectrometer


A fuel feeding module has a fuel pump, a coarse fuel filter, a fine fuel filter, a storage cup to be arranged on a bottom of a fuel tank, the fuel pump with the coarse fuel filter being surrounded by the storage cup, the storage cup having a wall which at least in portions is formed double-walled, the individual walls together forming a completely enclosed intermediate chamber in which the fine fuel filter is arranged, the intermediate chamber having a supply connection connected with a pressure connection of the fuel pump in a region of the fine filter and also having a discharge connection in a region of the fine filter.

The present invention relates to a fuel feeding module with integrated fuel fine filter arranged in a fuel tank.
In motor vehicles partially fuel pumps are utilized, which are installed in the interior of the fuel tank. In order to guarantee the situation that with the fuel pumps located mainly on the fuel tank bottoms also during partially emptied fuel tank on curved travel and/or sight travel a reliable supply of fuel is guaranteed, the fuel pump is built in a so called storage cup which maintains the fuel level directly around the fuel pump on a predetermined level. The storage cup is filled for example by a suction jet pump from the fuel tank bottom. As a driving agent, the fuel returned from the internal combustion engine is utilized. The returned fuel can however flow back also directly into the storage cup.
On the way to the internal combustion engine the fuel as a rule flows through two different fuel filters. The first, coarse-pore filter is located at a suction side on the fuel pump integrated in the storage cup. The second, fine-pore filter is arranged after the fuel pump and located outside the fuel tank. This is disclosed for example in Jurgen Kasedorf, "Benzineinespritzung und Katalysatortechnik, Vogel Buchverlag", first edition, 1995, page 115 in connection with page 116.

Fuel feeding module with integrated fuel fine filter


A computer system reads data corresponding to an IC layout target layer and performs an etch simulation on the target layer. Etch biases are calculated and the inverse of the etch biases are used to produce a new target layer. The new target layer is provided as an input to an optical process correction (OPC) loop that corrects the data for image/resist distortions until a simulation indicates that a pattern of objects created on a wafer matches the new target layer. In another embodiment of the invention, original IC layout data is provided to both the OPC loop and an etch simulation. Etch biases calculated by the etch simulation are used in the OPC loop in order to produce mask/reticle data that will be compensated for both optical and resist distortions as well as for etch distortions.

As integrated circuit (IC) features become smaller, process distortions have a growing impact on pattern fidelity in manufacturing and, in turn, on device performance. Examples of process distortions include pattern-dependent line-width biasing, corner rounding, and line end shortening, all of which create patterns on a wafer that are different than patterns defined on a corresponding mask or reticle.
In recent years, optical process correction (OPC) techniques have been developed that compensate for distortions that occur in printing. Originally, OPC modifications could be a simple set of rules applied to bias or otherwise alter a layout. However, as patterns became more intricate and distortions more severe, model-based OPC techniques were developed.
In model-based OPC, a process model is developed to allow simulation of the processing effects, typically through making a set of convolution kernels. Such kernels are usually chosen to be an orthogonal set, with the relative magnitudes determined by a calibration procedure with empirically gathered data from the distorting process. The simulation consists of calculating a mathematical convolution of the layout pattern with the kernels. If the simulated image is significantly different from the target layer (i.e., original layout), edges corresponding to the out-of-spec patterns are moved and a new layout is generated. The new layout is then used as an input to the simulator to estimate how the revised layout will print. Once an image is formed with specified tolerances, OPC correction is achieved and the final layout is passed on to be fabricated as a mask or reticle. The mathematically based techniques for analyzing image distortions can also be applied to resist processing distortions.
Another processing distortion that affects a wafer is the etch effect, whereby the patterns that are etched on the surface of a wafer differ from a desired pattern. In principle, etched distortions could be corrected using the iterative techniques applied to imaging and resist distortions. However, in practice the results are often inaccurate. This is because the physical phenomena of etching, such as density-based microloading and certain etch shadowing effects are non-linear and not well described by the linear mathematics of convolution. Furthermore, most optical and resist effects occur over a relatively small distance, typically on the order of 1-1.5 microns. Etch effects are dictated by the physical properties of a plasma that is formed above the wafer and often have interaction diameters of 4-5 microns. Since the computation time of convolution increases with the area, an increase in diameter from 1 to 5 microns would increase the area and the associated computation time by a factor of 25. Alternatively, attempts have been made to add separate etch simulators as part of an OPC correction loop. However, etch simulators tend to be computationally intensive and the addition of an etch simulator within each pass of an OPC loop can make the OPC correction process impractical to implement.
Given these problems, there is a need for a method of correcting layout data for etch distortions in a manner that is not computationally impractical yet still produces accurate results.

Method of compensating for etch effects in photolithographic processing


A safe power plugging mechanism is configured on a power base with a pivot joint, wherein a male plug with conducting plates at its inside is configured on the pivot joint and is electrically connected with the pivot joint. A half-tile-shaped insulating tile configured outside the pivot joint axis is integral with the enclosure of the male plug, and partly encloses the pivot joint axis. A power connection plate is configured inside the power base to electrically connect the conducting plates of the male plug when the male plug is turned to a specific angle. The safe plugging mechanism also includes a female plug, which is configured at its inside with two conducting poles fitting the conducting plates of the male plug. The safe power plugging mechanism adopts a method of electric connection through a pivot joint axis which maintains connection at a specific angle and insulation at other angles.

1. Field of the Invention
The present invention relates generally to a plugging mechanism for electric power, and more particularly to a plugging mechanism which ensures safe connection to electric power, and which can be configured on mobile sockets, wall-mounted sockets, etc., and is particularly suitable for smart plugs commonly employed as power plugs for notebook computers.
2. Description of Related Art
Along with rapid development of technologies, especially with improvement of safety standards in developed countries, safety of power plugging mechanisms nowadays is more and more emphasized.
In current power plugging mechanisms, usually a plug meeting respective national standards is inserted into a socket, the conducting plates of which are hidden inside the socket, while the conducting poles of the plug are exteriorly exposed.
In addition, in prior-art power plugging mechanisms, there is also a type of smart plug mechanism, in which a male plug is connected to electric power. There are conducting plates configured inside the insulating enclosure of the male plug. The connecting terminal is formed as an 8-shaped plugging edge; and on the female plug side, an 8-shaped plugging notch fitting the insulating enclosure is correspondingly configured to enclose the exposed conducting poles inside the plugging notch. In this way, the smart plug mechanism is relatively safer than ordinary plug-socket power plugging mechanisms. Currently, such smart plugs are commonly seen in the power connection of notebook computers.
However, in all prior-art power plugging mechanisms, including smart plugs, the plugging parts often fall apart under accidental impacts such as stumbling on the cord or children playing, causing separation between the plug and the socket, or between the male and female plugs. Particularly in a wet environment or when the plugging operator's hands are wet, there is still danger of electric shock since the inside of the socket or male plug is live.
Hence, the prior-art mechanisms require some improvement and development. A type of power plugging mechanism that has improved safety is provided.


A powered door latch may be actuated by a capacitive sensor or by movement of a mechanical release device. A controller may be utilized to prevent unlatching of the powered latch unless the vehicle is in Park and/or certain operating conditions are present.

Various powered latches with interior door releases for motor vehicles and the like have been developed. However, the powered latch may not operate properly if vehicle power is lost, and mechanical back up release arrangements have been developed to provide for unlatching of the vehicle door in the event the vehicle's main power supply is lost. However, known systems suffer from various drawbacks.