An RFID reader accessible thorough a personal computer and includes a PC card interface and a controller both operating according to clock signals from a crystal oscillator. The RFID reader further includes a linearized power amplifier modulator in a transmit path, a receive chain capable of demodulating either class_1 or class _0 signals from RFID tags, and an integrated switching device for selecting one of a plurality of antenna for transmitting or receiving RF signals.

RFID technologies are widely used for automatic identification. A basic RFID system includes an RFID tag or transponder carrying identification data and an RFID interrogator or reader that reads and/or writes the identification data. An RFID tag typically includes a microchip for data storage and processing, and a coupling element, such as an antenna coil, for communication. Tags may be classified as active or passive. Active tags have built-in power sources while passive tags are powered by radio waves received from the reader and thus cannot initiate any communications.
An RFID reader operates by writing data into the tags or interrogating tags for their data through a radio-frequency (RF) interface. During interrogation, the reader forms and transmits RF waves, which are used by tags to generate response data according to information stored therein. The reader also detects reflected or backscattered signals from the tags at the same frequency, or, in the case of a chirped interrogation waveform, at a slightly different frequency. The reader typically detects the reflected or backscattered signal by mixing this signal with a local oscillator signal. This detection mechanism is known as homodyne architecture.
In a conventional homodyne reader, such as the one described in U.S. Pat. No. 2,114,971, two separate decoupled antennas for transmission (TX) and reception (RX) are used, resulting in increased physical size and weight of the reader, and are thus not desirable. To overcome the problem, readers with a single antenna for both TX and RX functions are developed by employing a microwave circulator or directional coupler to separate the reflected signal from the transmitted signal, such as those described in U.S. Pat. No. 2,107,910. In another patent, U.S. Pat. No. 1,850,187, a tapped transmission line serves as both a phase shifter and directional coupler.
Recent developments in RFID systems present challenges for conventional RFID readers. First, identification data stored on tags must be sent to readers in a reliable manner. Encoding this data and transmitting it over a modulated signal are two critical components of communications between tags and readers. While data coding determines the representation of data, signal modulation determines the protocol of communications between tags and readers. There are three main classes of digital modulation: Amplitude Shift Keying (ASK) or Class 1 protocol according to the EPCglobal Standard, Frequency Shift Keying (FSK) or EPCglobal Class 0 protocol, and Phase Shift Keying (PSK). Each of these classes has its own power consumption, reliability, and bandwidth requirements. It would be desirable for an RFID reader to be able to process signals from tags using different protocols.
Other challenging issues arise from interrogating passive RFID tags because the same signal used to communicate with the tags has to be used to power the tags. Passive tags receive power from readers through mechanisms such as inductive coupling or far-field energy harvesting. The received power can be significantly reduced because of modulations in the signal. Also, modulating information into an otherwise pure sinusoidal wave spreads the signal in the frequency domain. This spread is usually referred to as "side band" and is regulated by government. The amount of information that may be sent from a reader to a tag is thus limited by these limitations on modulation.
Furthermore, RFID readers have not been made in a PC Card format so that it can be integrated in handheld, portable or laptop computers to read from and write to RFID tags. The flexibility of an RFID reader on a PC Card also allows easy integration of an intelligent long-range (ILR) system into enterprise systems and permits combination with other technologies such as bar code and wireless local area networks (LAN). A PC Card RFID reader, however, presents other challenges because RF components of a conventional reader cannot fit in a small PC card housing and the operation of a PC interface may generate spurs in the transmit channel of the reader, resulting in spurious emissions from the reader that do not comply with regulatory requirements from the government. A PC Card RFID reader also needs to be low in cost, and still highly sensitive to incoming signals.

Integrated switching device for routing radio frequency signals


A method for operating an asynchronous generator comprising receiving an indication that a power grid frequency is reduced. Responsive to the receiving the indication, reducing a speed of the asynchronous generator from a first speed to a second speed for a first time period, wherein the reduction of the speed of the asynchronous generator results in a momentary increase in a total power output of the asynchronous generator. Increasing the speed of the asynchronous generator from the second speed to a third speed responsive to the end of the first time period.

Embodiments of the invention relate generally to electrical power generators, and more particularly to running variable speed electrical power generators on a power grid.
In this regard, power grids operate near a set frequency, for example, 50 hz or 60 hz. The generators that produce the power often operate at a speed that is locked to the grid frequency. Generators that operate at a constant speed locked to the grid frequency are called synchronous generators.
Asynchronous generators operate at variable speeds and include a stator and rotor that are each controlled by a power converter. The power converters control electrical fields in the stator and rotor and adjust the fields to output a frequency that matches the grid frequency. As the speed of the generator changes, the power converters continually adjust the fields in the stator and rotor to match the grid frequency, so that the generator speed is not locked to the grid frequency.
One advantage of using asynchronous generators is realized when a gas turbine engine (engine) is used as a prime mover. When operating at maximum temperature, gas turbine engines increase mechanical power output when the speed of the gas turbine engine is increased. As the speed of the engine increases, the volume of air through the engine increases, and the engine may burn more fuel while respecting temperature limits, thereby producing more mechanical power. Using an asynchronous generator allows the gas turbine engine prime mover to operate at higher speeds than would a synchronous generator that is locked to the grid frequency.
While operating on a grid, if for example, other generators that supply power to the grid fail, the load on the generator will increase and the frequency of the grid may be reduced. Generators on the grid mitigate this frequency drop in two time frames. Because synchronous generators are locked to grid frequency, their speed will drop in response to the frequency depression. In the first fraction of a second, the energy stored in the inertia of synchronous machines is delivered to the grid as they slow down, and mitigates the rate of frequency decay, giving time for turbine controls to act to increase fuel. In the next several seconds the fuel increase in the turbine makes up for the generation deficit on the grid.
Introduction of asynchronous generators to the grid has the advantage of allowing more power from gas turbines by increasing their speed during a grid generation deficit, even though the grid frequency is depressed. However, the act of increasing speed draws power from the grid during the initial fraction of a second, to accelerate the inertia of the turgine-generator.
It is therefor the object of the present invention to define a strategy that accomplishes both an initial benefit to a grid disturbance by a speed reduction, and a longer-term benefit by a subsequent speed increase.

Systems and methods involving operating variable speed generators


In a method for automated evaluation of a three-dimensional map of a laterally-symmetric organ system as well as medical image acquisition system and a computer program for this purpose, a three-dimensional image of the organ system is segmented, and the segmented organ system is deformed such that the deformed organ system has two mirror-symmetric halves with regard to its external shape. The differences between both mirror-symmetrical halves of the deformed organ system are determined by a comparison of one half with the other half. Alternatively, instead of the deformation of the segmented organ system a mirror-symmetric normal model of the organ system can be deformed, relative to the organ system, or vice versa, such that differences of corresponding regions of both halves of the organ system can be determined using the normal model. The determined differences are presented to a user.

1. Field of the Invention
The present invention concerns a method for automated evaluation of a three-dimensional image of a laterally-symmetric organ system as well as a medical image data acquisition system and a computer program for this purpose.
2. Description of the Prior Art
Data acquisition methods in which a three-dimensional data set or image of organ systems of a patient to be examined is produced are well known in medical imaging due to the exceptional diagnostic possibilities. The methods employed (such as, for example, computed tomography or magnetic resonance tomography) generate large data sets. For example, modern computed tomography systems produce dozens of slice image exposures in a few hundred milliseconds. The large number of exposures that arise can often be evaluated by a radiologist only with a very large expenditure of time. The risk of overlooking findings increases given the evaluation of large data sets.
For the evaluation of laterally-symmetric organs situated in a laterally-symmetrical manner, it is helpful and often even necessary for the radiologist to analyze both sides of the organ in comparison with one another. Often only a laterally different assessment indicates pathologies or (in the reverse case) an apparently suspect finding in one half of the organ system turns out to be a harmless normal variant when it also occurs in the other half of the organ system.
Large data sets must also be evaluated in for oncological questions, since often the entire body of the patient, or at least large portions thereof, are to be scanned for indicative of metastasy lesions. A typical example is plasmocytoma, which can manifest at many points of the skeleton. Laterally-different findings here are considered as particularly suspect with regard to a possible metastasy
As a result, there exists a need for automatic evaluation methods that support the user (in particular the radiologist) by marking suspect points to which the user subsequently directs his or her attention.
A method for automatic generation of result images of an examination subject using slice image data is disclosed in DE 103 57 205 A1 and in the corresponding US 2005/14852 A1. A target structure is initially determined dependent on a diagnostic question and an anatomical normal model, the geometry of which can be varied using the model parameters, is automatically adapted to the target structure. A segmentation ensues from which the adapted normal model and relevant anatomical structures of the examination subject are separated with regard to the relevant diagnostic question, by such structures being identified with the aid of the normal model. The relevant anatomical structures are subsequently separately visualized and/or stored for a later visualization.
DE 199 20 300 A1 discloses a method for tracking pathological variations in the human body using magnetic resonance scanners, wherein a 3D image data set is automatically compared with old image data sets of the same patient and/or with anatomical atlases for determination of pathological variations.

Method and apparatus for evaluating a 3D image of a laterally-symmetric organ system


The invention relates to improvements in paper, and in particular to the use of watermarks and/or embossings for strengthening paper sheets and documents made therefrom. The invention therefore provides a sheet of paper having at least three corners and three sides joined at said corners, wherein corner reinforcing watermarks are provided at each of said corners. Alternatively, or in addition, corner reinforcing embossings are provided at each of said corners.

1. Field of the Invention
The invention relates to improvements in paper, and in particular to the use of watermarks and/or embossings for strengthening paper sheets and documents made therefrom.
2. The Prior Art
Folded or bent corners (dog-ears) on banknotes present a significant problem for many banks, as they can cause problems in cash handling machines and can result in an artificially short note life. Many machines will reject such notes from circulation. One major European central bank has indicated that 80% of the rejections from their machines are due to such corner folds. Notes with folded corners can also be problematic in ATMs and cash dispensers and other note handling equipment. This is becoming a more significant problem as the use of such machines is becoming more and more widespread.
Efforts have been made to resolve this problem by providing note handling equipment with apparatus for flattening banknotes to enable a dog-eared or curled document to be fed without jamming. Such a system is described in U.S. Pat. No. 5,265,856.
Another problem which occurs with banknotes in particular results from the tendency of users to roll and fold notes for storage or keeping in wallets and purses. This gives rise to damage at the middle of the edges of the notes and similar problems arise in ATMs and other note handling equipment as occurs with dog-ears and corners.
It is therefore an object of the present invention to find a way of reducing the occurrences of corner folds and/or middle edge damage.

Paper including watermarks and/or embossing


A method, apparatus, and computer program product for optimizing software are provided. The software includes a plurality of modules which include at least one controllable module, the method comprises: determining a shared symbol defined by the at least one controllable module, the shared symbol being a symbol used by two or more modules of the software; generating a symbol use file indicating the shared symbol defined by the at least one controllable module; and rebuilding the software based on the symbol use file, so that a symbol table in a controllable module of the rebuilt software only contains the shared symbol indicated in the symbol use file. A number of symbols in the symbol table can be reduced accurately and effectively, thereby time needed for loading the symbol table can be reduced and software execution efficiency can be improved.

The present disclosure relates to software optimization, and more particularly, to a method, apparatus, and computer program product for optimizing software symbol tables.
Software may include several modules, such as an executable file and a library which the executable file needs to invoke. Each module may include a number of symbols, e.g., functions and/or variables, which may include symbols defined by the module itself and used only by the module (which may be referred to as internal symbols hereinafter), symbols defined by the module itself and used by two or more modules and symbols defined by another module and used by two or more modules (the latter two types of symbols may be referred to as shared symbols hereinafter). Generally, a symbol table is established in each module to store all symbols in the module and information associated with the symbols, such as types of the symbols, absolute addresses and offsets of the symbols for positioning the symbols, and the like. When the module runs, the symbol table can be loaded, and a corresponding operation may be executed according to the symbols and the related information in the symbol table.
As the software becomes bigger and bigger, there are more and more symbols and related information in the symbol table, making the symbol table increasingly large. This leads to more time consumed to load and parse the symbol table when the software is executed, and thus reduces software execution efficiency. Conventionally, such a problem can be solved by two methods. In a first conventional method, a developer of the software manually analyzes source files of the respective modules of the software to identify all the shared symbols in the software, compiles an export file in which the shared symbols are labeled as "export", and then provides the export file for a linker which hides the internal symbols in the symbol table of the module according to the export file. However, as the source files of the software are often very big in size, the operation of manually identifying all the shared symbols is very difficult and time-consuming, and is easy to cause omission. In addition, in the software (which, for example, is based on a C++ language), names of the symbols and the like may change during compiling and linking, rendering the method difficult to implement. In a second conventional method, the developer of the software modifies the source file of each module to add to the symbols in the module visibility labels indicating whether the symbols should be hidden, then the linker determines whether to hide the symbols in the symbol table according to the visibility labels of the symbols. This method requires modification of the source file, which would introduce additional risks, and when the software is updated, the labels of the respective symbols need to be updated accordingly, which is troublesome.

International Business Machines Corporation


A semiconductor device includes a semiconductor substrate of a first conductivity type, a first insulating film region that is embedded in a trench formed on the semiconductor substrate, a gate electrode that covers a lower surface of the first insulating film region, and a gate insulating film that is provided between the gate electrode and the semiconductor substrate. The semiconductor device further includes a first diffusion region that covers a first side surface of the first insulating film region, a second diffusion region that covers a second side surface of the first insulating film region, and a third diffusion region that covers an upper surface of the second diffusion region. A selective element includes a field-effect transistor that is constituted by the gate electrode, the first diffusion region, and the second diffusion region, and a bipolar transistor that is constituted by the substrate and the second and third diffusion regions.

1. Field of the Invention
The present invention relates to a semiconductor device, and more particularity relates to a semiconductor device using an IGBT (Insulated Gate Bipolar Transistor) as a selective element.
2. Description of Related Art
In recent years, a semiconductor device including a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) and a PC-RAM (Phase Change Random Access Memory) has an increasingly smaller area that can be allocated to a selective element (such as a cell transistor of a DRAM) along with the progress of downscaling. As the allocated area becomes smaller, the value of a current flowing to a selective element (such as a drain current of a field-effect transistor and a write current Icell in a DRAM) becomes small. Therefore, to secure a certain level of the current value, constituting a selective element by a combination of a MOS (Metal Oxide Semiconductor) transistor and a bipolar transistor has been examined.
U.S. Pat. No. 6,576,921 discloses an example of a cell transistor of a phase-change memory that uses such a selective element. In this conventional example, word lines are formed on a surface of a P-type substrate via a gate insulating film, and first and second N-type diffusion regions are formed in a region within a substrate surface close to both sides of the word lines. In the second N-type diffusion region, a P-type diffusion region is further provided in a region within a substrate surface far from a gate electrode. With this arrangement, a MOS transistor is formed by the P-type substrate, the first and second N-type diffusion regions, the gate insulating film, and the gate electrode, and a bipolar transistor is formed by the P-type substrate, the second N-type diffusion region, and the P-type diffusion region. The second N-type diffusion region functions as both a drain of the MOS transistor and a base of the bipolar transistor.
The P-type substrate and the first N-type diffusion region are grounded. Meanwhile, the P-type diffusion region is connected to bit lines via a phase-change memory element. When a voltage that exceeds a threshold value of the MOS transistor is applied to word lines in this state, the MOS transistor is turned on, and a drain current flows. This drain current flows to the second N-type diffusion region, and turns on the bipolar transistor. Because the phase-change memory element is connected to the ground, writing and reading can be performed to the phase-change memory element by controlling a voltage applied to the bit lines.
However, the selective element described in U.S. Pat. No. 6,576,921 has a problem that the length in a lateral direction becomes large. That is, according to the configuration of the selective element described above, the first N-type diffusion region, the word lines, the second N-type diffusion region, and the P-type diffusion region are arranged in a bit line direction. Therefore, even when these regions and the word lines are formed in a minimum feature size F, respectively, the length of 4F in the bit line direction becomes necessary. Consequently, a configuration capable of reducing the length of a selective element in a bit line direction has been demanded.

Semiconductor memory using field-effect transistor as selective element


The invention is directed to a high-density dispersion nuclear fuel having spherical particles of an uranium alloy dispersed in a nonfissionable matrix. The alloy includes uranium and 4-9 wt % Q, wherein Q is selected from the group consisting of Mo, Nb, and Zr. A process of manufacturing the spherical particles is also disclosed.

Conventionally powder for dispersion nuclear fuel is produced by alloying and comminution. Alloying metals are alloyed into ingots by induction or arc heating in a vacuum atmosphere. The as-cast ingots are heat-treated in a vacuum for 100 hours at 900.degree. C. to ensure compositional homogeneity, and then quenched to form a meta-stable gamma phase. The ingots are machined into chips and milled under liquid argon using a hardened steel mill to obtain the appropriate particle size. The chips of uranium alloys are very pyrophoric due to its high oxidative characteristics. Thus, it is necessary to machine under a sufficient amount of cutting fluid to substantially prevent oxidation. The fuel powder is contaminated by the cutting fluid. Processes of rinsing with an organic solvent such as acetone etc. and drying under vacuum atmosphere at a high temperature are required. Also, during milling the small particles containing ferrous impurities are introduced by the wear of milling machine parts. A close-up of the particle surface reveals many dark spots on the surface which energy dispersive spectroscopy has determined to be iron-rich. Most of the particles containing ferrous components are removed by magnetic separation.
As it is difficult to comminute uranium alloy ingots due to its tough property, the yield of uranium alloy through a mechanical powdering process, which consists of many steps of chipping, milling, rinsing, and drying, is very low, in the range of 5 to 20%. In addition, during magnetic separation about 30% of fuel powder is lost because separated powder contains a considerable amount of fuel particles.
In the case of directly making powder having a particle size from alloy ingots using a high speed lathe equipped with a rotary file, the productivity of usable powder is very low, as it yields 12 grams per hour. The yield of powder smaller than 212 .mu.m ranges from 32.about.63% of the total powder, depending on the alloy composition. The powder is produced by grinding ingots with a tungsten/tantalum carbide tool rotating at approximately 2,500 rpm. This process has the drawback of carbide and nitride contamination in the powder due to the wear of the rotary file. Contamination levels range from 0.1.about.7.6% and are generally higher for uranium alloys with larger alloy contents.
The comminuted particles with longish and irregular shapes, arranged along the rolling or extruding direction perpendicular to heat flow, inhibit thermal conduction in fuel meat. The large specific surface area of these irregular particles enhances the interaction between the fuel particles and an Al matrix to form uranium-aluminide (UAl.sub.x) with low-density around the perimeter of the uranium alloy particles, with the consequence of thermal swelling of the nuclear fuel meats.

Dispersion fuel with spherical uranium alloy, and the fuel fabrication process


A memory includes: memory elements arranged in a matrix, each memory element having such characteristics that when an electric signal at a level equal to or higher than that of a first threshold signal is applied to the memory element, the resistance thereof is changed from a high value to a low value, and when an electric signal at a level equal to or higher than that of a second threshold signal is applied thereto, the resistance is changed from the low value to the high value, the polarities of the first and second threshold signals being different from each other; electric circuits for applying electric signals to the memory elements; and detection units each for measuring a current flowing through the corresponding memory element or a voltage applied thereto from the start of the application of electric signals to detect whether the resistance is high or low.

1. Field of the Invention
The present invention relates to memories and semiconductor devices and, more particularly, to a memory and a semiconductor device, which detect a state of each memory element during a write sequence or an erase sequence to reduce time necessary for writing or erasing.
2. Description of the Related Art
In information equipment, such as computers, high-speed and high-density dynamic random access memories (DRAMs) are widely used as random access memories.
The DRAM is volatile, i.e., it loses information when powered off. Accordingly, a nonvolatile memory which does not lose information when powered off is preferable.
Up-and-coming nonvolatile memories include a ferroelectric memory (FeRAM), a magnetic memory (MRAM), a phase change memory, and a resistance change memory, such as a programmable metallization cell (PMC) or a resistance RAM (RRAM).
Those memories are capable of maintaining written information for a long time even when power is not supplied. Since the above memories are nonvolatile, refresh is unnecessary. Accordingly, power consumption can be reduced by the amount for refresh.
In addition, in the nonvolatile memory, such as a PMC or an RRAM, a memory layer for storing and maintaining information contains a material having such characteristics that the resistance depends on an applied voltage or current. In addition, each memory element has a relatively simple structure in which two electrodes are arranged, with the memory layer therebetween, and a current or a voltage is applied between the two electrodes. Accordingly, each memory element can be easily miniaturized.
The PMC is constructed such that an ionic conductor containing predetermined metal is arranged between two electrodes and any one of the two electrodes also contains the same metal as that in the ionic conductor. The structure has such properties that when a voltage is applied between the two electrodes, the electrical characteristic of the ionic conductor, such as resistance or capacitance, varies. The PMC utilizes the above-mentioned properties.
PCT Japanese Translation Patent Publication No. 2002-536840 (Patent Document 1) discloses an example of the PMC structure. In this example, an ionic conductor includes a solid solution of chalcogenide and metal, e.g., amorphous GeS or amorphous GeSe, and any one of two electrodes contains Ag, Cu, or Zn.
An example of the RRAM structure is disclosed in, e.g., "Novel Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)", W. W. Zhuan et al., Technical Digest "International Electron Devices Meeting", 2002, p. 193 (Non-patent Document 1). In this example, a thin film of polycrystalline PrCaMnO3 is arranged between two electrodes and a voltage pulse or a current pulse is applied between the two electrodes, thus significantly changing the resistance of the thin film, serving as a recording layer. The polarity of a voltage pulse applied in recording (writing) information differs from that in erasing information.
An example of another RRAM structure is disclosed in, e.g., "Reproducible Switching Effect in Thin Oxide Films for Memory Applications", A. Beck et al., Applied Physics Letters, 2000, Vol. 77, pp. 139-141 (Non-patent Document 2). In this example, a thin film of monocrystalline or polycrystalline SrZrO3 doped with a small amount of Cr is arranged between two electrodes and a current is supplied so as to flow between the electrodes, thus changing the resistance of the film, serving as a recording layer.
Non-patent Document 2 shows the I-V characteristic of the recording layer. A threshold voltage upon recording or erasing is ±0.5 V. In this structure, information can be recorded and erased by applying voltage pulses. A necessary pulse voltage is ±1.1 V and a necessary pulse width is 2 ms. In addition, high-speed recording and erasing can be performed. Non-patent Document 2 reports the operation using a voltage pulse width of 100 ns. In this case, a necessary pulse voltage is ±5 V.
In the FeRAM, it is currently difficult to perform nondestructive reading. Unfortunately, since destructive reading is performed, read speed is low. In addition, the FeRAM has a finite number of polarization reversals while reading or writing. This results in a limit in the number of rewritable times.
The MRAM needs a magnetic field in recording. Since the magnetic field is generated by a current supplied to a line, a large amount of current is necessary for recording.
As for the phase change memory, voltage pulses having the same polarity and different levels are applied to record data. In the phase change memory, switching depends on temperature. Disadvantageously, the phase change memory is sensitive to a change in environmental temperature.
In the PMC disclosed in Patent Document 1, the crystallization temperature of amorphous Ges or amorphous GeSe is approximately 200° C. If the ionic conductor is crystallized, the properties are altered. Unfortunately, the material is not capable of resisting high temperatures in a step upon actually manufacturing memory elements, e.g., in a step of forming a CVD insulating film or a protection film.
The memory layers proposed to be used in the PRAMs disclosed in Non-patent documents 1 and 2 are made of crystalline materials, respectively. Accordingly, there are the following problems: Thermal treatment at approximately 600° C. is necessary. It is very difficult to produce a single crystal of each proposed material. In the use of a polycrystal of each material, it is difficult to miniaturize memory elements due to the influence of grain boundary.
To solve the above-mentioned problems, e.g., Japanese Patent Application No. 2004-22121 (Patent Document 2) proposes a memory including memory cells. In this memory, each memory cell includes a memory element and a circuit element, serving as a load, connected in series to the memory element. The memory element has such characteristics that the resistance varies by the application of a voltage of a threshold voltage or higher across the memory element. The resistance of the memory element and that of the circuit element are combined into the combined resistance of the memory cell. The memory has the following characteristics: When a voltage applied between the memory element and the circuit element is equal to or higher than the threshold voltage, the combined resistance, obtained after the resistance of the memory element changes from a high value to a low value, has a substantially constant value independently of the voltage level. According to the proposed memory, stable recording can be realized and time necessary for recording can be reduced.

Memory and semiconductor device with memory state detection


A method for reading a pixel, including at least two integration periods, at least one of said periods including at least one integration sub-period, wherein an output value of the pixel is determined by taking into account the amounts of photogenerated charges contained in the pixel at the end of each of said periods and the amount of photogenerated charges stored in a photodiode of the pixel beyond a threshold during said at least one sub-period.

1. Technical Field
The present disclosure relates to image sensors, for example a CMOS sensor such as a high-dynamic sensor, and to a method for reading or controlling the pixels of such a sensor.
2. Description of the Related Art
Conventionally, a CMOS image sensor comprises pixels arranged in rows and in columns. Each pixel essentially comprises a photodiode used in reverse mode, having its junction capacitance discharged by a photocurrent according to a received light intensity, and a circuit for reading the pixel. The measurement of the illumination level received by a pixel is performed by measurement of the voltage across the photodiode at selected times, including the end of a period, called image acquisition or integration period, before and after which the pixel is reset by recharging of its photodiode. The decrease of the voltage across the photodiode during the integration is proportional to the received light intensity. The sensor also comprises a circuit for controlling the read circuit of each pixel, which especially controls the shutting, and a circuit for processing the pixel signal provided by the read circuit of each pixel.
For high light intensities, the photocurrent may be such that the discharge of the junction capacitance during the integration phase adversely affects the measurement. In particular, beyond a given light intensity threshold, which especially depends on the integration time and on the features of the pixel elements, the photodiode reaches, before the end of the integration time, a so-called saturation discharge level, and brightness differences are no longer discriminated.
To improve the sensitivity dynamics of a sensor, that it, the illumination range that a pixel of the sensor is capable of discriminating, it has been provided, in French patent application 2957475 and in patent U.S. Pat. No. 7,586,523, to implement control methods having a double integration period, that is, where the integration period comprises an integration sub-period. The pixel output value is then determined by taking into account the amount of photogenerated charges contained in the pixel at the end of the integration period, and the amount of photogenerated charges stored in the photodiode above a threshold during the integration sub-period.


According to one or more embodiment, a hygiene management device includes a processor. The processor determines based on image recognition whether a plurality of predetermined procedures of a hand-washing action have been completed by a subject. The processor executes different types of processing, such as, for example, opening or closing a passage, depending on completion or incompletion of each of the plurality of predetermined procedures.

In a food factory and the like, a hygiene-controlled area or a clean area is separated from a non-clean area, and when entering the clean area from the non-clean area, it may be required to follow a hygiene control procedure including handwashing. Similarly, in a hospital, a shop, a restaurant, a nursing care site, an educational site, and the like, it is often required to wash hands in a requested or suggested manner for preventing infectious diseases and maintaining hygiene. In such a place where hygiene control is required, an employee, a worker, and other persons who enter and exit the place may be required to completely carry out a predetermined hand-washing routine.

Hygiene management device and hygiene management method


A column A/D converter includes two column A/D converting elements. Each of the column A/D converting elements is operable to divide a pixel signal read out from a pixel array into two blocks i.e. an upper block constituted of upper two bit data, and a lower block constituted of lower two bit data, and sequentially perform A/D conversion with respect to the blocks in the unit of one horizontal scanning period. A controller causes each of the column A/D converting elements to concurrently perform A/D conversion with respect to different blocks of pixel signals at different rows.

1. Field of the Invention
The present invention relates to a solid state image sensing device provided with a column AD converter.
2. Description of the Related Art
In recent years, a solid state image sensing device incorporated with a CMOS (Complementary Metal Oxide Semiconductor) image sensor provided with a column A/D converter has been widely spread. For instance, there is known a solid state image sensing device including a pixel array constituted of pixels arranged in a matrix of a predetermined number of rows and a predetermined number of columns; and column A/D converting circuits corresponding to the columns of the pixel array, and for reading out a pixel signal from the pixel array for A/D conversion. Each of the column A/D converting circuits is a double integral A/D converting circuit for dividing the pixel signal into two blocks, and performing A/D conversion with respect to the blocks (see Japanese Unexamined Patent Publication No. 2002-232291).
FIG. 9 is a circuit diagram showing a column A/D converting circuit, corresponding to one column, to be used in a conventional solid state image sensing device. The column A/D converting circuit shown in FIG. 9 is a single slope integration column A/D converting circuit, and includes, in the order of input of a pixel signal from a pixel array, a GCA (Gain Control Amplifier) section 100, a comparator section 200, a logic circuit 300, a latch section 400, and a switch section 500.
The GCA section 100 is operable to amplify a pixel signal outputted from the pixel array, while performing CDS (Correlated Double Sampling) to remove a noise signal from the pixel signal.
The comparator section 200 has two comparators provided stepwise, and is operable to compare a pixel signal outputted from the GCA section 100 with two ramp signals (hereinafter, called as ramp signals Ramp1 and Ramp2). The ramp signal Ramp1 stepwise decreases in four steps, as time elapses, and the ramp signal Ramp2 stepwise increases in four steps, as time elapses.
The comparator section 200 compares the pixel signal outputted from the GCA section 100, with the ramp signal Ramp1 for A/D conversion with respect to upper two bits of the pixel signal; and inverts the output signal, if the level of the ramp signal Ramp1 is under the level of the pixel signal. After the comparison between the ramp signal Ramp1 and the pixel signal is terminated, the comparator section 200 compares the pixel signal outputted from the GCA section 100, with the ramp signal Ramp2 for A/D conversion with respect to lower two bits of the pixel signal; and inverts the output signal, if the level of the ramp signal Ramp2 is over the level of the pixel signal.
In response to inversion of the output signal by the comparator section 200, as a result of comparison between the pixel signal and the ramp signal Ramp1, the logic circuit 300 sets a signal COMPOUT1 to COMPOUT1=L (low level), and outputs the signal to a latch circuit 410. In response to inversion of the output signal by the comparator section 200, as a result of comparison between the pixel signal and the ramp signal Ramp2, the logic circuit 300 sets a signal COMPOUT2 to COMPOUT2=L, and outputs the signal to a latch circuit 420.
A counter 710 is constituted of a two-bit counter provided at the exterior of the column A/D converting circuit, and starts a counting operation in response to input of the ramp signal Ramp1 to the comparator section 200. Likewise, a counter 720 is constituted of a two-bit counter provided at the exterior of the column A/D converting circuit, and starts a counting operation in response to input of the ramp signal Ramp2 to the comparator section 200.
The latch section 400 includes the latch circuit 410 and the latch circuit 420. The latch circuit 410 latches a currently counted value of the counter 710, when COMPOUT1=L. Thereby, the latch circuit 410 latches digital data of upper two bits of the A/D converted pixel signal.
Likewise, the latch circuit 420 latches a currently counted value of the counter 720, when COMPOUT2=L. Thereby, the latch circuit 420 latches digital data of lower two bits of the A/D converted pixel signal.
A horizontal scanning circuit 600 outputs a column selecting signal indicating a column to be sequentially selected to switches 510 and 520, upon completion of A/D conversion with respect to the upper two bits of the pixel signal and the lower two bits of the pixel signal, turns on the switches 510 and 520, and outputs the digital data of upper two bits latched by the latch circuit 410, and the digital data of lower two bits latched by the latch circuit 420 to a horizontal signal line.
FIG. 10 is a timing chart of the column A/D converting circuit shown in FIG. 9. The timing chart shows operations to be performed with respect to a pixel signal at the i-th row of a pixel array in one horizontal scanning period.
Referring to FIG. 10, the symbol Vpixel indicates a pixel signal to be inputted to the GCA section 100, φPRST indicates a signal for turning on and off a switch of the GCA section 100, φS1 indicates a signal for turning on and off a switch of the former comparator in the comparator section 200, φS2 indicates a signal for turning on and off a switch of the latter comparator in the comparator section 200, φSH indicates a signal for turning on and off a switch connected between the GCA section 100 and the comparator section 200, φCK1 indicates a signal to be inputted to the upper NAND gate in the logic circuit 300, φCK2 indicates a signal to be inputted to the lower NAND gate in the logic circuit 300, Counter 1 indicates a counted value of the counter 710, Counter 2 indicates a counted value of the counter 720, Horizontal Shift Register Start Pulse indicates a horizontal synchronizing signal representing start of one horizontal scanning period, and DATAOUT indicates digital data to be outputted from the latch circuits 410 and 420.
As shown in FIG. 10, in one horizontal scanning period, the following operations (1) through (3) are performed, and the following operation (4) is performed concurrently with the operations (1) through (3).
Operation (1): Pixel readout (i-th row) An operation of reading out a pixel signal at the i-th row, while performing CDS to remove a noise signal from the pixel signal.
Operation (2): Upper bit A/D conversion (i-th row) An operation of performing A/D conversion with respect to upper two bits of the pixel signal at the i-th row.
Operation (3): Lower bit A/D conversion (i-th row) An operation of performing A/D conversion with respect to lower two bits of the pixel signal at the i-th row.
Operation (4): Output ((i−1)-th row) An operation of outputting the A/D converted pixel signal at the (i−1)-th row.
As shown in FIG. 9, the latch section 400 has a two-step arrangement constituted of the latch circuit 410 and the latch circuit 420. Accordingly, the operations (1) through (3), and the operation (4) can be concurrently performed. Specifically, digital data of the pixel signal at the (i−1)-th row can be outputted, while performing A/D conversion with respect to the pixel signal at the i-th row.
If the level of the ramp signal Ramp1 is under the level of the pixel signal at a timing TM1 in the period of the operation (2), COMPOUT1=L. Since the counted value of the Counter 1 when COMPOUT1=L is "01", the latch circuit 410 latches "01".
If the level of the ramp signal Ramp2 is over the level of the pixel signal at a timing TM2 in the period of the operation (3), COMPOUT2=L. Since the counted value of the Counter 2 when COMPOUT2=L is "10", the latch circuit 420 latches "10".
Then, in a succeeding horizontal scanning period, "01" latched by the latch circuit 410, and "10" latched by the latch circuit 420 are outputted to the horizontal signal line.
As described above, the double integral A/D converting circuit having the above arrangement enables to perform A/D conversion with a less number of clocks. Accordingly, as compared with a single integral A/D converting circuit, a time required for A/D conversion can be reduced, and one horizontal scanning period can be reduced. Thereby, the frame rate can be increased, and a high-speed photographing operation can be performed.
FIG. 11 is a sequence diagram on pixel signals at the i-th row and the (i+1)-th row to be processed by the A/D converting circuit shown in FIG. 9. The operations (1) through (3) are performed in one horizontal scanning period for the first row, wherein the pixel signal at the i-th row is subjected to A/D conversion, and the A/D converted digital data is latched by the latch circuits 410 and 420.
Then, in one horizontal scanning period for the second row, the operations (1) through (3) are performed, wherein the pixel signal at the (i+1)-th row is subjected to A/D conversion, and the A/D converted digital data is latched by the latch circuits 410 and 420; and the operation (4) is also performed, wherein the digital data of the i-th row latched by the latch circuits 410 and 420 is outputted from the latch circuits 410 and 420.
Then, in one horizontal scanning period for the third row, the operation (4) is performed, wherein the digital data of the (i+1)-th row latched by the latch circuits 410 and 420 is outputted from the latch circuits 410 and 420.
Specifically, in each of the one horizontal scanning periods, A/D conversion of the pixel signal at the (i+1)-th row, and output of the pixel signal at the i-th row are concurrently performed.
In the case where a pixel signal is divided into data of upper two bits and data of lower two bits for A/D conversion, as implemented by the A/D converting circuit shown in FIG. 9, the computation result on digital data of upper two bits is important. A/D conversion with respect to data of upper two bits is performed based on a comparison result between the ramp signal Ramp1 and the pixel signal. However, a certain time is required until the ramp signal Ramp1 is completely settled. In view of this, it is necessary to secure a predetermined time as a period for A/D conversion with respect to data of upper two bits in order to perform high-precision A/D conversion with respect to data of upper two bits.
As shown in FIG. 11, the operations (1) through (3) are performed in one horizontal scanning period by the A/D converting circuit shown in FIG. 9. It is, however, difficult to reduce the time required for performing the operation (2) of performing A/D conversion with respect to data of upper two bits. Accordingly, in the above arrangement, it is impossible to reduce one horizontal scanning period, and increase the frame rate.

Konica Minolta Business Technologies, Inc.


An amplifier circuit of a BTL system is disclosed, which comprises a first operational amplifier which outputs an output signal having a same phase as an input signal input to a signal input terminal, a second operational amplifier which outputs an output signal having an opposite phase to the input signal, a voltage divider which generates a midpoint voltage of the input signal, a first resistor connected between an output terminal and a negative phase input terminal of the first operational amplifier, second and third resistors connected in series between the negative phase input terminals of the first and second operational amplifiers, a fourth resistor connected between an output terminal and the negative phase input terminal of the second operational amplifier, and an impedance converter connected between a midpoint voltage node of the voltage divider and a series-connection node of the second and third resistors.

1. Field of the Invention
The present invention relates to an amplification circuit, and in particular, to a power amplifier of a bridge tied load (BTL) system for audio (a BTL power amplifier), which is used for, for example, a power amplifier for car audio of a high output specification.
2. Description of the Related Art
In a conventional BTL power amplifier, an input signal Vin is subjected to voltage-current conversion (V-I conversion) at a gm amplifier serving as a preamplifier to be made into a BTL signal current, and the BTL signal current is output to a circuit formed of first and second resistance elements connected in series. The series-connection node of the first and second resistance elements are connected to a reference input terminal. A voltage generated across the first resistance element is amplified by a first operational amplifier, and is output from the first operational amplifier as a same phase output voltage VoutP having the same phase as the input signal Vin. On the other hand, a voltage generated across the second resistance element is amplified by a second operational amplifier, and the amplified voltage is output from the second operational amplifier as an opposite phase output voltage VoutM having an opposite phase to the input signal Vin. A closed loop gain GvP of the first operational amplifier and a closed loop gain GvM of the second operational amplifier can be given by the following expressions (1) and (2).
                    GvP        =                              VoutP            Vin                    =                                    gm              ·              R                                                                                3              ·                                                                    R                                                                                1                                    +                                      R                                                                                2                                                                    R                                                                                2                                                                                (        1        )                                GvM        =                              VoutM            Vin                    =                                                    -                gm                            ·              R                                                                                6              ·                                                                    R                                                                                4                                    +                                      R                                                                                5                                                                    R                                                                                5                                                                                (        2        )
Assuming that feedback quantity of the first operational amplifier and the second operational amplifier are defined as f1 and f2, respectively, f1 and f2 can be given by the following expressions (3) and (4).
                              f                                                              1                =                              R                                                                          2                                              R                                                                                1                        +                          R                                                                                2                                                          (        3        )                                          f                                                              2                =                              R                                                                          5                                              R                                                                                4                        +                          R                                                                                5                                                          (        4        )
The feedback quantity do not depend on a frequency and is at a fixed value, and thus the BTL power amplifier of the above configuration is excellent in oscillation stability. In addition, since the circuit configuration of the first operational amplifier is the same as that of the second operational amplifier, the BTL power amplifier according to the above configuration has advantages that the circuit structure can be made symmetric and the circuit designing can be made easy.
However, in the power amplifier configured as described above, a noise and an offset voltage generated in the gm amplifier are amplified by the first operational amplifier and the second operational amplifier. Thus, the power amplifier as described above is unsuitable for use in a power amplifier of a low noise and a low offset voltage. Particularly, in the case of applying the circuit of the above configuration to an audio power amplifier or the like which is made into an integrated circuit, a sound quality is deteriorated if the noise is large, and a POP noise becomes large if the offset voltage is large. In order to attain a low offset voltage, high accuracy is required for elements forming the gm amplifier, which increases the chip area of the gm amplifier.
A concrete example of the gm amplifier, which is a preamplifier in the BTL power amplifier circuit of the above configuration, is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 4-343506.


A terminal apparatus communicates with a base station apparatus. The terminal apparatus includes: a determination unit that determines the number of modulation symbols for channel state information transmitted on a physical uplink shared channel based on a value of an offset; and a transmission unit that transmits the channel state information to the base station apparatus on the physical uplink shared channel. When two subframe sets are configured by higher layers, the value of the offset is determined depending on the subframe set to which subframes for transmission on the physical uplink shared channel belong. Thus, the communication can be performed efficiently in a radio communication system in which the channel state information is used.

Radio access schemes and radio networks (hereinafter referred to as a long term evolution (LTE) or an evolved universal terrestrial radio access (EUTRA)) of cellular mobile communication have been examined in the 3rd Generation Partnership Project (3GPP). In the LTE, a base station apparatus is referred to as an evolved NodeB (eNodeB) and a terminal apparatus is referred to as user equipment (UE). The LTE is a cellular communication system in which a plurality of areas covered by base station apparatuses are arranged in cell forms. A single base station apparatus may manage a plurality of cells.
The LTE corresponds to time division duplex (TDD). The LTE adopting a TDD scheme is referred to as a TD-LTE or LTE TDD. The TDD is a technology for enabling full duplex communication at a signal frequency band by performing time division multiplexing on an uplink signal and a downlink signal.
The 3GPP have examined that traffic adaptation technologies and interference management and traffic adaptation (IMTA) technologies are applied to the TD-LTE. A traffic adaption technology is a technology for changing a ratio between an uplink resource and a downlink resource according to an uplink traffic and a downlink traffic. The traffic adaptation technology is also referred to as a dynamic TDD.
In NPL 1, a method of using a flexible subframe is suggested as a method of realizing traffic adaptation. A base station apparatus can receive an uplink signal or transmit a downlink signal in a flexible subframe. In NPL 1, a terminal apparatus regards a flexible subframe as a downlink subframe unless the terminal apparatus receives an instruction to transmit an uplink signal in the flexible subframe from the base station apparatus.
NPL 1 discloses that a hybrid automatic repeat request (HARQ) timing with respect to a physical downlink shared channel (PDSCH) is determined based on newly introduced uplink-downlink configuration and an HARQ timing with respect to a physical uplink shared channel (PUSCH) is determined based on initial UL-DL configuration.
NPL 2 discloses that (a) UL/DL reference configuration is introduced and (b) one subframe can be scheduled for either of an uplink and a downlink by dynamic grant/assignment from a scheduler.
In section 7.2 of NPL 3, an order of terminal apparatuses for reporting of channel state information (CSI) is described. A base station apparatus allocates downlink resources to the terminal apparatuses based on the channel state information reported from the plurality of terminal apparatuses. The channel state information includes a channel quality indicator (CQI).

Terminal apparatus, base station apparatus, integrated circuit, and radio communication method


The invention relates to a liquid detergent concentrate composition comprising an emulsion having an aqueous phase and an oil phase, the composition comprises based on the whole concentrate 1 to 50 wt-% of one or more alkalinity source, 1 to 60 wt-% of a guerbet alcohol ethoxylate of the formula R1—(OC2H4)n—OH, wherein R1 is a branched C8 to C10 alkyl group and n is from 2 to 10, 1 to 30 wt-% of a linear alkoxylated fatty alcohol of the formula R2—(OC2H4)x—(OC3H6)y—OH, wherein R2 is a linear C10 to C16 group and x is from 3 to 7 and y is from 3 to 7. 0.01-10 wt-% of one or more crosslinked or partly crosslinked polyacrylic acid Q or polymethacrylic acid or mixtures thereof and the rest up to 100 wt-% is water.

In institutional and industrial washing processes the wastewater of the washing process is usually cleaned and purified by using membrane filtration units. The obtained purified water can then be re-used in another washing cycle. The use of a membrane filtration process for the cleaning of wastewater results in a decrease of the amount of fresh water required to be added to the washing cycle and accordingly in a reduction of costs and saving resources. Also from an environmental point of view the use of membrane filtration is advisable.
However, the membrane cleaning processes can only be applied for wastewater which does not contain components blocking the membrane of the membrane filtration unit. Therefore it is necessary to use membrane-compatible detergents in these washing processes which do not contain any membrane-blocking or membrane-destroying components.
In the state of the art membrane-compatible detergent compositions are already known. However, most of these detergents are detergents in paste form having a high viscosity.
WO 2005/118760 A1 describes for example a membrane-compatible pasty soap composition which is used in a washing process in which the wastewater is purified by a membrane filtration unit and especially in a membrane filtration unit comprising one or more reverse osmosis steps. The detergent comprises anionic surfactants, non-ionic surfactants, an alkalinity source, and an organic and/or inorganic builder on a non-silicate basis. Furthermore the composition is free of greying inhibitors on a cellulose basis, silicates, and phosphates.
As non-ionic surfactants linear fatty alcohol alkoxylates are used which are ethoxylated. Furthermore the composition comprises alkyl polyglycoside having 8 to 14 carbon atoms.
The paste has a high viscosity preferably being between 30,000 to 60,000 mPas at 50 revolutions per minute measured using a Brookfield rotational viscosimeter with spindle no. 7 at 25° C.
A further paste-like detergent is described in WO 02/46351 A1. This detergent is also used in a washing process in which the accumulated wastewater is cleaned by a filtration process using a membrane filtration unit.
The use of detergents in paste form in washing processes has the disadvantage that expensive dosing units are necessary to pump the high viscous paste into the institutional and industrial washing machines. Therefore there is a need for providing a liquid membrane-compatible detergent concentrate having a low viscosity being able to be pumped through the washing device by using standard pumping units which are less expensive.
Liquid detergents are known from the state of the art. Such detergents are, for example, described in U.S. Pat. No. 5,880,083, WO 2004/065535 A1, and WO 2004/041990 A1. However, the liquid detergents being used in the state of the art often contain components causing the blocking of the membrane filtration unit and hence cannot be used for washing processes in which membrane filtration units are used for the cleaning of the wastewater. Those components, if used in high amounts, are for instance cationic surfactants, certain emulsifiers, carboxymethylcellulose and silicates. These components immediately block the membrane and lead to an interruption of the whole washing process. By leaving out such components the stability of the liquid detergent composition which normally is an emulsion or dispersion decreases. This decreased stability results in a separation of the emulsion or the dispersion after storage or when used at extremely different temperatures. Separated emulsions or dispersions cannot be used in the washing process and cannot be dosed applying the usual dosing units.
PCT/EP2006/060465 which is an earlier application describes a liquid detergent composition being membrane-compatible. The composition is storage-stable and shows a good washing performance. As non-ionic surfactants linear alkoxylated alcohols are used in the detergent composition. These are, for example. linear fatty alcohol ethoxylates having a C13-C15 alkyl group and 7 EO units. These non-ionic surfactants are, for example, available under the trade name Lutensol AO7 from BASF.
These linear non-ionic surfactants, however, have the disadvantage of being classified as highly toxic for water organisms. During transport they have to be declared as polluting substances.
Therefore it is necessary to replace such kinds of non-ionic surfactants by other surfactants which are also membrane-compatible resulting in a similar storage stability and washing performance and are environmentally more acceptable.

Liquid membrane compatible detergent formulation comprising branched alkoxylated fatty alcohols as non-ionic surfactants


The invention relates to a method for the preparation of imidodisulfuryl compounds in a continuous reaction at elevated temperatures.

In the following text, if not otherwise stated, the following meanings are used:
CSI chlorosulfonyl isocyanate
CSOS chlorosulfonic acid
ClSI bis(chlorosulfonyl)-imide
FSI fluorosulfonyl isocyanate
FSOS fluorosulfonic acid
FR flow rate
RT room temperature
Imidodisulfuryl compounds are used for a number of purposes. One example is the use of imidodisulfurylchlorid for the preparation of lithium bis(fluorosulfonyl)imid, which again is used as an electrolyte e.g. in lithium ionic batteries, which e,& can be used in automotive batteries, and is used as antistatic agent in touch screens.
DE 1 159 410 B discloses a method for preparation of halosulfonyl isocyanates by a reaction of halosulfonic acid with urea. The reaction is done preferably at a temperature of from 100 to 180° C. Specifically disclosed is the preparation of chlorosulfunyl isocyanate at a temperature of from 120 to 150° C.
DE 1 143 495 B discloses a method for preparation of imido-bis(sulfuryl)fluorid by a reaction of fluorosulfonic acid with urea. The reaction temperature is not stated apparently the reaction starts at room temperature and in the course of the reaction the reaction mixture is cooled from time to time.
CA 710255 A discloses a method for preparation of imido-bis(sulfurylchloride) by a reaction of chlorosulfonic acid with trichlorophosphazo-sulfuryl chloride. Methods such as disclosed in CA 710255 have the disadvantage of requiring phosphorus chemistry which is rather expensive and environmentally disadvantageous to use.
WO 20091123328 A1 discloses the preparation of ClSI in a batch method, details are given the example section of instant invention.
The reaction equation of instant invention for preparation of imidodisulfurylhalides, also named imidobis(sulfurylhalides), imidobissulfurylhalides or bis(halidosunnyl)imide, which also is applicable for similar compounds of instant invention, is depicted in Scheme 1;
with Xa and Xb being halogen.
Both starting compounds, the isocyanate and the sulfonic acid, and the product, the his imide, are toxic and corrosive. In case of Xa and Xb being Cl, the product shows a very high exothermic decomposition at elevated temperatures, making it necessary to provide adequate safety measures in production. The heat of reaction deltaH is ca. 100 kJ/mol, the onset of decomposition of the imidosulfurylchloride is around 180° C. with an adiabatic temperature rise to temperatures well over 400° C. The reaction of CSI with FSOS and the reaction of PSI with CSOS show similar temperatures for the onset of decomposition.
Therefore the reaction temperature in batch processes in production is not higher than 150° C. to avoid the risk of explosion. The reaction times of the batch processes ranges from ca, 8 h to 24 h.
On the other hand the isocyanate and the sulfonic acid only react at elevated temperatures. Due to these circumstance and safety considerations, in the past the imidodisulfurylhalides have been prepared only in small batches and at temperatures well below the onset of decomposition as mentioned, leading to the mentioned long reaction times.
There was a need for a method for preparation of imidodisulfurylhalides, which does not need phosphorous chemistry, has short reaction times and high yields, where the product shows high purity, and allows for safe handling of the substances and of the reaction, also on a large scale.
Unexpectedly, it is possible to react a halosulfonyl isocyanate with a halosulfonic acid at temperatures above the onset temperature of decomposition of the reaction product, the imidodisulfurylhalide without the expected decomposition of the desired imidodisulfurylhalide, the yields are high. It was unexpected to be able to conduct the reaction in a safe way. This allows for the desired short reaction times.
Furthermore the short reaction times can be realized still with a product with high purity, i.e. not showing discoloration due to decomposition or polymerization reactions usually taking place at too high temperatures.

Method for preparation of imidodisulfuryl compounds


An active GPS tracking system and method includes a user setting interface for receiving a reporting distance, a distance trigger module, a GPS module and a wireless communication module. The distance trigger module calculates a moving distance of the active GPS tracking system, and generates and sends an interrupt signals to the GPS module to make it enter a working mode when the moving distance is greater than or equal to the reporting distance. Then, the GPS module determines a current position of the active GPS tracking system and determines whether an actual displacement is greater than or equal to the reporting distance to determine if reporting the current position. If the actual displacement is greater than or equal to the reporting distance, the wireless communication module receives the current position from the GPS module, and reports to a monitor center.

1. Technical Field
The present disclosure relates to Global Positioning Systems (GPS), and especially to an active GPS tracking system and a method for reporting its position.
2. Description of Related Art
The Global Positioning System (GPS) is a communication system that transmits, receives, or processes signals via a plurality of satellites. An active GPS situated on a target can determine a current position of the target via communication with the plurality of satellites, and report the current position to a monitor center. Generally, an active GPS is required to report the current position of the target to the monitor center at predetermined time or distance intervals. That is, the active GPS is supposed to communicate with the satellites every the predetermined time or distance intervals to determine the position of the target. However, in general situations, the target might not move for a relative long time. The active GPS still reports the position of the target to the monitor center at the predetermined time intervals, which results in unneeded power consumption.
Therefore, a need exists in the industry to overcome the described limitations.

Active GPS tracking system and method for reporting position thereof


A positioning device for the work-piece backing plate of a table sawing machine includes a machine seat, a work-piece backing plate and a position-limiting device. The work-piece backing plate has its opposite sides respectively fixed with a rack engaged with a gear set installed in the interior of the machine seat. The work-piece backing plate can be controlled by the gear set to move forward and backward on the machine seat. The position-limiting device is assembled in the interior of the machine seat for restricting and fixing the work-piece backing plate in position to prevent the work-piece backing plate from shifting bias in the course of processing, able to elevate processing precision.

1. Field of the Invention
This invention relates to a positioning device for the work-piece backing plate of a table sawing machine, particularly to one able to prevent the work-piece backing plate from shifting bias to elevate precision in processing.
2. Description of the Prior Art
The work-piece backing plate of a conventional table sawing machine, as disclosed in a U.S. Pat. No. 6,736,042 B2, is provided at one side with an eccentric handle to be turned for actuating the opposite ends of a connecting rod to tightly clamp the side edges of a work table and firmly position the work-piece backing plate.
However, the handle of the work-piece backing plate of the conventional table sawing machine is exposed out of the outer edge of the table sawing machine for the sake of being operated conveniently. Therefore, in case of carelessness, an operator is likely to bump against the handle and get injured or cause damage to the handle.

Positioning device for the work-piece backing plate of a table sawing machine


A super capacitor (SC) and methods are disclosed, forming massive embedded capacitors connected in parallel over very wide radii varying from a few square feet to hundreds of square miles. The SC is enclosed within a water proof housing to keep out water by depositing a plurality of alternating layers of dielectric material between each conducting layer, whereby one or more electrodes are situated on each dielectric layer, and having at least one probe electrode exuding from said housing, and connected to the one or more electrodes, for receiving electric charge from a lightning source, for example. The dielectric layers separating each conducting layer may vary from a few layers to thousands, and possibly even millions or more layers, for example, to define a multilayer capacitive structure capable of providing electric power to supplement or replace other sources of electric power that harm the environment.

Microelectronic capacitors are typically formed by patterning a conductive region on a ceramic substrate to define a bottom electrode, depositing a thin layer of a dielectric material over the bottom electrode to form the dielectric for the microelectronic capacitor, and then forming a second electrode over the dielectric, patterned to form the microelectronic capacitor, using a second conductive region above the dielectric material. In this way, microelectronic capacitors store electric charge, and since work must be done to charge the microelectronic capacitor, the microelectronic capacitor will also store electric potential energy. If one considers an example isolated metallic sphere of radius R, any electric charge stored on this sphere, call it Q, can be articulated as a potential:
  V  =                              1                                                  4                        π                                                                                ɛ              0                                                                        Q                                      R                    such that the amount of charge stored on the sphere is directly proportional to the potential (V). This proportionality exists for any conductor of any shape or size. Capacitance (C) of this single conductor is large if the conductor is capable of storing a large amount of charge at a low potential, so that the relation:
  Q  =            CV                                      becomes                                      C        =                                        Q                                                V                              =                                                  Q                                                                                1                                      Q                                                                                4                                    π                                ∈                0                                                    R                                      =                  4                    π                                                                          ɛ            0                              R                    Therefore, the capacitance of the sphere increases with its radius, and many such spheres wired together in parallel creates a net capacitance that is the sum of their individual capacitances. Furthermore, capacitors store not only electric charge (Q), but also electric potential energy (U), which can be expressed roughly as:
  U  =                                          1            /            2                                                                        Q                                                              2                                    C            (ignoring the energy density in the dielectric layers). The electric potential energy (U) is also the total amount of work that must be performed to charge the capacitor.
What is needed is a macroelectronic circuit referred to herein as a super capacitor and method that exploits the above relationships to be used to capture and store the electric charge of lightning, whether naturally occurring or human generated, as an alternative energy source for human consumption. After determination of the total energy range generated by lightning strikes in a particular setting, an optimum radius and number of embedded parallel layers of capacitors forming the super capacitor of the present invention can be established based on the area of land, or other substrate, that is available to support the super capacitor housing of the present invention.


A fluid actuating drive for relative translational movement of first and second structural parts has a housing filled with a pressurizing medium, which in its longitudinal direction, runs along a gap that separates the structural parts, and is connected therewith. The width of the gap is dependant upon the relative position of opposing side walls of the housing, which side walls can be moved against one another with a pressurizing agent for the relative movement of the structure, where the side walls are alternately connected to the first and second structural part across the gap.

This application claims the priority of German patent document 100 09 157.1, filed Feb. 26, 2000, the disclosure of which is expressly incorporated by reference herein.
The invention relates to a fluid actuating drive which is operated with a hydraulic or pneumatic supply, for mutual displacement of two structural parts.
German patent document DE 4312503 A1 illustrates a folding bellows, with two mounting parts that move relative to one another. When activated, the bellows moves outwards or inwards across its folds. The direction of the forces thus applied on the mounting parts depends upon the operation of the mounting parts or of the components arranged accordingly on them. Hence, a high mechanical guiding force is required for components that extend over a relatively large area transverse to the direction of movement. A hydraulically operated spring bellows is described in German patent document DE 3420557, which is coupled with a pneumatically pressurized cylindrical chamber. The spring bellows is bent in a circular arc, in order to act in conjunction with a swivel bracket with the cylindrical chamber acting as a shock-absorbing element. The spring bellows is introduced into a housing with a circular cross-section. A suitable converter is required for converting the swivelling movement into a translational movement. Apart from this, appropriate mechanical guidance of the components moving against each other is also necessary.
A disadvantage of state of the art actuating drives is that the forces that act upon the structural components as a result of the actuating forces, can be conducted into these components only locally. As a result, comparatively greater forces are generated locally on the connecting points between the actuating drive and the structure, thus making it necessary to install expensive force transmission devices on the structure components concerned.
One object of the invention therefore is to provide a fluid actuating drive for effecting smooth adjusting movements that transmits the forces the concerned components as uniformly as possible.
Another object of the invention is to provide such a fluid actuating drive that is simple, space-saving and light-weight.
These and other objects and advantages are achieved by the fluid actuating drive according to the invention, for moving a first and a second structural part relatively to one another. A housing filled with fluid is arranged along the longitudinal direction of a slot or gap (13) which separates the first and second structure parts. The housing is shaped according to its relative position and its side walls are in contact with the first and second structural parts through its peripheral surface, alternating area-wise. The side-walls can change shape by means of a fluid, so that they move or swivel against each other, to move the structured parts against each other.
In another embodiment, a second housing can be mounted on this first housing, which is also filled with the fluid on both the sides. To change the cross-section of the first housing, fluid is circulated between the first housing and the area between it and the second housing. Adjusting movements in both the directions are possible with this arrangement.
In yet another embodiment, the fluid can be found in flexible hoses with negligible elongation, so that the housing need not be sealed.
An advantage of the invention is that, makes it possible to move large adjustment areas against one another using comparatively less equipment, since conduits are required at only a few points.
Another advantage of the invention is that with the actuator according to the invention both tension and compression movements are possible. Smaller fluid volume movements are required, so that the reservoirs otherwise need for the fluid used can be made small or eliminated. The structural parts can be held at specific positions with minimum energy consumption. Furthermore, by virtue of the invention, smaller conduit lengths are required for the fluid movements; thus, this invention proves to be favorable in respect of weight and total expenditure, such as costs. Another advantage is that a closed system is possible with this invention, which helps eliminate leakage problems almost entirely.
Since the forces are transmitted in a flat manner, the actuating drive helps avoid the concentration of larger forces, as known in the state of the art, which are usually generated in case of structural conduction of forces.
other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.

Fluid actuating drive for smooth adjusting movements


Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.

Memory devices can include internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), and non-volatile memory.
Non-volatile memory devices (e.g., flash memory) have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
Non-volatile memory devices are also incorporated into solid state storage devices such as solid state drives. Solid state drives can be used in computers to replace the hard disk drives that typically have used magnetic or optical disks for storing large amounts of data. A solid state drive does not use moving parts whereas a hard disk drive requires a complex and sensitive drive and read/write head assembly to interact with the magnetic/optical disk. Thus, the solid state drives are more resistant to damage and loss of data through vibration and impacts.
One drawback to current solid state drive technology is achieving the memory density necessary to adequately and cost effectively replace a computer's hard disk drive. Most modern computers require the capability for storing very large amounts of data (e.g., 250 GB or more) due to digital images, movies, and audio files. Thus, an effective solid state drive should have a memory density approaching a typical hard drive, remain cost competitive, and still fit within the constantly decreasing thickness of a laptop computer, for example.
FIG. 1 illustrates one typical prior art solid state drive with four channels between a controller and the memory devices and no DRAM buffer. A memory communication channel 110 is comprised of the address, data, and control signal lines for a group of memory devices 101-104. In this example, each channel is coupled to four stacked memory devices 101-104 that is connected to the controller 100.
In order to increase the performance of solid state drives, DRAM has been incorporated into the drives. FIG. 2 illustrates a block diagram of a typical prior art solid state drive that incorporates a DRAM device 200 for storage of temporary data. The drive of FIG. 2 shows an eight channel controller 230 in which the eight channels 201-208 are each connected to four memory devices. The DRAM device 200 is connected to the controller 230 over dedicated data 220 and address/command 221 buses.
Since DRAM has an access time that is substantially less than non-volatile memory, the DRAM can be used to maintain translation tables and buffers that would normally be done by the slower non-volatile memory. However, the size of the DRAM is limited by the number of address and data lines available on the controller 230. Memory controllers, in order to save space on the controller, typically have a small quantity of address/data signal lines. Thus only a relatively low density DRAM can be connected to the controller. If the translation tables and other temporary data requiring DRAM requires more memory, the controller will use non-volatile memory. This impacts the performance of the solid state drive since the non-volatile memory tends to be slower in both reading and writing of data.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a way to control both non-volatile and volatile memory in a solid state storage device while using larger volatile memory devices.

Solid state storage device controller with expansion mode


A packaging box includes a box and a support received in the box. The support includes a top board, a bottom board opposite to the top board, and a side board interconnecting the top board and the bottom board. The top board defines a hole and forms four limiting boards connecting to the top board and resisting against the bottom board. The limiting boards and the bottom board cooperatively form a receiving chamber. The receiving chamber comprises a standing leg formed from the bottom board. The standing leg is capable of folding relative to the bottom board and cooperatively supporting the support to position on a plane with the side board.

1. Technical Field
The disclosure generally relates to packaging boxes, and particularly to a packaging box including a support for electronic devices.
2. Description of Related Art
To prevent fragile precise electronic devices such as mobile phones from being damaged during transportation (e.g. by water, dust and impact), the electronic devices are commonly put in packaging boxes before shipment. However, most the packaging boxes are discarded after users buy the electronic devices and take the electronic devices out from the packaging boxes, which is a waste of resources.
Therefore, there is room for improvement within the art.

Support and packaging box for electronic device


A printer stores printer position information in sequence and calculates its representative value as statistical printer position information by a statistical method. When a public key is requested by a print client, the printer generates a public key with a passphrase containing the statistical printer position information and transmits the public key to the print client. The print client generates print transmitting data by encrypting print data with this public key and transmits the print transmitting data to the printer. The printer generates a private key with a passphrase containing the statistical printer position information at this point in time and decrypts the print data.

1. Field of the Invention
The present invention relates to a printer and a print system, and a data receiving device and a data transmitting and receiving system, and particularly relates to a printer and a print system, and a data receiving device and a data transmitting and receiving system which ensure security of data transmitted to the printer and the data receiving device.
2. Description of the Related Art
These days, a print system in which a printer is shared by means of a network has been increasingly used. Namely, by connecting plural computers as print clients to one network and connecting, for example, one printer to this network, one printer can accept print data from the plural print clients and print the print data.
In such a print system by means of the network, various users can transmit print data from their respective print clients to the printer and perform printing.
However, if the print data transmitted from the print clients is printed by the printer unconditionally, a print operation is executed even by the printer which is not installed in a place where the user intends to perform printing. In particular, in the case of a printer moved from one place where the printer has been heretofore used to another place, an IP address or the like which is an address on the network sometimes remains unchanged, and hence the transmitted print data may be printed by the printer moved to another place. The above situation is undesirable for users who want to ensure the security of print data.
Moreover, if the print data transmitted from the print clients is printed by the printer unconditionally, even print data transmitted from the print clients which are not duly authorized to perform printing with the printer is printed by the printer. In this case, print clients capable of perform printing with the printer cannot be restricted, which is undesirable as well. Especially when the possibility of the existence of users who transmit a large amount of print data with dishonest intention is considered, it is necessary to provide some print restriction.
Further, in some cases, a printer which has been used in one department of a company is moved to another department and used there. In such a case, even print clients which have heretofore had the authority of perform printing with this printer are not sometimes wanted to be given the authority to perform printing with this printer after the printer has been moved. In the above situation, a need for technology which prevents print data from the print clients from being printed on the printer side is acknowledged.
Hence, the present invention is made in view of the aforementioned problem, and an object of the present invention is to provide a print system which ensures security of print data and a printer by restricting printable print data based on information on a position where the printer is installed. Another object of the present invention is to provide a data transmitting and receiving system which ensures security of transmit data and a data receiving device by restricting processable data based on information on a position where the data receiving device is installed. Still another object of the present invention is to provide a print system capable of smoothly decrypting received print data or a data transmitting and receiving system capable of smoothly decrypting received data even if a measure of variations in position information detected by a printer and a data receiving device occur.

Printer and print system, and data receiving device and data transmitting and receiving system


Novel backbone cyclized peptide analogs are formed by means of bridging groups attached via the alpha nitrogens of amino acid derivatives to provide novel non-peptidic linkages. Novel building units disclosed are N.sup..alpha. (.omega.-functionalized) amino acids constructed to include a spacer and a terminal functional group. One or more of these N.sup..alpha. (.omega.-functionalized) amino acids are incorporated into a peptide sequence, preferably during solid phase peptide synthesis. The reactive terminal functional groups are protected by specific protecting groups that can be selectively removed to effect either backbone-to-backbone or backbone-to-side chain cyclizations. The invention is exemplified by backbone cyclized bradykinin antagonists having biological activity. Further embodiments of the invention are somatostatin analogs having one or two ring structures involving backbone cyclization.

Peptidomimetics
As a result of major advances in organic chemistry and in molecular biology, many bioactive peptides can now be prepared in quantities sufficient for pharmacological and clinical utilities. Thus in the last few years new methods have been established for the treatment and therapy of illnesses in which peptides have been implicated. However, the use of peptides as drugs is limited by the following factors: a) their low metabolic stability towards proteolysis in the gastrointestinal tract and in serum; b) their poor absorption after oral ingestion, in particular due to their relatively high molecular mass or the lack of specific transport systems or both; c) their rapid excretion through the liver and kidneys; and d) their undesired side effects in non-target organ systems, since peptide receptors can be widely distributed in an organism.
Moreover, with few exceptions, native peptides of small to medium size (less than 30-50 amino acids) exist unordered in dilute aqueous solution in a multitude of conformations in dynamic equilibrium which may lead to lack of receptor selectivity, metabolic susceptibilities and hamper attempts to determine the biologically active conformation. If a peptide has the biologically active conformation per se, i.e., receptor-bound conformation, then an increased affinity toward the receptor is expected, since the decrease in entropy on binding is less than that on the binding of a flexible peptide. It is therefore important to strive for and develop ordered, uniform and biologically active peptides.
In recent years, intensive efforts have been made to develop peptidomimetics or peptide analogs that display more favorable pharmacological properties than their prototype native peptides. The native peptide itself, the pharmacological properties of which have been optimized, generally serves as a lead for the development of these peptidomimetics. However, a major problem in the development of such agents is the discovery of the active region of a biologically active peptide. For instance, frequently only a small number of amino acids (usually four to eight) are responsible for the recognition of a peptide ligand by a receptor. Once this biologically active site is determined a lead structure for development of peptidomimetic can be optimized, for example by molecular modeling programs.
As used herein, a "peptidomimetic" is a compound that, as a ligand of a receptor, can imitate (agonist) or block (antagonist) the biological effect of a peptide at the receptor level. The following factors should be considered to achieve the best possible agonist peptidomimetic a) metabolic stability, b) good bioavailability, c) high receptor affinity and receptor selectivity, and d) minimal side effects.
From the pharmacological and medical viewpoint it is frequently desirable to not only imitate the effect of the peptide at the receptor level (agonism) but also to block the receptor when required (antagonism). The same pharmacological considerations for designing an agonist peptidomimetic mentioned above hold for designing peptide antagonists, but, in addition, their development in the absence of lead structures is more difficult. Even today it is not unequivocally clear which factors are decisive for the agonistic effect and which are for the antagonistic effect.
A generally applicable and successful method recently has been the development of conformationally restricted peptidomimetics that imitate the receptor-bound conformation of the endogenous peptide ligands as closely as possible (Rizo and Gierasch, Ann. Rev. Biochem., 61:387, 1992). Investigations of these types of analogs show them to have increased resistance toward proteases, that is, an increase in metabolic stability, as well as increased selectivity and thereby fewer side effects (Veber and Friedinger, Trends Neurosci., p. 392, 1985).
Once these peptidomimetic compounds with rigid conformations are produced, the most active structures are selected by studying the conformation-activity relationships. Such conformational constraints can involve short range (local) modifications of structure or long range (global) conformational restraints (for review see Giannis and Kolter, Angew. Chem. Int. Ed. Engl. 32:1244, 1993).

Conformationally constrained backbone cyclized peptide analogs

Yissum Research Development Co. of the Hebrew University