An air conditioner includes: liquid-side indoor expansion valves corresponding to a liquid side of respective indoor heat exchangers; and gas-side indoor expansion valves corresponding to a gas side of the respective indoor heat exchangers. In a case where both a heating-operation indoor heat exchanger and a heating-stopped indoor heat exchanger are present, the controller of the air conditioner controls the liquid-side indoor expansion valve and the gas-side indoor expansion valve corresponding to the heating-stopped indoor heat exchanger such that an opening degree of the gas-side indoor expansion valve becomes smaller than an opening degree of the liquid-side indoor expansion valve.

There has been an air conditioner including a refrigerant circuit and a control unit, the refrigerant circuit being constituted by connecting a compressor, a plurality of indoor heat exchangers that are parallel with each other, liquid-side indoor expansion valves corresponding to a liquid side of the respective indoor heat exchangers, and an outdoor heat exchanger, the control unit performing heating operation in which refrigerant sealed in the refrigerant circuit is circulated in the order of the compressor, the indoor heat exchangers, the indoor expansion valves (hereinafter referred to as "liquid-side indoor expansion valves"), and the outdoor heat exchanger. As such an air conditioner, as described in PTL 1 (Japanese Unexamined Patent Application Publication No. 7-310962), in a case where the plurality of indoor heat exchangers include both a heating-operation indoor heat exchanger that performs heating operation and a heating-stopped indoor heat exchanger that does not perform heating operation, in order to suppress accumulation of refrigerant in the heating-stopped indoor heat exchanger, the liquid-side indoor expansion valve corresponding to the heating-stopped indoor heat exchanger is controlled to be slightly open so that a small amount of refrigerant flows into the heating-stopped indoor heat exchanger. Alternatively, instead of controlling the liquid-side indoor expansion valve to be slightly open, an expansion mechanism (formed by using a capillary tube and a check valve) that bypasses the liquid-side indoor expansion valve is provided so that a small amount of refrigerant flows into the heating-stopped indoor heat exchanger through the expansion mechanism in a state where the liquid-side indoor expansion valve is closed.


Linear actuators (also known as an inchworm actuator) including a magnetically actuatable shape memory alloy (SMA) are described. The linear actuators include a bar and an actuator assembly, configured to achieve a linear displacement of the actuator assembly relative to the bar. A hybrid magnetic trigger including an electromagnet and a permanent magnet is used to selectively attract the magnetically actuatable SMA toward the magnetic trigger. The motion of the magnetically actuatable SMA can be converted to a linear displacement. The magnetically actuatable SMA can be implemented using a SMA exhibiting both ferromagnetic and SMA properties, or by a ferromagnetic mass coupled with an SMA (i.e., a ferromagnetic SMA composite). Linear actuators including bars incorporating a ratchet mechanism, and featureless bars are described. A hydraulic system incorporating actuators including magnetically actuatable SMA membranes is also disclosed.

Actuators are relatively simple mechanical components that are often incorporated into more complex mechanical systems, including those found in automobiles, airplanes, manufacturing facilities, and processing facilities. A conventional solenoid is one example of an actuator that has found broad application across many types of industries and technologies.
Shape memory alloys (SMAs) are metals that exist in two distinct solid phases, referred to as Martensite and Austenite. Martensite is relatively soft and easily deformed, whereas Austenite is relatively stronger and less easily deformed. SMAs can be induced to change phase by changes in temperature and changes in mechanical stress. SMAs can generate relatively large forces (when resistance is encountered during their phase transformation), and can exhibit relatively large movements as they recover from large strains. SMAs have been used commercially in many types of actuators, where a temperature change is used to control the actuation cycle. One of the most widely recognizable applications has been the use of SMA based actuators in automatic sprinkler systems.
One disadvantage of SMA actuators triggered by changes in temperature is that, depending upon the application, a heating or cooling device may need to be incorporated into the actuator, increasing the size, expense, and complexity of the actuator. Further, the response of such an actuator depends on heat transfer, which can occur too slowly for certain applications. Material scientists have more recently recognized that the phase change between Martensite and Austenite can be induced by changes in an applied magnetic field in certain alloys, as well as by changes in temperature and stress loading. Because magnetic fields generated with electromagnets can be rapidly switched on and off, particularly as compared to the time required to induce a change in temperature to initiate an actuation, electromagnetically controlled SMA based actuators appear to offer promise in applications where rapidly responding actuation is required. Such alloys are referred to as ferromagnetic shape memory alloys (FSMAs).
One such type of FSMA is an alloy of iron and palladium (FePd). Unfortunately, the cost of palladium is so prohibitive that commercial utilization of FePd-based actuators is not now economically feasible. In an attempt to identify other materials that could be of use in FSMA actuators, composites of a ferromagnetic material and a SMA alloy that itself is not ferromagnetic have been suggested. Because of the widespread utility of actuators, it would be desirable to develop different embodiments of actuators incorporating FSMAs (or composite FSMAs) that will likely have commercial value.

Actuators based on ferromagnetic shape memory alloy composites


The present invention is a foot operated control device that provides variable control by means of a single foot pedal. The foot operated control device can be locked to allow continuous unattended operation. The foot pedal can be flipped into an upper position, for example into a cabinet. In a preferred embodiment of the invention, the foot operated control device comprises a foot operated faucet.

This invention relates to control devices in general, and in particular to foot operated control devices.
Foot controlled faucets per se have been known in the art for some time. However, there has been a longstanding need for a practical foot controlled faucet that can provide variable foot control of both the volume of water flow and the mix of hot and cold water and can be locked to provide continuous unattended operation.


A transmission apparatus comprising a wave actuator having a wave-actuating disk mounted on an eccentric body through a rolling bearing; an oscillatory roller gear having Zh number of oscillatory rollers assembled in Zh radial slots of an oscillatory roller carrier, and a stationary gear with Zg number of inner teeth, where Zg=Zh.+-.1. The wave actuator pushes the oscillatory rollers to move radially. The oscillatory rollers roll along the inner surface of the stationary gear, driving the oscillatory roller carrier to rotate, thereby transmitting movement and power. Any one of the three components: the wave actuator, the oscillatory roller gear, and the stationary gear, can be chosen as a fixed component; the other two then form a speed-reducing or a speed-increasing transmission. When none of the components are fixed, they form a two-in/one-out differential transmission.

1. Field of the Invention
This present invention relates to a transmission apparatus, more particularly, to a transmission apparatus that employs gears having movable gear teeth. This type of device can be used for a broad range of applications, which require motion and power to be transmitted continuously from an input element to an output element with a predetermined velocity ratio.
2. Description of the Related Art
There are known mechanical power transmission devices comprise gears having a plurality of movable gear teeth that mesh with stationary gears, such as U.S. Pat. No. 4,798,104, Chinese patent No.CN85,101,702A, Chinese patent No.CN86,200,768U, and Russian patent No.SU-1,307,129. Since sliding occurs between moving pairs among the wave generators, the movable gear teeth and their carriers, and the stationary gears, these types of devices have low transmission efficiency and high wear.
Sliding also occurs in the variable speed transmission apparatus of U.S. Pat. No. 4,856,378 because the rollers can only rotate with either the eccentric cam or the stationary gear but not both at the same time. This type of device has limited transmission ratios and loading capacity since the number of inner teeth of the stationary gear is two less than that of the rollers of the special gear, so that only a few gear teeth are engaged at any time. Furthermore, because the eccentricity of the extendable cam varies, the transmission ratio is not constant. Similarly, the loading capacity and transmission ratio of U.S. Pat. No. 3,468,175 are also limited because it requires the number of the movable gear teeth to be a harmonic of the number of the casing teeth. In addition, this design requires complicated movable gear teeth comprising five different rollers.
U.S. Pat. No. 4,713,985 provides a pure rolling-style transmission. However, the connecting elements on the carrier disk not only reduce the number of driving rollers but also increase their size. This type of transmission device has limited loading capacity because it has less engaged gear teeth. It also has limited transmission ratio because fewer driving rollers can be arranged on the carrier disk. Furthermore, the asymmetrical gear tooth profile of the casing and the structure of the connecting elements make this transmission suitable only for rotating in the pulling direction of the connecting elements.
In Chinese patent No.CN1,020,383C one of the present inventors Zhi Chen proposes an oscillatory tooth transmission which eliminates sliding from all relative moving pairs. As it is shown by FIG. 10, the oscillatory tooth gear comprises two gear tooth carriers, staggered at a half pitch of a gear tooth, and connected by a plurality of screws. Holding a row of oscillatory teeth, each gear tooth carrier comprises a force-transmitting disk 23 and an oscillatory tooth disk 22. This arrangement is difficult to produce and subject to assembly error. In addition, the oscillatory gear carrier has limited strength and stiffness.


Apparatus, systems and methods for plasma etching substrates are provided. The invention achieves dissipation of charge build-up on a substrate being plasma etched to avoid notching or twisting in high aspect ratio contents and similar features.

Higher performance, lower cost, increased miniaturization of electronic components, and greater density of integrated circuits are ongoing goals of the computer industry. One commonly used technique to increase the density of integrated circuits involves stacking of multiple layers of active and passive components one atop another to allow for multilevel electrical interconnection between devices formed on each of these layers. This multilevel electrical interconnection is generally achieved with a plurality of metal-filled vias ("contacts") extending through dielectric layers which separate the component layers from one another. These vias are generally formed by etching through each dielectric layer by etching methods known in the industry, such as plasma etching. Plasma etching is also used in the forming of a variety of features for the electronic components of integrated circuits.
As described in U.S. Pat. No. 6,544,895, incorporated herein by reference, in plasma etching, a glow discharge is used to produce reactive species, such as atoms, radicals, and/or ions, from relatively inert gas molecules in a bulk gas, such as a fluorinated gas, such as CF4, CHF3, C2F6, CH2 F2, SF6, or other freons, and mixtures thereof, in combination with a carrier gas, such as Ar, He, Ne, Kr, O2, or mixtures thereof. Essentially, in a plasma etching process comprises: 1) reactive species are generated in a plasma from the bulk gas, 2) the reactive species diffuse to a surface of a material being etched, 3) the reactive species are absorbed on the surface of the material being etched, 4) a chemical reaction occurs which results in the formation of a volatile by-product, 5) the by-product is desorbed from the surface of the material being etched, and 6) the desorbed by-product diffuses into the bulk gas.
In a plasma etching chamber for semiconductor manufacturing, a plasma is maintained by coupling energy from a power source into the plasma, which comprises mobile, positively and negatively charged particles. An electric field, or bias voltage, develops in a sheath layer around the plasma, accelerating the ions toward the semiconductor substrate by electrostatic coupling. Applying an oscillating bias power can modulate the potential difference between the plasma and the semiconductor substrate. The difference between the instantaneous plasma potential and the surface potential defines the sheath potential drop. During the positive voltage phase, the substrate collects electron current from electrons that have enough energy to cross the sheath while during the negative voltage phase, positive ions are accelerated by the sheath voltage drop, strike the substrate, and are collected by the substrate.
However, plasma etching processes (as well as ion implantation and other charge beam processes) may damage the semiconductor substrate and the devices and circuits formed therein or thereon. In particular, electrical charging is a well-known problem that can occur during the plasma processing of semiconductor devices, leading to the degradation of the device performance.
Illustrated in drawing FIG. 6 is the phenomenon of electrical charging on a semiconductor device in the process of a plasma etch. A material layer 244 to be etched is shown layered over a semiconductor substrate 242. A patterned photoresist layer 246 is provided on the material layer 244 for the etching of a via. During the plasma etching process, the patterned photoresist layer 246 and material layer 244 are bombarded with positively charged ions 248 and negatively charged electrons 252 (i.e., the reactive species). This bombardment results in a charge distribution being developed on the patterned photoresist layer 246 and/or the semiconductor substrate 242. This charge distribution is commonly called "feature charging."
In order for feature charging to occur, the positively charged ions 248 and the negatively charged electrons 252 must become separated from one another. The positively charged ions 248 and negatively charged electrons 252 become separated by virtue of the structure being etched. As the structure (in this example a via 254) is formed by etching, the aspect ratio (height-to-width ratio) becomes greater and greater. During plasma etching, the positively charged ions 248 are accelerated (e.g., as a result of a DC bias at the semiconductor substrate 242) toward the patterned photoresist layer 246 and the material layer 244 in a relatively perpendicular manner, as illustrated by the arrows adjacent positively charged ions 248. The negatively charged electrons 252, however, are less affected by the DC bias at the semiconductor substrate 242 and, thus, move in a more random isotropic manner, as depicted by the arrows adjacent negatively charged electrons 252. This results in an accumulation of a positive charge at a bottom 256 of via 254 because, on average, positively charged ions 248 are more likely to travel vertically toward the substrate 208 than are negatively charged electrons 252. Thus, any structure with a high enough aspect ratio tends to charge more negatively at photoresist layer 246 and an upper portion of the material layer 244 to a distance A (i.e., illustrated with "−" indica) and more positively at the via bottom 256 and the sidewalls 258 of the via 254 proximate the via bottom 256 (i.e., illustrated with "+" indica).
As shown in drawing FIG. 7, the positively charged via bottom 256 deflects the positively charged ions 248 away from the via bottom 256 and toward the sidewalls 258 of the via 254, as a result of charge repulsion. The deflection results in an etching of the sidewalls 258 proximate the via bottom 256, known as "notching" or "twisting." Furthermore, the presence of the positively charged via bottom 256 slows the positively charged ions 248 as they approach the positively charged via bottom 256, thereby reducing etching efficiency.
Current High Aspect Ratio Contacts (HARCs) are known to twist at aspect ratios greater than about 20:1. Twisting is the deviation of the bottom of the contact from the center line of the etch front. Twisting is caused by asymmetric charge build-up in and around the contact causing a lateral deviation of the ion projectory. The twisting may be so serious that the etch processes actually generate corkscrew shaped contacts. The twisting of the contact is a concern for shorting contacts to other structures or to each other. Certain tools and chemistries help reduce the twisting, but all tools show this phenomenon.
Twisting is a current failure mechanism for contacts on 95 nm parts and has required extensive process development to overcome. HARC etches are probably the most difficult etch needed on DRAM parts and have very tight constraints on profiles, film selectivities, and Critical Dimensions (CDs). The twisting behavior of contacts will limit the aspect ratio of contacts that can be etched in the near future and there is little research to understand this phenomena and no known solution to eliminate it.
In a standard plasma etch system the ion angular distribution is very anisotropic whereas the electron angular distribution is very isotropic. For HARC features the electrons will mainly strike the contact near the top of the feature; while ions will reach the bottom of the feature. This is what causes the top of the contacts to charge negative while the bottom of the contacts charge positive. Small asymmetries in the top of the contacts due to photolithography or polymer loading will cause asymmetric charging at the top of the contact leading to bending of the incident ions. This will then cause the contact to etch faster on one side of the contact due to increased ion flux to this area.

Using positive DC offset of bias RF to neutralize charge build-up of etch features

Abstract: Charge build-up on a substrate being etched by plasma etching can be dissipated by a method for etching a substrate, the method comprising: providing a plasma processing chamber comprising a chamber enclosure and a substrate support adapted to support a substrate within the chamber enclosure; supporting a substrate on the substrate support; forming a plasma within the chamber enclosure such that a surface of the substrate is in contact with the plasma; etching the substrate by generating a negative bias on the substrate surface relative to the plasma; and intermittently changing the bias on the substrate surface to positive relative to the plasma. The present method can be readily integrated into known plasma processing systems.


An example computer-implemented method of providing security for a software container includes discovering credentials that a software container is expected to use at runtime. The discovering is performed prior to instantiation of the software container from a container image, and is based on one or more of credentials stored in the container image, credentials stored in runtime configuration data for the software container, and credentials from a secrets management service. An unsafe credential set is determined that includes one or more of the discovered credentials that do not meet predefined credential safety criteria. A runtime request is intercepted from the software container. A credential violation is detected based on the intercepted runtime request attempting to use a credential from the unsafe discovered credential set. A corrective action is performed for the software container based on the detected credential violation.

This application relates to software containers, and more particularly to credential safety management for software containers.
Virtual machines have gained popularity for a variety of computing tasks. A virtual machine is a software implementation of a physical machine that executes programs like a physical machine. A typical virtual machine includes an entire additional operating system that runs on top of a host operating system, and one or more applications that run within that additional operating system. Virtual machines enable administrators to run several operating system instances at the same time on a single server. A specialized application called a hypervisor manages the virtual machines that run on a given server. Running multiple operating system instances on a single physical machine, however, is resource-intensive.
More recently, software containers are being used as an alternative to running multiple virtual machines. Software containers allow administrators to virtualize a single application, or group of applications, without requiring virtualization of an entire operating system. A software container includes a software application plus dependencies required to run the application bundled into one package. These files are stored in a container image, and a software container is instantiated from the container image at runtime. The dependencies may include libraries, binaries, and/or configuration files, for example. By containerizing the application and its dependencies, differences in operating system distributions and underlying infrastructure are abstracted away, making it easy to migrate an application between various environments (e.g., development, testing, and production).
Multiple software containers can be run in isolation from each other on a single host operating system, which provides an alternative to running multiple virtual machines and their accompanying operating systems on a single server. Because software containers allow an administrator to virtualize a single application without requiring virtualization of an entire operating system, running a given quantity of software containers is less resource intensive than running the same quantity of virtual machines. One platform for building and running software containers is DOCKER.
Software containers may use credentials such as passwords during operation. It is undesirable for a container to use unsafe credentials that can be easily guessed or discovered by a third party.

This patent is subject to a terminal disclaimer.

Credential safety management for software containers


A piezoelectric/electrostrictive element is disclosed which includes a ceramic substrate formed principally of partially or fully stabilized zirconia, a lower electrode formed on the ceramic substrate, a piezoelectric/electrostrictive layer formed on the lower electrode, and an upper electrode formed on the piezoelectric/electrostrictive layer. The element further includes an auxiliary electrode formed on the ceramic substrate, apart from the lower electrode, such that a portion of the auxiliary electrode is located between the piezoelectric/electrostrictive layer and the ceramic substrate. The auxiliary electrode is formed of an electrically conductive material which permits sufficiently good adhesion of the auxiliary electrode to the ceramic substrate and the piezoelectric/electrostrictive layer. The upper electrode extends between and is electrically connected to the piezoelectric/electrostrictive layer and the auxiliary electrode.

1. Field of the Invention
The present invention relates to a uni-morph, bi-morph or other types of piezoelectric or electrostrictive elements which undergo displacement in the form of bending, deflection or flexure and which can be used for ink jet print heads, microphones, sounding bodies (such as loudspeakers), various resonators or vibrators, sensors, and other components or devices. The term "element" used herein is interpreted to mean an element capable of transducing or converting an electric energy into a mechanical energy, e.g., mechanical force, displacement, strain or vibrations, or transducing such a mechanical energy into an electric energy.
2. Discussion of the Related Art
In the recent years, in the fields of optics and precision positioning or machining operations, for example, there have been widely used and increasingly demanded an element whose displacement can be controlled for adjusting or controlling an optical path length or the position of a member or component of a device, on the order of fractions of a micron (.mu.m), and a detecting element adapted to detect infinitesimal displacement of a subject as an electric change. To meet this need, there have been developed various piezoelectric or electrostrictive elements utilizing the reverse or converse piezoelectric effect or electrostrictive effect in which a piezoelectric or electrostrictive material produces a mechanical displacement upon application of a voltage or electric field thereto, or the piezoelectric effect in which the piezoelectric material produces a voltage or electric field upon application of pressure or mechanical stress. Recently, there are increasing requirements for further improved capability and operating reliability of the piezoelectric/electrostrictive elements.
The piezoelectric or electrostrictive element of the uni-morph or bi-morph type is carried by a substrate in the form of a plate, which functions as an oscillator or transducer plate. For assuring sufficient amount and force of bending or flexural displacement of the substrate or plate, it is important to reduce the thickness of the substrate, on the one hand.
On the other hand, however, the reduction in the substrate thickness undesirably results in a decrease in the mechanical strength of the substrate. In addition, the piezoelectric or electrostrictive element of the conventional uni-morph or bi-morph type is unsatisfactory in its operating reliability since the element consists of mutually superposed plate-like members including a piezoelectric/electrostrictive plate, which members are bonded to each other by means of adhesives, for example.
In view of the above problems, the inventors of the present invention developed a piezoelectric/electrostrictive element as disclosed in co-pending U.S. patent application Ser. No. 07/912,920, which includes a ceramic substrate formed principally of zirconia whose crystal phase is partially or fully stabilized. On this ceramic substrate are formed in lamination a lower electrode, a piezoelectric/electrostrictive layer and an upper electrode, by a suitable film-forming technique. The piezoelectric/electrostrictive layer is formed of a piezoelectric/electrostrictive material having a composite perovskite structure which contains lead element.
The piezoelectric/electrostrictive element as described just above can be formed with a significantly reduced thickness as compared with the conventional counterpart, and is therefore able to produce a relatively large amount of displacement by application of a relatively low voltage thereto, with a sufficiently large magnitude of force or electric potential generated, assuring an improved operating response. Further, the use of the ceramic substrate formed principally of partially or fully stabilized zirconia leads to a significantly increased mechanical strength of the element.
In the piezoelectric/electrostrictive element of the above type, it is desirable that electrical lead portions of the lower and upper electrodes are both formed on the ceramic substrate, so as to facilitate electrical connection of the electrodes with an outside electric circuit. One considered example, such a desirable piezoelectric/electrostrictive element is constructed such that an upper electrode 6 is formed on a piezoelectric/electrostrictive layer 4 formed on a ceramic substrate 2, with an electrical lead portion of the electrode 6 formed on the substrate 2, as shown in FIG. 6, wherein reference numeral 8 denotes a lower electrode whose lead portion is also formed on the substrate 2.
However, it is difficult for this type of element to assure a sufficiently great bonding strength between the piezoelectric/electrostrictive layer 4 and the ceramic substrate 2, since desired piezoelectric/electrostrictive characteristics of the layer 4 can be maintained by restraining or reducing the chemical reaction between the layer 4 and the substrate 2. Also, the piezoelectric/electrostrictive layer 4 should not be bonded or joined to the ceramic substrate 2 in terms of the mechanism of displacement or deformation of the element.
If the upper electrode 6 is formed to extend between the piezoelectric/electrostrictive layer 4 and ceramic substrate 2 which are not joined together, the upper electrode 6 tends to be disconnected at the interface between the ceramic substrate 2 and the layer 4, due to heat, mechanical shock, vibrations and the like which may occur during manufacture or use of the element. This makes it difficult for the element to assure sufficiently high operating reliability.
To deal with the above problem, it is proposed to provide a coating layer made of resin, for example, at the interface between the substrate 2 and the piezoelectric/electrostrictive layer 4. However, this method was found unsatisfactory to solve the above problem.

Piezoelectric/electrostrictive element having auxiliary electrode disposed between piezoelectric/electrostrictive layer and substrate


A technique for forming 3D structures is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for forming 3D structures. The method may comprise providing a substrate comprising at least two vertically extending fins that are spaced apart from one another to define a trench; depositing a dielectric material in the trench between the at least two vertically extending fins; providing an etch stop layer within the dielectric material, the etch stop layer having a first side and a second opposite side; removing the dielectric material near the first side of the etch stop layer.

In response to an increased need for smaller electronic devices with denser circuits, devices with three dimensional (3D) structures have been developed. An example of such devices includes FinFETs having conductive fin-like structures that are raised vertically above the horizontally extending substrate. Referring to FIG. 1a, there is shown a perspective view of a conventional FinFET 100 formed on a substrate 102. The substrate 102 may comprise, for example, a semiconducting substrate, or silicon-on-insulator. In one example, the substrate 102 may comprise a semiconducting substrate 102a and an oxide layer 102b disposed on the semiconducting substrate 102a. FinFET 100 may also comprise a source region 112 and drain region 114 that are connected to one another by a fin structure 116 serving as the channels. For convenience, FIG. 1a shows FinFET device 100 with only two fin structures 116. However, those of ordinary skill in the art will recognize that other FinFET devices may contain a single fin structure, or three or more fin structures. The conventional FinFET device 100 may also include a gate structure 122 formed across the fin structures 116, and a gate dielectric 124 that electrically isolates the gate structure 122 from the fin structure 116. In the conventional FinFET device 100, the surface area of the fin structure 116 in contact with gate dielectric 124 may be the effective channel region. Referring to FIG. 1b, there is shown a cross sectional view of the FinFET 100 shown in FIG. 1a. For convenience, the source region 112 and the drain region 114 are omitted from the figure. As illustrated, the fin structures 116 may extend vertically from the substrate 102. In another example, the fin structures may be disposed above the oxide layer so that it is electrically isolated from the semiconducting substrate.
Referring to FIG. 2a-2f, there is shown a conventional method for manufacturing FinFET device 100 having fin structures 116 shown in FIG. 1. As illustrated in FIG. 2a, a substrate 202 such as a silicon wafer may be provided. On the substrate 202, a layer of hardmask 204 is formed (FIG. 2b). Thereafter, a layer of photoresist may be deposited onto the hardmask 204. After depositing the resist, the photoresist may be patterned. As known in the art, various methods including photolithography may be used to pattern the photoresist 206. Thereafter, the pattern of the resist 206 may be transferred onto the hardmask 204 and a portion of the substrate 202 via an etching process. The resulting structure may include the patterned hardmask 204 and fin structure 210 corresponding to the pattern of the photoresist 206, as illustrated in FIG. 2c. Those skilled in the art will recognize that the fins structures 210 formed in this process may be the fin structure 116 shown in FIGS. 1a and 1b. An oxide layer 220, such as SiO2, may be deposited on the substrate, as shown in FIG. 2d. Thereafter, a chemical-mechanical polishing/planarization (CMP) process may be performed to planarize the resulting structure (FIG. 2e). As illustrated in FIG. 2e, the CMP process may be performed until either the patterned hardmask 204 or the fin structure 210 is exposed. After the CMP process, a wet or dry etching process may performed to remove a portion of the oxide layer 210 until the sidewalls of the fin structures 210 are exposed (FIG. 2f). The structure that may be formed after the etching process may include a substrate 202, the oxide layer 220, and one or more fin structures 210 extending above the oxide layer 220.
The above process, although adequate, contains several shortcomings. One of such shortcomings may found in the uniformity of oxide layer 220 and the fin structures 210. In particular, the etching process used to expose the fin structures 210 may be a non-uniform process with non-uniform etch rate across the substrate 202. The oxide layer 220 in one part of the substrate 202 may be etched at a greater rate compared to the other parts of the substrate 202. Accordingly, the oxide layer 220, with varying thickness, may form.
In addition, the fin structures 210 in one part of the substrate 202 may be exposed before fin structures 210 in other parts of the substrate 202. Moreover, the fin structures 210 exposed earlier part of the etch process may be exposed to etchants for longer period of time. Ultimately, the fin structures 210 with non-uniform widths and heights may form across the substrate 202. Other processes including CMP process may also contribute to a non-uniform oxide layer 220 and fin structures 210. Moreover, the etching process used to expose the fin structures 210 is a timed etching process with a great number of variables. A slight variation in the etching process may result in reduced repeatability or increased substrate-to-substrate non-uniformity. The fin structures 210 on different substrates 202 may have different height and/or width. As the performance of the FinFET devices may be influenced by the properties of the fin structures 210, it may be desirable to form more uniform fin structures 210. As such, uniformity and repeatability of the process used to form the fin structures are highly desirable.
Further, if a wet etching process is used to expose the fin structure 210, a phenomenon such as corner rounding 211 may occur. Such a phenomenon may contribute to less than optimal performance of the FinFET devices.
Accordingly, a new method for forming the fin structure is needed.

Varian Semiconductor Equipment Associates, Inc.


A power semiconductor module having an increased reliability against thermal fatigue includes a power semiconductor element, a lower-side electrode connected to the lower side of the element, a first insulating substrate connected to the upper side of the lower-side electrode and having metallic foils bonded on both surfaces thereof, an upper-side electrode connected to the upper side of the power semiconductor element, a second insulating substrate connected to the upper side of the upper-side electrode and having metallic foils bonded on both surfaces thereof, a first heat spreader connected to the lower side of the first insulating substrate, and a second heat spreader connected to the upper side of the second insulating substrate. The power semiconductor element and the first and second insulating substrates are sealed with a resin.

The present invention relates to a power semiconductor module.
In order to make a power semiconductor module compact in size, it is necessary to minimize the size of a power semiconductor element or a cooling mechanism. For the miniaturization of the power semiconductor element, the element is required to reduce its loss. For the miniaturization of the cooling mechanism, it is effective to enable the element to be used at high temperatures. However, since the miniaturization involves an increase in heat generation density, more efficient cooling is required. The use of the element at high temperatures requires a reliability as high as endurable to thermal fatigue. JP-A-2003-17658 (Patent Document 1) discloses a structure wherein insulating substrates are provided each on the upper and lower surfaces of a power semiconductor, and heat sinks are provided at both sides of the semiconductor to cool the semiconductor from its upper and lower sides (refer to FIGS. 5 and 6, Paragraphs (0049)-(0056)).


Provided is a touch panel. The touch panel includes a base and a pressure-sensitive adhesive layer attached to the base and including an acryl-based polymer containing an acryl polymer containing 5 to 30 parts by weight of isobornyl (meth)acrylate, and 5 to 40 parts by weight of methyl (meth)acrylate in a polymerized form. Accordingly, it can effectively inhibit penetration of oxygen, moisture or other impurities at an interface between the base and the pressure-sensitive adhesive layer, or at an interface between a conductor thin film and the pressure-sensitive adhesive layer, and prevent degradation in optical properties such as visibility, etc. due to bubbles generated at the pressure-sensitive adhesive interface. In addition, when the pressure-sensitive adhesive layer is directly attached to the conductor thin film and even exposed to severe conditions such as high temperature or high temperature and high humidity, a change in the resistance of the conductor thin film may be effectively inhibited, and thus the touch panel can be stably driven for a long time.

1. Field of the Invention
The present invention relates to a touch panel, a pressure-sensitive adhesive composition for a touch panel, a double-sided pressure-sensitive adhesive tape using the same, and a method of preparing a pressure-sensitive adhesive composition for a touch panel.
2. Discussion of Related Art
A touch panel or touch screen is applied to various data processing terminals such as a mobile communication terminal or ATM, or displays such as a TV or monitor. In addition, as the touch panel is increasingly applied to compact portable electronic devices, the demand for a more compact and lighter touch panel or screen is increasing.
To configure the touch panel or screen, a pressure-sensitive adhesive is used. Such a pressure-sensitive adhesive should maintain transparency under severe conditions such as high temperature or high temperature and high humidity, have high peel strength, and inhibit lift-off and peeling. In addition, it is required that the pressure-sensitive adhesive effectively inhibits bubble generation which becomes a more frequent problem when a plastic film is used as a base.
Moreover, according to the structure of a touch panel or touch screen, when a pressure-sensitive adhesive is directly adhered to a conductor thin film such as an indium tin oxide (ITO) thin film, the pressure-sensitive adhesive also needs to have a characteristic of inhibiting a change in the resistance of a conductor thin film to stably drive the panel even when being used for a long time.


This invention is to enable appropriate routing based on transition prediction of network traffic. This routing control method includes: reading out predicted utilization transition data (e.g. utilization rate, or utilized bandwidth) associated with a received connection set-up request from a predicted utilization transition data storage storing said predicted utilization transition data for each resource (e.g. links between routers, or server) in a network in future; and selecting a resource satisfying a predetermined condition based on the read predicted utilization transition data. Thus, by using said predicted utilization transition data, an appropriate resource is identified in accordance with future time transition of the resource utilization rate, for example, and thereby, appropriate routing is possible. For example, when a link that a traffic volume will increase after a predetermined time exists, it is possible to judge that such a link is not used even when there are a lot of available bandwidths now.

In today's situation where various crimes using a network such as a DDoS attack, hacking, and the like are increasing and the problem is becoming increasingly serious, there is a growing need for information security. Focusing on that traffic characteristics change during a DDoS attack, hacking, or the like, many researches are being conducted on methods of detecting abnormalities by observing network traffic. For example, refer to "Technical Research on High-traffic Observation and Analysis Method (Information Security Guard R&D Evaluation Services)" in 15 Jokei No. 1632, April/2004, Information-technology Promotion Agency (IPA).
More specifically, according to the result of analyzing 12 representative attack cases, it is found that a delay in the DNS request increases by 230% and a delay in the web access also increases by 30% in the presence of malicious traffic. For example, refer to Kun-chan Lan, Alefiya Hussain and Debojyoti Dutta, "The effect of malicious traffic on the network" in proceeding of PAM, Apr. 6-8, 2003, La Jolla.
In addition, as a network-based anomaly detection, "Review of Anomaly-based Network Intrusion Detection, Jonathan Werrett, 2003/05/26" discloses an approach as described below. Specifically, as a probability-based approach, the probability of a possible value in a packet field is estimated and a packet including a field having a value of the low probability or a new value is tagged as "anomalous" and thereby detected as an unauthorized access. Moreover, as a multivariate approach, a lot of variables such as the number of packets, the number of sessions per unit time, and the like are used as inputs and the probabilities of the variables are estimated to detect the unauthorized accesses. Furthermore, as a state-based approach, sessions are reconstructed and state transitions of protocols, Internet Protocol (IP), and sessions are detected as probabilities to detect the unauthorized accesses. A normal session begins with SYN and ends with FIN. Therefore, a case including any different condition is tagged as "anomalous."
Furthermore, for the network administrative department in a communications carrier or an Internet Service Provider (ISP), it is an indispensable element of nonstop operation to detect a network failure at an early stage. Thus, a study is being conducted on a mechanism for deducing the cause of the network failure from a phenomenon specific to the cause of the failure.
In addition, as for the traffic engineering (TE), it has conventionally been studied to select an optimal path according to the current situation related to the load on a network or a server. The current situation related to the load on a network or a server is one of network contexts.
A certain concept of TE is based on maximizing the network performance by utilizing a planar expanse of a network in order to select a path. As for information on this concept, refer to, for example, D. Awduche, et al., "Overview and principles of Internet traffic engineering," RFC3272, IETF, May 2002, M. Katoh, T. Soumiya, K. Nakamichi, K. Takashima, H. Yamada and A. Chugo, "A study of IP traffic engineering mechanisms," ITG2002, Duisburg, Germany, March 2002, A. Okamura, K. Nakamichi, H. Yamada and A. Chugo. "A QoS Control Method Cooperating with a Dynamic Balancing Mechanism," APNOMS2003, Japan, September 2003, Hitoshi Yamada, Akiko Okamura, Akira Chugo and Masafumi Katoh, "IP Network Control Architecture for Providing On-Demand QoS Guarantee Service," WTC2004 (Sep. 11-16, 2004), and so forth.
Specifically, even if congestion or a failure occurs in a certain place on the network, the network service performance is maintained by dynamically bypassing the traffic toward another place. Moreover, when selecting a path or a server to ensure network resources for QoS guarantee, the resources to be ensured are equally dispersed. This enables an increase in the number of acceptable requests and maximizing the network performance. It means an increase in the probability of request acceptance without a call loss for a user and an increase in the service charge income for a network service provider. Moreover, because it is a basic principle of the two-dimensional TE to use the network completely, it can be said to be a technique to avoid a useless investment such as installing new equipments to cope with an instantaneous lack of resources.
The concept of the two-dimensional TE utilizing the planar expanse of the network can be expanded into the three-dimensional TE utilizing a spatial expanse of the network. Generalized Multi-protocol Label Switching (GMPLS) aims to integrally control and manage various layer paths including an optical wavelength path, a time division multiplexing (TDM) path, and a multi-protocol label switching (MPLS) path. Therefore, when the traffic volume in an MPLS network increases in the long term and the capacity of the entire network is insufficient, the two-dimensional TE reaches critical limit. When another optical wavelength plane is used anew on such an occasion as this, it becomes possible to absorb the traffic volume expected to overflow, thereby further improving the robustness and availability of the network by means of optimal path finding and traffic dispersion with consideration given to a plurality of wavelength planes. As for these techniques, refer to Toshio Soumiya, Shinya Kano, Akira Chugo and Masafumi katoh, "Robust and Efficient Control Method for Multilayered GMPLS Networks," WTC2004 (Sep. 11-16, 2004), Chung-Fong Su and Hung-Ying Tyan, "Multi-layer Traffic Engineering for OPEX Reduction in IP over WDM Networks," WTC2004 (Sep. 11-16, 2004), and so forth.
Moreover, recently, public attention is focused on a Contextware service control for dynamically changing a method of providing a service according to the user's situation. For example, refer to Masafumi Katoh, "Ubiquitous Network Strategy—Utilization of Knowledge using Network and Middleware—", [online], Jun. 24, 2004, Ubiquitous Networking Forum, Ubiquitous Strategy Symposium, Internet <URL:http://www.ubiquitous-forum.jp/documents/sympo20040624/index.html>, and so forth.
Moreover, there has already been suggested that technical know-how and knowledge (i.e. network context) obtained through network operations are utilized by reflecting them on the network controls. As for the detailed information, refer to Kazuo Imai, "Fourth Generation Mobile Network and Expansion to Ubiquitous Network," [online], Jul. 20, 2004, The Institute of Electronics, Information and Communication Engineers (IEICE) Technical Committee on Ubiquitous and Real-World Oriented Networking (URON), Internet <URL: http://www.ieice.org/cs/uron/workshop2004.html> and so forth.
Moreover, there has been suggested a network control method including deducing a user's intention from the user's situation, setting requirements to the network while referring to a user profile, and searching for an optimal path by using a network context while referring to the policy of a service provider and the policy of a network operator.
Moreover, JP-A-2000-253055 discloses a path control method having a low incidence of call loss and a low load on a network. Specifically, it includes carrying out a routing by a routing table search when a resource reservation request occurs and causing an application to generate information concerning a call duration, storing the information into the resource reservation request packet and causing respective nodes to transfer the packet, predicting changes in the bandwidth capacity on the network from the information concerning the call duration in the respective nodes, and reflecting the information on the routing at the time of the resource reservation. However, the technique of this publication causes the application itself using the network to inform the call duration and predicts changes in the bandwidth capacity on the network, which includes the call, on the basis of the information. Therefore, consideration can be made for only bandwidth changes within holding time from the actual occurrence of the call to a time when the call will disappear, however, this technique is not intended to predict a future traffic transition before the occurrence of the call. Granted that the network resources are optimized on the basis of this prediction, only the short-time transition is considered. Therefore, this technique has a limit on improving resource efficiencies by optimization. Moreover, the publication does not mention any method of using the prediction for optimizing the network resources.
Originally, much knowledge exists on networks. For example, a study is being conducted of finding out information leakage by viewing information concerning an upper layer such as an e-mail title or the content of the e-mail. In the present application, however, it is assumed to use knowledge obtained from "an amount of layer 3 packets" and "traffic volume" that can be generally known on networks originally.
Conventionally, empirical knowledge obtained through network operations has been commonly used. For example, the timing for expansion of equipments and facilities is judged from a long-term trend of increased demands. Furthermore, when an occurrence of planning-type congestion caused by an event is anticipated, a cache function is provided near users to reduce the load on the traffic of the core network. Furthermore, at the time of earthquake or other abnormal conditions, blocking of calls is often used. In this manner, various countermeasures are taken through knowledge of experts as human beings. There has not been, however, carried out any routing using knowledge quantitatively and dynamically.
While various researches have been conducted to detect a mixture of trouble or malicious traffic by observing traffic as described above, they are based on the premise of offline analysis and thus are only assumed to be used as a tool only for obtaining a formal knowledge.
Furthermore, like an intrusion detection system (IDS) or an intrusion prevention/protection system (IPS), there are being developed techniques of detecting an unauthorized intrusion from an accidental increase of traffic or from a difference in pattern from the past. Furthermore, there is an example of the reactive control to block the intrusion when it is determined unauthorized. It is, however, limited to controls that are reactive and for use in protecting endpoints. More specifically, it is not adapted to control the entire network in a preventive manner so as to satisfy a certain service criterion by using knowledge accumulated in the network.
Furthermore, while the traffic engineering aims at the efficient use of network resources, the optimum resource allocation is conducted based on the current traffic. More specifically, the knowledge obtained through the past operations is not used and therefore only an instantaneous optimum solution is obtained.
Still further, while the document discussing the contextware service control describes a concept using a network context or a brief information flow, it does not describe how the network context should be collected and be used as a practical matter.

Routing control method, apparatus and system


A method for automatically detecting a plurality of parameters for a NAND-Flash memory. A first step of the method may include generating a plurality of address cycles for the NAND-Flash memory. A second step may set an address number parameter of the parameters based on (i) a first number of the address cycles generated and (ii) a status signal generated by the NAND-Flash memory responsive to the address cycles. A third step generally includes generating at least one read cycle for the NAND-Flash memory after determining the address number parameter. A fourth step may set a page size parameter of the parameters based on (i) a second number of the read cycles generated and (ii) the status signal further responsive to the read cycles.

A NAND-Flash memory is one type of memory used in many different applications. Compared with NOR-Flash memory, the NAND-Flash has advantages of low cost and high capacity. NAND-Flash is widely used in many different applications such as MP3 players, digital cameras and thumb drives. A SmartMedia™ Card has the same signal name and timing with an 8-bit NAND-Flash memory. ("SmartMedia" is a trademark of Toshiba Corporation, Tokyo, Japan.) Usually, a SmartMedia™ card is just a NAND-Flash with a card package. Unlike NOR-Flash or ROM, interface timing at a NAND-Flash is complex. Since the NAND-flash memory does not have explicit address pins, a read access is not straightforward. A series of address and command cycles with proper timing are issued before data can be read out of the NAND-Flash memory. Furthermore, different types of NAND-Flash memories have different number of address cycles and command sequences.
Due to the variable attributes of the NAND-Flash architecture, no clear way exists to read the contents of any particular NAND-Flash memory directly. A central processing unit (CPU) conventionally controls the access cycles to the NAND-Flash memory once the interface parameters are known. Automated detection of the interface parameters for the particular NAND-Flash memory typically involves software or firmware-based solutions executed by the CPU. In another conventional approach, a NAND-Flash device ID can be used to detect the NAND-Flash manufacture and type. Once the manufacture and type are known, the CPU can read the appropriate interface parameters from a database stored in another memory. Therefore, based on the current technology, the CPU cannot be booted directly from NAND-Flash. As a result, additional external ROM or NOR-Flash memory is commonly implemented to boot the CPU so that the CPU can detect or read the NAND-Flash memory interface parameters.
The CPU and the extra memory add to the cost and complexity of the application system. The software or firmware for parameter detection increases a complexity of the application system. Parameter detection is relatively slow. A boot-up speed for the software/firmware-based NAND-Flash boot-up approaches are much slower than a pure hardware-based solution. Furthermore, new NAND-Flash designs cannot be accommodated without changing the software, firmware or database.

Method to detect NAND-flash parameters by hardware automatically


This patent discloses an efficient PWM controller for generating a pulse signal in response to a feedback signal, capable of operating in a normal mode or a green mode, comprising: a capacitor for building a saw-tooth signal by current integration, the saw-tooth signal having a ramp-up period and a ramp-down period; a first composite current source for the ramp-up period, detachable into a first constant current source and a first variable current source; and a second composite current source for the ramp-down period, detachable into a second constant current source and a second variable current source; wherein, the first variable current source is attached to the first constant current source and the second variable current source is attached to the second constant current source respectively in the green mode.

1. Field of the Invention
The present invention relates to a PWM (Pulse Width Modulation) controller, and more particularly to a PWM controller capable of performing power management in power conversion applications.
2. Description of the Related Art
To describe the related art of the present invention, the relation between a PWM controller and a power conversion application shall be introduced first. Please refer to FIG. 1, which shows the architecture of a typical application of PWM controller. As shown in FIG. 1, the architecture realizing a fly-back type power converter, at least includes: a PWM controller 100, an input rectifier and filter 101, a main transformer 102, an output rectifier and filter 103, a feedback network 104, and an NMOS transistor 105.
In the architecture, the PWM controller 100 is used for generating a pulse signal SP in response to a feedback signal VFB.
The input rectifier and filter 101 is used for generating a first DC voltage according to an AC input power source.
The main transformer 102 and the output rectifier and filter 103 are used to transfer the first DC voltage to a DC output voltage VO.
The feedback network 104 is used to generate the feedback signal VFB according to the DC output voltage VO.
The NMOS transistor 105 is used to control the power transformation through the main transformer 102 in response to the pulse signal SP.
Through a periodic on-and-off switching of the NMOS transistor 105, which is driven by the pulse signal SP generated from the PWM controller 100, the input power is transformed through the main transformer 102 to the output. The operating principle of the PWM controller 100 is to be illustrated according to FIG. 2, which shows the circuit diagram of a prior art PWM controller. As shown in FIG. 2, the prior art PWM controller at least includes: a saw-tooth signal generator 200, a trigger generator 201, a latch 202, a NOT gate 203, a NOT gate 204, a reset generator 205 and an output stage 206.
In the circuit, the saw-tooth signal generator 200 is used for generating a saw-tooth signal VSAW in response to an ICKB signal and an ICK signal, and comprises a current source IUP, a switch SWUP, a capacitor CT, a switch SWDN and a current source IDN. When the switch SWUP is on, the current source IUP flowing into the capacitor CT will cause the saw-tooth signal VSAW to ramp up; when the switch SWDN is on, the current source IDN flowing out from the capacitor CT will cause the saw-tooth signal VSAW to ramp down.
The trigger generator 201 is used to generate a pair of trigger signals for the latch 202 according to the comparisons of the saw-tooth signal VSAW to a level VH and a level VL.
The latch 202 is used for generating a CKB signal and a CK signal according to the pair of trigger signals, in which the CKB signal is a complement to the CK signal.
The NOT gate 203 is used to generate the ICKB signal according to the CKB signal; the NOT gate 204 is used to generate the ICK signal according to the CK signal.
The reset generator 205 is used for generating a RESET signal according to a ramp signal VS and a V+ signal which is derived from the feedback signal VFB. When the RESET signal is at low logic level, the pulse signal SP of the output stage 206 will be pulled down to low logic level and the NMOS transistor 105 (shown in FIG. 1) will therefore be turned off.
The output stage 206 is used to generate the pulse signal SP in response to the CK signal and the RESET signal. The timing relation among the saw-tooth signal VSAW, CKB signal, V+ signal, ramp signal VS and pulse signal SP is shown in FIG. 3. As shown in FIG. 3, the ramp-up period and the ramp down period are fixed, so the period of the pulse signal SP is fixed. In this case, the NMOS transistor 105 (shown in FIG. 1) will be switched at a fixed frequency regardless the loading condition of the fly-back type power converter. However, if the loading condition is in light load or in empty load, this design will waste much power and surely does not comply with the energy-saving requirement.
Therefore, there is a demand to provide an efficient PWM controller with adjustable output pulse frequency that can offer flexibility in selecting the pulse frequency according to the loading condition, to manage the power consumption of a power conversion application.


A technique for receiving and transmitting wireless telecommunications through use of a generic architecture is disclosed. The present invention mitigates the complexity of different transceiver operations by allowing a generic architecture to be used in a variety of situations with different channels and different telecommunications standards. An illustrative embodiment of the present invention comprises: receiving uplink analog RF signals at a base station; converting the uplink analog wide-band RF signals into IF uplink digital signals at an analog-to-digital converter; converting the IF uplink digital signals into a number of uplink channels; and demodulating selected narrow-band uplink channels from the total number of narrow-band uplink channels.

The present invention relates to telecommunications in general, and, more particularly, to a technique for using a software-defined transceiver to support wireless telecommunications.
FIG. 1 depicts a schematic diagram of a portion of a typical wireless telecommunications system in the prior art, which system provides wireless telecommunications service to a number of wireless terminals (e.g., wireless terminals 101-1 through 101-3) that are situated within a geographic region. The heart of a typical wireless telecommunications system is Wireless Switching Center (xe2x80x9cWSCxe2x80x9d) 120, which may also be known as a Mobile Switching Center (xe2x80x9cMSCxe2x80x9d) or Mobile Telephone Switching Office (xe2x80x9cMTSOxe2x80x9d). Typically, Wireless Switching Center 120 is connected to a plurality of base stations (e.g., base stations 103-1 through 103-5) that are dispersed throughout the geographic area serviced by the system and to the local and long-distance telephone and data networks (e.g. local-office 130, local-office 138 and toll-office 140). Wireless Switching Center 120 is responsible for, among other things, establishing and maintaining calls between wireless terminals and between a wireless terminal and a wireline terminal (e.g., wireline terminal 150), which is connected to the system via the local and/or long-distance networks.
The geographic region serviced by a wireless telecommunications system is partitioned into a number of spatially distinct areas called xe2x80x9ccells.xe2x80x9d As depicted in FIG. 1, each cell is schematically represented by a hexagon; in practice, however, each cell usually has an irregular shape that depends on the topography of the terrain serviced by the system. Typically, each cell contains a base station, which comprises the radios and antennas that the base station uses to communicate with the wireless terminals in that cell and also comprises the transmission equipment that the base station uses to communicate with Wireless Switching Center 120.
For example, when wireless terminal 101-1 desires to communicate with wireless terminal 101-2, wireless terminal 101-1 transmits the desired information to base station 103-1, which relays the information to Wireless Switching Center 120 over wireline 102-1. Upon receipt of the information, and with the knowledge that it is intended for wireless terminal 101-2, Wireless Switching Center 120 then returns the information back to base station 103-1 over wireline 102-1, which relays the information, via radio, to wireless terminal 101-2.
Wireless terminals 101-1 and 101-2 may, however, operate under different wireless telecommunications standards (e.g., FDMA, TDMA, CDMA, etc.). Such different standards vary in numerous ways, including carrier frequencies, bandwidth, modulation scheme, to name but a few. To enable communication between wireless terminals 101-1 and 101-2 operating under such different standards, base station 103-1 must be able to provide the processing required to support both such telecommunications standards.
One prior art approach for supporting multiple telecommunications standards involves using duplicative hardware. In particular, for such an approach, base station 103-1 uses a first receiver/transmitter pair for communication with wireless terminal 101-1 and a second receive/transmitter pair for communication with wireless terminal 101-2. Such duplicative hardware increases base station cost.
As an alternative to using duplicative hardware, software-defined radios have been used as receivers and transmitters. With software-defined radios, an operator of a wireless telecommunications system can program a processor containing software and execute such software to both receive and transmit radio signals. To support the different telecommunications standards, the operator of the wireless telecommunications system will typically program the software processor with different programs to receive and transmit signals for the different systems employed within the telecommunications system. While more cost effective than using duplicative hardware, using multiple software programs to support different telecommunications disadvantageously requires software modifications whenever telecommunications standards are updated. The updating of numerous software programs can in itself be an expensive maintenance cost of an operating wireless telecommunications system.
While there have been attempts in the prior art to simplify transceiver operation via software-defined devices, such devices have typically been xe2x80x9cstandards specific.xe2x80x9d In other words, such devices include unique programming to support communications for a specific telecommunications standard. A software control logic package capable of handling communications supported by a variety of telecommunications standards would simplify transceiver operation and would be beneficial to the art. The efforts of the prior art notwithstanding, such desired simplification has, until now, remained elusive.
In some embodiments, the present invention provides a wireless telecommunications system that uses a transceiver having a generic architecture. For transceiver operation to be xe2x80x9cgeneric,xe2x80x9d it must be able to handle a plurality of channels associated with each of a variety of telecommunications systems. Such a generic package, which would be installed unmodified at different locations operating under different standards, reduces the hardware costs associated with duplicative hardware and the maintenance requirements of duplicative software packages of the prior art.
Such a transceiver is operable to receive and transmit information-bearing signals over the variety of telecommunications systems and standards without hardware or software modifications thereto.
The present invention advantageously avoids the complexity of the prior art approaches, either hardware or software based. For example, in one embodiment of the present invention, a generic receiving section of a base station will reject channels that are not specifically allocated to the base station. Unlike a typical prior art receiver, there is no need to design or tune the receiver to handle the allocated channels. In other words, the same generic receiving section could be located in another base station and used to handle other channels allocated to the other base station without modification thereto.
An illustrative method in accordance with the present teachings comprises the operations of: receiving uplink analog RF signals at a base station; converting the uplink analog RF signals into IF uplink digital signals in an analog-to-digital converter; converting the IF uplink digital signals into a number of narrow-band uplink channels; and demodulating selected narrow-band uplink channels from the total number of narrow-band uplink channels.

Software-defined transceiver for a wireless telecommunications system


A polycarbonate resin composition which has excellent flame retardancy, even when containing neither any phosphorus compound flame retardant nor any halogenated flame retardant, and which is highly reflective and has light-shutting properties and excellent thermal stability. The polycarbonate resin composition comprises 5 to 98 parts by weight of a polycarbonate/polyorganosiloxane copolymer, 0 to 93 parts by weight of a polycarbonate resin, 2 to 50 parts by weight of titanium oxide, 0 to 1.0 parts by weight of a fibril-forming polytetrafluoroethylene, and 0.05 to 2.0 parts by weight of an organosiloxane, the sum of the ingredients (A), (B), and (C) is 100 parts by weight.

A polycarbonate resin is excellent in mechanical strength (especially, impact resistance), electrical properties, transparency, etc., and has been widely used as an engineering plastic in various fields such as office automation (hereinafter referred to as OA) equipment, electrical and electronic equipment, automobiles, etc. Among them, there is a field in which flame retardancy is required, mainly in the fields of OA equipment, and electrical and electronic equipment. A polycarbonate resin has a high oxygen index among various thermoplastic resins, and is generally considered to be a resin with self-extinguishing properties. However, the flame retardancy level required in the fields of OA equipment and electrical and electronic equipment is generally so high as the V-0 level of UL 94 Standards on flame retardancy, that other flame retardants and auxiliaries are usually added in order to impart the flame retardancy meeting the level.
On the other hand, it is known that a polycarbonate-polyorganosiloxane copolymer or a mixture of the polycarbonate-polyorganosiloxane copolymer and a polycarbonate resin generally shows higher flame retardancy than that of the polycarbonate resin. However, since the flame retardancy of the polycarbonate-polyorganosiloxane copolymer alone is not sufficient to meet the above-mentioned level of the flame retardancy, a composition in combination with various flame retardants has been disclosed (for example, Japanese Patent Application Laid-Open No. 289059/1988 (Showa 63), Japanese Patent Application Laid-Open No. 210462/1989 (Heisei 1), Japanese Patent Application Laid-Open No. 200862/1991 (Heisei 3), Japanese Patent Application Laid-Open No. 202465/1992 (Heisei 4), Japanese Patent Application Laid-Open No. 320519/1993 (Heisei 5), Japanese Patent Application Laid-Open No. 36836/1994 (Heisei 6), Japanese Patent No. 3007046, etc.). However, these disclosed techniques have a drawback, wherein thermal stability is in general decreased when a bromine compound is added as a flame retardant. In the case when a phosphorus compound is added, fluidity is improved, while heat resistance decreases. Especially, when environmental problems are taken into consideration, it has been considered generally difficult to achieve flame retardancy and high reflectance at the same time in a thin-walled molding with a wall thickness of 1 mm or less for a product required in a reflecting plate and the like used for backlight of a liquid crystal display etc., without using a bromine compound or a phosphorus compound.
Furthermore, when such a polycarbonate resin composition is formed to an extruded sheet molding, since not only high reflectance but also high light-shutting properties are required for optical properties in light reflecting applications such as a backlight reflecting plate etc. of a liquid crystal display etc., it is necessary to blend titanium oxide in a high concentration. However, when the titanium oxide was blended in a high concentration, there was a problem in that a polycarbonate resin matrix became degraded, and consequently the light reflectance of a resin molding decreased. Also, when the titanium oxide is blended in a large quantity, decrease in the molecular weight of the polycarbonate becomes substantial, which causes reduction in the mechanical strength. A polycarbonate resin composition blended with titanium oxide, having a good mechanical strength and excellent optical properties after improving the above-mentioned problems has been disclosed in Japanese Patent Application Laid-Open No. 320519/1993 (Heisei 5). Nevertheless, a polycarbonate resin composition is desired, which, in addition to further improving these properties, exhibits excellent flame retardancy without adding a phosphorus compound flame retardant or a halogenated flame retardant while maintaining heat resistance, and also satisfies high reflectance and high light-shutting properties in terms of optical properties.

Polycarbonate resin composition and molded object thereof


A method for merging pixel fragments to reduce memory usage in a graphics rendering system. In rendering a graphics scene, geometric primitives of objects in the scene are rasterized to create pixel data including pixel fragments representing partially covered pixels. Lists of pixel fragments having color, depth, and coverage data are stored in a fragment buffer. When a new fragment is generated, an attempt is made to merge the fragment with the last fragment stored for a corresponding pixel location. Fragments are merged if they are within predefined depth and color tolerances.

Graphics rendering refers generally to the process of generating a two-dimensional image from graphical models. A graphical model defines attributes of a real or imaginary object which are to be represented in a rendered image. These attributes include, for example, color, shape, and position of an object in a graphics scene. In the process of rendering these models, a graphics system generates a display image, which is comprised of an array of pixel data.
A pixel is a point or picture element in a display device, and in the context of graphics processing, also corresponds to a point in the two-dimensional space to which the graphical models are rendered. Each pixel element of a rendered image includes one or more data values describing attributes of the pixel used to display it. For instance in color graphics, this pixel data can include intensity values for color components that give the pixel element its color. The intensity values stored in an array of pixel elements are then used to display the array on physical output device such as a raster display device.
Graphics processing is often classified by the dimension of the models to be rendered to an image. For instance, two-dimensional graphics processing ("2-D graphics") refers to the generation of an image from graphical models having two dimensions (x and y coordinates) and three-dimensional graphics processing ("3-D graphics") refers the processing of three-dimensional models.
Graphics processing can also be classified as "real-time" which means that 1) the display image is updated so that the user perceives continuous motion of the objects in the scene; and 2) there is minimal and predictable "transport delay" between user input, which change the position of objects or the viewpoint of the scene, and the display of an image in response to this input. To achieve this affect, objects in the scene, must be rendered within a predefined period of time.
In 3-D graphics applications, an object in a scene is represented by a 3-D graphical model, which includes geometric data used to model the surface and position of the object, and visual attributes used to model the appearance of the object. There are a number of ways that a geometric model can represent a 3-D object, including polygon meshes, parametric surfaces, or quadratic surfaces. Using a polygon mesh, for example, the surface of an object is modeled with several interconnected polygons,. The surface elements, in this case polygons, are referred to as geometric primitives. Visual attributes such as red, green, and blue color data, and possibly other model data is stored at the vertices of the polygon.
In the rendering process, the geometric primitives corresponding to objects in a scene are processed to generate a display image. In the context of 3-D graphics, the rendering process includes transforming the graphical models in a scene, and rasterizing the geometric primitives in the models to generate pixel data. In some systems, this pixel data is processed further to enhance image quality. The final product of the rendering process is a display image comprised of a collection of pixel values. To display the image, these pixel values are transferred from a memory buffer, such as a frame buffer, to a display controller.
The typical graphics processing system includes a physical output device that displays rendered images. Although other forms of display devices have been developed, the predominant technology today is referred to as raster graphics. A raster display device includes an array of individual points or picture elements (i.e., pixels), arranged in rows and columns, to produce the image. In a CRT, these pixels correspond to a phosphor array provided on the glass faceplate of the CRT. The emission of light from each phosphor in the array is independently controlled by an electron beam that "scans" the array sequentially, one row at a time, in response to stored information representative of each pixel in the image. The array of pixel values that map to the screen is often referred to as a bitmap or pixmap.
The rendering process typically begins by transforming the vertices of the geometric primitives to prepare the model data for the rasterizing step. While the specific details of the transformation phase varies, a few examples will illustrate the process. The modeling transform, in some systems, is used to convert the vertices of a model from the model's local coordinates to world coordinates, the coordinates in which a complete scene is represented. The next step is to determine potentially visible objects in a 3-D space referred to as the view volume. This step is commonly performed in view reference coordinates, which describes object locations relative to a viewpoint or eyepoint. Objects that are not potentially visible at this stage can be disregarded while objects that are at least partially in the view volume are "clipped" to the view volume.
After transforming the objects, the geometric primitives for the objects are "rasterized" or "scan converted." Rasterizing refers generally to the process of computing a pixel value for a pixel in the image being rendered based on data from the geometric primitives that project onto or "cover" the pixel. Rasterizing is sometimes referred to as "tiling" because of the analogy to tiling a floor. Imagine that the pixels are square elements or tiles, and that a polygon is the floor plan. The rasterizing step includes tiling this floor plan by computing pixel values for the pixels or "tiles" within the polygon. The pixel values can include, for example, intensity values representing the red, green, and blue (R, G, B) color components of a pixel.
While there are a number of ways to raisterize a geometric primitive, this process generally involves computing a pixel intensity value or values based on the data from a primitive that projects onto or "covers" a pixel. For example, color values stored at the vertices of a polygon can be interpolated to find a color value at a given pixel. During this process, lighting and shading models can also be used to compute pixel values for pixels across the surface of the polygon.
From the tiling analogy above, it is clear that discrete pixels cannot precisely represent continuous surfaces. For example, a polygon may only partially cover a pixel region. In this case, the edge or edges of a polygon cross over the pixel region. If the pixel were approximated as being fully covered by this polygon, anomalies such as jaggy edges in the rendered image would likely result. A technique known generally as anti-aliasing attempts to address this problem. In general, anti-aliasing is used to compute pixel intensities for partially covered pixels to reduce the discontinuities introduced by representing a continuos object with a discrete array of pixels.
In a given 3-D graphics scene, a number of polygons may project onto the same area of the view space, and some of these polygons may occlude others. As such, some primitives may not be "visible" in the scene. Hidden surface removal is the process of determining which objects or portions of objects are, and conversely, are not visible in the scene. There are a number of approaches to hidden surface removal. Some approaches involve pre-sorting primitives before the rasterizing step. Examples of these types of approaches include: 1) sorting primitives and then rendering the primitives in back to front order so that pixels for visible objects overwrite pixels for occluded objects; and 2) sorting primitives in depth order *and then clipping the primitives relative to each other to eliminate hidden portions of the primitive. Of course there are a number of variations to these examples as well as a variety of additional examples.
These approaches are generally not preferred because they are computationally complex and therefore consume precious processing resources. Additional processing is required to sort the primitives in the scene before the rasterizing step. For real-time systems where objects are in motion from scene to scene, the computations required to sort and/or clip primitives makes them untenable alternatives. In any practical system, there is a trade-off between image quality and computational complexity. If the hidden surface removal technique is complex, yet does not improve image quality relative to other alternatives, it is not an acceptable solution.
In other approaches, the primitives are not sorted before scan conversion, but instead, the pixel data generated from the scan conversion process includes depth values used to perform hidden surface removal. The Z-buffer is one such approach. The Z-buffer includes an array having elements for storing pixel data including depth values for every pixel location in a display image. As geometric primitives are rasterized, the depth value for newly generated pixel data is compared with a depth value of pixel data stored in the z buffer. If the newly generated pixel data is closer to the viewpoint, it is written over the current values in the Z-buffer for the corresponding pixel location. If :not, it is disregarded.
The primary advantages of the Z-buffer approach are computational speed and simplicity. However, by itself, the Z-buffer approach provides no support for dealing with partially covered pixels or translucent pixels.
One improvement to the Z-buffer approach is known as the A-buffer and is described in: L. Carpenter "The A-Buffer, An Anti-Aliased Hidden Surface Method," in Computer Graphics, SIGGRAPH '84 proceedings, July 1984, Vol. 18, No. 3, pp. 103-108.
In this approach, polygons are clipped into fragments at the boundaries of a pixel region. For example, assume a pixel is represented as a square. If 3-sided polygon (triangle) partially covers this square, a pixel fragment is generated to represent the portion of the triangle covering the square. A bit mask, created by exclusive ORing masks representing polygons edges, is used to describe how a polygon partially covers the pixel region.
In the A-buffer approach, there are two different data types representing pixel data. One type data type, called a "pixelstruct," is used to store color and depth of a fully covered pixel, and a pointer to a depth sorted fragment list for partially covered pixels. The other data type is called a "fragment," which can store a pointer to the next fragment in a linked list, color, opacity, area, an object tag, a pixel mask, and a range of z values. Pixelstructs are stored in an array having the size and shape of the final image.
Geometric prirnitives are rasterized to generate the pixel data in the pixelstruct array and fragment lists. After the pixel data is generated for the pixelstruct array, the pixels having fragment lists are processed in a technique called "packing." Packing refers to the process of computing pixel values from a depth sorted fragment list.
The primary advantage of the A-buffer approach is that it supports high-quality anti-aliasing and translucency computations. The A-buffer improves the general Z-buffer approach so that anti-aliasing for partially covered pixels and translucency for non-opaque pixels can both be supported.
One problem with the A-buffer approach is that it requires additional memory to store the fragment lists. The memory required to store fragments for an entire frame of image data can be enormous. The Carpenter paper refers to a software implementation where the pixelstruct array is "paged in software to save virtual memory space." This approach assumes that the computer system used to render an image has enough memory to store fragments generated during the rendering process.
Carpenter uses a technique referred to as fragment merging in which two or more fragments are combined into a single fragment. According to Carpenter, "merging two or more fragments simplifies the data structure and reclaims the space used by the merged-in fragments." Carpenter's approach merges fragments if they have the same object tag and overlap in Z. The object tag identifies an object from which the fragment originates and also includes data indicating whether the surface of the object faces forward or backward. While not described fully in the paper, the Z overlap appears to refer to the case where the range of z values overlap for fragment merge candidates.
In Carpenter's approach, the test to determine whether to merge a fragment is performed "whenever a new fragment is added to the pixelstruct list."
While fragment merging can reduce memory consumption, Carpenter's approach has a number of drawbacks. Every fragment must have an object tag. This complicates the rasterizing process because the object tag, including data indicating a front or back facing surface, must be determined and stored for each fragment. In addition, Carpenter's method has to maintain a Zmax and Zmin value for each fragment, which complicates processing and requires more storage. Carpenter further suggests that fragments should be maintained in a sorted order. While this can improve the efficiency by reducing the number of fragments that need to be examined to merge a fragment, this type of sorting further complicates the fragment generation process.
Carpenter describes fragment processing in terms of a software implementation, which cannot generate images for real-time, interactive applications. While the Carpenter approach is an improvement to the Z-buffer algorithm, it is extremely difficult to implement in a real-time system. In a real-time system, each pixel must be processed very quickly so that a new image can be generated within rigorous timing constraints. In Carpenter's A-buffer approach, this is not a concern because it is only used to compute images in a non-real time software system.

Method and system for merging pixel fragments in a graphics rendering system


To provide a semiconductor device with high performance and low cost and a manufacturing method thereof. A first region including a separated (cleavage) single-crystal semiconductor layer and a second region including a non-single-crystal semiconductor layer are provided over a substrate. It is preferable that laser beam irradiation be performed to the separated (cleavage) single-crystal semiconductor layer in an inert atmosphere, and laser beam irradiation be performed to the non-single-crystal semiconductor layer in an air atmosphere at least once.

1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
The history of developing semiconductor devices having transistors using semiconductors has been a history of the challenge of providing higher performance semiconductor devices at lower cost.
One of methods for improving the performance of semiconductor devices is to improve crystallinity of a semiconductor.
Single-crystal semiconductors have the highest crystallinity.
Single-crystal semiconductor wafers, SOI (silicon on insulator) substrates, and the like are given as substrates for single-crystal semiconductors.
However, such substrates have a disadvantage of high cost. This disadvantage is more significant as the substrates have larger area.
On the other hand, semiconductor devices using semiconductors formed on low-cost substrates (e.g., glass substrates) by a film formation method are given as low-cost semiconductor devices in which larger substrates are suitably used.
Further, regarding a semiconductor device using a semiconductor formed on a substrate by a film formation method, there have been attempts to provide higher performance semiconductor devices at low cost, in which crystallinity of a semiconductor is improved (for example, Reference 1: Japanese Published Patent Application No. 117-130652).
However, it is very difficult to make a perfect single-crystal semiconductor from a semiconductor formed on a substrate by a film formation method.
In response, there have also been attempts to form a single-crystal semiconductor on a low-cost substrate by bonding a single-crystal semiconductor onto a low-cost substrate (Reference 2: Japanese Published Patent Application No. 1111-163363).
However, the techniques disclosed in Patent Document 1 and Patent Document 2 have a problem of damaging a single crystal due to implantation of ion species of hydrogen or the like and a problem of generating large projections and depressions on a surface of a single crystal which remains over a base substrate.
When a gate insulating film is formed, the large projections and depressions penetrate the gate insulating film, causing a problem of leakage between the semiconductor layer and a gate electrode.
With the invention disclosed in Reference 2, high performance semiconductor devices can be provided at low cost; however, since a single-crystal semiconductor is used, the cost is higher compared with the cost involved in the case of using the invention disclosed in Reference 1.
Here, a semiconductor device has various circuits, and there are cases where not all the circuits are necessarily formed using a single crystal, but only some high performance circuits should be formed using a single crystal.

Manufacturing method of semiconductor device

Semiconductor Energy Laboratory Co., Ltd.


A seat assembly (21) including a seat (22), a backrest (23) and a mounting assembly (24) mounting the seat (22) in a near horizontal orientation for movement along an upwardly concaved arcuate seat path having a center of curvature (37) proximate the center of mass (39) of a person seated on the seat, and the mounting assembly (24) further mounting the backrest (23) in a near vertical orientation for movement independently of the seat along a forwardly concaved arcuate path having a center curvature (37) proximate the center of mass (39) of the person. An adjustment assembly (61) is provided for adjusting the radius of curvature of the path of motion of the backrest (23). Also provided are a backrest tilt adjustment assembly (71), an armrest adjustment assembly (90), a seat biasing assembly (110) and a seat motion latching assembly (111). A method of self-adjusting support and alignment of a backrest also is disclosed.

Considerable work has been directed toward the development of seat assemblies or chairs which are ergonomically well suited for use by persons who are engaged in tasks that require that they be seated for prolonged periods of time. Typical of such applications are the seats or chairs which are used in offices or at home for tasks such as typing, reading and computer use.
In recent years it has been recognized that it is highly desirable for such seat assemblies or chairs to be constructed in a manner which allows the seat to move along an upwardly concaved arcuate path, or some approximation thereof. Such arcuate movement is most desirably implemented by mounting the seat for movement about an arcuate path having a center of curvature which is proximate the center of mass of the person seated on the seat. This geometry dynamically balances the bio-mechanics of a user's body with movement of the chair so that the user can have a plurality of equilibrium positions in a variety of postures. The design principle is one of counterbalanced motion in which the mass of the user's body is counterbalanced by angular forces of the motion of the seat in a fore-and-aft direction.
My previous U.S. Pat. Nos. 5,244,252; 5,460,427; 5,558,399 and 5,735,574 describe in more detail the advantages of mounting a seat for movement along an upwardly concaved path having a center of curvature proximate the center of mass of the person seated on the seat. These patents are incorporated herein by reference. Such seat assemblies also are particularly well suited for use in vehicles in order to dissipate the dynamic forces generated when the vehicle is involved in a sudden deceleration or crash.
In addition to mounting the seat of a chair for arcuate movement, it is also well known to mount the back of the seat assembly for movement or for movement of a portion of the back, such as the lumbar support region. Various schemes for moving the back are also disclosed in my above-referenced patents. Most of these movable back mounting systems couple the back to the seat and have been designed primarily for dynamic deceleration in vehicles, but they are usable to varying degrees in office chairs.
U.S. Pat. Nos. 5,261,732; 5,366,269; 5,437,494; 5,577,802; 5,961,073; 5,979,984 and 6,334,648 disclose chairs or seat assemblies in which one or both of the back and seat are mounted for movement. It is also well known in office chairs and the like to provide for backrest reclining mechanisms as, for example, are shown in U.S. Pat. Nos. 5,975,634 and 6,086,153.
Generally, however, there still remains a need for a chair or seating assembly which can be used for long periods of time that has a movably mounted seat and backrest which will accommodate a wide range of seating postures while providing many balanced or equilibrium positions matched to the bio-mechanics of the user's body. Thus, the person using the chair will want to assume various postures, such as a forward reaching posture (where the person is performing manual tasks on a support surface such as a desk), or an erect posture (for tasks such as typing), or a semi-reclined posture for increased comfort. The seat and backrest should be movable to an equilibrium position about which dynamic micro-adjustments of the user's body and the seat assembly about the center of mass of the user are possible in order to provide the greatest comfort during prolonged use.

Dynamically balanced seat assembly having independently and arcuately movable seat and backrest and method