This invention concerns a database computer system and method for making applications recoverable from system crashes. The application state (i.e., address space) is treated as a single object which can be atomically flushed in a manner akin to flushing individual pages in database recovery techniques. To enable this monolithic treatment of the application, executions performed by the application are mapped to logical loggable operations which can be posted to the stable log. Any modifications to the application state are accumulated and the application state is periodically flushed to stable storage using an atomic procedure. The application recovery integrates with database recovery, and effectively eliminates or at least substantially reduces the need for check pointing applications. In addition, optimization techniques are described to make the read, write, and recovery phases more efficient.

This invention relates to database computer systems and applications that execute on them. More parsicularly, this invention relates to methods for recovering from system crashes in a manner that ensures that the applications themselves persist across the crash.
Computer systems occasionally crash. A xe2x80x9csystem crashxe2x80x9d is an event in which the computer quits operating the way it is supposed to operate. Common causes of system crashes include power outage, application operating error, and computer goblins (i.e., unknown and often unexplained malfunctions that tend to plague even the best-devised systems and applications). System crashes are unpredictable, and hence, essentially impossible to anticipate and prevent.
A system crash is at the very least annoying, and may result in serious or irreparable damage. For standalone computers or client workstations, a local system crash typically results in loss of work product since the last save interval. The user is inconvenienced by having to reboot the computer and redo the lost work. For servers and larger computer systems, a system crash can have a devastating impact on many users, including both company employees as well as its customers.
Being unable to prevent system crashes, computer system designers attempt to limit the effect of system crashes. The field of study concerning how computers recover from system crashes is known as xe2x80x9crecovery.xe2x80x9d Recovery from system crashes has been the subject of much research and development.
In general, the goal of redo recovery is to return the computer system after a crash to a previous and presumed correct state in which the computer system was operating immediately prior to the crash. Then, transactions whose continuations are impossible can be aborted. Much of the recovery research focuses on database recovery for database computer systems, such as network database servers or mainframe database systems. Imagine the problems caused when a large database system having many clients crashes in the midst of many simultaneous operations involving the retrieval, update, and storage of data records. Database system designers attempt to design the database recovery techniques which minimize the amount of data lost in a system crash, minimize the amount of work needed following the crash to recover to the pre-crash operating state, and minimize the performance impact of recovery on the database system during normal operation.
FIG. 1 shows a database computer system 20 having a computing unit 22 with processing and computational capabilities 24 and a volatile main memory 26. The volatile main memory 26 is not persistent across crashes and hence is presumed to lose all of its data in the event of a crash. The computer system also has a non-volatile or stable database 28 and a stable log 30, both of which are contained on stable memory devices, e.g. magnetic disks, tapes, etc., connected to the computing unit 22. The stable database 28 and log 30 are presumed to persist across a system crash. The persistent database 28 and log 30 can be combined in the same storage, although they are illustrated separately for discussion purposes.
The volatile memory 26 stores one or more applications 32, which execute on the processor 24, and a resource manager 34. The resource manager 34 includes a volatile cache 36, which temporarily stores data destined for the stable database 28. The data is typically stored in the stable database and volatile cache in individual units, such as xe2x80x9cpages.xe2x80x9d A cache manager 38 executes on the processor 24 to manage movement of data pages between the volatile cache 36 and the stable database 28. In particular, the cache manager 38 is responsible for, deciding which data pages should be moved to the stable database 28 and when the data pages are moved. Data pages which are moved from the cache to the stable database are said to be xe2x80x9cflushedxe2x80x9d to the stable state. In other words, the cache manager 38 periodically flushes the cached state of a data page to the stable database 28 to produce a stable state of that data page which persists in the event of a crash, making recovery possible.
The resource manager 34 also has a volatile log 40 which temporarily stores computing operations to be moved into the stable log 30. A log manager 42 executes on the processor 24 to manage when the operations are moved from the volatile log 40 to the stable log 30. The transfer of an operation from the volatile log to the stable log is known as a log flush.
During normal operation, an application 32 executes on the processor 24. The resource manager receives requests to perform operations on data from the application. As a result, data pages are transferred to the volatile cache 36 on demand from the stable database 28 for use by the application. During execution, the resource manager 34 reads, processes, and writes data to and from the volatile cache 36 on behalf of the application. The cache manager 38 determines, independently of the application, when the cached Data State is flushed to the stable database 28.
Concurrently, the operations being performed by the resource manager on behalf of the application are being recorded in the volatile log 40. The log manager 42 determines, as guided by the cache manager and the transactional requirements imposed by the application, when the operations are posted as log records on the stable log 30. A logged operation is said to be xe2x80x9cinstalledxe2x80x9d when the versions of the pages containing the changes made by the operation have been flushed to the stable database.
When a crash occurs, the application state (i.e., address space) of any executing application 32, the data pages in volatile cache 36, and the operations in volatile log 40 all vanish. The computer system 20 invokes a recovery manager which begins at the last flushed state on the stable database 28 and replays the operations posted to the stable log 30 to restore the database of the computer system to the state as of the last logged operation just prior to the crash.
Explaining how to recover from a system crash requires answering some fundamental questions.
1. How can the designer be sure that recovery will succeed?
2. How can the stable state be explained in terms of what operations have been installed and what operations have not?
3. How should recovery choose the operations to redo in order to recover an explainable state?
4. How should the cache manager install operations via its flushing of database pages to the stable state in order to keep the state explainable, and hence recoverable?
The answers to these questions can be found in delicately balanced and highly interdependent decisions that a system designer makes.
One prior art approach to database recovery is to require the cache manager to flush the entire cache state periodically. The last such flushed state is identified in a xe2x80x9ccheckpoint recordxe2x80x9d that is inserted into the stable log. During recovery, a redo test is performed to determine whether a logged operation needs to be redone to help restore the system to its pre-crash state. The redo test is simply whether an operation follows the last checkpoint record on the log. If so (meaning that a later operation occurred and was posted to the stable log, but the results of the operation were not installed in the stable database), the computer system performs a redo operation using the log record.
This simple approach has a major drawback in that writing every change of the cached state out to the stable database 28 is practically unfeasible. It involves a high volume of input/output (I/O) activity that consumes a disproportionate amount of processing resources and slows the system operation. It also requires atomic flushing of multiple pages, which is a troublesome complication. This was the approach used in System R., described in: Gray, McJones, et al, xe2x80x9cThe Recovery Manager of the System R Database Manager,xe2x80x9d ACM Computing Surveys 13,2 (June, 1981) pages 223-242.
Another prior art approach to database recovery, which is more widely adopted and used in present-day database systems, involves segmenting data from the stable database into individual fixed units, such as pages. Individual pages are loaded into the volatile cache and logged resource manager operations can read and write only within the single pages, thereby modifying individual pages. The cache manager does not flush the page after every incremental change.
Each page can be flushed atomically to the stable database, and independently of any other page. Intelligently flushing a page after several updates have been made to the page produces essentially the same result as flushing each page after every update is made. That is, flushing a page necessarily includes all of the incremental changes made to that page leading up to the point when the flushing occurs.
The cache manager assigns a monotonically increasing state ID to the page each time the page is updated. During recovery, each page is treated as if it were a separate database. Resource manager operations posted to the stable log are also assigned a state ID. A redo test compares, for each page, the state ID of a stable log record with the state ID of the stable page. If the log record state ID is greater than the state ID of the stable page (meaning that one or more operations occurred later and were recorded in the stable log, but the page containing updates caused by the later operations was not yet flushed to the stable database), the computer system performs a redo operation using the last stable page and the operations posted to the stable log that have state IDs higher than the state ID of the stable page.
While these database recovery techniques are helpful for recovering data, in the database, the recovery techniques offer no help to recovering an application from a system crash. Usually all active applications using the database are wiped out during a crash. Any state in an executing application is erased and cannot usually be continued across a crash.
FIG. 2 shows a prior art system architecture of the database computer system 20. The applications 32(1)-32(N) execute on the computer to perform various tasks and functions. During execution, the applications interact with the resource manager 26, with each other, and with external devices, as represented by an end user terminal 44. The application states can change as a result of application execution, interaction with the resource manager 26, interaction with each other, and interaction with the terminal 44. In conventional systems, the application states of the executing applications 32(1)-32(N) are not captured. There is no mechanism in place to track the application state as it changes, and hence, there is no way to recover an application from a crash which occurs during its execution.
When the application is simple and short, the fact that applications are not recoverable is of little consequence. For example, in financial applications like debit/credit, there may be nothing to recover that was not already captured by the state change within the stable database. But this might not always be the case. Long running applications, which frequently characterize workflow systems, present problems. Like long transactions that are aborted, a crash interrupted application may need to be re-scheduled manually to bring the application back online. Applications can span multiple database transactions whereby following a system crash, the system state might contain an incomplete execution of the application. Cleanly coping with partially completed executions can be very difficult. One cannot simply re-execute the entire activity because the partially completed prior execution has altered the state. Further, because some state changes may have been installed in the stable database, one cannot simply undo the entire activity because the transactions are guaranteed by the system to be persistent. The transactions might not be undoable in any event because the system state may have changed in an arbitrary way since they were executed.
Accordingly, there is a need for recovery procedures for preserving applications across a system crash. Conceptually, the entire application state (i.e., the address space) could be posted to the stable log after each operation. This would permit immediate recovery of the application because the system would know exactly, from the last log entry for the application, the entire application state just prior to crash. Unfortunately, the address space is typically very large and continuously logging such large entries is too expensive in terms of I/O processing resources and the large amounts of memory required to hold successive images of the application state.
There are several prior art techniques that have been proposed for application recovery. All have difficulties that restrict their usefulness. One approach is to make the application xe2x80x9cstateless.xe2x80x9d Between transactions, the application is in its initial state or a state internally derived from the initial state without reference to the persistent state of the database. If the application fails between transactions, there is nothing about the application state that cannot be recreated based on the static state of the stored form of the application. Should the transaction abort, the application is replayed, thereby re-executing the transaction as if the transaction executed somewhat later. After the transaction commits, the application returns to the initial state. This form of transaction processing is described by Gray and Reuter in a book entitled, Transaction Processing: Concepts and Techniques, Morgan Kaufnann (1993), San Mateo, Calif.
Another approach is to reduce the application state to some manageable size and use a recoverable resource manager to store it. The resource manager might be a database or a recoverable queue. Reducing state size can be facilitated by the use of a scripting language for the application. In this case, the script language interpreter stores the entire application state at well-chosen times so that failures at inappropriate moments survive, and the application execution can continue from the saved point.
Another technique is to use a persistent programming language that logs updates to a persistent state. The idea is to support recoverable storage for processes. When the entire state of the application is contained in recoverable storage, the application itself can be recovered. Recoverable storage has been handled by supporting a virtual memory abstraction with updates to memory locations logged during program execution. If the entire application state is made recoverable, a very substantial amount of logging activity arises. This technique is described in the following publications: Chang and Mergen, xe2x80x9c801 Storage: Architecture and Programming,xe2x80x9d ACM Trans. on Computer Systems, 6, 1 (February 1988) pages 28-50; and Haskin et al., xe2x80x9cRecovery Management in QuickSilver,xe2x80x9d ACM Trans. on Computer Systems, 6,1 (February 1988) pages 82-108.
Another approach is to write persistent application checkpoints at every resource manager interaction. The notion here is that application states in between resource manager interactions can be re-created from the last such interaction forward. This is the technique described by Bartlett, xe2x80x9cA NonStop Kernel,xe2x80x9d Proc. ACM Symp. on Operating System Principles (1981) pages 22-29 and Borg et al. xe2x80x9cA Message System Supporting Fault Tolerance,xe2x80x9d Proc. ACM Symp. on Operating System Principles (October 1983) Bretton Woods, N.H. pages 90-99. The drawback with this approach is that short code sequences between interactions can mean frequent checkpointing of very large states as the state changes are not captured via operations, although paging techniques can be used to capture the differences between successive states at, perhaps, page level granularity.
The inventor has developed an improved application recovery technique.
This invention concerns a database computer system and method for making applications recoverable from system crashes. The application state (i.e., address space) is treated as a single object that can be atomically flushed in a manner akin to flushing individual pages in database recovery techniques. And like the pages of the database, log records describing application state changes are posted on the stable log before application state is flushed.
To enable this monolithic treatment of the application, executions performed by the application are mapped to loggable operations which are posted to the stable log. Any modifications to the application state are accumulated and the application state is flushed from time to time to stable storage using an atomic write procedure. Flushing the application state to stable storage effectively installs the application operations logged in the stable log. Since the application state can be very large, a procedure known as xe2x80x9cshadowingxe2x80x9d can be used to atomically flush the entire application state. As a result, the application recovery integrates with database recovery, and substantially reduces the need for checkpointing applications, i.e. logging or flushing the entire application state. According to one implementation, a database computer system has a processing unit, a volatile main memory that does not persist across a system crash, and a stable memory that persists across a system crash. The volatile memory includes a volatile cache which maintains cached states of the application address space and data records and a volatile log which tracks the operations performed by the computer system. The stable memory includes a stable database which stores stable states of the application address space and data records and a stable log which holds a stable version of the log records that describe state changes to the stable database.
The database computer system has at least one application which executes from the main memory on the processing unit. A resource manager is stored in main memory and mediates all interaction between the application and the external world (e.g., user terminal, data file, another application, etc.). During execution, the internal state changes of the application are not visible to the outside world. However, each time the application interacts with the resource manager, either the application state is exposed or the application senses the external state. The resource manager tags the application states at these interaction points by assigning them state IDs. Application operations are defined that produce the transitions between these application states. These operations are immediately entered into the volatile log, and subsequently posted to the stable log.
The application state is treated as a single object that can be atomically flushed to the stable database. In addition, the application operations often cause changes to the data pages, records, or other types of objects stored in the volatile cache. The modified objects that result from application operations are from time to time flushed to the stable database. The flushed application states and objects are assigned state IDs to identify their place in the execution sequence. Flushing the application object effectively installs all the operations, updating the application operations that are in the stable log which have earlier state IDs.
In the event of a system failure, the database computer system begins with the stable database state and replays the stable log to redo certain logged application operations. The database computer system redoes a logged application operation if its state ID is later in series than the state ID of the most recently flushed or already partially recovered application state.
Another aspect of this invention is to optimize the application read operation to avoid writing the object data read to the log record. Posting the read values to the log is helpful in one sense because the cache manager is not concerned about which sequence to flush objects. Certain object states need not be preserved by a particular flushing order because any data values obtained from an object which are needed to redo an application operation are available directly from the stable log. However, posting objects to the log often involves writing large amounts of data, and duplicating data found elsewhere on the system.
The read optimizing technique eliminates posting the read values to the log by substituting, for the read values, an identity of the location from where the values are read and posting the identity instead of the values. However, the data is now only available from the read object itself and hence, attention must be paid to the order in which objects are flushed to stable storage. If objects are flushed out of proper sequence, a particular state of an object may be irretrievably lost.
A cache manager has an object table which tracks the objects maintained in the volatile cache. The object table includes fields to track dependencies among the objects. In one implementation, the object table includes, for each object entry, a predecessor field which lists all objects that must be flushed prior to the subject object, and a successor field which lists all objects before which the subject object must be flushed. In another implementation, the object table contains, for each object entry, a node field to store dependencies in terms of their nodes in a write graph formulation.
Another aspect of this invention is to optimize the application write operation to avoid posting large amounts of data to the log record. Posting the values to be written is helpful in one sense because the cache manager is not concerned about which sequence to flush objects. However, the process is inefficient and costly in terms of computational resources.
The write optimization technique eliminates posting the write values to the log by substituting for those values, an identity of the object from where the values originate and posting the identity instead of the values. While this reduces the amount of data to be logged, the write optimization technique introduces dependencies between objects, and often troubling xe2x80x9ccyclexe2x80x9d dependencies when the read optimization technique is also being used, which can require atomic and simultaneous flushing of multiple objects.
The cache manager tracks dependencies via the object table and is configured to recognize cycle dependencies. When a cycle dependency is realized, the cache manager initiates a blind write of one or more objects involved in the cycle to place the objects"" values on the stable log. This process breaks the cycle. Thereafter, the cache manager flushes the objects according to an acyclic flushing sequence that pays attention to any predecessor objects that first require flushing.
Still another aspect of this invention is to optimize the recovery procedures invoked following a system crash. During normal operation, each log record is assigned a log sequence number (LSN). The cache manager maintains a recovery log sequence number (rLSN) that identifies the first log record for an associated object at which to begin replaying the operations during recovery. The cache manager occasionally flushes an object to non-volatile memory to install the operations performed on the object. On some occasions, the flushing of one object installs operations that wrote another data object that has not yet been flushed (i.e., an object that is unexposed in the write graph, meaning that its contents are not needed for recovery). The cache manager advances the rLSN for both objects to identify subsequent log records that reflect the objects at states in which the operations that previously wrote the states are installed in the non-volatile memory.
During recovery, the recovery manager starts at the advanced rLSNs to avoid replaying operations that are rendered unnecessary by subsequent operations, thereby optimizing recovery.

Database computer system with application recovery and dependency handling write cache


A drill bit for percussive rock drilling of the type that comprises a front head and a tubular skirt, which extends rearward from the head to a rear, ring-shaped end and includes an internal thread for the transfer of combined impact and rotary motions to the drill bit is disclosed. The rear end of the skirt is, via an unelastic joint, e.g., a friction weld, united to a front end of a sleeve having an envelope surface, from which a plurality of projections are peripherically spaced-apart from each other project, e.g., ridges, having the purpose of guiding the drill bit in the drill hole. By assembling the drill bit of two parts, the internal thread can be turned with high accuracy and smoothness, at the same time as the drill bit is given an inherent good controllability. In an additional aspect, a method for the manufacture of such a drill bit is also disclosed.

In the discussion of the background that follows, reference is made to certain structures and/or methods. However, the following references should not be construed as an admission that these structures and/or methods constitute prior art. Applicant expressly reserves the right to demonstrate that such structures and/or methods do not qualify as prior art.
For the boring of deep holes in rock or earth, drill strings are used, which comprise a plurality of rods and coupling sleeves, which are assembled as the depth of the hole increases. A terrestrial machine having a shank adapter has the purpose of transferring combined impact and rotary motions to the upper end of the drill string, the lower end of which carries a drill bit, which performs the active operation to crush the rock and form the hole. By flushing fluid through the drill string to the drill bit, the detached drill cuttings can be conveyed to the hole entry by passing between the outside of the drill string and the inside of the hole.
In rock drilling equipment of this type, a number of requirements and needs are made, one of which is that the recessed hole should be as straight as possible, for instance in order to in the best way impinge on a predetermined target deep down in the rock. For this purpose, a number of control devices have previously been proposed, which make use of tubular controlling elements adjacent to those coupling sleeves, which couple together the different rods, or alternatively along the proper rods. Disadvantages of this type of control devices are that the drilling equipment in its entirety becomes complicated, expensive and ungainly to handle. A previously known rock drill bit, which to a certain extent has improved the straightness of drilled holes is shown in U.S. Pat. No. 7,281,594. A number of steps have there been provided on the skirt of the drill bit, which steps guide the bit in succession.
Another requirement is that the components included in a rock drilling equipment, and in particular the expensive drill bit, should have an optimum service life. In order to provide for this requirement, it is among other things important that the internal thread of the rear skirt of the drill bit is turned by smooth and precision-shaped thread ridges and thread grooves, because otherwise tendencies to crack and other phenomena may arise, which result in early corrosion fatigue

Percussive drill bit for rock drilling and method for the manufacture of such a drill bit


The present invention has an object to provide a simpler and quicker method for diagnosing tinea, method for detecting a Trichophyton, or method for detecting the Trichophyton gene. Use of at least four kinds of specific primers each designed based on a DNA sequence of the Trichophyton gene makes it possible to simply and quickly detect the Trichophyton gene.

Tinea is a type of fungal disease that causes an infection at skin keratin or nails. Dermatophytes such as Trichophyton rubrum (T. rubrum) and Trichophyton mentagrophytes (T. mentagrophytes) account for 90% or more of tinea-causative fungi detected in tinea patients. Other tinea-causative fungi are a Candida fungus (particularly, Candida albicans), an Aspergillus fungus, a Fusarium fungus, and the like.
The prevalence of tinea pedis and tinea unguium patients in Japan is said to be 25% for tinea pedis and 10% for tinea unguium. On the other hand, there are many non-infectious diseases with findings resembling tinea symptoms. A result obtained from patients each receiving a check-up with tinea as a chief complaint is that about ⅔ of the patients actually had tinea and the other patients did not have tinea. For this reason, there is a need for a simpler and quicker method for diagnosing tinea in order to select an appropriate treatment method.
As a method for diagnosing tinea, a method is known in which a specimen (a nail, keratin, or the like) collected from an affected area is analyzed by a direct microscopic method or a culture method. The direct microscopic method is a method of fusing protein with potassium hydroxide to expose fungus bodies, and then observing the fungus bodies with a microscope. The culture method is a method of culturing fungi on a selective medium for several weeks and observing colonies and the like in detail to identify the fungal species.
In recent years, with the advancement of molecular biology, it has become possible to use a nucleic acid amplification detection method for fungus-derived nucleic acids in order to identify a tinea-causative fungus, and methods using real-time PCR and nested PCR have been reported (Patent Literature 1 and Non-Patent Literature 1).
On the other hand, the LAMP method is a method of amplifying DNA quickly at a fixed temperature, and is a method that allows the amplified DNA to be confirmed even by a visual check through measurement such as turbidity or fluorescence detection (Patent Literatures 2 to 4). As previous reports using this method, methods for detecting Bordetella pertussis, diphtheria toxin, and so on have been known (Patent Literatures 5 and 6), but a method for detecting a Trichophyton using the LAMP method is not known.

Primer set for detecting trichophyton gene by lamp method, kit including same, and method for detecting trichophyton using same


A pseudo-dynamic operating method and a flash memory cell capable of performing this operating method are disclosed. A parasitic capacitor near the drain terminal of the flash memory can be charged in few microseconds during operation. Interference generated between the floating gate and the source is avoided by using a first oxide layer which is thicker at the interface between floating gate and source and thinner near central part under stacked gate.

1. Field of the Invention
The present invention relates to a nonvolatile memory cell, and more particularly, to a channel write/erase flash memory cell and its manufacturing method.
2. Description of the Related Art
Please refer to FIG. 1. FIG. 1 is a cross-sectional view of a conventional flash memory cell 10. It includes a substrate 11, a first field oxide layer 12, a stacked gate 14, an N-type doping region 16, a shallow P-type doping region 18, a deep P-type doping region 20, and a source region 22.
The stacked gate 14 includes a control gate 13 and a floating gate 15 under the control gate 13. The N-type doping region 16 is formed between the first field oxide layer 12 and the stacked gate 14. The shallow P-type doping region 18 is formed next to the N-type doping region 16 and under the stacked gate 14. The deep P-type doping region 20 and the shallow P-type region 18 are doped with the same type of dopants. The deep P-type doping region 20 is formed under the N-type doping region 16 and is in contact with the first field oxide layer 12 and also the shallow P-type doping region 18. The deep P-type doping region 20 functions as a P well and its well depth is much deeper than the well depth of the shallow P-type doping region 18. The deep P-type doping region 20 and the N-type doping region 16 are electrically connected which functions as a drain terminal of the flash memory cell 10. The source region 22, functioning as a source terminal of the flash memory cell 10, is formed next to the shallow P-type region 18. Additionally, under the source region 22 a lightly doped region 24 is formed which is doped with the same type of dopants like the source region 22 but with a lighter density.
The programming method of the flash memory cell 10 will be explained below. When programming the flash memory cell 10, a word line voltage VWL=xe2x88x9210 V is applied to the control gate 13, a bit line voltage VBL=5 V is applied to the drain terminal, i.e. the shorted N-type doping region 16 and the deep P-type doping region 20, and no voltage is applied to the source terminal 22 so as to make it floating. Under this programming condition, electrons will eject from the floating gate 15 to the drain terminal due to the edge Fowler-Nordheim effect thereby achieving the effect of programming the flash memory cell 10.
However, in the above conventional programming method, a series of flash memory cells are programmed in a cell-by-cell sequence. As shown in FIG. 2, two flash memory cells 30 and 32 arranged in parallel are shown. Typically, it takes about 4ms to complete the programming of one flash memory cell when a bit line voltage VBL=5 V is applied to the flash memory cells 30 and 32. If 10 parallel flash memory cells are to be programmed, it will take 40 ms (10*4 ms) to complete the programming job. It means a great deal of time is needed when using the conventional programming method. Consequently, there is a need to provide a more effective flash memory structure and programming method.
Accordingly, it is the primary objective of the present invention to provide a new channel write/erase flash memory cell structure and also a new programming method.
In another aspect, the present invention provides a programming method in which a parasitic capacitor is used to temporally store bit line data to significantly increase the programming speed.
In one further aspect, the present invention provides a method of forming the aforementioned channel write/erase flash memory cell structure.
To achieve these and other advantages and in accordance with the purpose of the claimed invention, as embodied and broadly described herein, the present invention provides a channel write/erase flash memory cell structure capable of providing a pseudo-dynamic programming method. The structure includes a substrate of first conductivity type, a deep ion well of second conductivity type, an ion well of first conductivity type, a first oxide layer, a stacked gate, a doping region of first conductivity type, a shallow doping region of second conductivity type, and a deep doping region of second conductivity type.
The deep ion well of second conductivity type is formed in the substrate. The ion well of first conductivity type is positioned above the deep ion well of second conductivity type to create a parasitic capacitor during programming. The first oxide layer is formed on the substrate above the ion well of first conductivity type. The stacked gate is formed next to the first oxide layer and over the ion well of first conductivity type. The doping region of first conductivity type is positioned under the first oxide layer and on one side of the stacked gate to function as a drain. The shallow doping region of second conductivity type is formed next to the doping region of first conductivity type and under the stacked gate. The deep doping region of second conductivity type is positioned under the doping region of first conductivity type and is in contact with the shallow doping region of second conductivity type.
In the preferred embodiment of the present invention, the first conductivity type is N type and the second conductivity type is P type. The first oxide layer extends into the stacked gate with a decreasing oxide thickness for reducing interference during operation.
Further, a source doping region is formed next to the shallow doping region of second conductivity type and under the first oxide layer to function as a source terminal. The doping region of first conductivity type and the source doping region are doped with VA elements such as phosphorus. The shallow doping region of second conductivity type and the deep doping region of second conductivity type are both doped with IIIA elements such as boron.
Furthermore, the doping region of first conductivity type and the deep doping region of second conductivity type are short-circuited together by using, for example, a metal contact penetrating through the doping region of first conductivity type to the deep doping region of second conductivity type, or, alternatively, by using a metal contact formed across exposed doping region of first conductivity type and the deep doping region of second conductivity type.
Additionally, the present invention provides a method of forming a channel write/erase flash memory cell capable of performing a pseudo-dynamic programming method. The structure is formed by providing a substrate of first conductivity type, and then forming a deep ion well in the substrate. Next, an ion well of first conductivity type is formed in the deep ion well of second conductivity type. A first oxide layer is then formed over the ion well of first conductivity type. A stacked gate is formed later partially over the first oxide layer. A doping region of first conductivity type acting as a drain is formed under the first oxide layer and next to the stacked gate. A shallow doping region of second conductivity type is formed next to the doping region of first conductivity type and under the stacked gate. A deep doping region of second conductivity type is formed under the doping region of first conductivity type and is in contact with the shallow doping region of second conductivity type.
The method according to the present invention further includes a source doping region acting as a source terminal formed next to the shallow doping region of conductivity type and under the first oxide layer. A metal contact is formed to short-circuit the doping region of first conductivity type and the deep doping region of second conductivity type. Or, a metal contact can be formed across the exposed doping region of first conductivity type and the deep doping region of second conductivity type so that these two regions can be short-circuited together. In one preferred embodiment according to the present invention, the substrate and the ion well of first conductivity type are both doped with N type dopants, and the deep ion well of second conductivity type is doped with P type dopants. To avoid interference during operation, the first oxide layer has a thickness that is thinner under the central part of the stacked gate and is thicker at two sides of the stacked gate.
Additionally, the present invention provides a pseudo-dynamic programming method for programming the channel write/erase flash memory cell. When programming, a word line voltage VWL, a source line voltage VSL, and a bit line voltage VBL are applied respectively to control gate, source terminal, and drain terminal of the flash memory cell. An N well, a deep P well and an N substrate are positioned in order under the flash memory cell. A well voltage VP is applied to the deep P well. The N well and the deep P well constitute a parasitic capacitor when programming the flash memory cell.
When performing an erase operation, the word line voltage VWL is in a high voltage level, the source line voltage VSL is in a voltage level relatively lower than the word line voltage VWL, and the bit line voltage VBL is floating. The well voltage VP and the source line voltage VSL are the same. When performing a programming operation, the word line voltage VWL is in a low voltage level, the bit line voltage VBL is in a voltage level relatively higher than the word line voltage VWL, and the source line voltage VSL is floating. The well voltage VP is in a voltage level higher than the word line voltage VWL but lower than the bit line voltage VBL.
When performing a read operation, the word line voltage VWL is in a high voltage level, the source line voltage VSL is in a voltage level relatively lower than the word line voltage VWL and the bit line voltage VBL is in a voltage level relatively lower than the source line voltage VSL. The well voltage VP is in a voltage level lower than the source line voltage VSL.

Channel write/erase flash memory cell and its manufacturing method


A circuit and method for generating write compensated write data signals in magnetic data recording. The circuitry is programmable to enable generation of write compensation meeting a variety of write compensation specifications. In particular, the circuitry can be programmed to generate extra write pulses, to adjust the pulse width and to adjust the pulse spacing within data cells. In an example embodiment, an input waveform drives a reset input on a state machine. An output waveform shape is stored as a pattern of bits in a register. The state of the state machine determines which register bits are selected by a multiplexer for output as a new write compensated write data signal.

In general, in digital recording, information is encoded in the spacing of magnetic polarity reversals. During the reading process, the polarity reversals are converted into voltage pulses, so that the information in the read signal is encoded in the spacing of pulse peaks. Therefore, for data integrity, the accuracy of the timing of the peaks in the read signal is critical. There are, however, inherent distortions of the read signal that must be accommodated.
Binary information on magnetic disks and tapes is stored by magnetizing small areas of the magnetic surface with one of two polarities. For flexible disks and tapes, the small magnetized areas are typically recorded primarily longitudinally (in the plane of the surface). Although the magnetized areas are primarily longitudinal, they also have an unavoidable partial vertical component (perpendicular to the surface). During reading, a magnetic coil in a read head intersects magnetic fields from the small magnetized areas. As the head passes through the fields, a transition from one polarity to the opposite polarity results in a changing field that in turn induces a changing current in the coil of the read head. The changing current typically drives a resistive load to provide a voltage signal. Ideally, for purely longitudinal magnetization, an isolated transition from one polarity to the opposite polarity results in a perfectly symmetrical voltage pulse. Ideally, for purely vertical magnetization, an isolated transition from one polarity to the opposite polarity results in a perfectly symmetrical dipulse (a pulse of one polarity followed by a pulse of the opposite polarity). The combined longitudinal and vertical components result in an asymmetrical voltage pulse. The asymmetry is sometimes referred to as a peak shift. As bit densities increase, the transitions are no longer isolated. In particular, if two adjacent write transitions are very close together, the combined effects of peak shift and adjacent pulses make the time between read pulses on read-back longer than the time between the transitions during writing.
Given a particular digital pattern in the write waveform, it is possible to predict some of the resulting distortion in the read waveform. It is then possible to distort the writing signal (called precompensation or write equalization) to make the resulting read signal closer to ideal. For example, if two adjacent write transitions are very close together, then the first transition may be written late and the second transition written early. As a result, the time between transitions during writing is shorter than the ideal time and the time between pulses during read back is equal or closer to the ideal time. Alternatively, the shape of the analog read signal can be affected by inserting extra pulses in the write waveform. Typically, the frequency response of the magnetic head is such that these extra pulses do not result in complete polarity reversals in the surface of the data storage medium, but instead the fields on the magnetic medium are slightly modified (write equalized) to compensate for distortion and noise in the resulting read signals. For additional general background, see R. J. Schneider, "Write equalization in high-linear-density magnetic recording," IBM J. Res. Develop., vol. 29, No. 6, 563-568 (November 1985).
Many removable-medium drives are adapted to accept a variety of magnetic media. Typically, different media types require different write equalization parameters. For example, flexible disk drives may accept flexible disks having two different recording densities. Likewise, tape drives may accept multiple types of tape. In some cases, after a particular drive has been shipped, a new magnetic medium may become commercially available having a new higher bit density or a different encoding pattern and therefore requiring different specifications for write compensation. In that case, it would be useful to be able to program the write equalization circuitry to accommodate the new media. There is an ongoing need for write equalization circuitry that can be programmed to accommodate a variety of equalization specifications.

Programmable write equalization for magnetic data recording


This invention is related to a method for shaping profile an extrudable plastic material attached to a surface. In the process, a die being part of a cylinder and having a shape corresponding to the desired cross-section of the profile is introduced into the plastic material and is then extracted therefrom by rolling the cylinder. The invention is also related to a device for carrying out the process.

It is known to provide articles of various types with a frame-shaped sealing profile of polymer, and in particular of elastomer, by extruding a profiled member of extrudable material directly onto the article. For automobile panes, in particular, processes of this class are widely used. To do this, extrudable systems are used which polymerize or cross-link, such as systems of humidity-hardening polyurethane, and also thermoplastic elastomers. Processes of this class are described in detail for example, in European Patents EP-A-0 421 833 and EP-A-0 524 092.
When a profiled frame, closed on itself, is applied by extrusion onto the surface of an object, it is necessary to post-shape or finally shape the junction between the start of the extruded profiled cord and its end, because an accumulation of the viscous material inevitably takes place with a more or less undefined form. For post-shaping this undefined transition zone, various processes and devices are known.
According to a method known from DE 40 25 166 A1, in which a profiled polyurethane cord is applied by extrusion onto a surface, the extruded cord is allowed to harden, a portion of the cord is removed from the position of the transition, and a corresponding portion of a profiled cord which has already hardened is glued at this position.
According to another method known from EP-A-524 060, a portion of the profile is also removed by mechanical means after it has hardened. Then a calibrated mould, covering the two contiguous ends of the frame-shaped profile, is placed at this position and a polymer that hardens relatively rapidly is injected into the mould and hardened to complete the profiled frame.
In addition, it is known to post-shape the profiled frame at the transition position during the extrusion and before the polymer has hardened, by using tools that shape by compression. A tool known from EP-B-421 833 is composed of a lower plate, in which a moulding cavity is formed and which can be in one or more pieces. The upper compression plate is lowered onto the lower moulding plate, where it forms the profile.
A process of this type, well known and described in DE 90 115 73 U1, serves for the post-shaping of a profiled cord constituted of a reactive system based upon polyurethane and extruded and applied onto a pane. In this process, the mould is composed of a device equipped with two jaws, which is guided in the open position from the outside above the peripheral part of the pane, equipped with the profiled cord. The pivoting axis of the two jaws is disposed outside the object. After the positioning of the device of the mould, in which the surface of the pane in relation to the profiled cord is disposed in a corresponding recess of the one of the jaws, the other jaw, which imprints its form onto the cord, pivots around the pivot axis and is pressed onto the cord.
In the case in which the cord possesses a groove with an undercut or back-cut, the above-mentioned processes for post-shaping before hardening are not suitable. The same is true when the wall of the groove is fluted on one side where the wall closes in. These two arrangements are common when, as in the document EP-B-258 128, a reversible fixing is desired of an automobile pane into an opening of the bodywork. In this case, the engagement between the positioning mastic and the profiled frame is made without gluing solely on account of the shape of the groove of the profiled frame onto which the mastic engages. But by the same token, if a traditional die is used for shaping the groove, it will be impossible to remove it before hardening without definitively deforming the profile.

Process and device for shaping an extrudable plastic material


A high power optical element streetlamp using a thermocouple includes a body unit, a lamp head unit, and a power supply unit fixed to the body unit. The lamp head unit includes a circuit board connected to the power supply unit, at least one optical element installed on the lower surface of the circuit board, a molding, and a heat dissipation plate installed on the upper end of the circuit board and including a plurality of heat dissipation fins to dissipate heat generated and transmitted from the at least one optical element and the circuit board. The thermocouple is arranged in the shape of a checkerboard on the surfaces of the heat dissipation fins and converts dissipated heat into thermoelectromotive force, and forming junctions where two kinds of metals having different thermal conductivities intersect to generate thermoelectric current is formed on the heat dissipation plate.

In general, applications of optical elements including light emitting diodes (LEDs) as next generation illumination sources have been gradually increased. Among these, an LED is a kind of semiconductor element which converts electrical energy into light energy using characteristics of a semiconductor formed of a specific compound, has high light conversion efficiency and thus achieves energy consumption reduction of up to 90% at maximum as compared with conventional illumination, such as incandescent lamps and fluorescent lamps, has a small size and is thus proper for miniaturization and lightweight trends, is capable of being infinitely expanded, and has a semi-permanent lifespan.
Further, since the LED has advantages that it does not execute thermal light-emission or discharge light-emission and does not require pre-heating and thus has fast response time and a simple lighting circuit, and does not use a discharge gas and a filament and thus has high impact resistance and is safe, scarcely causes environment pollution, executes high repetition pulse operation, decreases fatigue of the optical nerve and executes full color realization, the LED is widely used in various digital products or home appliances and peripheral devices. Particularly, as a high luminance LED solving a low luminance problem of the conventional LED comes onto the market, purposes and usages of the LED are expanded.
Particularly, since a white LED is very useful as indoor and outdoor illumination, the frequency of use of the white LED is rapidly expanding and it is predicted that the white LED will dominate the illumination market soon because the government promotes a plan of raising the supply rate of the white LED in consideration of high energy efficiency and environmentally friendly advantages of the white LED together with a tendency to replace incandescent lamps with fluorescent lamps.
Given the rapid speed of development of techniques using LEDs, it is judged that LEDs will graft onto streetlamps installed on a road through which persons and vehicles pass and used to allow pedestrians and vehicles to efficiently walk on and pass through the road at night.
Conventionally, illumination lamps for streetlamps are formed of a heavy metal harmful to the human body, such as halogen or mercury, and these lamps have a short lifespan and are periodically replaced and thus require considerable expenditure and effort for maintenance and repair. Therefore, high power LED lamps reducing power consumption and having excellent illumination performance are widely used now. The high power LED lamps have a long lifespan and remarkably reduce power consumption to save energy while having high brightness as compared to a general halogen or mercury lamp.
However, the high power LED lamps generate high heat in operation, and such heat influences peripheral parts as well as the high power LED lamps and thus may cause malfunction thereof or reduction in the lifespan thereof.
That is, an optical element using light sources, such as LEDs, is essentially a semiconductor element, and is thus relatively weak to heat as compared to light emitting elements, such as incandescent lamps or fluorescent lamps. Therefore, when junctions within the semiconductor element maintain a constant temperature, the semiconductor element may maintain the original advantages thereof, such as high light emitting efficiency and long lifespan. That is, in case of an LED, the LED may maintain the original advantages thereof if the temperature of junctions of the semiconductor element maintains 85° C. or less always.
Therefore, research on techniques relating to optical elements, such as LEDs, to improve light emitting efficiency of LED chips and to efficiently extract the light emitting efficiency and research on application of optical element light sources to various fields have been conventionally carried out. However, as heat generated from an optical element during driving directly influences optical efficiency of the optical element light source and the optical element is applied to high power lamps, problems due to generated heat become serious.
Accordingly, a structure of an optical element in which a heat dissipation plate serving to dissipate heat generated during driving of the optical element is connected to a semiconductor element has been proposed.
In relation to such a heat dissipation plate applied to LEDs, Korean Utility Model Registration No. 20-0448163 discloses a heat dissipation plate for LED lamps which is installed on an LED lamp. Such a heat dissipation plate for LED lamps includes at least one heat dissipation fin connected to a case of the lamp and formed on the upper portion of the heat dissipation plate to have a sufficient heat dissipation area, a support to fix a circuit board on which at least one LED is mounted, at least one connection fixing groove formed on the lower portion of the heat dissipation plate so that the support is inserted into the at least one connection fixing groove, and a fixing screw to fix the circuit board to the support, the support includes at least one screw hole formed at a designated interval along the center of the support, the circuit board includes at least one tightening hole formed along the center of the circuit board so as to correspond to the at least one screw hole of the support, the at least one LED is arranged between the at least one tightening hole and is installed integrally with the heat dissipation plate for LED lamps by fixing the circuit board to the support by combining the fixing screw with the at least one screw hole and the at least one tightening hole, the at least one heat dissipation fin is formed integrally with the at least one connection fixing groove, and the heat dissipation plate for LED lamps is formed of an extruded product using aluminum and may thus minimize heat resistance and maximize heat dissipation effect.
Further, in relation to a streetlamp to which LEDs and a heat dissipation plate are applied, Korean Utility Model Laid-open Publication No, 20-2008-0003317 discloses a cooling apparatus of a high power LED lamp streetlamp having an LED lamp assembly provided with a plurality of high power LED lamps. Such a cooling apparatus includes a thermally conductive heat collecting plate provided with an adhesive surface attached to one surface of the LED lamp assembly opposite the high power LED lamps and including a receipt groove part formed on the other surface of the heat collecting plate, a heat exchange tub combined with the receipt groove part of the heat collecting plate and accommodating a liquid heat medium executing heat exchange with the thermally conductive heat collecting plate, and a plurality of thin heat dissipation plates separated from the outer circumferential surface of the heat exchange tub by a designated interval and executing heat exchange with the heat medium in the heat exchange tub, and increases exchange and dissipation performance and efficiency of high heat generated from the LED lamps, thus improving cooling performance of the LED lamps and preventing malfunction of the lamps and peripheral parts or reduction of lifespans thereof due to heat.
However, the above-described conventional heat dissipation plates merely exhibit a function of dissipating heat, generated from semiconductor elements due to light emission of optical elements, to the outside, and such heat is only dissipated to the outside but is not used as energy. Recently, as problems due to lack of resources become more serious, solutions to conserve resources are urgently required and development of techniques to improve requirements for using waste heat inevitably generated in the optical element field having a high application degree are required.

This patent is subject to a terminal disclaimer.

High-power optical element street lamp using thermocouple


A communication device according to an embodiment includes: a processor configured to execute a media clock for generating a frame synchronization signal having a frequency which is m times a sampling frequency; a first interface configured to output 2m-channel audio data to a DAC or receive an input of the 2m-channel audio data from an ADC, in synchronization with the frame synchronization signal; and an external counter configured to generate a frequency-divided frame synchronization signal obtained by 1/m-frequency division of the frame synchronization signal and output the frequency-divided frame synchronization signal to the DAC and the ADC.

An AVB (audio video bridging) network system, for example, has been used in an in-vehicle infotainment system. The AVB network system uses an Ethernet line and transfers video data, audio input/output data, and warning data using an Ethernet (registered trademark, the same shall apply hereinafter) frame.
However, in the in-vehicle infotainment system, there is a tendency that not only the amount of video data to be handled but also the amount of audio data to be handled increases. Therefore, a system using a TDM (time-division multiplexing) interface (TDM I/F) capable of transferring 8-channel data or 16-channel data per line has been commercialized.
On the other hand, an example of an interface for audio data includes I2S (inter-IC sound) interface (I2S I/F) used to serially transfer digital audio data between ICs. Since the I2S interface can transfer data of at most 2 channels (specifically, L channel and R channel in 2-channel stereo) per line, it is difficult to handle multi-channel audio data only with the I2S interface.

Communication device, communication system, communication method, and recording medium

Toshiba Electronic Devices & Storage Corporation


An aircraft (100) includes a body (10) and an outer frame (1) rotatably coupled to the body (10). The body (10) includes a plurality of rotary blades (15a-15d) and a driver (14a-14d) configured to rotate the plurality of rotary blades (15a-15d). The outer frame (1) includes a rotary frame (1a-1c) rotatable about a rotation axis intersecting the direction of gravity, and a center of gravity of the plurality of rotary blades (15a-15d) and the driver (14a-14d) is located lower than the rotation axis in the direction of gravity.

Certain road-related public infrastructure, such as tunnels and bridges, were built during the period of high economic growth and are now aging. Such road-related public infrastructure requires appropriate maintenance and periodic inspection for continued safe use thereof. To facilitate inspection of less accessible structures, such as high places and confined areas (e.g., side faces and back faces of bridges), there are methods for remotely piloting an unmanned aircraft (drone) equipped with a camera and inspecting the structure using an image acquired with the camera.
However, if a rotary blade of such a remotely piloted aircraft contacts an external object (an obstacle) and the remotely piloted aircraft collides with the obstacle, the attitude or the trajectory of the aircraft can be significantly disturbed. To prevent such disturbance, for example, Patent Document 1 discloses a remotely piloted aircraft having a rotary frame.

Aircraft, flight system, and structure inspection system


A display device includes a first substrate having formed thereon a plurality of video signal lines and a plurality of gate signal lines, a plurality of pixel electrodes, a plurality of thin film transistors, and a plurality of pixels. Each pixel includes a pixel electrode of the plurality of pixel electrodes and a thin film transistor of the plurality of thin film transistors. The thin film transistor includes a semiconductor layer, a drain electrode electrically connected to a drain signal line, and a source electrode electrically connected to the pixel electrode. The semiconductor layer has an outline so that a nearest portion to a center of the pixel is positioned under the source electrode in plan view.

1. Field of the Invention
The present invention relates to a liquid crystal display device and, more specifically, to a liquid crystal display device in which a pair of insulating substrates are opposed to each other via a predetermined gap that is maintained by spacers, a liquid crystal composition (a liquid crystal molecule) is held in the gap, and a storage capacitor portion is formed in each pixel region.
2. Description of the Related Art
High-resolution liquid crystal display devices capable of color display for use in notebook-sized computers and computer monitors are now widely utilized.
Basically, in this type of liquid crystal display device, what is called a liquid crystal panel is formed by holding a layer of a liquid crystal composition between two insulating substrates (hereinafter also referred to simply as substrates) such as glass plates at least one of which is transparent. This type of liquid crystal display device is generally classified into a type (simple matrix type) in which an image is formed by changing the orientation directions of liquid crystal molecules of desired pixels by selectively applying voltages to various electrodes for pixel formation that are formed on the insulating substrates of the liquid crystal panel and a type (active matrix type) in which various electrodes for pixel formation and active elements for pixel selection are formed and an image is formed by changing the orientation directions of liquid crystal molecules of desired pixels by making selections from the active elements.
In general, the active matrix liquid crystal display device employs that is called a vertical electric field type in which electric fields are developed between electrodes formed on one substrate and an electrode formed on the other substrate.
On the other hand, the liquid crystal display device of what is called a lateral electric field type (also called as In-Plane Switching type, abbreviated as "IPS type" hereinafter) has been put into practical use in which the directions of electric fields that act on the liquid crystal layer are approximately parallel with the substrate surfaces. In an example of the lateral electric field type liquid crystal display device, a very wide viewing angle is obtained by forming comb-teeth electrodes for electric field formation on one of the two substrates.
In the lateral electric field liquid crystal display device, an active matrix substrate is provided with scanning signal lines and video signal lines, switching elements formed in the vicinity of the crossing points of the scanning signal lines and the video signal lines, pixel electrodes to which drive voltages are applied via the respective switching elements, and counter electrodes that are formed in the same plane as the pixel electrodes. A color filter substrate is provided with a black matrix made of a resin composition and color filter layers formed for each pixel in an opening region of the black matrix. A liquid crystal panel is formed by holding a liquid crystal composition between the active matrix substrate and the color filter substrate. The liquid crystal display device is configured in such a manner that a backlight is disposed in the rear of the liquid crystal panel and a unified structure is obtained by using top and bottom cases.
Image display is performed by changing the light transmittance of the liquid crystal compound by electric field components that are formed between the pixel electrodes and the counter electrodes so as to extend approximately parallel with the substrate surfaces.
In contrast to the vertical electric field type one, the lateral electric field type liquid crystal display device is superior in viewing angle; that is, it allows a user to view a clear image even when he is located at a position that forms a large angle with the display screen.
The liquid crystal display device having the above configuration is disclosed in Japanese Unexamined Patent Publication No. Hei. 6-160878 and its counterpart U.S. Pat. Nos. 5,598,285, and 5,737,051, for example.
FIG. 1 is a plan view showing one pixel, a light shield region of a black matrix BM, and its vicinity of a conventional lateral electric field type liquid crystal display device.
As shown in FIG. 1, each pixel is provided in a region enclosed by four signal lines that cross each other, that is, a scanning signal line (gate signal line or horizontal signal line) GL, a counter voltage signal line CL, and two adjacent video signal lines (drain signal line or vertical signal line DL.
Each pixel includes a thin-film transistor TFT, a storage capacitor portion Cstg, a pixel electrode PX, and an counter electrode CT. In FIG. 1, a plurality of scanning signal lines GL and counter voltage signal lines CL are provided at the top and bottom of the pixel direction so as to extend in the right-left or horizontal direction. A plurality of video signal lines DL are provided at the right-left side of the pixel so as to extend in the top-bottom or vertical direction. The pixel electrode PX is connected to the thin-film transistor TFT, and the counter electrode CT is integral with the counter voltage signal line CL.
The pixel electrode PX and the counter electrode CT confront each other, and display is controlled by modulating transmission light or reflection light by controlling the orientation state of a layer of a liquid crystal composition LC (hereinafter also referred to simply as a liquid crystal or a liquid crystal layer) by means of an electric field developed between the pixel electrode PX and the counter electrode CT. Each of the pixel electrode PX and the counter electrode CT assumes a comb-teeth shape and has long and narrow portions extending in the top-bottom or vertical direction in FIG. 1.
The pixel electrode PX and the counter electrode CT are formed in such a manner that the number P of comb-teeth portions of the pixel electrode PX and number C of comb-teeth portions of the counter electrode CT in one pixel necessarily satisfy a relationship C=P+1 (in FIG. 1, C=2 and P=1). The comb-teeth portions of the counter electrode CT and those of the pixel electrode PX are arranged alternately so as to have the comb-teeth portions of the counter electrode CT arranged adjacent to the video signal lines DL. With this structure, shielding from electric lines of force originating from the video signal lines DL can be effected by the counter electrode CT so that electric fields between the counter electrode CT and the pixel electrode PX are not influenced by the electric fields originating from the video signal lines.
The potential of the counter electrode CT is stable because it is always supplied with a potential externally via the counter voltage signal line CL. Therefore, the counter electrode CT has almost no potential variation even if it is adjacent to the video signal lines DL. Further, the above structure makes the geometrical position of the pixel electrode PX more distant from the video signal lines DL, whereby the parasitic capacitances between the pixel electrode PX and the video signal lines DL are greatly reduced and hence a variation of a pixel electrode potential Vs due to video signal voltages can be controlled.
As a result, vertically extending crosstalk lines (an image quality failure called vertical smears) can be prevented.
In a specific construction, widths Wp and Wc of the pixel electrode PX and the counter electrode CT, respectively, are set at 6 μm, which is sufficiently larger than 4.5 μm which is the maximum setting thickness of a liquid crystal layer (described later). It is desirable that the electrode widths Wp and Wc be sufficiently larger than 5.4 μm because it is preferable to provide a margin of 20% or more in view of processing variations in manufacture. As a result, electric field components parallel with the substrate surfaces that are applied to the liquid crystal layer become stronger than those perpendicular to the substrate surfaces, which prevents voltages for driving the liquid crystal to become unduly high. It is preferable that the maximum values of the electrode widths Wp and Wc be smaller than an interval L between the pixel electrode PX and the counter electrode CT. This is because it the interval between the electrodes is too short, electric lines of force are curved sharply and hence regions where electric field components parallel with the substrate surfaces are stronger than those perpendicular to the substrate surfaces are made larger, as a result of which the electric field components parallel with the substrate surfaces cannot be applied to the liquid crystal layer efficiently. To give a margin of 20% to the interval L between the pixel electrode PX and the counter electrode CT, it is necessary that the interval L be larger than 7.2 μm. For example, in a case of constructing a liquid crystal display device having a diagonal size of about 14.5 cm (5.7 inches) and a resolution of 640×480 dots, an interval L that is larger than 7.2 μm can be realized by setting the pixel pitch at about 60 μm and dividing each pixel into two parts.
To avoid disconnection, the electrode width of the video signal lines DL is set at 8 μm, which is somewhat larger than the widths of the pixel electrode PX and the counter electrode CT. To avoid short-circuiting, an interval of about 1 μm is provided between the video signal lines DL and the counter electrode CT. The video signal lines DL and the counter electrode CT are provided in different layers by forming the video signal lines DL and the counter electrode CT above and below a gate insulating film, respectively. On the other hand, the interval between the pixel electrode PX and the counter electrode CT is changed in accordance with the liquid crystal material used, for the following reason. The electric field intensity for attaining the maximum transmittance depends on the liquid crystal material. To obtain the maximum transmittance within the range of the maximum amplitude of a signal voltage that is set by the breakdown voltage of a video signal driver circuit (signal-side driver) used, the electrode interval needs to be set in accordance with the liquid crystal material. The electrode interval becomes about 15 μm when a liquid crystal material that will be described later is used.
In the example configuration being discussed, in a plan view of FIG. 1, a black matrix BM surrounds an opening of the pixel and is formed on the gate line GL, the counter voltage signal line CL, the thin-film transistor TFT, and the drain lines DL, and between the counter electrode CT and the drain lines DL. The storage capacitor portion Cstg is located outside the opening of the black matrix BM (i.e., outside the pixel region) and is composed of the pixel electrode PX, the counter voltage signal line CL, and an insulating film formed between them.
In the liquid crystal display device, an alignment film is applied after formation of the respective electrodes and electrode wiring lines, protective films, and insulating films and is given a liquid crystal alignment control ability by being subjected to a treatment called rubbing.
In the conventional lateral electric field type liquid crystal display device, since the storage capacitor portion Cstg is formed outside each pixel region, there is no large height change or steps in the pixel region and hence the alignment film in the pixel region can be given a uniform liquid crystal alignment control ability.
However, in recent years, liquid crystal display devices have been proposed in which the aperture ratio of the entire screen is increased by forming the storage capacitor portion Cstg in each pixel region. In those devices, the storage capacitor Cstg produces large steps in the pixel region and those steps may cause an alignment defect in a rubbing treatment. As a result, what is called a domain occurs and causes display unevenness.
In particular, alignment defects of the above kind occur frequently in a case where the multilayered film structure that constitutes the storage capacitor portion Cstg has steps extending perpendicularly or approximately perpendicularly to the alignment direction (rubbing direction) of the alignment film. When such an alignment defect occurs, the liquid crystal does not operate normally in the vicinity of the storage capacitor portion Cstg, to cause a domain. This results in a problem that the contrast is lowered and display unevenness occurs, which means a marked reduction in image quality.

Liquid crystal display device having particular semiconductor layer


A redundant communications scheme for a protective relay which allows high-speed, reliable, and fault tolerant communications between peer protective devices in a power distribution network. Communications over a selectable primary communication channel are interrupted and switched to a secondary communication channel, which can operate according to a different communication protocol, when a fault is detected on the primary communication channel. The fault detection and switching is performed transparently to the main protective relay processor.

To further enhance protective control of electrical power distribution systems, intelligent protective relay devices have been developed which are provided with communication capabilities to communicate protective relay data. To date, network communication capabilities have been implemented using data rates of less than 1 Megabits per second, and using RS-485, RS-232, fiber optic asynchronous serial interfaces, or UART interfaces. Typically, communication among networked protective relays has been implemented using "master-slave" protocols, in which certain network devices are prioritized. For example, U.S. Pat. No. 4,972,290 to Sun et al. discloses an electrical power distribution system with remote monitoring and control of protective relays. The disclosed system includes slave stations which continuously monitor activity of analog protective relays, and a master station which communicates with the slave monitoring stations and stores network relay data. The Sun patent also discloses communication of relay data via RS-232 communication channels.
While the desire for protective relays having communications capabilities has been recognized, there are shortcomings associated with known schemes for communicating protective relay information. For example, known relay communication schemes do not adequately address potential problems relating noise (e.g., due to electromagnetic interference) and communication line faults, and do not adequately provide high speed (greater than 1 Mbps) communication capability. Further, the environment in which intelligent protective relays operate is subject to severe conditions, including relatively wide temperature variations, which presents design challenges for potential solutions to the problem of providing a reliable, fault-tolerant, high-speed communications scheme for protective relays.

Redundant communications in a protective relay


A resin mixture including a composition containing polypropylene that includes a portion insoluble in xylene, an isotactic pentad fraction of not less than 96.5% and an isotactic average chain length of not less than 90, 45.about.70 parts by weight; a polyolefin resin, 5.about.20 parts by weight; an inorganic filler selected from precipitated calcium carbonate, hydrated silicic acid, and hydrated calcium silicate, 5.about.30 parts by weight; and an inorganic filler selected from talc, mica, and potassium titanate, 5.about.30 parts by weight; is superior in scratch resistance, moldability, and balance of rigidity and impact resistance. In addition, a laminate having a layer of this mixture has superior gloss. This mixture and the laminate are useful in automobile parts, electric and electronic parts, packaging materials, etc.

1. Field of the Invention
The present invention relates to a propylene resin composition and molded articles thereof which are superior in scratch resistance, moldability, and balance of rigidity and impact resistance; and which are suited for use in electric and electronic parts, packaging materials, engineering plastic substitutes, etc.
Furthermore, the present invention relates to a propylene resin laminate which has, in addition to the above properties, a superior gloss.
2. Background Art
Propylene is widely used, for example, in industrial materials for vehicle parts, electric and electronic parts, etc., and in various packaging materials, since it is generally inexpensive, and has the advantages of light-weight characteristics, mechanical strength, heat resistance, chemical resistance, etc.
In recent years, there has been a strong demand for improvements in quality along with increased functionality and reduced costs for these materials.
In addition, there is the problem that the surface gloss of goods is degraded by heating during secondary molding by means of vacuum forming and the like, and therefore use is limited.
As ways to improve the rigidity, impact resistance, heat resistance, etc., of polypropylene, methods have been proposed such as incorporating an ethylene-propylene rubber and a nucleating agent into an ethylene-propylene block copolymer (Japanese Patent Application, Second Publication, No. Sho 60-3420), and incorporating an ethylene-propylene rubber, an ethylene copolymer, and an inorganic filler into an ethylene-propylene block copolymer (Japanese Patent Application, First Publication, No. Hei 4-275351, Japanese Patent Application, First Publication, No. Hei 5-5051, Japanese Patent Application, First Publication, No. Hei 5-98097, Japanese Patent Application, First Publication, No. Hei 5-98098).
In addition, in order to improve the gloss of secondarily molded articles, a laminate comprising a polyolefin composition layer and a surface layer to which organic or inorganic fillers have been added has been proposed (Japanese Patent Application, First Publication, No. Sho 59-165654).
However, in the above-mentioned methods, although some characteristics have been improved, heat resistance and rigidity still have not been adequately improved. In addition, there is the problem that moldability for vacuum forming and the like is inferior. Furthermore, a satisfactory level for the gloss of secondarily molded articles has not been reached.

Propylene resin composition including isotactic polypropylene and polyolefin resin


Treatment fluids and methods of using a treatment fluid for minimizing fluid loss in a wellbore are disclosed. A method may comprise providing a drill-in fluid. The drill-in fluid may comprise an aqueous liquid, a base oil, a polyol, an emulsifying surfactant, and a solid bridging agent. The method may further comprise circulating the drill-in fluid through a drill-string and past a drill bit. The method may further comprise drilling in a reservoir section of a subterranean formation to extend a wellbore in the reservoir section the drill-in fluid is circulated therein.

Many oil and gas wells in unconsolidated or poorly consolidated sandstone formations are completed "open hole," meaning that the well bores do not contain casing or liners. Although this type of completion allows the produced fluids to flow directly into the well bore, it suffers the disadvantage that the sandface is unsupported and may collapse. Also, selective treatments or remedial operations within the reservoir section may be more difficult.
Unconsolidated or poorly consolidated formations generally are high permeability production intervals and are drilled with specialized fluids referred to in the art as "drill-in fluids." In addition to these high permeability production intervals, drill-in fluids also may be used when drilling through other reservoir sections of a wellbore, for example, to minimize damage while maximizing production. A drill-in fluid generally may include particulate solids (e.g., for bridging on the pore throats of the sandstone of the formation); and polymeric components (e.g., for providing viscosity and fluid loss control). Under pressurized downhole conditions, the drill-in fluid may form a filter cake that includes an acid-soluble portion (e.g., calcium carbonate bridging solids) and a polymeric portion on the face of a portion of the subterranean formation. In most instances, once formed, the integrity of the filter cake should be maintained to provide the necessary fluid loss control and hole stability for subsequent operations.
Fluid loss when drilling through reservoir sections, such as high permeability sandstone can be problematic for drill-in fluids. Fluid loss is undesirable as it results in more fluid needing to be pumped, which increases expense. Moreover, the fluid that leaks off into the formation can cause damage to the formation, which may decrease permeability and/or productivity.

Oil-based drill-in fluid with enhanced fluid loss properties


An electrical connector system having a male and female connector. The male connector includes a U-shaped shroud axially surrounding a male terminal having an opening generally perpendicular to the male terminal's longitudinal axis. The female connector includes a female terminal having two openings, one generally parallel with the female terminal's longitudinal axis and another generally perpendicular to that axis. The male and female terminals mate in a parallel configuration having the male terminal axis generally parallel to the female terminal axis or in a perpendicular configuration having the male terminal axis generally perpendicular to the female terminal axis. A connector body holds the female terminal. The connector body defines a locking means that releasably secures the connector body to the shroud in both the parallel and perpendicular mating configurations. The locking means may include a triangular shaped lock tab that engages a similarly shaped lock aperture.

Electrical connection systems may have a wide variety of applications. Some applications may require a straight connection wherein the major axes of the connectors are generally parallel to one another while other applications require a ninety-degree connection wherein the major axes of the connectors are generally perpendicular to one another. Typically these different connector alignments require two different sets of connectors, one set configured for straight connections and a second set configured for ninety-degree connections. Requiring two different sets of connectors may increase manufacturing cost by necessitating two different sets of manufacturing tooling for each set of connectors.
The subject matter discussed in the background section should not be assumed to be prior art merely as a result of its mention in the background section. Similarly, a problem mentioned in the background section or associated with the subject matter of the background section should not be assumed to have been previously recognized in the prior art. The subject matter in the background section merely represents different approaches, which in and of themselves may also be inventions.

Electrical connector system connectable in a straight or right angle configuration


A new class of optical source having a truncated waveguide is provided, where a guided section of a light generating medium is terminated at an angle at a predetermined distance away from one end facet of the waveguide, thereby leaving a section for unguided light propagation. A truncated waveguide when implemented in combination with waveguide tilt, effective front facet reflectivity is reduced significantly to eliminate unwanted facet reflections. By extending electrical pumping in the unguided propagation section, the light in the unguided path propagates to a corresponding end facet without attenuation. The reflected light propagates freely without being intercepted by the waveguide. The principles are incorporated in different types of light generating and amplifying medium including a “double-pass” gain medium for designing optical sources having significantly high output power and negligibly small spectral modulation arising from unwanted facet reflections.

1. Field of the Invention
This invention is in the field of optical source and in particular, in the field of high optical power broadband optical sources free of facet reflections over an extended bandwidth.
2. Description of the Related Arts
Optical sources and in particular high power optical sources having a broad spectral width, are key components in improving performance of many applications such as, OCT (optical coherence tomography), IFOG (interferometric fiber optic gyroscope), high-power illumination, optical sensing, optical spectroscopy, to name just a few. Often times, semiconductor optical sources are preferred for such applications for their low drive current, efficiency and small footprint. A conventional broadband semiconductor light emitting device for example, a Light Emitting Diode (LED) provides very low output power and is not suitable for many of these applications. Alternative edge emitting semiconductor light-generating and amplifying devices, such as Super Luminescent Diodes (SLD) provide higher power output but have a smaller bandwidth. Although these devices may be operated at a high gain, often times spectral quality and in particular, spectral modulation puts a practical limit on the output power.
Most semiconductor optical sources comprise a waveguide structure extending between two parallel end facets, and include a p-n double hetero junction constructed from multiple layers of semiconductor materials of appropriate thickness and composition, on a semiconducting substrate. Light from such an edge emitting device propagates at one or both end facets depending upon the reflectivities of the two end facets. For a waveguide structure to provide a high output power, it needs to be operated at a drive current high enough to produce optical gain in the waveguide medium. However, operating the device at high gain also reduces the bandwidth.
In the past, different waveguide designs have been explored for achieving higher output power from a waveguide light source. In a non-patent literature publication entitled "Low spectral modulation high-power output from a new AlGaAs Superluminescent diode/optical amplifier structure", authored by Alphonse et al. and published in Applied Physics Letters vol. 55 (22), November 1989, pp. 2289-2291, a light source having a tilted waveguide structure is disclosed to exhibit higher output power. A similar design for a SLD is disclosed in the U.S. Pat. No. 4,958,355 issued on Sep. 18, 1999 to Alphonse et al. A tilted waveguide design for this device allows operation at a high gain level without lasing by reducing reflectivity at the end facets of the waveguide. The resulting source provides about 20 mW (milli Watt) of output power, and a spectral modulation of about 1%. While this device may be adequate for certain applications, spectral modulation may still be a limiting factor for applications requiring significantly higher power.
In a different design disclosed in the U.S. Pat. No. 6,339,606 issued on Jan. 15, 2002, to Alphonse, a diamond waveguide structure including multiple tapered sections is disclosed (FIGS. 6 & 7). In this structure the waveguide extended between the two end facets is expanded in the center to achieve higher output power. By placing the waveguide at an angle with respect to one or both end facets, higher output power and low spectral modulation is expected from such a device. However, when operated at high drive current to achieve high output power, the facet reflectivity still contributes significant amount of spectral modulation and reduction in the bandwidth, thereby limiting the utility of such source as a broadband source.
Edge emitting semiconductor optical sources having even high output power and enhanced bandwidth are disclosed in the U.S. Pat. Nos. 8,269,977 and 8,259,304 issued on Sep. 18, 2012, and Sep. 4, 2012, respectively, both to Alphonse. The disclosures of the above mentioned patents are hereby incorporated by reference, in their entirety. More specifically, the optical sources described therein comprise a Semiconductor Optical Amplifier (SOA) and Super Luminescent Diodes (SLD) having a waveguide, and in particular a ridge waveguide disposed between two etched channels at a small angle with respect to end facets of the guiding region.
One important design aspect of said broadband sources is to provide different optical coatings having predetermined reflectivity profile for example, antireflection, raised-edge reflectivity, etc. at the two end facets, resulting in high optical power and extended bandwidth that surpass emission from a SOA or a SLD alone. However, spectral profile of said optical sources exhibits a discrete set of emission lines resembling teeth of a comb. While this type of source is beneficial for certain applications (e.g. OCT), it may not be useful for other applications where a broad spectral profile source having high output power and low spectral modulation is preferable (e.g. IFOG).

Semiconductor light source free from facet reflections


Disclosed is a method for making a film assembly used in a PDP filter positioned on the front surface of a PDP, a film assembly manufactured by the method, and a PDP filter using the film assembly. The method includes providing a roll of an EMI film formed on a surface of a long transparent polymer resin film with a predetermined spacing and mounting the wound roll of the EMI film on a first feed roller; providing a roll of at least one long transparent functional film capable of covering at least partially the effective screen portions of the EMI film and mounting the wound roll of the functional film on a second feed roller which is spaced a predetermined distance from the first feed roller; and integrating the EMI film with the functional film by feeding them into a gap between the first and second compression rollers.

In general, a PDP is an image display device that uses plasma created by gas discharge to display images. It can be manufactured in a flat shape with reduced weight, it can display image on a large screen, and it has excellent viewing angle. Therefore, it is spotlighted as the next-generation image display device.
A PDP filter as shown in FIG. 1 includes a reinforced or semi-reinforced glass 1 having a predetermined size and a film assembly 2 attached to one surface or to the other surface of the glass to generate various effects advantageous to a PDP TV.
The film assembly 2 is made up of at least two films chosen from a group including an EMI (electromagnetic interference) film 3 for shielding electromagnetic waves, an NIR (near infrared) film 4 for preventing near infrared waves from being generated to enable smooth remote control, a color compensation film 5 for compensating for the color of light, and an AR (anti-reflection) film 6 for reducing the surface reflection of external light.
As shown in FIGS. 2 and 3, the EMI film 3 includes a transparent polymer resin film 3a and an effective screen portion 3b having a conductive material formed on the polymer resin film 3a by an etching or deposition process to shield electromagnetic waves.
The conductive material constituting the effective screen portion 3b is opaque metal or metal oxide and is formed in a mesh pattern or a dispersed particle pattern to secure the transparency of the effective screen portion 3b. Respective functional films 4, 5, and 6 laminated on the effective screen portion 3b of the EMI film 3 play the role of preventing the screen from being unclear due to the uneven surface of the effective screen portion 3b, in addition to their own basic function.
Four edges of the EMI film 3 are exposed to the exterior to shield electromagnetic waves generated from the PDP and act as a ground portion 3aa that is grounded to the corresponding surface of the PDP.
However, the functional films attached to the effective screen portion of the EMI film must have a size smaller than that of the EMI film so that the ground portion of the EMI film can be sufficiently grounded to the corresponding surface of the PDP. As a result, the film assembly partially constituting the PDP filter cannot be manufactured in large amounts.
In addition, the functional films which are smaller than the EMI film must be aligned with and attached to the effective screen portion of the EMI film one by one every time a film assembly is manufactured. This process is very inefficient and degrades the productivity.

Method for making film assembly used in PDP filter, film assembly manufactured by the method, and PDP filter with the film assembly


A sensor comprising a silicon substrate having a first and a second surface, integrated circuitry provided on the first surface of the silicon substrate, and a sensor structure provided on the second surface of the silicon substrate. The sensor structure and the integrated circuitry are electrically coupled to each other.

WO 01/84099 (Sensirion AG) discloses a sensor module and a method for the production of the same. The sensor module comprises a thermopile and an electronic evaluation unit integrated into a semiconductor substrate. As the electronic evaluation unit is located on the same substrate as the thermopile, temperature differences can thus be measured with greater accuracy and lower susceptibility to interference.
U.S. Pat. No. 7,154,372 (Sensirion AG) discloses a micromechanical flow sensor with tensile coating. The sensor, in particular a flow sensor, is integrated on a semiconductor device and comprises a measuring element on a membrane.
US 2006/0289981 (Nickerson et al) discloses packaging logic and memory integrated circuits. This document discloses that logic and memory may be packaged together in a single integrated circuit package and that the logic may be stacked on top of the memory which may be stacked on a flex substrate. Such a substrate may accommodate a multi layer interconnection system.
WO 2005/104228 describes a sensor system that includes a sensor device and an integrated circuit for driving the device. The device includes a sensor body of a silicon-based material, an upper sealing member of a silicon-based material, and a lower sealing member of a silicon-based material. The upper sealing member and the lower sealing member are joined together to cooperatively house the body therewithin in an airtight manner. The device and the circuit are formed as a stacked body.
US 2009/0179751 describes a hybrid sensor/communication device and method.
U.S. Pat. No. 7,255,001 describes a thermal fluid flow sensor.
The listing or discussion of a prior published document or any background in the specification should not necessarily be taken as an acknowledgement that the document or background is part of the state of the art or is common general knowledge.