A controller for executing instructions has one the order of five addressing modes and can allow executing of processes concurrently in multiple modes. A specific embodiment can effectively run legacy code written for the Z80 micoprocessor without requiring recompiling of code. An optional embodiment includes autonomous Multiply/Accumulator Engine (MAC) optimized to perform sum-of-products (SOP) operations with little controller overhead, making the invention capable of more effectively handling a number of processing tasks, particularly tasks related to digital signal processing (DSP).

The present invention is in the field of methods and devices for digital processors and processor cores. More specifically, the present invention is directed to an enhanced processor that maintains backwards compatibility with a number of.earlier designs in the same family, including earlier processors with different address space and data widths.
A large literature exists regarding the history of processor development and evolution. A brief summary of this history is presented below. The reader is referred to infopad.eecs.berkeley.edu/CIC /archive/cpu_history.html and its cited documents for more information.
While processors have evolved dramatically over the last several decades, in many design applications and environments there remains an extensive interest in utilizing mature processor designs. Older designs have the advantage of a well-designed tool set, a large base of engineering expertise and familiarity, and in some cases a large investment in software code.
The Z-80 processor is one older processor design in which there remains a large interest. The Z-80 was originally developed to be a successor to the Intel 8080 and was regarded at the time as a vast improvement. Like the 8080, the Z-80 used 8 bit data and 16 bit addressing. The Z-80 could execute all of the 8080 instructions and included 80 additional instructions (1, 4, 8 and 16 bit operations and block move and block I/O). The register set was doubled from the 8080, with two banks of data registers (including A and F) that could be switched between. This allowed fast operating system or interrupt context switches. The Z-80 also added two index registers (IX and IY) and 2 types of relocatable vectored interrupts (direct or via the 8-bit I register). Aspects of the Z80 are described in U.S. patent application No. 4,332,008.
One characteristic that made the Z-80 popular in designs was the memory interfacexe2x80x94the CPU generated its own RAM refresh signals, which meant easier design and lower system cost, the deciding factor in its selection for the Radio Shack TRS-80 Model 1, introduced on Aug. 3, 1977.
Like many processors, the Z-80 featured many undocumented instructions. In some cases, they were a by-product of early designs (which did not trap invalid op codes, but tried to interpret them as best they could), and in other cases chip area near the edge was used for added instructions, but fabrication made the failure rate high. Instructions that often failed were not documented, increasing chip yield. Later fabrication made these more reliable.
After its introduced, many variants of the Z-80 were developed and produced by a variety of manufacturers. A number of these processors were sold with peripheral components included on-chip. More recently, Z80 family processors are developed and distributed as soft-core specifications in a register transfer language (RTL), which can then be combined with other components to produce ASICs.
Hitachi produced the 64180 (1984) with added components (two 16 bit timers, two DMA controllers, three serial ports, and a segmented MMU mapping a 20 bit (1M) address space to any three variable sized segments in the 16 bit (64K) Z-80 memory map).
Zilog produced the Z-180, compatible with Z-80 peripheral chips, plus variants (Z-181, Z-182). The Z-280 was a 16 bit version introduced about July, 1987, with a paged (like Z-180) 24 bit (16M) MMU (8 or 16 bit bus resizing), user/supervisor modes and features for multitasking, a 256 byte (4-way) cache, 4 channel DMA, and a large number of new op codes added (total of almost 3,500, including previously undocumented Z-80 instructions).
A 16/32 bit Z-380 version also exists (1994) with an added 32-bit linear addressing mode that is not Z-80 compatible.
Z380
Another addition to the Z80 family is the Z380. While the Z380 was intended as an advanced 32-bit version of the Z80, with 16 Mb linear addressing, the processor had mixed results. One problem was that Z80 binary code could not run on the 380 without recompiling, therefore Z380 systems were not xe2x80x9cturn-keyxe2x80x9d compatible with software written for the Z80. A further difficulty is that the Z380 mechanisms for extending the capabilities of the Z80 and Z180, while maintaining binary program compatibility, were inconvenient for both assembly-language programmers and C compiler writers, and expanded the code space requirements for both kinds of programs. The Z380""s multi-byte op-code prefixes meant that every time a 24- or 32-bit address or data value was used in an instruction, the instruction not only had to extend by the necessary 8 or 16 bits, but by another 16 bits of xe2x80x9cDDIR prefixxe2x80x9d as well. This has proved to be linear addressing and wider data at too high a price in code size.
Despite all the further developments made in mP design since 1977, there remains continuing interest in Z80-based processing. For many computer control applications, Z80 processing remains a versatile, reliable and inexpensive solution. As a result of this continued interest, a substantial body of tools and support components for the Z80, including emulators, compilers, etc. continues to be distributed. See, for example, the resources listed at www.geocities.com/SiliconValley/Peaks/3938/z80_home.htm.
Zilog, Inc., continues to produce a sell a number processors in the Z80 family. A brief comparison of the features of these processors is presented in the table below. Further information is available at http://www.zilog.com/resources/ z80r.html.
Memory Management
An important enhancement in processor design is the ability to address a large address space. The address space is determined by the number of bits the processor can manipulate and output as an address
Most 8 bit processors are limited to addressing 64k of memory, using two 8-bit words to address each memory location. A 16 bit CPU generally can support 1 to 16 Mb of memory. To support these larger address spaces, the processes generally utilize a memory management unit (MMU) to access an address space larger than 64k, but still maintain compatibility with earlier instruction sets. Under one MMU scheme, all instructions, in all modes, issue 16 bit addresses. The MMU converts these 16 bit addresses to 20 bits.
In such a scheme, physical memory generally refers to the entire universe of memory addressible by the processor. The memory that can be addressed with any one map, or configuration, of the MMU is called the logical address space. In this scheme, every address generated by a user""s program is a logical address and the MMU""s role is to translate these logical addresses into physical ones. On power up, the MMU may translate every logical address to exactiy the same physical address (which simulates the Z80).
In an MMU scheme, address references made by a program is passed through the MMU before being presented to the physical memory space. If the address matches a range previously programmed into the MMU, then the MMU will add an offset to that address, forming the physical address.
Exd Z80
A number of years ago, Zilog purchased the exclusive rights to the Exd Z80 softcore. One advantage of the ExdZ80 was its single clock bus cycles. As implemented and marketed, the core was xe2x80x9cpurexe2x80x9d Z80, even including hidden Z80 instructions from 1975.
While the Z180 family has long advertised 20-bit address capability, its mechanism for achieving this, called the Memory Management Unit or MMU, is difficult to use and has impeded the use of this family into larger-scale applications. One would like to add a 24-bit mode in which the processor automatically fetches longer addresses and data, so that no prefix is required for most instructions.
What is needed is a processor xe2x80x9cbetweenxe2x80x9d the Z18x and Z38x families, that provides 24-bit linear addressing, is more natural and convenient to program than the MMU or 380, and allows more compact programs than the 380.
The present invention is a controller for executing instructions. A controller according to the invention may exist in a wide variety of embodiments, including, but not limited to, an integrated circuit, a part of an integrated circuit, a xe2x80x9csoft-corexe2x80x9d RTL descriptor language module, etc.
In one specific embodiment, a controller according to the invention is designed to maximize compatibility with Z80 and 18x applications at the binary level, while simultaneously minimizing code space and maximizing programming convenience for upgrades and new applications that utilize 24-bit operation.
According to a further embodiment, an instruction set for a controller is basically that of the Z18x family, with some optional new facilities to enable 24-bit addresses and data and further provides a Z80 derivative with 24-bit linear addressing and 24-bit ALU, but an external 8-bit data path.
In a further embodiment, the present invention provides a mP or mP core with multiple modes of memory addressing. These modes are designed to allow for backwards compatibility with legacy processor code. According to the present invention, these modes can operationally coexist, with processes written for different modes sharing the processor under control of a supervising or kernel process.
In a specific embodiment, these modes consist of at least five key modes, which may may be referred to as:
Note that while specific memory address space sizes are given above, the invention may in other embodiments have different memory space sizes.
In one specific embodiment, the invention can include an autonomous Multiply/Accumulator Engine (MAC). This engine is optimized to perform sum-of-products (SOP) operations with little CPU overhead, making the invention capable of more effectively handling a number of processing tasks, particularly tasks related to digitalsignal processing (DSP).
A further understanding of the invention can be had from the detailed discussion of specific embodiments below. For purposes of clarity, this discussion refers to devices, methods, and concepts in terms of specific examples. However, the method of the present invention may operate within a variety of types of logical devices. It is therefore intended that the invention not be limited except as provided in the attached claims.
Furthermore, it is well knowvn in the art that logic systems can include a wide variety of different components and different functions in a modular fashion. Different embodiments of a system can include different mixtures of elements and functions and may group various functions as parts of various elements. For purposes of clarity, the invention is described in terms of systems that include many different innovative components and innovative combinations of components. No inference should be taken to limit the invention to combinations containing all of the innovative components listed in any illustrative embodiment in this specification.
All publications, patents, and patent applications cited or listed herein are hereby incorporated by reference in their entirety for all purposes. The invention will be better understood with reference to the following drawings and detailed description.
FIG. 1 is a block diagram of a processor according to an embodiment of the invention.
FIG. 2 is a block diagram showing pinout of an example processor according to an embodiment of the invention.
FIG. 3 (Table 1) indicates operation of CALL Instruction according to an embodiment of the invention.
FIGS. 4, 4A, 4B (Table 2) indicate operation of RST et al according to an embodiment of the invention.
FIG. 5 (Table 3) indicates which prefix selection affects each (class of) instruction according to an embodiment of the invention.
FIG. 6 (Table 4) indicates register loading to enable a MAC status according to an embodiment of the invention.
FIG. 7 (Table 5) indicates bits indicating MAC status according to an embodiment of the invention.
FIG. 8 (Table 6) indicates State of IEF1 and IEF2 according to an embodiment of the invention.
FIGS. 9, 9A, 9B (Table 7) indicate Processor and Device Pin Descriptions according to an embodiment of the invention.
FIG. 10 (Table 8) indicates Common Base Register (0038H) CBR according to an embodiment of the invention.
FIG. 11 (Table 9) indicates Bank Base Register (0039H) BBR according to an embodiment of the invention.
FIG. 12 (Table 10) indicates Common/Bank Area Register (003AH) CBAR according to an embodiment of the invention.
FIG. 13 (Table 11) indicates Load Instructions according to an embodiment of the invention.
FIG. 14 (Table 12) indicates Arithmetic Instructions according to an embodiment of the invention.
FIG. 15 (Table 13) indicates Logical Instructions according to an embodiment of the invention.
FIG. 16 (Table 14) indicates Exchange Instructions according to an embodiment of the invention.
FIG. 17 (Table 15) indicates Program Control Instructions according to an embodiment of the invention.
FIG. 18 (Table 16) indicates Bit Manipulation Instructions according to an embodiment of the invention.
FIG. 19 (Table 17) indicates Block Transfer Instructions according to an embodiment of the invention.
FIG. 20 (Table 18) indicates Rotate and Shift Instructions according to an embodiment of the invention.
FIG. 21 (Table 19) indicates Input/Output Instructions according to an embodiment of the invention.
FIG. 22 (Table 20) indicates Processor Control Instructions according to an embodiment of the invention.
FIG. 23 (Table 21) indicates Flag Register according to an embodiment of the invention.
FIG. 24 (Table 22) indicates Flag Settings Definitions according to an embodiment of the invention.
FIG. 25 (Table 23) indicates Condition Codes according to an embodiment of the invention.
FIGS. 26A, 26B (Table 24) indicate Instruction Summary according to an embodiment of the of the invention.
FIGS. 27, 27A-27L (Table 25) indicates Op Code Map (1st Op Code) according to an embodiment of the invention.
FIGS. 28A, 28A-1, 29A-2 (Table 26) indicates Op Code Map (1st Op Code) according to an embodiment of the invention.
FIG. 28B shows the organization of the table of FIG. 28A.
FIGS. 29A, 29A-1, 29A-2 (Table 27) indicate Op Code Map (2nd Op Code after OCBH) according to an embodiment of the invention.
FIG. 29B shows the organization of the table of FIG. 29A.
FIGS. 30A, 30A-1, 30A-2 (Table 28) indicate Op Code Map (2nd Op Code After ODDH) according to an embodiment of the invention.
FIG. 30B shows the organization of the table of FIG. 30A.
FIGS. 31A, 31A-1, 31A-2 (Table 29) indicate Op Code Map (2nd Op Code After OBDH) according to an embodiment of the invention.
FIG. 31B shows the organization of the table of FIG. 31A.
FIGS. 32A, 32A-1, 32A-2 (Table 30) indicate Op Code Map (2nd Op Code After 0FDH) according to an embodiment of the invention.
FIG. 32B shows the organization of the table of FIG. 32A.
FIG. 33A (Table 31) indicates Op Code Map (4th Byte, after 0DDH, 0CBH, and d) according to an embodiment of the invention.
FIG. 33B shows the organization of the table of FIG. 33A.
FIG. 34A (Table 32) indicates Op Code Map (4th Byte, after 0FDH, 0CBH, and d) according to an embodiment of the invention.
FIG. 34B shows the organization of the table of FIG. 34A

Method and apparatus for an enhanced processor


A short-wavelength light generating apparatus comprising a pumping semiconductor laser and an intra-cavity solid state laser, the intra-cavity solid state laser is excited in response to a laser light beam from the semiconductor laser to generate a short-wavelength light beam to an external. Also included in the apparatus is an external grating mirror having on its one surface a reflection type diffraction grating and placed between the semiconductor laser and the intra-cavity solid state laser. The external grating mirror reflects the laser light beam from the semiconductor laser to feedback a portion of the laser light beam to said semiconductor laser so that an oscillated wavelength of the semiconductor laser becomes within a wavelength acceptance of the intra-cavity solid state laser. Further, the external grating mirror supplies a portion of the laser light beam from the semiconductor laser to the intra-cavity solid state laser. This arrangement can output a stable harmonic wave with a high efficiency.

The present invention relates to short-wavelength light generating apparatus using an external-cavity semiconductor laser (laser diode), which apparatus is applicable to a high-density optical disk system and others.
Recently, in optical disk high-density recording and image processing fields, there is a need to provide a green or blue light source by high-efficiency wavelength conversion using a semiconductor laser being used as an exciting (pumping) light source. The output light from the green or blue light source is required to be arranged to have the Gaussian transverse mode and to be converged up to near the diffraction limit and further required to be about several mW and stable in frequency and time. For obtaining such a high-power short-wavelength light generating apparatus using a semiconductor laser, a quasi-phase matching (QPM) type waveguide ("Optics Letters" Vol. 16, No. 15, 1156 (1991), written by Yamamoto and others) is used as a wavelength conversion means, or an intra-cavity (resonator) method is used which offers harmonic light with a semiconductor laser light being as the pumping light and a wavelength conversion device being provided within a resonator of a solid state laser.
FIG. 18 shows a schematic arrangement of a conventional short-wavelength light generating apparatus using a semiconductor laser and QPM polarization-inverted waveguide. In FIG. 18, light emitted from a semiconductor laser I01 is incident on a collimating lens I02 to be converted into a parallel light beam. The parallel light beam from the collimating lens I02 arrives at a half-wave (.lambda./2) plate I03 so that its deflection direction rotates, and then reaches a focusing lens I04, whose numerical aperture (NA) is 0.6, so as to be focused on an incident end surface I05 of a polarization-inverted waveguide I06, thereby obtaining blue light. Here, although anti-reflection coating is made on the end surface I05 of the waveguide I06 in order to prevent the return light to the semiconductor laser I01, in practice the return light of about 1% occurs.
FIG. 19 illustrates a schematic arrangement of an intra-cavity type short-wavelength light generating apparatus using a semiconductor laser pumped solid state laser. In FIG. 19, light emitted from a semiconductor laser Jo1 is incident on a collimating lens J02 to be converted into a parallel light beam and then incident on a focusing lens J03 to be focused on a laser material (Nd:YVO.sub.4) J04. An incident end surface J05 of the laser material J04 is coating-processed so as to allow anti-reflection (AR) with respect to the wavelength (809 nm) of the light from the semiconductor laser J01 and allow high reflection (HR) with respect to an oscillated wavelength (1.064 .mu.m) and harmonic light wavelength (532 nm). Further, the other surface J06 of the laser material J04 is antireflection-coated with respect to the oscillated wavelength and harmonic light wavelength. Light from the laser material J04 passes through a nonlinear optical material (crystal) KTP (KTiOPO.sub.4) J08 to reach an output mirror J07. The output mirror J07 is high-reflection-coated with respect to the oscillated wavelength. The output mirror J07 and the end surface J05 of the laser material J04 constitutes a resonator whose basic wavelength is 1.064 .mu.m so that the harmonic wave wavelength-converted by the nonlinear optical material KTP J08 can be obtained by the output mirror J07.
However, although the FIG. 18 apparatus can provide 1.1 mW blue light in relation to an incident light intensity 25 mW into the QPM polarization inverted waveguide, since the wavelength acceptance of the QPM polarization-inverted waveguide device is only 0.2 nm, the fluctuation of the oscillation frequency is 0.2 nm/.degree.C. in relation to the fluctuation of the temperature of the semiconductor laser and the mode hopping due to the return light appears to be about 1 nm, the output is stable only for several seconds. Thus, the FIG. 18 apparatus is required to be arranged to make stable the wavelength of the semiconductor laser.
Further, in the FIG. 19 apparatus, in the case that a single longitudinal mode semiconductor laser is used as a pumping laser, the return light occurring because the transmission factor of the anti-reflection coating on the end surface (Nd:YVO.sub.4) J05 of the laser material is about 93% causes the mode hopping and multiple longitudinal modes to occur, thereby generating noises because the half width of the absorption spectrum is several nm in the case of Nd:YVO.sub.4. Thus, the FIG. 19 apparatus is also required to be arranged to make stable the wavelength of the semiconductor laser.
In the above-described FIGS. 18 and 19 apparatus, as one countermeasure for the return light, it is considered to use an isolator or improve the anti-reflection coating on the incident end surface. The isolator cannot prevent the wavelength fluctuation due to the fluctuation of temperature of the semiconductor laser itself concurrently with being costly and large in size. Further, difficulty is encountered to improve the anti-reflection coating in accordance with the current technique.

Short-wavelength light generating apparatus

Matsushita Electric Industrial Co., Ltd.


The present invention provides methods that utilize compositions containing colostrinin, a constituent peptide thereof, an active analog thereof, and combinations thereof, as modulators of intracellular signaling molecules, for example.

Colostrum is a component of the milk of mammals during the first few days after birth. Colostrum is a thick yellowish fluid and is the first lacteal secretion post parturition and contains a high concentration of immunogloblins (IgG, IgM, and IgA) and a variety of non-specific proteins. Colostrum also contains various cells such as granular and stromal cells, neutrophils, monocyte/macrophages, and lymphocytes. Colostrum also includes growth factors, hormones, and cytokines. Unlike mature breast milk, colostrum contains low sugar, low iron, but is rich is lipids, proteins, mineral salts, vitamins, and immunoglobins.
Colostrum also includes or contains a proline-rich polypeptide aggregate or complex, which is referred to as colostrinin (CLN). One peptide fragment of colostrinin is Val-Glu-Ser-Tyr-Val-Pro-Leu-Phe-Pro (SEQ ID NO:31), which is disclosed in International Publication No. WO-A-98/14473. Colostrinin and this fragment have been identified as useful in the treatment of disorders of the central nervous system, neurological disorders, mental disorders, dementia, neurodegenerative diseases, Alzheimer's disease, motor neurone disease, psychosis, neurosis, chronic disorders of the immune system, diseases with a bacterial and viral aetiology, and acquired immunological deficiencies, as set forth in International Publication No. WO-A-98/14473.
Although certain uses for colostrinin have been identified, it would represent an advancement in the art to discover and disclose other uses for colostrinin, or a component thereof, that are not readily ascertainable from the information currently known about colostrinin or its constituents.

Use of colostrinin, constituent peptides thereof, and analogs thereof as modulators of intracellular signaling molecules

Board of Regents, The University of Texas System


A plasma processing apparatus includes a processing chamber encased in a vacuum vessel equipped with an evacuator; a sample stage located in the processing chamber and having an upper surface on which a sample as an object to be processed rests; a gas feeding unit for feeding processing gas into the processing chamber; a plurality of refrigerant ducts which are laid out in the internal of the sample stage and through which liquid refrigerant flows and can be evaporated; a cooling circuit including a compressor, a condenser, an expansion valve and a set of pipelines to connect the compressor, the condenser and the expansion valve in this order; and a selecting unit for selectively feeding the refrigerant through the plural refrigerant ducts in the different steps of the processing. The sample is processed by using plasma while the temperature of the sample stage is being controlled by the cooling circuit.

This invention relates to a plasma processing apparatus which uses plasma to work the surface of a sample such as a semiconductor wafer, in the process of fabricating semiconductor devices, and more particularly to a plasma processing apparatus wherein the sample is processed while the temperature of the sample stage for holding the sample is being controlled.
It is important to keep the surface of the semiconductor wafer under processing precisely at a predetermined temperature in a fabricating process using such a plasma processing apparatus as mentioned just above wherein the surface of the semiconductor wafer as a sample is processed to form fine patterns serving as semiconductor device circuits with high precision. If the temperature of the wafer surface can be maintained at the optimal value as the steps of the fabrication process proceed, then the selective ratio and the throughput of the processing as well as the precision of working can be improved.
Today, the surface area of the semiconductor wafer to be processed is becoming larger and larger with the result that the high-frequency power consumed in the process is also increasing. Especially, in the process of etching the interlayer insulation films for insulating from one another the multiple layers to serve as semiconductor devices, power in the order of kilowatts must be supplied so as to maintain a high speed in etching. The application of such heavy power causes the increase in the energy of ions bombarding the surface of the semiconductor wafer so that the inflow of heat into the semiconductor wafer also increases. To cope with this increase in the heat inflow, therefore, the sample stage for holding the semiconductor wafer must have such a function that it can adjust the temperature of the wafer to a predetermined value quickly enough against such increase in heat inflow.
In controlling the temperature of wafer surface with such a plasma processing apparatus as described above, the temperature of the sample resting surface, which contacts the semiconductor wafer surface, of the sample stage is made controllable or variable. For example, the sample stage using a conventional technique incorporates therein ducts through which a heat exchange medium of liquid (e.g. fluorinate) passes so as to dissipate such heat inflow as mentioned above, cool the sample stage and keep the wafer surface at a desired temperature.
Such liquid refrigerant is caused to flow through the ducts laid out in the sample stage after it has been adjusted to a predetermined temperature by means of a cooler or a heater installed in a refrigerant supplying apparatus (e.g. chiller unit) communicating with the ducts of the sample stage through a refrigerant pipeline. This refrigerant supplying apparatus has a reservoir such as a tank to contain liquid refrigerant in it and the liquid refrigerant whose temperature has been controlled is pumped out. Since the heat capacity of the liquid refrigerant is large, it is easy to keep the sample stage and the semiconductor wafer placed on it, at a predetermined temperature.
On the other hand, however, there still is a problem that when it is required to change the temperature of the sample stage or the semiconductor wafer, the response in control is poor so that it is difficult to adjust the temperature to a desired value in short time. Further, since the efficiency of heat transfer is low, the flow rate or the pressure of the refrigerant must be increased if there is large heat inflow into the sample stage. This must lead to the increase in the size of the cooling apparatus and therefore the increase in the running cost thereof.
To solve such a problem, there has been provided a plasma processing apparatus having a so-called sample stage of direct refrigerant expansion type (hereafter referred to as DRE type), wherein the sample stage is incorporated in a cooling circuit, that is, wherein a compressor for pressurizing the refrigerant, a condenser for condensing the pressurized refrigerant, an expansion valve for expanding the refrigerant and the sample stage are communicated through refrigerant pipelines so that the sample stage is cooled by the latent heat generated in the evaporation of the liquid refrigerant within the sample stage. This type of sample stage is known as disclosed in the Japanese patent documents such as JP-A-06-346250 and JP-2005-89864. These conventional techniques, provided with the sample stage of DRE type, aim to adjust the semiconductor wafer at a predetermined temperature with high efficiency and speed even in the case of increased heat inflow during the fabrication process.


The invention relates to methods and devices for securing a product against theft. The security device comprises a connection mode (110) and an on position mode (100). A receiver (6) of the security device is activated when in the on position (100) and the security device switches from the on position (100) to the connection mode (110) when the receiver (6) is impinged upon by a transmitter (5). The receiver (6) is deactivated in the connection mode (110). The energy consumption of the security device is reduced by deactivating (111) the receiver (6). The security device can be prevented from being unintentionally impinged upon by selection signals from the transmitter because of said deactivation (111).

In shops or warehouses it is customary at times to display the radios or television sets, video sets, telephones and so forth that are offered for sale. To accomplish this, frequently one display sample of each type of item is made available to customers for test purposes. To prevent any possible loss, these display samples are preferably equipped with devices that will trigger an alarm in the event of an attempted theft.
There are known devices for protecting commercial goods against theft, which are equipped with a receiver, wherein the receiver is continuously in operation, so that the security component requires a high power input level, which is undesirable especially in battery-operated security devices.
Furthermore, known devices have the disadvantage that, for example, when multiple security units are operated using a single common central unit, a cumbersome selection of a specific security unit to be activated next is required, e.g., via corresponding input from an operator, before that particular security unit can be activated.

This patent is subject to a terminal disclaimer.

Methods and devices for securing a product against theft


Methods and apparatus relating to robust governing of power management infrastructure in a bridge design are described. In one embodiment, a first agent (such as a processor core) is coupled to a second agent (such as an input/output device) via a bridge. The bridge may or may not enter a different power management state from a current power management state based on a second derivative value. The second derivative value may be in turn determined based on a plurality of first derivative values corresponding to received packets Other embodiments are also disclosed and claimed.

One common interface used in computer systems is Peripheral Component Interconnect (PCI) Express ("PCIe", in accordance with PCI Express Base Specification 3.0, Revision 0.5, August 2008). In today's bridge designs (such as PCI Bridges), power management may be triggered using an "idle timeout counter" mechanism. A timeout counter may generally represent a static guessing mechanism that has no real correlation with the actual traffic activities. For example, the timeout counter mechanism may be solely based on the idle period between two packets.
However, the consequences of a wrong value for idle timeout counter to trigger power management in a bridge may either cause a performance impact with no power saving at all or even hardware compliancy issues. Therefore, to avoid such issues, the timeout counter is usually programmed with a large value for pessimistic and safe guard reasons. But, a large timeout value would in turn directly penalized power saving opportunity.

Power management in a bridge based on a second derivative value derived from a mathematical derivative of plurality of values corresponding to the received packets


An X-ray collimator formed of stacked laminated layers with apertures therein aligned to form complex 3-dimensional collimator structures, and method of fabrication thereof, is presented.

X-ray inspection systems are often used to inspect objects that may be difficult to inspect using optical or other inspection techniques. For example, x-ray inspection systems are particularly useful in the inspection of objects that are embedded within, or are otherwise visually blocked by, other objects. X-ray inspection involves the capture of projected images of an object under inspection by one or more x-ray sensors. In this regard, one or more x-ray sources generate x-rays that may illuminate one or more sensors as attenuated by an intervening object under inspection. During image acquisition, the quality of the images captured by the one or more sensors may be limited due to the presence of x-ray scatter, which can result in loss of dynamic range in a captured image, thus reducing the system's inspection capability.
To reduce interference from x-ray scatter, a collimator may be placed between an x-ray source and the object space. As used herein, the term "collimator" refers to a device that produces directed beams from one or more x-ray sources. For example, a collimator may collimate x-rays from one or more x-ray sources into one or more fan beams. As used herein, the term "fan beam" refers to an x-ray beam having a constant ratio of major to minor dimension at any transverse cross section. To reduce x-ray scatter in an X-ray inspection system, a collimator may be used to collimate the x-rays generated by the x-ray source(s) into a number of fan beams, each directed at a respective sensor along a respective controlled solid angle. For example, a collimator may be configured to produce one or more fan beams having respective ratios of major to minor dimensions that substantially match respective ratios of major to minor dimensions of corresponding sensor areas—thus, the x-rays substantially illuminate only the sensing area of the sensor(s) located in the imaging plane.
To obtain the advantages of X-ray collimation, very precise tapered windows must be machined into material that is an effective attenuator of X-rays. Tungsten (W) is generally the material of choice for an application where precision, strength and X-ray attenuation are required, although any x-ray attenuating material may be used. However, the manufacture of Tungsten collimators is very expensive due to the miniscule complex shapes that must be created. Although Tungsten is quite pliant in its purest form, it typically contains small concentrations of carbon and oxygen, which gives tungsten metal its considerable hardness and brittleness. Given these properties, collimators made from Tungsten or other hard materials are typically created using Electrical Discharge Machining (EDM) techniques.
In EDM metal is removed by producing a rapid series of repetitive electrical discharges between an electrode and a metal workpiece. The electrical discharges actually remove small amounts of material and allow the electrode to be moved through the metal. The path of the electrode is typically controlled by a computer, which allows extremely intricate contours or delicate cavities that would be difficult to produce with a grinder or other cutting tools.
Lead (Pb) and other softer X-ray attenuating materials can also be used to create lower cost X-ray collimators, but the window sizes must be increased and additional thickness is required compared to Tungsten collimators. Larger windows make a collimator less effective at attenuating scatter X-rays and the additional thickness required for equivalent attenuation reduces the allowable distance from the X-ray source to the object being imaged.
Accordingly, a need exists for creating complex shaped 3-dimensional internal structures in hard materials such as Tungsten to allow the fabrication of effective X-ray collimators at a cost much lower than traditional methods of construction.

Fine geometry X-ray collimator and construction method


A semiconductor chip is provided that is highly packageable and particularly well suited for mounting on a circuit board having a curved surface. The semiconductor chip comprises a warpage control film that controls the warpage of a substrate.

1. Technical Field
The present invention relates to a semiconductor chip and a circuit board, a manufacturing method of the same, and electronic equipment.
2. Related Art
For wearable equipment such as wristwatches, it is being demanded that they should make more efficient use of the holding space on their circuit boards due to requirements for increased compactness of such equipment (see for example Inoue, "Chrono-Bit no Kaihatsu to Jisso Gijutsu" (Chrono-Bit Development and Packaging Technology)", Erekutoronikkusu Jisso Gijutsu (Electronics Packaging Technology), Gicho Publishing & Advertising Co., Ltd., 2000, Vol. 16 No. 12 (December 2000 issue), p. 40-45). To meet such need, the use of circuit boards with curved surfaces is being considered. It would for instance be possible to realize flat-type equipment by bending the case and the circuit board to the same curvature.
When semiconductor chips are packaged onto circuit boards with curved surfaces, flexible boards with a base material such as polyimide have been used. Multilayer interconnection is problematic with flexible boards however, so there is a limit to their capacity for high density and high functionality. Furthermore, inducing warpage in the circuit boards after the semiconductor chip has been packaged produces stress in the bonding portions that could lead to poor couplings. Sheathing with resin for reinforcement purposes causes a marked fall in bendability.
The present invention has been made in consideration of the aforementioned problems, and intends to provide a highly packageable semiconductor chip that is capable of, among other things, being mounted on a circuit board with a curved surface.
Another purpose of the present invention is to provide a high reliability semiconductor device and a method for manufacturing the same.
A further purpose of the present invention is to provide electronic equipment that is flatter, more compact and that allows greater degrees of freedom in design.

Semiconductor chip, semiconductor device and electronic equipment including warpage control film, and manufacturing method of same


The present invention provides a technology for decreasing a dispersion of the performance among electromechanical transducers each having through wiring. A method for manufacturing an electromechanical transducer includes: obtaining a structure in which an insulative portion having a through hole therein is bonded onto an electroconductive substrate; filling the through hole with an electroconductive material to form a through wiring which is electrically connected with the electroconductive substrate; and using the electroconductive substrate as a first electrode, forming a plurality of vibrating membrane portions including a second electrode, which opposes to the first electrode through a plurality of gaps, on an opposite side of the first electrode to the side having the insulative portion, to thereby forming a plurality of cells.

1. Field of the Invention
The present invention relates to an electromechanical transducer to be used for an ultrasound probe of an ultrasound diagnosis apparatus and the like, and to a method for manufacturing the same.
2. Description of the Related Art
An electromechanical transducer such as an ultrasound transducer conducts at least one of conversion from an electric signal to an ultrasound wave and conversion from the ultrasound to the electric signal, and it is used as a probe for ultrasound diagnosis for medical application, a probe for a non-destructive test and the like. In recent years, along with the development of a fine processing technology, a capacitance type electromechanical transducer (CMUT: Capasitive Micromachined Ultrasonic Transducer) produced by using the technology has been actively developed. An exemplary CMUT has a structure that an element substrate having a cell includes a substrate having a lower electrode (where the substrate occasionally serves as lower electrode as well), a vibrating membrane formed on the substrate so as to keep a fixed space between itself and the lower electrode, and an upper electrode, which element substrate being electrically connected with a driving circuit substrate. Furthermore, the CMUT has a structure in which the element substrate has a plurality of elements to which two or more cells are electrically connected, which element substrate being electrically connected to the driving circuit substrate (see Japanese Patent Application Laid-Open No. 2006-319712). A CMUT with high ability in transmitting or receiving the ultrasound by using a lightweight vibrating membrane, and having excellent broadband characteristics in any of a liquid and an air, can be easily obtained. Consequently, since the use of CMUT enables diagnosis with higher accuracy than that of a conventional medical diagnosis, and CMUT has received attention as a promising technology.
In operating CMUT, when transmitting the ultrasound, the CMUT applies a DC voltage and an AC voltage between the lower electrode and the upper electrode so that the voltages are superimposed. Thereby, the vibrating membrane vibrates and transmits the ultrasound. When receiving the ultrasound, the CMUT detects a signal from a change in the capacitance between the lower electrode and the upper electrode due to the change of a distance between both of the electrodes along with the deformation of the vibrating membrane, which occurs when the vibrating membrane has received the ultrasound. The methods for applying voltage to electrodes for driving the CMUT include: providing an electrode on the surface of the substrate of the CMUT and routing wires which are connected to the upper and lower electrodes; and guiding wires from the upper and lower electrodes to the rear surface of the substrate by using through wiring provided on the substrate, and thereby electrically connecting the electrodes to each other. In the former method, since it is necessary to route the wires on the surface of the substrate, an element can hardly be arranged in a portion occupied by the wire. Therefore, a fill factor, which is expressed by a ratio of the cells occupying in the elements having the same area, decreases. In addition, as for the space between the elements, since it is necessary to arrange the elements so as to be separated from each other by the area occupied by the wire, the elements can hardly be arranged at a high density. As a result, the performance of the CMUT is lowered. On the other hand, in the method of using the through wiring, normally, every element is insulated from each other in the substrate, and the through wiring is formed for the respective elements to electrically connect the electrodes. Thus manufactured CMUT is described in Japanese Patent Application Laid-Open No. 2007-215177 and Japanese Patent Application Laid-Open No. 2010-35134. Since there is need to route wires on the surface of the substrate in the CMUT formed by using the through wiring, the cell can be arranged in the portions occupied by the wires and the element can be arranged at a high density. Therefore, the CMUT having a high fill factor and a high arrangement density of the element can be produced, which leads to the enhancement of the performance.

Method for manufacturing an electromechanical transducer


A gas diffusion layer for a fuel battery is used, which is configured by a porous member containing conductive particles, conductive fibers and a polymer resin as main components. An aggregate of the conductive fibers is formed inside the porous member, and an area ratio of the aggregate in any cross-section of the porous member is 0.5% or more and 8% or less. Further, a membrane electrode assembly including the gas diffusion layer for the fuel battery is used. Further, a fuel battery including the gas diffusion layer for the fuel battery is used.

An example of a fuel battery is, for example, a polymer electrolyte fuel battery. The basic principle of the polymer electrolyte fuel battery is that, with one surface of a hydrogen ion conductive polymer electrolyte membrane exposed to a fuel gas such as hydrogen and the other surface to oxygen, water is synthesized by a chemical reaction via an electrolyte membrane, and thus, reaction energy generated at that time is electrically extracted.
A unit cell of a polymer electrolyte fuel battery has a membrane electrode assembly (hereinafter referred to as MEA) and a pair of conductive separators disposed on both surfaces of the MEA.
The MEA includes a hydrogen ion conductive polymer electrolyte membrane and a pair of electrode layers sandwiching the electrolyte membrane. The pair of electrode layers are formed on both surfaces of the polymer electrolyte membrane and have a catalyst layer containing carbon powder carrying a platinum group catalyst as a main component and a gas diffusion layer formed on the catalyst layer and possessing a current collection function, gas permeability, and water repellency.
Since the gas diffusion layer plays a role of uniformly supplying the gas supplied from the separator to the catalyst layer, it is necessary to have good gas permeability and gas diffusibility. Further, the gas diffusion layer needs to have excellent conductivity as a conductive route of electrons between the catalyst layer and the separator. For this reason, a conductive porous member is used for the gas diffusion layer.
Further, the gas diffusion layer is required to have high water repellency so that excessive moisture generated by the cell reaction in the catalyst layer is quickly removed and discharged to the outside of the MEA system, and pores of the gas diffusion layer are not blocked by the generated water. Therefore, in the gas diffusion layer, water repellent treatment is performed on the conductive porous member with a fluororesin or the like. Furthermore, a water repellent layer containing a water repellent resin such as a carbon powder and a fluororesin as main components is generally used on a side of the conductive substrate in contact with the catalyst layer.
In this way, the conductive substrate is subjected to the water repellent treatment so that blockage by the generated water of the pores of the gas diffusion layer is prevented. Further, the water repellency of the water repellent layer is made to be higher than that of the conductive substrate, excessive moisture generated in the catalyst layer can be quickly discharged to the outside of the MEA system.
Such gas diffusion layer is disclosed in, for example, Japanese Patent No. 4938133 (JP '133), WO2017/085901 (WO '901), and WO2005/043656 (WO '656).
The gas diffusion layer of JP '133 is configured by a porous member containing conductive particles and a polymer resin as main components, with carbon fibers having a weight smaller than that of the polymer resin added.
The gas diffusion layer of WO '901 is configured by a porous member containing conductive particles and a polymer resin as main components, with carbon fibers having a weight smaller than that of the polymer resin added, and includes pores of 0.01 to 0.05 μm and vacancies of 1 to 200 μm inside.
The gas diffusion layer of WO '656 is a sheet with a thickness of 0.05 to 2 mm and made by a mixture of fine carbon fibers and conductive particles and water repellent resin particles having a fiber diameter of 0.5 to 500 nm, a fiber length of 1000 μm or less, and a central axis made of a hollow structure.

Gas diffusion layer for fuel battery, membrane electrode assembly, and fuel battery

PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.


A bowling lane maintenance machine has its operating functions designed and controlled in such a manner that the machine may be battery-operated without loss of performance. Included in the operation are special movements of the machine at the pin deck to flick moisture off blades of the squeegee assembly and limited activation of the vacuum motor to reduce battery drain.

It is well known in the prior art to provide a lane machine that applies cleaning liquid to the lane at the front of the machine, picks up the liquid, surface grime and old dressing (oil) near the middle of the machine, and then applies a new film of oil to the cleaned surface at the rear of the machine as the machine is traveling along the length of the lane. In the past, such machines have required connection to house current through a long, unwieldy supply cord because the sequence of operations performed by the machine drew too much electrical current to make battery operation practical considering the significant number of lanes in a bowling facility.
In a machine constructed in accordance with the principles of the present invention the operational steps of the machine are such that battery operation can become a practical reality, without sacrificing quality and speed. Although the inventive operating steps are beneficial even if not incorporated into a machine that is battery-powered, the convenience of battery operation makes incorporating these principles into a battery-powered machine particularly attractive.


There is provided a power-supply device includes: a case receiving a curved wire harness; a guide rail mounted on the case; a slider mounted slidably on the guide rail, through which the wire harness being routed out from the case; an urging member having a resilient part mounted on the slider, and a long rack. The long rack alternately has crests and troughs, and slidably engaged with the resilient part of the urging member. Preferably, the long rack is mounted on the guide rail, and the urging member is mounted on a slidable engaging part of the slider for engaging with the guide rail. Preferably, the urging member is slidably engaged with the slider.

1. Field of the Invention
The present invention relates to a power-supply device for constantly feeding electric power to a sliding door, a sliding seat of a vehicle or the like by a substantially U-shaped wire harness expanded and contracted with a movement of a slider in a case.
2. Description of the Related Art
FIG. 10 shows an embodiment of a conventional power-supply device 61 disclosed in FIG. 2 of Japanese Published Patent Document H11-342807.
This power-supply device 61 is used for a sliding door of a vehicle, and includes: a long case 63 for receiving a substantially U-shaped flat wire harness 62; a resilient reinforcing plate 64 mounted on an outer wall of the wire harness 62; a slider 65 disposed on a movable end of the wire harness 62; and a guide rail 66 engaging slidably with the slider 65.
The movable end of the wire harness 62 is connected to a connector of a wire harness 68 extending to a vehicle body through the slider 65. A fixed end of the wire harness 62 is connected to a wire harness 69 extending to a sliding door.
While the slider 65 is slid forward and backward along the guide rail 66 corresponding to opening and closing of the sliding door, the wire harness 62 is kept in the substantial U-shape, and expanded or contracted integrally with the slider 65 to absorb a stroke between opening and closing of the sliding door. Thus, electric power and signals are constantly fed from the vehicle body to various auxiliaries disposed on the sliding door.
Another embodiment (not shown) of the conventional constant power-supply device for a sliding door is, for example, disclosed in FIG. 1 of Japanese Published Patent Document 2004-48977.
In an interior of a synthetic resin made substantially semicircular protector of the conventional power-supply device, a metallic flat spring urging a wire harness routed in a curve shape urging upward, the supporting member made of synthetic resin and fixed to the flat spring stably supporting the wire harness, and a spring piece mounted on the supporting member contacting an inner wall of the protector prevent a noise caused by a roll of a supporting member.
However, in the power-supply device 61 described in Japanese Published Patent Document H11-342807, because the slider 65 has no noise protection mechanism, when the sliding door is fully opened, a vibration of a moving vehicle or a vibration of an engine of a stopping vehicle may produce resonance of the slider 65, so that the slider may rattle with the guide rail 66 of the case 63 to make a noise, and that the slider 65, the guide rail 66, and the like may be abraded. Particularly, when the synthetic resin made case 63 is molded relatively large, owing to a variation of size of the molded case 63, the case 63 may rattle harder with the slider 65 to increase the noise and the abrasion.
Further, when the sliding door is opened or closed and the slider 65 is moved along the guide rail 66, the rattle may cause the abrasion, and make a larger noise. Further, before the power-supply device 61 is mounted on a vehicle, the slider 65 may move freely depending on an attitude and a form of packaging of the transported power-supply device 61. Thereby, a troublesome work to return the slider 65 to a predetermined position may be generated.
Accordingly, an object of the present invention is to provide a power-supply device for preventing noise and abrasion caused by a rattle generated when a slider is moved and stopped, and regulating an unnecessary movement of the slider before the power-supply device is mounted.


A method and a filling machine for the temperature control of a mass flow in a filling machine, wherein the mass flow passes through several sections. In order to also process temperature-sensitive types of filling material reliably with the minimum outlay, the temperature of the filling material is measured in several sections of the filling machine and the temperature of the filling material is controlled by a heating/cooling device to a certain temperature in dependence of the measured temperatures.

Filling machines of this nature for filling sausage casings with paste material are already known. During the processing of certain types of filling material, e.g. raw sausage, it should be ensured that the temperature of the filling material does not undercut or exceed a certain temperature in the complete processing chain. If the filling material undercuts or exceeds a certain temperature, it cannot then be processed further. For this reason currently the temperature of the mass flow is acquired, wherein on reaching a certain limit the operator must intervene actively and manually in the process. With heated hoppers the intervention can take place as long as filling material is located in them. Production may even need to be interrupted and the filling material removed from the machine, because it can no longer be processed. The ejection of the filling material from the machine or the cleaning of the machine requires however a high outlay and is correspondingly cost-intensive. The known filling machines therefore demand predictive actions. Consequently, increased concentration is required of the operator.

Temperature control of the mass flow in a filling machine

Albert Handtmann Maschinenfabrik GmbH & Co. KG


Certain aspects of determining a signal quality metric in event of a CRC false positive may comprise measuring an amplitude and/or phase of at least a portion of a phase shift keyed section of a frame. The measured amplitude and/or phase may be checked to determine if it lies within a range of a reference amplitude and/or phase respectively. An amplitude and/or phase counter may be incremented if the measured amplitude and/or phase lies outside the range of the reference amplitude and/or phase respectively. A confidence level value of a cyclic redundancy check (CRC) for at least a portion of the phase shift keyed section of the frame may be determined based on a determined value of the incremented amplitude and/or phase counter.

In an ideal situation, a transmitter may transmit information over a channel or medium and the transmitted information may be received without alteration and processed by a receiver. However, a transmission medium or channel is constantly subjected to impairments such as noise and interference. Consequently, when a transmitter transmits information, a receiver may not receive the information in an identical manner in which it was transmitted. This may be due to impairments in a channel that may typically introduce errors in the transmitted information. A transmitter may code the data in such a manner that error introduced during transmission may be detected and/or corrected during reception.
Cyclic redundancy is one method, which may be utilized to code information for transmission so that at least some errors may be detected and/or corrected. A cyclic redundancy check (CRC) may be computed for a group or block of bits referred to as frames. The computed CRC may then be appended to each frame for which a CRC is computed and the frame with the CRC may be transmitted. The appended CRC may be referred to as a frame check sequence (FCS).
On the receive side, the frame check sequence may be extracted from the received information and a CRC may be computed for the received information. This calculated CRC of the received frame may then be compared with the frame check sequence and if there is a mismatch, then the received frame may be in error.
CRC utilizes very little overhead and may be easily implemented. Many conventional devices currently use cyclic redundancy check (CRC) to determine if there is an error in information that has been received from a transmitting entity. For example, a receiver may be adapted to determine a CRC on frames in a payload of a received packet. The computed CRC may be compared with a frame check sequence to determine whether the frame is in error. If the frame is determined to be in error and the error may be corrected, then the frame may be acknowledged. If the frame is in error and the error may not be corrected, then the receiver may send an indication or a signal such as a negative acknowledgement, thereby causing the packet to be retransmitted by the transmitter.
In certain instances, for example, when a very large file is transmitted and received for processing, there may be a possibility that when a CRC is computed on a corresponding received frame, the computed CRC may pass even though there may be multiple bit errors in the receive frame. This may be referred to as a false CRC pass. These types of false CRC pass indicators may be destructive in a large program or image that is being transferred.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.

Method and system for determining a signal quality metric in event of a CRC false positive


Beverage cans often are stored or transported in surroundings which are not hygienic. The result is that a beverage can may reach the end user in a condition, which is not only unattractive but is also unhygienic. The invention provides a cover for assisting in overcoming this problem and, if required, providing additionally or alternatively a promotional advantage. Such as a cover for a dispensing opening of a beverage can includes a disc and an attachment area associated with the disc for attaching the disc removably to a beverage can for closing off the dispensing opening of the beverage can. The invention also is directed to a method for applying the cover to a beverage can.

Beverage cans often are stored or transported in surroundings which are not hygienic. The result is that a beverage can may reach the end user in a condition, which is not only unattractive but is also unhygienic.
It is an object of the invention to suggest ways and means for assisting in overcoming this problem and, if required, providing additionally or alternatively a promotional advantage.


The present invention provides a three-dimensional structures of P. tremuloides isoprene synthase and P. alba isoprene synthase. The invention also provides methods of using the three-dimensional structure to design isoprene synthases with improved activity for increased isoprene production in microbial host cells. Biosynthetically produced isoprene of the present invention finds use in the manufacture of rubber and elastomers.

Isoprenoids are isoprene polymers that find use in pharmaceuticals, neutraceuticals, flavors, fragrances, and rubber products. Natural isoprenoid supplies, however, are limited due to ecological concerns. For this reason, and to provide isoprenoid compositions having fewer impurities and greater uniformity, isoprenoids such as rubber are often produced synthetically.
Isoprene (2-methyl-1,3-butadiene) is a volatile hydrocarbon that is insoluble in water and soluble in alcohol. Commercially viable quantities of isoprene can be obtained by direct isolation from petroleum C5 cracking fractions or by dehydration of C5 isoalkanes or isoalkenes (Weissermel and Arpe, Industrial Organic Chemistry, 4th ed., Wiley-VCH, pp. 117-122, 2003). The C5 skeleton can also be synthesized from smaller subunits. It would be desirable, however, to have a commercially viable method of producing isoprene that was independent of nonrenewable resources.
Biosynthetic production of isoprene occurs by two distinct metabolic pathways (Julsing et al., Appl Microbiol Biotechnol, 75:1377-1384, 2007). In eukaryotes and archae, isoprene is formed via the mevalonate (MVA) pathway, while some eubacteria and higher plants produce isoprene via the methylerythritol phosphate (MEP) pathway. Isoprene emissions from plants are light and temperature-dependent with increases linked to leaf development. An isoprene-producing enzyme, isoprene synthase, has been identified in Aspen trees (Silver and Fall, Plant Physiol, 97:1588-1591, 1991; and Silver and Fall, J Biol Chem, 270:13010-13016, 1995) and is believed to be responsible for the in vivo production of isoprene from whole leaves. Bacterial production of isoprene has also been described (Kuzma et al., Curr Microbiol, 30:97-103, 1995; and Wilkins, Chemosphere, 32:1427-1434, 1996), and varies in amount with the phase of bacterial growth and the nutrient content of the culture medium (U.S. Pat. No. 5,849,970 to Fall et al.; and Wagner et al., J Bacteriol, 181:4700-4703, 1999, both herein incorporated by reference in their entirety). The levels of isoprene obtainable through bacterial systems of the prior art, however, are insufficient for commercial uses.
Polypeptides, e.g. isoprene synthase, have a three-dimensional structure determined by the primary amino acid sequence and the environment surrounding the polypeptide. This three-dimensional structure establishes the polypeptide's activity, stability, binding affinity, binding specificity, and other biochemical attributes. Thus, knowledge of a protein's three-dimensional structure can provide much guidance in designing improvements to its biological activity, for example, greater catalytic activity, dimerization and/or solubility.
The three-dimensional structure of a polypeptide can be determined in a number of ways. Many of the most precise methods employ X-ray crystallography (See, e.g., Van Holde, (1971) Physical Biochemistry, Prentice-Hall, New Jersey, pp. 221-39). This technique relies on the ability of crystalline lattices to diffract X-rays or other forms of radiation. Diffraction experiments suitable for determining the three-dimensional structure of macromolecules typically require high-quality crystals. The crystallization properties of a polypeptide vary greatly (Dale, et al., J. Struct. Biol. 142:88-97, 2003; MacPherson, A., Methods 34:254-265, 2004; and Slabinski, L et al., Protein Science 16:2472-2482, 2007). In some cases polypeptides crystallize readily whereas in other cases polypeptides have proven extremely difficult to obtain. There is no comprehensive theory to guide efforts to crystallize macromolecules and as a result, most efforts macromolecular crystal growth is empirical in nature (MacPherson, 2004).
Previous efforts to utilize the structure of isoprene synthase in order to improve production of isoprene have relied on the structures of other terpene synthases in which three-dimensional structures are available including bornyl diphosphate synthase and 5-epi-aristolochene synthase (See e.g., U.S. patent application Ser. No. 12/429,143 and WO 2008/137092). What is needed is a three-dimensional structure of isoprene synthase to aid in the design of variants of isoprene synthase to allow commercial scale biological production of isoprenoids.
A three-dimensional structure of isoprene synthase is found to have a structurally homologous fold with previously determined synthetases, e.g. bornyl diphosphate synthase and limonene synthase, including conservation in the region involved with the coordinates of required metal ion cofactors, the active and substrate binding sites. The structure has provided insight in the conformational changes that are necessary for these enzyme to bind substrate and catalyze a coordinated series of reactions. Specifically the structure has identified flexible regions that are likely to be shared by all structurally homologous synthetase and that modification of the amino acids found in these regions and the neighboring regions would be expected to effect improved performance of these enzymes. A three-dimensional structure of isoprene synthase may provide a three-dimensional configuration of points, or reaction coordinates, representing the active site of isoprene synthase for the conversion of dimethylallyl diphosphate (DMAPP) into isoprene. Such a configuration of points can aid in the design of synthetic agents for the conversion of DMAPP into isoprene.

Three-dimensional structure of isoprene synthase and its use thereof for generating variants


An electronic device includes a communication component; a location-determining component; a display; and a computing device all housed within a portable, handheld housing or other enclosure. The communications component transmits and receives mobile communications over a wireless communication network or path and provides identification information to the computing device. The location determining component determines locations of the electronic device as it is carried or driven from place to place and provides corresponding location data to the computing device. The computing device links the identification information with the location data to indicate the location of the device when a communication was made or received. The identification information and location data may be linked by adding a geocode or geotag to the identification information or by cross-referencing the information and data in a database. The computing device may also display a representation of the location data alongside a representation of the communication on a cartographic map and then display some of the identification information for the communication when a user scrolls over or otherwise selects either of the representations.

The present invention relates to electronic devices such as navigation devices, cellular phones, and the like. More particularly, the invention relates to a device and method for linking communications received by an electronic device with location data.
Mobile phones equipped with or attached to GPS receivers or other location-determining components are becoming increasingly popular because they allow users to make and receive phone calls and navigate to desired locations with a single electronic device rather than two. Up to now, however, these combined devices have provided few synergies, with each component basically operating the same way it does as a stand-alone device.

Mobile communication device and method for linking communications with location data


A dual link transmitter constructed according to the present invention employs a single Phase Locked Loop (PLL) to service both a primary link and a secondary link during dual link mode operations. The structure of the dual link transmitter includes both a primary link PLL and a secondary link PLL. The primary link PLL produces a primary link clock and the secondary link PLL produces a secondary link clock. During dual single link operations, the primary link clock is used to service the primary link while the secondary link clock is used to service the secondary link. However, during dual link operations, the primary link clock is used to service both the primary link and the secondary link.

Communication technologies that link electronic devices are well known in the art. Some communication technologies link electronic devices via networks. Examples of such networks include wired computer networks, wireless computer networks, wired telephone networks, wireless telephone networks, and satellite communication networks, among other networks. Within such communication networks, a network infrastructure couples electronic devices to one another. Other communication technologies simply link one electronic device to another electronic device. Examples of these types of links include links between computers and their peripheral devices, links between portable data units and computers, links between video devices sources and video monitors, and links between audio sources and audio playback devices, among other examples. With regard to the computer and peripheral device example, communication links couple the computer to its display, the computer to its printer, the computer to its mouse, and the computer to its keyboard, among links.
Many communication link applications require high data rate throughput with minimal or no errors in the data transmitted. Some of these communication links operate in a parallel fashion in which data is carried on a plurality of physical conductors and is clocked in unison. Other of these communication links operates in a serial fashion in which data is carried on a single physical conductor or multiple physical conductors from the first device to the second device in a serial fashion.
One particular type of serial link is a high-speed bit stream serial link. In a high-speed bit stream serial link, data is transmitted from a transmitting device to a receiving device one bit at a time so that, over time, a plurality of bits of data are transferred. An example of such a high-speed bit stream serial link is described generally in the Digital Visual Interface (DVI) standard promulgated by the Digital Display Working Group, which is incorporated herein by reference for all purposes. The DVI standard sets forth a high-speed bit stream serial link that carries display information from a video source (transmitter) to a video display (receiver), in one operation. The transmitter may be contained in a computer, a cable modem set top box, a satellite receiver set top box, or another source of video content while the receiver is typically contained in a monitor that displays the visual information received via the high data rate bit stream DVI serial link.
The DVI standard describes the operational characteristics of the physical communication path between the transmitter and the receiver. The DVI standard provides for one or two DVI links, each of which includes a plurality of bit stream paths (data channels) that is synchronized to a clock signal (bit clock). The bit clock and bits streams may operate at frequencies up to 1.65 Gigahertz. At such operating frequencies, the bit streams traveling along the bit stream path(s) are subject to a number of operating conditions that distort the bits as they pass from the transmitter to the receiver. Distortion of bits caused by dispersion along the conductors carrying the bit streams is generally referred to as inter-symbol interference (ISI). ISI distorts the bits such that extraction of the bits from the bit stream is subject to error. Further, the data bit stream(s) is/are often times not aligned fully with the bit clock. Misalignment between a bit stream and the bit clock typically varies over time and is referred to as bit stream jitter. Bit stream jitter often prevents the successful extraction of bits from the bit stream. Whenever bits are not properly extracted by the receiver from the bit stream, data is lost. However, bit stream jitter is common. In many operations, bit stream jitter makes it extraordinarily difficult to successfully meet a data rate, e.g., an error rate of 10−9 or less.
In dual link DVI applications, six channels are supported, three channels for a primary link and three channels for a secondary link. The data contained on these channels is theoretically synchronized upon its transmission such that it arrives at a receiver in a synchronized form. However, the pair of transmitters that service the dual link DVI application may drift with respect to one another such that transmissions are not synchronized with respect to one another. Further, differences in the respective transmission paths that service the dual link DVI may be such to cause the signals to be further offset from one another when they reach respective servicing receivers. Finally, mismatches in operation of a pair of receivers that service the dual link DVI may also introduce skew into the received data path. Resultantly, data that is received in a serial format and converted to a parallel format for each of the dual links may be skewed in time, causing errors in operation of a servicing receiver.
Therefore, there is a need in the art for a DVI transmitter that minimizes transmission skew of data bits during dual link mode operations.

Dual link DVI transmitter serviced by single phase locked loop


A salicide block area is provided around a gate electrode. Polysilicon coupling portions are formed, which extend at plurality of points from the gate electrode to an area outside of an active region. A contact provided at this inactive region electrically connects the gate electrode to gate electrode metal wiring, which is provided above the gate electrode.

1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor integrated circuit device. More particularly, the invention relates to a structure of a semiconductor device adapted for preventing electrostatic discharge damage, which is to be formed as an output circuit of a semiconductor integrated circuit device.
2. Description of the Related Art
An example of semiconductor devices, which are conventionally known as the above type of semiconductor device, includes: a gate electrode formed, via a gate insulating layer, on a semiconductor layer of a silicon substrate; an impurity diffused layer formed on a semiconductor layer of an active region and forming a source region or a drain region; and contact areas formed on a gate electrode present in the active region, and does not include a silicide layer on the impurity diffused layer (see, for example, Japanese Patent Application Laid-Open (JP-A) No. 2001-189429, p. 1, FIG. 3).
By connecting the gate electrode to a metal wiring layer, which is disposed above and along the gate electrode, at a plurality of points via the contact areas, an apparent gate resistance can be reduced. However, a stress is generated when the contact areas for connection are formed on the gate electrode. In order to avoid the stress affecting the gate insulating layer, and in order to prevent the gate insulating layer from being damaged by etching, a pad-like insulating layer is provided under the gate electrode at areas where the contact areas are formed. Therefore, the structure becomes complicated and this complicates the layout design.
Technical backgrounds for the invention will be described below in more detail.
In recent years, development of SOI (Silicon On Insulator) devices, which are excellent in accomplishing high-speed LSIs and low power consumption, are progressing. For producing the SOI devices, a SALICIDE (Self-Aligned Silicide) process is particularly favored. The salicide process is a technique of forming silicide, which is a compound of silicon and a metal, on an impurity diffused layer and polysilicon.
FIGS. 5A and 5B show a structure of a main portion of a salicide NMOS transistor 100 created on a SOI substrate. FIG. 5A is a plan view, and FIG. 5B is a sectional view of the main portion taken along line A—A in FIG. 5A.
The NMOS transistor is fabricated by a MOS process on the SOI substrate, which includes a buried oxide film 102 on a P semiconductor substrate 101.
Low resistance silicides 106, 107 and 108 are respectively formed on impurity diffused layers formed of a source (or drain) region 103 and a drain (or source) region 104, as well as on a gate electrode 105 formed of polysilicon. An interlayer insulating layer 115 is formed over the silicides, and contacts 116, which connect the silicides 106 and 107 to metal wiring (not shown) formed on the interlayer insulating layer 115, are formed in the interlayer insulating layer 115.
Usually, such a salicide transistor is very weak to ESD (Electro-Static Discharge). This is because that a surge current due to ESD flows through the low resistance silicide layer which lies above the drain or source, and a stress of a heavy-current after breakdown concentrates at a PN junction surface region 110 or 111, and therefore, junction breakdown is likely to be caused. This surge current is generated in the following mechanism.
In a case of a NMOS transistor, for example, when a positive surge voltage due to ESD is applied to the drain, breakdown is caused between the drain region (N+) and the body region (P−). Then, holes are accumulated in the body region and a potential at the body region is raised. As the potential at the body region is raised beyond a potential barrier at the PN junction between the body region (P−) and the source region (N+), a parasitic NPN bipolar transistor, formed of the drain region (N+)—the body region (P−)—the source region (N+), is turned on and the ESD surge current flows from the drain to the source as a bipolar current.
In order to prevent element breakdown caused by ESD, salicide block-type NMOS transistors have been proposed. FIGS. 6A and 6B show a structure of a main portion of a salicide block NMOS transistor 130. FIG. 6A is a plan view, and FIG. 6B is a sectional view of the main portion taken along line B—B in FIG. 6A. It should be noted that elements which are substantially common with those of the salicide NMOS transistor 100 in FIGS. 5A and 5B are designated by the same reference numerals.
The salicide block NMOS transistor 130 is a transistor which is produced such that, when the silicide is formed, a salicide block is formed at a salicide block area 139, which includes the gate electrode 105 and partial areas of a source (drain) 133 and a drain (source) 134 in the vicinity of the gate electrode 105, so that the silicide is not formed in this area.
With this structure, the surge current due to ESD does not concentrate at a portion in the impurity diffused layer and flows relatively uniformly so that electric field concentration is not caused. Further, a resistor component in the impurity diffused layer, at areas of the drain and the source where the silicide is not formed thereon, causes a drop in the high ESD surge voltage, and the stress applied to the PN junction is reduced. Thus, ESD resistance is remarkably improved.
The salicide block area is provided so as to extend to both of the drain and the source. This is because that, unlike to a process using a bulk substrate, where no breakdown is caused at a PN junction at a source side when potentials at a well and at the source are the same, in a SOI device having a complete element isolation structure using a buried oxide film and a field oxide film, PN junction breakdown may be caused by breakdown at the source side depending on a polarity of the ESD surge. The same applies to a PMOS transistor.
The salicide block transistor having excellent ESD resistance, as described above, is used, for example, as a final output transistor in a LSI which operates as a semiconductor integrated circuit device. FIG. 8 is a circuit diagram of a main portion showing a position, in a circuit configuration, of a salicide block NMOS transistor 144 used as a final output transistor in an output circuit in an LSI 140.
As shown in FIG. 8, the salicide block NMOS transistor 144 forms, together with a salicide block PMOS transistor 143, a push-pull output circuit, where a drain is connected to an output terminal 142 of the LSI 140. Further, a protective circuit 141 is provided in a wiring path connecting the drain to the output terminal 142.
With this structure, the salicide block transistors 143 and 144, which have excellent ESD resistance, are not broke down even when an ESD surge is applied to the output terminal 142. While, transistors in an internal circuit 145 are protected by the protective circuit 141. Therefore, salicide MOS transistors, such as shown in FIGS. 5A and 5B described above, can be used for forming the internal circuit 145.
FIGS. 7A and 7B show an exemplary structure of the salicide block NMOS transistor 144 shown in the circuit diagram of FIG. 8. FIG. 7A is a plan view, and FIG. 7B is a sectional view of a main portion taken along line C—C in FIG. 7A.
As shown in FIGS. 7A and 7B, the NMOS transistor is fabricated on a SOI substrate by a MOS process. The SOI substrate includes silicon 152 having a buried oxide film therein, formed on a P semiconductor substrate 151 serving as an insulating layer.
During a silicide forming process, no silicide is formed on partial areas of an impurity diffused layer formed of a source (or drain) region 154 and drain (or source) regions 153 and 155, as well as on polysilicon gate electrodes 158 and 159 formed on body regions 156 and 157 via oxide films 160 and 161, because of salicide blocks formed in salicide block areas 162a and 162b, and low resistance silicides 170, 171 and 172 are respectively formed in only areas other than these areas.
An interlayer insulating layer 163 is formed over the silicides. Further, on top of the interlayer insulating layer 163, drain (source) metal wiring 164, source (drain) metal wiring 165 and gate metal wiring 167 are formed. The drain (source) metal wiring 164 includes a connecting portion 164a extending along the silicide 170, a connecting portion 164b extending along the silicide 172, and a coupling portion 164c coupling the connecting portions 164a and 164b together. The source (drain) metal wiring 165 extends along the silicide 171. The gate metal wiring 167 electrically couples the two gate electrodes 158 and 159 with each other.
Further, the interlayer insulating layer 163 is provided with contacts 175 for electrically connecting the silicide 170 to the connecting portion 164a at a plurality of points, contacts 176 for electrically connecting the silicide 172 to the connecting portion 164b at a plurality of points, contacts 177 for electrically connecting the silicide 171 to the source (drain) metal wiring 165 at a plurality of points, and contacts 178 for electrically connecting the two gate electrodes 158 and 159 to the gate metal wiring 167. As described above, the salicide block NMOS transistor 144 used as the final output transistor here has a structure where two salicide block transistors having a large gate width W are arranged in parallel with each other.
By making the transistors having a large gate width W into the salicide block transistor, since resistance of polysilicon of the gate electrodes is large at portions of the gate electrodes which are far from the gate metal wiring 167, to which a gate signal is connected, a very large gate resistance, which is equivalent to a resistor 147, is inevitability inserted. For a device requiring high-speed operation, increase in a gate delay time at the final output transistor has to be avoided.
Therefore, although it is ideal for the salicide block NMOS transistor 144 shown in FIGS. 7A and 7B to have a structure where the low resistance silicide layer is formed only on the gate electrodes 158 and 159, considering an accuracy of masking of the salicide block and the gate electrodes, the silicide layer is inevitably formed also on a part of the drain or source in the vicinity of the gate electrodes 158 and 159, and this lowers ESD resistance. It should be noted that, as a measure against this, a method for reducing the gate resistance without forming the silicide layer on the gate electrodes is disclosed in the above-cited JP-A No. 2001-189429.
The present invention is made on the above-described technical background, and solves the above-described prior-art problems.

Semiconductor device including first and second transistor groups and semiconductor integrated circuit device