A switching power supply device control circuit and switching power supply can combat fluctuation due to the input voltage in the peak current of a switching element, even when using an oscillator. A control IC is connected to a switching element and to a current detecting resistor, and controls the switching element, the control IC being configured of an OCP comparator that detects an overcurrent with respect to a load, an overcurrent level setting circuit that corrects a fluctuation occurring in the peak current of the switching element in response to the output voltage from the AC input, an oscillator having a frequency modulating function whereby the switching frequency with respect to the switching element can be modulated, and a slope compensation circuit that generates a slope compensation signal increasing monotonically in proportion to the time from the start of each cycle of an oscillating signal of the oscillator.

1. Field
Embodiments of the present invention relate to a control circuit and switching power supply of a flyback type switching power supply device that converts the voltage of an AC input that turns a switching element on and off into a predetermined direct current voltage and supplies the voltage to a load, and in particular, relate to a control circuit and switching power supply of a switching power supply device that can combat fluctuation due to the voltage value of the AC input in an overcurrent peak current flowing through the switching element.
2. Description of the Related Art
FIG. 5 shows a circuit configuration of a flyback power supply using a PWM controlling integrated circuit (IC).
An AC input 1 is supplied via a transformer 2 and capacitor 3 configuring an input filter to a diode bridge 4, and rectified to a direct current input voltage. A capacitor 5 is provided between the diode bridge 4 and a ground, and has a function of absorbing switching noise. Also, a diode 6 supplies the half-wave rectified AC input 1 via a current limiting resistor 7 to a VH terminal of a control IC 8. Current input into the VH terminal is limited by the current limiting resistor 7.
A thermistor 9 for carrying out heated latch protection of the control IC 8 is connected to an LAT terminal of the control IC 8. Also, the voltage of a sense resistor 12 is input via a noise filter formed of a capacitor 10 and resistor 11 into an IS terminal of the control IC 8. A VCC terminal of the control IC 8 is connected to one end of a capacitor 13, and is connected via a backflow preventing diode 14 to an auxiliary winding 15 of a transformer T. The capacitor 13 holds a power supply voltage supplied to the control IC 8 when a PWM control operation is carried out. Also, the backflow preventing diode 14 acts so as to prevent a backflow of current from the VCC terminal to the auxiliary winding 15.
One end of a primary winding 16 of the transformer T is connected to the capacitor 5, while the other end is connected to the drain terminal of a MOSFET 17. Also, the source terminal of the MOSFET 17 is earthed via the sense resistor 12, and a drain current Ids flowing through the MOSFET 17 is detected by the sense resistor 12. That is, an on-state current of the MOSFET 17 is converted in the sense resistor 12 into a voltage signal of a size proportional to the on-state current, and the voltage signal is supplied via the noise filter to the IS terminal of the control IC 8.
One end of a secondary winding 18 of the transformer T is connected to a diode 19, and also earthed via a capacitor 20. The voltage of the capacitor 20 is sent from the secondary side to the primary side by a photocoupler 21 as information relating to the output voltage supplied to a load 25. That is, the photocoupler 21 is connected in series to a shunt regulator 22, a connection point of resistors 23 and 24 that divide the output voltage is connected to the shunt regulator 22, and the divided output voltage value and an unshown reference voltage are compared by the shunt regulator 22. As a result of this, information on an error in the secondary side output voltage with respect to the reference voltage is converted into a current signal, and load information is sent to the primary side by the current signal driving the photocoupler 21.
In a switching power supply device configured using the PWM controlling control IC 8, the rectified AC input voltage is converted via the transformer T into a predetermined DC voltage by a switching operation of the MOSFET 17 being controlled. In the control IC 8 configured of an IC circuit, load information output to the load 25 on the secondary side of the transformer T is fed back to an FB terminal of the control IC 8 via the shunt regulator 22 and photocoupler 21, as heretofore described, and detected. Also, the voltage of the MOSFET 17 drain current is converted in the sense resistor 12, and the voltage is detected by the IS terminal of the control IC 8. By the FB terminal voltage and IS terminal voltage being compared, and the on-state duration of the MOSFET 17 being variably controlled from an OUT terminal, it is possible to perform the PWM control of the switching power supply device, and thus possible to regulate the power supplied to the secondary side load 25.
FIG. 6 is a block diagram showing an internal circuit configuration of a related PWM controlling control IC.
A start-up circuit (Startup) 31 supplies current from the VH terminal to the VCC terminal when starting up, and on the AC input 1 being applied to the flyback power supply, current flows in the control IC 8 from the VH terminal via the start-up circuit 31 to the VCC terminal. Because of this, the capacitor 13, which is externally connected to the VCC terminal, is charged, and the voltage value thereof rises.
A low voltage malfunction prevention circuit (UVLO) 32 is connected to the VCC terminal and a reference power supply V1. The low voltage malfunction prevention circuit 32 is such that a UVLO signal, which is the output of the low voltage malfunction prevention circuit 32, changes to an L (Low) level on the voltage value of the VCC terminal rising to or above the reference power supply V1, an internal power supply (5VReg.) 33 starts up, and a supply of power to each circuit in the control IC 8 is carried out, while conversely, the UVLO signal is at an H (High) level while the VCC terminal voltage is low, stopping the operation of the control IC 8.
An oscillator (OSC) 34 is connected to the FB terminal, and a frequency modulation function is incorporated therein in order to reduce EMI (electromagnetic interference) noise generated by a switching operation of the MOSFET 17. The oscillator 34 determines the switching frequency of the MOSFET 17 according to the control IC 8, also has a function, separate from the heretofore described frequency modulation function, of lowering the oscillation frequency when there is a light load, and outputs an oscillating signal (a maximum duty cycle signal) Dmax. The oscillating signal Dmax is a signal with a long H level time that changes to an L level for a short time in every cycle, the cycle thereof is the switching cycle of the switching power supply, and the ratio between the cycle and the time of the H level during the cycle provides a maximum time ratio (maximum duty cycle) of the switching power supply. Also, a slope compensation circuit 35 is connected to the IS terminal, and includes a function of preventing sub-harmonic oscillation, of a kind to be described hereafter.
An FB comparator 36 is connected to the FB terminal and a reference power supply V2. When the FB terminal voltage falls below the reference power supply V2, it is determined that the output voltage is excessive, and a clear signal CLR is output from the FB comparator 36 to a one-shot circuit 37 of a subsequent stage, stopping the switching operation. The one-shot circuit 37 is triggered by the rise of the oscillating signal Dmax of the oscillator 34, and generates a set pulse for an RS flip-flop 38 of a subsequent stage. Also, while the H level clear signal CLR is being input, the one-shot circuit 37 does not output a set pulse for the RS flip-flop 38.
The RS flip-flop 38, together with an OR gate 39 and an AND gate 40, forms a PWM signal. That is, a blanking signal, which is a sum (OR) signal of two input output signals—the output signals of the one-shot circuit 37 and RS flip-flop 38—is generated in the OR gate 39. Basically, the blanking signal forms the PWM signal, but furthermore, the maximum duty cycle of the PWM signal is determined in the AND gate 40 based on the oscillating signal Dmax of the oscillator 34.
The UVLO signal output from the low voltage malfunction prevention circuit 32 is supplied via an OR gate 41 to a drive circuit (OUTPUT) 42, and the gate of the MOSFET 17 is on/off controlled by a switch signal Sout output via the OUT terminal from the drive circuit 42. That is, when the VCC terminal voltage is low and the UVLO signal is at an H level, the output of the drive circuit 42 is turned off (a signal causing the MOSFET 17 to be turned off is output). Conversely, when the VCC terminal voltage is high and the UVLO signal is at an L level, the drive circuit 42 on/off controls the gate of the MOSFET 17 in accordance with the output signal of the AND gate 40.
A level shift (Level Shift) circuit 43 has a function of shifting the level of the FB terminal voltage to a voltage range that can be input into an IS comparator 44, and the output signal of the level shift (Level Shift) circuit 43 is supplied to the inversion input terminal (−) of the IS comparator 44. The output signal of the slope compensation circuit 35 is supplied to the non-inversion input terminal (+) of the IS comparator 44. A power supply voltage Vcc is connected via a resistor R0 to the FB terminal, and the resistance R0 is the load resistance of a phototransistor configuring the photocoupler 21. Because of this, the size of the load 25 connected to the switching power supply device is detected from the drop in voltage from the power supply voltage Vcc according to the resistance R0.
The slope-compensated IS terminal voltage and the level-shifted FB terminal voltage are compared in the IS comparator 44, thus determining the timing at which the MOSFET 17 is turned off. Also, an OCP comparator 45 that determines the overcurrent protection level of the MOSFET 17 is connected to the IS terminal of the control IC 8. The non-inversion input terminal (+) of the OCP comparator 45 is connected to the IS terminal and the inversion input terminal (−) is connected to a reference power supply V3, respectively, and the OCP comparator 45 determines the overcurrent protection level of the MOSFET 17. Further, an off-state signal from the IS comparator 44 and an off-state signal from the OCP comparator 45 are both supplied via an OR gate 46 to the reset terminal of the RS flip-flop 38.
Current from a current source 47 is supplied via the LAT terminal to the thermistor 9. An LAT comparator 48 is connected to the LAT terminal and a reference power supply V4 and, on detecting that the voltage of the LAT terminal (that is, the voltage of the thermistor 9) has fallen to or below the voltage of the reference power supply V4, determines that there is a heated condition, and outputs a set signal to a latch circuit 49. The latch circuit 49 receives the set signal of the LAT comparator 48, and outputs an H level latch signal Latch to the OR gate 41 and an OR gate 51. Because of this, the drive circuit 42 and start-up circuit 31 are turned off. Also, the UVLO signal of the low voltage malfunction prevention circuit 32 is supplied to the reset terminal of the latch circuit 49, and a latching condition is deactivated when the potential of the VCC terminal falls.
On the internal power supply 33 starting up and power being supplied to the internal circuit, voltage is applied via the resistor R0 and FB terminal to the phototransistor configuring the photocoupler 21, and the FB terminal voltage rises. On the FB terminal voltage signal rising to or above a constant voltage value, the oscillating signal Dmax is output from the oscillator 34, and a set pulse is output from the one-shot circuit 37 to the RS flip-flop 38, triggered by the rise of the oscillating signal Dmax. The set pulse is input into the OR gate 39 together with the output signal of the RS flip-flop 38, and a blanking signal is generated as heretofore described. Further, this signal is output as a PWM signal from the OUT terminal, via the AND gate 40 and drive circuit 42, to the gate terminal of the MOSFET 17, becoming the switch signal Sout and driving the MOSFET 17. Because of this, the MOSFET 17 is turned on at the rise of the oscillating signal Dmax. Taking the sum (OR) of the output signal of the RS flip-flop 38 and the set pulse from the one-shot circuit 37 is done so that, even in a condition wherein the RS flip-flop 38 is left reset for some reason, the MOSFET 17 is turned on for the duration of the set pulse from the one-shot circuit 37. As the drain current Ids flows through the sense resistor 12 when the MOSFET 17 is turned on, the voltage of the IS terminal of the control IC 8 rises.
Further, on the slope-compensated IS terminal voltage of the control IC 8 reaching a voltage which is the FB terminal voltage level-shifted by the level shift circuit 43, a reset signal is output from the IS comparator 44 to the RS flip-flop 38 via the OR gate 46. By the RS flip-flop 38 being reset, the output of the OR gate 39 changes to an L level (during normal operation, the set pulse from the one-shot circuit 37 is at an L level at this point), and as the output of the AND gate 40 also changes to an L level in response, the MOSFET 17 is turned off by the switch signal Sout.
Also, even in the event that the load 25 connected to the switching power supply device becomes extremely heavy, and the voltage value fed back to the FB terminal of the control IC 8 is outside the (high voltage side) control range, it is possible, by comparing the voltage value of the IS terminal with the constant reference voltage value V3 using the OCP comparator 45, to turn off the MOSFET 17 when the voltage value of the IS terminal is equal to or higher than the reference voltage value V3.
Before the level-shifted FB terminal voltage is compared with the IS terminal voltage in the IS comparator 44, slope compensation whereby a slope compensation voltage proportional to the on-state duration of the MOSFET 17 is added is carried out on the IS terminal voltage by the slope compensation circuit 35. Generally, provided that the MOSFET 17 is operating in a steady state, the sizes of the current flowing through the MOSFET 17 at the start and end of the switching cycle coincide. However, when the duty cycle (on-state time ratio=on-state time duration/switching cycle) of the MOSFET 17 becomes too long, the sizes of the current are no longer able to coincide, and the condition of the current flowing through the MOSFET 17 fluctuates with each switching cycle. This kind of oscillation at low frequency is known as sub-harmonic oscillation, but there are conditions for this sub-harmonic oscillation to occur. Sub-harmonic oscillation can be prevented by slope compensation whereby a monotonically increasing signal is superimposed on the IS terminal voltage, thus preventing the conditions from being established (refer to PTL 1).
FIG. 7 is a circuit diagram showing one example of a heretofore known slope compensation circuit, while FIG. 8 is a timing diagram showing a slope compensation signal generated by the slope compensation circuit of FIG. 7.
Hereafter, a description will be given, based on the timing chart shown in FIG. 8, of a slope compensation operation in the slope compensation circuit 35.
In FIG. 7, the IS terminal voltage signal is input into an input terminal 35a, while the oscillating signal Dmax of the oscillator 34 is input into an input terminal 35b. The gate terminal of each of a serially-connected p-channel transistor M1 and n-channel transistor M2 is connected via an inverter 351 to the input terminal 35b. Of the serially-connected transistors M1 and M2, the source terminal of the M1 is connected to a current source circuit I1, the source terminal of the M2 is grounded, and the commonly connected drain terminals are connected to the base of a PNP transistor T1. Also, a connection point of the transistors M1 and M2 is connected to one end of a capacitor C1, while the other end of the capacitor C1 is grounded.
The emitter of the PNP transistor T1 is connected to the base of an NPN transistor T2 and a current source circuit I2, while the collector of the PNP transistor T1 is grounded. The collector of the NPN transistor T2 is connected to the power supply Vcc, while the emitter of the NPN transistor T2 is connected via serially-connected resistors R1 and R2 and the input terminal 35a to the IS terminal. Also, a connection point of the resistors R1 and R2 is connected to an output terminal 35c.
The slope compensation circuit 35 with the heretofore described configuration is such that the oscillating signal Dmax from the oscillator 34 is supplied to the input terminal 35b, and when the oscillating signal Dmax is at an H level, the transistor M1 is turned on, the transistor M2 is turned off, and the capacitor C1 is charged by the current from the current source circuit I1. This monotonically increasing integrated voltage is applied to the base of the PNP transistor T1 as the kind of continuously rising voltage signal Sa shown in FIG. 8. The voltage signal Sa is level shifted by two emitter followers formed one by each of the PNP transistor T1 and NPN transistor T2 (the level shift amount=(the base-emitter voltage of the PNP transistor T1)−(the base-emitter voltage of the NPN transistor T2)≈0), and a voltage of the same level as the voltage signal Sa is generated at the emitter of the NPN transistor T2. Also, as shown by a dotted line in FIG. 8, the IS terminal voltage signal also rises continuously from a timing t1 at which the MOSFET 17 is turned on. The inclination of the voltage signal is determined by the inductance value of the primary winding 16 of the transformer T shown in FIG. 5 and the input voltage from the AC input 1 (the voltage value of the capacitor 5). It can be assumed that the voltage value of the capacitor 5 is constant within one switching cycle.
Herein, the rise of the oscillating signal Dmax and the turning on of the MOSFET 17 occur at the same timing, because of which, taking the resistance values of the resistors R1 and R2 to be R1 and R2 respectively, the waveform of the voltage signal Sa is added at a voltage division ratio (R1/(R1+R2)) to the IS terminal voltage signal, and output from the output terminal 35c. The voltage waveform of the output terminal 35c is compared in the IS comparator 44 with the feedback voltage waveform from the FB terminal shown in FIG. 6 level shifted by the level shift circuit 43, and when the voltage of the output terminal 35c rises above the level-shifted feedback voltage, the output of the IS comparator 44 changes to an H level. This signal resets the RS flip-flop 38 via the OR gate 46, and as an output Q of the RS flip-flop changes to an L level, the MOSFET 17 is turned off by the drive circuit 42.
At a timing t2 at which the oscillating signal Dmax changes to an L level, the transistor M2 is turned on, and the charge of the capacitor C1 is swiftly released. Because of this, the output voltage of the slope compensation circuit 35 (the voltage of the output terminal 35c) becomes zero, voltage is added again from zero potential when the MOSFET 17 is next turned on, and the switching power supply device is subject to the PWM controlling.
FIG. 9 is a circuit diagram showing one example of a heretofore known oscillator including a frequency modulating function.
The heretofore known oscillator 34 shown in FIG. 9 is configured of current source circuits I3 and I4, which cause a constant current to flow, a p-channel transistor M3 connected via the current source circuit I3 to the power supply Vcc, an n-channel transistor M4 connected in series to the transistor M3 and grounded via the current source circuit I4, a timing capacitor C2, one end of which is connected to a connection point of the transistors M3 and M4 and the other end of which is grounded, comparators 341 and 342 that set a charge voltage upper limit value and discharge voltage lower limit value respectively of a voltage signal Sb of the timing capacitor C2, a frequency modulating modulation period setting circuit 343, to be described hereafter, an AND gate 344 into which an output signal Sc of the modulation period setting circuit 343 and the output signal of the comparator 341 are input, an RS flip-flop 345 that turns the transistors M3 and M4 on and off in a complementary way, and an inverter 346. When it is determined from the feedback signal to the FB terminal that there is a light load condition, the oscillator 34 functions so as to reduce the switching frequency by reducing the current values of the current source circuits I3 and I4, but with regard to the description of the oscillator, it may be supposed that the current is constant.
A first reference voltage V5 is input into the inversion input terminal (−) of the comparator 341, while a second reference voltage V6 is input into the non-inversion input terminal (+) of the comparator 342. The first reference voltage V5 and second reference voltage V6 specify the charge voltage upper limit value and discharge voltage lower limit value respectively of the voltage signal Sb of the timing capacitor C2, and have a relationship such that V5>V6. The output terminal of the comparator 342 is connected to a set terminal S of the RS flip-flop 345, while the output terminal of the comparator 341 is connected via the AND gate 344 to a reset terminal R of the RS flip-flop 345. The Q output (the signal output from the output terminal Q is taken to be the Q output) of the RS flip-flop 345 is supplied from the RS flip-flop 345 to an output terminal 34a of the oscillator 34, output as the oscillating signal Dmax, and connected via the inverter 346 to the gate of each of the transistors M3 and M4.
Now, it will be assumed that the output terminal of the comparator 341 is connected directly to the reset terminal R of the RS flip-flop 345, and that the oscillator 34 has no frequency modulating modulation period setting function. In this case, on the voltage signal Sb of the timing capacitor C2 reaching the first reference voltage V5 input into the inversion input terminal of the comparator 341 at the timing at which the timing capacitor C2 is charged by the current from the current source circuit I3, the flip-flop 345 is immediately reset, and the on and off-states of the transistors M3 and M4 are inverted. Because of this, the timing capacitor C2 is discharged by the current of the current source circuit I4, and on the voltage signal Sb reaching the second reference voltage V6 input into the non-inversion input terminal of the comparator 342, the flip-flop 345 is immediately set, and the on and off-states of the transistors M3 and M4 are inverted again. In this way, an operation whereby the timing capacitor C2 is charged by the current source circuit I3 then discharged by the current source circuit I4 is repeated. Consequently, the length of timings t1 to t4 shown in FIG. 10, to be described hereafter, is specified by the total duration of the charging period and discharging period of the timing capacitor C2 (the length of t2 to t3 is zero). Because of this, the switching frequency of the MOSFET 17 shown in FIG. 5 is determined by the timing capacitor C2 alone, while the maximum duty cycle is specified by only the charging period and discharging period of the timing capacitor C2.
As opposed to this, the oscillator 34 of FIG. 9 equipped with the frequency modulating function is such that it is possible, using the modulation period setting circuit 343, to provide a modulation period (idle period), whose temporal length fluctuates with each cycle, between the charging period and discharging period. Consequently, the cycle of the oscillator 34 oscillating signal, that is, the switching cycle of the switching power supply, is the sum of the charging period, the modulation period (idle period), and the discharging period.
The modulation period setting circuit 343 is configured of an inverter 347 that inverts the output signal of the comparator 341, a current source circuit I5 connected to the power supply Vcc, a p-channel transistor M5 and n-channel transistor M6, whose gate terminals are connected to the output terminal of the inverter 347 and which are turned on and off alternately, a counter 348 that sets an idle period, p-channel transistors M71, M72 to M7n selected by an n-bit on/off signal of the counter 348, and capacitors C31, C32 to C3n connected in series to the transistors M71, M72 to M7n respectively.
FIG. 10 is a timing diagram showing a signal waveform of each portion of the oscillator.
Herein, a description will be given of the waveform of the oscillating signal Dmax shown in FIG. 10 output from the oscillator 34.
The oscillator 34 shown in FIG. 9 is such that, although the operation of charging the timing capacitor C2 finishes at the timing t2, a modulation period (idle period t2 to t3) is provided from the timing t2 to t3, rather than starting discharging immediately after the charging operation. That is, the modulation period setting circuit 343 is such that when the operation of charging the timing capacitor C2 finishes, the current of the current source circuit I5 starts charging the capacitors C31, C32 to C3n via the selected transistors M71, M72 to M7n. The operation of discharging the timing capacitor C2 starts at a timing t3 at which the charging of the capacitors C31, C32 to C3n is completed (that is, the timing at which the voltage Sc, which is the charge voltage of the capacitors C31, C32 to C3n, reaches a threshold value voltage with respect to the input of the AND gate 344). The modulation period setting circuit 343 is such that the capacitance values of the capacitors C31, C32 to C3n can be switched by turning on or off the switches of the p-channel transistors M71, M72 to M7n, because of which the length of the charging period of the capacitors C31, C32 to C3n, that is, the modulation period (idle period t2 to t3), varies. In this way, the oscillator 34 is such that it is possible, using the modulation period setting circuit 343, to set a modulation period (idle period t2 to t3) between the frequency fixing periods (t1 to t2, t3 to t4) of the oscillating signal Dmax of the oscillator 34.
In this way, the modulating method of the oscillator 34 equipped with a frequency modulating function is such that it is possible to modulate the frequency of the oscillating signal Dmax by modulating the idle period t2 to t3 of the timing capacitor C2. This is because the switching cycle of the MOSFET 17 is specified by the total of the charging period (t1 to t2) of the timing capacitor C2, the charging period (t2 to t3) of the capacitors C31, C32 to C3n, and the discharging period (t3 to t4) of the timing capacitor C2. In this way, it is possible to modulate the switching frequency of the switch signal Sout by modulating the idle period of the timing capacitor C2. Further, the charging period of the capacitors C31, C32 to C3n is inversely proportional to the total capacitance value of the capacitors connected to the current source circuit I5, and which capacitors are to be connected is determined by the p-channel transistors M71, M72 to M7n, which are turned on or off in accordance with the count value of the counter 348, which value is lowered or raised with each cycle of the oscillating signal Dmax (each switching cycle) (refer to PTL 2).
Regarding the way of modulating the switching cycle, various methods have been proposed to date, apart from that heretofore described.
The control IC 8 described above is such that level limitation is carried out by the OCP comparator 45 so that the drain current Ids flowing through the MOSFET 17 does not rise to or above the constant current. This is as has already been described based on FIG. 6, which shows the internal circuit configuration of the IC 8.
FIGS. 11A and 11B are diagrams showing changes in the overcurrent protection level when the input voltage changes.
The MOSFET 17 is turned off after the size of the drain current Ids flowing when the MOSFET 17 is in an on-state reaches an overcurrent detection level, but a certain delay time r is needed until the drain current Ids is actually cut off, as shown in FIG. 11A. The length of the delay time τ is specified by a current detecting terminal noise filter, circuit delay factors inside the control IC 8, a delay time in the switching operation of the MOSFET 17 itself, or the like. Further, when the input voltage from the AC input 1 is high, the inclination of the current flowing through the primary winding 16 of the transformer T when the MOSFET 17 is turned on increases, as shown in FIG. 11B. Although the angle of inclination also depends on the inductance value of the primary winding 16, the inclination when the input voltage is low is gentle, as shown in FIG. 11A, while the inclination is steep when the input voltage is high.
However, as shown in FIG. 6, the overcurrent detection voltage in the OCP comparator 45 is set to a constant value in accordance with the reference power supply V3. Because of this, the inductance current (=Ids) flowing during the delay time r continues to rise, and the current limit value when the MOSFET 17 is actually turned off is such that the higher the input voltage from the AC input 1, the higher the value of the peak current when an overcurrent protection operation is carried out. Generally, as the current limit value set for the load 25 is determined in accordance with the overcurrent detection level when the input voltage is low, a current higher than the overcurrent detection level desired by the designer flows when the input voltage is high. Consequently, the heretofore known flyback power supply whose PWM is to be controlled is such that it is necessary to increase the rated current of the MOSFET 17, transformer T, and the like, which is a factor leading to an increase in the cost and size of the power supply device.

Switching power supply device control circuit having an overcurrent protection control circuit


Simplified wireless device activation may be achieved using temporary and permanent numbers used to connect to a wireless service provider. In one implementation, an electronic book reader device includes a memory that contains a temporary number that may be used to connect to a wireless service provider. The temporary number may be replaced with a permanent number that is used to connect to the wireless service provider. This replacement may occur once the electronic book reader device connects with the wireless service provider for the first time. The permanent number may be used to connect to the wireless service provider after the initial connection with the wireless service provider has transpired.

Generally, an activation process for a recently acquired wireless device is an intensive and time consuming process. The process often requires a user to bring the wireless device to a service center or retailer in order to activate the device. A representative at the service center or retailer manually programs the wireless device with a telephone number. The representative normally has to also notify a wireless service provider of the assigned telephone number and a serial number associated with the wireless device. Improving the activation process for wireless devices may be beneficial to both providers and customers using the devices.

Over-the-air device provisioning and activation


An antenna including a planar conductor, in which the planar conductor is self-supporting and the radiating pattern of the antenna is substantially isotropic.

Monopole antennas are commonly used in radio antenna design for mobile applications. A monopole antenna has a single radiating element. The simplest monopole antenna is the quarter-wave isotropic antenna. It comprises two elements, the first being a conductive radiating element that is usually a round structure and has an electrical length of ¼ wavelength. The second element is a ground plane element.
Quarter-wave antennas are excellent performing antennas and are the smallest resonating structures that are used when the radiating structure is straight. Unfortunately, the radiating structure length in radio frequency (hereinafter "RF") bands now used in wireless communications can be prohibitively long for low profile enclosures. For example, the radiating element for a quarter-wave antenna operating at 2.4 Gigahertz (hereinafter "GHz") to 2.5 GHz would be about 1.1 inches in length.
Vertically polarized antennas are often used in mobile applications, either as the portable terminal or the base station. However, currently available vertically polarized antennas such as the quarter-wave antenna, are often too large for current applications, where compactness is extremely important. For example, in a personal digital assistant, an extremely small antenna is particularly desirable.
Horizontally polarized antennas may be very low profile when antennas are etched on a radio personal computer (hereinafter "P.C.") board (such as a PCMCIA or Compact Flash card), but suffer from attenuated performance in mobile applications due to incorrect polarity for most applications. Single and dual element (quarter-wave and dipole) horizontally polarized antennas have deep signal nulls around the antennas, even when the units being communicated with use the same polarization. Most mobile applications use vertically polarized antennas (monopoles) to eliminate nulls around the antennas.
What are needed are antennas to overcome the problems described above.


A carry look-ahead circuit for an adder to decrease circuit size and power consumption. The carry look-ahead circuit is composed of 2-input NAND gates 101, 102, 2-input NOR gate 103, AND-NOR type composite gates 201, 202, OR-NAND type composite gate 251, or other gates with 2 or less series stages of transistors inserted between the output terminal and the power source line or the ground line. When the number of series stages of transistors increases, the driving power decreases. Consequently, in order to maintain the same operation speed, it is necessary to increase the transistor size. The use of multi-input NAND gates and NOR gates, makes it possible to suppress the number of series stages of transistors and to reduce the transistor size. As a result, it is possible to decrease the circuit size and power consumption.

When an adder is formed, the most important factor related to the efforts to increase the operation speed is the delay in propagation of the carry signal. For example, in a ripple carry type adder, because the carry signal is propagated sequentially from the least significant position to the most significant position, a delay time is generated proportional to the bit length of the addition object signal until the operation result and overflow of the most significant position are determined.
FIG. 16A is a circuit diagram illustrating an example of constitution of a ripple carry type adder that adds 4-bit signals. The ripple carry type adder shown in FIG. 16A is composed of four full adders (1)-(4).
Full adders (1)-(4) take 1-bit carry signal C1 of from the lower position as input, and at the same time, have 1-bit signals a and b as addition objects as inputs. Then, each of the full adders outputs 1-bit signal s as the addition result, and at the same time, outputs 1-bit carry signal c0 to the upper position. Addition result signal s and carry signal c0 are expressed by the following equations, respectively.
[Numerical Formula 1]s=a⊕b⊕c1  (1)c0=a·b+(a⊕b)·c1  (2)
The signals of the various positions of the addition object signals are input to full adders (1)-(4) shown in FIG. 16B. That is, in a corresponding order, the least significant position (a0, b0), . . . , and finally, the most significant position (a3, b3) are input to full adders (1), . . . , (4), respectively. Also, for each of full adders (1)-(4), the carry signal is input from the lower-position full adder. That is, carry signal cin from the exterior is input to full adder (1). Carry signal c0 from full adder (1) is input to full adder (2). Carry signal c1 from full adder (2) is input to full adder (3). Carry signal c2 from full adder (3) is input to full adder (4). Signals s0-s3 as addition results output from full adders (1)-(4) correspond to the least significant position-most significant position of the 4-bit addition results. The carry signal output from full adder (4) shows overflow in the 4-bit addition result.
In the adder with the constitution shown in FIG. 16A, before output of lower-position carry signal c2, the addition result s3 of the most significant position and its overflow signal c3 are not determined. Also, the carry signal c2 is not determined until output of the lower-position carry signal c1, and carry signal c1 is not determined until output of the lower-position carry signal c0.
That is, in order to determine the addition result and carry for a certain position, it is necessary to determine the carry signals of all the positions lower than the position. Consequently, the propagation path of the carry signal (indicated by broken line in FIG. 16A) becomes the longest delay path (critical path) in the ripple type adder. As the bit length of the addition object signals increases, the number of stages of full adders that have to be added increases. All these added full adders are added to the critical path. Consequently, the delay time before the final addition result can be determined increases.
As a method for alleviating the delay in propagation of the carry signal, a scheme has been proposed in which a carry look-ahead circuit is used. In this scheme, the least significant position of the addition object signal is taken as the first position, and carry signal ci formed due to addition of the (i+1)th position (where, i is a positive integer including zero) has the following relationship, which is exploited to detect the carry of the upper position without waiting for detection of the lower-position carry.
[Numerical Formula 2]
                                                                        c                i                            =                                                                                p                      ′                                        i                                                                          c                                          i                      -                      1                                                                      +                                  g                  i                                                                                =                                                                                p                      ′                                        i                                                                                p                      ′                                                              i                      -                      1                                                                                ⋯                                                                                ′                                                                                p                      ′                                        1                                                                          g                    o                                                  +                                                                                p                      ′                                        i                                                                                p                      ′                                                              i                      -                      1                                                                                ⋯                                                                                ′                                                                                p                      ′                                        2                                                                          g                    1                                                  +                                                                                ⋮                                                                                p                      ′                                        i                                                                          g                                          i                      -                      1                                                                      +                                                                                g                i                                                                        (        3        )
In Equation (3), using signals (ai, bi) of the (i+1)th position of the addition object signals, signals pi and gi can be expressed by the following equations.
[Numerical Formula 3]pi=ai⊕bi  (4)gi=ai·bi  (5)
Usually, signal pi is known as a carry propagation signal, and signal gi is known as a carry generation signal. Also, in Equation (3), carry signal c−1 is set at "0", that is, it is assumed that no carry input exists from the exterior with respect to the first position of the addition object signals. On the other hand, when external carry signal cin exists, carry signal ci is expressed by the following equation.
[Numerical Formula 4]
                                                                                c                  i                                =                                                                                p                        ′                                            i                                                                                p                        ′                                                                    i                        -                        1                                                                                ⋯                                                                                ′                                                                                p                        ′                                            o                                                                                c                                              i                                                                                n                                                                              +                                                                                p                      ′                                        i                                                                                p                      ′                                                              i                      -                      1                                                                                ⋯                                                                                ′                                                                                p                      ′                                        1                                                                          g                    0                                                  +                                                                                p                      ′                                        i                                                                                p                      ′                                                              i                      -                      1                                                                                ⋯                                                                                ′                                                                                p                      ′                                        2                                                                          g                    1                                                  +                                                                                ⋮                                                                                p                      ′                                        i                                                                          g                                          i                      -                      1                                                                      +                                                                                g                i                                                                        (                  3                    A                )
For example, if no external carry signal cin exists, by means of Equation (3) carry signal c3 from the most significant position (4th position) in the 4-bit adder can be expressed by the following equation.
[Numerical Formula 5]
                                                        c3              =                                                                            p3                  ·                  p2                  ·                  p1                  ·                  g0                                +                                                                                p3                  ·                  p2                  ·                  g1                                +                                                                                p3                  ·                  g2                                +                                                                                g3                                                          (        6        )
FIG. 17A is a circuit diagram illustrating an example of the generation circuit of carry signal c3 formed according to the relationship of Equation (6). The generation circuit of carry signal c3 shown in FIG. 17A has half adders (5)-(8), each of which is shown in FIG. 17B, 4-input NAND gates (9) and (13), 3-input NAND gate (10), 2-input NAND gate (11), and inverter (12). Half adders (5)-(8) take the addition object signals of the various positions as inputs, perform exclusive OR expressed by Equation (4) and AND expressed by Equation (5), and output a carry propagation signal and carry generation signal. That is, corresponding to the order, half adders (5), . . . , (8) have the least significant position (a0, b0), . . . , and most significant position (a3, b3) of the addition object 4-bit signals as inputs, respectively. Then, for the input addition object signals, exclusive OR and AND are performed, and then carry propagation signal/carry generation signal groups (p0, g0), . . . , (p3, g3) are output, respectively.
The 4-input NAND gate (9) takes carry generation signal g0 from half adder (5) and carry propagation signals p1-p3 output from half adders (6)-(8) as inputs, and outputs NAND of the four input signals. This output signal corresponds to the NOT signal of the first item on the right side of Equation (6). The 3-input NAND gate (10) takes carry generation signal g1 from half adder (6) and carry propagation signals p2 and p3 output from half adders (7) and (8) as inputs, and outputs NAND of the three input signals. This output signal corresponds to the NOT signal of the second item on the right side of Equation (6). The 2-input NAND gate (11) takes carry generation signal g2 from half adder (7) and carry propagation signal p3 output from half adder (8) as inputs, and outputs NAND of the two input signals. This output signal corresponds to the NOT signal of the third item on the right side of Equation (6). Inverter (12) outputs NOT of carry generation signal g3 output from half adder (8). This output signal corresponds to the signal of NOT of the fourth item on the right side of Equation (6). The 4-input NAND gate (13) takes the output signals of NAND gates (9)-(11) and inverter (12) as its inputs, and outputs NAND of the input four signals. This output signal corresponds to carry signal c3 shown in Equation (6).
With the aid of the generation circuit of carry signal c3 with the constitution, carry signal c3 can be formed directly from addition object signals (a0, . . . , a3) and (b0, . . . , b3), without waiting for determination of the lower-position carry signals (c0-c2). Compared with the ripple carry system shown in FIG. 16A, the delay in propagation of the carry signal can be shortened. The circuit shown in FIG. 17A is a circuit for forming the carry signal for the 4th position counted from the least significant position. When a carry signal is to be formed for addition of more bits, one usually adopts a system in which plural CLA circuits are connected in a hierarchical constitution.
FIG. 18 is a circuit diagram illustrating an example of the generation circuit of carry signal c15 composed of plural CLA circuits connected in a hierarchical constitution. The generation circuit of carry signal c15 shown in FIG. 18 has 4-bit half adders (21)-(24) and CLA circuits (25)-(29). 4-bit half adders (21)-(24) have the 4-bit signals obtained by dividing the 16-bit addition object signals into four portions as inputs, and they operate using Equations (4) and (5) to get a carry propagation signal and carry generation signal respectively, for the various positions. That is, half adder (21) has the addition object signals (a0, . . . , a3) and (b0, . . . , b3) of the least significant position (first position)-fourth position as inputs. Half adder (22) has the addition object signals (a4, . . . , a7) and (b4, . . . , b7) of the fifth-eighth positions as inputs. Half adder (23) has the addition object signals (a8, . . . , a11) and (b8, . . . , b11) of the ninth-12th positions as inputs. Half adder (24) has the addition object signals (a12, . . . , a15) and (b12, . . . , b15) of the 13th-16th positions as inputs.
For each position of the input addition object signals, exclusive OR according to Equation (4) and AND according to Equation (5) are determined in operation. Half adder (21) calculates and outputs carry propagation signal (p0, . . . , p3) and carry generation signal (g0, . . . , g3). Half adder (22) calculates and outputs carry propagation signal (p4, . . . , p7) and carry generation signal (g4, . . . , g7). Half adder (23) calculates and outputs carry propagation signal (p8, . . . , p11) and carry generation signal (g8, . . . , g11). Half adder (24) calculates and outputs carry propagation signal (p12, . . . p15) and carry generation signal (g12, . . . , g15).
FIG. 19 is a circuit diagram illustrating an example of constitution of 4-bit half adder (21). For example, as shown in FIG. 19, the 4-bit half adder (21) is composed of four half adders (30)-(33) of 1-bit half adders. Also, other 4-bit half adders (22)-(24) may have the same constitution as that shown in FIG. 19. CLA circuits (25)-(28) have carry propagation 4-bit signals and carry generation 4-bit signals output from 4-bit half adders (21)-(24) as inputs, respectively, and, corresponding to these signals, they output carry propagation 1-bit signals and carry generation 1-bit signals, respectively.
That is, CLA circuit (25) has carry propagation signal (p0, . . . , p3) and carry generation signal (g0, . . . , g3) of half adder (21) input to it. CLA circuit (26) has carry propagation signal (p4, . . . , p7) and carry generation signal (g4, . . . , g7) of half adder (22) input to it. CLA circuit (27) has carry propagation signal (p8, . . . , p11) and carry generation signal (g8, . . . , g11) of half adder (23) input to it. CLA circuit (28) has carry propagation signal (p12, . . . , p15) and carry generation signal (g12, . . . , g15) of half adder (24) input to it. Then, corresponding to the inputs, carry propagation 1-bit signals and carry generation 1-bit signals are calculated. That is, CLA circuit (25) calculates and outputs carry propagation signal P0 and carry generation signal G0. CLA circuit (26) calculates and outputs carry propagation signal P1 and carry generation signal G1. CLA circuit (27) calculates and outputs carry propagation signal P2 and carry generation signal G2. CLA circuit (28) calculates and outputs carry propagation signal P3 and carry generation signal G3. The input carry propagation 4-bit signals for CLA circuits (25)-(28) are represented as signals p(0)-p(3) from the lower position, also, the input carry generation 4-bit signals are represented as signals g(0)-g(3). In this case, output 1-bit carry propagation signal P and output 1-bit carry generation signal G are expressed by the following equations.
[Numerical Formula]
                                                        G              =                                                                                p                      ′                                                              (                      3                      )                                                                                p                      ′                                                              (                      2                      )                                                                                p                      ′                                                              (                      1                      )                                                                                g                                          (                      0                      )                                                                      +                                                                                p                      ′                                                              (                      3                      )                                                                                p                      ′                                                              (                      2                      )                                                                                g                                          (                      1                      )                                                                      +                                                                                p                      ′                                                              (                      3                      )                                                                                g                                          (                      2                      )                                                                      +                                                                                g                                  (                  3                  )                                                                                (        7        )                                P        =                                            p              ′                                      (              3              )                                                                    p              ′                                      (              2              )                                                                    p              ′                                      (              1              )                                                      p                          (              0              )                                                          (        8        )
FIG. 20 is a circuit diagram illustrating an example of the constitution of CLA circuit (25). Circuits (14)-(18) generating output carry generation signal G0 in CLA circuit (25) are identical to circuits (9)-(13) generating carry signal c3 shown in FIG. 17. Also, generation of carry propagation signal P0 is realized by performing operation of NAND for carry propagation signals p0-p3 in 4-input NAND gate (19), followed by NOT of the operation result with inverter (20). Other CLA circuits (25)-(28) may also have the same circuit constitution as that shown in FIG. 20. CLA circuit (29) takes output 4-bit carry propagation signal (P0, . . . , P3) and output 4-bit carry generation signal (G0, . . . , G3) from CLA circuits (26)-(28) as inputs, and corresponding to them, it outputs 1-bit carry propagation signal Po and 1-bit carry generation signal Go. For CLA circuit (29), output carry generation signal Go and output carry propagation signal Po are calculated in the same way as in CLA circuits (25)-(28) by just replacing input carry propagation signal (p(0), . . . , p(3)) and input carry generation signal (g(0), . . . , g(3)) with output carry propagation signal (P0, . . . , P3) and output carry generation signal (G0, . . . , G3) of CLA circuits (25)-(28) in Equations (7) and (8). Consequently, the circuit constitution of CLA circuit (29) can be realized in the same way as in FIG. 20.
In the generation circuit of carry signal c15 with the constitution, when i=15 in the Equation (3), output carry generation signal Go of CLA circuit (29) is equal to carry signal c15. That is, using Equation (3), carry signal c15 is expressed by the following equation.
[Numerical Formula 7]
                                                                        C                15                            =                                                                                p                      ′                                        15                                                                                p                      ′                                        14                                                                                ⋯                                                                                ′                                                                                p                      ′                                        1                                                                          g                    o                                                  +                                                                                p                      ′                                        15                                                                                p                      ′                                        14                                                                                ⋯                                                                                ′                                                                                p                      ′                                        2                                                                          g                    1                                                  +                                                                                p                      ′                                        15                                                                          g                    14                                                  +                                                                                g                15                                                                        (        9        )
Output carry propagation signals P1-P3 of CLA circuits (26)-(28) and output carry generation signal G0 of CLA circuit (25) are expressed by the following equations.
[Numerical Formula 8]
                              P          3                =                              p            15                    ·                      p            14                    ·                      p            13                    ·                      p            12                                              (                  10                    A                )                                          P          2                =                              p            11                    ·                      p            10                    ·                      p            9                    ·                      p            8                                              (                  10                    B                )                                          P          1                =                              p            7                    ·                      p            6                    ·                      p            5                    ·                      p            4                                              (                  10                    C                )                                                                                G                0                            =                                                                                p                    3                                    ·                                      p                    2                                    ·                                      p                    1                                    ·                                      g                    0                                                  +                                                                                p                    3                                    ·                                      p                    2                                    ·                                      g                    1                                                  +                                                                                p                    3                                    ·                                      g                    2                                                  +                                                                                g                3                                                                        (                  10                    D                )
By substituting Equations (10A)-(10D) into items 1-4 on the right side of Equation (9), one can represent OR W14 of items 1-4 by the following equation.
[Numerical Formula 9]
                                                                        W                14                            =                                                                                P                    3                                    ·                                      P                    2                                    ·                                      P                    1                                    ·                                      p                    3                                    ·                                      p                    2                                    ·                                      p                    1                                    ·                                      g                    0                                                  +                                                                                P                    3                                    ·                                      P                    2                                    ·                                      P                    1                                    ·                                      p                    3                                    ·                                      p                    2                                    ·                                      g                    1                                                  +                                                                                P                    3                                    ·                                      P                    2                                    ·                                      P                    1                                    ·                                      p                    3                                    ·                                      g                    2                                                  +                                                                                P                    3                                    ·                                      P                    2                                    ·                                      P                    1                                    ·                                      g                    3                                                  +                                                                                =                                                                            P                  3                                ·                                  P                  2                                ·                                  P                  1                                ·                                  G                  0                                                                                (        11        )
OR of items 5-8, items 9-12, and items 13-16 on the right side of Equation (9), just as OR W14 of Equation (11), may also be represented with the output carry propagation signals and output carry generation signals of CLA circuits (25)-(28). As a result, carry signal c15 is expressed by the following equation.
[Numerical Formula 10]
                                                                        C                15                            =                                                                                P                    3                                    ·                                      P                    2                                    ·                                      P                    1                                    ·                                      G                    o                                                  +                                                                                P                    3                                    ·                                      P                    2                                    ·                                      G                    1                                                  +                                                                                P                    3                                    ·                                      G                    2                                                  +                                                                                G                3                                                                        (                  9                    A                )
The right side of Equation (9A) is equal to output carry generation signal Go of CLA circuit (29). From this fact, one can see that output carry generation signal Go becomes equal to carry signal c15. The circuit shown in FIG. 18 is a CLA circuit that takes a 4-bit carry propagation signal and a 4-bit carry generation signal as inputs, and outputs a carry propagation 1-bit signal and carry generation 1-bit signal. Usually, for a CLA circuit that takes an N-bit carry propagation signal and an N-bit carry generation signal, output carry propagation signal P and output carry generation signal G are expressed by the following equation.
[Numerical Formula 11]
                                                        G              =                                                                                p                      ′                                                              (                                              N                        -                        1                                            )                                                                                p                      ′                                                              (                                              N                        -                        2                                            )                                                                                ⋯                                                                                ′                                                                                p                      ′                                                              (                      1                      )                                                                                g                                          (                      0                      )                                                                      +                                                                                p                      ′                                                              (                                              N                        -                        1                                            )                                                                                p                      ′                                                              (                                              N                        -                        2                                            )                                                                                ⋯                                                                                ′                                                                                p                      ′                                                              (                      2                      )                                                                                g                                          (                      1                      )                                                                      +                                                                                ⋮                                                                                p                      ′                                                              (                                              N                        -                        1                                            )                                                                                g                                          (                                              N                        -                        1                                            )                                                                      +                                                                                g                                  (                                      N                    -                    1                                    )                                                                                (        12        )                                P        =                                            p              ′                                      (                              N                -                1                            )                                                                    p              ′                                      (                              N                -                2                            )                                                                                ⋯                                                                                p              ′                                      (              1              )                                                      p                          (              0              )                                                          (        13        )
For example, for a carry look-ahead circuit made of plural CLA circuits connected in hierarchical constitution, the technology described in Patent Reference 1 is available.
For the CLA circuit used in the generation circuit of a carry signal shown in FIGS. 17 and 18, NANDs having plural inputs, such as 3 inputs and 4 inputs, are used. Usually, in a NAND gate, NOR gate, and other gates, the larger the input signal number, the larger the number of series stages of transistors inserted between the output terminal and the power source line or the ground line. For example, for a 4-input NAND gate, 4 stages of transistors are inserted in series between the output terminal and the ground line. Consequently, for a gate having plural inputs, the driving ability of the output current decreases, and the operation speed tends to decrease.
In order to suppress decrease in the speed of a multi-input gate, it is necessary to increase the size or gate width of the transistors so as to decrease the ON resistance. As a result, the circuit size increases, and due to an increase in gate capacitance, the driving loss of transistors increases. This is undesirable. However, because the generation circuit of the carry signal is the critical path of the entire adder, in order to improve the overall performance of the adder, it is necessary to increase the area of the transistors used in the plural input gates of the CLA circuit. Consequently, in a conventional CLA circuit, as a cost in increasing the operation speed of the adder, the circuit size and power consumption increase, and this is always a problem.
FIG. 5 in Japanese Kokai Patent Application No. Hei 5[1993]-61643 is a circuit diagram illustrating an example in which composite gates are used in a CLA circuit that generates the same signal as that of output carry generation signal G expressed by Equation (7). FIG. 21 is a circuit diagram illustrating an example of a CLA circuit made of the composite gates. For the composite gate shown in FIG. 21, four transistors, that is, p-type MOS transistors Qp1-Qp4, are inserted in series between the input terminal of inverter (34) and power source line Vcc, and four transistors, that is, n-type MOS transistors Qn1-Qn4, are inserted in series between the input terminal of inverter (34) and ground line G. Consequently, in order to increase the speed of the CLA circuit, it is necessary to increase the size of these transistors, and as explained above, problems of increase in circuit size and power consumption occur. This is undesirable.

Carry look-ahead circuit and adder using same


An antennae device for reading electronic labels includes passive antennae arranged in the form of an array comprising L lines and C columns. The antennae are located in the array by co-ordinates (i, j), i ranging from 1 to L, j ranging from 1 to C. Each antenna (i, j) is controlled by two control switches, one controlling the antennae located on a line i, the other controlling the antennae located on a column j.

The invention relates to an antenna device for reading electronic labels and a system for reading electronic labels.
The field of the invention is that of radio frequency identification or RFID applied in particular to the reading of electronic labels (tags) apposed to objects grouped together in a small area.
An electronic label comprises a chip and an antenna, both buried in any support, generally of small size. The electronic label functions according to a contactless mode by means of an input-output interface consisting of the antenna. The antenna is of small size in relation to the dimensions of the electronic label.
The electronic label is read (or written to) by a reader which has a reading antenna for effecting an electromagnetic coupling with the electronic label.
So that the electromagnetic coupling is sufficient despite the small dimensions of the electronic label antenna, one solution consists of the reader being close to the electronic label.
These conditions are not always achievable in practice.
Another solution described in patent application WO 97/49076 consists, as shown schematically in FIG. 1, of using, between the antenna 10 of the reader 1 and the antenna 20 of the electronic label 2, an auxiliary passive antenna 30, sometimes referred to colloquially as a parasitic antenna, which begins to resonate at a given frequency under the action of a radio-frequency signal. When it is thus tuned to the given frequency, this auxiliary passive antenna 30 reinforces the electromagnetic coupling M1 between the reader 1 and the electronic label 2, by focusing the electromagnetic illumination of the antenna 10 of the reader 1 onto the antenna 20 of the electronic label 2. This reinforcement is obtained by electromagnetic coupling M2 between the antenna 10 of the reader and the auxiliary passive antenna 30 and by electromagnetic coupling M3 between the passive antenna 30 and the antenna 20 of the electronic label.
When it is wished to read numerous electronic labels grouped together in the same reading zone of the reader, it is possible to multiply the passive antennae as described above, but the passive antennae, then close to one another, will mutually interfere with each other.
It is also possible to use devices comprising as many active antennae as there are electronic labels. However, this multiplication of the active antennae is expensive since it results in a multiplication of the commands managing the transmission and reception radio frequencies of these active antennae.

Antennae device for reading electronic labels and system comprising same


A reflector is provided which surrounds a light source that has emissions in both the visible and radio frequency ranges. The electrically conductive reflecting coating of the reflector is connected to the system electrical ground so that the radio frequency component is effectively shielded by the reflector. The visible component of the spectrum emitted by the source escapes the reflector cavity after at least one reflection from the reflector surface and forms the required beam pattern.

1. Field of the Invention
This invention relates to a lighting device, specifically to a lamp reflector used with gas discharge light sources. More particularly, the invention is directed to a reflector design intended to suppress radio frequency electro-magnetic radiation from a light source.
2. Description of the Prior Art
Heretofore, EMI (electro-magnetic interference) from a source of EMR (electro-magnetic radiation) has been suppressed by shielding that source. Opaque materials such as metals, metal filled plastics or metallic coatings are used for EMI shielding of electronic components, ballasts, etc.
Discharge light sources emitting in the visible spectral range, generate a certain amount of EMR due to the nature of the processes in the source and its excitation. The level of that EMR could cause serious interference with electronic devices. One example of such a source is a neon light tube.
Opaque shielding materials are not applicable, since they would not pass the visible radiation.
To provide EMI shielding for sources of this nature, woven metal wire meshes with small cell size are widely used. Disadvantages of this approach include increased cost and performance limitations. Regarding increased costs, the addition of the wire mesh increases both component and assembly cost, affecting the overall cost of the finished product.
Regarding performance limitations, the size of the mesh cells applies limitation on the high frequency range that can be efficiently shielded, and reduces the light output due to absorption and scattering from the mesh.
Another technique of EMI shielding is the use of conductive coatings that are transparent in the visible range. ITO (Indium Tin Oxide) is widely used. Although this technique does not have the performance limitations mentioned above, the application of the coating is expensive, and the coating itself is highly toxic.

Lamp reflector for use with gaseous discharge lighting


Systems and methods for peer-based code quality analysis reporting are provided. In accordance with an embodiment, a system can include a peer-based code quality analysis tool, executing on a computer, which is configured to receive one or more source code files, and perform an analysis of the one or more source code files based on a plurality of rules. The peer-based code quality analysis tool can further compare results of the analysis to peer results data to determine a percentile based score, and create an interactive report which includes the results of the analysis and the percentile based score.

When companies acquire a new software application, they typically work with a vendor or systems integrator to incorporate that software application with the rest of the company's IT system. The quality of code implementations received from the systems integrator can vary widely, and so to ensure that they are receiving quality code, companies will often turn to code quality consultants to evaluate and recommend changes to their implementation. Code quality analysis can be performed manually or using a number of different analysis tools.
Code quality analysis tools provide a way for companies to analyze the quality of computer code they receive from their systems integrators. These tools can include static code quality analysis tools, which analyze code without executing it, and dynamic code quality analysis tools which analyze code at runtime. These tools can check for possible coding errors, inefficiencies, and other metrics based on a particular company's best practices or quality standards.
When a user runs one particular standard code quality analysis tool, the output provided is typically given in absolute values. For example, the tool will create a report that indicates there are 750 issues identified in the code. However, absolute values such as these are of limited use when evaluating the quality of a particular code implementation. In other words, absolute values alone, without context, do not indicate whether, for example, code having 750 issues is an example of good coding or bad coding.
Additionally, not all available code analysis quality tools provide the same quality checks. Therefore, to get a more comprehensive analysis of the quality of a given code project, multiple tools typically need to be separately utilized.

System and method for peer-based code quality analysis reporting


Rotor unit for a centrifuge for purifying flowing fluids, which rotor unit (12) comprises a plurality of disk elements (14) which are stacked concentrically one on another and provided with at least one centrally located fluid flow-through hole, where the disk elements (14) have lead-through openings by means of which the disk elements (14) are pushed onto a number of essentially axially elongate guide elements (16) distributed in the circumferential direction for guiding the disk elements in the circumferential direction and radially. The disk elements (14) are held together by a first and a second end element (18, 20) at the ends of the stack of disk elements. A central portion of at least some of the guide elements (16) are interconnected by means of a cross-stay construction (36) in order to prevent deflection of the rods owing to the centrifugal force during rotation of the rotor unit (12).

1. Technical Field
The present invention relates to a rotor unit for a centrifugal separator for purifying flowing fluids, which rotor unit comprises a plurality of disk elements which are stacked concentrically one on another and provided with at least one centrally located fluid flow-through hole, where the disk elements have lead-through openings by means of which the disk elements are pushed onto essentially axially elongate guide elements distributed in the circumferential direction for guiding the disk elements in the circumferential direction and radially, and where the disk elements are held together by a first and a second end element at the ends of the stack of disk elements, at least some of the guide elements comprising tie rods which are arranged so as to interact with the end elements in such a way that the end elements can be displaced toward one another while the disk elements are pressed together, in addition to which means are arranged so as to engage in a locking way with the tie rods for retaining the disk elements in a pressed-together state with a small gap-forming interspace between the disk elements, the rotor unit being arranged so as to be rotated in a surrounding housing by a motor.
2. Background Art
In centrifugal separators of the abovementioned kind with axially long rotor units, problems of deflection of the central portions of the guide and tie rods can occur during operation as a result of the centrifugal forces acting on them. The deflections are proportional to the length of the rods raised to the fourth power and inversely proportional to the radius raised to the second power. Doubling the length of the rods therefore requires a fourfold greater diameter, which makes the rods 16 times heavier per unit length. In order to increase the flow capacity through the rotor unit, it is usual to increase the diameter of the fluid flow-through hole of the disk elements as well. By virtue of this, the rods have to be moved outward, which means that the centrifugal force on the rods, and thus the deflection problem, increases.


The present invention relates to a nectarine tree, Prunus persica, and more particularly to a new and distinct variety broadly characterized by a large size, vigorous, hardy, self-fertile, productive and regular bearing tree. The fruit matures under the ecological conditions described approximately the last week in May, with first picking on May 26, 1997. The fruit is uniformly medium in size, subacidic and very good in flavor, clingstone in type, firm in texture, and nearly full red in skin color. The variety was developed as an open pollinated seedling of an unnamed white flesh nectarine seedling.

In a continuing effort to improve the quality of shipping fruits, we, the inventors, typically hybridize a large number of nectarine, peach, plum, apricot, and cherry seedlings each year. We also grow a reasonable number of open pollinated seeds of each of these species. The present invention relates to a new and distinct variety of nectarine tree, which has been denominated varietally as `Kay Sweet`. The present variety was selected from a group of open pollinated seedlings resulting from a mixed collection of seeds grown in 1992 from various unnamed white flesh nectarine trees located in a cultivated area of our experimental orchard at Bradford Farms near Le Grand, Calif. in Merced County (San Joaquin Valley). Subsequent to origination of the present variety of nectarine tree, we asexually reproduced it by budding and grafting, and such reproduction of plant and fruit characteristics were true to the original plant in all respects. The reproduction of the variety included the use of Nemaguard Rootstock, the standard of the stone fruit industry in central California, upon which the present variety was compatible and true to type.
The present variety is most similar to the `Diamond Bright` U.S. Plant Pat. No. 9,495) nectarine by producing nearly full red colored clingstone nectarines that are yellow flesh in texture and that ripen in late May and early June, but is very distinguished therefrom and an improvement thereon by blooming early instead of late, as compared to other nectarine trees, and by producing fruit that is subacidic in flavor instead of acidic, that is much sweeter in flavor, and that is somewhat conical instead of globose in shape.


A circuit arrangement for generating light pulses includes an electro-optical converter; a switching element; and a charge store. The electro-optical converter is connected to the charge store via the switching element. The closing of the switching element triggers a discharging process in the charge store and, in the process, generates an electrical pulse that is converted to a light pulse in the electro-optical converter. First and second impedance matching circuits are arranged, respectively, between the charge store and the switching element and between the switching element and the electro-optical converter.

The invention generally relates to a circuit arrangement that may be used to generate light pulses.
Circuit arrangements of this type are used in particular as transmitting units for optical sensors. These optical sensors can be embodied as distance sensors, which typically operate based on the light transit time method. For the distance measuring, light pulses are generated with predetermined timing with the aid of the circuit arrangement of the transmitting unit. The transit time of a light pulse to the object and back to the optical sensor is evaluated as a measure of the distance between an object and the optical sensor.
To achieve a highly precise distance measurement, it is necessary to generate sequences of very short light pulses, wherein the pulse duration of a light pulse typically is approximately one nanosecond. Accordingly, light pulses of this type are also required to have extremely short rise times below one nanosecond.
Circuit arrangements of this type for generating the aforementioned short light pulses are provided with laser diodes functioning as electro-optical converters. A charge store, typically a charge capacitor, is connected to this laser diode by way of a switching element, for example, a transistor.
The charge capacitor is discharged by closing the switching element and, in the process, a current pulse is generated, which is then converted in the laser diode to a light pulse.
With ideal components for such a circuit arrangement, the resulting time history for the current pulse would correspond to a discharge of an ideal RC (resistance-capacitance) element. This would mean an infinitely rapid rise time for the current pulse and an exponential decay of the current pulse.
However, during actual operations system-related deviations occur from the ideal time history of such current pulses, wherein these deviations in particular are caused by parasitic inductances in the components used.
A first deviation is that a finite rise time is obtained for the current pulse in place of an infinitely rapid rise time. Furthermore, the time history of the current pulse takes the form known for the discharge of an RLC (resistance-inductance-capacitance) element. Accordingly, post-oscillations occur during the decay of the current pulse. These post-oscillations comprise negative undershoots which are followed by positive overshoots. The negative undershoots polarize the laser diode in non-conducting direction and result in a Zener breakdown of the pn junction for the laser diode, thereby drastically reducing its operating life.
If the positive overshoots of the current pulse exceed a specific amplitude value, additional parasitic light pulses can thus be generated in the laser diode which follow the actual light pulse and result in distorting the distance measurements.

Circuit arrangement for generating light pulses


A zoom lens in which a lens group located in the vicinity of an aperture stop includes two subgroups and one of the subgroups is shifted so that an image is shifted. An increase in the size of lens groups including a shift lens group can be prevented. In addition, the sensitivity with respect to the axis tilt can be reduced while maintaining a sufficient distance between the two subgroups without increasing the size of the lens groups.

A method has been known in which a subject image is formed on an image sensing device using a photoelectric transducer, such as a charged coupled device (CCD) or a complementary metal-oxide semiconductor (CMOS) that serves as recording means of a camera, and the light intensity of the subject image is converted to an electrical output by the photoelectric transducer and is recorded.
In recent years, with the advancement of microfabrication techniques, central processing units (CPUs) have been increasing in processing speed and recording media have been increasing in memory density. Thus, a large volume of image data that could not be processed before can now be processed at a high speed. In addition, the density of light receiving elements has been increased with decreasing size of an image sensing element. The increased density of light receiving elements allows a camera to record an image of high spatial frequency. The decreased size of light receiving elements allows the size of the body of a camera to be decreased.
In addition, in order for users to use a camera in a wide range of an image capturing environment, the demand for a zoom lens is increasing and, in particular, the demand for a zoom lens with a high zoom ratio is increasing.
However, in an optical system having a high zoom ratio, the angle of field of view is decreased in a telephoto setting. Accordingly, even a slight hand vibration causes significant blurring of an image. Therefore, in video cameras having a high zoom ratio, electronic image stabilization systems have been developed in which an image receiving area of the light receiving element is shifted so that the image blurring caused by hand vibration is reduced.
In addition, image stabilization optical systems have been developed in which some of the lens groups of a lens system are shifted in a direction substantially perpendicular to the optical axis so that degradation of the optical performance caused by a shift in the image position is reduced.
These image stabilization optical systems include, for example, a detection subsystem for detecting image blurring caused by hand vibration occurring, for example, when a shutter is released, a control subsystem for providing an amount of correction for moving a lens position on the basis of a signal output from the detection subsystem, and a drive subsystem for moving a predetermined lens on the basis of the output from the control subsystem. Thus, these image stabilization optical systems can function as optical image stabilization systems.
These optical image stabilization systems can shift the image by the drive subsystem shifting the lens. Accordingly, the optical image stabilization systems can correct the image blurring due to shaking of the camera by shifting the lens using the drive subsystem.
For example, Japanese Unexamined Patent Application Publication Nos. 2002-244037, 2003-228001, and 2003-295057 describe such image stabilization optical systems.
A zoom lens described in Japanese Unexamined Patent Application Publication No. 2002-244037 includes a third lens group disposed on the image side of an aperture stop. The third lens group includes a negative subgroup and a positive subgroup. By moving the positive subgroup, the image is shifted.
A zoom lens described in Japanese Unexamined Patent Application Publication No. 2003-228001 includes a third lens group disposed on the image side of an aperture stop. The third lens group includes a positive subgroup and a negative subgroup. By moving the positive subgroup, the image is shifted.
A zoom lens described in Japanese Unexamined Patent Application Publication No. 2003-295057 includes a third lens group. By moving the entire third lens group, the image is shifted.