An apparatus for intermittently feeding a movie film on a frame by frame basis to a film processing unit for processing thereat by inserting projections into openings formed on both sides of the movie film at predetermined pitches and driving the same by use of a driving device. The film processing apparatus may include a guiding device for guiding the film along a path which passes nearby the film processing unit so as to enable the film processing unit to capture an image from the film and to perform processing of the same. The film processing apparatus may further include a device for exerting pressure on the film by moving the guiding device so that a portion of the film which passes nearby the film processing unit is held in tension, and a restraining device for restraining the guiding means from moving.

The present invention relates to a film processing apparatus, which may be utilized with a telecine apparatus for generating television signals from a movie film, a movie projector, and so forth, and, more particularly, to such apparatus which detects positioning errors of a running movie film and corrects the position of the film in accordance therewith, and provides a film path such that the film is protected from damage and enables high quality film processing.
Film processing apparatus may utilize a film feeding system (such as a continuous film feeding system and an intermittent film feeding system) depending on the type of apparatus. For example, a telecine apparatus generally uses a continuous film feeding system, and movie projectors which project pictures of a lighted movie film directly on a screen frame by frame use an intermittent film feeding system.
The continuous film feeding system uses a capstan for feeding a movie film at a constant rate. A telecine apparatus using such system lights the movie film with a light in a repeating one-dimensional vertical scanning arrangement in the film feeding direction. Consequently, the movie film is picked up frame by frame in such cluster scanning order and supplied to light receiving elements so as to generate television signals from the movie film.
On the other hand, the intermittent film feeding system uses rectangular openings called perforations formed on both sides of the film for feeding the movie film frame by frame intermittently. For movie projectors using this system, a cam mechanism may be used to insert pins called registration pins into the perforations of the film and to drive the same so as to feed the film intermittently. Furthermore, synchronized with this intermittent feeding of the film, a light is projected intermittently on the film from a light source and the transmitted light from the film is projected on a screen.
The continuous film feeding system has an advantage in that a relatively small load is applied to the film because there is no repetition of feeding and stopping the film. However, it has a disadvantage in that the lighting may not be properly synchronized with the feeding of the film. Thus, the continuous film feeding system may cause jitters in the longitudinal direction of the film and flickering which may result in shifting or distortion of pictures. Furthermore, for a telecine apparatus using a so-called flying spot scanner for scanning pictures by projecting a spot-like light on the film, the accuracy may vary and the life may be shortened depending on the operation hours, temperatures, and other conditions of the apparatus. As a result, troublesome and costly periodical maintenance and inspection are needed for such apparatus.
An intermittent film feeding system may simplify the configuration of the optical system and the film feeding system, but may require laborious adjustment to correct the positioning of the registration pins so as to engage the perforations of the film. Unless registration pins are positioned correctly, the film may be damaged by the registration pins. Further, such apparatus may produce large and bothersome mechanical sounds.
The above intermittent film feeding system also has a problem in that pictures projected on a screen may vibrate and shift each time a frame is fed, or may gradually go up/down from an initial position (hereafter, displacement of a picture caused as a result of processing in the apparatus is referred to as picture shift). Such problem may not be prevented completely. As is to be appreciated, picture shift deteriorates the quality of pictures projected on a screen by a movie projector, which is typically unacceptable to an audience.
In a telecine apparatus, this picture shift is converted to video signals which cause still pictures to seem as if they are vibrating which, in turn, may causing the frequency to become high when such video signals are compressed and causing an unnecessary increase in the amount of data. Furthermore, when digitizing pictures, the desired effect cannot be obtained if the object to be edited, which is expected to be at a certain same position, vibrates.
Therefore, in a film processing apparatus, it is desirable that the film guided by a guiding unit is positioned correctly. A position detector has been proposed for detecting whether or not the object film is positioned correctly. In the position detector, a plurality of electrodes are provided at the edge of the film and a conductor facing these electrodes is provided across the film. A condenser is formed with these electrodes and the conductor may be used as polar plates spaced with the film thickness. The capacitance of the condenser, which varies according to change in the film position, is used for detecting the film position on the basis of the amount of the capacitance variation.
However, a movie film often expands and contracts depending on environmental conditions like temperature, humidity, and so forth. These conditions may cause the positioning accuracy to be lowered.
Furthermore, perforations are apt to deform as the film is used for a long time. Additionally, foreign objects may also stick on the film surface. Even if a plurality of electrodes are arranged so that perforations cross between these electrodes to detect film positioning errors according to the capacitance formed between these electrodes, the above deformation and stuck foreign objects of the film may locally change the thickness of the film which may cause the film positioning accuracy to be significantly lowered.
A movie film has a dielectric constant and a thickness which may be dependent upon the film material and, as such, may be different from that of other films. Since the relation between film positioning error and capacitance changes due to such film characteristics, correct positioning error detection may not be obtained.


A stroller is provided having a stroller frame supporting a stroller seat. The stroller frame includes a linkage that facilitates collapsing or folding of the stroller frame from an in-use configuration to a folded or collapsed configuration, and unfolding of the stroller frame from the folded or collapsed configuration to the in-use configuration. The linkage also facilitates adjustment of the stroller seat height between at least two vertically offset positions.

1. Field of the Disclosure
The present disclosure is generally directed to strollers, and more particularly to a stroller with a frame structure that permits seat height adjustment and can be moved between an in-use configuration and a collapsed or folded configuration.
2. Description of Related Art
Well-designed strollers should be sturdy and balanced, and should provide the child passenger with safe and comfortable transport. Throughout the development of strollers, an effort has been made to include features that render the stroller versatile and convenient. Efforts have been made to provide these features while achieving a simple design, yet maintaining the stroller rugged and reliable.
A conventional stroller has a plurality of wheels supporting a stroller frame that supports one or more stroller seats. Some conventional stroller frames can be moved between an in-use position and a collapsed or folded configuration for easy, space-minimizing storage. Some conventional stroller seats can be articulated to a horizontal position so that an infant can lie in a prone position while riding in the stroller. Unfortunately, the seats have a fixed height, and define a distance to the caregiver that requires the caregiver to bend substantially to reach the infant, if needed.
What is therefore needed is a stroller having a seat supported by the stroller frame that is height-adjustable and capable of articulating between a vertical and a horizontal orientation. It would further be desirable that such a stroller be configured to move between a folded, or collapsed, storage configuration and an unfolded, or open, in-use configuration.


Embodiments of the invention relate to improvements to the support vector machine (SVM) classification model. When text data is significantly unbalanced (i.e., positive and negative labeled data are in disproportion), the classification quality of standard SVM deteriorates. Embodiments of the invention are directed to a weighted proximal SVM (WPSVM) model that achieves substantially the same accuracy as the traditional SVM model while requiring significantly less computational time. A weighted proximal SVM (WPSVM) model in accordance with embodiments of the invention may include a weight for each training error and a method for estimating the weights, which automatically solves the unbalanced data problem. And, instead of solving the optimization problem via the KKT (Karush-Kuhn-Tucker) conditions and the Sherman-Morrison-Woodbury formula, embodiments of the invention use an iterative algorithm to solve an unconstrained optimization problem, which makes WPSVM suitable for classifying relatively high dimensional data.

Automatic text classification involves first using some labeled documents to train a classifier and then using the classifier to predict the labels of unlabeled documents. Various methods have been proposed for performing automatic text classification. For example, SVM (Support Vector Machine), which is based on the statistical learning theory as discussed in Vapnik, V. N., Statistical Learning Theory. John Wiley & Sons, 1998, has been shown to be a good method for text classification problems as discussed in Lewis, D. D., Applying support vector machines to the TREC-2001 batch filtering and routing tasks, in the Tenth Text Retrieval Conference (TREC 2001), pages 286-292, Gaithersburg, Md. 20899-0001, 2002, National Institute of Standards and Technology; and Lewis, D. D., Yang, Y. Rose, T. and Li, F., RCV1: A New Benchmark Collection for Text Categorization Research, Journal of Machine Learning Research, 5:361-397, 2004. Research has been done to make SVM practical to classify relatively large-scale datasets as discussed in Joachims, T., Making Large-Scale SVM Learning Practical, Advances in Kernel Methods—Support Vector Learning, 1999; and Platt, J., Fast Training of Support Vector Machines using Sequential Minimal Optimization, Advances in Kernel Methods—Support Vector Learning, 1998.

Text classification by weighted proximal support vector machine based on positive and negative sample sizes and weights


The invention provides isolated BTL-II proteins, nucleic acids, antibodies, antagonists, and agonists and methods of making and using the same. Diagnostic, screening, and therapeutic methods using the compositions of the invention are provided. For example, the compositions of the invention can be used for diagnosis and treatment of inflammatory bowel diseases and for enhancing a mucosal immune response to an antigen.

Modulation of an immune or inflammatory response can be a valuable tool in controlling various kinds of diseases including autoimmune diseases, diseases characterized by abnormal inflammation and/or immune response, and infections. In treating diseases characterized by abnormal inflammation and/or immune responses, such as inflammatory bowel diseases and autoimmune or inflammatory diseases, down-modulation of an immune response is desirable. In other situations, for example when vaccinating a patient to impart immunity to an infectious disease, stimulation of an immune response is desirable. In the vaccine setting, adjuvants that can heighten an immune response to a coadministered antigen can be valuable in providing long term protection against disease. Particularly lacking in the art are adjuvants capable of stimulating a mucosal immune response. A mucosal immune response, as opposed to a systemic immune response, is valuable because it can attack an infection at a very common point of entry, that is, at a mucosal surface. The present invention addresses these needs in the art by providing therapeutic agents to diagnose and treat diseases characterized by inappropriate and/or abnormal inflammation and/or immune responses and therapeutic agents that can act as adjuvants to stimulate an immune response, particularly a mucosal immune response.


An optical sensor system for use in a currency validator is described. The system includes a controller, a plurality of light transmitters, a plurality of light receivers and a variable gain amplifier circuit connected to the receivers and to the microcontroller. The microcontroller controls the gain of the variable gain amplifier circuit. The variable gain amplifier circuit includes dual transconductance amplifiers connected together in such a manner to compensate for leakage current over a wide range of temperatures.

1. Technical Field
The present invention pertains to a device and technique for providing a stable optical sensor system. In particular, the invention concerns a variable gain amplifier circuit for controlling leakage current in an optical sensor system of a bill validator, and a method for obtaining light measurements.
2. Background Information
Bill validators used in vending machines and the like typically utilize optical, magnetic and other sensors to obtain measurements from an inserted bill to determine authenticity and denomination. Typically, the bill is transported past a plurality of photosensors, typically made up of light-emitting diodes (LEDs) and phototransistors, and a plurality of signals are generated corresponding to measurements taken from different areas of the bill. The LED drive signals are typically multiplexed between two or more LEDs to emit light at a number of wavelengths in a short period of time to ensure high security against fraud. The signals are then processed to validate and authenticate the bill.
Factors which may adversely affect the bill measurements include the following: the output power of an LED can degrade on the order of fifty percent with aging, inserted bills are of differing quality, and bill path cleanliness may vary. Further, some bill validator applications require undiminished performance under harsh outdoor conditions such as extreme cold or heat, and such temperature changes can cause wildly varying gain characteristics in LED-receiver pairs resulting in erroneous sensor readings. In addition, there are normal production variations in LED optical power output and receiver sensitivity, which can lead to units having varying current and voltage requirements in order to operate effectively. In order to compensate for such phenomena, optical sensor measurements were taken over a large dynamic range. However, a gain adjustment range for the amplifier circuitry of ten to one was typically used, which proved to be marginally adequate only if tightly specified and sorted optical components were utilized in the bill validator. Since performance of a bill validator must be acceptable over a wide temperature range, and LED/receiver pairs are subject to variations in performance characteristics, a system having an adjustable gain is required to ensure a robust bill validator sensor system.

Optical sensor system for a bill validator


The disclosure provides chemical compounds useful as activators of PKR. PKR activating compounds are useful in the treatment of disease and disorders associated with modulation of PKR and/or PKM2, such as pyruvate kinase deficiency (PKD).

Pyruvate Kinase (PK) converts phosphoenolpyruvate (PEP) and adenosine diphosphate (ADP) to pyruvate and adenosine triphosphate (ATP), respectively, which is the final step in glycolysis. In humans, four PK isoforms are expressed by two structural genes. The PKLR gene encodes PKR and PKL, tissue specific isoforms expressed in erythroid cells and liver cells, respectively. The PKM gene codes for isoforms PKM1, expressed in brain and skeletal muscle, and PKM2 (M2-type pyruvate kinase), expressed in fetal and most adult tissues except erythroid cells.
Mutations in the PKLR gene can lead to pyruvate kinase deficiency (PKD), an autosomal recessive disorder, which is the most frequent enzymatic defect of the glycolytic pathway in erythrocytes. Over 200 different mutations have been identified on the structural PKLR gene. Generally, most PKD patients are heterozygous with two different mutant alleles, but homozygous mutations have also been described. Clinical symptoms of PKD vary considerably from mild to severe anemia. Mutations can reduce PK enzymatic activity or decrease PK protein stability. Pathological manifestations are usually observed when enzyme activity falls below 25% normal PK activity, and severe disease has been associated with a high degree of reticulocytosis. Although the global incidence of PKD is unknown, it has been estimated at 51 cases per million in North America. Heterogenous genetic mutations in PKR can lead to dysregulation of its catalytic activity. These mutations represent wide range genetic lesions that include deletional and transcriptional or translational abnormalities, including missense mutation in the coding region that can affect conserved residues within domains that are structurally important for optimal catalytic function of PKR.
Currently, there is no definitive treatment for severe PKD. Although splenectomy can be clinically useful in patients with severe disease, in some cases, allogeneic hematopoietic transplantation is required. In these patients, hematopoietic stem cell (HSC) gene therapy might be a good and more effective treatment. Gene therapy strategies for PKD have been addressed in animal models demonstrating that introduction of the correct version of the human PKLR gene into hematopoietic stem cells using retroviral vectors alleviates the disease. Although bone marrow transplant (BMT) or gene therapy strategies would be definitive treatments of the disease, they have yet to be realized clinically, and important adverse effects are associated with both approaches.
There remains a need for strategies to improve the treatment of diseases related to PKR, such as PKD, including the discovery and development of PKR activating small molecules. PKR exists in both a dimeric and tetrameric state, but functions most efficiently as a tetramer. Small molecules have been shown to be capable of shifting the equilibrium of PKR to the tetrameric (most active) form, providing a mechanistic rationale for their use as therapy for PKD-associated hemolytic anemia. Thus, there is a need for PKR activating compounds, useful for treating diseases and disorders associated with modulation of PKR and/or PKM2.

Activating pyruvate kinase R and mutants thereof


Image forming system including at least one image forming apparatus for forming images on sheets on the basis of image data. At least one temporary containing apparatus is disposed downstream of the image forming apparatus for temporarily containing therein the sheets on which the images have been formed. A separating and conveying apparatus separates and conveys the sheets contained in the temporary containing apparatus one by one. A sheet post-processing apparatus conveys the sheets conveyed by the separating and conveying apparatus and the sheets on which the images have been formed by the image forming apparatus and which bypass the temporary containing apparatus in an arbitrary order, in order to effect a set post-process on the conveyed sheets.

1. Field of the Invention
This invention relates to an image forming system provided with at least one image forming apparatus, an image forming method therefor and an image forming apparatus.
2. Related Background Art
Generally, much waste occurs when outputting a document including different kinds of data patterns such as color data, text data or image data by an image forming apparatus. For example, in a color image forming apparatus, the printing speed is generally low, and when a single black image is to be outputted, it is better from the viewpoint of efficiency to use a monochrome image forming apparatus than to use a color image forming apparatus.
Therefore, as shown, for example, in Japanese Examined Patent Publication No. H04-68153, in order to be capable of coping with various data forms, there has been proposed a technique of paging and sorting the output documents of a color image forming apparatus and the output documents of a monochromatic image forming apparatus to thereby obtain a form of document.
In recent years, however, due to improvements in and advance of software and hardware, the image editing capability on a computer has become diverse and along therewith, image forming patterns are becoming diversified and advanced highly. As a result, as a document, one having an image comprising a different pattern on each page is increasing.
Also, a document having pages of different sizes such as A3 size and A4 size mixedly present therein, like large-sized paper Z-folded so as to match with small-sized paper is increasing.
In such a background, when originals or document data are to be copied or printed from different print patterns or different sizes of respective pages in a document, it is strongly desired to efficiently effect copying or printing in the order of pages.

Image forming system, image forming method and image forming apparatus


A method and a tool are provided for producing structural parts from sheet metal which have a vault-structured stiffening zone and adjacent, flat connection zones. The starting point for producing these structural parts is vault-structured blanks which are smoothed in the region of the connection zones in the course of the forming, whereas the vault structure is retained unchanged in the region of the stiffening zone. These structural parts are produced by an embossing tool which has a die and a two-piece punch including of a fixing punch and a forming punch. In the process, the blank is first of all fixed relative to the fixing punch in the region of the vault-structured stiffening zone by a fixing element which is in a leading position with respect to the die. The connection zones are then shaped between the punch and the forming punch.

The invention relates to a method of producing a structural part from sheet metal, in particular a body sheet, and to an embossing tool for producing such a structural part.
Many structural parts in automobile body construction must fulfill stringent requirements with regard to the inherent stability and bending stiffness. Such structural parts are as a rule produced from sheet and are normally provided with beads for increasing the inherent stability and bending stiffness. However, the beading of the sheets leads to a highly directional stiffness increase: thus, although sheet-metal strips having beads arranged in the longitudinal direction are certainly flexurally rigid in the longitudinal direction, they have only low torsional rigidity and are flexible in the transverse direction. Uniform homogeneous stiffening of the sheets therefore cannot be ensured by embossing such beads.
Stiffening with substantially less directional dependence can be achieved if the sheets—instead of being provided with the beading—are provided with "vault structuring" by bulge forming; this method is described, for example, in DE 44 37 986 A1. In contrast to the conventional forming processes (such as deep drawing for example), in which plasticizing of the sheet takes place during the forming, the sheet is merely folded locally during the vault structuring; this is associated with only a small surface enlargement of the material. The bulge forming is effected in a continuous process, so that entire sheets of material (or band-like regions on them) are provided with the vault structure. To produce body structural parts having increased stiffness, blanks are cut out of these sheets of material, and the desired structural parts are then produced from these blanks by further process steps. Thus, for example, DE 199 42 383 A1 describes a motor vehicle floor which is produced by deep drawing a vault-structured sheet.
However, difficulties occur if body parts of vault-structured sheet are to be connected to other structural parts using conventional joining processes (spot welding, screwed connections, etc.). This is because, on account of the vault structuring of the structural part, it cannot be ensured that the members to be joined meet one another in a planar manner in the connection zones in which the vault-structured structural part is to be joined to other structural parts. In order to be able to ensure controlled, high-strength joining of such structural parts by means of a welding process—or a positive-locking screwed connection—the vault structuring of the structural parts must be removed to the greatest possible extent in the connection zones so that the structural parts in these connection zones can bear in a planar manner on (flat) connecting regions of other adjacent subassemblies.
The object of the invention is to propose a method by means of which vault structures can be smoothed locally. It is also the object of the invention to provide a tool which permits simple and controlled smoothing of a locally limited connection zone on a vault-structured structural part.
This object is achieved according to providing a method of producing a structural part from sheet metal, in particular a body sheet having a stiffening zone in which the structural part is provided with vault structuring which increases the stiffness, and having a connecting zone which is more or less free of vault structures, a vault-structured cut-to-size sheet being used as a blank for producing the structural part, said method comprising the following method steps: placing the blank into an embossing tool having a punch and a die; lowering the die with the blank being fixed relative to the punch in a region of the vault-structured stiffening zone by a fixing element which is in a leading position with respect to the die; and further lowering of the die to shape, the connection zone between the punch and die.
This object is also achieved according to the invention by providing an embossing tool for producing a structural part having a vault-structured stiffening zone and a connection zone largely free of vault structures, starting from a blank of vault-structured sheet, the embossing tool having a punch and a die, wherein the die has a leading fixing element for fixing the blank in the tool and also has a basic die body, wherein the punch of the embossing tool is of multi-piece design and comprises a fixing punch interacting with the fixing element of the die, and a forming punch displaceable with respect to the fixing punch, and wherein the basic die body and the forming punch are provided with interacting smoothing regions for embossing the connection zone on the structural part.
Accordingly, in order to produce the desired structural part, a structural-part blank, i.e. a suitably shaped vault-structured sheet-metal section, is formed in an embossing tool comprising a punch and a die. The embossing tool is designed in such a way that the vault structuring originally present on the structural-part blank is not affected in the region of the stiffening zones, whereas the vault structure is smoothed in the connection zones. In order to achieve this, the punch of the embossing tool is of multi-piece design: the punch comprises a fixing punch which is arranged in a region of the punch corresponding to the stiffening zone of the structural part and whose function—in interaction with the leading fixing element on the die—is to fix the blank in the tool without deforming it. Furthermore, the punch comprises a forming punch which is displaceable relative to the fixing punch and is arranged in the region of the punch corresponding to the connection zone of the structural part and whose function—in interaction with a part of the die facing this forming region—is to smooth the sheet locally in the connection zone.
To produce the structural part, first of all, the fixing punch of the embossing tool is raised, and the structural-part blank is put onto the fixing punch in the desired orientation; by lowering the die of the embossing tool, the blank is then clamped in place relative to the punch in the region of the stiffening zone by the leading fixing element of the die; the position of the blank in the tool is therefore fixed. The die is then lowered further, in the course of which the connection zones are formed between the forming regions, corresponding to one another, on punch and die.
Smoothed connection zones in which the vault structure is mostly removed can therefore be produced on the vault-structured blank by means of the embossing tool according to the invention. In these connection zones, the structural parts can be connected to connection parts in following production steps with the aid of conventional joining processes—for example by spot welding or seam welding during the body-in-white stage or by screwed connections during assembly. In the process, the vault structure of the stiffening zones is retained without being deformed. Therefore structural parts which are provided in selected stiffening zones with a (more or less directional) vault structure, but have a more or less smooth surface structure in adjacent connection zones, can be reproduced by means of the embossing tool according to the invention.
In an advantageous configuration of the invention, the end face of the fixing punch is provided with a surface contour which corresponds to the vault structuring of the blank. This has the advantage of helping to orient and position the blank in the tool in a defined manner when the blank is put into the embossing tool, this orientation and position corresponding to the surface structure of the fixing punch. In this way, in particular, the vault structure of the sheet can be oriented in a highly precise manner relative to the forming regions of the embossing tool, so that the smoothed connection zone produced in the course of the embossing operation is positioned in a highly precise manner relative to the vault structure of the stiffening zone.
The fixing element, interacting with the fixing punch, of the die is preferably made of an elastic material, in particular rubber. When the fixing element guided in the die is lowered onto the vault-structured surface of the blank to be fixed, the end face of the fixing punch elastically adapts itself to the vault structure; during the further lowering of the die, the fixing element is compressed, as a result of which the fixing force, exerted by the fixing element, on the blank is increased. The blank is therefore clamped in place with high force (and thus in a nonslip manner) between fixing punch and fixing element during the smoothing of the connection zone.
Alternatively, the fixing element may be designed as a spring-mounted slide, the end face of which is provided with a vault structure (complementary to the end face of the fixing punch). In this case, the blank, in the region of the stiffening zone, is clamped in place in a positive-locking manner between fixing element and fixing punch.
In the course of the smoothing of the connection zone, the surface enlargement which has been produced during the vault structuring in the course of the production of the blank must be reduced in a specific manner. In order to avoid fold formation and/or the generation of radiating patterns on the structural part in the process, it is expedient to provide "consumers", which ensure a defined flow of the excess material. Beads which are provided in the connection zone—preferably close to the transition to the stiffening zone—serve as such "consumers". To shape these beads, bead regions are provided in the forming regions of the embossing tool.
The invention is explained in more detail below with reference to an exemplary embodiment shown in the drawings.

Method and embossing die for producing a body structural part from a vault-structured sheet metal


A wearing article including a region in which the wearer's skin is not seen-through other than the existence region of the absorbent structure even when an area of the absorbent structure is relatively small so that the existence region of the absorbent structure may be un noticeable from the outside. A region of the absorbent structure of a diaper overlapping with the first waist region has a dimension in the transverse direction corresponding to 20 to 30% of a dimension in the transverse direction of the first waist region, the first waist region is disposed with a hardly see-through panel overlapping with the absorbent structure and includes a first region in which the chassis, the absorbent structure and the hardly see-through panel are laminated, second regions adjacent on both outsides in the transverse direction of the first region, in which the chassis and the hardly see-through panel are laminated and third regions adjacent on both outsides in the transverse direction of the respective second regions and only the chassis is included; and a differential total luminous transmittance between the first region and the second regions is smaller than a differential total luminous transmittance between the second region and the third region.

Conventionally, disposable wearing articles are known having an absorbent structure attached to the skin-facing surface of a chassis. For example, Patent Literature 1 discloses a disposable wearing article including a chassis formed from a fibrous nonwoven fabric so as to define front and rear waist regions and a crotch region and an absorbent structure attached to a skin-contact surface of the chassis so as to extend across the crotch region into the front and rear waist regions. Total luminous transmittance of the fibrous nonwoven fabric forming the chassis is set relatively high so that a picture on film may be visually recognized even through the fibrous nonwoven fabric.


A static elimination device is proposed for eliminating static electricity on the surface of a large-size glass substrate. The static elimination device includes a rotation axis and an electrostatic neutralizer. The rotation axis is installed outside a cassette in which the glass substrate is installed. The electrostatic neutralizer is permanently connected to the rotation axis. The rotation axis is driven to rotate, causing the electrostatic neutralizer centered on the rotation axis to rotate back and forth at a specific angle. The static elimination device of the present invention features simple structure, low fuel consumption and high efficiency, low cost, and high efficiency in static elimination. Owing to these features, the static elimination device of the present invention could work very well for the glass substrate of an arbitrary size. A cassette including the static elimination device is also proposed.

1. Field of the Invention
The present invention relates to a static elimination technology, and more particularly, to a static elimination device. The present invention also relates to a cassette in which the static elimination device is installed.
2. Description of the Prior Art
A flat-panel device such as art LCD is an essential display device for an electrical product. During the manufacturing, process of a TFT-LCD (short for Thin Film Transistor-Liquid Crystal Display), static electricity is often produced on the surface of a glass substrate when the glass substrate is brought into contact or friction in different processes. Static electricity on the surface of the glass substrate absorbs particles, causing the particles to be attached to the surface of the glass substrate. As a result, the glass substrate is polluted; or even, an electrostatic discharge (ESD) event might occur. Static electricity also causes static charge accumulation. A huge sudden discharge would occur when electric charges are accumulated to a certain degree. A semiconductor element on the glass substrate would be damaged due to the sudden discharge. Moreover, static electricity might be produced when as cassette where the glass substrate is installed is carried or transported.
To settle the damage caused by static electricity, two methods for eliminating static electricity are used in the LCD panel industry. The first one method is that, devices are grounded and the relative humidity of the environment is adjusted so as to eject static electricity from the surface of the object. Or, ions are sprayed on the surface of the glass substrate using an electrostatic neutralizer for eliminating static electricity. The second one method is that, four to six rod-like electrostatic neutralizers installed on the four corners of the outside of the cassette so that every glass substrate layered in the cassette could obtain the sprayed ions from the nozzles of the electrostatic neutralizers. However, the above-mentioned methods have shortcomings:
1. The electrostatic neutralizers are vertically disposed on the four comers of the cassette. The legs of the electrostatic neutralizers may hinder the nozzles of the electrostatic neutralizers from effectively spraying ions on the surface of the glass substrate.
2. The glass substrate is layered inside the cassette. The glass substrate could only obtain scanty ions sprayed by the electrostatic neutralizers, let alone a large-size glass substrate. To effectively eliminate static electricity on the surface of the large-size glass substrate, a plurality of electrostatic neutralizers are used. However, the increasing electrostatic neutralizers are a burden. Production costs increase because of the periodical renewal of the increasing electrostatic neutralizers and the power consumption of the increasing electrostatic neutralizers.
3. The ions sprayed by the electrostatic neutralizers are obviously affected by the airflow inside the dust-free cavity. The airflow inside the dust-free cavity flows in a specific direction, and the specific direction is often contradictory to the path of the sprayed ions. The to contradiction causes the alternation of some paths of the sprayed ions, thereby impeding the electrostatic neutralizers to eliminate static electricity.

Static elimination device and a cassette

Shenzhen China Star Optoelectronics Technology Co., Ltd


A vehicle door latch has a selectively engaged security lock that prevents a vehicle door from being unlatched by an inside door handle. The security lock overrides the door lock when the inside door handle is operated with the security lock engaged so that the vehicle door latch may be unlocked from inside the vehicle easily when the security lock is engaged.

An automotive closure, such as a door for an automobile passenger compartment, is hinged to swing between open and closed positions and conventionally includes a door latch that is housed between inner and outer panels of the door. The door latch functions in a well-known manner to latch the door when it is closed and to lock the door in the closed position or to unlock and unlatch the door so that the door can be opened manually. The door latch is operated remotely from inside the passenger compartment by two distinct operators--a sill button or electric switch that controls the locking function and a handle that controls the latching function. The door latch is also operated remotely from the exterior of the automobile by a handle or push button that controls the latching function. A second distinct exterior operator, such as a key lock cylinder, may also be provided to control the locking function, particularly in the case of a front vehicle door. Each operator is accessible outside the door structure and extends into the door structure where it is operatively connected to the door latch mechanism by a cable actuator assembly or linkage system located inside the door structure.
U.S. Pat. No. 5,277,461 granted to Thomas A. Dzurko et al on Jan. 11, 1997 for a vehicle door latch, which is hereby incorporated in this patent specification by reference, discloses a typical door latch. The door latch disclosed in the Dzurko '461 patent includes an inside latch operating lever that is pivotally mounted on a flange of a metal face plate and that is connected by a suitable linkage for rotation by an inside door handle (not shown). See column 4, lines 10-18 of the Dzurko '461 patent. The door latch also includes an inside lock operating lever that is pivotally mounted on the flange of the metal face plate near the inside latch operating lever. The inside lock operating lever is operated by an inside sill button or lock slide. See column 5, lines 46-58 and column 6, lines 8-15 of the Dzurko '461 patent. The door latch disclosed in the Dzurko '461 patent is released from the passenger compartment in two stages. First, the inside lock operating lever is rotated counterclockwise by an inside sill button or lock slide to unlock the door latch. Then, the inside latch operating lever 56 is rotated clockwise by an inside door handle to unlatch the door latch so that the vehicle door may be opened manually.
Door latches of the type disclosed in the Dzurko '461 patent have been used successfully by General Motors Corporation for many years.
Another vehicle door latch of General Motors Corporation is disclosed in U.S. Pat. No. 5,308,128 granted to Alfred L. Portelli and Rita M. Paulik on May 3, 1994 for a vehicle door latch that operates in a similar manner. The vehicle door latch disclosed in this patent, however, has a selectively activated security lock that prevents the door latch from being unlatched by an inside door handle or other inside operator. While this system is useful for many purposes, there are instances where it is desirable to allow passengers to unlock the door latch from inside the vehicle even though these passengers are not able to unlatch the door from inside the vehicle. While the vehicle door latch can often be unlocked by a sill button or an electric switch in the case of electric door locks, sill buttons are often difficult to operate by small children and an electric door lock may not be operable in case of a dead battery.


An apparatus for breaking in new pad conditioning disks for use in a chemical mechanical polishing (CMP) system that polishes a semiconductor wafer by pressing the semiconductor wafer against a moving polishing pad. The apparatus comprises a break-in head that is removably attached to a drive shaft to which a polishing head that holds the semiconductor wafer is normally attached. The break-in head holds multiple pad conditioning disks and presses the plurality of pad conditioning disks against the moving polishing pad. The break-in head comprises a drive mechanism for rotating the multiple pad conditioning disks. The drive mechanism is coupled to the drive shaft and rotates the multiple pad conditioning disks by translating a rotating motion of the drive shaft into rotating motions of the multiple pad conditioning disks.

Chemical mechanical polishing (CMP), also called chemical mechanical planarization, is a well-known process for removing oxide and other deposits from the surface of a wafer. CMP systems are frequently used during the processing of silicon semiconductor wafers. CMP systems are made by a number of vendors, including Applied Materials, Inc., of Santa Clara, Calif. Many conventional CMP systems polish semiconductor wafers by abrading the surface of the wafer with a silica-based slurry.
FIG. 1 illustrates selected portions of chemical mechanical polishing (CMP) system 100 according to an exemplary embodiment of the prior art. CMP system 100 comprises support platform 101, platen 105, polishing pad 110, pad conditioning disk 115, spindle 120, disk actuator 125, motor 130, and drive shaft 135. CMP system 100 further comprises motor 130, drive shaft 145, polishing head 150, motor 160, drive shaft 165, and slurry dispenser 170. Applied Materials (AMAT) manufactures the AMAT Mirra™ CMP system, which houses three CMP systems similar to CMP system 100 in an enclosure. It is noted that the components of CMP system 100 depicted in FIG. 1 are not drawn to scale. Rather, the sizes and relative positions of the components of CMP system 100 are selected for easy reference and explanation.
The operation of CMP system 100 is widely understood. Drive motor 140 and drive shaft 145 rotate platen 105 and polishing pad 110. Slurry dispenser 170 dispenses onto polishing pad 110 a silica-based slurry made from de-ionized water mixed with SiO2 (or KOH). Rotation of pad 110 carries the slurry underneath polishing head 150. A silicon wafer (not shown) is attached to the bottom surface of polishing head 150, which may be, for example, a Titan™ polishing head from Advanced Material, Inc. The wafer may be held in place on the bottom surface of polishing head 150 by vacuum pressure created by a membrane.
Motor 160 and drive shaft 165 rotate polishing head 150 and the attached wafer and press polishing head 150 and attached wafer downward onto polishing pad 110. This downward pressure forces the exposed surface of the attached silicon wafer into firm contact with the moving slurry dispensed on rotating polishing pad 110. The movement and pressure of the slurry abrades the exposed surface of the silicon wafer. The abrasion removes silicon oxide or other materials that are deposited on the exposed surface of the silicon wafer attached to the bottom of polishing head 150.
The efficient operation of CMP system 100 requires that the surface of polishing pad 110 be continually conditioned by pad conditioning disk 115. Polishing pad 110 may be made of polyurethane, for example. The surface of polishing pad 110 is covered by tiny grooves (e.g., depth=0.03 inch) that capture slurry particles. Pad conditioning maintains an acceptable oxide removal rate and stable performance. Pad conditioning helps maintain optimal pad roughness and porosity, thereby ensuring the even transport of slurry to the wafer surface. Without conditioning by pad conditioning disk 115, the surface of polishing pad 110 glazes and oxide removal rates decline.
The bottom surface of disk 115 is coated by an abrasive layer, such as a layer of nickel in which fine diamonds are embedded. Diamond pad conditioning disks are the most widely used method of pad conditioning in wafer fabrication facilities today. Pad conditioning disk 115 refreshes (or wears) the surface of polishing pad 110 during CMP processing to thereby maintain a uniform surface on polishing pad 110.
Disk actuator 125, motor 130 and drive shaft 135 drive pad conditioning disk 115, which is rigidly attached to spindle 120. Disk actuator 125 and drive shaft 135 contain the necessary gearing and other drive mechanisms to rotate spindle 120, thereby rotating disk 115. Disk actuator 125 and drive shaft 135 also contain the necessary drive mechanisms to sweep rotating disk 115 back and forth across the surface of rotating polishing pad 110.
The performance of pad conditioning disk 115 has a significant impact on the cost of operating CMP system 100. Aggressive use of pad conditioning disk 115 gives good process performance, but rapidly wears out polishing pad 110, thereby reducing pad life and increasing cost. A less aggressive use of pad conditioning disk 115 may not provide enough conditioning to polishing pad 110, resulting in unstable process performance.
Disk flatness is an important aspect of pad conditioning disk 115, since uniform wear across polishing pad 110 increases pad life and process stability. To ensure disk flatness, a new pad conditioning disk 115 must be broken, in prior to use in an on-line CMP process. The process of breaking in a new disk 115 typically involves taking CMP system 100 off line, removing the wafer and polishing head 150, and attaching new disk 115 to spindle 120. Next, new disk 115 scours the surface of pad 110 for about 30 minutes, until the bottom surface of disk 115 is evenly worn.
At this point, broken-in disk 115 is removed, pad 110 is replaced with a new pad, polishing head 150 is re-attached, and CMP system 100 is re-qualified. The process of re-qualifying CMP system 100 may require another two hours. The AMAT Mirra™ CMP system, which houses three CMP systems similar to CMP system 100 in a single housing, may break in three pad conditioning disks 115 at a time. Nonetheless, the process of breaking-in pad conditioning disk 115 may take CMP system 100 off line for two and a half hours.
It is important to improve process performance by increasing productivity and reducing cost of ownership. However, taking CMP system 100 off line to break in new disks 115 makes achieving these goals more difficult. Reducing off-line time has the added benefit of minimizing the frequency of tool re-qualification, resulting in higher availability and more finished wafers per month.
Therefore, there is a need in the art for an improved chemical mechanical polishing (CMP) system that has reduced off-line time. In particular, there is a need for an improved system and method for breaking in pad conditioning disks that reduce the amount of time that a chemical mechanical polishing (CMP) system must be taken off line.

Apparatus and method for breaking in multiple pad conditioning disks for use in a chemical mechanical polishing system


A processor and associated memory device that includes a fetcher for fetching instructions stored in the memory device. Each instruction constitutes either a value generating instruction or a non-value generating instruction. The processor further including a decoder for decoding the instructions, an issue unit for routing decoded instructions to an execution unit. The processor further having a predictor being responsive to a first set of instructions, from among the value generating instructions, for predicting, with respect to each one instruction in said first set of instructions, a predicted value that is determined on the basis of a prediction criterion which includes: (i) a previous value generated by the instruction; and (ii) at a stride.

Current processors technology allows different execution units (pipes) to operate in parallel. As the number of gates on silicon chip increases, a major problem that processor architecture meets is the limited parallelism within the instruction stream. Such parallelism is limited because of data dependencies as well as because of control dependencies.
For a better understanding of the terms data dependency and control dependency consider, for example, the following exemplary computer program segment that performs a certain computation on non-overlapping arrays of variables:
______________________________________ loop: A[j + 1]: = A[j] + j B[j]: = 4*B[j] j: = j + 1 i: = 1 + j while (j! = 1000) go to loop k: = k + 1 ... ______________________________________
From the processor point of view, the program can be illustrated as a stream of instructions (Architectural instructions or micro machine instructions) that can be divided into three main categories: (1) arithmetic instructions that aims to modify values existing in the processor's storage areas, such as registers, (2) control instructions that aims to determine what instruction out of the program's area will be execute next and (3) load store instructions that aims to move data from and to the process's local memory area (such as registers) and the memory. The goal of ALL the modern processors is to perform as many operations as possible in parallel, while keeping the correctness of the execution; i.e., the user should not distinguish between a program running on such a parallel machine and the same program running on machine that performs the operation sequentially.
Modern processors analyze the streams of instructions the processor should execute and determine which operations the processor can perform in parallel. To this end, the processor needs to examine for each operation whether all of the inputs needs for the operation are available at that time. Input may not be available for different reasons such as the value has not be calculated (by another instruction) or the fetching process of the data into the processor's area have not been completed yet. All the operations that have been found to be ready can be executed in parallel (See Mike Johnson, Design of Superscalar Processor). The average number of operations the processor, or a system can execute in parallel is termed Instruction Level Parallelism--ILP. As for the above simple example, intuitively, the instruction B[j]:=4*B[j] albeit placed after the instruction A[j+1]:=A[j]+j in the source code, both instructions can be marked "ready" at the same time, since the outcome of the latter (i.e. modifying the value of certain cell in the array `A`) does not affect the former (i.e. modifying the value of certain cell in array `B`). Thus, the processor can execute them in parallel. In other words, the latter scenario illustrated the lack of data dependency.
Conversely, the processor must execute the instructions j:=j+1 and i:=1+j exactly in the order they appear (in respect to each other) since the value of j, as determined in the former instruction, affects the value of i in the latter instruction. Put differently, the latter scenario illustrates data dependency. As will be explained in greater detail below, data dependencies are divided into three main categories, i.e. output data dependency, anti data dependency and true data dependency (Superscalar Microprocessor Design, Mike Johnson, Book).
In order to take advantage of independent operations and in order to speed up the execution rate, current processor technology integrates the mechanisms to exploit parallelism within the multi-stage (pipeline) architecture, as illustrated e.g. in FIG. 1.
In the example of FIG. 1, several instructions are fetched in parallel into an instruction buffer (in the fetch stage), then they are decoded, the dependencies are explored and the instructions are placed in a buffer termed reorder buffer. The issue stage sends the instructions which are ready to the execution stage; i.e., their input data is available and they do not depend on outcome of other operation(s), and so, independent instructions can be executed in parallel. The outcome of the execution can update register(s), memory location(s), hardware flag(s), the program counter and/or operations on the reorder buffer to make instructions which are marked as stalled to be moved into ready to be executed state.
The amount of parallelism exists in the execution stream, depends on the size of the instruction window; i.e., the number of instructions that are classified by the system as ready to be executed. Control instruction and hardware complexity limits the size of the instruction window significantly. It was reported (Hennessy and Patterson: Computer architecture: a quantitative approach) that as many as 20% of the instruction the processor executes can be control instruction, bringing the average size of the instruction window available between control instructions to 4 instructions. It is clear that without enlarging the size of that window, the amount of parallelism the architecture can benefit from is very limited. Control instructions usually appears as different types of conditional or non-conditional branch instructions. (For simplicity, conditional or non-conditional branch instructions will also be referred to, in short, branch or control instructions). An example of conditional branch being: "while (j!=1000) go to loop". Conditional branch instruction includes, as a rule, a logical condition and a destination address. When the condition is met, the next instruction for execution resides in dostination. If, on the other hand, the condition is not met, the next instruction for execution follows the branch instruction (some architecture such as VAX.TM. introduced more sophisticated branch instructions that uses tables of addresses to control the instruction flow, but this instructions has the same nature from the perspective of the present invention.) When executing a sequential set of instructions that does not include branch instructions, the issue of control dependency is irrelevant since the address of the next instruction to be executed can be unequivocally resolved. In contrast, the next instruction for execution cannot be unequivocally predicted if branches are encountered, since at the prediction stage the processor has not resolved the logical condition and the target address calculation that is associated with the branch instruction and accordingly it is unclear whether jump occurs, (in which case the next address for execution resides at the destination address of the branch), or alternatively the condition is not met (in which case the next instruction to execution is the one that follows the conditional branch instruction).
Bearing this in mind, branches (control instructions) can significantly reduce the amount of parallelism the processor can utilize (J. Lee and A. J. Smith. Branch Prediction Strategies and Branch Target Buffer Design. IEEE Computer, January 1984, pp. 6-22. and T.-Y. Yeh and Y. N. Patt. Adaptive Training Branch Prediction. The 24.sup.th ACM/IEEE International Symposium and Workshop on Micro-architecture). When the branch instruction is evaluated in decode stage, the decode stage and the fetch stage cannot continue their operation until the branch conditions are resolved and the address of next instruction to be fetched and decoded is calculated.
This drawback is clearly illustrated in the specified exemplary computer program segment. Thus, encountering the "if" statement (i.e. conditional branch) hinders the possibility of keeping on revealing independencies among the instructions, in the manner specified, since it is not known at this stage (which, as recalled, precedes the actual execution) whether the next instruction is A[j+1]:=A[j]+j (i.e. the condition of the "if" clause has been met), or k:=k+1 (i.e. the condition of the jump has not been met). Of course, the condition will be resolved at run time, but relying on this misses the whole point of prediction in-advance (i.e. before actual execution) which instructions are independent, one with respect to the other, so as to route them, in due course, to separate execution units thereby accomplishing parallel processing.
To cope with the problem of conditional branches, various branch predictors were suggested; e.g., when the decoder hits a branch, it predicts the outcome and continue to decode the operands based on this assumption. The instructions that were decoded based on this prediction are marked as speculative. As soon as the branch can be resolved (calculate its condition and the target address), all the speculative instructions belonging to that decision are either validated (in case of successful prediction) or be discarded (in case of failure) from the system. This mechanism was found to be very effective and so is used by many of the existing processors (T. A. Diep and C. Nelson and J. P. Shen Performance Evaluation of the PowerPc 620 Micro architecture. The 22.sup.nd Annual Symposium on Computer architecture, 1995, pp 163-174. [Diep95]).
Branch predictors of the kind specified whilst increasing the level of parallelism (ILP) to a certain extent, are not always successful in their prediction in which case the instruction level parallelism (ILP) is, of course, detracted since all the speculative instructions that followed the mis-predicted branch instruction must be discarded.
The ILP accomplished by virtue of the branch predictors does not accommodate the ever increasing capacity of modern processors in terms of their capability to concurrently process instructions.
In this connection it should be noted that the trend in modern processors is to employ more and more execution units, which of course calls for enhancement of the ILP in order "to keep them all busy" and thereby expediting the processing time of the executed application. An example of this trend is manifested by the increase in number of execution units that is employed in the known PowerPC.RTM. 601 model (three units) compared to the succeeding generation PowerPC.RTM. 620 which already employs 6 execution units.
The necessity for increased parallelism further stems from the use of known pipelining techniques which affords overlapping of multiple instructions even when one execution unit is utilized and apportions when multiple execution units are utilized. A detailed discussion of the pipelining concept can be found, e.g. in: David A. Patterson and John L. Hennessy, "Computer Architecture: A quantitative approach", Morgan Kaufmann Publishers Inc., Section 6.1 (1990).
Having described the improvement in ILP accomplished by coping with control dependency, the herein below description focused on other hitherto known techniques for further enhancing ILP by coping with the so called anti-data dependency and output data dependency (referred to also as write-after-read conflict and write-after-write conflict, respectively). It should be noted that in the context of the invention, "write-instruction" and/or "read instruction" should be construed as forming part of write-after-write, read-after-write or write-after-read conflicting instructions. For a better understanding of the foregoing, attention is directed to the following exemplary computer program segment written in pseudo-assembly language:
______________________________________ ADD R1, R2, R3 ADD R4, R7, R1 ADD R1, R7, R2 ______________________________________
The first instruction sums the contents of registers R2 and R3 and stores the result in register R1. Likewise, the second and third instructions realize the arithmetic operations R4=R7+R1 and R1=R7+R2 respectively.
Whilst, ideally, it would be desirable to route the three specified instructions to three separate execution units, respectively, so as to attain maximal ILP, it is readily seen that the first and second instruction constitute true data dependency (referred to also as read-after-write conflict) since the input operand R1 of the second instruction (the read instruction), can be set only after the termination of the execution of the first instruction (the write instruction), i.e. R1 holds the value of R2+R3. Accordingly, the first and second instructions should be executed serially. The first and the third instructions exemplify the output data dependency (or write-after-write conflict). Write-after-write conflict always involves instructions write to the same location. By this particular example it is not possible to execute the first and third instructions simultaneously (and only afterwards the second instruction), since the second instruction requires as an input R1=R2+R3. Had the first and third instructions been executed simultaneously and assuming that the third execution unit is slower (in only fraction of a second), it would have result in R1 holding the value of R2+R3 upon the termination of the first execution unit, and immediately afterwards (i.e. when the third execution unit terminates its calculation) the latter value of R1 is overwritten by a new value (i.e. R1 holds the value of R7+R2). Now the execution of second instruction is erroneous since the input operand R1 holds a wrong value (i.e. R7+R2 rather than R2+R3).
The write-after-write conflict is easily resolved, e.g. by employing a so called register renaming technique (Superscalar Microprocessor Design, Mike Johnson, Book). Thus, for example, the register R1 of the third instruction is assigned to a virtual register R' (which may practically be a free physical register R.sub.n). Now, the first and the third instruction may be executed simultaneously and upon termination of the first instruction, the second instruction is executed.
By following this approach, the input operand R1 of the second instruction stores the correct value of R2+R3 whereas the result of the third instruction is temporarily stored in R' (R.sub.n). All that remains to be done is to move the contents of register R' to R1 so as to duly realize the third instruction.
A similar approach is used with respect to the so called "anti-data" dependency and a detailed discussion of the anti-data and output-data dependencies as well as the possible solutions to cope with this phenomenon can be found in (Superscalar Microprocessor Design, Mike Johnson, Book).
All the hitherto known techniques do not address the problem of true data dependency as explained above, and albeit they improve the ILP, this does not bring about sufficient utilization of the multiple execution units employed by present and future processors.
Mikko H. Lipasti, Christopher B. Wilkerson and John Paul Shen in their publication (Value Locality and Load Value Prediction, Proceeding of the PACT Conference 1996) have introduced a new technique which purports to address to a certain extent, the problem of true data dependency.
The proposed technique attempts to overcome the inherent delay in a program's execution that occurs when encountering a "load" instruction. Normally, a load instruction loads an operand from a source address into a destination register. If the source address is located in a memory other than the fast cache or physical register, a relatively long number of processor cycles (hereinafter wait cycles) are required for fetching the operand from the source address. (The same applies, of course, to the destination address.)
Consider, for example, the following two instructions in pseudo-assembly language:
LOAD R1, source PA1 ADD R3, R2, R1 PA1 the processor further comprising a decoder for decoding said instructions, an issue unit for routing decoded instructions to at least one execution unit; PA1 the processor is characterized in further having a predictor being responsive to a first set of instructions, from among said value generating instructions, for predicting, with respect to each one instruction in said first set of instructions, a predicted value that is determined on the basis of a prediction criterion which includes; (i) at least one previous value generated by said one instruction; and (ii) at least one stride; PA1 said issue unit being further capable of detecting a sequence of write instruction followed by at least one read instruction, the sequence constituting read-after-write conflicting instructions, such that the destination of said write instruction and at least one input operand of each one of said read instructions being the same; said write instruction belongs to a second set of instructions from among said first set of instructions and each of the at least one read instruction belongs to a third set of instructions from among said instructions; PA1 said issue unit is capable of assigning the predicted value of said write instruction to the at least one operand of said read instructions thereby rendering the latter speculative instructions, and is further capable of routing said write and at least one of said read instructions to distinct execution units, from among said at least two execution units, so as to accomplish parallel processing; and PA1 (i) fetching instructions stored in said memory device; each instruction constitutes either a value generating instruction or a non-value generating instruction; each one of said value generating instructions having at least one destination for storing said value; PA1 (ii) decoding said instructions; PA1 (iii) routing decoded instructions to at least one execution unit; PA1 (iv) predicting with respect to each one instruction in a first set of instructions, from among said value generating instructions, a predicted value that is determined on the basis of a prediction criterion which includes: (i) at least one previous value generated by said one instruction; and (ii) at least one stride; PA1 (v) detecting a sequence of write instruction followed by at least one read instruction, the sequence constituting read-after-write conflicting instructions, such that the destination of said write instruction and at least one input operand of each one of said read instructions being the same; said write instruction belongs to a second set of instructions from among said first set of instructions and each of the at least one read instruction belongs to a third set of instructions from among said instructions; PA1 (vi) assigning the predicted value of said write instruction to the at least one operand of said read instructions thereby rendering the latter speculative instructions; PA1 (vii) routing said write and at least one of said read instructions to distinct execution units, from among said at least two execution units, so as to accomplish parallel processing; and PA1 (viii) committing at least said speculative instructions. PA1 the processor further comprising a decoder for decoding said instructions, an issue unit for routing decoded instructions to at least one execution unit; PA1 the processor is characterized in further having a predictor being responsive to a first set of instructions, from among said calculating instructions, for predicting, with respect to each one instruction in said first set of instructions, a predicted value that is determined on the basis of a prediction criterion which includes: (i) at least one previous value generated by said one instruction; PA1 said issue unit being further capable of detecting a sequence of write instruction followed by at least one read instruction, the sequence constituting read-after-write conflicting instructions, such that the destination of said write instruction and at least one input operand of each one of said read instructions being the same; said write instruction belongs to a second set of instructions from among said first set of instructions and each of the at least one read instruction belongs to a third set of instructions from among said instructions; PA1 said issue unit is capable of assigning the predicted value of said write instruction to the at least one operand of said read instructions thereby rendering the latter speculative instructions, and is further capable of routing said write and at least one of said read instructions to distinct execution units, from among said at least two execution units, so as to accomplish parallel processing; and PA1 commit unit for committing at least said speculative instructions. PA1 (i) fetching instructions stored in said memory device; each instruction constitutes either a value generating instruction or a non-value generating instruction; each one of said value generating instructions having at least one destination for storing said value; said value generating instructions include calculating instructions; PA1 (ii) decoding said instructions; PA1 (iii) routing decoded instructions to at least one execution unit; PA1 (iv) predicting with respect to each one instruction in a first set of instructions, from among said calculating instructions, a predicted value that is determined on the basis of a prediction criterion which includes: (i) at least one previous value generated by said one instruction; PA1 (v) detecting a sequence of write instruction followed by at least one read instruction, the sequence constituting read-after-write conflicting instructions, such that the destination of said write instruction and at least one input operand of each one of said read instructions being the same; said write instruction belongs to a second set of instructions from among said first set of instructions and each of the at least one read instruction belongs to a third set of instructions from among said instructions; PA1 (vi) assigning the predicted value of said write instruction to the at least one operand of said read instructions thereby rendering the latter speculative instructions, PA1 (vii) routing said write and at least one of said read instructions to distinct execution units, from among said at least two execution units, so as to accomplish parallel processing; and PA1 (viii) committing at least said speculative instructions.
As shown, after loading the content of the "source" address into register R1 it is added to R2 and stored in register R3. Obviously, the execution of the second instruction (ADD) can commence only upon the termination of the first instruction, thereby constituting true data dependency.
Since, as specified before the load instruction may require a few wait cycles until the input operand is fetched, this necessarily leads to slowing down the execution time of the entire program due to the constraint to commence the execution of the ADD instruction only upon the termination of the load instruction. This is particularly relevant when bearing in mind that a typical computer program includes few and occasionally many load instructions.
Having explained the normal operation of load instruction in the context of true data dependency, there now be explained the proposed improvement of the Mikko H. Lipasti, Christopher B. Wilkerson and John Paul Shen which introduces ILP in read-after-write conflict in the specific case of load instruction. The proposed improvement is based on the fundamental premise that the value of a source operand fetched from a source address has not changed since the previous access to the same individual load instruction. Applying this approach to the previous exemplary instructions results in that after executing the "load" instruction for the first time (which as recalled may require few processor wait cycles) the value stored in the source address is copied to a readily accessible data structure, (i.e. an indexed but not tagged hash table). Now, when the same instruction is encountered for the second time, the readily accessible data structure is accessed and the value is retrieved therefrom and may be stored immediately at the input operand of the second instruction (ADD) before the actual value is fetched from the source address. This scenario enable to expedite the execution of the program since the second instruction (ADD) is executed before the first instruction (load) has been terminated.
All that remains to be done is to commit afterwards the result of the second instruction, similar as to the verification process of the branch prediction i.e. to ascertain that the predicted value (as retrieved from the readily accessible data structure) matches the value as actually retrieved from the source address. If in the affirmative, the second instruction is committed and a certain level of parallelism has been accomplished. If on the other hand, the values do not match the results of the second instruction has to be discarded and the instruction must be executed again. The latter case of mis-prediction involves a penalty of a single clock cycle.
The proposed "expedite load" technique resembles to a certain extent the hitherto known "forward" technique for enhancing execution. As is well known to those versed in the art, "forwarding" is a technique that is normally used in the case that the output of a given instruction is used as an input of a succeeding instruction (i.e. read-after-write conflict). In the latter case the forwarding technique affords to skip conventional "house cleaning" stages, that are normally executed upon termination of the execution of an instruction, by "injecting" the result to the waiting operand of the succeeding instruction (the read instruction), immediately upon the production thereof at the output of the execution unit, thereby expiating the processor performance.
The proposed "load expedite" purports to offer a solution for true data dependency prediction only in the context of load instructions, accordingly the accomplished ILP is indeed limited. As reported, the improvement of only 3-9% is obtained when the "load expedite" method is implemented in Power Pc 620.TM. and Alpha 21064.TM..
It should be noted that several other hitherto known per se technologies are capable of addressing the same problem whilst accomplishing comparable results such as data pre-fetching and write-cache techniques. In so far as practical realization of the proposed "load expedite" technique is concerned, it should be noted that in order to benefit from executing multiple mutually dependent load instructions at the same time, multiple load/store units are required to access the memory system, and possibly to carry out parallel verification procedures. However, utilizing multiple load/store units poses undue cost to current and future processor technology in terms of overly large die space and increased power dissipation.
It is accordingly a general object of the object of the present invention to further enhance ILP and in particular to offer, an enhanced technique to cope with read-after-write instruction conflict (or true data dependencies).

System and method for concurrent processing

Technion Research and Development Foundation Ltd.


A valve device controls a flow of intake air within a surge tank connected to an engine. The surge tank is divided into a plurality of tank chambers by a partition wall disposed within the surge tank. The valve devices include a valve body and a valve member. The valve body has a frame mounted within a communication opening defined within the partition wall. The valve member is rotatably mounted to the valve body in order to open and close a frame opening defined in the frame. A motor is coupled to the valve member in order to rotate the valve member. The motor includes a stator molded integrally with the valve body.

1. Field of the Invention
The present invention relates to valve devices for controlling the flow of intake air supplied to internal combustion engines, in particular, multicylinder internal combustion engines.
2. Description of the Related Art
In order to control the flow of intake air of multicylinder internal combustion engines, variable intake air systems having valve devices have been used. In particular, in order to shift nodes of acoustic oscillations the intake air may produce and to increase an effective intake-air column length, variable intake air systems known as "acoustic control induction systems (ACIS)" have been proposed.
Japanese Laid-Open Patent Publication No. 2000-55200 teaches a valve device for controlling the flow of intake air and for use with an acoustic control induction system. The valve device includes a valve body, a valve member, and an actuator. The valve body is made of resin and has a frame portion fittable into an opening defined within a partition wall. The partition wall is disposed within a tank chamber of a surge tank of an internal combustion engine in order to divide the tank chamber into sub-chambers. The valve member is rotatably mounted on the valve body in order to open and close an opening defined by the frame portion of the valve body. The valve member operates in order to permit and interrupt communication between the sub-chambers. The actuator serves to rotate the valve member.
In the above publication, a diaphragm-type, negative-pressure control device is typically incorporated as the actuator. However, this type of actuator involves various components and tubes, complicating assembly and increasing manufacturing costs.

Valve devices for controlling flow of intake air


A data processing apparatus having a pipeline computer architecture with an input pipeline latch is disclosed. The data processing apparatus includes an ALU that executes a plurality of processing instructions. At least some of the instructions have an immediate data format including a field for intermediate data and a field for specifying a destination for an output. The ALU uses two operands for performing at least some of the instructions having the immediate data format. The ALU conditionally accepts either the contents of the input pipeline latch or the ALU output of the previous instruction as a second operand to an immediate instruction depending on the destination specified in the destination field of the previous instruction.

1. Field of the Invention
The present invention is directed to a pipelined processor. Specifically, the present invention is directed to a pipelined processor having sequential processing instructions wherein at least some of the processing instructions conditionally use an operand.
2. Prior Art
A typical processor architecture may include a series of processing instructions where an instruction having an immediate data format can use one or more operands. Because immediate instructions can not specify all the operands they need, they use implied operands that are typically the result of the prior instruction. The typical implied operands are an "accumulator," a register usually located in the arithmetic unit of a processor, or a "top of stack," the last memory location used in a last in first out data memory mechanisms. In addition to an accumulator or top of stack a pipeline architecture has several pipeline latches or bus states that may contain useful data that could also be used as an implied operand.
Restricting an immediate instruction's second operand to be the outputs of the previous instruction or data supplied by a single pipeline latch limits the functionality of the immediate instruction in the processor. It is therefore an object of the present invention to provide a pipelined processor enhanced functionality through an expanded availability of operands that can be received by an immediate instruction.

Microprocessor system with flexible instruction controlled by prior instruction


In odd-numbered current-supplying periods of a plurality of current-supplying periods constituting a gross current-supplying time, a control unit 42 allows continuous switching actions of only a first set of switching elements at an inverter frequency, with a second set of switching elements remaining OFF. In even-numbered current-supplying periods, the control unit 42 allows continuous switching actions of only the second set of switching elements at the inverter frequency, with the first set of switching elements (24, 28) remaining OFF. As a result of this, a secondary circuit of the power supply apparatus allows a secondary current i2, namely a fusing current I having a substantially trapezoidal current waveform to flow in a positive direction in the odd-numbered current-supplying periods, and to flow in a negative direction in the even-numbered current-supplying periods.

1. Field of the Invention
The present invention relates to a fusing processing method making use of Joule heat and a pressurization force in order to crimp a workpiece.
2. Description of the Related Art
An exemplary fusing work is illustrated in FIGS. 3A to 3C. This work provides electrical and physical connections between a covered wire 10 and a strip-like terminal 12 made of e.g., copper or copper alloy.
Referring first to FIG. 3A, a workpiece is inserted between a pair of (e.g., upper and lower) electrodes 14 and 16, the workpiece consisting of the terminal 12 and the covered wire 10 embraced in a hooked portion or a bent portion 12a of the terminal 12. The undersurface of the terminal hooked portion 12a is carried by the lower electrode 16 at a fixed position, with the upper electrode 14 abutting against the top surface of the terminal hooked portion 12a so that the latter is pressed downward with a predetermined pressurizing force F by a pressure device not shown. At the same time, a predetermined voltage is applied to the two electrodes 14 and 16 by a power supply apparatus not shown.
Then, current I first flows, through the terminal hooked portion 12a providing a current path, between the pair of electrodes 14 and 16, to generate Joule heat at the terminal hooked portion 12a. As a result of this, an insulator 10aof the covered wire 10 melts by Joule heat and peels off a conductor 10b as illustrated in FIG. 3B.
Once the insulator 10a is removed, current I is allowed to flow, through the conductor 10b (typically, made of copper) of the covered wire 10, between the two opposing electrodes 14 and 16 as illustrated in FIG. 3C. During the current-supplying period as well, the pressurization force F is still continuously applied to the two electrodes 14 and 16, and hence Joule heat and pressurization force F act, in cooperation, to cause the terminal hooked portion 12a and the covered wire conductor 10b to be integrally pressure welded or pressure squashed for crimping. This enables the covered wire 10 and the terminal 12 to be electrically and physically joined together in a rigid fashion. Due to an extremely small resistance of the conductor 10b of the covered wire 10 and the terminal 12, no nugget will be generated therebetween.
FIG. 6 illustrates a circuit configuration of a single-phase AC power supply apparatus that has hitherto been used for the fusing work as described above. FIG. 7 illustrates waveforms of the voltage and current delivered from the power supply apparatus.
In this power supply apparatus, a single-phase AC voltage V of a commercial frequency fed to input terminals 100 and 102 is applied to a primary coil of a step-down transformer 108 by way of a contactor that is comprised of a pair of thyristors 104 and 106. An AC induced electromotive force (secondary voltage) generated at the secondary coil of the transformer 108 is applied through the secondary conductor and the electrodes 14 and 16 to the workpiece W (10, 12) so as to allow a secondary current i2 having a larger current value than that of a primary current i1 to flow as the fusing current I through the secondary circuit.
The magnitude (effective value) of the fusing current I (i2) is determined depending on a conduction angle. Due to the presence of a substantially fixed relation between a firing angle and the conduction angle, it may be said that the magnitude depends on the firing angle. This power supply apparatus provides a control of firing angles (firing timings) xcex8 of the thyristors 104 and 106 by way of a firing circuit 112, to thereby control the effective value of the fusing current I (i2).
FIG. 8 illustrates a configuration of a DC inverter power supply apparatus that has hitherto been used in the fusing work. FIGS. 9A and 9B depict waveforms of the voltage and current output from the power supply apparatus.
This power supply apparatus comprises an inverter circuit 120 to which a DC voltage E is applied at a predetermined voltage level by a rectifying circuit not shown. The inverter circuit 120 includes switching elements and serves to issue high-frequency AC pulses in such a manner as to chop up the DC input voltage E at a high-frequency switching in response to a control pulse CP from a inverter control unit 128. The AC pulses output from the inverter circuit 120 are fed to a primary coil of a step-down transformer 122 so that AC pulses similar to those at primary side are acquired in the secondary coil. The secondary pulsed alternating current is converted into a direct current by a rectifying circuit 126 consisting of a pair of diodes 124a and 124b, with the secondary direct current i2 being fed as a fusing current I to the workpiece W (10, 12) by way of the electrodes 14 and 16.
In such a conventional fusing processing method using the single-phase AC power supply apparatus, the ratio is small of the effective current-supplying time (the time during which current actually flows) to the gross current-supplying time, so that a current peak value needs to be increased in each current-supplying cycle if it is desired to supply a sufficient thermal energy for the fusing work. However, the increased current peak value tends to result in an increased instantaneous peak value of Joule heat generated in the workpiece, which may possibly cause undesirable deformations or damages as a result of heat shock to which the workpiece W may be subjected. In the example of FIGS. 3A to 3C, immediately after the commencement of current supply (i.e., at the stage of FIG. 3A), the bend of the hooked portion 12a of the terminal 12 may crack in the vicinity of its top due to the heat shock.
On the contrary, in the conventional fusing processing method using the DC inverter power supply apparatus, the ratio of the effective current-supplying time is large and its heat generating efficiency is high, so that a sufficient thermal energy can be supplied to the workpiece even at a relatively low current peak value, and thus any heat shock can be suppressed. However, this method is problematic in that since the fusing current I can flow between the two electrodes only in the same direction (polarity), the amount of heat generation may differ from place to place due to Peltier effect appearing between the electrodes 14, 16 and the workpiece W, whereupon the deformations and wears at the extremities of the electrodes are apt to concentrate in one electrode (typically, in the electrode 14 at positive side), which may result in a cumbersome maintenance and a rise in cost.
The present invention was conceived in view of the above problems. It is therefore the object of the present invention to provide a fusing processing method capable of preventing any heat shock on a workpiece to improve the work quality and evening out the wears and degradations of the electrodes to improve the maintenance (workability, costs).
According to an aspect of the present invention, in order to attain the above object, there is provided a method of fusing a workpiece in which a pair of electrodes are pressed against the workpiece while simultaneously a current flows through the pair of electrodes to the workpiece to generate Joule heat, the method comprising the steps of converting an AC voltage of a commercial frequency into a DC voltage by means of a rectifying circuit; converting the DC voltage output from the rectifying circuit, into a pulsed voltage of a high frequency by means of an inverter; passing the high-frequency pulsed voltage output from the inverter through a transformer, to apply it via the pair of electrodes to the workpiece without any rectification at secondary side of the transformer; and segmenting a current-supplying time for a single fusing processing into a plurality of current-supplying periods, to output the high-frequency pulses with one polarity from the inverter in odd-numbered current-supplying periods, but to output the high-frequency pulses with the other polarity from the inverter in even-numbered current supplying periods.
In a fusing processing method of the present invention, the inverter allows a high-frequency waveform-controlled current to flow between two electrodes in each current-supplying period, whereby it is possible to achieve a high heat generating efficiency and hence to supply a sufficient heat energy to the workpiece even with a relatively low current peak value. This prevents the workpiece from being subjected to any heat shocks, enabling a stabilized fusing quality to be acquired. Furthermore, the polarity (direction) of current flowing between the two electrodes during the current-supplying time is inverted for each current-supplying period so that Peltier effect appearing between the electrodes and the workpiece is cancelled out or evened out and the amount of heat generation is also uniformed, thereby preventing deformations and wears at the electrode extremities from concentrating in one electrode, to ensure a fine finish in the fusing processing.


A communication terminal device includes a wireless communication unit, an integrity measurement request unit, a cryptographic processing unit, a pointing unit. The integrity measurement request unit generates a command to request another computer device to measure integrity. The cryptographic processing unit performs cryptographic processing concerning communication with the another computer device. The pointing unit acquires positional information when a result of the integrity measurement satisfies a predetermined condition.

1. Field of the Invention
The present invention relates to a communication terminal device and a computer device and specifically, relates to a portable communication terminal device which has a function equivalent to a mouse used as a pointing device of the computer device and can verify the reliability of the computer device.
2. Description of the Related Art
When a user uses a computer which is not the user's own at a place where the user goes or the like, if whether the computer is reliable can be verified, the user can use the computer for purposes critical in security such as electronic commerce and access to a company's private network, thus improving the convenience of the user.
Specifications to prove a computer to be reliable have been proposed by TCPA (TCG) (for example, see Compaq Computer Corporation, Hewlett-Packard Company, IBM Corporation, Intel Corporation, Microsoft Corporation, "Trusted Computing Platform Alliance (TCPA) Main Specification Version 1.1b", 22 Feb. 2002, http://www.trustedcomputing.org/docs/main %20v11b.pdf). However, these specifications are based on cryptographic processing, and an entity challenging the reliability of the computer also must have a cryptographic capability. Specifically, to verify the reliability of the computer at the place where the user goes, the user has to bring any equipment including the cryptographic capability. Herein, the equipment needs to provide excellent portability and reliability for the user.
A method in which a user verifies the reliability of the computer using a smart card has been therefore disclosed (for example, see "Trusted Computing Platforms: TCPA technology in context", Siani Pearson, et al, Published July, 2002 by Prentice Hall PTR, ISBN 0-13-009220-7". The smart card provides excellent portability and tamper resistance, which is reliable equipment for the user. However, the smart card does not include an I/O function and needs a device to transmit results of reliability verification of the computer to the user. In "Trusted Computing Platforms: TCPA Technology in context", a user previously stores in the smart card secret information (a particular image or word) that only the user can know, and the smart card challenges the computer. Only when obtaining the result that the computer is reliable, the smart card transmits the secret information to the computer. The secret information is displayed on a display of the computer, so that the user can verify the reliability of the computer.
This method allows the user to verify the reliability of the computer before the computer is brought into use but does not provide a mechanism allowing the user to easily know that the reliability of the computer continues while the computer is in use. Accordingly, for example, it is highly possible that the user does not know if the computer is invaded by a virus during use and carries out an operation dangerous to the security. Moreover, when the secret information that only the user can know is repeatedly used, the secret information used in the past remains in the computer, and a malicious person can use the secret information to cause a unreliable computer to display the same and mislead the user.
In the light of the aforementioned problem, an object of the present invention is to provide a communication terminal device and a computer device which can perform easy, continuous, and sure verification whether a computer is reliable when the computer is used.

Communication terminal device and computer device