Systems and methods provide for the rewriting and transformation of a code unit through an extensible, composable, set of code rewriters that can be implemented at various phases throughout the development, deployment, and execution of the code unit. The described systems and methods provide a powerful way for program developers and system administrators to implement code transformations at different stages throughout the development, deployment, and execution of programs that is largely independent of such programs and does not significantly increase the complexity of the source programs, compilers, or execution environments.

Program development typically follows a cycle of writing source code, editing the source code, compiling the source code, and then executing the resulting binary code. The development cycle may occur in various computing environments ranging, for example, from an individual developer's computer to a system of computing devices that includes the developer's computer, intermediate computers, and an enterprise of deployment computers interconnected through one or more networks. Thus, the cycle may also include intermediate stages that involve, for example, the installation and execution of the program on an intermediate computer prior to the installation and execution of the program on final deployment computers.
There are various reasons why a program might need to be transformed at some point throughout its development cycle. For example, there may be a need to introduce code into a program to monitor its execution and determine whether it is running correctly. Such "watchdog" code might perform tasks such as counting the number of times a particular function is called or sending the output of a particular function to a file. If a problem is discovered in the execution of a program, there may be a need to further transform the program to include additional code designed to discover the source of the problem.
Some programming languages support features that enable certain transformations such as the introduction of "watchdog" code. However, these transformation features are typically very limited. In addition, such features are typically implemented through compilers that are language-specific. Thus, one programming language may support a "watchdog" code transformation feature while another may not.
Other reasons for transforming a program during development might include the varying execution environments in which the program will be deployed. For example, a program may run as part of an operating system, a database, or an application program. The semantics, or defined system behaviors, may vary from one environment to another, or they may vary within an environment when the environment changes (e.g., an operating system upgrade). Thus, a program may behave differently in different and changing environments. Therefore, ensuring that a program performs in a consistent manner in different environments may require a program transformation. Such transformations can be achieved by the developer introducing environment-specific code into the source, or by introducing such code through the compiler. Another option is to transform the execution environment. Each of these options has the disadvantage of significantly increasing the complexity of either the program, the compiler, or the execution environment.
Accordingly, there is a need for a way to implement code transformations at different stages throughout the development and deployment cycle of a program that does not significantly increase the complexity of the source program, compiler, or execution environment.


In such electronic components as semiconductor packages and semiconductor chips which are possessed of groups of connecting bumps as input and output terminals, the groups of connecting bumps comprise not less than two kinds of connecting bumps different in melting point or not less than two kinds of connecting bumps different in mechanical strength. The groups of connecting bumps comprise connecting bumps made of high temperature solder or connecting bumps made of a high strength In type solder in the part of formation thereof. The connecting bumps made of high temperature solder are not directly affected by the influence of displacement because they retain the shape of a ball even after the step of connection such as solder reflow. The connecting bumps made of In type solder form connecting parts of high strength. These groups of connecting bumps contribute to exalt the reliability of the connecting parts without decreasing the number of input and output terminals.

1. Field of the Invention
This invention relates to an electronic component possessed of connecting projections as input and output terminals and an electronic component connecting structure electrically connected through the medium of the connecting projections.
2. Description of the Related Art
Various packages formed of ceramic, resinous, metallic, and other materials and intended to mount thereon such semiconductor devices as LSI are tending toward larger densification, fuller adaptation for high speed operation, and more thorough heat release in consequence of the steady trend of LSI toward greater integration, higher operating speed, more power consumption, and more extensive conversion of components into chips. Further, the utility of these semiconductors has disseminated to the extent of covering such industrial products as work stations, personal computers, miniature computers, and large computers and such electronic appliances as portable devices, printers, copiers, cameras, television sets, and video sets. Moreover, the semiconductors themselves have been enjoying continuous improvement in quality.
The packages which serve to mount LSI's of high quality and large integration thereon are required to be capable of permitting connection of the LSI's thereto by means of multiple terminals of narrow pitches, allowing amply dense wiring, releasing heat sufficiently, handling high-speed signals, and admitting multiple terminals of narrow pitches for their input and output terminals. Further, the necessity for perfecting a technique which permits packages of high quality satisfying these requirements to be manufactured inexpensively by a simple procedure with high reliability has been finding widespread recognition.
First, as means to connect a package to semiconductor elements with multiple terminals of narrow pitches, the wire bonding method, the TAB method, the flip chip method, and others have been heretofore known. The wire bonding has been undergoing successive automation and has been most widely adopted to date. Since it can be accommodated to packages differing in mode of programming, it is adaptable to the small-lot great-variety manufacture of packages. In terms of the trend toward narrowing pitches, the technique of the latest development permits bonding with pitches of the order of 100 .mu.m.
The TAB method is at an advantage in permitting collective bonding of chips of multiple terminals, rendering the bonded chips fit to be tested, reducing inductance on account of large lead, and promising an effective heat release by a Cu lead as a radiating path for the LSI. Thus, it is used for liquid crystal driver grade IC's and gate arrays. The flip chips are partly used for high-performance computers, LSI testers, work stations, and others. They are at an advantage in reducing the area for packaging and, at the same time, decreasing the parasitic inductance, capacity, etc. due to the lead junction.
For the sake of enabling such connecting techniques as mentioned above to function effectively, the relevant packages likewise require an inner lead part using narrow pitches and multiple terminals. Further, it has become essential that the connection of such packaging boards as substrates for printed circuits to packages similarly require densification (increase in the number of components per chip) by increasing the number of terminals and narrowing the size of pitches. This connection further demands due consideration of electrical characteristics because the packages themselves require to handle high-speed signals owing to the trend of LSI's toward increasing operating speed as mentioned above.
To meet this trend of packages toward increasing number of terminals and decreasing size of pitches, the package structures are now in transition from the conventional pin insertion type to the surface mount type such as QFP (quad flat package). In the package structures of the surface mount type, those which have large numbers of terminals and high speeds of operation include the SM-PGA (surface mount type pin grid array) packages and narrow pitch QFP packages, for example. The surface mount type packages which use pins and leads, however, incur difficulty in further decreasing the size of pitches because they have such pins and leads joined to their packages proper. A hard problem from the viewpoint of process is encountered in decreasing the size of pitches below 1.27 mm in PGA packages and below 0.3 mm in QFP packages, for example. These packages are further at a disadvantage in requiring such works as solder printing and mounting to be carried out at elevated temperatures when components are mounted on substrates for printed circuits and others.
The PGA and the QFP packages which are possessed of pins and leads, when so operated as to handle signals of high speeds, entrain the problem of inducing reflection of the signals owing to the high-frequency characteristics and aggravated delay of the signals owing to the inductance component because the effect of inductance is exalted in the parts of pins and leads. Even when the inductance is decreased as by controlling the characteristic impedance or providing a power source or a ground surface for the purpose of adapting the multilayer wiring structure of a package proper for an operation of a high speed, the degradation of the characteristics in the parts of pins and leads mentioned above is so heavy as to render difficult the adaptation for signals of high speeds.
The BGA (ball grid array) package was proposed for the solution of such problems as mentioned above. At first, it found utility in super computers and other large computers. Recently, it has been finding growing utility in such household products as personal computers and portable implements. The BGA is a package structure which uses connecting projections such as, for example, solder bumps as input and output terminals for a package. Owing to the use of solder bumps which are capable of decreasing the distance of connection, such problems as the reflection, delay, etc. of high-speed signals by the inductance which originate in the pins and the leads mentioned above can be eliminated.
The formation of bumps, in addition to permitting a decrease in the distance of connection, facilitates the increase in number of terminals and the decrease in size of pitches. Thus, the BGA promises as a future LSI package. The success of the bumps in attaining a decrease in the size of pitches and an increase in the number of terminals can be expected to reduce the size of package itself, improve the density of package as on a substrate for a printed circuit, enhance the electrical characteristics by lowering the parasitic capacity, the inductance, the resistance, etc. of a wiring, and improve the high-frequency characteristics owing to the reduction of the size of package. Further, the BGA, having no pins nor leads which are easy to bend, contribute to facilitate the packaging work as compared with that in the SM-PGA package using pitches of 1.27 mm or that in the QFP package using pitches of 0.3 mm.
From the viewpoint of the heat release from a package, the power consumption and the amount of heat to be generated are both on the increase year after year owing to the trend of LSI's toward increasing speeds of operation. The packages themselves, therefore, require a structure and a material which both excel in the ability to release heat. For packages of high radiation, ceramic packages are mainly used. Packages using ceramic materials predominate, though there are packages which use a metallic material in their main bodies and packages which comprise a printed circuit, use a resinous material, and incorporate therein a heat sink for radiation. In the ceramic packages, those which use such a highly conductive material as aluminum nitride (AlN) are utilized as offering particularly low thermal resistance.
The BGA packages using ceramic materials are high-density packages which enjoy high heat release and excellent electrical characteristics and, at the same time, permit an increase in the number of terminals and a decrease in the size of pitches as described above and are expected to find utility as packages for semiconductor devices of heightened speeds of operation and increased degrees of densification. The BGA packages which use ceramic materials, however, are at a disadvantage in respect that, when they are actually mounted as on substrates for printed circuits, the solder parts destined to serve as connecting parts have poor reliability because the thermal expansion coefficient of a ceramic substrate and that of a printed circuit are widely different. The thermal stress which is generated by this difference of thermal expansion is ascribable partly to the thermal hysteresis which occurs in the step of solder reflow during the mounting of the BGA package on a printed circuit and to the change of the ambient temperature during the course of normal use of the BGA package. In any event, owing to the large difference in thermal expansion between the ceramic package and the printed circuit, the stress is concentrated in the connecting parts with solder bumps which have low mechanical strength. This concentration of stress in the connecting parts entrains the problem of inflicting a crack in the connecting parts or fracturing the connecting parts and impairing the reliability of electrical connections and mechanical connections.
Meanwhile, the feasibility of improving the shapes of the connecting parts by solder bumps, namely the shapes the solder bumps assume after they are melted, for the purpose of solving such problems as mentioned above is now being studied. In terms of shape, by imparting the general shape of an hourglass to the connecting parts with solder bumps, the parts in which stress is concentrated can be shifted from the interfaces between the connected parts and the printed circuit to the central portions of the connected parts and the reliability of these connected parts can be consequently exalted.
Since the hourglass shapes of the connected parts are different from the shapes (like spheres or drums) which the connected parts assume when their solder is naturally melted, however, the distances between the opposed surfaces which are being connected must be controlled for the purpose of imparting the shape of an hourglass to all the connected parts. Thus, the feasibility of controlling the distances between the opposed surfaces being connected by having a spacer inserted between a package and a printed circuit preparatorily to the insertion of the package into a reflow furnace for melting the solder is being studied in a certain quarter of the industry. This measure, however, results in impairing the advantage of BGA as a package of high density because the number of input and output terminals is decreased proportionately to the area to be sacrificed for the insertion of the spacer. Moreover, the spacer serves solely as a heat spreader for transmitting heat to the substrate and plays absolutely no function electrically and disrupts all efforts of cutting the total number of components.
The problems remarked above are not limited to the BGA packages but are encountered by semiconductor devices of flip chip structures possessed of solder bumps as input and output terminals and surface-mounted products similarly using plural semiconductor devices in the form of modules. The connection of the input and the output terminal of a semiconductor device to a package or a printed circuit has been heretofore implemented predominantly by the wire bonding as already described above. This connection is becoming increasingly difficult because the capillary of wire bonding increases in proportion as the pad pitches of the semiconductor devices decrease. Further, the resultant addition to the length of connection augments the inductance to the extent of intolerably degrading the electrical characteristics. As a means to decrease this unduly large inductance, the use of bumps in packaging a semiconductor device has a bright prospect. This approach, however, incurs the same problem as the BGA package made of a ceramic material on account of a large difference in thermal expansion between the semiconductor device and a printed circuit.
In the electronic components which are possessed of connecting projections (bumps) as input and output terminals for the conventional BGA packages made of ceramic materials and the semiconductor elements of flip chip structures, when they succumb to the thermal hysteresis due to a change in the ambient temperature at the step of reflow soldering during the packaging of such an electronic component as on a printed circuit or during the course of actual use of the electronic component, the difference in thermal expansion between the ceramic package or semiconductor and the printed circuit gives rise to stress or strain in the connecting parts with solder bumps. The stress or strain brings about the problem of causing the connected parts to sustain fracture due to thermal fatigue, inflicting a fracture by stress on the ceramic package or semiconductor element itself, and degrading the reliability of connection.

Electronic component and electronic component connecting structure


A method for crystallizing an amorphous semiconductor thin film using a non-metal seed epitaxial growth (NSEG) is provided. The method includes the steps of: forming a pair of non-metal seeds for inducing a crystallization of an amorphous semiconductor thin film at a predetermined distance on a transparent insulation substrate; depositing the amorphous semiconductor thin film on the insulation substrate; and heat-treating the insulation substrate to thereby epitaxially grow a poly-crystalline semiconductor thin film from the non-metal seeds, and to thus crystallize the amorphous semiconductor thin film. In the crystallization method, non-metal seeds are used instead of using crystallization induced metal to thereby epitaxially grow the poly-crystalline semiconductor thin film and to thus realize the amorphous semiconductor thin film without having metal pollution.

1. Field of the Invention
The present invention relates to a method for crystallizing an amorphous semiconductor thin film, and a method for fabricating a poly-crystalline thin film transistor using the same, and more particularly, to a method for crystallizing an amorphous semiconductor thin film, and a method for fabricating a poly-crystalline thin film transistor using the same, in which a poly-crystalline semiconductor thin film is epitaxially grown using a non-metal seed to thereby realize a crystallization of an amorphous semiconductor thin film having no metal pollution and to thus manufacture a thin film transistor having excellent characteristics.
2. Description of the Related Art
In general, a thin film transistor which is used in a display device such as a liquid crystal display (LCD) or an organic light emitting diode (OLED) is fabricated by processes of depositing amorphous silicon on a transparent substrate such as glass or quartz, forming a gate insulation film and a gate electrode, injecting impurities into a source and a drain, and then annealing the impurities-injected source and drain to thereby activate the injected impurities.
By the way, as a display device using a thin film transistor gradually requires for a fast operating speed and becomes compact in size, a degree of integration of a driving integrated circuit (IC) becomes large and an aperture ratio of a pixel region becomes reduced. Accordingly, an electron mobility on a silicon film should be heightened so that a driving circuit is formed simultaneously together with a pixel thin film transistor (TFT), and an aperture ratio of each pixel should be heightened.
For this purpose, amorphous silicon is crystallized to form poly-crystalline silicon having a large electron mobility. Poly-crystalline silicon is largely divided into high-temperature poly-crystalline silicon obtained by processes of depositing amorphous silicon on a quartz substrate, and then heat-treating the amorphous silicon at a high temperature, and low-temperature poly-crystalline silicon obtained by processes of depositing amorphous silicon on a glass substrate, and then heat-treating the amorphous silicon at a low temperature. Here, a low-temperature poly-crystalline silicon fabrication technology is divided into an eximer laser annealing (ELA) method and a metal induced lateral crystallization (MILC) method which uses crystallization induced metal such as nickle as a catalyzer.
The eximer laser annealing (ELA) method requires for expansive equipment and crystallize silicon by a scanning process, and thus has defects in view of surface roughness and crystallization uniformity. In contrast, the MILC method can utilize conventional heat-treatment equipment and has merits of having a relatively low processing temperature and a relatively short processing time.
However, since the MILC method uses crystallization induced metal, electrical characteristics of a thin film transistor deteriorate due to metal pollution. That is, a leakage current of the thin film transistor increases and an electron mobility thereof decreases. Although various methods have been developed in order to suppress them, fundamental problems have not been solved yet.
A conventional eximer laser annealing (ELA) method of fabricating a poly-crystalline thin film transistor using a conventional method will follow.
FIGS. 1A through 1D are cross-sectional views for explaining a method of fabricating a poly-crystalline thin film transistor using an eximer laser annealing (ELA) method according to the conventional art.
Referring to FIG. 1A, a buffer layer 10 made of an oxide film is formed on an insulation substrate (not shown) such as a glass substrate, and then an amorphous silicon film 11 is formed thereon. Then, laser 12 is irradiated on the amorphous silicon film 11 by a scanning process, to thereby crystallize amorphous silicon film 11.
Thereafter, referring to FIG. 1B, the crystallized silicon film 11 is patterned by a photographic etching process, to thereby form a semiconductor layer 11a. Then, an insulation film and a metal film are sequentially deposited on the substrate, and patterned using the photographic etching process, to thereby form a gate insulation film 13 and a gate electrode 14.
Then, as shown in FIG. 1C, N-type or P-type dopant ions are injected into a source region 11S and a drain region 11D on the substrate using the gate electrode 14 as a mask. Here, a reference designation 11C denotes a channel region.
Thereafter, referring to FIG. 1D, the source region 11S and the drain region 11D are heat-treated by a scanning process in order to electrically activate the dopant ions injected thereinto.
FIGS. 2A through 2D are cross-sectional views for explaining a method of fabricating a thin film transistor using a conventional metal induced lateral crystallization (MILC) method.
Referring to FIG. 2A, a buffer layer 20 made of an oxide film is formed on an insulation substrate (not shown) such as a glass substrate. Then an amorphous silicon film of 500 Å is formed thereon and is patterned by a photographic etching process, to thereby form a semiconductor layer 21. Then, an insulation film and a metal film are sequentially deposited on the substrate, and patterned using the photographic etching process, to thereby form a gate electrode 23 and a gate insulation film 22.
Referring to FIG. 2B, N-type or P-type dopants are ion-injected on the substrate using the gate electrode 23 as a mask, to thereby form a source region 21S and a drain region 21D. As a result, a channel region 21C is defined between the source region 21S and the drain region 21D.
Referring to FIG. 2C, an off-sect structure of approximately 2 μm is formed using a photosensitive agent 24 larger than the pattern of the gate electrode 23. Crystallization induced metal 25 such an nickle (Ni) is deposited by about 50 Å in thickness on the entire surface of the photosensitive agent 24 by a sputtering method.
Thereafter, as shown in FIG. 2D, the photosensitive agent 24 is removed by a lift-off method. Accordingly, the crystallization induced metal 25 is patterned into crystallization induced metal pattern 25a so as to locally remain only in some portions of the source region 21S and the drain region 21D. Thereafter, the substrate is heat-treated using the crystallization induced metal pattern 25a at a temperature of about 580° C. under the hydrogen atmosphere, to thereby crystallize the source region 21S, the drain region 21D, and the channel region 21C, by a metal induced crystallization (MIC) method and the MILC method.
As described above, the conventional crystallization method using a conventional laser heat treatment process requires for expansive equipment and has non-uniform crystallization and inferior surface roughness. As a result, a production cost becomes high and a yield is lowered. Also, metal pollution occurring on a metal film deposited on the amorphous silicon surface for the conventional MILC method exists in the poly-crystalline silicon film, to thus deteriorate an electrical feature of a device (see IEEE Trans. Electron Devices, Vol. 40, No. 5, p. 404, 1993).

Method for crystallizing amorphous semiconductor thin film by epitaxial growth using non-metal seed and method for fabricating poly-crystalline thin film transistor using the same


A cutting apparatus in a strong plastic housing having two rotatable slitter blades. The cutting apparatus is mounted on a guide rail for movement by hand across a tightly held sheet of media such as paper, vellum or film. The slitter blades are mounted back-to-back at an angle, and the shafts to which the blades are mounted are positioned in the housing so that their longitudinal axes are not parallel to each other. This offset minimizes the region of contact between the two blades.

1. Field of the Invention
The present invention relates to a cutting apparatus and method and, more particularly, to a cutting apparatus and method used to cut sheet media such as paper, vellum or film.
2. Description of the Related Art
The cutting of sheet media material has been accomplished automatically by a variety of devices including scissors, razor blades and other sharp instruments. In the field of plotters and printers, such as those used by engineers, cutting may be accomplished by a single cutting wheel as illustrated by U.S. Pat. No. 5,363,123. As disclosed in that patent, substantial work has been invested to automate the cutting operation of such media.
Thus, workers in the field appear to be devoting themselves to automating the cutting operation. This usually means that devices are designed having increased complexity and expense. However, it also means that an operator will have little involvement with the cutting process.


A device for anchoring on biological tissue a prosthetic heart valve, includes first and second anchoring assemblies mutually couplable to secure biological tissue therebetween. The anchoring assemblies include at least one pair of complementary arched portions having anchoring formations for anchoring on the biological tissue. The anchoring formations include integral extensions of the anchoring assemblies extending radially outwardly of one of the anchoring assemblies.

Anchoring a prosthesis to its implantation site may play a key role in implanting cardiac valve prostheses.
Implantation performed in an easy and rapid manner may reduce the risks related to procedures that are complex and/or long to perform.
U.S. Pat. No. 3,143,742, U.S. Pat. No. 3,546,710, U.S. Pat. No. 3,574,865 and U.S. Pat. No. 6,059,827 are representative of so-called sutureless cardiac valve prostheses, which are adapted for anchoring at the implantation site by a technique that does not require suturing the valve to the implantation site.
Once implanted, the valve must resist displacement with respect to the implantation site.
Displacement of the valve may occur, for example, as a consequence of the hydraulic pressure/thrust exerted by the blood flow or due to the movements of the beating heart.

Sutureless anchoring device for cardiac valve prostheses


Apparatus and methods to magnetize and demagnetize the magnetic poles of a rotor assembly for an electrical machine, such as a generator. The apparatus and methods provide for individually magnetize magnetic domains in the permanent magnetic material of the magnetic poles of a rotor assembly of the electrical machine after the electrical machine is installed in a larger assembly. The magnetization system may be used to magnetize and demagnetize the magnetic poles while the rotor assembly is connected with a prime mover, such a rotor of a wind turbine.

This application relates generally to electrical machines and, more specifically, to apparatus and methods for magnetizing and demagnetizing the permanent magnets used in the rotor assemblies of electrical machines, such as permanent magnets found in the rotor assemblies of wind turbine generators.
Wind turbines can be used to produce electrical energy without the necessity of fossil fuels and can be aggregated in onshore and offshore wind farms connected to the electric power transmission network. Generally, a wind turbine is a rotating machine that converts the kinetic energy of the wind into mechanical energy and, when used for power generation, converts the mechanical energy into electrical power. A conventional horizontal-axis wind turbine includes a tower, a nacelle located at the apex of the tower, and a rotor that is supported in the nacelle by means of a shaft. The shaft couples the rotor either directly or indirectly with a rotor assembly of a generator housed inside the nacelle.
Wind turbine generators and their rotor assemblies can have relatively large diameters of up to ten meters. The primary component of the generator weight is the numerous permanent magnets that constitute the magnetic poles of the generator rotor assembly. In particular, the permanent magnets can weigh on the order of two to five metric tones. Installation of the permanent magnets into the rotor assembly of the generator is challenging, particularly as the size of the generator scales upwardly. The permanent magnets are composed of a material that generates a high-Gauss magnetic field when magnetized and, therefore, a material that is capable of generating strong repulsive or attractive forces with surrounding structures.
Conventionally, the magnetic poles used in the rotor assembly of a wind turbine generator are magnetized before it is installed in the nacelle. One conventional option is to magnetize the permanent magnets, install them into the rotor assembly of the generator, and then install the rotor assembly holding the magnetized permanent magnets into the generator. This assembly option requires use of one mechanical fixture to install the magnetized permanent magnets into the rotor assembly and another mechanical fixture to place the rotor assembly holding the magnetized magnets into the generator housing. A variation on this conventional option is to assemble the wind turbine generator sans permanent magnets and then to use a mechanical fixture to load magnetized permanent magnets into slots defined in the rotor assembly. For either of these conventional assembly options, the strong magnetic fields generated by the permanent magnets interact with surrounding structures, such as nearby ferromagnetic structures of the generator and even other permanent magnets previously installed in the rotor assembly. For example, the stator assembly of the generator may be difficult or impossible to remove because of the forces generated by the magnetized permanent magnets.
Another problem arises during maintenance or service of the generator while located in the nacelle. Generally, generator maintenance may be required, for example, as a result of a lightning strike or a short circuit. Once the permanent magnets are magnetized, the rotor assembly and stator assembly are difficult to remove from the generator because the strong magnetic fields. The difficulty is amplified if a gear box is absent and the rotor assembly of the generator is directly driven by the rotation of the rotor. In this instance, the generator cannot be simply decoupled from a gear box and replaced. The permanent magnets are also practically impossible to demagnetize while positioned within the wind turbine generator.
Improved apparatus and methods are needed to facilitate the installation of an electrical machine, such as a wind turbine generator, as well as improved apparatus and methods for servicing the electrical machine.

Methods for magnetizing and demagnetizing magnetic poles in an electrical machine


A through via is constructed in a two-stage process. A void in a portion of the depth of the substrate is filled from a first surface of the semiconductor substrate creating an enclosed volume within the substrate. Thereafter, the enclosed volume is exposed and the remaining portion of the void is filled.

The present invention is generally directed to the field of semiconductor manufacturing, and, more particularly, to various methods for forming conductive through-wafer vias and for forming stacked packages.
Integrated circuit technology relies on transistors to formulate vast arrays of functional circuits. The complexity of these circuits requires the use of an ever-increasing number of linked transistors. As the number of transistors increases, the integrated circuitry dimensions shrink. One challenge in the semiconductor industry is to develop improved methods for electrically connecting and packaging circuit devices which are fabricated on the same and on different integrated circuit dies or chips. In general, it is desirable in the semiconductor industry to construct circuits which occupy less surface area on the silicon chip/die.
As integrated circuit technology progresses, there is a growing desire for a "system on a chip." Ideally, a computing system would be fabricated with all the necessary integrated circuits on one wafer, as compared with today's method of fabricating many chips of different functions and packaging them to assemble a complete system. Such a structure would greatly improve integrated circuit performance and provide higher bandwidth. In practice, it is very difficult with today's technology to implement a high-performance "system on a chip" because of vastly different fabrication processes and different manufacturing yields for the various logic and memory circuits.
As a result, there are economic advantages associated with forming a module or system from an interconnected group of different types of previously-tested integrated circuits. One way of connecting circuit elements at the interface of a module or integrated circuit is to form an electrically conductive via or passage through a wafer or die.
For these applications, a metal filled void-free through via is desired. The conventional fill process is to plate metal into the via. To achieve a complete void-free via, bottom up plating is a typical approach. However, such bottom up plating is difficult. First, due to the high aspect ratio of the via, the diffusion of metal ions from a plating solution to the bottom of the via results in a slow fill rate. Second, plating thickness is not uniform with the layer near the bottom of the via being much thinner than the layer at the opening of the via. The application of a higher plating current density only exacerbates the problem as the significantly higher deposit rate at the via opening results in metal filling the upper portion of the via before the bottom of the via can be filled. Plating chemistry has been modified in an attempt to accomplish a void-free via. These attempts include additives to suppress plating at the opening of the via and additives to accelerate the diffusion of ions into the via. A suitable plating chemistry has not been identified. The application of a low current density for current (DC) plating or pulse and reverse-pulse plating techniques have been used to completely fill a via. Unfortunately, these process techniques are time consuming taking from hours for relatively small volume vias to days for larger vias.
Consequently, successful and efficient methods of forming conductive void free through-wafer vias are desired.


A method and system for determining a billing rate of a telecommunications connection is disclosed. The method and system may be used in a location aware telecommunications system that can determine the location of a telecommunications unit (TU) being used within the system. The geographic location of a mobile unit (MU) is determined, and compared to a list a predetermined subsidized zones. When the MU initiates or receives a call from within a subsidized zone, and the MU is otherwise responsible for paying a predetermined billing rate associated with the call, the predetermined rate is subsidized for at least the portion of the call made while the MU is located within the subsidized zone.

Billing systems for mobile telecommunication units have traditionally been designed on the assumption that all calls were being made while mobile, and that standard land-line telephones would be used whenever possible to garner reduced phone rates. However, cell phone providers have now largely achieved high coverage, and are switching their attention away from building cell infrastructure to plugging coverage holes, increasing revenues from installed infrastructure, and increasing capacity at heavily used cells.
Billing systems in these mobile telecommunications systems presently do not provide an incentive for customers to place or receive calls from a specified geographic location. That is, billing within a telecommunications system is generally ubiquitous. A common billing system in a mobile telecommunications system might charge a mobile user a flat fee per minute of voice airtime. Another common billing system is to charge users a monthly fee, with which is included an allotment of minutes, beyond which the user must pay an additional fee per minute. Yet another common billing system is to allow multiple mobile users to share commonly owned minutes. For example, a husband and wife may each have their own mobile phone, but they share from a common monthly allotment of minutes, and only receive one bill from the mobile telecommunications provider.
As mobile telecommunications systems are becoming more advanced, a mobile unit's geographic location may be used to provide location-based services (LBS). That is, mobile telecommunications devices that are presently available and under development by various companies include Global Positioning System (GPS) capabilities. In addition to GPS, mobile telecommunications service providers may use a network-based geographic location system to determine the position of a mobile unit. Examples of such network-based methods include time difference of arrival (TDOA) systems and angle of arrival (AOA) systems, among others. Mobile Telephones or other mobile telecommunications devices that include GPS capability, or mobile telephones (or other devices) used in a telecommunications system that can use a network-based method to determine its location, are herein referred to as location-enabled mobile units. The advent of location-enabled mobile units provides a new capability around which services may be designed.
Previous known billing systems have included the use of rate zones associated with locations defined by a user. For example, a known system disclosed in U.S. Pat. No. 5,774,802 (Tell, et al.) teaches using rate zones linked to an individual, such as his or her home or business. In this known system, the user defines predetermined sites that he or she frequents and is charged low rates for usage at these locations, whereas other locations have a premium rate charged. This encourages a user to use a mobile phone even when at home if mobile phone rates in the "at home" zone are comparable to rates charged for land line use, or are covered under an unlimited blanket monthly charge, etc. The infrastructure support for a user at home is no different, however, than the support for that same user walking down the street several blocks from home—it is only the rate being charged that differs. What is considered a "home" zone with low rates for one user is generally considered a "mobile" zone with high rates for other users. This may tend to influence people's behavior to increase cell phone usage in generally predictable ways as an alternative to available land-line telephones, and does not involve any changes to infrastructure other than the addition of a location-sensitive billing capability.
Another known location-based billing system is where a mobile telecommunications company agrees to give free or heavily discounted usage to a certain class of users in exchange for permission to erect a cell base station. For example, employees of a company might be given free cell phone use for all calls handled by a cell base station erected on top of that company's building in exchange for the cell phone company being permitted to erect that same base station. This location-based system, however, does not provide an incentive to users to place or receive mobile telephone calls from any location other than from the area covered by the erected cell base station.
In present mobile telecommunications environments, there is no means known in the art to provide an incentive to place or receive a mobile telephone call or use a mobile telecommunications data service from a dynamically specified geographic location defined by someone other than the user. Thus, an improved system is needed that can provide this capability, determine the location of a MU, and charge the user or owner of the mobile unit a selective fee based on the location at which the MU is located.

Method and apparatus for location-sensitive, subsidized cell phone billing


A stylus pen for use as a computer input device includes a pen holder with an associated tip, a chamber defined in the pen holder and filled with a non-compressible fluid, a pressure sensor having a pressure receiving surface that detects pressure in the chamber, and a means for converting a mechanical force applied to the tip to a change in pressure of the non-compressible fluid enclosed in the chamber. In the use of the pen a mechanical force applied to the tip changes the pressure of the non-compressible fluid; and this pressure change is detected by the pressure sensor to produce a change in the output signal from the sensor usable as a computer input.

1. Field of the Invention
The present invention relates to a stylus pen (input device) which is used to input information into information processing equipment, such as a computer.
2. Description of Related Art
A conventional stylus pen, which is used as an input device of a computer, typically displays positional data (i.e., two-dimensional data in a cartesian coordinate system) on an input and output display (i.e., board or panel) and is merely an input device auxiliary to the keyboard. A stylus pen is known which has a switch that is turned ON and OFF in response to mechanical displacement of a nib (i.e., writing tip) or pressure applied to the nib. Such a device is used, for example, to indicate selection of letters, FIGURES, or symbols on a display screen, input necessary operations, input positional data of a coordinate system on the display screen, draw freehand FIGURES or letters, or identify the same, etc. The- pressure applied to the tip of the stylus pen is detected by a pressure sensor which actuates the switch when the detected pressure is above or below a predetermined threshold value.
In recent computers which do not use a keyboard as an input means, it is necessary to provide the stylus pen with a 3-dimensional input function (i.e., an input function using Z-directional data of a cartesian coordinate system in addition to X-Y coordinate data). In such a known stylus pen having an X-Y-Z coordinate data inputting function, color density data is input and the size of a selected FIGURES or letter is changed in accordance with the pressure (i.e., mechanical force) applied to the tip.
In conventional stylus pens which can detect mechanical force, detection is in principle effected in accordance with an output, such as resistance, electrostatic capacity, or magnetic field, which varies depending on the stroke (i.e., linear reciprocating movement) of the tip of the pen. Therefore, in order to increase the output, it is necessary to increase the stroke of the tip. However, it is difficult for a user to use a stylus pen having a large stroke.
Furthermore, the known type of stylus pen in which a mechanical displacement of the tip is directly applied to a diaphragm of the pressure sensor, as mentioned above, does not have a large resistance to shock or overload. Consequently, for instance, if the pen is accidentally dropped, inducing shock to the pen tip, the pen can be easily broken. In practice, during the course of usage of the stylus pen, for example, with a personal computer, the stylus pen is often dropped, etc., jamming the tip of the pen. Accordingly, to increase the life of the pen, it is necessary to provide a stylus pen tip that is capable of withstanding a large degree of external shock.


Methods of forming integrated circuit devices are provided. A first mask layer is formed overlying a first portion of a semiconductor substrate. The first mask layer further overlies a second mask layer overlying a second portion of the semiconductor substrate. The first mask layer overlying the first portion of the semiconductor substrate is patterned to define areas for removal of one or more layers of material interposed between the semiconductor substrate and the first mask layer. Portions of the one or more layers of material exposed by the patterned first mask layer are removed to define elements of the integrated circuit device overlying the first portion of the semiconductor substrate.

Memory devices are typically provided as internal storage areas in computers. The term memory identifies data storage that comes in the form of integrated circuit chips. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address.
One type of memory is a non-volatile memory known as flash memory. A flash memory is a type of EEPROM (electrically-erasable programmable read-only memory) that can be erased and reprogrammed in blocks. Many modern personal computers (PCs) have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in wireless electronic devices because it enables the manufacturer to support new communication protocols as they become standardized and to provide the ability to remotely upgrade the device for enhanced features.
A typical flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating-gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed on an individual basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge on the floating gate.
Memory devices are typically formed as semiconductor devices on semiconductor substrates using semiconductor fabrication methods and may include a memory array portion that includes the array of memory cells disposed on the substrate and a periphery that may include logic devices disposed on the substrate, e.g., of row access circuitry and column access circuitry of the memory device.
For some applications, the layers for forming the memory devices in the memory array portion are formed overlying the substrate. The memory array portion is then patterned to form the individual memory cells. Then, the array junctions are implanted in the array portion. The layers for forming the logic devices on the periphery are formed overlying the substrate and are patterned for forming the logic devices of the periphery. However, this often requires forming a relatively thick mask layer, e.g., greater than about 5000 angstroms, overlying the array portion and the periphery to protect the array portion as the logic devices are defined in the periphery. One problem with using such thick mask layers is that it is hard to maintain critical dimensions of the pattern. Another problem with using such thick mask layers is that the resist tends to topple or fall over due to stresses that form during the formation of the logic devices on the periphery.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternatives for forming peripheries of semiconductor devices.


A method of filling at least one fluid housing with fluid is disclosed. The method includes: (a) arranging at least one fluid housing within a sealable vessel containing a fluid and attached to a vacuum; and (b) activating the vacuum such that air is withdrawn from the sealable vessel and the fluid is drawn into the at least one fluid housing.

Fluid housings, such as lash adjusters, are used in a wide range of applications. These housing typically have at least one internal chamber that contains fluid in order to effectuate some actuating function.
Known lash adjuster assemblies are disclosed in U.S. Pat. No. 10,066,517; DE 200610045017; EP 20150717410; and DE 201510221038, which are each incorporated by reference as if fully set forth herein.
During shipping or pre-installation handling, fluid housings typically inherently lose some fluid or the fluid contained therein develops air bubbles. It is undesirable for fluid housings, particularly used in lash adjuster assemblies, to include aerated fluid because air causes unreliable operation.
Fluid housings can be filled or refilled with fluid prior to installation, sometimes requiring a complex mechanism or process to access critical fluid chambers within the fluid housings. Known methods for filling or refilling fluid housings can require disassembly of the housings, which is time consuming and can damage components within the housings.
One other method for eliminating air in a fluid housing is disclosed in U.S. Pat. No. 9,650,921. This reference requires mounting a fluid housing in a spinning structure which de-aerates the fluid housing via a centrifuge.
It would be desirable to provide a more convenient and efficient method for filling a fluid housing with fluid.

Method of filling a fluid housing with fluid


There is disclosed charge-modified conjugates comprising a targeting protein bound to a therapeutic or diagnostic agent. Charge-modifying a conjugate to cause an acidic shift in the isoelectric point results in prolonged serum half-life upon in vivo administration and is useful to accumulate a therapeutic agent at the target site. Conversely, charge-modification to cause a basic shift in the isoelectric point of the conjugate reduces serum half-life upon in vivo use for diagnostic imaging purposes and results in higher target-to-background ratios.

Prior to describing the background of the invention, it is helpful to define certain terms which are used throughout this specification.
Conjugate: The term "conjugate" applies to any composition that comprises a targeting moiety, such as a biologic response modifier (BRM), (including lymphokines, interferons, erythropoietin, and colony stimulating factors) peptide hormones, antibody or antibody fragment, preferably a monoclonal antibody or monoclonal antibody fragment, and an effector moiety such as a radionuclide, toxin, drug, fibrinolytic enzyme or BRM molecule. The effector moiety can be attached to the targeting moiety either directly or through a linking group, ligand (e.g., bifunctional chelating agent), or a carrier molecule (e.g., albumin, dextran, poly-l-lysine).
Antibody Fragment: An antibody fragment comprises the specific binding regions of the antibody molecule corresponding to the variable and first constant regions on heavy and light chains . Examples of antibody fragments include IF (ab')2, Fab' and Fab fragments. An antibody fragment can also include only the variable regions (Fv). Antibody fragments may also include chimetic molecules wherein constant regions of the antibody are substituted with constant regions of immunoglobulin from a different species.
Immunogenicity: Immunogenicity is a measure of the ability of a targeting protein or therapeutic moiety to elicit an immune response (humoral or cellular), when administered to a host. The present invention is concerned with the immunogenicity of the conjugates and their component parts.
Targeting Protein: In this specification a targeting protein is defined as a protein which is capable of binding to a cellular target or other target site, including but not limited to: antibodies and fragments thereof; lymphokines such as IL-1, 2, 3, 4, 5, and 6; .alpha., .beta., and .gamma. interferon; erythropoietin; colony stimulating factors such as G-CSF, GM-CSF and M-CSF; other biologic response modifiers and peptide hormones such as melanocyte stimulating hormone (MSH), follicle stimulating hormone (FSH), leutenizing hormone (I,H), and human growth hormone (HGH); fibrinolytic enzymes and serum proteins (e.g., low density lipoproteins).
Serum Half-Life: Serum half-life is a time point at which half of the administered amount of targeting protein or conjugate thereof remains in the serum or plasma. Serum determinations over a series of time points can generate a curve which is useful for determining whole body exposure to an agent.
The advent of recombinant DNA and monoclonal antibody technologies has spawned a renewed interest in proteins that may have pharmaceutical applications. These technologies have made possible, for the first time, the large-scale production of substantially purified, homogeneous proteins with little lot-to-lot variation. Protein molecules such as interleukin-2, tissue plasminogen activator, human insulin, atrial naturetic peptide, interferons, monoclonal antibodies to tumor-associated antigens, and to effector cell subsets and fragments and conjugates thereof, have either received marketing approval in the United States or are currently undergoing multisite clinical trials.
In particular, there has been considerable interest in the "magic bullet" approach to cancer therapeutics using monoclonal antibodies conjugated to drugs, toxins, radionuclides and biological response modifiers. More recent efforts have been devoted to the conjugation of cytotoxic or antineoplastic drugs to specific antibodies, such as monoclonal antibodies, to produce conjugates which can selectively target tumor cells while sparing normal tissues.
A large number of different classes of agents have been considered. These agents include beta- and alpha-emitting isotopes, plant and bacterial toxins, and a variety of antineoplastic drugs, including intercalating agents, antimetabolites, alkylating agents and antibiotics. It is desirable to conjugate chemotherapeutic drugs to targeting molecules such as antibodies to decrease their toxicity directed toward normal tissues.
Conjugates of radioisotopes, drugs and toxins, as well as biologic response modifiers, may be potentially useful in the treatment of cancer and autoimmune diseases, and in the abrogation of transplant rejections. Each class of agent conjugated to an antibody provides conjugates having properties which may be useful for the treatment and diagnoses of cancers and other diseases, but each type also has potential drawbacks.
Radiotherapeutic conjugates, for example, are limited by the low dose of antibody that reaches the tumor and by the sensitivity of the bone marrow to the radiation dose absorbed from the circulating levels of antibody. Toxin conjugates are often potent cytotoxic agents, but suffer from rapid serum clearance usually by the liver. This results in poor tumor delivery. Conjugates formed with cytotoxic drugs are usually of lower potency than toxin conjugates. However, cytotoxic drug conjugates are extracted less rapidly by the liver and reticuloendothelial system (RES), resulting in improved tumor delivery properties.
Similarly, molecules such as tissue plasminogen activator (TPA) and interleukin-2 (IL-2) and some of the interferons have characteristic short serum half-lives. This results in decreased bioavailability for target tissue and, in some instances, increased toxicity. The common problem affecting all four types of conjugates is the limitation of the effective dose of the cytotoxic agent (radionuclide, toxin or drug) attached to the antibody or targeting protein that reaches the tumor site or receptor on potential effector cells.
It has been a goal of therapy and diagnostic imaging with conjugates to increase bioavailability of the circulating conjugate to the tumor site(s). Nonspecific binding of the conjugate to normal cells can occur by nonspecific interactions of the antibody, or agents conjugated to the antibody. Nonspecific binding of the antibody components can occur with cells of the RES tissue. An antibody's Fc region can interact with receptors both for Fc and complement components bound to antibody. One method that has been developed to reduce nonspecific interactions of antibody with RES cells is by treatment of the conjugate with an amphipathic molecule, such as an anionic surfactant, as disclosed in co-pending U. S. patent application No. 767,493, filed Aug. 20, 1985. The entire disclosure of this patent application is hereby incorporated by reference.
Another method for increasing bioavailability of an conjugate is disclosed in co-pending U.S. patent application No. 917,176, filed Oct. 9, 1986. The entire disclosure of this patent application is hereby incorporated by reference. As disclosed in U.S. patent application No. 917,176, an irrelevant antibody or conjugate is pre-injected, thereby swamping the mechanism(s) of nonspecific uptake of the pharmaceutically active conjugate.
Another method whereby nonspecific interactions of the conjugates with the Fc receptor can be minimized is to remove the Fc portion of the antibody with a proteolytic enzyme to create an antibody fragment as the targeting moiety of the conjugate. The use of an antibody fragment as the targeting agent still does not eliminate the problems of nonspecific interactions and binding of the conjugate to normal cells. As an example, in order to increase the sensitivity of radionuclide/antibody imaging, investigators have injected radiolabeled antibodies intralymphatically to detect disease bearing lymph nodes. Despite success in animal models, the method has not been of use in man because of nonspecific accumulation of radiolabel in both diseased and nondiseased lymph nodes. To overcome this nonspecificity, antibody fragments were produced and administered by this route for detection of malignant melanoma. Irrelevant, as well as relevant, Fab antibody fragments showed enhanced accumulation in tumor-involved nodes and less uptake in noninvolved nodes following subcutaneous or intralymphatic administration. (Nelp et al., "Preliminary Studies of Monoclonal Antibody Lymphoscintigraphy in Malignant Melanoma," J. Nucl. Med. 28:34-41, 1987). Thus, even antibody fragments can undergo nonspecific interactions when administered by the intralymphatic route.
Nonspecific binding to normal cells by the conjugate can be further reduced by understanding the nature of the nonspecific binding. For example, the nonspecific binding of a radiolabeled antibody is increased by the use of radionuclides/chelate systems in which the chelate is not stable enough not to allow leaching of the radiolabel. For example, DTPA, a commonly used chelate for Indium-111 (In-111), does not bind In-111 avidly enough, allowing the leaching (e.g., 10%/day) from the radioconjugate. Free In-111 can then bind to transfertin and then the transfertin binds to receptors in RES tissues. The use of radionuclides can be improved by the use of more stable chelate systems as well as the use of radionuclides that are rapidly excreted upon dissociation from the conjugate.
Conjugates useful for cancer therapeutic purposes will require multiple administrations. Since the targeting protein of the conjugate is a monoclonal antibody or monoclonal antibody fragment of murine (mouse) origin, a host immune response will be generated against the antibody or the agent conjugated to the antibody. Nonspecific uptake into normal tissues, especially RES tissues, through any reception mediated mechanism, would result in catabolism of the conjugate to peptides by macrophages with presentation to immunocompetent T-cells and B-cells. These peptides could then be recognized by T-cell dependent or independent mechanisms and an antibody response generated. Conjugation of toxins or drugs to antibodies, which increase liver accumulation, would also enhance the immunogenicity of both the antibody and the agent conjugated to antibody. Generation of antibodies to components of the conjugate can lead to further nonspecific uptake of circulating conjugate into certain organs, especially RES tissue. Thus, biodistribution, serum clearance, normal organ accumulation, and excretion all impact the degree of immunogenicity of the conjugate and the ability to give multiple administrations to the patient.
Conjugates are not the only proteins useful for targeted imaging or therapy. Lymphokines like IL-2; .alpha., .beta., and .gamma. interferon, all termed "biologic response modifiers (BRMs)"; as well as TNF (tumor necrosis factor); and TPA (tissue plasminogen activator), share common features of requiring in vivo administration to target intra or extravascular receptors. These proteins can be removed from the circulation by either binding to cellular receptors or by excretion/catabolism. It is difficult to estimate what process accounts for the largest amount of protein removed from the circulation, however, modification of the protein to reduce receptor binding is not feasible since that may also reduce its effect or function. Thus, modification of excretion/metabolism may represent the best means for increasing serum half-life of these agents.
This has been recently addressed for TPA, an agent useful for blood clot lysis and imaging. The serum half-life of TPA was increased by producing a mutant protein by recombinant methods which had glycosylation sites and then producing the mutant in eukaryotic cells (Lau et al., Biotechnology 5: 953, 1987). Lau et al. showed that, in addition to increased serum half-life, lower doses of TPA were required to give the same in vivo fibrinolytic activity as non-glycosylated TPA. Glycosylation has been shown previously with many proteins to effect metabolism and excretion.
Thus, the ability to increase the serum half-life of proteins administered in vivo can have substantial impact on the efficacy and therapeutic index of such proteins. Therefore, a method is needed to reduce the nonspecific uptake and excretion of these protein molecules thereby improving their serum half-lives and thus their availability for target tissues.

Alteration of pharmacokinetics of proteins by charge modification


An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.

Serial communication links, such as serial data interfaces defined by Society of Motion Picture and Television Engineers (SMPTE) standards ST 2081, 2082, and the like, experience high frequency distortion (phase and amplitude) between the transmitter and receiver over a lossy channel. This distortion is manifested at the receiver as inter-symbol interference, such as, a smearing of the transmitted data bits/symbols. Channel equalization is used to counteract inter-symbol interference and other channel induced distortion. Channel equalization is applied using transmission pre-emphasis that pre-distorts a transmit signal and/or as receiver equalization that applies post-compensation for the undesirable frequency effects of the channel.


The invention provides a method and apparatus for end-users to allocate a communication medium locally without requiring a central arbitration device while guaranteeing access to the end-users. The end-users bid for control of an upstream data channel by concurrently transmitting auction data and address data on a first upstream signaling channel and a second upstream signaling channel. An end-user gains control of the upstream data channel when data received from the first and second downstream signaling channels match the auction and address bits. When it is determined that the end-user lost the bid, the end-user backs off from the first and second upstream signaling channels and refrains from bidding until the first and second upstream signaling channels become quiet.

1. Field of Invention
This invention relates to a distributed method and apparatus that allocates a communication medium via efficient arbitration techniques.
2. Description of Related Art
Conventionally, management of a communication medium requires either a centralized head-end to control arbitration among end-users (e.g., telephone stations or personal computers, for example) or end-users randomly competing for access. While centrally controlled arbitration may provide guaranteed access, an end-user must first arbitrate successfully before transmitting end-user information. This management scheme undesirably requires an arbitration overhead time to be added to a data transmission time as well as centralized arbitration hardware to manage the arbitration.
On the other hand, while overhead is avoided by random competition techniques such as Ethernet protocol, end-users are not guaranteed access. Thus, new technology is required to reduce overhead and guarantee access to communication mediums.
The invention provides a method and apparatus for end-users to allocate a communication medium locally without requiring a central arbitration device. The end-users are coupled together via a first upstream signaling channel, a first downstream signaling channel, a second upstream signaling channel, a second downstream signaling channel, a downstream data channel and an upstream data channel. The end-users bid for control of the upstream data channel by arbitrating on the first and second upstream signaling channels. When an end-user desires to gain control of the upstream data channel, both auction data and address data are transmitted concurrently on the first and second upstream signaling channels, respectively. When data received by the end-user from the first and second downstream signaling channels matches the auction and address data, the end-user wins the bid and gains control of the upstream data channel. However, if the data received from the first downstream signaling channels does not match the auction data, the end-user backs off from the first and second upstream signaling channels and refrains from bidding for control of the upstream data channel until the first and second upstream signaling channels become quiet. In all other cases the end-user will continue to bid.
The auction data values may be used to set priorities among the end-users. During a first few auction cycles, each of the end-users transmit auction data values according to a priority preassigned by a head-end, for example. After the first few auction cycles, only the highest priority end-users remain to bid for control of the upstream data channel. For subsequent auction cycles, the remaining end-users generate auction data values randomly to bid for control of the upstream data channel.
The auction data values and the address bits are transmitted concurrently when each of the end-user is bids for control of the upstream data channel. Concurrent transmission of the auction data values and address bits increases the efficiency of the communication medium allocation process. In addition, the end-users may also transmit data on the upstream data channel while transmitting the auction data values and address bits. For this case, the time required to transmit both the auction data values and address bits are overlapped by the data transmission so that if only one user arbitrates for control of the upstream data channel, no overhead is expended for the arbitration process. If data is transmitted on the,: upstream data channel in frames, bidding for control of the upstream data channel may be performed while another end-user is transmitting data on the upstream data channel. Thus, the time required for gaining control of the upstream data channel is completely masked by the data transmission time.

Distributed method and apparatus for allocating a communication medium


A CMOS image sensor with an effectively increased aperture ratio and moreover with improved optical sensitivity, and a method of manufacture of such a CMOS image sensor is provided a first aspect of the invention is an image sensor, has a pixel region 10 in which are formed a plurality of pixels each having at least a photodiode, a reset transistor, and a source-follower transistor; and a peripheral circuit region 12 in which are formed peripheral circuits which process read-out signals read out from the pixel region, a well region PW2 in the pixel region PW1 is formed to be more shallow than a well region in the peripheral circuit region. Also, reset transistors or source-follower transistors are formed in the shallow well region PW2 of the pixel region 10, and a photodiode region PHD2 is embedded below the transistor well region PW2.

Image sensors include CCDs (Charge Coupled Devices) and APSes (Active Pixel Sensors); CMOS image sensors are a representative example of APSes. CCDs are used in video cameras and other devices, and CMOS image sensors are used in inexpensive digital still cameras and other devices. Of the two, CMOS image sensors can be manufactured using CMOS processes and so have low manufacturing costs, and have lower power consumption compared with CCD image sensors, and so are used in portable telephones, portable information terminals, and other battery-driven devices.
CMOS image sensors have a photodiode as a photoelectric conversion element, read out the amount of electric charge accumulated on the photodiode by using a source-follower transistor or similar and capture, the incident light intensity is captured as an electrical signal. CMOS image sensors which have already been commercialized are three-transistor type devices comprising a photodiode, a reset transistor, a source-follower transistor, and a selector transistor. In addition, recently a four-transistor type APS has been proposed, in which a transfer gate transistor is provided between the photodiode and the reset transistor.
Three-transistor type and four-transistor type APSes are for example described in Patent Document 1 (Japanese Patent Laid-open No. 2002-16243 (published Jan. 18, 2002)).
In a four-transistor type APS, a floating diffusion (FD) region, comprising a floating diffusion layer, is provided at the point of contact between the transfer gate transistor and the reset transistor. And, after placing this floating diffusion region at the reset level of the reset transistor, the transfer gate transistor is made conducting, so that charge accumulated in the photodiode region is transferred to the floating diffusion region to cause the potential thereof to change, and this change in potential is captured in a signal line via the source-follower transistor. By detecting the difference between the potential in the floating diffusion region at the time of reset and at the time charge is transferred from the photodiode, a signal with noise eliminated can be captured.
Further, a five-transistor type APS has been proposed, with an overflow drain transistor added in order to prevent photodiode overflow. By controlling the overflow drain transistor, the accumulation start time of the photodiode can be controlled, and a global shutter design can be adopted.
As the number of transistors within pixels increases in this way to accompany enhanced performance, the area ratio of the photodiode region to the pixel area decreases, leading to a decrease in the so-called aperture ratio. In order to alleviate this problem, common use of transistors and other elements by adjacent pixels has been proposed. However, in the case of a four-transistor type APS, three transistors are used in common between adjacent pixels, and so the layout of each pixel is not completely the same, and the unevenness in optical sensitivity among pixels is increased, leading to a decline in image quality.
Further, in order to prevent a decline in aperture ratio, a configuration has been proposed in which the photodiode region is embedded below the transistor formation region within pixels. For example, such a method is disclosed in Patent Document 1.
FIG. 1 is a cross-sectional view of a CMOS image sensor described in Patent Document 1. At a P-type epitaxial layer 52 formed on the P-type semiconductor substrate 51 are formed the gate electrode 55 of a transfer gate transistor TG, the gate electrode 58 of a reset transistor, and the gate electrode 61 of a source-follower transistor, with gate oxide films 56, 63, 61 intervening; on either side of these gate electrodes are provided source and drain regions 57, 59, 60, 62. A high-density N-type photodiode region 53 is formed in the depth direction from the surface of the epitaxial layer 52, and this photodiode region 53 is embedded so as to be extended below the transfer gate transistor, reset transistor, and source-follower transistor. The photodiode region 53 is embedded and isolated from the insulating film 54 at the surface by a high-density P+ region formed at the surface of the epitaxial layer 52, so that the dark current due to a leakage current from this insulating film 54 can be suppressed.
In this way, in the CMOS image sensor described in Patent Document 1, by embedding the photodiode region in superposition below the transistor formation region within a cell, reduction of the aperture ratio can be prevented, and photosensitivity is enhanced.

Image sensor with embedded photodiode region and manufacturing method for same


Programming methods and products are described for developing and producing installation and/or upgrade software for systems where multiple versions of software are available. Information is stored representing the version of software that is being installed, the version of software being installed having an updated feature. Groups of commands enable the transition from a present version of the software to another version of software having another version of the feature. An example of such a feature is deployment of logical volume partitions. A state machine is executed that consults the stored information to access one or more of the groups of commands. The one or more groups of commands is executed to transition from the present version of the software to the version of software that is being installed having the updated feature. If an error occurs during the execution of a group of commands, then recovery information including remediation commands is executed.

Today's data centers store ever-larger amounts of business critical data that must be immediately and continuously available, and highly reliable. Information technologists, storage managers, and administrators of storage systems work continuously to support the increasing software operating system, support, and management requirements of these growing systems. As the capacity, performance, and reliability of systems grows, operating system (OS) and application capabilities and requirements grow concomitantly. System specific OS and/or application upgrades are continually developed to operate, support, and manage the ever more complex systems.
Eventually, after many versions of OS and/or application upgrades have been developed, there are products distributed throughout the world that may have installed thereon one of many different versions the OS and/or applications. Therefore, when it is time to upgrade a product to a current version of OS and/or applications, the upgrade must transition the product from one of many possible old product configurations. It is inconvenient to require a separate product upgrade mechanism for each permutation of old product configuration to new product configuration.

Flexible storage application deployment mechanism


A method for transmitting data, in which a first signature is formed according to a specifiable signature formation method as a function of the data to be transmitted, the first signature is transmitted together with the data a second signature is formed according to the signature formation method as a function of the transmitted data and the first signature is compared with the second signature. To reduce the likelihood of fault masking in monitoring the transmission of the data using signature analysis, a provision is made to invert the data to be transmitted, to form the first signature according to the specifiable signature formation method as a function of the data to be transmitted and of the inverted Data, to transmit the first signature and the data to invert the transmitted data, to form the second signature according to the signature formation method as a function of these inverted data and the transmitted data, and to compare the first signature with the second signature.

From the related art, signature analysis is known as a method for compressing data, which is based on the so-called CRC (cyclical redundancy check) method. As a function of the data to be transmitted, a resulting data word is formed according to a specifiable signature formation method, which constitutes the signature and characterizes the compressed data stream. The likelihood that a correct signature is formed in spite of faults in the data stream is very low and decreases with the data capacity of the signature word. Signatures are used, for example, for securing data transmissions, for monitoring read-only memories in computers and for identifying data streams such as for example of digital hardware signals in the context of testing circuits or data contained in a document. For the related art, reference is made to Abramovici, Miron, et al.: Digital Systems Testing and Testable Design, New York, IEEE Press, 1990.
In hardware, the signature is usually formed sequentially bit by bit with the aid of a linear feedback shift register (LFSR). It is known to implement this sequential signature analysis method in software as well. This method, however, is either very slow due to the sequential method of operation or it requires a relatively high amount of memory space for tables (so-called lookup tables) in order to shorten the computing time. Regarding the related art of such software-implemented sequential methods for signature analysis, reference is made to Williams, R. N.: A Painless Guide to CRC Error Detection Algorithms, Version 3, Aug. 19, 1993, Rocksoft Pty Ltd., Hazelwood Park 5066, Australia, ftp://ftp.rocksoft.com/Qapers/crc v3.txt.
Furthermore, a method for signature formation using a parallel method of operation (data word by data word) is known. This known method operates for example with the aid of a signature register having multiple inputs (MISR, multiple input shift register). The parallel method of operation, for example, allows for 32 bit input data to be processed in one step using a 32 bit processor. A method of this kind is known, for example, from U.S. Pat. No. 5,938,784.
Especially for safety applications in a motor vehicle such as, for example, steer-by-wire or autonomous driving, fault-tolerant and therefore redundant electronic systems are used that have a high demand for secure data exchange between systems, control units, computers and/or processing units. This communication can occur on three levels of communication. A system communication between two or more control units occurs, for example, via a bus system such as, for example, CAN (controller area network), TTCAN (time triggered CAN), FlexRay or TTP/C (time triggered protocol class C). A control unit-control unit communication or a computer-computer communication involving two control units or computers occurs via interfaces such as, for example, RS232, RS422, SPI (serial peripheral interface) or SCI (serial communications interface). A processing unit-processing unit communication occurs within a control unit. Since in these systems, in addition to computing time, data communication time also represents a bottleneck, using the MISR method to safeguard the many data communications is especially advantageous. It reduces to a minimum the computing time required for safeguarding the data communication in the sender and in the receiver.
In the case of the known methods, it may happen—even if it is an extremely rare occurrence—that a faultless signature is formed in spite of faulty data within a message. That is to say that, although the data to be transmitted and the transmitted data do not match each other, the first signature formed via the data to be transmitted and the second signature formed via the transmitted data match nevertheless. This is known as fault masking.

System and method for transmitting data in a motor vehicle


To provide a carbon fiber reinforcement having excellent thermal conductivity and mechanical properties which is manufactured by mixing together two different types of pitch-based carbon short fibers having a ratio of the degree of filament diameter distribution to average fiber diameter of 0.05 to 0.2 and a fiber length of 20 to 6,000 μm which differ from each other in average fiber diameter or by mixing one of them with a pitch-based carbon fiber web to improve dispersibility into a matrix resin or increase the dispersion ratio of the pitch-based carbon short fibers.

High-performance carbon fibers can be classified into PAN-based carbon fibers obtained from polyacrylonitrile (PAN) and pitch-based carbon fibers obtained from pitches. Carbon fibers are widely used in aerospace, construction and civil engineering, and sport and leisure applications, making use of their feature that they have much higher strength and elastic modulus than ordinary synthetic polymers.
While much attention is now paid to methods for making efficient use of energy, typified by energy saving, the generation of Joule heat from high-speed CPU's and electronic circuits is becoming an issue. To solve these, the efficient processing of heat, so-called "thermal management" must be attained.
Although carbon fibers have a higher thermal conductivity than ordinary synthetic polymers in general, the further improvement of thermal conductivity is now under study. Commercially available PAN-based carbon fibers generally have a thermal conductivity lower than 200 W/(m·K). In contrast to this, it is perceived that pitch-based carbon fibers easily attain a higher thermal conductivity than PAN-based carbon fibers.
However, to make carbon fibers actually function as a thermal conductive material, the thermal conductivity of a molded product of the carbon fibers must be improved. To make thermal conduction equal three-dimensionally, a filler which mainly serves to conduct heat must form a three-dimensional network. For example, in the case of a spherical filler which is uniform in size, the network of the filler contained in a molded product behaves like percolation when it is dispersed uniformly though this depends on the dispersion state of the filler. Therefore, in order to obtain a sufficiently high thermal conductivity and electric conductivity, a certain amount or more of a filler must be added. However, it is extremely difficult to disperse a medium and a filler in a concentration higher than a certain level in most cases when a molded product is to be formed. Although a composite material composed of a fabric formed of conventionally used fibers and a matrix has an improved thermal conductivity in the in-plane direction, it is hard to say that its thermal conductivity in the thickness direction is satisfactory because carbon fibers cannot form a network completely.
Under the above situation, many attempts have been made to improve the thermal conductivity drastically. JP-A 5-17593 discloses a thermal conductive molded article having high mechanical strength which is manufactured by impregnating carbon fibers drawn in one direction with graphite powders and a thermosetting resin. JP-A 2-242919 discloses that physical properties such as thermal conductivity of a molded product are improved by the improvement of the physical properties of carbon fibers. However, the improvement of the thermal properties of a molded product is not clear therefrom.
Development is under way from the viewpoint of increasing the thermal conductivity of carbon fibers as described above. However, from the viewpoint of thermal management, the thermal conductivity of a molded product must be high. Then, it is desired that carbon short fibers having a suitable thermal conductivity can be controlled to show optimum thermal conduction in a molded product, or a carbon fiber reinforcement which has a suitable thermal conductivity and can increase the content of carbon fibers in a molded product and a carbon fiber reinforced composite material which has an improved 3-D thermal conductivity and excellent mechanical properties are strongly desired.

Pitch-based carbon fiber, web and resin molded product containing them


Disclosed is a battery module receiving apparatus of a rectangular parallelepiped shape having an inner space with the open front and rear, in which a plurality of battery cell insertion slots are formed at corresponding locations on the upper plate and the lower plate constituting the inner space to erectly insert a plurality of battery cells, and a plurality of heat transfer plate insertion slots are formed adjacent to a plurality of the battery cell insertion slots to erectly insert a plurality of heat transfer plates. A battery pack and a stack-type power storage system may be implemented by inserting a battery module through the front of the battery module receiving apparatus and a battery module thermostat through the rear of the battery module receiving apparatus.

1. Field
The present invention relates to a battery module receiving apparatus and a power storage system comprising the same, and more particularly, to a battery module receiving apparatus for easily receiving and replacing battery cells or modules and a battery module thermostat and for uniformly controlling the temperature between the battery cells, a battery module thermostat, and a power storage system comprising the same.
2. Description of Related Art
A secondary battery has high applicability depending on the product group and excellent electrical characteristics such as high energy density, and thus is commonly used as an electric power source of electric vehicles (EVs) or hybrid vehicles (HVs) as well as mobile devices.
This secondary battery is repeatedly charged and discharged by electrochemical reactions between the components or elements including an electrode current collector, a separator, an active material, an electrolyte, and an aluminum thin-film layer, and thus has a primary advantage of greatly reducing the use of fossil fuels. Also, since a secondary battery does not generate by-products that come with energy consumption, it can improve energy efficiency and is considered environmentally friendly. For these reasons, a secondary battery is gaining attention as an alternative energy source.
A secondary battery as an elementary unit is a battery cell, a plurality of secondary batteries are an assembly or a battery module, and a plurality of assemblies are a battery pack. However, the present invention is not limited in this regard. Unless otherwise stated, a secondary battery stated herein is used to commonly indicate a battery cell, a battery module, and a battery pack.
Recently, with the increasing significance of global issues relating to the exhaustion of energy resources such as fossil fuels, environmental pollution, economically efficient energy use, and the like, a smart grid system has been actively studied to effectively overcome the inequality in power consumption and power production and solve the problems caused thereby, such as, for example, the waste of power when power is oversupplied and power overload when power supply is in shortage. The smart grid system flexibly controls the power supply using a variety of information and communication infrastructures.
In other words, the infrastructure of a smart grid system is configured to store surplus power when power consumption is low and supply the stored power with supply power to consumers when power consumption is high.
In this instance, the smart grid system needs a medium for storing power. As such a medium, a secondary battery or a battery pack is dominantly used.
A power storage system may be used in various fields as well as smart grid systems. For example, a power storage system may be used in EV charging stations that store a great amount of power needed to supply to EVs.
To implement a high capacity power storage system, a battery pack constituting the system includes a considerable number of secondary batteries assembled in various configurations, for example, a tower-type stack battery pack in which battery packs are vertically stacked. However, since a secondary battery is repeatedly charged and discharged by electrochemical reactions inside the battery, the secondary battery cannot avoid the heat generated during charging and discharging. The heat generation dramatically increases during charging and discharging as the capacity is higher.
Heat may cause potential injury or damage to a secondary battery allowing electrochemical reactions, resulting in deterioration in the performance of the battery, which may not guarantee the life of the battery. Furthermore, heat is also known as a fatal factor exerting a bad influence on the safety of the battery, which may cause explosion and the like.
Accordingly, a secondary battery needs cooling during operation. Particularly, in the case of a high-capacity high-integration power storage system, a cooling system is even more necessary to solve the heat generation problem.
However, a conventional cooling system only focuses on cooling an individual battery cell or module rather than the entire power storage system.
Since the conventional cooling system employs an independent operation to individually cool battery cells or modules constituting a tower-type stack battery pack, there is variation in the cooling performance, which makes it difficult to uniformly cool the battery cells or modules. Also, excessive cooling may occur due to overlapping in cooling. To enable individual control, a battery management system (BMS) suitable for individual control and logic for operating such a BMS should be provided, and as a result, a complex air conditioning system along with very low efficiency in the maintenance and repair of the system are posed.
On the other hand, when the temperature of a secondary battery becomes too low at cold start, the performance of a power storage system may reduce. In this case, suitable heating is required. Accordingly, there is a need for a mechanism for properly maintaining the temperature of a secondary battery through suitable cooling and heating and for easily and uniformly controlling the temperature between battery cells, between battery modules, or further between battery packs.

Battery module receiving apparatus, battery module thermostat, and power storage system comprising the same


A method of preventing concurrent or quasi-concurrent commutations of a pair of phase shift modulation (PSM) drive signals of an output bridge stage driving an electrical load includes establishing a threshold level of a programmed current level to be transmitted though the electrical load. The method also includes, if the programmed current level is lower than the threshold level, enhancing a time offset between commutation edges of the pair of PSM drive signals by a minimum time.

In operation, a disk drive controller generates a command to move the head to a certain location, and the command is translated into drive voltage signals applied to the winding of a VCM mounted at one extremity of the movable arm. These drive signals may be linear or switched mode signals. Switched mode drivers may implement different techniques such as, for example, pulse width modulation (PWM), phase shift modulation (PSM) and others, Generally, switched mode drivers may have the advantage of reducing power dissipation in the output transistors that comprise a common output bridge stage to which the motor coil is connected, and thus allow smaller devices and packaging, as compared to linear mode drivers.
The drive signals that are applied to the VCM functioning in a PSM mode are illustrated in FIG. 1. The PSM output power signals OUT1 and OUT2 are driven to a high logic level Vcc (where Vcc is power supply voltage), when PSM input signals are at high digital level, and to a low logic level equal to the ground voltage, when PSM input signals are at low digital level. In a PSM driver, a null output current may be obtained by driving both OUT1 and OUT2 with a 50% duty cycle. The ripple on the output current, Iload, is also shown. The functioning of a PSM driver and its advantages are disclosed in U.S. Pat. No. 5,917,720 to Galbiati.
The main advantage of PSM driver technique may be its outstanding linearity of control under any condition. In fact, as will be appreciated by the person of ordinary skill in the art, the PSM technique may not suffer, like the PWM technique, of the "Ton minimum" problem. The "Ton minimum" problem may not allow good control of the output voltage below a certain value of the duty cycle. Moreover, when PSM drives an inductive load like a VCM, the load current ripple decreases as the load current decreases toward zero, and this may be a benefit when there is need to implement very precise control under relatively low output current levels, as is typically the case in disk drives.
FIG. 2 illustrates a photographic reproduction of a typical disk drive mechanical arrangement. FIG. 2 also illustrates the VCM moving the R/W head carrying arm and the flexible flat cable connection (Flex Cable) carrying the power signal lines (PSM OUT1 and PSM OUT2!) as well as the low level signal lines (R/W head signals), running parallel in the flat cable. However, certain characteristics of the PSM driver for applications, such as, the one illustrated in FIG. 2 and alike, may be found to degrade the signal-to-noise ratio (S/N). These characteristics may manifest especially during precise controlling of the position of the R/W head over the rotating disc, a phase during which the resulting output current that is applied to the PSM driven coil of the VCM is relatively low level.
In fact, when controlling the VCM at relatively low current levels, both PSM drive signals may approach the 50% duty cycle, and, therefore, the PSM commutations may become so close to each other that they may practically be considered concurrent. In these conditions of operation, switching energies may sum and reach a level that may be sufficient to inject switching noise from the VCM power lines into adjacent low level signals lines of the flexible flat cable of electrical connection of the moving arm.
FIGS. 3 and 4 illustrate simulation waveforms when the commutations of the two PSM drive signals are not concurrent and concurrent, respectively. As may be observed in the latter case, the noise due to the two commutations concentrates in a narrowing time zone, and the resulting energy level may increase to a point sufficient to inject noise into adjacent low level signals lines of the flexible cable, corrupting data being transferred through the R/W channel.

Prevention of concurrent PWM or PSM commutations of power signals driving a voice coil motor (VCM) to reduce S/N ratio degradation of low level signal lines of a R/W head