The input speech is segmented using plural grammar networks, including a network that includes a filler model designed to represent noise or extraneous speech. Recognition processing results in plural lists of candidates, each list containing the N-best candidates generated. The lists are then separately aligned with the dictionary of valid names to generate two lists of valid names. The final recognition pass combines these two lists of names into a dynamic grammar and this dynamic grammar may be used to find the best candidate name using Viterbi recognition. A telephone call routing application based on the recognition system selects the best candidate name corresponding to the name spelled by the user, whether the user pronounces the name prior to spelling, or not.

Current speech recognition technology involves the recognition of patterns in acoustic data and the correlation of those patterns with a predetermined set of dictionary entries that are recognized by the system. The speech recognition problem is an extremely challenging one because there are so many different variants. In general, the speech recognizer applies the incoming acoustic data in digital form to a mathematical recognition process that converts the digital data into parameters based on a predefined model.
Conventionally, the model is one that has been previously trained using a sufficiently large training set so that individual speaker variances are largely abated. The model-based recognition process segments the incoming data into elemental components, such as phonemes, that are then labeled by comparison with the trained model. In one form of recognizer, once individual phonemes have been labeled, the phoneme data are compared with prestored words in the system dictionary. This comparison is performed through an alignment process that will accommodate imprecise matches due to incorrect phoneme recognition as well as insertion and deletion of phoneme within a given sequence. The system works on the basis of probabilities. Conventionally, the speech recognizer will select the most probable word candidate that results from the previously described segmentation, labeling and alignment process.
By their very nature, current speech recognizers select word candidates from the predefined dictionary and hence they will only recognize a predefined set of words. This raises a problem, particularly in systems where further decisions are made based on the results of speech recognition. Extraneous noise or speech utterances of words that are not found in the dictionary are often incorrectly interpreted as words that are found in the dictionary. Subsequent decisions based on such incorrect recognition can lead to faulty system performance.
To illustrate the problem, consider a spelled name telephone call routing application. The user is instructed by synthesized voice prompt to spell the name of the person to whom the call should be routed. If the user follows these instructions, the speech recognizer identifies each of the letters uttered and then is able to look up the spelled name by alignment of the sequence of letters with the dictionary. The system then routes the call to the appropriate extension using routing information found in the dictionary. However, if the user utters extraneous information first, such as by pronouncing the person's name prior to spelling, the recognition process is highly likely to fail. This is because the recognition system expects to receive only a sequence of uttered letters and will attempt to "recognize" the spoken name as one or more letters. The conventional system simply is not equipped to properly segment the incoming acoustic data, because the underlying model on which the system is built assumes a priori that the data are all equivalent units (spoken letters) that are useful or meaningful to the system.
The present invention solves the aforementioned problem through a speech recognition system that employs and integrates multiple grammar networks to generate multiple sets of recognition candidates, some based on a model that assumes the presence of extraneous speech, and some based on a model that assumes the absence of extraneous speech. The results of both models are used to make the ultimate recognition decision, relying on the respective match probability scores to select the most likely candidate.
According to one aspect of the invention, the acoustic speech data are separately processed using different first and second grammar networks that result in different segmentation of the acoustic speech data. In this way, the system will extract speech that has utility from speech that does not. For each grammar network, a plurality of recognition candidates are generated. The preferred embodiment generates the N-best candidates using a first grammar network and the M-best candidates using the a second grammar network, where N and M are integers greater than one and may be equal. The first and second plurality of recognition candidates (N-best, M-best) are transformed based on a least one set of a priori constraints about the speech that has utility. The transformation may comprise, for example, matching the candidates to a dictionary of spelled names that are recognized by the system. The recognition decision is then based on the transformed recognition candidates.
As will be more fully explained below, the invention splits the acoustic speech data into two or more paths that are each handled differently. One path is processed using a first grammar network based on the assumption that only useful utterances (e.g., letters) are supplied. Another path is processed using a different grammar network that assumes extraneous, nonuseful speech precedes the useful speech. The different grammar networks thus result in different segmentation of the data.
The recognition candidates generated by each path may each be scored according to how well each candidate matched the respective models. Rather than requiring the two paths to compete at this stage-in order to select the single candidate with the highest score-the two sets of recognition candidates are maintained separate. At this stage, the recognition candidates represent the N-best and M-best letter sequence hypotheses. To select which hypothesis is the best candidate, both sets are separately matched to the dictionary of all names that are recognized by the system.
The dictionary is, in effect, a collection of a priori constraints about the speech that will have utility to the system. Thus certain letter sequence hypotheses may be scored less probable because those letter sequences do not well match the letter sequences stored in the dictionary. The presently preferred embodiment uses the N-best and M-best letter sequences to select the N-best and M-best names from the dictionary. Thus contributions from both paths are included in the decision making process. Finally. the N-best and M-best sets of names may be combined to form a reduced set of dictionary candidates to which the input utterance is applied.
This reduced size dictionary can be used to build a dynamic grammar that is built from the N-best and M-best name candidates. This dynamic grammar will tend to favor one set of candidates or the other, depending on whether the input utterance contains extraneous speech or not. If extraneous speech is present, the grammar network designed to identify and reject the extraneous speech will tend to produce better recognition results. and those results will be reflected as the better candidates in the dynamic grammar that is constructed from the N-best and M-best name candidates. On the other hand, if no extraneous speech is present, the other grammar network will produce better recognition results, and it will be better reflected as the better candidates in the dynamic grammar.
Once the dynamic grammar is constructed, the input acoustic speech data may be processed using a recognizer based on the dynamic grammar to extract the single most probable name candidate as the recognized name. The recognized name is then used to access a suitable database for routing the telephone call appropriately.

Speech recognition system employing multiple grammar networks

Matsushita Electric Industrial Co., Ltd.


Fluoride catalyzed rearrangement reactions of polymeric silsesquioxanes [RSiO1.5]n involve reacting at least one silsesquioxane material with a catalytic amount of an organic fluoride at a temperature ranging from about −50° C. to about 120° C. thereby forming a reaction mixture for a period ranging from 60 minutes to 48 hours. To the reaction mixture, a quenching agent is added to remove fluoride from the reaction mixture. A silsesquioxane cage compound can be isolated from the reaction mixture using a precipitation or other extraction process.

Polymer properties are dictated by a combination of monomer structure, chain length and processing. Monomer structure can often determine how the polymer coils, crystallizes, forms electrostatic or hydrogen bonds and of course dissolves. If the monomer unit provides extended conjugation along the polymer backbone, the polymer may offer conducting, semiconducting, emissive or light absorptive properties of use in organic electronic and photonic applications. Rigid monomers lead to polymers with excellent mechanical properties and/or liquid crystallinity. Finally monomer structure can also dictate miscibility with other polymers.
Chain length will normally dictate the glass temperature (Tg), diffusion rates, viscosities, CTEs, extents of mechanical crosslinking and for short chains, the melting temperature. Processing provides control of chain-chain interactions on a molecular scale as a means of controlling global properties through control of molecular alignment providing for example, toughness, transparency, conductivity etc. It is well recognized that specific polymer properties arise from specific types of monomers, degrees of polymerization and processing. Simply said, "One size does not fit all." There are certain types of polymer (oligomer) systems that may offer much more tailorability than others such that "One size fits many." One such system encompasses the family of compounds called silsesquioxanes (SQ) as illustrated in FIG. 1. Because of the breadth of their properties, silsesquioxanes are of considerable interest to both the academic and industrial communities, having been the subject of numerous reviews in the last 25 years.
To illustrate, random structured silsesquioxanes are often called T resins and offer a number of useful properties centered about their excellent adhesion and high temperature stability. In one form, with R as H or CH3, they are used as interlayer dielectrics processed either by spin-on or vapor deposition methods. They are also called organic silicates. In other forms they are used to form molds, as clear coats for a wide variety of substrates and are a major component of silicone based caulks for example.
Polyhedral silsesquioxanes, such as the T8 octasilsesquioxane "cubes" [RSiO1.5]8 (FIG. 1), represent a versatile class of highly symmetrical three-dimensional organosilicon compounds with well-defined nanometer size structures. The combination of a rigid silica core and a more flexible, modifiable organic shell make these compounds useful as platforms for assembling hybrid nanocomposite materials with properties intermediate between the properties of ceramics and organics.
Silsesquioxanes have been used in recent years to: (1) model catalytic surfaces, (2) generate new catalysts and (3) novel porous media, and serve as (4) NMR standards, and (5) encapsulants. The decameric T10 and dodecameric T12 cages are frequently formed alongside the T8 cube, albeit in lower yields, and their derivatives often exhibit chemical, thermal, and mechanical properties parallel to those of T8 derivatives.
Cubic or T8 silsesquioxanes are typically prepared via acid or base-catalyzed hydrolytic condensation of trifunctional organosilanes or by chemical transformation of the pendant groups on pre-existing cages. Since their initial discovery in 1946, there have been numerous studies on the synthesis of polyhedral silsesquioxanes. However, no universal preparative procedures have been established.
The R groups are selected from wide variety of aliphatic and aromatic functional groups, offering considerable potential to control the properties of any oligomeric, polymeric, and/or organic/inorganic hybrid nanocomposites that could be made from them.
In general, most of the work reported for SQs centers on monofunctional materials with seven inert R groups (typically R=iBu, cyclopentyl, cyclohexyl and occasionally phenyl) and one reactive group. There are only a few examples of difunctional octameric or heptameric partial or whole cages and even fewer examples of polymers (oligomers) that contain the SQ as part of the main chain. The reason is that isolation of these types of compounds is very difficult and there are only a few reports on their use in the production of linear polymers.

The Regents of the University of Michigan


A framework based Java naming and lifecycle services system includes a Moniker class which universally identifies an instance of any object model, whether the instance exists or not. Moniker objects instantiated from the Moniker class operate with a set of directory service classes and object adapters to create a directory service framework and a mechanism for connecting the directory service framework to existing directory services. A set of runtime classes provide “in process” services for objects. For example, the Moniker class is automatically substituted for a client reference when the underlying object instance is streamed or persisted. In accordance with one embodiment, life cycle services are provided by associating a predefined policy with each Moniker object, which policy specifies how and when life cycle services should be performed. Remote objects are then created or bound in accordance with these policies which eliminates the need for the client to directly incorporate life cycle services code into its logic.

Software is increasingly becoming a major portion of cost associated with computer systems because it is very "labor-intensive." Some of this cost is due to the effort involved in writing and debugging programs, other costs involve maintaining programs after they have been written. Accordingly, considerable effort has been expended in order to reduce the time and costs involved with writing, debugging and maintaining moderate and large software programs. Much of this effort has been related to developing programming languages and programming techniques which will allow programmers to build on or "reuse" programs and code segments that have been written by others.
Until very recently, software programming was heavily dominated by an approach referred to as "structured programming." Common software programming languages used in this approach were, and remain, BASIC, FORTRAN, and PASCAL. These are considered "higher order" languages that are written in human readable code and ultimately translated into machine or computer readable code by a compiler. Typically, structured programs have consisted of a combination of defined variables of specific data types, e.g. integer, real, and character, and a complimentary set of functions or routines which operate on these variables. Often, a program would include sub-routines which are smaller routines within a program or larger routine that carry out certain operations, e.g. printing data in a given output format. The emphasis to this approach was inputs—functions—outputs and they were often represented as flowcharts by the designers, which logically represented how the program functioned and branched into different functional paths. As an increasing number of programs became large (tens of thousands of lines of code and above) structured programs became increasingly complex and difficult to write, troubleshoot and maintain.
Flowcharts became unwieldy and the tracking of errors through permutations of variables, lengthy code, and a wide variety of program branches was time and cost intensive and often produced less than adequate results. Consequently, a new approach to software programming called Object-Oriented Design (OOD) or Object-Oriented Programming (OOP) emerged and has gained increasing popularity among software developers. OOP promised greater reuse and maintainability than its structured programming predecessor because of an emphasis on well-defined and self contained objects, rather than the structured programming emphasis on a proliferation of relatively loosely-related data manipulating functions and subroutines.
Object Oriented Programming techniques involve the definition, creation, use and destruction of "objects." These objects are software entities comprising data elements, or attributes, and methods, or functions, which manipulate the data elements. The attributes and related methods are treated by the software as an entity and can be created, used and destroyed as if they were a single item. Objects are defined by creating "classes" which are not objects themselves, but which act as templates that instruct the computer how to construct the actual object. A class may, for example, specify the number and type of data variables and the steps involved in the methods which manipulate the object's data.
Object-Oriented Programming languages include C++ and Java, as well as other languages. Each language has an express or implied "object model." Generally speaking, an object model is a unifying set of rules that describe object structure, object life cycle, and inter-object communication. Object structure relates to the physical layout of objects in memory, while object life cycle refers to how applications create and destroy objects. Inter-object communication refers to protocols by which objects communicate with one another. Object models are useful in contexts where all objects in a given system need to conform to a given protocol governing these parameters.
In addition to object-oriented programming languages, code sharing has been facilitated by distributed object systems. In a distributed object system a client object can invoke methods in a server object as if the methods were local to the client object. The server object may be located locally with respect to the client object or may be remote and accessible by a network. Such distributed object systems offered the promise of allowing objects written by different programmers to easily communicate.
However, initially, the promise of reusability and economy of OOP and distributed object systems was not realized. Standards were not in place to insure interoperability of objects or cross-platform interoperability and the proliferation of objects conforming to different object models prevented significant reuse, as originally envisioned. This problem became even more evident when the Internet and the World Wide Web (Web) emerged as widely-used resources and ensured that a wide variety of platform configurations would attempt to access and use commonly-available information on the Internet. As a result, applications designed to operate on the Web used languages designed specifically for the Web, such as hyper-text mark-up language (HTML) as a way to provide a static, but commonly useable, form of coded information while object-oriented programming was applied in other applications. But the problem of cross-platform interoperability persisted and grew as it became more desirous to add dynamic capability to the Web and as many organizations were using multiple platforms and grappling with interoperability internally.
In order to solve these problems, a number of common object models were developed for use with distributed object systems. These models are based on a well-known application programming interface (API), predefined life cycle steps and a homogeneous distributed object model. Such models typically included some type of interface definition language which allows objects written in different languages to have standardized interfaces so that the objects will be able to communicate. Some object models also include predefined mechanisms for transporting communications between remotely-located objects which have interfaces that conform to their specifications. Finally, some object models have also included naming services which allowed client objects to locate server objects when the server objects were located remotely.
Even with such systems the promise of reusability and economy of OOP and distributed object systems has still not been realized because there are a myriad of object models commonly in use, including RMI, CORBA, BOSS, San Francisco, PDO, OpenDoc, COM/DCOM and proprietary object models. There are a further group of persistent store protocols including RDBMS, flat files, ODBMS, ODBC, JDBC, CICS/IMS and proprietary protocols. Finally, there is a proliferation of naming services including LDAP, DNS, X.500, StreetTalk, DCE CDS, URL, Lotus Address Book, Novel NDS, Whois++, SOLO, IDS and various proprietary systems. Therefore, the environment with which client applications and the program developers which develop and support them must work is chaotic.
Consequently, a need exists for a method and apparatus for providing distributed object systems with consistent naming and life cycle policies. A further need exists for providing such services without requiring the users to completely complete their existing systems.

Method and apparatus for providing protocol independent naming and life cycle services in an object-oriented system

International Business Machines Corporation


A robot with a safety fence includes: a base; a movable part having a base end supported to the base so as to be rotatable about a first axis, and a tip end performing operation on an operation target; and a safety fence rotated about the first axis together with the movable part, and disposed on a rear side opposite to a front side of the robot with a safety fence where the tip end of the movable part performs operation. The safety fence is disposed in a position radially closer to the first axis than the farthest distance the tip end of the movable part travels from the first axis on the front side, and a position radially farther away from the first axis than the farthest distance a portion of the movable part travels from the first axis during operation, on the rear side.

Heretofore, a robot system including a safety fence disposed in a position surrounding a robot has been known (for example, see PTL 1). In the robot system described in PTL 1, the position of the robot and the position of a virtual safety fence set as a virtual region are set in advance to prevent entry of the robot beyond the virtual safety fence.

Robot with safety fence and robot system


An alkaline production system comprising an electrochemical unit comprising a hydrogen-oxidizing anode, a cathode compartment comprising a cathode and a hydrogen delivery system configured to deliver hydrogen gas to the anode, wherein the unit is operably connected to a carbon sequestration system configured to sequester carbon dioxide with the cathode electrolyte; and methods thereof. In another embodiment, a system comprising a hydrogen-oxidizing anode in communication with a cathode electrolyte comprising bicarbonate ion; and an hydrogen delivery system configured to deliver hydrogen gas to the anode; and methods thereof.

In many chemical processes an alkaline solution comprising, e.g., hydroxide ions and/or carbonate ions and/or bicarbonate ions is utilized to achieve a chemical reaction, e.g., to neutralize an acid, or buffer the pH of a solution, or precipitate an insoluble hydroxide and/or carbonate and/or bicarbonate from a solution. An alkaline solutions can be produced by an electrochemical system that converts an aqueous salt solution to the alkaline solution and an acid as described in the above-referenced US Provisional patent applications, herein incorporated by reference in their entirety. However, as the process is very energy intensive, a large amount of electrical energy is consumed; also, large amounts of salt and water are consumed. Consequently, lowering the energy and material consumed are very desirable.

This patent is subject to a terminal disclaimer.

Low-voltage alkaline production using hydrogen and electrocatalytic electrodes


The present invention is for a grinding device, such as a surface grinding disc or an annular grinding wheel, constructed from a plurality of abrasive segments arranged in an array thereon, wherein the plurality of abrasive segments are embedded in a matrix composition, and wherein the device is abapted to perform a “dry machining” operation. The abrasive segments may be resin bonded or vitrified and may include diamond or other superhard or superabrasive particles, such as, for example, cubic boron nitride (“cBN”), dispersed therein. Both the abrasive segments and the matrix composition include a dry lubricant, such as hexagonal boron nitride, molybdenum disulfide or graphite, dispersed therein. The abrasive segments further include a melt phase metal composition, such as bronze or other copper alloys, to aid in heat dissipation.

The present invention relates to grinding devices, such as grinding discs and wheels. More particularly, the present invention relates to grinding devices, such as grinding discs and wheels, wherein the grinding device is adapted to perform "dry machining" operations.
In the machining of substantially planar workpieces, such as brake rotors, power steering pump rings and rotors, valve plates, coil spring ends, and the like, it is known to pass the workpiece along the radial "face" surface of a surface grinding disc. For example, U.S. Pat. No. 6,419,564 to Herrman, et al., teaches a surface grinding machine and a surface grinding disc used therewith to machine substantially flat workpieces. In particular, Herrman '564 teaches a segmented grinding disc constructed from a circular base to which a plurality of abrasive pieces are secured in a predefined array. The abrasive pieces are arranged so as to define spaces therebetween for the purpose of allowing cooling fluids to flow over, around, in between and away from the abrasive pieces, thereby flushing swarf from the abrasive pieces and facilitating heat dissipation. According to one aspect of the present invention, it is desirable to provide a grinding device, such as, for example, a surface grinding disc or an annular grinding wheel, wherein the device includes a plurality of abrasive segments arranged in an array thereon (or therearound, as the case may be).
Herrman '564 also teaches that the abrasive pieces may include diamond or superabrasive particles, such as cubic boron nitride ("cBN") dispersed therein for reasons which are obvious to those of ordinary skill in the art However, it is customary for machining operations being performed with such a superabrasive grinding device to require a flow of coolant to be directed thereover, as described in Herrman '564, for the purposes discussed therein. For reasons that will be obvious to one of ordinary skill in the art, such "wet machining" operations are undesirable. It is desirable, therefore, to provide a grinding device, such as, for example, a surface grinding disc or an annular grinding wheel, constructed from a plurality of abrasive segments arranged in an array thereon, wherein the abrasive segments include superabrasive particles dispersed therein, and wherein the device is adapted to operate in a "dry machining" environment, that is, for example, without the use of more than a nominal quantity of coolant or other lubricant.
The efficiency of conventional dry machining operations is limited by the rate at which workpiece material may be removed therefrom without imparting workpiece failure or damage, such as, for example, burning. This is because coolants serve an important function of dissipating heat and dry machining is—by definition—machining in a dry or near-dry environment (i.e., without the use of coolants). It is desirable therefore to provide a grinding device, such as, for example, a surface grinding disc or an annular grinding wheel, constructed from a plurality of abrasive segments arranged in an array thereon, wherein the plurality of abrasive segments are embedded in a matrix composition adapted to enhance heat dissipation.
It is desirable furthermore to provide a method of dry machining workpieces wherein the method provides a grinding device, such as, for example, a surface grinding disc or an annular grinding wheel, constructed from a plurality of abrasive segments arranged in an array thereon, wherein the plurality of abrasive segments are embedded in a matrix composition adapted to enhance heat dissipation.
It is also desirable to provide a method of dry machining workpieces with increased machining efficiency, that is, for example, by increasing workpiece material removal rates.
It is even furthermore desirable to provide a method of dry machining workpieces constructed from hard materials, which typically are difficult to dry machine using known dry machining methods and devices.


A test pattern generating method for a logical circuit comprises selecting failures to be detected in the logical circuit on which a test pattern is generated, selecting a target failure from all failures selected, generating a test pattern for detecting the target failure, performing a failure simulation on all selected failures by the generated test pattern, selecting the target failure from the failures not detected by the test pattern, and deleting a redundancy test pattern, which has a low failure detection rate, from the test patterns for detecting all failures.

1. Field of the Invention
The present invention relates to a method for generating a failure detection test pattern for detecting a failure in a logical circuit and a test pattern generating system, and more particularly to a failure detection test pattern generating method which can shorten time required for the pattern generation and reduce the test pattern number and a test pattern generating system.
2. Description of the Related Art
In a conventional generation of the above type of test pattern, "test pattern generating process" for generating a test pattern to detect a single target failure which is determined in a circuit diagram and "failure simulation" for determining a failure which is detected by a given test pattern are performed.
Such a conventional test pattern generating method has disadvantages that when a test pattern for obtaining a high failure detection rate is generated, the possibility of increasing the total number of test patterns generated (test pattern length becomes long) becomes high and it is hard to shorten the test time.
In order to remedy the above disadvantages, for example, Japanese Patent Laid-Open Publication (Kokai) No. Heisei 5-341011 proposes a test pattern generating method which performs the test pattern generation and the failure simulation in combination. This test pattern generating method determines a single failure as a target failure, and when a pattern for detecting the target failure is obtained in multiple numbers by the test pattern generation, selects several patterns from the obtained patterns, performs the failure simulation on respective patterns, and determines a pattern, which can detect most failures at the time, among the obtained results as the test pattern with respect to the target failure, thereby enabling to decrease the total number of test patterns (test pattern length).
Now, description will be made of the test pattern generating method described in the above-described Japanese Patent Laid-Open Publication No. Heisei 5-341011 with reference to the flowchart of FIG. 6 and the circuit diagram of FIG. 7 which shows an example of the logical circuit on which the test patterns are generated. The logical circuit of FIG. 7 comprises a first AND gate G701 having inputs i2, i3 as input, a second AND gate G703 having a reverse signal of the input i3 from an inverter G702 and an input i4 as input, an OR gate G704 having the first and second AND gates G701, G703 as input, and a third AND gate G705 having an input i1 and the output of the OR gate G704 as input.
First, a failure table 800 is prepared as shown in FIG. 8 in step 601. It is judged in step 602 whether or not all failures are detected, and if not, a single failure target is taken from undetected failures and determined as a target failure (step 603). First, a 0 degeneracy failure at an output f1 (stuck-at-0, hereinafter referred to as "f1/sa0") of the gate G705 is determined to be a target failure.
It is judged in step 604 whether or not the failure f1/sa0 has been detected, and if not, a test pattern for detecting the failure f1/sa0 is generated in step 605. In the logical circuit shown in FIG. 7, test patterns by which the failure f1/sa0 is detected are four of (i1, i2, i3, i4)=(1, 0, 0, 1), (1, 1, 0, 1), (1, 1, 1, 0) and (1, 1, 1, 1).
Since multiple test patterns are generated (step 606), the respective test patterns are subjected to the failure simulation (step 610), and respective failure detection numbers are recorded (step 611).
Then, a test pattern (1, 0, 0, 1) which has the most failure detection numbers is selected (step 612), and the failure table 800 is renewed (step 608).
A 1 degeneracy failure at the output f1 (stuck-at-1, hereinafter referred to as "f1/sa1") of the gate G705 is taken from the undetected failures and determined as a target failure (step 603). It is judged in step 604 whether or not the failure f1/sa1 has been detected, and if not, a test pattern for detecting the failure f1/sa1 is generated in step 605.
Test patterns by which the failure f1/sa1 is detected are 12 of (i1, i2, i3, i4)=(0, 0, 0, 0), (0, 0, 0, 1), (1, 0, 1, 0), (1, 0, 1, 1), (1, 1, 0, 0), (0, 0, 1, 0), (0, 0, 1, 1), (0, 1, 0, 0), (0, 1, 0, 1), (0, 1, 1, 0), (0, 1, 1, 1) and (1, 0, 0, 0). Since multiple test patterns are generated (step 606), the respective test patterns are subjected to the failure simulation (step 610), and the respective failure detection numbers are recorded (step 611).
Then, a test pattern (1, 0, 1, 1) which has the most failure detection numbers is selected (step 612), and the failure table 800 is renewed (step 608).
According to the flowchart shown in FIG. 6, the above-described respective steps are repeated until all failures are detected (step 602).
By the above process, the conventional test pattern generating method can detect a 0 degeneracy failure (sa0) and a 1 degeneracy failure (sa1) at inputs and outputs f1 to f11 of all gates by five test patterns (i1, i2, i3, i4)=(1, 0, 0, 1), (1, 0, 1, 1), (0, 0, 0, 1) and (1, 1, 0, 0) as shown in FIG. 8.
The above-described test pattern generating method needs to generate multiple test patterns with respect to a single target failure and, when the multiple test patterns are obtained, needs to perform the failure simulation on all the test patterns, so that it has a disadvantage that the time required to perform the failure simulation becomes enormous. Especially, large-scaling of semiconductor ICs and expansion of the failure simulation (namely, prolonging of the test pattern generating time) are serious issues.

Test pattern generating method and test pattern generating system


A method for restoring ink conductivity of ink in an ink reservoir comprises detecting an ink conductivity of an ink volume in an ink reservoir, and comparing the detected ink conductivity to a predetermined ink conductivity operational range. A flush routine is performed in response to the measured ink conductivity being outside of the predetermined ink conductivity operational range. The flush routine includes: disabling ink supply operations to the ink reservoir; emptying the ink reservoir of ink; refilling the ink reservoir with ink; measuring an ink conductivity of an ink volume in the refilled ink reservoir; and comparing the detected ink conductivity to the predetermined ink conductivity operational range. The imaging device is returned to a normal operating mode in response to the measured ink conductivity being within the predetermined ink conductivity operational range after a flush routine has been performed.

Solid ink or phase change ink printers conventionally receive ink in a solid form, either as pellets or as ink sticks. The solid ink pellets or ink sticks are typically inserted through an insertion opening of an ink loader for the printer, and the ink sticks are pushed or slid along the feed channel by a feed mechanism and/or gravity toward a heater plate in the heater assembly. The heater plate melts the solid ink impinging on the plate into a liquid that is delivered to a melt reservoir. The melt reservoir is configured to maintain a quantity of melted ink in liquid or melted form and to communicate the melted ink to one or more printheads as needed.
In order to prevent the ink storage and supply assembly of the imaging device from exhausting the available supply of ink, the reservoirs of the ink storage and supply assembly may be provided with ink level sensors. Recently, ink level sensors have been developed that enable a continuous measurement of the level of ink in the reservoirs of the printer. These ink level sensors include a lower probe positioned near a lower portion of the reservoir, an upper probe that extends upward form the lower probe toward the top of the reservoir, and an outer probe. To detect the level of ink in an ink reservoir, an AC signal is driven to the outer probe. The ink in the reservoir conducts the AC signal to the lower probe and to the upper probe. A current flow is detected from the outer probe through the ink to the lower probe and from the outer probe through the ink to the upper probe. Assuming that the ink temperature and conductivity remains relatively consistent, a substantially constant current flow is detected via the lower probe. Varying levels of current flow are detected via the upper probe as more or less of the upper probe's surface area is covered or uncovered in ink. A continuous measurement of the height of ink in the ink reservoir may then be determined by comparing the varying current flow in the upper probe to the constant current flow in the lower probe.
The ink level sensor described above is robust to variation in ink conductivity that may result due to normal variation in the manufacturing processes of the ink and/or due to natural variation in the ink components. For example, due to variation inherent in the manufacture of ink from raw components, a moderate variation in the conductivity of the ink may be expected from batch to batch and accounted for accordingly. However, if ink having a conductivity that exceeds the range of reliable operation of a level sensor enters the reservoir, the level readings generated by the level sensor for that reservoir may not be accurate or the level sensor may fail altogether resulting in various printhead failures, including introduction of air which causes jetting failure, and weeping of jets which can contaminate the drum.

Ink conductivity recovery method for an imaging device


An auto optical focus detecting device of a camera comprises a center zone being located in a center of a view finder of a camera body; at least two peripheral zones being located in the view finder, one of the two peripheral zones center zone and the other being located in the left-hand side; the camera body containing a center auto focus optical system and at least two peripheral auto focus optical systems; the center auto focus optical system having a zone corresponding to the center zone, the zone being substantially conjugate with the center zone; the peripheral auto focus optical systems, respectively, having a substantially conjugate zone corresponding to the peripheral zone, each zone being substantially conjugate with the peripheral zone; a photographic lens being attached to the camera body, an exit pupil of the photographic lens being looked through the center zone of the center auto focus optical system, at least two aperture zones being defined on the exit pupil by the at least two peripheral auto focus optical systems, each of the aperture zones being looked through the peripheral zone, at least one of the two aperture zones being located at an upper side away from a central portion of the exit pupil and the other being located at a lower side away from the central portion; the center auto focus optical system and the two peripheral auto focus optical systems, respectively, having at least one photoelectronic device for producing an output signal; and the output signal produced by the photoelectronic device being adapted to move the photographic lens automatically, thereby to bring the camera to be in focus.

There has been known an auto optical focus detecting device of a camera having an auto focus optical system. FIG. 1 is a schematic view showing an optical system of an auto optical focus detecting device of, for example, a single-lens reflex camera which has the auto focus optical system. In the figure, 1 denotes a photographic lens, 2 a subject to be photographed, 3 a view field mask, 4 a condenser lens, 5 a diaphragm mask, 6 and 7 a separator lens as an image splitting optical element, and 8 a CCD as a image receiving element. The view field mask 3, the condenser lens 4, the diaphragm mask 5, the separator lenses 6 and 7, and the CCD 8 are integrally modulated as one unit and constitute an auto focus optical system 9.
In this auto focus optical system 9, the view field mask 3 is disposed in the vicinity of a film equivalent plane 10. The film equivalent plane 10 is in a position optically conjugate with the subject 2 to be photographed through the photographic lens 1. A well focussed image 11 of the subject 2 is formed on the film equivalent plane 10 when the photographic lens 1 is in focus. The condenser lens 4 and the diaphragm mask 5 have the function of splitting the photographic light passing on both right and left sides of the photographic lens 1. The separator lenses 6 and 7 are in a position optically conjugate with the photographic lens 1 through a condenser lens 4.
The separator lenses 6 and 7, as shown in FIG. 2, are disposed in the horizontal direction. Further, the separator lenses 6 and 7 face imaginary opening areas 14 and 15 of an exit pupil 13 of the photographic lens 1 through a zone 12 located in a position optically conjugate with a center zone of a finder as will be described. The separator lenses 6 and 7 intake a bundle of rays passed through the opening areas 14 and 15. The image 11 formed on the film equivalent plane 10 is reimaged as images 11' in two areas on the CCD 8.
A distance between the images 11' well focussed (see FIG. 3(a)) is represented by l.sub.o as shown in FIG. 4. When the photographic lens 1 is focussed in a position in front of shown in FIG. 3(b), the distance between the images 11' becomes less and, as a result, the distance between signals S corresponding thereto becomes less than the distance l.sub.o. On the contrary, when the photographic lens 1 is focussed in a position behind, the focal point of the afore-mentioned well focussed image as shown in FIG. 3(c), the distance between the images 11' becomes greater and, as a result, a distance between signals S corresponding thereto becomes greater than the distance l.sub.o. Since the distance between the images 11' is changed in proportion to a defocussing amount of the photographic lens 1, in the conventional auto optical focus detecting device of a single-lens reflex camera, a distance between images of the CCD 8 is detected and the signals are arithmetically processed, and the photographic lens 1 is moved to the focal position with reference to the focussing direction and defocussing amount of the photographic lens 1. And, as shown for example in FIG. 5, if the optical focus is found by framing as such that a desired subject 2 to be photographed is located in the center zone 17 arranged at the center of the finder 16, the photographic lens 1 is automatically brought to a focussing state. If a photograph is taken in the foregoing state, a well focussed photograph can be obtained.
In this conventional auto optical focus detecting device of a single-lens reflex camera, since the zone is located in the center of the finder 16, a desired subject 2 will be positioned in the center of an obtained photograph unless an adequate arrangement is made. However, there are some instances where a desired subject 2 is preferably positioned in the peripheral area of a photograph instead of the center thereof. To this end, thereofore, in the conventional single-lens reflex camera, a focus lock mechanism is provided. That is, the subject 2 to be photographed is positioned in the center of the finder 16 to automatically find the distance to the subject 2. In that state, the focus is locked. If a photograph is taken in the framing as shown in FIG. 6, a photograph can be obtained in which a desired subject 2 is positioned in the peripheral area.
However, in this conventional auto optical focus detecting device of a single-lens reflex camera, the subject 2 must first be positioned in the center of the finder 16. Then, the photographic lens 1 must be moved to a focussing state. In that state, the focus must be locked to fix the photographic lens 1. Then, the framing must be performed once again. Only thereafter, a photograph can be taken. Therefore, much time and labor are required before the camera is ready to take a photograph.

Auto optical focus detecting device and eye direction detecting optical system


The present invention provides a method for generating a point-in-time restoration of database files and associated log files by utilizing a snapshot feature of the file system storing the files. At regular intervals, snapshots, which produce read-only copies of the files, are taken along with backups of the associated log files. To restore to a given point-in-time, the snapshot and stored log files are transferred to the active file system. In a second embodiment, all log files associated with snapshots taken after the selected snapshot are also restored.

Microsoft® Exchange is a messaging and collaboration software system that provides a variety of applications for group interaction using networked computer systems. Specifically, Microsoft Exchange (by Microsoft Corp. of Redmond, Wash.) provides support for electronic mail (e-mail) over various networks. Specifically, the Exchange software provides an e-mail server to support remotely connected e-mail clients such as, e.g., Microsoft Outlook®. The Exchange software acts as a server for providing various functionalities to clients. An Exchange server can run on a variety of operating systems including, for example, the Microsoft Windows NT® or Microsoft Windows® 2000 operating systems.
In a typical configuration, Microsoft Exchange stores data associated with e-mail services in a series of three databases. In the particular example of Microsoft Exchange version 5.5, these three databases are named priv.edb, pub.edb and dir.edb. However, it is contemplated that other versions support different database structures. The default storage locations for these databases are on a disk locally connected to the computer on which the Exchange software is running. Specifically, the priv.edb file stores the actual e-mail messages received by the Exchange server. The pub.edb file tracks and stores the public folders associated with the electronic mail messages. The dir.edb file holds the topology of the various folders.
FIG. 1 shows a flow chart of an exemplary e-mail passing through an Exchange server. In step 105, the electronic mail is received via known e-mail processes. These processes can include the use of such protocols as the post office protocol (POP). Next, in step 110, the message is stored in the memory of the server. The storage of the message in memory is often transient in nature until the message is committed to some form on nonvolatile storage. The e-mail message is then written to a log file in step 115. The log files typically have a preallocated size. In one known example, each log file is 5 megabytes (MB) in size. Thus, an Exchange server may have a variable number of log files at any given point-in-time, depending on how many log files have been incorporated into the database files. Next, the log files are written to and incorporated into the database files, in step 120. The writing of the log file to database occurs in a lazy write fashion. By "lazy write" it is meant a writing process or procedure of the Exchange software that performs the write when central processing unit cycles are available. Thus, this lazy write proceeds mainly during off-peak times when the server is not being heavily utilized.
FIG. 2 is a schematic block diagram of an exemplary Exchange server environment 200. An exemplary server 205 executing the Microsoft NT operating system containing a local disk 210 is shown connected to a tape drive 220 and an external disk 215. The external tape drive 220 is connected via either a small computer system interface (SCSI) connection or a switching network, such as storage area network (SAN). Similarly, the external disks 215 may be connected via a SAN or other suitable networking architectures. The Exchange server 205 may be incorporated into a Microsoft Clustering System (MSCS) environment 225. Such a clustering environment provides for redundant data program access to clients.
In known examples of Exchange servers, the Exchange software provides an application program interface (API) that is accessible by other programs executing on the server for performing backup and restore operations on the various databases. Other applications or processes executing on the server can access these APIs to perform various backup/restore operations. These API's are targeted toward the use of tape drive as a backup storage device. Such backup operations are normally performed while the Exchange server is operating. As tape drives typically have a slower read/write time than disk drives, the backup of databases with a tape device can consume a significant amount of time. While the Exchange server is still operational during a backup operation, performance is degraded during the course of the backup operation. Due to the extended degradation caused by the use of tape devices a backup storage media, backups are typically performed at night (or other off-peak time), when few users are utilizing the system. Similarly, a restore operation using a tape device consumes a substantial amount of time to restore the databases. When performing a backup or restore operation, the database files and any unincorporated log need to be saved and/or restored. Thus as the size of the various database files increases, the time required to perform a backup/restore operation to a tape device also increases.
In a further known example, the Exchange server is adapted to have the database and log files preferably written to a local disk. However, by utilizing other software products such as, e.g. SnapManager® Data Migrator available from Network Appliance, Inc. of Sunnyvale, Calif., the log files and databases may be written to disks that are remotely connected to Exchange server. In one known implementation, the Exchange server is operatively interconnected with a file server and associated disk arrays, which provides file service for storage and access of the database and log files.
A file server is a computer that provides file service relating to the organization of information on storage devices, such as disks. The file server or filer includes a storage operating system that implements a file system to logically organize the information as a hierarchical structure of directories and files on the disks. By "file system" it is meant generally a structuring of data and metadata on a storage device, such as disks, which permits reading/writing of data on those disks. A file system also includes mechanisms for performing these operations. Each "on-disk" file may be implemented as a set of disk blocks configured to store information, such as text, whereas the directory may be implemented as a specially-formatted file in which information about other files and directories are stored. A filer may be configured to operate according to a client/server model of information delivery to thereby allow many clients to access files stored on a server, e.g., the filer. In this model, the client may comprise an application, such as a file system protocol, executing on a computer that "connects" to the filer over a computer network, such as a point-to-point link, shared local area network (LAN), wide area network (WAN), or virtual private network (VPN) implemented over a public network such as the Internet. Each client may request the services of the filer by issuing file system protocol messages (in the form of packets) to the filer over the network.
A common type of file system is a "write in-place" file system, an example of which is the conventional Berkeley fast file system. In a write in-place file system, the locations of the data structures, such as inodes and data blocks, on disk are typically fixed. An inode is a data structure used to store information, such as meta-data, about a file, whereas the data blocks are structures used to store the actual data for the file. The information contained in an inode may include, e.g., ownership of the file, access permission for the file, size of the file, file type and references to locations on disk of the data blocks for the file. The references to the locations of the file data are provided by pointers, which may further reference indirect blocks that, in turn, reference the data blocks, depending upon the quantity of data in the file. Changes to the inodes and data blocks are made "in-place" in accordance with the write in-place file system. If an update to a file extends the quantity of data for the file, an additional data block is allocated and the appropriate inode is updated to reference that data block.
Another type of file system is a write-anywhere file system that does not overwrite data on disks. If a data block on disk is retrieved (read) from disk into memory and "dirtied" with new data, the data block is stored (written) to a new location on disk to thereby optimize write performance. A write-anywhere file system may initially assume an optimal layout such that the data is substantially contiguously arranged on disks. The optimal disk layout results in efficient access operations, particularly for sequential read operations, directed to the disks. A particular example of a write-anywhere file system that is configured to operate on a filer is the Write Anywhere File Layout (WAFL™) file system also available from Network Appliance, Inc. of Sunnyvale, Calif. The WAFL™ file system is implemented within a microkernel as part of the overall protocol stack of the filer and associated disk storage. This microkernel is supplied as part of Network Appliance's Data ONTAP™ storage operating system, residing on the filer, that processes file-service requests from network-attached clients.
As used herein, the term "storage operating system" generally refers to the computer-executable code operable on a storage system that implements file system semantics and manages data access. In this sense, Data ONTAP™ software is an example of such a storage operating system implemented as a microkernel. The storage operating system can also be implemented as an application program operating over a general-purpose operating system, such as UNIX® or Windows NT®, or as a general-purpose operating system with configurable functionality, which is configured for storage applications as described herein.
Disk storage is typically implemented as one or more storage "volumes" that comprise physical storage disks, defining an overall logical arrangement of storage space. Currently available filer implementations can serve a large number of discrete volumes (150 or more, for example). Each volume is associated with its own file system and, for purposes hereof, volume and file system shall generally be used synonymously. The disks within a volume are typically organized as one or more groups of Redundant Array of Independent (or Inexpensive) Disks (RAID). RAID implementations enhance the reliability/integrity of data storage through the redundant writing of data "stripes" across a given number of physical disks in the RAID group, and the appropriate caching of parity information with respect to the striped data. In the example of a WAFL-based file system, a RAID 4 implementation is advantageously employed. This implementation specifically entails the striping of data across a group of disks, and separate parity caching within a selected disk of the RAID group. As described herein, a volume typically comprises at least one data disk and one associated parity disk (or possibly data/parity) partitions in a single disk) arranged according to a RAID 4, or equivalent high-reliability, implementation.
A file server, as described above may be interconnected by a network to an Exchange or other database server to provide file service operations. In the example of an Exchange database server, the various database files can be stored on a set of disks interconnected with a file server through the use of such software programs as the above-described SnapManager software. As noted, such file servers typically utilize a tape device for backup/restore operations. A substantial amount of time is required to perform a backup operation to a tape device. Consequently, many system administrators do not frequently perform backup operations, thus preventing system performance degradation due to the ongoing backup operation. To restore a database to a particular point-in-time, the administrator typically requires a backup of the file system or database files generated at the desired point-in-time. As backups are typically written to tape devices with lengthy intervals between successive backups, the possible selection of discrete points-in-time to restore to is generally limited.

System and method for creating a point-in-time restoration of a database file


In a drive unit for a hybrid motor vehicle including an internal combustion engine and a dynamoelectric machine to be connected to a transmission of the motor vehicle, wherein the drive unit comprises an input shaft connected to the internal combustion engine, an output shaft connected to the dynamoelectric machine for rotation therewith and a clutch for connecting the input shaft to the output shaft, the clutch includes centrifugal actuators for causing engagement of the clutch upon rotation at a speed in excess of a threshold value, springs counteracting the centrifugal actuators for causing the release of the clutch at a speed below the threshold value, and an electromagnetic actuators for causing engagement of the clutch at a speed below the threshold value to permit startup operation of the internal combustion engine by the dynamoelectric machine.

The invention relates to a drive unit for a hybrid motor vehicle for coupling an internal combustion engine and/or an electro-dynamic machine to a transmission.
DE 43 23 601 A1 discloses a drive unit for a hybrid motor vehicle which includes an input shaft, a single disc dry clutch, an output shaft and an electric motor-generator. The input shaft is driven by the internal combustion engine. Within the drive unit, the input shaft is connected to the primary side of the clutch. The output shaft extends to the transmission and is connected within the drive unit to the secondary side of the clutch and the motor-generator. When the clutch is closed, a power path is established from the internal combustion engine via the input shaft and the clutch to the output shaft. The state of the clutch is determined by a throw-out plunger, a throw-out bearing and a closing spring effective in axial direction. During operation by the electric motor, the clutch must be de-activated in order to uncouple the internal combustion engine from the motor-generator. To this end, the closing spring must be held in the non-closing position, that is, a corresponding high holding force must be applied via the throw-out plunger and the throw-out bearing. Critical also is the use of single disc and two-disc dry clutches for hybrid vehicles with high-torque internal combustion engines, of for example, more than 1000 Nm. A single disc dry clutch for the transmission of such high torques requires a relatively large space which increases the weight correspondingly.
It is therefore the object of the present invention to provide a drive unit capable of transmitting a high torque while having only moderately large space requirements.


The present invention provides an automatic system for engaging the hydromatic brake on a drilling rig or a service rig. This system monitors both the hook load and traveling block velocity, and uses an electrical solenoid to activates the hydromatic when either the hook load or rotating drum velocity exceeds a maximum value, requiring hydromatic brake engagement.

This invention relates to rigs used in oil well operations. Although it is primarily directed to service rigs used in the maintenance and overhaul of existing oil wells, it might also be adapted to use in association with rigs for drilling new oil wells.
While the operation of drilling an oil well has long been performed automatically by a drilling rig, there are operations in connection with oil well drilling or oil well servicing which require a great deal of non-productive time and man power. In the case of a drilling rig it is frequently necessary to pull the drill string out of the hole ("tripping out") to replace the bit and to run the drill pipe back into the hole. After an oil drilling rig drills a well and installs the well casing, the rig is dismantled and removed from the site. From that point on, a mobile repair unit, or workover rig, is typically used to service the well. Servicing includes, for example, installing and removing inner tubing strings, sucker rods, and pumps. It is frequently necessary to pull out a string of production pipe to service the well or maintain downhole equipment. In either case this involves a long series of repetitive steps in which joints of pipe are withdrawn from the hole, (one or two or three at a time), disconnected by "breaking out" their threaded ends, and stored while subsequent lengths are withdrawn. The process is repeated in reverse when lengths of pipe are connected ("made up") together and inserted one after another to replace the drill string or the production string in the hole. This is generally done with a cable hoist system that includes a traveling block that raises and lowers the aforementioned tubing strings, sucker rods, and pumps.
While running lengths of pipe, it is obvious that as more and more lengths are run into the hole, the heavier and heavier the string of pipe becomes. This puts an ever increasing strain on conventional brake drums of the cable hoist system, sometimes leading to brake failure or brake inefficiency due to heating while tripping into the hole. Installing disk assist brakes on service rigs delivers the control and safety needed in the well servicing industry. As disk assist brakes are installed on remanufactured rigs, algorithms are being developed to control the speed throughout the range of downward block travel, but these algorithms are not currently being implemented. Because the conventional drum brakes are self energizing, they are difficult to use to finely control downward speeds.
Heat is the brake's worst enemy. As hookloads get heavier and the blocks get faster, more braking action must be applied to control and stop the blocks. Bringing heavily loaded blocks to a stop from fast moving downward motion generates energy that ends up being dissipated as heat. Hot brakes have control issues, resulting in part from band stretching and when the drums get out of round. Spraying water on the brake bands is one solution used in the field. As the brakes heat, the rig has a nozzle system that is designed to cool the bands down, however this system has it problems too. Heat and water changes metallurgy and causes corrosion. This can lead to component failure and general brake failure. Therefore, it is incumbent on the drilling and service industry to avoid heating the brakes too much.
Enter the hydromatic or water brake. The hydromatic brake is usually nothing more than a water pump connected to the tubing drum. When the hookload gets high, the hydromatic brake should be engaged to both slow down and control the speed. When engaged, the falling blocks and hookload energy are dissipated into the pumping of water, thereby delaying the tubing drum brake heating. However, while the hydromatic brake system can reduce conventional brake wear, it must be used to be effective. One drawback of the hydromatic is the slowing down of the running speed. When the energy of the downward moving block is transferred to the brake, the rig experiences a loss of freefall and therefore a slowing effect. As a result of this, an operator or driller will not engage the hydromatic until it is needed or mandated by standard operating procedures. If he is in a hurry to trip into the hole, he is more likely to delay the brake engagement. Often times drilling or rig operators will not engage the brake, and thus it would be desirable if an automated system was developed to automatically engage the hydromatic brake when appropriate.

System for assuring engagement of a hydromatic brake on a drilling or well service rig


According to one embodiment, a magneto-resistance effect device includes: a multilayer structure having a cap layer; a magnetization pinned layer; a magnetization free layer provided between the cap layer and the magnetization pinned layer; a spacer layer provided between the magnetization pinned layer and the magnetization free layer; a function layer which is provided in the magnetization pinned layer, between the magnetization pinned layer and the spacer layer, between the spacer layer and the magnetization free layer, in the magnetization free layer, or between the magnetization free layer and the cap layer, the function layer having oxide containing at least one element selected from Zn, In, Sn and Cd, and at least one element selected from Fe, Co and Ni; and a pair of electrodes for applying a current perpendicularly to a film plane of the multilayer structure.

A magneto-resistance effect device having a thin-film spin filter layer (SF) which is made of oxide or nitride and which is inserted in each of ferromagnetic layers or in an interface between each of the ferromagnetic layers and a nonmagnetic spacer layer has been proposed in JP-A-2004-6589. This SF layer can increase the MR (Magneto-Resistance) ratio because it has a spin filter effect in inhibiting conduction of either up-spin electrons or down-spin electrons.

Magneto-resistance effect device with mixed oxide function layer


A method for forming an air region or an air bridge overlying a base layer (12). Air regions (20a, 20b, 28a, and 48) are formed overlying the base layer (12) to provide for improved dielectric isolation of adjacent conductive layers, provide air-isolated conductive interconnects, and/or form many other microstructures or microdevices. The air regions (20a, 20b, 28a, and 48) are formed by either selectively removing a sacrificial spacer (16a and 16b) or by selectively removing a sacrificial layer (28, 40). The air regions (20a, 20b, 28a, and 48) are sealed, enclosed, or isolated by either a selective growth process or by a non-conformal deposition technique. The air regions (20a, 20b, 28a, and 48) may be formed under any pressure, gas concentration, or processing condition (i.e. temperature, etc.). The air regions (20a, 20b, 28a, and 48) may be formed at any level within an integrated circuit.

The integrated circuit industry is constantly reducing the separation between conductive layers of material in order to achieve a smaller integrated circuit. By reducing the spacing of conductive materials in an integrated circuit, an increase in a phenomenon known as capacitive crosstalk is observed. Conventional integrated circuits typically use an interconnect structure wherein a first metal line is adjacent a second metal line. If the crosstalk or capacitance between the first metal line and the second metal line is high, then the voltage on the first metal line alters or affects the voltage on the second metal line. This alteration in voltage could cause an integrated circuit to misinterpret logic zeros, logic ones, and voltage levels, and therefore incorrectly process binary and/or analog information. An integrated circuit that incorrectly processes any information is usually totally inoperable.
In order to reduce capacitive coupling and therefore reduce crosstalk, the integrated circuit industry has been developing low dielectric constant (low-K) materials to replace conventional dielectric/insulative materials. Conventional semiconductor insulative materials have a dielectric constant having a value of roughly four. Some new/advanced dielectric materials such as Teflon, organic dielectrics, and the like, may have a dielectric constant between roughly four and two. The use of many low-K dielectric materials is not feasible due to the fact that equipment is not available to properly process the new dielectric materials in various integrated circuits. Also, the chemical or physical properties of many low-K dielectric materials are usually difficult to make compatible or integrate into conventional integrated circuit processing.
Coaxial cable structures and similar structures have been attempted in integrated circuits with little success. A coaxial structure has a first conductor which carries a signal (i.e. a digital signal or an analog signal) and a second conductor surrounding the first conductor which is used to shield the first conductor from other conductors in the integrated circuit. In an integrated circuit, it is very difficult to form a first conductor entirely surrounded by a second conductor. Furthermore, two or more conductive layers are required to form the coaxial structure. Several layers of conductive material are therefore required in order to produce one functional layer of conductive interconnect. Using several conductive layers to form one functional conductive interconnect layer is not substrate surface area effective, manufacturing-throughput effective, or cost effective in most cases.
In order to attempt to reduce capacitive coupling and resistor/capacitor (RC) delays, superconductive material has been researched in the integrated circuit industry. Superconductors require low temperatures in order to operate properly and are therefore expensive to operate and expensive to maintain. In many cases, superconductive material is highly sensitive to oxygen and must be specially encapsulated in integrated circuits to avoid other oxygen containing areas, such as oxides and the like, from introducing unwanted contamination. Superconductors tend to be brittle, and are therefore not suited to integrated manufacturing. In many cases, a superconductor could not survive the mechanical stresses induced on a semiconductor wafer when manufacturing integrated circuits.
A new method and structure for reducing capacitive crosstalk between conductive regions in a semiconductor device is required.

Method of forming a semiconductor structure having an air region


A silver halide color photographic light-sensitive material in roll form comprises a support, and provided thereon, a silver halide emulsion layer and, on the side of the support opposite the silver halide emulsion layer, a backing layer containing gelatin and a hardener, wherein the backing layer has a degree of swelling of 250% or less represented by the following equation: EQU Degree of swelling=[(A-C)/(B-C)].times.100.

Compact cameras are widely used today. And, to make these compact cameras more handy to carry, much smaller ones are desired. In various attempts to realize the further miniaturization of these compact cameras, one of the prime essentials is to reduce the space to house a photographic film.
When loaded in a compact camera, a photographic film is generally wound on a spool in roll. Therefore, to reduce the housing space for a photographic film without decreasing the number of exposures, the film itself must be made thinner. The thickness of a photographic support now in use is about 120 to 125 .mu.m and considerably thicker than that of a light-sensitive layer (20 to 30 .mu.m) formed on the support. Accordingly, thinning a photographic support is the most effective means for reducing the thickness of a whole photographic film.
As photographic supports used now, triacetylcellulose (occasionally abbreviated as TAC) films are the most typical. However, TAC films are poor in mechanical strength by nature; therefore, when made much thinner, TAC films become apt to cause troubles during conveyance or handling in a camera or in the developing process after photographing. Accordingly, it is not expedient to make the thickness of a TAC film support less than the thickness of a photographic support in use today.
On the other hand, polyethylene terephthalate films, which have so far been employed as films for X-ray photography or for photomechanical process in the photographic industry, are excellent in mechanical strength and, thereby, come to attract much attention as a photographic support which may enable the reduction of the thickness of a photographic film without lowering the mechanical strength. However, polyester resin films including polyethylene terephthalate films are unsuitable for photographic supports by nature, because these films are likely to cause a curl and can be hardly recovered from it once wound in roll.
However, the technique to provide a polyester resin with hydrophilicity disclosed in Japanese Pat. O.P.I. Pub. Nos. 120857/1990, 244446/1989, etc. has made possible to prevent polyester resin films from curl. Since then, active studies have been made with the aim of developing a thinner photographic film by use of a polyester resin support.
When such a polyester resin photographic support is used, a thinner photographic film can be certainly obtained; but, there arises a problem that the photographic film becomes apt to curl because of high water content of by a emulsion layer formed on one side of a support. To prevent such curl by balancing the moisture contents between the two sides, there is a method of using gelatin in a backing layer formed on the side of the support opposite to the emulsion layer.
A photographic film having gelatin in the backing layer does not curl, because the moisture contents of layers formed on the two sides of a photographic support are nearly equal to each other and, thereby, the curling property is balanced between the two sides. However, there arises another problem that the backing layer is stained with dust or foreign matters adsorbed thereon when brought into contact with a roller in the developing process using a cine automatic processor.

Silver halide color photographic light-sensitive material in roll form


A resettable latch circuit provides a modified address transition detection (XATD) signal in response to receiving an address-change input pulse signal at a SET input terminal thereof. A RESET input terminal for the latch circuit receives a delayed reset signal from a resettable delay circuit which has its input terminal coupled to the output terminal of the resettable latch circuit to receive the XATD signal. The resettable delay circuit includes a reset control signal terminal to which is coupled an inverted address-change input pulse. One embodiment of the resettable delay circuit includes a series of inverters and MOSFET load resistors as well as shunt MOSFET transistors turned on by the address-change signal to shunt the output terminals of the inverters and reset the delay line. The SET input terminal of the latch circuit also receives a chip-select-change signal pulse which is similar to the address-change pulse.

1. Field of the Invention
This invention relates memory control circuits and, more particularly, to an improved address transition circuit for a memory device.
2. Prior Art
Previously, random access memories (RAMs) were purely static devices, that is, clocking techniques were not used with static RAMs. When address signals were applied to such devices, the address signals just rippled through to the memory cells to retrieve data stored therein. These devices were simple in operation, but slow and consumed large amounts of power.
Next, an address transition detection (ATD) technique was used which simulated static operation externally while clocking techniques were used inside the memory circuit to save power, chip area, and to speed up operation.
With reference to FIGS. 1 and 2, an ATD circuit 100 is shown In FIG. 1 and timing diagrams are shown in FIG. 2. An address-change input pulse is provided at node N19. This address-change input pulse is produced when a memory address bit signal changes. The memory address bit signal is sent through a delay line (not shown). The memory address bit and a delayed memory address bit from the delay line are then both inputted to an Exclusive-OR (XOR) circuit. The XOR circuit produces the address-change input pulse at node N19 which has a pulse width equal to the delay time of the delay line.
FIG. 2 is a timing chart timing showing an address bit signal changing levels and a resultant address-change input pulse at node N19. The address-change input pulse is applied to an input terminal of a resettable latch circuit 102 having a SET input terminal connected to node N19, a RESET input terminal connected to a node N6, and an OUTPUT terminal at a node N20. A latch output signal is provided at node N20 and inverted with an inverter 104 to provide a modified ATD signal called XATD at an output terminal 106. The XATD signal at terminal 106 is also directed to a delay circuit 110 to provide a delayed reset signal at the reset node N6 of the resettable latch circuit 102. The address-change input pulse at node N19 sets the XATD signal and the reset signal at node N6 resets the XATD signal. The XATD signal passes through the delay line 110 to put the signal at node N6 back to its initial condition as a logic one as shown in FIG. 2.
One embodiment of the latch circuit 102 includes three PMOS transistors M3, M4, M5 and four NMOS transistors M5, M6, M7, M8 connected as illustrated in FIG. 1.
The delay circuit 110 provides a delayed reset signal at the reset node N6 of the resettable latch circuit 102. One embodiment of the delay circuit 110 is shown in FIG. 2 and uses five inverters 112, 114, 116, 118, 120 to provide signal delays with respective MOSFET shunt loads 122, 124, 126, 128, coupled to the output terminals of the first four inverters, as illustrated in the Figure.
When the XATD output signal is high, the bit lines of the memory device are precharged to a one, as indicated in FIG. 2. When XATD goes low, the word line of the memory goes high so that some of the precharged bit lines are selectively discharged, depending upon the state of the memory bits. When XATD goes low, the charge level of the charged or discharge bit line is then detected and a corresponding signal is sent to the appropriate memory output terminal, that is, the memory content is "evaluated" as being either a one or a zero state, as indicated in FIG. 2.
Each address bit has a latch circuit for providing a corresponding XATD signal. All of the XATD signals are combined in an OR circuit to provide a global, or summarized, XATD signal.
For static operation, no restrictions are placed upon the time that address bits can occur. One address bit can arrive early and another address bit can arrive very late. This is acceptable because the specified access time to retrieve information in a memory starts from the last arriving address bit.
A chip select signal is usually associated with operation of an ATD circuit. When an ATD chip is selected, it is not known whether or not an address bit has been changed before the chip selection. To play it safe, assertion of a chip select signal causes a chip-select-change signal pulse, which is similar to an address-change pulse, to appear at the input node N19 (from a circuit not shown).
FIG. 3 is a timing chart which indicates that a problem arises when a chip select signal is asserted first and then, at a later time, an address bit subsequently changes when the reset signal at node N6 is low. If the address bit changes when N6 is low, that is, has not recovered yet, the signal at node N20 goes low. Because transistor M4 is on instead of off, the signal at output node N20 will go back up as soon as the signal at input node N19 goes low again. A narrow pulse on output node N20 causes a corresponding narrow XATD signal to appear at terminal 106. The corresponding narrow XATD signal is too short to precharge up the selectively discharged bit lines that were discharged by the #1 memory evaluation period (#1 memory evaluate in the Figure) if the #1 memory evaluation period was long enough. The result is that during the #2 memory evaluation period (#2 evaluate) the memory is incorrectly evaluated. This produces a window of non-operation so that the operation of the memory chip does not match that of a purely static operation.
One possible way to correct this situation is to ensure that signal the reset signal at node N6 is not low when a pulse arrives at input node N19. One possible way to provide this is to size the transistors in the delay line 110 so that the positive edge of the signal at node N20 ripples through the delay line quickly and the negative edge of the signal at node N20 goes through the delay line 110 with the required delay time for precharging the bit lines. This narrows the window of non-operation somewhat, but not completely.
A need exists for an improved address transition circuit which can accommodate address bit changes in an ATD circuit.


Alerting a user of an integrity error in a global positioning system (GPS) signal transmitted from a transmitter in a global positioning system (GPS) satellite, by detecting an error in the global positioning system (GPS) signal, alerting the user of the error by shifting a phase of the global positioning system (GPS) signal from an initial value by a predetermined phase-shift amount, and returning, in the case that the detected error is corrected, the phase of the global positioning system (GPS) signal to the initial value. Preferably, the GPS signal is phase-shifted by the predetermined phase-shift amount using an alert timing pattern which indicates the level of detected error.

1. Field of the Invention
The present invention concerns providing an integrity alert to a user of the Global Positioning System (GPS) when the signal contains an error. Specifically, the invention concerns alerting the user of the signal error by shifting the phase of the Global Positioning System (GPS) signal from an initial value by a predetermined phase-shift amount.
2. Description of the Related Art
The use of the Global Positioning System (GPS) is increasing rapidly in a variety of applications. Accordingly, the users of GPS expect to have, and often must have, confidence in the integrity and accuracy of the GPS signal. U.S. Pat. No. 6,603,426, (hereinafter "the '426 patent"), issued Aug. 5, 2003, sets forth one solution to this problem by the same applicant of the present invention.
As explained in the Background section of the '426 patent, the Global Positioning System (GPS) consists of 24 earth-orbiting satellites. The GPS satellites broadcast a navigation message via a radio frequency (RF) signal. This signal allows any individual with a GPS receiver to process the GPS signals and determine his or her precise longitude, latitude, altitude, velocity and time anywhere in the world.
Although the Global Positioning System (GPS) provides very accurate position and time information, there are times when GPS satellite system malfunctions can introduce errors into the GPS signal transmitted from the GPS satellite. When this occurs, the GPS receivers will not be able to accurately determine position and/or time. Past data has shown that the GPS signal has typically malfunctioned on the average of around 45 minutes a year. When the GPS satellite system is functioning properly and producing accurate GPS data, the GPS data is described as having "integrity."
GPS signal errors can be caused by a number of conditions. For example, if one of the GPS satellite transmitter elements, or any of the other satellite components, fail, the GPS signal waveform can become corrupted. For example, an output amplifier in the GPS satellite may start to malfunction and thereby corrupt the transmitted signal. Another source of error is a failure of the satellite's atomic clock. If a clock failure occurs, the satellite will transmit incorrect time data and introduce error into the computed position information. Another potential error is the transmission of erroneous correction data from GPS ground stations to GPS satellites. GPS ground stations uplink correction data to the GPS satellites every 24 hours. If a ground station sends the wrong correction data, then the GPS satellites will produce inaccurate or erroneous output signals. As an example of this type of error, a ground station could mistakenly send correction data for Tuesday when it was supposed to send correction data for Wednesday.
Errors in GPS signals can lead to severe safety issues or inefficient operation for many systems that use GPS signals, such as aircraft systems, transportation systems, weapon systems and so forth. New aircraft navigation systems are being developed which rely on GPS signals for navigation. It can be appreciated that errors in the received GPS signal in an aircraft navigation system could lead to mid-air crashes or other dangerous situations. The Federal Aviation Administration (FAA) has a goal of having no more than a 2 times 10−8 probability of error in the GPS signal without an alert that the signal is hazardous or misleading. With the current GPS system, the probability of error in the GPS signal is on the order of 10−4 per satellite per hour or even higher. Thus, for example, it is possible that a current GPS satellite could produce a probability of error ten thousand times higher than the FAA's desired goal.
One of the proposed systems that will utilize GPS is an intelligent highway system. Intelligent highway systems would use GPS signals to manage traffic by providing autonavigation for the automobiles on the freeways. Similar systems have been proposed for trains. Thus, it will be a very important safety issue for these systems to ensure the integrity of the received GPS signals.
Currently, the Global Positioning System (GPS) system does not have any form of integrity monitoring as part of the system. A system known as the "Wide Area Augmentation System" (WAAS) is currently being designed and developed to provide integrity monitoring of GPS. The WAAS will use a series of new ground stations at known locations all over the world. Each ground station will include a satellite antenna which receives GPS signals from the in-view GPS satellites. Each ground station will use these GPS signals to calculate its own position. By comparing the calculated position with the known position of the ground system, the accuracy and the integrity of the GPS signal of each corresponding in-view GPS satellite can be determined.
If the calculated position is different from the known position of the WAAS ground station, a correction message is generated by the ground station. The ground station transmits the correction message to an independent messaging system, such as a geosynchronous satellite. This geosynchronous messaging satellite then broadcasts the correction message to all GPS users in the region. The GPS users then use the correction message to correct the GPS data received from the GPS satellites. Alternatively, the geostationary messaging satellite can transmit an integrity message to all GPS users in the region, informing the users of a potential satellite malfunction. GPS users can thereby be informed that they should not rely on the GPS signals being received. Alternatively, the ground system could send the integrity message to a mission control system which sends a message to the GPS satellites to correct the erroneous data or to cease transmitting all GPS navigation data.
The WAAS integrity monitoring system will require an enormous cost including the cost of building the new WAAS ground stations, procuring the new geostationary messaging satellites, and the costs of maintaining and operating the ground stations. Estimated costs for the development and implementation of WAAS are greater than 2 billion dollars. Moreover, the WAAS may not be able to signal a problem with GPS integrity with sufficient speed. Many systems, such as aircraft navigation systems, using GPS frequently need to know of a change in GPS signal integrity in times less than 1 sec after a malfunction or error occurs.
The '426 patent offers one solution to the GPS integrity problem by having each GPS satellite verify the accuracy and/or integrity of its own operations by calculations and processing internal to the GPS satellite and by crosslink communications with other GPS satellites in the GPS constellation, after which the GPS satellite transmits an integrity message to all GPS users in view of the satellite, the integrity message being either incorporated into the existing GPS navigation message, or being transmitted over a separate communication channel. This solution offers the GPS user the ability to monitor the GPS integrity message to determine whether any errors exist in the received GPS navigation signal. Although the solution of the '426 patent provides a reliable way for GPS users to be alerted to inaccuracies in the GPS signal, the solution requires the GPS user to read the GPS integrity message to determine if any error exists, and the magnitude of the error. Time is required to read the integrity message, and if the integrity message is transmitted over a separate communication channel, the GPS user must have an upgraded receiver capable of receiving the separate communication channel.
What is needed is a system that can provide a high-level of confidence in GPS integrity by alerting GPS users to a loss of GPS signal integrity with sufficient speed to satisfy safety concerns and regulatory standards, without the need for using a separate communication channel, and without the enormous cost and complexity associated with a system such as the WAAS.

Phase step alert signal for GPS integrity monitoring


An improvement to automatic classifying of threat level of objects in CT scan images of container content, methods include automatic identification of non-classifiable threat level object images, and displaying on a display of an operator a de-cluttered image, to improve operator efficiency. The de-cluttered image includes, as subject images, the non-classifiable threat level object images. Improvement to resolution of non-classifiable threat objects includes computer-directed prompts for the operator to enter information regarding the subject image and, based on same, identifying the object type. Improvement to automatic classifying of threat levels includes incremental updating the classifying, using the determined object type and the threat level of the object type.

In various systems for electromagnetic (EM) scanning of containers for potential threat items, e.g., airport EM baggage scanning systems, an EM scanning equipment sends an operator a visible image of the EM scan of the entire container, accompanied by a request to the operator to identify which, if any, among the content items requires further action, e.g., manual inspection. In various of such systems, the operator draws a bounding box around each content item requiring further attention. Baggage items, though, can contain visually obstructive distributions, e.g., stacking and bunching, of many different kinds of items. This can make the operator task of mentally separating the item images from one another and determining, for each, whether it's an image of a threat item, a benign item, or an unknown item, time and labor intensive. Further, upon operator reception of a stream of baggage items, cumulative time and labor of separating and adjudicating their content images can result in operator errors.

The Government of the United States of America, as represented bv the Secretan/ of Homeland Security


A substrate-through electrical connection (10) for connecting components on opposite sides of a substrate, and a method for making same. The connection includes a substrate-through via made from substrate material (10′). There is a trench (11) provided surrounding the via, the walls of the trench being coated with a layer of insulating material (12) and the trench (11) is filled with conductive or semi-conductive material (13). A doping region (15) for threshold voltage adjustment is provided in the via material in the surface of the inner trench wall between insulating material (12) and the material (10′) in the via. There are contacts (17′, 17″) to the via on opposite sides of the substrate, and a contact (18) to the conductive material (13) in the trench (11) so as to enable the application of a voltage to the conductive material (13).

Applicants own Swedish patent SE-0300784-6 (publication number 526 366) discloses and claims through-connections (also referred to as vias) made in a wafer material from the native wafer itself. The vias thereby comprises the same material as the remainder of the wafer and will thus be capable of being processed in a more versatile manner, as describe in detail in said patent, the disclosure of which is incorporated herein in its entirety by reference.
However, for certain applications the resistivity that is attainable in these prior art vias may be too high, and it would be desirable to provide vias with very low resistivity.
It is known to provide vias made of metal, but the conventional methods used (sputtering, plating, or evaporation methods) are all suffering from the problem that it is difficult to fill very small holes with them. Metal vias only allows via last processes (e.g. CMOS structures must be made before via formation).
A general problem addressed in WO2007/089207 is that on one hand it is desirable to have substrates (wafers) having low resistivtiy electrical through-connections (vias). This requires that the starting substrate for making the vias exhibits a low resistivity, e.g. it is highly doped.
On the other hand electronic circuits are made in high resistivity materials (such as non-doped silicon). It is desirable to connect the circuits made on one side of a wafer with structures on the other side using vias of the type mentioned.
These two requirements and preconditions are contradictory. The invention according to WO2007/089207 provides methods for solving this problem.
In U.S. Pat. No. 6,373,097 there is disclosed a field-effect-controllable vertical semiconductor component, and a method for producing the same. The component includes a semiconductor body having at least one drain region of a first conduction type, at least one source region of the first conduction type, at least one body region of a second conduction type between the drain regions and the source regions, and at least one gate electrode insulated from the entire semiconductor body by a gate oxide. A gate terminal and a drain terminal are located on a front side of the wafer, and a source terminal is located on a rear side of the wafer. A monolithically integrated half bridge with a low-side switch and a high-side switch includes the field-effect-controllable vertical semiconductor component and a conventional field-effect-controllable vertical semiconductor component.

Starting substrate for semiconductor engineering having substrate-through connections and a method for making same


The invention is devised to facilitate the editing of a graphic displayed on a screen. An editing device includes: an edit object display unit for displaying on a screen a graphic to be edited which includes at least one line graphic defined as a line segment extending from a first end point to a second end point; an edit graphic display unit for displaying on the screen an edit graphic for editing the line graphic; an edit graphic moving unit for moving the edit graphic on the screen in accordance with a user operation; an edit graphic moving unit for moving the edit graphic on the screen in accordance with a user operation; an edit object dividing unit for dividing, in response that the edit graphic contacts a line graphic, the line graphic by generating an end point at a contact point; and an edit object moving unit for moving, in response that the edit graphic is further moved in a direction of a line graphic which contacts the edit graphic, an end point of the line graphic, which contacts the edit graphic in accordance with the movement of the edit graphic.

In recent years, the editing of image, graphic or the like by a computer is conducted in various fields. For example, in a Geographic Information System (GIS) and the like, a graphic such as a polyline and a polygon is represented by a vector data. In order to move a linear graphic represented by a vector data, a user clicks the mouse on a vertex of the graphic and drags the mouse to move the graphic. On the other hand, in order to edit a vector data, a user adds a new vertex to a side of the graphic and moves the vertex. If a user specifies a vertex and opens a pop-up menu or the like to select a command to eliminate the vertex, the unnecessary vertex can be eliminated.
As another method for editing a graphic, there has been disclosed in Japanese Published Unexamined Patent Application No. 5-108786 a method in which a line segment to be edited on a screen is made to overlap with a polygon for editing the line segment, thereby transforming that part of the line segment which overlaps the polygon into the shape of the periphery of the polygon.