A locking system for a door of an enclosure has a handle, lock, and locking bolts mounted to the door, door jams mounted to the enclosure, dead bolts coupled to the locking bolts, and a blocking bolt coupled to the lock. When door is closed and handle is closed, then locking bolts are moved to locked position, such that door jams block path of locking bolts and thereby prevent door from being opened. When lock is unlocked, dead bolts can move toward each other allowing door to be opened. However, when lock is locked, door cannot be opened because blocking bolt, between dead bolts, prevents dead bolts from moving toward each other.

1. Technical Field
The present invention relates to a locking system, and more particularly relates to a locking system used to securely lock a door of an enclosure such as a safe, vault, or other enclosure.
2. Related Art
A safe, vault, or other secure enclosure may be utilized to store items. Locking systems have been developed for such structures, in order to help prevent compromise of the items stored therein.
A variety of systems for locks and doors have been developed, such as, for example: U.S. Pat. No. 131,699 for IMPROVEMENT IN BOLTS FOR SAFES, DOORS, &c. issued to L. H. Miller on Sep. 24, 1872; U.S. Pat. No. 393,883 for SAFE OR VAULT DOOR LOCK issued to W. M. Brown, Jr. on Dec. 4, 1888; U.S. Pat. No. 636,325 for SAFE LOCK issued to C. Eyster on Nov. 7, 1899; U.S. Pat. No. 874,833 for FASTENER FOR REFRIGERATOR DOORS issued to L. G. Coon on Dec. 24, 1907; U.S. Pat. No. 1,173,068 for LOCKING MECHANISM FOR SAFE OR VAULT DOORS issued to H. C. Von Philp on Feb. 22, 1916; and U.S. Pat. No. 1,366,015 for SAFETY LOCK MECHANISM issued to J. Morris on Jan. 18, 1921.
Additional systems for locks and doors have been developed, such as, for example: U.S. Pat. No. 1,554,700 for DOOR LATCH OPERATING DEVICE issued to F. A. Anderson on Sep. 22, 1925; U.S. Pat. No. 2,460,961 for QUICK-ACTING SECURING MEANS FOR WATERTIGHT DOORS issued to D. G. Wilson on Feb. 8, 1949; U.S. Pat. No. 2,511,268 for BULKHEAD DOOR AND THE LIKE AND FASTENING MEANS FOR SAME issued to Karl L. Schiff on Jun. 13, 1950; U.S. Pat. No. 4,754,715 for TOGGLE-TYPE SAFE DOOR LOCKING MECHANISM issued to William D. Squires on Jul. 5, 1988; U.S. Pat. No. 5,026,102 for MECHANICAL SECURITY DEVICE FOR DOORS issued to James Pitman on Jun. 25, 1991; and U.S. Pat. No. 5,333,920 for PANEL FOR CLOSING AN OPENING, AND CLIP SYSTEM FOR USE AS A PART THEREOF issued to Jan de Rover on Aug. 2, 1994.
Further systems for locks and doors have been developed, such as, for example: U.S. Pat. No. 5,472,247 for MULTI-POINT HIGH SECURITY LOCKING MECHANISM FOR LOTTERY MACHINES issued to Gavin M. Monson on Dec. 5, 1995; U.S. Pat. No. 6,101,764 for PIVOTING DOOR OF THE TYPE HAVING AT LEAST ONE LEAF OF WHICH TWO BARS ARE MOUNTED IN PARALLEL BY MEANS OF LINKS issued to Alix Guy-Paul on Aug. 15, 2000; and U.S. Pat. No. 6,319,479 for CLOSURE FOR A HINGED STERILIZER DOOR issued to John C. Houston on Nov. 20, 2001.
The references listed above may provide a variety of advantages. However, in view of the foregoing, it is believed that there is still a need for a new lock assembly for a door of an enclosure which can provide a more convenient, reliable, and more secure manner of protecting the contents stored in the enclosure, having a simplified operation and a minimum number of moving parts.
Accordingly, further improvements in lock assemblies and systems for doors of enclosures can be envisioned.

Locking system for a door of an enclosure


A turbine comprises a turbine wheel for rotation within a turbine housing, the turbine housing including at least one volute arranged to deliver a fluid to the turbine wheel via the turbine nozzle. A method for determining a width of a turbine nozzle for the turbine, comprises selecting from a relationship between a turbine stage efficiency and an effective nozzle area, at least one target effective nozzle area. As used here, the effective nozzle area is dependent on both the width of the turbine nozzle and a whirl angle induced by the at least one volute. The method further comprises determining, in dependence on the whirl angle, the width of the turbine nozzle as a width that will achieve the at least one target effective nozzle area.

Turbomachines are machines that transfer energy between a rotor and a fluid. For example, a turbomachine may transfer energy from a fluid to a rotor or may transfer energy from a rotor to a fluid. Two examples of turbomachines are a power turbine, which uses the rotational energy of a rotor driven by a fluid to do useful work, for example, generating electrical power; and a compressor which uses the rotational energy of the rotor to compress a fluid.
Turbochargers are known turbomachines for supplying air to an inlet of an internal combustion engine at pressures above atmospheric pressure (boost pressures). A conventional turbocharger comprises an exhaust gas driven turbine wheel mounted on a rotatable shaft within a turbine housing connected downstream of an engine outlet manifold. Rotation of the turbine wheel rotates a compressor wheel mounted on the other end of the shaft within a compressor housing. The compressor wheel delivers compressed air to an engine inlet manifold.
The turbocharger shaft is conventionally supported by journal and thrust bearings, including appropriate lubricating systems, located within a central bearing housing connected between the turbine and compressor wheel housings. After driving the turbine wheel the exhaust gas exists the turbine through a gas outlet which is at the opposite end of the rotational axis of the turbine wheel from the bearing housing.
It is known for the multiple cylinders of an internal combustion engine to be portioned into two groups of cylinders, and for the exhaust gas emitted by the respective groups of cylinders to be transmitted into two respective gas inlets of a turbocharger. The gas inlets are in fluid communication with a chamber of the housing containing the turbine wheel via respective volutes. The volutes are spaced from each other along the rotational axis of the turbine wheel, such that a first of the volutes is closer to the bearing housing (the "bearing housing side volute"—BH), and the other is closer to the turbine outlet side (the "turbine outlet side volute"—TO). The inlets to the volutes may be circumferentially-spaced from each other about the rotational axis of the turbine wheel ("double-entry" volutes), or axially-spaced but not circumferentially-spaced ("twin-entry" volutes).
It may be desirable to provide a new method for designing turbines for turbochargers that at least partially addresses one or more problems associated with prior art methods, whether identified here on not.

Effect of the nozzle width to harness on engine pulse energy


A voltage to current converter comprises a signal stage (1) with a first transistor (11) and a first resistor (12). The first transistor (11) is adapted to be fed with an input signal voltage (Vin). The converter is adapted to generate an output current, comprising an output DC bias current (IB1) and an output signal current (iout), and to provide a gain adjustment through the variation of the first resistor (12). The converter further comprises a bias stage (2), adapted to generate and feed the signal stage (1) with an input DC bias voltage (VDC), which input DC bias voltage (VDC) is adapted to keep the output DC bias current (IB1) constant during the variation of the first resistor (12).

It is known to add different kinds of variable gain amplifiers (VGA) in front of the voltage to current converter.
Patent publication GB 2 334 163 shows a variable transconductance amplifier comprising two transistors whose emitters are connected via resistors to a constant current source to form a differential or long tail pair. A feedback amplifier whose transconductance is controllable has inputs connected to the collectors of the transistors and outputs connected to the emitters thereof. The feedback amplifier thus supplies a differential current to the emitters of the transistors, which corresponds to the product of the differential output signal of the transistors and the variable transconductance of the feedback amplifier. The arrangement is said to improve the noise figure.
Patent publication US 2003/0062951 shows a mixer/amplifier capable of providing variable gain while maintaining a substantially constant common mode operating voltage level and maintaining a substantially constant operating voltage in new, low voltage designs, thus providing a mixer/amplifier in low-power direct conversion receiver.
A low noise amplifier is shown in which a gain control signal is provided through a differential current source. Two output currents I1 and I2 are provided. I1+I2=a constant. I1 and I2 are mirrored in first and second paths, one including amplifier transistors and optionally a Gilbert cell multiplier. Irrespective of amplifier gain, the current through the two paths remains equal to I1 and I2, and common mode voltage remains constant.

Voltage to current converter and method for converting


A microprocessor having a Precision Control (PC) field, an instruction dispatcher, and a Floating Point unit (FPU). The FPU receives an FP Add instruction from the instruction dispatcher, and generates a sum from its addends. The FPU determines whether any conditions exist in the addends with respect to their contribution to a rounding determination and relative to the PC field. If none of the conditions exists, the FPU makes the rounding determination based on the smaller addend and the PC field, and selectively rounds the sum based on the rounding determination. If any conditions exist, the FPU saves the sum and rounding information derived from the addends, and signals the instruction dispatcher to re-dispatch the instruction. On re-dispatch, the FPU makes the rounding determination based on the saved rounding information and the PC field, and selectively rounds the sum based on the rounding determination.

Floating point numbers are typically represented by a sign bit, an exponent, and a mantissa (also referred to as the significand) that contains the significant digits of the floating point number. For example, when representing a normalized floating point number in the IEEE Standard 754 for binary floating point arithmetic, the mantissa comprises an integer "1" and a fraction following a binary point.
The x87 architecture is a popular architecture for performing floating point arithmetic. The x87 architecture is described in the IA-32 Intel Architecture Software Developer's Manual, Volume 1: Basic Architecture, June 2006, which is hereby incorporated by reference in its entirety for all purposes (referred to herein as the "Intel manual"). In particular, section 4.8 describes the representation of real numbers in various floating point formats; chapter 8 generally describes programming with the x87 FPU; and section 5.2 describes the specific x87 floating point unit (FPU) instructions.
There are three different floating point formats that must be supported by an x87 FPU: single precision format numbers are 32 bits comprising a 1-bit sign, an 8-bit exponent, and a 23-bit mantissa; double precision numbers are 64 bits comprising a 1-bit sign, an 11-bit exponent, and a 52-bit mantissa; and double extended-precision numbers are 80 bits comprising a 1-bit sign, a 15-bit exponent, 1 integer bit, and a 63-bit mantissa. The precision of a floating point number is limited to the number of bits in its mantissa. Thus, given an implied integer '1' bit to the left of the binary point in the single-precision and double-precision formats and the explicit integer '1' bit to the left of the binary point in the double extended-precision format, the precision of a single precision format floating point number is limited to 24 bits, the precision of a double precision format floating point number is limited to 53 bits, and the default precision of a double extended-precision format floating point number is limited to 64 bits. However, the precision of calculations performed on double extended-precision format floating point numbers may be limited to less than 64 bits, and the precision limit is determined by the programmer. An x87 FPU includes a Precision Control (PC) field in its Floating Point Control Word (FPCW) that determines whether the precision of its floating point calculations are 64, 53, or 24 bits. A program may write to the PC field to change the precision of the x87 FPU floating point calculations. For example, if the program writes to the PC field to specify single precision, then the x87 FPU generates results with 24 bits of precision, even though one or more of the addends may have greater than 24 bits of precision. That is, the FPU rounds the mantissa of the result by clearing to zero the bits that are of less arithmetic significance than the precision specified by the PC field.
One common set of floating point arithmetic instructions executed by an x87 FPU are the addition (and subtraction) instructions. A floating point addition instruction performs the calculation of Ra+Rb, where Ra and Rb are floating point addends. The mantissa of Ra is denoted here as A, and the mantissa of Rb is denoted B. Assume Ra is the larger addend and Rb is the smaller addend, i.e., Ra has a larger exponent than Rb. The x87 FPU shifts B right by a number of bits equal to the difference between the exponents of Ra and Rb in order to align the mantissa of the smaller addend with the mantissa of the larger addend. The x87 FPU then adds mantissa A to the aligned mantissa B to generate a resultant sum. The FPU then normalizes the sum to remove any leading zeroes. Finally, the FPU performs a rounding operation on the normalized sum.
The rounding operation may be critical with respect to the timing of the execution of a floating point addition instruction by an x87 FPU. An FPU executes instructions according to a clock signal having a frequency and period. For a given semiconductor manufacturing process technology employed and FPU design (e.g., the number of gate delays required to execute the addition instruction), the clock period might have to be lengthened to accommodate the time to perform the rounding operation to execute the instruction. In the alternative, it is typical for an FPU to execute addition instructions in multiple clock cycles. In this case, it is desirable from a performance perspective for an FPU to execute floating point addition instructions in the smallest number of clock cycles possible given the clock period, the number of gate delays required by the FPU design to execute the instruction, the semiconductor manufacturing process technology employed, etc.
The rounding operation may be determinative of whether or not an additional clock cycle is required to execute a floating point addition instruction, i.e., whether the FPU can execute the floating point addition instruction in N clock cycles or N+1 clock cycles. This is because the rounding determination (i.e., whether the sum of the addends needs to be rounded up by incrementing) for an addition instruction by an x87 FPU depends upon the precision of the addends relative to the precision specified by the PC field of the FPCW. More specifically, the fact that the programmer could specify a precision via the PC field that is different than the precision of one or both of the addends could cause the rounding determination to take longer under some conditions than in others. There may be some conditions under which the longer time to make the rounding determination would cause the total execution time of the instruction to require an additional clock cycle. Thus, for example, whereas an x87 FPU could be designed to execute a floating point addition instruction in three clock cycles for a first set of conditions of the precision of the addends and the precision specified by the PC field, the FPU may require four clock cycles to execute the instruction for a second set of conditions of the precision of the addends and the precision specified by the PC field because the rounding determination takes longer for the second set of conditions. Following are some specific examples of conditions of the precision of the addends relative to the precision specified by the PC field and their affect on the rounding determination time.
If the precision specified by the PC field is the same as the precision of the addends, then only the smaller addend contributes bits to the rounding operation (referred to herein as sticky bits) due to the mantissa alignment discussed above. In this case, the rounding determination may be performed in parallel with the addition of the larger addend and aligned smaller addend by simply examining the sticky bits of the smaller addend, namely the number of least significant bits shifted right during the alignment operation. That is, the rounding determination time is mostly, if not all, hidden by the time taken to perform the actual addition of the two addend mantissas.
However, if the precision of the larger addend is greater than the precision specified by the PC field, then the larger addend may also contribute sticky bits to the rounding determination. In this case, the x87 FPU must add the sticky bits contributed by each of the two addends in order to make the rounding determination. The addition of the sticky bits may take as long as the addition of the non-sticky bits of the mantissa, i.e., the upper bits that are within the precision specified by the PC field. The x87 FPU subsequently examines the sticky bits sum in order to make the rounding determination after the addition of the mantissas. Importantly in this case, unlike the case in which only the smaller addend contributes sticky bits, the FPU cannot make the rounding determination in parallel with the addition of the larger mantissa and aligned smaller mantissa. Rather, the FPU must wait to make the rounding determination until the addition of the sticky bits has completed.
Much work has been done to perform fast floating point add operations. For example, see ON THE DESIGN OF FAST IEEE FLOATING-POINT ADDERS, Seidel, et al., IEEE Computer Society, Proceedings of the 15th IEEE Symposium on Computer Arithmetic (ARITH '01). However, this paper fails to take into account the requirements imposed upon a commercially-viable x87 FPU with respect to the ability of the programmer to specify the precision of floating point number calculations via the PC field. Specifically, the paper assumes that only one of the addends will contribute sticky bits to the rounding determination. However, as discussed above, the peculiarities of the x87 architecture, namely the PC field, can create situations where both of the addends contribute bits to the rounding determination. Depending upon factors such as the clock frequency of the microprocessor and the number of gate delays within the various circuits of the x87 FPU (e.g., adders, shifters, and control logic circuits), the additional time required to perform the rounding determination in some cases, such as where both addends contribute sticky bits, may in some designs be enough to require an additional clock cycle for the x87 FPU to execute a floating point add instruction or the clock cycle to be undesirably lengthened.
One solution to the problem is to have the FPU execute floating point addition instructions in a variable number of clock cycles. However, this solution is undesirable with respect to instruction scheduling, particularly within a superscalar, out-of-order execution microprocessor. Another solution is to simply take the same greater number of clock cycles (four in the example above) to execute all floating point addition instructions, regardless of the set of conditions. However, this solution is obviously not a high performance solution.
Accordingly, what is needed is a solution that generates correct results of an x87 floating point addition instruction in cases where the rounding determination is relatively long, such as where both addends contribute sticky bits to the rounding determination, and yet does not penalize the time to execute an x87 floating point addition instruction in cases where the rounding determination is relatively short, such as where only one addend contributes sticky bits to the rounding determination.

Apparatus and method for optimizing the performance of x87 floating point addition instructions in a microprocessor


A COX-2 selective inhibiting drug is disclosed as useful in treating or preventing prostate cancer. The compound is used alone or in combination with other drugs.

The present invention relates to the treatment or prevention of prostate cancer using cyclooxygenase-2 (COX-2) selective inhibiting drugs. Prostate cancer is the most common form of malignancy and second leading cause of cancer-related deaths among men in the United States. While conventional therapy for advanced prostate cancer can be paliative, patients having advanced prostate cancer generally relapse over time.
Cyclooxygenase-2 is a key enzyme in the conversion of arachidonic acid to prostaglandins and other eicosanoids. Cyclooxygenase-2 is the inducible form of the enzyme, cyclooxygenase-1 being constitutively expressed in many tissues and cell types.
Cyclooxygenase-2 expression can be induced by a variety of factors, including, for example, growth factors, interleukin-1 and tumor promoting factors. The enzyme is expressed in a number of tumor cells, and human cancers, among which is prostate cancer.
One object of the present invention is to provide a method of treating or preventing prostate cancer using a cyclooxygenase-2 selective inhibiting drug.
Another object of the present invention is to provide a treatment and prevention modality that is less toxic than conventional cancer chemotherapy, and less debilitating than conventional radiation therapy.
Another object is to provide a treatment and prevention means that is readily combinable with other treatment modalities such as radiation therapy, hormonal therapy, and surgery. These and other objects will be apparent to those of ordinary skill from the teachings herein.
A method of treating or preventing prostate cancer in a mammalian male patient in need thereof, comprising administering to said patient an amount of rofecoxib that is effective for treating or preventing prostate cancer.

Treatment or prevention of prostate cancer with a COX-2 selective inhibiting drug


A modular electronics enclosure for one or more circuit card assembly includes top and bottom lids formed substantially the same with at least one intermediate circuit card support member disposed therebetween. At least one spring clip clamps the top and bottom lids together around the intermediate support member.

1. Field of the Invention
The present invention pertains to an enclosure for electronics. In particular, the present invention pertains to a modular enclosure for housing electronic components. The modular container comprises interchangeable elements to expand or reduce the interior volume of the container.
2. Description of the Related Art
As seen in FIG. 1, conventional electronics enclosures 10 are typically constructed to include four sides 12, a top 14 and a bottom 16. In some instances, the bottom 16 is formed integrally with the sides 12. The top 14 and bottom 16, or top 14 only in the case of the latter, are then secured to the sides 12 in order to seal the enclosure and any circuit card assemblies therein.
Typical enclosures are sealed through a variety of methods. In one version, the top and bottom 12 and 14 are held in place around an intermediate section that forms or is integral with the sides 12 via a nut 20 and bolt 22 assembly. The bolt 22 passes through apertures or holes 24 in the corners of the top 12 and bottom 16, leaving the threaded end 26 accessible to thread a nut 20 thereon. The intermediate section may have matching passages 28 through which the bolt 22 passes in the walls and at positions corresponding to holes 24 in the top 14 and bottom 16. Alternatively, the top and bottom 14 and 16 have a skirt that extends beyond the outer perimeter of the intermediate section and the bolt passes through the top and bottom only; the intermediate section being securely held between the top and bottom.
Threaded fasteners have several disadvantages when assembling modules for housing circuit card assemblies. For instance, threaded fasteners increase the time required for assembly and disassembly of a modular enclosure; torque must be applied to each fastener for assembly, which requires additional verification to ensure the proper amount of torque has been applied. Thus, enclosure envelope size is often made larger than necessary for certain uses, in order to accommodate a sufficient number of appropriately sized fasteners to provide adequate clamping pressure. The increased clamping pressure is required to create a seal preventing the contamination of the enclosure from environmental conditions.
In addition to inspecting proper assembly torque application, each fastener must be inspected to make sure it is not missing, that they have been properly installed, and that any additional elements, e.g., lock washer, are also included.
The enclosures are designed to house one or more circuit card assemblies within. Normally, internal circuit card assemblies are fastened to the bottom 16 from the inside and/or are stacked one on top of each other. The circuit card assemblies are positioned and secured inside the enclosure with a required standoff distance from each other. The required distance is achieved by securing mounting bosses or similar hardware onto the mounting panel of the enclosure. When an enclosure contains fewer circuit card assemblies than it is designed to hold, a portion of the enclosure is wasted, and therefore decreases the packing efficiency of the enclosure. One shortfall is that space must be reserved to accommodate fasteners, (e.g., screw heads, washers) on both the upper and lower surfaces of the circuit card assemblies. Should a circuit card assembly be re-laid (i.e., turned), the pre-existing mounting boss locations may become an impediment to circuit routing and component placement. This design requirement is a significant limitation of the existing enclosure designs.
Yet another drawback of the prior art enclosures is the inability to provide adequate electromagnetic interference (EMI) shielding. EMI shielding is pre-planned to maximize efficiency and effectiveness of the enclosure. The efficiency and effectiveness of the pre-planned EMI shielding is reduced when less than the intended number of circuit card assemblies is housed within an enclosure.
Similarly, thermal transfer of heat and electrical grounding are achieved through contact with bosses and/or mounting screws and conveyed through the chassis. Those designs create hot spots and require heat sinks in the vicinity of the bosses to avoid damaging the circuit card assemblies.
In this respect, each enclosure is unique, allowing for very limited expansion of the enclosure to accommodate additional or different circuit card assemblies. Most modular enclosures of the prior art are specifically constructed to house a specific number of circuit card assemblies. This configuration restricts the flexibility of the enclosure to accommodate a varying number of circuit card assemblies.
Furthermore, a necessary characteristic of enclosures for circuit card assemblies is the ability to provide thermal conduction away from the circuit card assemblies. The prior art enclosures utilize mounting bosses to provide the necessary thermal conduction of heat generated on the circuit card assemblies, but the mounting bosses actually in turn transfer that heat to the enclosure structure itself.


‘LMV200’ is a distinctive variety of Lomandra hystrix which is characterized by the combination of an arched foliage habit and the presence of light yellow to green leaf variegation.

The present invention relates to a new and distinct perennial variety of Lomandra hystrix, which has been given the variety denomination of 'LMV200'. Its market class is that of an ornamental plant. 'LMV200' is intended for use in landscaping and as a decorative plant.
Parentage: In March 2005, seed from openly-pollinated Lomandra hystrix was sown at a commercial nursery operation in Limpinwood, NSW Australia. The resulting seedlings were potted and grown on as nursery stock. In November 2005 the variety now called 'LMV200' was selected from said seedlings for exhibiting leaf variegation whereas the parent plant and all other resulting progeny did not.
Asexual Reproduction: 'LMV200' was first propagated asexually by division in Limpinwood, NSW Australia and has since been propagated through 7 subsequent generations. The distinctive characteristics of the inventive 'LMV200' variety have proven to be stable from generation to generation; clones of the variety produced by asexual reproduction maintain the distinguishing characteristics of the original plant.


A plug-type connector includes a connector main body having a first end formed into a plug portion and an opposite second end formed into a pull portion; a pinch unit movably coupled to the pull portion, and having at least a vertical plate corresponding to an end face of the pull portion and a pinch plate perpendicularly extended from the vertical plate and corresponding to a back face of the pull portion; and an elastic element located between the back face of the pull portion and the pinch plate. Two plug-type connectors can be plugged in a two-leveled housing back to back. The connector main bodies are normally firmly connected to the housing by the pinch units, and any one of the two connector main bodies can be easily removed from the housing simply by pulling the pinch unit thereof without being interfered by the other pinch unit.

A conventional plug-type connector 5 as shown in FIGS. 1 and 2 includes a plug portion 51 formed at one end and a pull portion 52 formed at the other end thereof. A pinch plate 53 is movably provided to a back of the pull portion 52. Two pieces of the plug-type connector 5 can be simultaneously plugged in a two-leveled housing 6 back to back. By operating the pinch plates 53, the pull portions 52 of the plug-type connectors 5 can be firmly coupled to the two-leveled housing 6 or removed from the housing 6.
As having been mentioned above, the pinch plate 53 is located at the back of the pull portion 52. Therefore, when two plug-type connectors 5 are plugged in the two-leveled housing 6 back to back, the pinch plates 53 thereof would contact with each other at distal ends thereof. When it is desired to remove any one of the two plug-type connectors 5 from the housing 6 by pulling the pinch plate 53, the mutually contacting pinch plates 53 would prevent a user from conveniently pulling the desired pinch plate 53, and accordingly, it is uneasy to remove the plug-type connector 5 from the housing 6.
It is therefore tried by the inventor to develop an improved plug-type connector that can be easily plugged into and removed from a two-leveled connector housing.


A method of fabricating a semiconductor device that includes forming a gate stack layer including a metal-containing layer on a semiconductor substrate having an NMOS region and a PMOS region, introducing arsenic to the gate stack layer in the NMOS region, introducing aluminum to the gate stack layer in the PMOS region, and etching the gate stack layers, where the arsenic and the aluminum are introduced, to form a first gate structure and a second gate structure in the NMOS region and the PMOS region, respectively.

1. Field
Various exemplary embodiments of the present invention relate to a semiconductor device and, more particularly, to a semiconductor device with a transistor and a method of fabricating the same.
2. Description of the Related Art
As transistors in a semiconductor device are scaled down to improve performance, the gate dielectric layer gets thinner and gate leakage increases. To address this concern, the gate dielectric layer is replaced with a high-k material having a dielectric constant greater than the dielectric constant of silicon dioxide (SiO2). The high-k material may include a metal oxide containing hafnium, zirconium, etc. As the high-k material is introduced, a Fermi level pinning effect is caused by the contact between the high-k material and a polysilicon gate electrode. The Fermi level pinning effect is a characteristic of the interface between the polysilicon gate electrode and the metal oxide, and it increases the threshold voltage of a transistor.
Recently, a gate structure including a high-k material and a metal gate electrode have been utilized to address the Fermi level pinning effect. However, during the CMOS device fabrication process it may be difficult to form a metal gate electrode having an N-type work function and a P-type work function, which require an appropriate threshold voltage Vt for each transistor. Although a metal gate electrode having an appropriate work function for each transistor is formed, the work function of the gate structure may fluctuate due to the materials of the gate dielectric layer that contact the metal gate electrode, and various other factors originating from the gate stack formation process, such as an etch process and a high-temperature thermal process.

Semiconductor device with transistor and method of fabricating the same


An absorbent article is provided for use in the perineal area of the body having an absorbent core having an upper body facing surface, a lower garment facing surface, first and second longitudinal sides, and first and second transverse ends. A body fluid impervious sealing wrapper, having upper and lower portions each having longitudinally and transversely extending edges along which said portions are joined, is formed around the absorbent core so as to enclose at least the entirety of the garment facing surface, the longitudinal sides and the transverse ends, thereby forming a seal. A centrally disposed opening is formed in the upper portion of the sealing wrapper thereby forming a window on the body facing surface of the absorbent core that exposes it to fluid flow. A fluid pervious layer covers at least the portion of the body facing surface on which the window is formed. The upper portion of the sealing wrapper and the pervious layer are joined so as to form a laminated layer. In another embodiment, the window is formed in a fibrous non-woven fabric that covers the longitudinal sides of the absorbent core and the window is covered by an apertured plastic film.

Traditionally, absorbent articles have included a center absorbent portion having a body facing surface--that is, a surface that faces the perineum--, a garment facing surface, longitudinally extending sides and transverse ends. These articles generally include an absorbent core made of loosely associated hydrophilic materials, such as wood pulp. The body facing surface of the absorbent core is covered by a layer of body fluid pervious fabric, typically referred to as a "cover". The garment facing surface and the longitudinally extending sides of the absorbent core are enclosed by a layer of body fluid impervious material, typically referred to as a "barrier", that is preferably non-wicking and pervious to gases. These layers are sometimes sealed around the absorbent core by joining them together along their longitudinal and transverse edges so as to form flanges see, for example U.S. Pat. No. 4,678,527 (Ulman), assigned on its face to the same assignee as the current invention. In this arrangement, the cover and barrier each form a portion of the longitudinal sides of the center portion.
Alternatively, the barrier is sometimes formed into a C-shaped boat enclosing the garment facing surface and longitudinal sides of the absorbent core. In this case, the cover is wrapped around both the barrier boat and the absorbent core and the overlapping longitudinal edges of the cover are joined together--see, for example, U.S. Pat. No. 4,200,103 (Black et al.), assigned on its face to the same assignee as the current invention. This alternative method is sometimes referred to as "flow wrapping".
Unfortunately, these approaches to forming the coverings for the absorbent article suffer from several drawbacks. First, although the barrier is effective in preventing leakage through the garment facing surface and the longitudinal sides of the article, it does not prevent leakage through the transverse ends of the article, which are, at best, only partially enclosed by the barrier.
Second, more recently, the cover forming the body facing surface has been formed from an apertured plastic film. Such films give the surface of the article a feeling of dryness against the skin, as compared to the more traditional fibrous non-woven fabrics used for the cover. Although the apertured plastic film is most useful as a covering for the body facing surface that is in contact with the perineum--that is, the surface subjected directly to the fluid flow--typically, the cover also encloses the longitudinal sides of the article that bear against the user's thighs. Experience has shown that although the apertured plastic film feels dry against the skin even after having been subjected to fluid flow, contact against the user's thighs produces the hot and sticky feeling associated with plastics, rather than the more comfortable feeling associated with contact by a fibrous non-woven fabric.
Consequently, it would be desirable to provide an absorbent article that was enclosed by a body fluid impervious barrier on its transverse ends as well as its longitudinal sides. It would also be desirable to provide an absorbent article that had an apertured plastic film on its body facing surface but a fibrous non-woven fabric on it longitudinal sides where contact is made with the thighs.

Method of making an absorbent article having strike window


An improved writing implement holder adapted to be removably attached to headwear having a headband. The writing implement holder has an attaching member connected to a holding member to form a channel for holding a writing implement. The attaching member has a hook portion adapted for insertion into the headband of headwear, thereby removably securing the device to the headwear.

Devices which hold writing implements such as pencils and pens have existed for many years. For example, U.S. Pat. No. 803,464 (Beck) discloses a pencil holder and bookmark combination. U.S. Pat. No. 1,481,984 (Carnett) discloses a pencil holder designed to attach to the cover of a book. U.S. Pat. No. 3,983,602 (Barry) discloses a writing implement holder designed to attach to a safety helmet. U.S. Pat. No. 5,066,154 (Renaud) discloses a writing implement holder designed to attach to a security hat. Other patents, such as U.S. Pat. No. 5,829,103 (Allen) and U.S. Pat. No. 5,867,874 (Simpson) disclose a writing implement holder designed to attach to a hat.
None of the foregoing patents utilizes the apparatus of the present invention, which has significant advantages, as described below. Furthermore, no prior art pencil holder provides a hook portion adapted for insertion into the headband of a cap to secure the holder to the cap. While some prior art pencil holders attach specifically to headwear, such holders may be unreliable, unsecure or uncomfortable. The number and complexity of parts or elements of the prior art also makes manufacturing such devices costly. There is a need, therefore, for a reliable, comfortable writing implement holder that may be efficiently and inexpensively manufactured to securely hold a writing implement and allow for its easy retrieval.


A method and medialess personal computer system workstation (or LAN station as herein defined) adaptable for securing the system against attack on a secured network with which the LAN station is associated. A flag bit is set in system memory during a power on self test to indicate whether access may be had to certain security features of the system, and a procedure is described by which access to a network stored configuration setting program may be gained in order to install, change or remove a password used for securing the LAN station while avoiding passing the critical password data through the network.

Personal computer systems in general and IBM personal computers in particular have attained widespread use for providing computer power to many segments of today's modern society. Personal computer systems can usually be defined as a desk top, floor standing, or portable microcomputer that consists of a system unit having a single system processor and associated volatile and non-volatile memory, a display monitor, a keyboard, one or more diskette drives, a fixed disk storage, and an optional printer. One of the distinguishing characteristics of these systems is the use of a motherboard (also known as and occasionally mentioned herein as a system board, system planar or planar) to electrically connect these components together. These systems are designed primarily to give independent computing power to a single user and are inexpensively priced for purchase by individuals or small businesses. Examples of such personal computer systems are IBM's PERSONAL COMPUTER AT and IBM's PERSONAL SYSTEM/2 Models 25, 30, 35, 40, L40SX, 50, 55, 56, 57, 65, 70, 80, 90 and 95.
These systems can be classified into two general families. The first family, usually referred to as Family I Models, use a bus architecture exemplified by the IBM PERSONAL COMPUTER AT and other "IBM compatible" machines. The second family, referred to as Family II Models, use IBM's MICRO CHANNEL bus architecture exemplified by IBM's PERSONAL SYSTEM/2 Models 57 through 95. Early Family I models typically used the popular INTEL 8088 or 8086 microprocessor as the system processor. Certain later Family I and the Family II models typically use the high speed INTEL 80286, 80386, and 80486 microprocessors which can operate in a real mode to emulate the slower speed INTEL 8086 microprocessor or a protected mode which extends the addressing range from 1 megabyte to 4 Gigabytes for some models. In essence, the real mode feature of the 80286, 80386, and 80486 processors provides hardware compatibility with software written for the 8086 and 8088 microprocessors.
Beginning with the earliest personal computer system of the Family I models, such as the IBM Personal Computer, it was recognized that software compatibility would be of utmost importance. In order to achieve this goal, an insulation layer of system resident code, also known as "firmware", was established between the hardware and software. This firmware provided an operational interface between a user's application program/operating system and the device to relieve the user of the concern about the characteristics of hardware devices. Eventually, the code developed into a Basic Input/Output System (BIOS), for allowing new devices to be added to the system, while insulating the application program from the peculiarities of the hardware. The importance of BIOS was immediately evident because it freed a device driver from depending on specific device hardware characteristics while providing the device driver with an intermediate interface to the device. Since BIOS was an integral part of the system and controlled the movement of data in and out of the system processor, it was resident on the system planar and was shipped to the user in a read only memory (ROM). For example, BIOS in the original IBM Personal Computer occupied 8K of ROM resident on the planar board.
As new models of the personal computer family were introduced, BIOS had to be updated and expanded to include new hardware and I/O devices. As could be expected, BIOS started to increase in memory size. For example, with the introduction of the IBM PERSONAL COMPUTER AT, BIOS grew to require 32K bytes of ROM.
Today, with the development of new technology, personal computer systems of the Family II models are growing even more sophisticated and are being made available to consumers more frequently. Since the technology is rapidly changing and new I/O devices are being added to the personal computer systems, modification to the BIOS has become a significant problem in the development cycle of the personal computer system. For instance, with the introduction of the IBM personal System/2 with Micro Channel architecture, a significantly new BIOS, known as advanced BIOS, or ABIOS, was developed. However, to maintain software compatibility, BIOS from the Family I models had to be included in the Family II models. The Family I BIOS became known as Compatibility BIOS or CBIOS. However, as previously explained with respect to the IBM PERSONAL COMPUTER AT, only 32K bytes of ROM were resident on the planar board. Fortunately, the system could be expanded to 96K bytes of ROM. Unfortunately, because of system constraints, this turned out to be the maximum capacity available for BIOS. Luckily, even with the addition of ABIOS, ABIOS and CBIOS could still squeeze into 96K of ROM. However, only a small percentage of the 96K ROM area remained available for expansion. It has been believed that, with the addition of future I/O devices, CBIOS and ABIOS will eventually run out of ROM space. Thus, new I/O technology will not be able to be easily integrated within CBIOS and ABIOS.
Due to these problems, plus the desire to make modifications in Family II BIOS as late as possible in the development cycle, it became necessary to offload portions of BIOS from the ROM. This was accomplished by storing portions of BIOS on a mass storage device such as a fixed disk, preferably in a defined portion of such a disk known as a system partition. The system partition also stores an image of a system reference diskette, which includes certain utility programs used in establishing system configuration and the like. Since a disk provides writing as well as reading capabilities, it became feasible to modify the actual BIOS code on the disk. The disk, while providing a fast and efficient way to store BIOS code, nevertheless greatly increased the probability of the BIOS code being corrupted. Since BIOS is an integral part of the operating system, a corrupt BIOS could lead to devastating results and in many cases to complete failure and non-operation of the system. Thus, it became quite apparent that a means for preventing unauthorized modification of the BIOS code on the fixed disk was highly desirable. This was the subject matter of U.S. patent application Ser. No. 07/398,820, filed Aug. 25, 1989, and now U.S. Pat. No. 5,022,077 issued Jun. 4, 1991. The interested reader is referred to that patent for additional information possibly helpful in understanding of the invention here disclosed, and the disclosure of that patent is hereby incorporated by reference into this specification to any extent necessary to a full understanding of the inventions here disclosed.
With the introduction of IBM's PS/2 Micro Channel Systems came the removal of switches and jumpers from I/O adapter cards and planar. The Micro Channel Architecture provided for programmable registers to replace them. Utilities to configure these programmable registers or programmable option select (POS) registers were required. These, and other utilities to improve system usability characteristics along with system diagnostics, were shipped with each system on a system reference diskette.
Prior to initial use, each Micro Channel system requires that its POS registers be initialized. For example, if the system is booted with a new I/O card, or a slot change for an I/O card, a configuration error is generated and the system boot up procedure halts. The user is then prompted to load the system reference diskette and press the F1 key. A "Set Configuration Utility" can then be booted from the system reference diskette to configure the system. The Set Configuration Utility will prompt the user for the desired action. If the appropriate I/O card's descriptor files are loaded on the system reference diskette, the Set Configuration Utility will generate the correct POS or configuration data in non-volatile storage. The descriptor file contains configuration information to interface the card to the system.
With the phenomenal growth and use of personal computers in the world in recent years, more and more data or information is being collected and retained or stored in such systems. A lot of this data is sensitive in nature. In the wrong hands, data could become embarrassing to individuals, a company could lose a competitive edge, or sensitive data could be used to force payment for silence or lead to physical violence against individuals. As more users recognize the sensitive nature of data and its value, the more it becomes desirable to protect against such misuse. To protect themselves and the persons associated with the stored data, users are requiring incorporation of security and integrity features into the personal computers that they purchase.
Users are not the only people to recognize the sensitivity of the data being collected and stored. Governments are also enacting laws to enforce protection of sensitive data. One such government is that of the United States. It has recognized and responded to the gravity of the situation. The United States federal government has defined security levels and the associated requirements it takes to meet those levels, and provides a certification agency for personal computer manufacturers to submit products in order to see if the products meet the security level claimed by the manufacturer. The source for the Federal Requirements is the Department of Defense, Trusted Computer System Evaluation Criteria, DOD 5200.28 STD, 12/85, generally referred to as The Orange Book. The government has legislated that by Jan. 1, 1992 all data related to the government must only be processed and stored on personal computers with a minimum security level of C-2. For computer system hardware, the essence of the requirements is contained in the Assurance section, Requirement 6: "trusted mechanisms must be continuously protected against tampering and/or unauthorized changes . . . "
In yet another related development, personal computers have been joined together into networks in various ways and through the use of various schemes. In some such networks, personal computers are used essentially as "dumb" terminals communicating with a powerful host computer which may be of the large size known as a mainframe and which serves to provide large databases and as the location of residence of applications programs which will manipulate data. In other network arrangements, personal computers are used as "smart" terminals which obtain application programs and sometimes data from a central file server (which may be another personal computer equipped with a direct access storage device of large capacity and capable of operating at relatively quick data recovery speeds), manipulate or receive entry of data, and return data to the file server. In still other arrangements, a group of personal computers may share among the group resources available to one or more of the systems in the network, such as peripheral devices such as printers, scanners, modems, etc. and application program or data files located on various direct access storage devices each of which is more directly associated with a single one of the resource sharing personal computers. Many such network arrangements are known as a local area network or LAN (the latter acronym being a defined term for purposes of this description).
As the use of personal computers in a LAN has increased, it has been recognized that the expense of a machine used in such an environment can be decreased by removing from such a computer system elements which are more usually found in personal computers as defined hereinabove. As a result, personal computers lacking direct access storage devices such as hard drives and floppy disc drives have come into use. Such systems are often known as media-less systems or LAN stations (the latter phrase being a defined term for purposes of this description).
The use of personal computers in local area networks may give rise to yet another area of potential impact in that any given personal computer typically is configured for certain functions which are provided, with such configuring being done at least in part as a BIOS function. These functions may include (particularly where C-2 security is targeted to be achievable) controls over access to various secure levels of information. With a stand alone personal computer not associated with a LAN, autoconfiguration is known and conventionally occurs as part of a start up procedure and security features may include those of the first mentioned related applications (which are hereby incorporated by reference into this application to any extent necessary to a full understanding of the invention here described). With a computer associated with a LAN, such configuration may occur as a function of BIOS stored in the computer and accessed as part of the start up procedure. However, it may be desirable for configuration of a particular computer connected with a LAN to be automatically set by the LAN on power on for that computer. Specifically in the case of a LAN station connected into a LAN dealing with data to be secured, it is imperative that appropriate provision be made for the system owner to control any possibility of attack on the LAN through such a LAN station.

LAN station personal computer system with controlled data access for normal and unauthorized users and method


An aspect of the present disclosure is directed to a monorail system configured and arranged for displacing at least one maintenance device configured and arranged for machining substantially vertically extending surfaces. Another aspect is directed to a maintenance system consisting of at least one maintenance device which is displaceable on the monorail system.

The invention relates to a monorail system which can be assembled in a modular manner and has a plurality of rail segments, its use for displacing maintenance devices for machining essentially vertically extending surfaces, in particular ship hulls, and a maintenance system consisting of at least one maintenance device and the monorail system according to the invention.
In many areas of technology, it is necessary to examine and treat the surface of large construction areas, especially those made of steel. For example, the hull of ships must be protected against corrosion at certain intervals. For this purpose, old defective coatings are removed in a special process, so that the cleaned steel surfaces of the ship's hull can then be provided with a new coating. This process is referred to as "recoating".
In ship docks, maintenance devices are usually used to clean, paint and/or recoat ship hulls and/or ship superstructures. These maintenance devices are designed either as rigidly mounted large-area superstructures or as smaller mobile units which are moved along the surface to be machined, e.g. ship hull. Such a maintenance device can, for example, be found in EP 2 370 312 B1 of the applicant. These devices are usually either mounted on a motor vehicle, such as a truck, or on a rail system.
Rail systems are usually rigidly mounted on the dock, i.e. in a positive fit, or arranged within a track bed, so that the maintenance device has to compensate for differences in the distance between the rail system and the area to be machined. However, since the size and/or shape of the vessels vary and there is also an increasing distance between the maintenance device and the hull, particularly in the bow and stern areas of the vessel, the maintenance device on such rail systems must compensate for this distance in accordance with the prior art. Such rail systems are therefore extremely inflexible.


A double pipe cultivation system which enables the reduction of falling the mussels cultivated with the effect of vertical and horizontal forces that would occur due to wind, wave and tides that can be received in all directions in mussel farms established in sea and lake areas, and the losses that can occur due to similar reasons.

In the current techniques, buoy, main carrier rope on the sea surface, and similar methods are still frequently being used. In such methods, problems of the falling of the cultivated mussels are experienced due to the factors as the oscillation occurring due to wind, wave and tides, the friction between the ropes, continuous movement of the ropes and kinking.

Double pipe cultivation system for reducing losses occurring due to wind, wave and tide in mussel cultivation farms


Methods and devices for determining a load vector on an object are disclosed herein. An example method includes collecting location observations related to the object. The example method further includes filtering the location observations to determine an estimated model path. The example method further includes outputting a set of data from the estimated model path, wherein the set of data includes a model location, a model velocity, a model acceleration, and a model jerk. The example method further includes calculating a load vector from the set of data, scaling the load vector via a scaling index, and transmitting the scaled load vector to a remote device.

Warehouses, retail spaces, hospitals, daycares, laboratories or other venues often employ Radio Frequency Identification (RFID) technology to track various objects located therein. Products, packages, vehicles, people, scanners, and robots may all be tagged with an RFID tag. For example, athletes playing competitive sports may have RFID tags embedded within their equipment. An RFID positioning system located in the venue (e.g., stadium) may then track the athletes' location as they traverse the venue. Receivers may be positioned throughout the venue, such as in overhead locations, on walls, or other surfaces, and operated to identify the RFID tags on the athletes moving throughout the venue.
The receivers are connected to a network host computer or server. The specific location of any particular athlete in the venue is typically determined by having the host computer process the payloads and capture data from a plurality of the receivers and using triangulation/trilateration techniques. A conventional host computer may then use this location data to calculate other physical quantities related to the athlete (e.g., velocity, acceleration). However, conventional systems fail to adequately interpret various physical quantities when determining an overall physiological load experienced by an athlete. Consequently, there is a need for techniques to efficiently and accurately determine overall physiological load based upon physical quantities.

Estimating physiological load from location data


A plurality of pixel electrodes, TFTs to control the switching of the pixel electrodes, scan lines to supply scan lines to the gates of the TFTs, and data lines to supply image signals to the pixel electrodes via the TFTs when the TFTs are put into an ON state are provided on a substrate. A scan-signal supply circuit to line-sequentially supply the scan signals is further provided. The scan-signal supply circuit holds the scan signals to an intermediate potential for a predetermined period in the middle of changing the potential of the scan signals between a high potential that puts the TFTs into the ON state and a low potential that puts the TFTs into the OFF state.

1. Field of Invention
The present invention relates to electro-optical devices, such as liquid crystal devices. More particularly, the present invention relates to a type of electro-optical device that has transistors to control the switching of pixel electrodes arranged in a matrix and that performs active-matrix driving by sequentially supplying scan signals to scan lines provided for corresponding pixel rows, a drive device and a drive method which are preferably used for such an electro-optical device, and an electronic apparatus having such an electro-optical device.
2. Description of Related Art
The electro-optical device of this type has, in an image display area on a substrate, pixel electrodes, thin-film transistors (hereinafter "TFTs") to switch the pixel electrodes, scan lines to supply scan signals to the corresponding TFTs, data lines to supply image signals to the sources of the TFTs, storage capacitors connected to the pixel electrodes, and the like. Drive circuits, including a scan-line drive circuit to supply scan signals to the scan lines, a data-line drive circuit to supply image signals to the data lines, and a sampling circuit, are provided at peripheral regions located around the image display area.
More specifically, the scan-line drive circuit line-sequentially supplies a scan signal having a pulsed waveform for each scan line or each row. That is, scan signals are supplied such that, at the same time when TFTs that are connected to the mth row (m is a natural number) are turned off, TFTs that are connected to the (m+1)th scan line are turned on. In parallel, the data-line drive circuit supplies image signals to the respective data lines in each horizontal-scanning period so as to write the image signals to corresponding pixel electrodes from the sources of the TFTs that are turned on by the scan signals through the drains thereof. The supply of such scan signals and image signals then causes the writing of an image for one row in a single horizontal-scan period. In addition, the electro-optical device is configured such that the above write operation is sequentially performed on all the rows in a vertical scan period to thereby write an image corresponding to one frame.
However, since the TFTs, the scan lines, capacitance lines, the data lines, and the like are fabricated in gaps between the pixel electrodes that are arranged in a plain matrix, parasitic capacitances are generated between the pixel electrodes in the (m+1)th row and the drains of the TFTs, the scan lines, the capacitance lines, and the like in the mth row. As a result, when the TFTs in the (m+1)th row are turned on by using scan signals having a pulsed waveform at a moment when the TFTs in the mth row are turned off, a scan signal or the like in the (m+1)th row is introduced as noise into an image signal written into the pixel electrodes in the mth row. This causes the pixel potentials, which are essentially to be held by the corresponding pixel electrodes, to fluctuate. In particular, since the parasitic capacitances are different depending on pixel units, there is a problem in that pixel irregularities occur in an image that is eventually displayed.
Furthermore, the above problem becomes more severe as the pixel pitch is reduced so as to meet a common requirement for higher definition of a displayed image in the art, since the parasitic capacitances between the pixel electrode in the (m+1)th row and the drains of the TFTs, the scan lines, the capacitance lines, and the like in the mth row become relatively large as the pixel pitch is increased.
Additionally, the waveform of scan signals is rounded depending on the corresponding wire capacitances. Thus, the degree to which the waveform of scan signals is rounded is greater at the center portion, which is farther from the scan-line drive circuit, of the image display area than at a peripheral portion, which is adjacent to the scan-line drive circuit, of the image display region. Thus, the ON/OFF timings of the TFTs are different between the peripheral portion and the center portion, depending on the degree to which the waveform of the scan signals is rounded. As a result, the influences of noise due to the next row's scan signal that is introduced into an image signal when the TFTs are turned off, as described above, are also different from each other between the peripheral portion and the center portion. Thus, in particular, in order to prevent flicker and/or aging of liquid crystal and the like, when AC inversion driving in which a drive potential of each pixel electrode is inverted in each field period or the like is adopted, adjusting the potential of the opposing electrode such that no DC component is generated in a potential applied to the liquid crystal causes such a DC component to be generated at the peripheral portion. Conversely, adjusting the potential of the scan signal or the like such that no DC component is generated in a potential applied to the liquid crystal at the peripheral portion of the image display area causes such a DC component to be generated at the center portion. For these reasons, a problem occurs in that flicker is generated at the peripheral portion or the center portions.
Meanwhile, when the mth-row's scan line and the mth-row's TFTs that are driven therethrough are considered, the pulsed waveform of a scan signal affects the pixel potentials at the drains of the TFTs since parasitic capacitances exist between the scan line and the drains. Specifically, at a moment when the corresponding gates are turned off, a pulsed potential corresponding to a pulsed waveform in the scan line is superimposed as noise on the potential of an image signal and the resulting potential is held as a pixel potential. Thus, in this case, the influences of noise introduced to image signals are different from each other between the peripheral portion and the center portion, because the degrees to which the waveform of the scan signals is rounded are different between the peripheral portion and the center portion. As a result, potentials applied to the liquid crystal are different and the luminance levels are also different. A problem also occurs in that flicker is generated at either of the peripheral portion and the center portion. In order to reduce or prevent the generation of such flicker, Japanese Unexamined Patent Application Publication No. 6-110035 discloses a technique of shaping the rising waveform of a scan signal, not into a rectangular waveform, but into a ramp waveform or a stepped waveform. This approach, however, cannot prevent the generation of pixel irregularities and flicker which result from parasitic capacitances between the pixel electrodes in the (m+1)th row and the drains of the TFTs, scan lines, capacitance lines, and the like in the mth row.

Electro-optical device, drive device and drive method for electro-optical device, and electronic apparatus


The present teachings relate to an organic electroluminescent transistor with improved light-emission characteristics. More specifically, the present organic electroluminescent transistor has an emissive ambipolar channel including at least one layer of an n-type semiconductor material, at least one layer of a p-type semiconductor material, and at least one layer of an emissive material arranged between the layers of the p-type and n-type semiconductor materials, where the multilayer emissive ambipolar channel includes, among various layers, a layer of a p-type semiconductor material comprising a benzothieno-benzothiophene compound, and/or a layer of an emissive material comprising a blend material that includes an organic carbazole derivative as the host matrix compound and an iridium complex as the guest emitter.

Organic electroluminescent field effect transistors, also known as OLETs (Organic Light Emitting Transistors) are a relatively recent type of devices, that have characteristics and applications that make them particularly interesting. For example, compared to OLEDs (Organic Light Emitting Diodes), ambipolar OLETs have enhanced efficiency and luminosity, and also can afford the possibility of using low-cost production processes once they have been optimized.
Further details about the structure of an ambipolar OLET device may be found in European Patent No. EP 1609195. More specifically, EP 1609195 discloses a three-layer organic light emitting transistor having an emissive ambipolar channel that includes at least one layer of an n-type semiconductor material, at least one layer of a p-type semiconductor material and at least one layer of an emissive material arranged between said layers of p-type and n-type semiconductor materials. Further details about the applications and the functional characteristics of these devices may be found in R. Capelli et al., "Organic light-emitting transistors with an efficiency that outperforms the equivalent light-emitting diodes," Nature Materials, vol. 9, pp. 496-503 (2010). The three-layer organic light-emitting transistor disclosed in Capelli et al. has a layer of an n-type semiconductor material composed of 5,5′-bis((5-perfluorohexyl)thiophen-2-yl)-2,2′-bithiophene (DFH4T), a layer of a p-type semiconductor material composed of 5,5′-bis(3-hexyl-2-thienyl)-2,2′-bithiophene (DH4T), and a layer of an emissive material composed of tris(8-hydroxyquinolinato)aluminium:4-(dicyanomethylene)-2-methyl-6-(p-dimethylaminostyryl)-4H-pyran (Alq3:DCM).
Among different p-type semiconductor materials that have been reported in the literature, diacene-fused thienothiophenes, specifically, [1]benzo-thieno[3,2-b][1]benzothiophenes (BTBTs) and dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophenes (DNTTs) have been shown to exhibit high mobility, air stability, and good reproducibility. See e.g., M. J. Kang et al., "Two Isomeric Didecyl-dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophenes: Impact of Alkylation Positions on Packing Structures and Organic Field Effect Transistor Characteristics," Jpn. J. Appl. Phys., vol. 51, pp. 11PD04 (2012); and H. Ebata et al., "Highly Soluble [1]Benzothieno[3,2-b]benzothiophene (BTBT) Derivatives for High-Performance, Solution-Processed Organic Field-Effect Transistors," J. Am. Chem. Soc., vol. 129, pp. 15732-15733 (2007). In Ebata et al., a series of 2,7-dialkylderivatives of BTBT (Cn-BTBT) were synthesized and used to fabricate organic field-effect transistors (OFETs). The OFETs were evaluated under ambient conditions and thin films of Cn-BTBT derivatives were shown to provide mobilities higher than 10−1 cm2 V−1 s−1. In Kang et al., two isomeric dodecyl-dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophenes (2,9- and 3,10-C10 DNTTs) were shown to afford high-performance OFETs with an average mobility of 6.8 cm2 V−1 s−1 for 2,9-C10-DNTT, and an average mobility of 4 cm2 V−1 s−1 for 3,10-C10-DNTT.
European Patent Application Publication No. EP 2402348 describes dialkyl-substituted DNTTs and related selenium analogs. OTFTs fabricated with the described compounds showed mobilities close to 4 cm2 V−1 s−1. No BTBT compounds are described.
International Publication Number WO 2013/039842 describes various acene-fused thienothiophenes and related chalcogen analogs that are mono- or bis-substituted with branched alkyl. OTFTs fabricated with the described compounds showed mobilities close to 2.3 cm2 V−1 s−1. No BTBT compounds are described.
Each of the above-identified documents is silent as to the possibility of using BTBT compounds in an OLET device having a trilayer emissive ambipolar channel and how the performance of such OLET device may compare to a similar OLET device using DNTT compounds.
So far, all studies and characterizations have shown that ambipolar OLET devices have an enhanced luminosity, though obtained at bias conditions where the efficiency of charge current conversion into light emission is very low (in the order of 1×10−1%). Conversely, the device efficiency can be usually maximized by modifying its bias conditions but with detrimental effects on the luminosity. These emission characteristics limit the possible application fields when high brightness and high efficiency are simultaneously needed such as, for example, in the fields of light emitting displays, Point of Care biomedical applications, and photon sources integrated on photonic chips. Further improvements in electroluminescence intensity (from the order of nanoWatt (nW) to microWatt (μV) with constant device geometry) also is desirable.


An image forming apparatus includes an image carrier; an exposing unit that exposes the image carrier to light to form an electrostatic latent image on the image carrier; a developing unit that has at least a toner, and develops the electrostatic latent image formed on the image carrier as a toner image; a transfer unit that transfers the toner image onto a recording medium; a fixing unit that fixes the toner image transferred on the recording medium; an exposure-energy modulating unit that modulates exposure energy of the exposing unit; and a development-time detecting unit that detects operation time of the developing unit. The exposure-energy modulating unit modulates the exposure energy based on a result of detection by the development-time detecting unit.

1) Field of the Invention
The present invention relates to an image forming apparatus like a copying machine, a printer, a plotter, or a facsimile and a process cartridge used in the image forming apparatus.
2) Description of the Related Art
In recent years, image forming apparatuses like a copying machine and a printer have been widespread in the market. A color image forming apparatus is also being widespread in the market in accordance with colorization of documents.
In an electrophotographic system that is widespread as a system for an image forming system, a process described below is executed as a representative image forming process. First, a photosensitive member serving as an image carrier is uniformly charged by a charger and, then, exposure corresponding to image information is applied to the charged photosensitive member to cause a potential difference between a non-image portion and an image portion. Then, toner particles are deposited only on the image portion by a developing unit to form a toner image, which is transferred onto a recording medium such as recording paper or an OHP sheet directly or via an intermediate transfer member. When a color image is formed, toner images of respective colors are superimposed one on top of another by various publicly known methods. For example, the image forming process described above is carried out for each color to sequentially form color images of respective colors on a photosensitive member, and the toner images are sequentially transferred on to a recording medium directly or via an intermediate transfer member. Alternatively, toner images of plural colors are formed one on top of another on a photosensitive member to transfer the toner images collectively on to a recording medium directly or via an intermediate transfer member. Alternatively, toner images of respective colors are formed on plural photosensitive members, respectively, and the toner images are superimposed on a recording medium directly or via an intermediate transfer member at the time of transfer. A single color toner image or a color toner image formed on the recording medium is fixed on the recording medium in a fixing unit.
Incidentally, compared with the single color image, the color image is often colored in a background portion as well, which tends to increase a quantity of toner to be consumed for forming one image. The increase in a quantity of toner consumption is unfavorable from the viewpoint of a reduction in an environmental load.
From the viewpoint of an image quality, when a large quantity of toner is deposited on one pixel, a toner layer thickness per one pixel increases. Thus, dust of the toner tends to scatter when a toner image is transferred, and a dot area of the toner image tends to increase when the toner image is fixed. These phenomena occur even in the single color image and occur particularly conspicuously in the color image. As a result, sharpness of the images is hindered, which leads to deterioration of image qualities.
Moreover, in the color image, the number of colors of toners deposited on one pixel is different for each pixel. Thus, a thickness of a toner layer changes for each pixel and a rate of increase in the dot area also changes when the toner image is fixed. When a dot area per one pixel varies, granularity of an image worsens, that is, the image is roughened, which leads to deterioration of the image quality.
As conventional technologies for improvement of granularity according to a control of exposure energy, various systems are disclosed in, for example, Japanese Patent Application Laid-Open No. 2000-118036 and Japanese Patent Application Laid-Open No. 2003-54026. In the system disclosed in Japanese Patent Application Laid-Open No. 2000-118036, output energy of a light beam of an exposure device is controlled taking notice of optical potential attenuation characteristics of a photosensitive member. In the system disclosed in Japanese Patent Application Laid-Open No. 2003-54026, an exposure pattern is selected and used in a highlight portion.
On the other hand, when a developing unit is used for a long period of time, a toner inside the developing unit deteriorates due to mechanical and thermal stresses. In particular, an extraneous additive like silica coating the toner is buried in the toner surface or separated from the toner due to the stresses. This causes a problem in that charging characteristics and flow characteristics of the toner change and an image quality deteriorates. To cope with this problem, a system for preventing aged deterioration of a toner by specifying a shape and a particle diameter of an extraneous additive is proposed as disclosed in Japanese Patent Application Laid-Open No. 2002-196526 and Japanese Patent Application Laid-Open No. 2003-057864.
As effective means for improving an image quality, it is possible to reduce a quantity of toner to be deposited per a unit area of an image portion. In the following description, a weight of toner to be deposited per a unit area of an image portion is called M/A, which is used as a characteristic representing a quantity of toner to be deposited per the unit area.
The reduction in a quantity of deposited toner leads to a reduction in a quantity of toner consumption and a reduction in an environmental load. In addition, the-transfer dust and the increase in a dot area at the time when a toner image is fixed are controlled through the reduction in the quantity of deposited toner, and a dot area difference among pixels is also reduced. Moreover, deficiencies like deformation and curl of a recording medium due to a thickness of a toner layer are also reduced significantly. From such viewpoints, the applicant has been studied an improvement of an image quality and the like at the time when a quantity of deposited toner is reduced.
However, while the applicant carried forward the examination, the applicant noticed that, in an image forming process with a reduced quantity of deposited toner, granularity of an image deteriorated noticeably as an image forming apparatus was used longer, and an initial image quality could not be maintained. In particular, the applicant found that, as an image quality that changed with time, granularity in a highlight portion worsened compared with the initial image quality of the image forming apparatus.
The applicant observed a toner in a developing unit when the toner is in an initial period and when the toner is aged using an electron microscope (SEM). Then, although a state in which an extraneous additive coated the toner surface was observed in the initial toner, no extraneous additive was observed on the toner surface in the aged toner. This indicates that the extraneous additive was buried in or separated from the toner surface in the aged toner due to mechanical and thermal stresses as explained above concerning the conventional technologies.
The applicant carried out an experiment described below to investigate how the aged toner, in which the extraneous additive was buried or from which the extraneous additive was separated, affected an image quality.
First, the applicant prepared two types of developing units in an initial state and an aged state and set the developing units in an image forming apparatus to output images. In the developing unit in the aged state, in which a developer is inside the developing unit, images are created in an accelerated manner by idling of the developing unit with a single driving device for 120 minutes. In this case, the applicant sampled the toner and observed a coating state of the extraneous additive using the electronic microscope. Then, the applicant confirmed that a state of the toner surface was the same as that of the aged toner in the state in which the extraneous additive was buried in the toner surface or separated from the toner surface described above.
As image forming conditions, a resolution was set to 1200 dots/inch (dpi), a charging potential was set to −630 volts, a developing bias was set to −500 volts, a toner diameter was set to 5.5 micrometers, and a carrier diameter was set to 35 micrometers. Conditions for the experiment were set such that a quantity of deposited toner per a unit area M/A in a solid image on paper (a state in which a toner was deposited over the entire surface of the paper) was 0.45 mg/cm2.
Here, assuming that granularity, which was roughness of an image, was caused by fluctuation in a dot area in a half-tone dot, the applicant evaluated the fluctuation in the dot area to use the fluctuation as substitute for the granularity. In addition, to check contribution of deterioration in an image quality in respective processes, as evaluation of images, the applicant evaluated a dot image on a photosensitive member after development, a dot image on an intermediate transfer member after transfer, and a dot image on paper after fixing, respectively. In the evaluation of a dot area, the applicant photographed dot images in the respective processes using a digital microscope and binarized the images to thereby obtain respective dot areas in the half-tone dot. The applicant evaluated a standard deviation of the dot areas as an amount of fluctuation in the dot areas.
FIG. 6 shows an evaluation result in this case. The horizontal axis indicates the respective processes, and "after development", "after transfer", and "after fixing" represent an image on a photosensitive member, an image on an intermediate transfer member, and an image on paper after fixing. In addition, the vertical axis indicates a standard deviation σ representing fluctuation in a dot area. From FIG. 6, it is seen that a difference between an initial toner and an aged toner increases after transfer, which indicates that deterioration in an image quality is large in a transfer process when the aged toner is used. Consequently, it is considered that this deterioration in an image quality is promoted even after fixing to worsen granularity.
The applicant assumes a mechanism as described below concerning the deterioration in an image quality in the transfer process of a toner (aged toner) in which the extraneous additive is buried or from which the extraneous additive is separated from. Since the aged toner is coated with the extraneous additive in a small area on the toner surface compared with the initial toner, it is estimated that a non-electrostatic adhesive force of the toner adhering with the photosensitive member is large. Thus, although transfer efficiency falls, usually it is possible to adjust the transfer efficiency according to conditions like a transfer bias. However, in this case, the transfer efficiency is mainly adjusted using a pattern with a large quantity of deposited toner like a solid image. In this experiment, for the initial toner and the aged toner, transfer conditions are already adjusted such that a quantity of deposited toner in a solid portion on paper is fixed. However, since a dot image in a highlight portion has a transfer characteristic different from that in the solid portion, it is considered that proper transfer efficiency is not obtained.
The applicant considers the difference in transfer efficiency according to an image pattern as follows. It is found in conventional measurement or the like that a toner layer consisting of about two to three layers is formed in the toner image on the photosensitive member after development. Since a transfer electric field is applied in the transfer process, a force moving from the photosensitive member in a direction of the intermediate transfer member acts on the toner on the photosensitive member. In this case, the toner image is required to be at least electrostatically transferred with a force stronger than an adhesive force between the photosensitive member and the toner such that the toner is transferred entirely. Here, a simple model as described below is devised. First, in the case of the solid image, in the toner image on the photosensitive member, it is assumed that a toner layer in contact with a photosensitive member (OPC) is A, and a toner layer on the toner layer A is B as shown in FIG. 7A. When the toner layer shown in FIG. 7A is considered, an adhesive force between toners acts on the toner layer A and the toner layer B, and an adhesive force between a toner and a photosensitive member acts on the toner layer A and the photosensitive member (OPC). Usually, a non-electrostatic component is large in the latter adhesive force. Therefore, when the transfer electric field is weak or when a non-electrostatic force is large, the toner layer A portion remains on the photosensitive member in a large quantity. In other words, since the non-electrostatic force is large in the aged toner, a quantity of transfer residual toner in the toner layer A portion is large. Therefore, adjustment is performed such that a target quantity of solid deposited toner by intensifying the transfer electric filed or increasing an input quantity of deposited toner (toner layer B portion). However, it is well known that, to the contrary, application of an excessive transfer electric field deteriorates the transfer efficiency and causes deficiencies like scattering of a toner. Thus, it is necessary to set a quantity of solid deposited toner taking into account a target quantity of deposited toner and a target transfer rate in advance.
On the other hand, in the case of the dot image in the highlight portion, an area of the dot image is reduced and, unlike the solid image, an edge portion of the dot image affects the toner image on the photosensitive drum. Thus, it is considered that the toner layer B has an angle shape as shown in FIG. 7B in the toner image on the photosensitive drum. Although the same action as that in the solid portion acts in the transfer process, when the toner deteriorates and a non-electrostatic adhesive force increases, even if the toner layer is increased at the same rate as that in the solid image, an amount of the increase is small because the toner layer B has the angle shape. Thus, in the aged toner, even if there is a sufficient amount of solid image on paper, a quantity of transferred toner is not sufficient in the highlight dot image. It is considered that this worsens granularity with time.

Image forming apparatus and process cartridge


A stacked semiconductor apparatus includes a plurality of chips which are stacked one upon the other. One chip of the plurality of chips may be configured to generate a plurality of refresh period signals for performing refresh operations within the plurality of chips, and may be configured to transmit the plurality of refresh period signals to the plurality of chips excluding the one chip. The plurality of chips may respectively receive refresh period signals allocated to them according to chip ID signals, and may perform the refresh operations.

1. Technical Field
Various embodiments generally relate to a semiconductor apparatus, and more particularly, to a stacked semiconductor memory apparatus in which a plurality of chips are stacked.
2. Related Art
To improve the integration density of a semiconductor apparatus chips may be stacked and packaged making a 3D (three-dimensional) semiconductor apparatus. However, 3D semiconductor apparatuses have a maximum integration density limit.
One method of creating a 3D semiconductor apparatus is to implement a plurality of chips having the same structure by stacking them and connecting them all together with metal wires that are peripheral to the chips. With this configuration the plurality of chips may operate as a single semiconductor apparatus.
Another method of creating a 3D semiconductor apparatus is to implement TSV (through-silicon via) which pass through the plurality of stacked chips to electrically connect the chips. However, manufacturing 3D semiconductor apparatus that implement TSVs are subject to processing skews which may prevent the stacked chips from sequentially operating.

Stacked semiconductor apparatus for generating refresh signal


The present invention relates to a method for detecting a permeability or patency of a section of an extracorporeal tube which is inserted in a tube pump, a detection device for executing a method according to the present invention, a medical treatment apparatus which comprises at least one detection device and/or is in signal transmission with it or is connected for signal transmission with it, a digital storage medium, a computer program product as well as a computer program.

In addition to other fields of application, tube pumps are i.a. used in extracorporeal blood treatment such as dialysis to convey a fluid, in this case blood. Spring-loaded rollers which are to limit the maximum pressure of the pump—which additionally depends on the pump tube diameter—are state of the art. With increasing mechanical complexity of the pump rotor, the number of possible sources of failure usually increases, this is also true for tube pumps. Therefore, it is useful to check the proper functioning of the rotor. In WO 2010/020380 A1, a method is disclosed for monitoring the pump rotor during pump operation. Thereby, pressure gradients which are caused by the roller which is in mesh in the moment of observation are raised and compared with pressure gradients of other rollers. If deviations occur, a defect of the pump motor is concluded. A defect similarly affecting both (in the sense of all) rollers cannot, inherent to the functional principle, be detected. This is not the case using certain embodiments of the method according to the present invention. In such embodiments, defects and failures which lead to the improper performance of all involved displacers or the displacers which are checked for their functioning can advantageously also be detected. Such a failure can be—for example because of its tube diameter or material—the use of a tube which is not suitable for the concrete application. Further, such a failure can exist for example because of striations in the inner layer of the pump tube which can be caused through production faults. Because of the absolute measurements which are possible according to the present invention, which can be performed for each displacer independently from one another, a damage which can affect all displacers in the same way can be advantageously recognized.
As such one object of the present invention is to propose a further method for verification of the function of the displacers of a tube pump. In addition, suitable apparatuses, a suitable digital storage medium, a suitable computer program product and a suitable computer program are to be specified.
Thus, according to the present invention a method for detecting a permeability or patency of a section of an extracorporeal tube which is inserted in a tube pump and/or for verifying an occlusion effect of displacers of the tube pump on the tube, i.e. the flow rate in the longitudinal direction of the tube is proposed. The method according to the present invention encompasses the meshing of a displacer of the tube pump with the section of the tube in such a manner that the displacer reduces the permeability or patency of the lumen of the section for a fluid and/or the cross-sectional area of the section of the lumen. The method further encompasses building up, setting or effecting a first pressure or the effecting a first pressure change inside the tube on a first side of the section and/or the meshed displacer. Furthermore, the method according to the present invention encompasses measuring a second pressure or a second pressure change and/or evaluating a second pressure already measured or a second pressure change already measured respectively on a second side of the section and/or of the meshed displacer.

Method as well as apparatuses for detecting a permeability or patency in a tube which is inserted in a tube pump


A transmission beam control unit 8 changes a main beam direction of a radar transmission beam every predetermined number of transmission periods. A radar transmitting unit Tx transmits a radar transmission signal using the radar transmission beam of which the main beam direction has been changed. In a radar receiving unit Rx, an estimation range selection unit 22 selects an estimation range of the direction of arrival of a reflected wave signal by limiting the estimation range to the approximate transmission beam width on the basis of the transmission beam width of the radar transmission beam and the output from the transmission beam control unit 8. The direction-of-arrival estimation unit 23 estimates the direction of arrival of the reflected wave signal on the basis of phase information between a plurality of antennas according to the selected range.

A radar device transmits a high-frequency radar transmission signal from a measurement point to a space, receives a reflected wave signal reflected by the target, and measures at least one of the distance between the measurement point and the target and a direction in which the target is present (direction of arrival). In recent years, development of a radar device that estimates a direction of arrival or a distance to the target including a vehicle and a pedestrian by performing high-resolution measurement using a radar transmission signal with a short wavelength including a microwave or a millimeter wave has been carried out.
The radar device receives mixed signals of respective reflected waves from a target present at a short distance and a target present at a long distance. A range side lobe occurs in the reflected wave signal from the target present at a short distance. When the range side lobe and the main lobe of the reflected wave signal from the target present at a long distance are mixed, the detection accuracy of the target present at a long distance is degraded.
Therefore, it is required for the radar device, for which high-resolution measurement is required for a plurality of targets, to transmit a pulse wave or a pulse modulated wave using a transmission code having an autocorrelation characteristic for a low range side lobe level (hereinafter, referred to as a "low range side lobe characteristic").
When a vehicle and a pedestrian are present at the same distance from the measurement point, the radar device receives mixed signals of respective reflected wave signals from the vehicle and the pedestrian whose radar cross sections (RCS) are different. The radar cross section of the pedestrian is smaller than the radar cross section of the vehicle. That is, the signal level of the reflected wave signal changes with the distance or type of the target.
In contrast, even if a vehicle and a pedestrian are present at the same distance from the measurement point, the radar device is required to properly receive the respective reflected wave signals from the vehicle and the pedestrian. For this reason, the radar device is required to have a wide receiving dynamic range to the extent of receiving reflected wave signals having various signal levels.
For example, PTL 1 is known as a related art to detect a plurality of targets simultaneously with high azimuth resolution using a small number of antennas.


The accumulated change in values representative of actions taken by a processor, such as the number of email messages processed by an email server, in a given time period is determined. Actions are represented as data points on a plot. Look-ahead intervals are defined for each point. Candidate pairs of points are determined for each look-ahead interval by comparing the first value in the look-ahead interval with other values in the look-ahead interval. A candidate pair comprises the first point and another point having a lesser value. If a candidate pair has a value therebetween, the candidate pair is discarded. If, however, a candidate pair has no value therebetween, the first value of the candidate pair is a peak value for the look-ahead interval. The accumulated change is determined by calculating the sum of the peak values, plus the final value, minus the initial value, for the given time period.

It is not uncommon for the owner or administrator of a server to want to determine the accumulated change in the number of events processed by the server in a given time period. For example, an owner of an email service or the owner of a web site may want to determine the number of messages processed by each of its servers over a specific time period, and whether the number increases or decreases, and by how much, over extended time. This information is useful, for example, to facilitate load balancing of the servers and/or o determine the effectiveness of an advertisement on a web site.
This information can be determined by calculating the total (peak) number of events over a period of time and tracking the accumulated peaks. For example, the total number of events (e.g., action taken by a processor, messages processed) since a service started can be calculated. Each time the service is restarted, the total number of events (peak value) is reset to zero. The peak values can then be used to determine the accumulated change in the number of processed events. A typical approach to determining the peak values is to iterate through all data points by time and find the points that have an adjacent neighboring point with a lesser value. This approach can be slow and leads to low performance, especially if the number of data points and number of servers is large. Also, since the data is often saved in a data base, this search approach often leads to low performance query algorithms when the data set is large. Further, the data must be sorted by time before the search. Another common database query technique to solve this issue is to sort the data and add an order ID field. The order ID filed can then be used to group the adjacent points together and compare their values. This approach, however, requires extra space to save the temporary data. It also compares the value of every adjacent data point. This does not scale well for large data sets.

Determination of incremental value in server processed data