Described are method and apparatus for protecting content of a semiconductor non-volatile memory and a semiconductor non-volatile memory itself, the semiconductor non-volatile memory being constituted by, for example, a flash memory, so that a reduction in a life time of the non-volatile memory due to an excess number of times a refresh (rewrite) operation can be prevented. For example, a first data deterioration determining voltage V.sub.1 is applied via a row decoder to one of word lines to which a selected bit is connected to determine whether the selected bit is turned on and a second data deterioration determining voltage V.sub.2 is applied to the same word line to determine whether the selected bit is turned off. The results of the determinations are stored in a second memory unit. If the selected bit is turned on in the former result and is turned off in the latter result, a control circuit determines that the data in the selected bit is deteriorated and carries out the refresh operation for the selected bit. The value of V.sub.1 is set which falls in a voltage range from a relatively high threshold voltage to a rated power supply voltage (V.sub.CC) and the value of V.sub.2 is set which falls in a voltage range from the power supply voltage (V.sub.CC) to a relatively low threshold voltage.

a) Field of the Invention
The present invention relates to a semiconductor non-volatile memory such as a flash memory, EPROM, or EEPROM. More particularly, the present invention relates to a technology suitably applied to method and apparatus for determining a deterioration of stored data in the semiconductor non-volatile memory and refreshing the data deteriorated non-volatile memory so as to protect memory content of the non-volatile memory and the memory itself.
b) Description of the Related Art
A Japanese Patent Application First Publication (non-examined) No. Heisei 3-238697 published on Oct. 24, 1991 exemplifies a previously proposed single-chip microcomputer having a non-volatile memory such as EEPROM (Electrically Erasable Programmable Read Only Memory).
A semiconductor device disclosed in the above-identified Japanese Patent Application First Publication is constituted by a CPU (Central Processing Unit), a memory matrix, a timer, and a write circuit including a control circuitry. The CPU is connected to the memory matrix, the timer, and the write circuit which is connected to the memory matrix and the timer. The memory matrix is constituted by a plurality of memory cells of transistors and is constituted by a flash memory or Programmable ROM such as the EEPROM or EPROM (Erasable Programmable Read Only Memory). Each non-volatile memory transistor is constituted by a bit.
Each memory cell, i.e., each non-volatile memory transistor used in Programmable ROM is generally provided with a floating gate surrounded by an insulating film. In the PROM, a high threshold value voltage condition developed due to an injection of electrons toward the floating gate is a data write and a low threshold value voltage condition developed due to a draw out of the electrons from the floating gate is a data erasure.
Each memory cell, i.e., each non-volatile memory transistor used in Programmable ROM is generally provided with a floating gate surrounded by an insulating film.
In the programmable ROM, a high threshold value voltage condition developed due to an injection of electrons to the floating gate is a data write and a low threshold value voltage condition developed due to a draw out of the electrons from the floating gate is a data erasure.
However, in such a PROM as described above, the following three problems are raised. Consequently, it cannot be guaranteed that stored data in the PROM are continued to be stably retained. That is to say, at first, in a case where an environmental temperature of the PROM in use is considerably high, e.g., in a case where the PROM is used for an automotive vehicle purpose (is used in an engine compartment of the automotive vehicle), it becomes easy for charges within the floating gate to be vanished. This is called a worsening of a retention characteristic of the PROM.
Secondly, a disturb occurs which is caused by a voltage application to a corresponding bit line or a corresponding word line when the data is written into another bit or the written data is erased.
Thirdly, a soft write occurs which is caused by electrons injections into the floating gate when the data in the corresponding bit is read.
To cope with the above-described three problems, in the semiconductor device disclosed in the above-identified Japanese Patent Application First Publication, a refresh (rewrite) operation is carried out to prevent the stored data from being inverted (or reversed). This refresh operation will be explained below briefly.
The CPU supplies a data rewrite signal to the timer and the write circuit in accordance with a program stored in the memory matrix. At this time, the timer supplies a time duration required to rewrite the data in the respective bits of the memory matrix sequentially to the write circuit and, then, the write circuit sequentially rewrites (refreshes) the data in the respective bits. The refresh operation is carried out before the data in the respective bits in the memory matrix are vanished so that the data reversal can be prevented.

Method and apparatus for protecting content of semiconductor non-volatile memory and memory itself

1243-40 Kanasaki Showa-machi Kitakatsusika-gun Saitama 34401


Surgical apparatus for inserting a plastic, split end, adjusting ring into the stroma of the cornea of the eye wherein the adjusting ring includes, as a part thereof, a dissecting head to part the stroma and provide a pathway for the adjusting ring as the ring is rotated. The ends of the adjusting ring are moved to change the shape of the cornea to a desired shape in accordance with the desired visual correction after which the ends of the adjusting ring are fixably joined to maintain the desired shape.

This invention relates overall to an apparatus for adjusting the shape of the components of the eye and more particularly to making fixed changes in the corneal curvature. Deviations from the normal shape of the corneal surface produce errors of refraction in the visual process. The eye in a state of rest, without accommodation, focuses the image of distant objects exactly on the retina. Such an eye enjoys distinct vision for distant objects without effort. Any variation from this standard constitutes ametropia, a condition in which the eye at rest is unable to focus the image of a distant object on the retina. Hyperopia is an error of refraction in which, with the eye at rest, parallel rays from distant objects are brought to focus behind the retina. Divergent rays from near objects are focused still further back. In one aspect of hypertopia, the corneal surface is flattened which decreases the angle of refraction of rays as they pass through the refractive surfaces of the cornea, causing a convergence or focus of the rays at a point behind the retina. The retina is comprised partially of nerve fibers which are an expansion of the optic nerve. Waves of light falling on the retina are converted into nerve impulses and carried by the optic nerve to the brain to produce the sensation of light. To focus parallel rays on the retina, the hyperopic eye must either accommodate, i.e., increase the convexity of its lens, or a convex lens of sufficient strength to focus rays on the retina must be placed before the eye.
Myopia is that refractive condition in which, with accommodation completely relaxed, parallel rays are brought to focus in front of the retina. One condition which commonly causes myopia is when the corneal curvature is steepened, thus the refraction of rays is greater as they pass through the refractive surfaces of the cornea, and the over refracted rays converge or focus in front of the retina in the vitreous of the eye. When the rays reach the retina they become divergent, forming a circle of diffusion and consequently a blurred image. A concave lens is used to correct the focus of the eye for myopia.
The normal treatment of these classic forms of refractive error of the eye is with the use of eyeglasses or contact lenses, both of which have well-known disadvantages to the user. Recent research has been directed to operative techniques to change the refractive condition of the eye. Such techniques are generally referred to "keratorefractive techniques". Two such techniques are more particularly called keratophakia and keratomileusis. Keralomileusis involves the regrinding of a corneal lamella into a meniscus or hyperopic lens to correct myopia or hyperopia. A corneal optical lathe has been especially developed for this procedure and is also used in the keratophakia procedure, when a homograft ground into a convex lens is placed interlamellarly to correct aphakic hypermetropia. The homograft tissue (corneal lamella) is frozen with carbon dioxide. The homograft is cut as a contact lens would be, i.e., to the optical power required to effect the desired optical correction of the cornea. In keratomileusis, the anterior corneal lamella is shaped by the lathe and in keratophobia, it is the corneal stroma of a donor eye that is shaped by the lathe. These techniques have a broad application in the correction of high hyperopic and myopic errors. These procedures require radial cutting of the cornea about the periphery of the graft which weakens the cornea so that pressure from fluids below the incisions pushes up under the cuts and flattens the curvature of the cornea. This flattening of the cornea results in refractive errors to the eye not compensated for by the graft. Suturing in these operations also causes radial asymmetry of the cornea consequently promotes astigmatic error in this regard. Sutures also cause scarring of the corneal tissue, which scar tissue loses its transparency. Surgical correction of astigmatism is accomplished by asymmetrically altering the corneal curvatures. The effect of a peripherical distorting force may be easily visualized by imagining an inflated balloon with a spherical surface being compressed between the palms of the hands. Because the volume of air in the balloon is constant, the surface area remains constant. The previously spherical anterior surface is distorted meridianally as a result of compressing the diameter between the hands so that the curvature changes without changes the circumference of the surface. The meridian passing over the balloon between the extended fingers steepens, while the uncompressed meridian at right angles thereto flattens as its diameter lengthens in proportion to the shortening of the compressed diameter. This demonstrates the effect that may result from slight variations in the symmetrical patterns or intentional asymmetrical patterns attempted to be accomplished during surgical procedures and attendant suturing. It is thus seen that present procedures in keratorefractive techniques are best limited to situations where other more standard corrective practices are found ineffective. It is readily seen that the limiting factors in such surgical techniques is the gross complexity involved not only with multiple incisions in corneal tissue for affecting the procedures but also complex suturing patterns, resulting in gross restructing of the eye. The eye is thus faced with a difficult job of adjusting to this trauma.


A calorimetric hydrocarbon gas sensor (10) includes an electrochemical oxygen pump (18), a sensing element (12), and a multi-layered substrate (26) separating the sensing element (12) from the electrochemical oxygen pump (18). The multi-layered substrate (26) includes a plurality of overlying insulating layers, in which at least one intermediate layer (60) supports a first primary heater (58), and in which another intermediate layer (52) supports a temperature compensation heaters (50a, 50b). The primary heater (58) functions to maintain the calorimetric hydrocarbon gas sensor (10) at a constant, elevated temperature, while the active compensation heater (50a) functions to maintain substantially equal temperatures as determined by the thermometers (46a, 46b) located on an intermediate layer (48) overlying the compensation heaters (50a, 50b). Control circuitry is integrated with power measurement circuitry to measure differences in the heat produced by the compensation heater (50a) and the thermometer (46a) in an active region (100), and the heat produced by the compensation heater (50b) and the thermometer (46b) in a reference region (102).

Sensors for the detection of particular compounds present in a high temperature gas stream find numerous applications in many different mechanical systems. For example, detection of certain compounds in a high temperature gas stream is important in industrial emission monitoring for detection of gas pollutants, such as sulfur dioxide (SO.sub.2), in residential heating systems for detection of carbon monoxide (CO), and in automobile exhaust systems for various compounds including hydrocarbons.
In automotive applications, gas sensors can be placed at various locations in an exhaust system. Exhaust gas from an internal combustion engine typically contains hydrogen (H.sub.2), carbon monoxide (CO), methane (CH.sub.4), carbon dioxide (CO.sub.2), nitric oxide (NO), water (H.sub.2 O), and nonmethane hydrocarbons (C.sub.n H.sub.m), where n is an integer larger than 1 and m is an integer whose value depends upon the kind of hydrocarbon compound, for example, alkane, alkene, alkyl, or aryl. Important environmental pollution concerns dictate that the emission of hydrocarbons be minimized. To minimize pollutants in the engine exhaust, sensors can be placed before and after the catalytic converter to monitor the performance of the converter. Also, the emission of hydrocarbons can be controlled, in part, by an engine exhaust control system that receives a feedback signal from an exhaust sensor capable of selectively detecting the presence of hydrocarbons in the engine exhaust.
One method for monitoring the performance of a catalytic converter includes the use of oxygen sensors within the exhaust gas system. By measuring the amount of oxygen in the exhaust gas entering and exiting a catalytic converter, an estimate of the amount of oxygen stored in the catalytic converter can be made. Since oxygen storage capacity is necessary for a catalytic converter to oxidize hydrocarbons and reduce nitrogen oxide, an indirect measurement of the pollution control efficiency of the catalytic converter can be made by determining the amount of oxygen stored within the catalytic converter at any given point in time. Accordingly, by estimating the amount of oxygen stored within the catalytic converter, an indirect measurement of the catalytic converter efficiency can be obtained. Although oxygen sensors are relatively simple to manufacture, using oxygen measurements to estimate catalytic converter performance is imprecise.
A sensor that directly estimates the hydrocarbon concentration in an exhaust gas stream can be used to provide a more precise determination of catalytic converter efficiency. For example, several types of sensing elements have been developed for detecting various chemical species within an exhaust gas stream. These sensing elements includes calorimetric sensors having a catalyst coating, semiconductor metal oxide based sensors, and the like. Calorimetric hydrocarbon gas sensors measure the amount of heat released by the catalytic oxidation of hydrocarbons contained within the exhaust gas. To obtain optimum sensitivity for the measurement of hydrocarbon species within an exhaust gas, a calorimetric hydrocarbon gas sensor must be designed to maintain a relatively constant internal temperature. This requirement is especially important given the wide temperature variations encountered in an exhaust gas system, together with the need to internally generate oxygen for catalytic combustion within the sensor.
While providing a measurement of hydrocarbon concentration, a calorimetric hydrocarbon gas sensor must be carefully designed for operation in a high temperature exhaust gas stream. For precise measurement of hydrocarbons in an exhaust gas, small temperature rises, or small quantities of liberated heat, must be detected when the hydrocarbons are oxidized within the sensor. Detection these small variations can be difficult when exhaust gas temperatures are rapidly changing and subjecting the sensor to a variable temperature environment. For example, automotive engine operation is dynamic and the exhaust gas temperature varies from ambient temperature, at engine start-up to more than 1,000.degree. C. during periods of high power operation. Thus, in calorimetric hydrocarbon gas sensor technology for applications to high temperature exhaust gas systems, a major technical challenge involves thermal management within the gas sensor.
In addition to the need to accommodate thermal variations within the exhaust gas, calorimetric sensors require an oxygen source for the catalytic oxidation of the hydrocarbons. Typically, the oxygen supply systems used in calorimetric hydrocarbon gas sensors must operate at elevated temperatures. High temperature operation is necessary to attain the level of efficiency needed to supply sufficient oxygen to the catalyst within the sensor. The necessity of including an oxygen supply system adds additional design constraints for a calorimetric hydrocarbon gas sensor. Thus, improved thermal management is needed within a calorimetric hydrocarbon gas sensor designed for the measurement of hydrocarbons in an exhaust gas stream.


A liquid crystal display is provided. A liquid crystal display includes: a first substrate; a thin film transistor disposed on the first substrate; and a first electrode disposed on the thin film transistor and connected to an output terminal of the thin film transistor, wherein the first electrode includes a first region and a second region each including a plurality of minute branches separated from each other by open parts, portions of at least two minute branches among the plurality of minute branches are connected to form a plurality of minute plate branches, and wherein the minute plate branch has a wider width than a minute branch.

Field of the Invention
Exemplary embodiments of the present invention relate to a liquid crystal display.
Discussion of the Background
A liquid crystal display panel, which is one of the more common types of flat panel displays currently in use, includes two sheets of substrates with field generating electrodes such as a pixel electrode and a common electrode, and a liquid crystal layer interposed therebetween.
The liquid crystal display generates electric fields in the liquid crystal layer by applying voltages to the field generating electrodes, determines the alignment of liquid crystal molecules of the liquid crystal layer by the generated electric field, and controls polarization of incident light to display images.
The liquid crystal display also includes a switching element connected to each pixel electrode, and a plurality of signal lines including gate lines and data lines to apply the voltage to the pixel electrode by controlling the switching element.
Among the liquid crystal displays, a vertically aligned mode ("VM mode") liquid crystal display in which long axes of the liquid crystal molecules are arranged to be vertical to a display panel in the absence of an electric field has been in the limelight due to its high contrast ratio and wide viewing angle thereof.
Among the vertical alignment (VA) mode LCD devices, the liquid crystal display of a SVA (super vertical alignment) mode controls a liquid crystal direction through a vertical electric field and a horizontal electric field by using an electrode pattern having a minute slit structure, thereby increasing transmittance.
However, in the liquid crystal display of the SVA mode, spots may be generated because of non-uniform luminance while reducing an interval of the minute slits or minute branches.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.


A circuit and method for testing address uniqueness of a memory array are disclosed. The circuit includes a plurality of current sinks associated with rows and columns of the memory array. A plurality of word lines of the memory array are coupled to the plurality of current sinks. A current mirror circuit is coupled to the plurality of current sinks and a circuit output node is coupled to the current mirror circuit. The circuit output node is configured to compare a total current from tested word lines of the memory array with a predetermined reference current, and to output a test pass or test fail indication in response to the comparison.

1. Field of the Invention
The present invention relates to testing memory arrays. More particularly, the present invention relates to a high speed method and circuit for testing non-volatile memory devices for address uniqueness.
2. Background Information
A conventional address uniqueness test in memory devices is a significant test in the memory device manufacturing process. Due to silicon defects in the address path, stuck-at-faults occur in the address path, which can cause address uniqueness to fail. The address uniqueness testing is done to screen bad components in a memory device having address uniqueness failure even before testing for the more time consuming memory program or erase write or read testing.
One such conventional technique of address uniqueness testing involves writing to and reading from the memory. In order to cover all the addresses, all address locations are written and read with unique data bytes. In another conventional technique, the method of uniqueness testing involves a single latch/flip-flop per word line and column line output that stores the state of the word line or column line. The word or column line is then serially sent to logic to identify if one and only one address is enabled. In yet another conventional case, the method involves the use of a ladder-like series configuration of transistors built over the rows and columns of the memory array.
FIG. 1 illustrates a circuit diagram 100 of a four word line ladder structure 115. The ladder structure 115 comprises a plurality of transistors (referenced as 101, 102, 103, 104, 105, 106, 107, 108, 109, 110 and 111) arranged in vertical and horizontal legs fed by an input coupled to a ground terminal (Vgnd). The output of the ladder structure 115 serves as inputs to a read out logic 112 (AND gate) via a parallel leaker resistance circuit that is charged by a power supply (Vpwr). The leaker resistance circuit comprises a first resistor leaker_0 113 and a second resistor leaker_1 114. The first leaker resistor 113 is further coupled to an input of the read out logic 112 via an inverter 116. The leaker resistance circuit is powered by a supply voltage (Vpwr). The gates of the transistors in the ladder structure 115 are controlled by word lines (W0, W1, W2, W3, W0b, W1b, W2b and W3b). The ladder structure 115 is triggered by a signal Vgnd from the top of the ladder structure through the horizontal and vertical legs to overcome a weak power supply signal (Vpwr) triggered through the second resistor leaker_1 114. The signal Vgnd further enables the read out logic 112 to identify one of the three ideal operating conditions of the word lines and to thereby provide an output (Pass/Fail) for the address uniqueness test. The three operating conditions for determining memory address uniqueness are: no word lines active; one word line active; and two or more word lines active.
The conventional methods for address uniqueness tests have limitations in terms of longer testing time and parallel operation of sensing and writing circuitries. Although the testing is done for address uniqueness alone, it may also show problems related to memory storage space and limitations of the ladder structure 115 with reference to speed for higher density memories.
It would be desirable to have an improved method and an analog circuit for address uniqueness test in memory devices, which will significantly decrease test time for high density non-volatile memories.

High speed circuit and a method to test memory address uniqueness


An imaging apparatus has a primary media tray, a priority media feed tray, and a media feed mechanism configured to extract media from the priority feed tray and the primary media feed tray. The imaging apparatus further includes a priority media release device configured to selectively block media in the priority feed tray from being released to the media feed mechanism, and admit media in the priority feed tray to the priority media feed mechanism. In one configuration the priority media release device has a priority media release member selectively moveable from a first position to block media in the priority feed tray from the media feed mechanism, to a second position to admit media in the priority feed tray to the media feed mechanism.

The present invention addresses a common problem encountered by users of imaging apparatus. More specifically, the present invention provides for methods and apparatus to reduce the likelihood that special imaging media is printed with the wrong print job.
Imaging apparatus, as the term is used herein, include printers (such as self-standing units and table-top computer printers, for example), photocopiers, and other apparatus which are configured to generate an image on imaging media. Non-limiting examples of imaging media include paper, transparencies, card stock, envelopes, and labels. The present invention is particularly useful for imaging apparatus which generate an image on imaging media using a digital file (a "print file") as the image source. The invention is also particularly useful for imaging apparatus which are used in a shared manner within a computer network. That is, a computer network can include a central server which is configured to direct print jobs from a number of different user stations to a central imaging apparatus. (A "print job" is a digital file containing instructions to allow the imaging apparatus to generate an image, such as text and/or graphics, on imaging media.) The user stations can be, for example, computer workstations or desk-top computers. The network configuration thus allows a plurality of users to access one or more imaging apparatus, reducing the number of imaging apparatus required to support all of the users.
Imaging apparatus are generally configured with one of more primary media trays. (Imaging media trays are commonly known as "paper trays", although the use of the term should not be considered as limiting the type of media contained in the tray.) For example, an imaging apparatus can have a first paper tray configured to hold letter-sized paper, and a second paper tray configured to hold legal sized paper. In addition to the primary media tray(s), an imaging apparatus can include a priority imaging media tray, also known sometimes as a bypass tray. The priority tray allows a user to print a print job on specialty imaging media (i.e., imaging media not contained in the primary tray(s)) without having to remove the imaging media in the primary tray(s). For example, a user may desire to print an address on an envelope, or print a sheet of adhesive labels. Accordingly, the user will load the desired specialty media into the priority media tray, and then print the desired image onto the specialty media.
Many prior art imaging apparatus which contain a priority media tray are configured to require an additional drive mechanism to allow the user to associate a print job with the media within the priority tray. This is accomplished by providing the imaging apparatus with a priority tray media detection device (such as a switch or a sensor) which detects the presence of media within the priority tray. When media is detected in the priority tray, the imaging apparatus actuates media feed components (mostly comprising feed rollers) to pull media from the priority tray, and to print the next-received print job onto that media. Other prior art imaging apparatus have only a single feed mechanism comprising a feed roller which picks or feeds media from a common feed area. In this configuration, both the primary media tray and the priority media tray position media in the common feed area, and the feed roller thus feeds the next sheet of media presented to the roller. A problem with this configuration is that the user can insert specialty media into the priority tray, but then may send a different print job (i.e., a print job not intended to be imaged onto the specialty media) to the imaging apparatus, forgetting that the imaging apparatus has been loaded with specialty media. The result is that the print job is imaged onto the specialty media, when it was not intended to be. That is, since the imaging apparatus has no way to differentiate one type of media from another, the next print job received by the imaging apparatus will be imaged onto the media in the priority tray, whether it was intended to be or not. This results in wastage (primarily of the specialty media), as well as lost time since the user will need to reprint the print job once it has been discovered that the print job was imaged onto the wrong media.
What is needed then are methods and apparatus to allow the use of a priority media tray with an imaging apparatus which achieves the benefits to be derived from similar prior art methods and apparatus, but which avoids the shortcomings and detriments individually associated therewith.

Methods and apparatus for providing imaging media in imaging apparatus

Hewlett-Packard Development Company, L.P.


Various embodiments provide an interface between a Web browser's layout engine and a scripting engine. The interface enables objects from the layout engine to be recognized by a memory manager in the scripting engine and interact in a streamlined, efficient manner. In accordance with one or more embodiments, the interface allows browser layout engine objects to be created as objects that are native to the scripting engine. Alternately or additionally, in some embodiments, the native objects are further configured to proxy functionality between the layout engine and the scripting engine.

Over time, Web pages have evolved to include complex operations that can alter and/or modify a document being rendered in a host environment. In order to achieve some of these complex operations, Web programmers can utilize scripting languages to work within the host environment and with the document being rendered. Many host environments distinguish between a layout engine, which facilitates the rendering of a document, and a scripting engine, which executes script included in an associated Web page. Scripts running in the scripting engine can be designed to access not only the document being rendered in the layout engine, but objects and/or elements within the document. In some cases, when a layout engine supports standardized document access, such as a Document Object Model (DOM), a Web programmer can write a script to manipulate a document and its elements based upon this model.
A layout engine and a scripting engine provide different functionality from one another and, as such, they typically reside, on some level, in separate modules. This can range from a simple logical separation to a more complex separation between software and/or hardware components. More often, these engines reside in separate and/or associated software modules that communicate with one another. One benefit of this separation is that it enables a layout engine to more easily support multiple scripting engines. However, since the layout engine is separated, on some level, from a scripting engine, communication mechanisms between the modules oftentimes limit what can be exposed between the modules, can adversely affect runtime performance, and can introduce unintended memory management issues.

This patent is subject to a terminal disclaimer.

Security model for a layout engine and scripting engine


A linearity coil of a horizontal deflecting circuit includes a core; a winding connected in series to a horizontal deflecting coil and wound on the core; and a pair of permanent magnets respectively fixed to both ends of the core in the direction of increasing a magnetic force line induced to the core.

1. Field of the Invention
The present invention relates to a linearity coil of a horizontal deflecting circuit, and more particularly, to a linearity coil which can increase its core saturation quantity.
2. Description of the Related Art
The present inventor has participated in the development of a semiwide screen television. Since the screen of a semiwide screen television is longer in the horizontal dimension than the screen of a general standard television by about one inch, an improvement in a horizontal deflecting circuit has been demanded. If a linearity coil connected in series to a horizontal deflecting coil is small in its core saturation quantity, a right edge portion of the screen becomes "loose" ("loose" meaning that the horizontal dimension is increased as shown in FIG. 4C, or in other words, the horizontal scanning velocity of an electronic beam is decreased) compared with a left edge portion thereof because of weak linearity, and the screen is therefore distorted. To solve such a problem, in a conventional standard television, a permanent magnet 14 is fixed to one end of a core 12 of a linearity coil 10, as shown in FIG. 1. In spite of a solution for this problem, in the semiwide screen television, the right edge portion of the screen still has a distortion problem according to an increase in the horizontal dimension of the screen.

Linearity coil of horizontal deflecting circuit


The voltage regulator comprises a regulation loop (2), which comprises at least a pass transistor (18), a source transistor (28), a sensing transistor (22) and a retention transistor (24), and a stability compensation circuit (10), which comprises a first MOS resistor (12) and a second MOS resistor (14) coupled with the first MOS resistor (12). The gate of the second MOS resistor (14) is coupled to the gate of the pass transistor (18).

A low dropout or LDO regulator is a DC linear voltage regulator which can operate with a comparatively small input-output differential voltage. In general, such regulators feature a comparatively low dropout voltage and a comparatively low minimum operating voltage, further having a high efficiency operation and comparatively low heat dissipation. Typically, such regulators comprise at least one field effect transistor (FET) which is typically implemented by a metal oxide semiconductor component.
Low dropout regulators are of particular interest when it comes to efficient power management in battery operated portable consumer products. The fundamental design challenge in an LDO is to stabilize it over a zero load current (no load) to a maximum load current (full load) that is required for a particular application. Moreover, LDO regulators should exhibit a stable and fast transient response to load modifications. More specifically, a transient voltage peak in a controlled output of the LDO should not exceed a maximum voltage range both during dynamic load current steps and large current spikes inherent to digital load circuitry.
Typically, LDO regulators also comprise at least one capacitor, e.g. for a dominant pole frequency compensation at the output of the regulator. A non-ideal behavior of such a capacitor can be modeled with an equivalent resistance which typically generates a zero in the loop transfer function of the LDO regulator. Crucial drawbacks of prior art solutions arise from the fact that the LDO stability critically depends on the value of the equivalent resistance, which does not only depend on the manufacturer of the capacitor but also varies with an operating frequency and temperature. The equivalent resistance of such LDO regulators therefore imposes a stability problem.


Systems and techniques relating to IQ mismatch estimation and compensation are described. A described technique includes obtaining samples of a received signal via circuitry having an IQ mismatch; determining an estimated gain imbalance parameter for the IQ mismatch based on an in-phase average value of in-phase training samples and a quadrature average value of quadrature training samples; determining an estimated phase imbalance parameter for the IQ mismatch based on a combined average value, the estimated gain imbalance parameter, and a squared average value, the combined average value being based on a pair-wise multiplication of the in-phase training samples and the quadrature training samples, the squared average value being based on squared versions of the in-phase training samples; updating the in-phase data samples based on the estimated gain imbalance parameter to produce updated in-phase data samples; and updating the quadrature data samples by respectively adding quadrature update values thereto.

Communication devices can use analog quadrature down-mixing on a received signal to produce signals on an in-phase (I) branch and a quadrature (Q) branch. Due to hardware imperfections or differences between the I and Q branches, there may exist an in-phase/quadrature (IQ) mismatch between the I and Q branches. Devices can use one or more techniques to estimate and compensate for the IQ mismatch. Such techniques can include blind estimation, non-blind estimation, adaptive estimation, or non-adaptive estimation.
Devices such as wireless communication devices can use one or more wireless communication technologies such as orthogonal frequency division multiplexing (OFDM), code division multiple access (CDMA), or direct-sequence spread spectrum (DSSS). Wireless communication devices can communicate based on one or more wireless standards such as Bluetooth, wireless local area network (WLAN) standards such as IEEE 802.11 standards, or a ZigBee standard. Various examples of wireless communication devices include mobile phones, smart phones, wireless routers, wireless hubs, base stations, and access points. In some cases, wireless communication electronics are integrated with data processing equipment such as laptops, personal digital assistants, and computers.

Method and apparatus for estimating and compensating for in-phase and quadrature (IQ) mismatch in a receiver of a wireless communication device


A pocket divider including a major panel including a plurality of binding holes formed therein and a pocket panel coupled to the major panel and defining a pocket therewith. The pocket panel includes at least one binding hole formed therein. The pocket divider further includes a binding mechanism extending through the binding holes of the major panel and the at least one binding hole of the pocket panel. The at least one binding hole of the pocket panel is elongated to provide expansion capacity to the pocket.

Pocket dividers or folders may be used to store various items such as loose papers, writing utensils, or the like. In some cases, the shape and configuration of the pocket divider may limit its storage capacity. The storage capacity can be particularly limited when the pocket of the pocket divider is bound on one or more sides, or is bound into a component such as a notebook.


A polymer comprising at least one structural unit derived from a dihydroxy compound of Formula (I)

This disclosure relates to polymers prepared using dihydroxy compounds. More particularly this disclosure relates to polycarbonates prepared using dihydroxy compounds, methods of preparing the polycarbonate and polycarbonate resins, compositions comprising the polycarbonate and polycarbonate resins, and uses thereof.
Polymers are useful in the manufacture of articles and components for a wide range of applications, from automotive parts to electronic appliances. Because of their broad use, particularly in high heat applications and in other applications, it is desirable to provide polymers with high glass transition temperature (Tg), high refractive index (RI), chemical resistance, and barrier properties.
Accordingly, there is a continuing need for new compounds that will provide polymers with better chemical resistance and at the same time retaining high Tg values, to enable their use in forming a gamut of articles.

Polymers, polymer compositions and method of preparation

Abstract: wherein R1 is an aromatic divalent functionality having 6 to 60 carbons, R2 can be the same or different at each occurrence and is independently at each occurrence selected from the group consisting of a cyano functionality, a nitro functionality, a halogen, an aliphatic functionality having 1 to 10 carbons, a cycloaliphatic functionality having 3 to 10 carbons and an aromatic functionality having 6 to 10 carbons and “n” is an integer having a value 0 to 3.


The present invention comprises an ultra-dry fog box for the emission of a fog along a dimension, comprising a fog retention enclosure, having a length along which a fog is desired. In principal part, the enclosure includes at least one emission opening along the length of the enclosure for the emission of a fog. The enclosure further includes at least one inlet passage permitting the intake of ambient air and an internal circuitous path within the enclosure comprising a flow path between the inlet passage and the emission opening. The flow path includes at least in part, a near reversal of a flow from a gravitational direction. The enclosure further includes the capability to create a flow of ambient air into the inlet passage of the enclosures, and out of the enclosure through the emission opening. At least one pin jet nozzle is included in the enclosure to provide a fog, with the nozzle placed so that fluid discharged from the nozzle will enter the flow path.

1. Field of the Invention
The present invention relates to an ultra-dry fog box, for use in providing a fog along a dimension. In particular, the present invention relates to an ultra-dry fog box for the emission of a fog along a dimension, comprising a fog retention enclosure, having a length along which a fog is desired. The enclosure comprises at least one emission opening along its length for the emission of a substantially uniform fog. At least one inlet passage is located in the enclosure, permitting the intake of ambient air into the enclosure. An internal circuitous path is located within the enclosure, comprising a flow path in fluid communication between the inlet passage and the emission opening and including, at least in part, a near-reversal of flow from a gravitational direction. The enclosure further includes a means for creating a flow of ambient air into the enclosure through the inlet passage, and out of the enclosure through the emission opening. At least one pin jet nozzle is provided in the enclosure and is adapted for use in providing a fog. The pin jet nozzle is located proximate to the inlet passage or within the enclosure so that fluid discharged from the pin jet nozzle enters the flow path.
In a preferred embodiment, the device of the present invention provides an ultra-dry fog box for the emission of a fog along a dimension, including a fog retention enclosure having a length along which a fog is desired. The enclosure comprises at least one emission opening along its length for the emission of a substantially uniform fog, and at least one inlet passage permitting the intake of ambient air into the enclosure. The enclosure further includes an internal circuitous path comprising a flow path in fluid communication between the inlet passage and the emission opening, and including, at least in part, a near-reversal of a flow from a gravitational direction. The enclosure further includes means for creating a flow of ambient air into the enclosure through the inlet passage and out of the enclosure through the emission opening. The enclosure further includes at least one improved pin jet nozzle which is adapted for use in providing a fog consisting essentially of fluid particles having a diameter of less than fifty micrometers. The nozzle comprises a base portion which includes a means for connecting the nozzle to a pressurized hydraulic system, a means for receiving fluid from the hydraulic system, and an orifice component. The orifice component includes an inlet adapted to receive fluid from the hydraulic system, an outlet orifice for the release of fluid from the system in the form of a jet, and a delivery channel which is adapted to convey fluid from the inlet to the outlet orifice. The nozzle further comprises a pin portion which includes a support and centering means, and an impingement pin member mounted upon the support and centering means which is positioned over the outlet orifice, wherein the impingement pin member has an impingement face in the path of the fluid jet which is substantially similar in dimension to the diameter of the fluid jet. Further, the nozzle includes a nozzle insert which includes an insert member comprising a hollow, generally cylindrical insert which is adapted to be held firmly within the outlet orifice of the base portion, and an orifice member which is held firmly within the generally cylindrical insert member. The orifice member comprises a wear-resistant material, a central orifice with a diameter of from about three one-thousandths of an inch (0.003 inch) to about fifteen one-thousandths of an inch (0.015 inch), and a high degree of concentricity, with a variance in the concentricity of the central orifice of less than five ten-thousandths of an inch (0.0005 inch). The pin jet nozzle is located proximate to the inlet passage or within the enclosure so that fluid discharge from the pin jet nozzle will enter the flow path.
In a still further preferred embodiment, these devices of the present invention further provide at least one mesh filter disposed within said flow path for fluid particles.
2. Description of Related Art
Evaporative cooling systems have been employed in various applications for a number of years. Such systems typically involve a pressurized fluid, usually water, escaping through a small orifice and impinging on a proximate surface. The force of the pressurized stream against the proximate surface causes the fluid to disperse into minute particles creating a localized fog. A fog differs from a mist, although the terms are often used imprecisely. As used herein, a fog contains small droplets which evaporate from the air rather than falling to cause a localized wetting. Fogs are typically used for cooling, and sometimes, for humidification. A mist, as used herein, contains larger particles which fall to create a localized wetting, and are typically used more for providing irrigation.
Because of the difficulty in precisely cutting the small diameter orifice and delivery channel, such prior art nozzles have typically been formed from brass and other relatively soft metals because of the difficulty in working. Recently, some nozzles have been produced in stainless steel, however, such nozzles still follow the design of previous nozzles.
The short delivery channels of the prior art appeared to be necessary because of the limitations of metalworking. Cutting a narrow orifice, typically on the order of six one-thousandths of an inch (0.006 inch), is typically done with a pin drill, usually a stationary drill which engages rotating work. The depth which can be achieved with such a metalworking procedure, typically no greater than fifteen-thousandths of an inch (0.015 inch), is chiefly a function of how well the drill bit can be supported during the metal working process.
Further, and perhaps more important to the present invention, the nature of the metalworking employed to cut the orifice and delivery channel is such that the concentricity of the orifice and the integrity of the orifice and channel walls is difficult to maintain. The drilling operation is known to gouge and scar the interior surface (of the delivery channel and leave an imprecise mouth to the orifice itself.
These problems were addressed in U.S. Pat. No. 4,869,430 to Good. That reference teaches the use of an insert cut from a length of stainless steel surgical tubing. While this reference overcomes many of the difficulties of the prior art, the internal diameter of such tubing is not always dimensionally accurate, and the metalworking of the cut ends of the tubing sometimes distorts the mouth of the orifice. Further, the extrusion process which draws such tubing is primarily concerned with the outside diameter of the finished tubing, and the inside diameter is often imprecise, with fluting and a lack of concentricity being common problems. Such fluting can cause collection of debris, while a lack of concentricity causes a variance in spray patterns. In either case, the variable flow which resulted from piece to piece variations meant that system flow volumes could not be accurately predicted.
Even with the improvements taught in the Good reference, however, it has been difficult, if not impossible, to predict the flow requirements of a system where a plurality of nozzles of different flow rates are employed. Such a situation has rendered it difficult to design efficient spray patterns and regular flow levels.
A pin-jet nozzle is used in a hydraulic system in which the water is pressurized to about 350 to over 1,000 pounds per square inch. At that pressure a thin, substantially-coherent stream of water is forced out through an orifice which is a hole approximately six one-thousandths of an inch in diameter and against an external impingement pin, which is also about six one-thousandths of an inch in diameter, although it is common for larger size impingement pins to be employed.
This creates droplets that are small, small enough that such droplets are essentially unaffected by gravity because of their increased surface area in proportion to their volume. Water droplets of such small dimension evaporate in the air rather than causing localized wetting. With the evaporation of each droplet, it's heat of vaporization is removed from the ambient air, reducing the ambient air temperature. An array of 200 to 300 of these nozzles can cool a large area, even an outdoor area.
Wetting was always the problem with prior art evaporative cooling systems. Not only does wetting mean that cooling isn't being done efficiently, wetting can actually be harmful in many applications, by leading to mildew and mold, and damaging perishables, etc. A nozzle that puts out any significant number of large particles causes wetting, limiting the uses of the cooling system. Wear was one reason why nozzles did not perform in service, but manufacturing irregularities have been a much greater factor. The wear characteristics of a nozzle were unimportant if the nozzle could not be put into service in the first place.
A substantially uniform fog of small particle size has recently become practical, as taught by U.S. patent application Ser. No.: 08/474,947, filed Jun. 7, 1995, claiming priority of application Ser. No.: 07/919,164, filed Jul. 23, 1992, issued Apr. 15, 1997, as U.S. Pat. No. 5,620,142, the teachings of which reference are hereby incorporated by reference, as if fully set forth herein.
With a fog of such small particle size, it has become possible to utilize a water fog for theatrical effects and amusement displays, as well as cooling in environments where people are present. Where fog is employed for effects, however, it is the quantity and opacity of the fog which is generally important, not its cooling capacity. When several nozzles of the type taught in this reference are brought into close proximity to create a fog for theatrical purposes, however, a fog with larger particle size water droplets results. While the reason for this remains conjectural, it is believed that the relatively high kinetic energy of the small water particles issuing from each independent nozzle causes collisions of the particles with the particles from adjacent nozzles, resulting in larger droplet size. As such, the benefits of small particle size fogs have not heretofore been achieved by closely-spaced arrays of these nozzles.


A semiconductor memory circuit, comprising: a memory array, the memory array including a plurality of wordlines each connected to a respective row of cells and a plurality of bitlines each connected to a respective column of cells. The semiconductor memory circuit also comprises at least one row decoder for selecting a group of wordlines within the plurality of wordlines; and a plurality of driver circuits for driving the plurality of bitlines respectively and setting the cells connected to the group of wordlines to a predetermined logic state. Also, a method for presetting at least part of a memory array, the memory array comprising a plurality of wordlines each connected to a respective row of cells. The method comprises selecting a group of wordlines within the plurality of wordlines; and simultaneously setting memory cells connected to the group of wordlines to a predetermined logic state.

Semiconductor memory is used in a variety of applications. One of the most useful and widely employed types of semiconductor memory is SRAM, or static random access memory. As long as power can be continuously supplied to the cells of an SRAM array, this type of semiconductor memory allows fast access for both reading and writing individual memory cells.
In some applications, SRAM cells in a secondary array are used as a status indicator (e.g., cell validity) for corresponding memory cells in a primary array. For example, a given SRAM cell can be set to "1" when the corresponding memory cell in the primary array is deemed "valid"; prior to this event, the given SRAM cell will be expected to carry the value "0", thereby indicating that the corresponding primary cell is invalid. The use of a secondary SRAM array thus allows an external entity to rapidly access information about the validity of the cells in the primary array without having to access the primary array. This can be useful when the primary array is manufactured using a type of memory that may not allow individual cells to be as flexibly or as quickly accessed as in SRAM.
However, because SRAM cells acquire an unpredictable value upon power-up, an initialization ("preset") phase is required in order to guarantee that the given SRAM cell will indeed carry the value "0" before being written to with a "1", or vice versa. Applying this initialization operation to all SRAM cells in an array can lead to a cumbersome and lengthy preset phase.
It will be appreciated that a preset phase is required in many applications involving the use of SRAM. Improvements in the area of presetting the cells of a semiconductor memory array are therefore welcome.

Semiconductor memory with multiple wordline selection


Flexible closures and other flexible optical assemblies that are installed within a factory, or in the field, and then deployed using cable installation methods, wherein the flexible closures and assemblies have the ability to bend and twist without incurring physical damage to their structure, optical fibers and splices disposed within, and without significant attenuation in the optical fibers when exposed to conventional installation stresses. Flexible closures that replace conventional substantially rigid closures in order to facilitate pre-engineered and assembled distribution cable installation within an optical network, and the physical, bending and material properties of such closures, and methods of manufacturing and installing the same.

1. Field of the Invention
The present invention relates generally to flexible solutions for protecting and sealing cable access locations, cable assemblies and optical interconnection points, and more specifically, it relates to flexible optical closures and optical connection terminals, and the performance and material properties of such closures and terminals.
2. Technical Background
Optical fiber is increasingly being used for a variety of broadband communications including voice, video and data transmissions. As a result of the increasing demand for broadband communications, fiber optic networks typically include a large number of mid-span access locations, also referred to herein as "network distribution points" or "termination points," at which one or more optical fibers are terminated from a distribution cable and spliced to other optical fibers of tether cables or fiber optic drop cables. These mid-span access locations provide a distribution point from the distribution cable leading to another distribution point, or a drop point from the distribution cable leading to an end user, commonly referred to as a subscriber, thereby extending an "all optical" communications network closer to the subscriber. In this regard, fiber optic networks are being developed that deliver "fiber-to-the-curb" (FTTC), "fiber-to-the-business" (FTTB), "fiber-to-the-home" (FTTH), or "fiber-to-the-premises" (FTTP), referred to generically as "FTTx." Based on the large number of mid-span access locations and the unique demands of terminated optical fibers at these mid-span access locations, protective enclosures are needed for maintaining and protecting the optical fibers, splice points and accessed portions of fiber optic cables at these numerous mid-span access locations positioned along the length of the distribution cable. Protective enclosures are also needed to maintain and protect, and in some embodiments seal, optical connectors and optical fibers of optical connection terminals spliced or otherwise interconnected with the mid-span access locations and positioned within the FTTx network.
Creating mid-span access locations and splicing tether or drop cables to them in the factory prior to distribution cable installation has been developed in order to eliminate the substantial expertise and experience required to access a distribution cable and configure optical connections in the field. In particular, it is not only difficult to access a distribution cable at a predetermined position once the cable is installed, but it is also difficult to access and identify a particular optical fiber of the distribution cable to be optically connected with an optical fiber of the tether or drop cable. Once identified, the optical fiber of the distribution cable is typically joined directly to the optical fiber of the tether or drop cable at the mid-span access location using conventional splicing techniques, such as fusion splicing. In other instances, the optical fiber of the distribution cable and the optical fiber of the drop cable are first spliced to a short length of optical fiber having an optical connector mounted on the other end, which is generally referred to in the art as a "pigtail." The pigtails are then routed to opposite sides of an alignment member to properly interconnect the tether or drop cable with the distribution cable. In either case, the process of creating the mid-span access location and splicing the pre-selected optical fibers is not only time consuming, but must be accomplished by a highly-skilled field technician at significant cost and under field working conditions that are less than ideal.
Accordingly, the processes of creating access locations, terminating optical fibers and splicing the optical fibers to tether or drop cables was moved from the field to the factory with the introduction of pre-engineered solutions in which distribution cable assemblies including mid-span access locations are built in the factory for successful deployment and field installation. In addition to the problem of manufacturing these pre-engineered cable assemblies with their mid-span access locations in the proper positions, there are also problems encountered with using conventional components to protect the access locations and optically connect the optical fibers of the distribution cable with optical fibers of tether or drop cables at the mid-span access locations. For example, rigid enclosures are typically used to protect the section of the distribution cable that must be exposed to access the appropriate optical fibers and the splices. Distribution cables provided with conventional enclosures tend to be large in size and inflexible, and thus, unable to satisfy common deployment constraints, such as being wound onto a reel, deployed through conduits having a relatively small inner diameter or significant bends, or deployed through conventional aerial lashing equipment, such as sheaves and rollers. Furthermore, such enclosures are often structurally complex and difficult to install.
Thus, along with the development of pre-engineered cable assemblies, a need has arisen for a solution to replace the use of conventional rigid enclosures that are incapable of being installed within a factory and then deployed using typical cable installation methods (e.g., drive-off) without incurring any damage to the enclosure or optical fibers within. An enclosure solution for a pre-engineered cable assembly should not only meet or exceed the protection and sealing performance characteristics of conventional rigid enclosures, but should also allow the distribution cable to be installed using typical cable installation methods without damage to the enclosure, without compromising the sealing integrity of the enclosure and without exposing the optical fibers or splices to physical damage or significant attenuation caused by installation stress as defined by industry standards. In addition, it would be desirable to use those same material and physical properties of a flexible optical splice enclosure and apply them to other components of the pre-engineered cable assembly to aid in installation, such as optical connection terminals interconnected with the distribution cable at an access location and added in the factory. The flexible enclosures and other components would provide the pre-engineered cable assembly with a small enough diameter and the flexibility to be wound onto a reel, deployed through a conduit having a relatively small inner diameter or significant bends, or deployed using conventional aerial lashing equipment.

Flexible optical closure and other flexible optical assemblies


A dual-gate transistor formed of two transistors connected in series between a first power terminal and a first node is used as a charging circuit for charging a gate node (first node) of a transistor intended to pull up an output terminal of a unit shift register. The dual-gate transistor is configured such that the connection node (second node) between the two transistors constituting the dual-gate transistor is pulled down to the L level by the capacitive coupling between the gate and second node in accordance with the change of the gate from the H level to the L level.

In an image display apparatus such as a liquid crystal display, a shift register for performing a shift operation in one frame period of a display signal can be used as a gate-line driving circuit (scanning-line driving circuit) for scanning the display panel. It is desirable that this shift register be formed by field effect transistors of the same conductivity type only in order to reduce the number of steps in the manufacturing process of the display apparatus.
A display apparatus employing amorphous silicon thin-film transistors (hereinafter referred to as "a-Si transistors") as shift registers of the gate-line driving circuit easily achieves large-area display with great productivity, and is widely used as the screen of a notebook PC, a large-screen display apparatus, etc.
On the other hand, it is known that a-Si transistors are characterized in that the threshold voltage is shifted when the gate electrode is continuously (dc-) biased. In addition, as shown in "Relative importance of the Si—Si bond and Si—H bond for the stability of amorphous silicon thin film transistors" by R. B. Wehrspohn etc., Journal of applied physics, vol. 87, pp. 144-154, a-Si transistors generally undergo progressive degradation.
Further, since the shift of threshold voltage (Vth shift) of transistors causes malfunctions of the circuit, various types of shift registers having taken measures against such malfunctions have been proposed (e.g., Japanese Patent Application Laid-Open No. 2006-107692). It is known that this Vth shift problem similarly occurs in organic transistors, not only in a-Si transistors.
The threshold voltage of an a-Si transistor shifts in the negative direction with the lapse of time when the potential condition where the gate continues having a lower potential than both the drain and source continues. When the threshold voltage of the a-Si transistor shifts in the negative direction, reducing the gate-source potential to turn off the a-Si transistor (into non-conducting state) will not bring about a complete off state. That is, the a-Si transistor cannot interrupt current completely, which causes malfunctions of the circuit.
A shift register includes an output pull-up transistor (Q1 in FIG. 1 of the present application) supplying a clock signal to an output terminal to pull up the potential of the output terminal and a charging transistor (transistor Q3 in the same drawing) for charging the gate node (node N1 in the same drawing) of the output pull-up transistor. In the normal operation of the shift register as will be described later in detail, the charging transistor is in the aforementioned potential condition (where the gate of the transistor has a lower potential than both the drain and source) for a certain period of time, disadvantageously causing the negative shift of threshold voltage, which results in malfunctions.

Semiconductor device and shift register circuit


The accumulation of registered sub-frame residuals in an address-mapped repartitioned digital pixel matches the intensity resolution (dynamic range) to the spatial resolution of the image. The digital accumulation of pixel quantization events (QEs) is extended to include sub-frame residuals. After all QEs are digitally accumulated, then removed from the analog accumulator, an analog residual value remains. Residual capture logic is configured to trigger residual digitization logic at least twice per frame interval for selected pixels to capture, digitize and then clear the residual value on the storage device. Memory update logic is configured to accumulate the quantization event digital values and residual digital values into existing digital values at the address-mapped memory locations in digital memory. Resolution enhancement is enabled by an address mapping that maps a one-pixel spacing on the detector to two or more pixel spacing in the digital memory.

1. Field of the Invention
This invention relates to a readout circuit for a detector array, and more particularly to an address mapped repartitioned digital pixel with sub-frame residual accumulation.
2. Description of the Related Art
A focal plane array (FPA) includes a two-dimensional detector array of detector elements, or pixels, typically organized by columns and rows and a readout integrated circuit (ROIC). The detector array and ROIC may be integrated into a single layer in which each cell includes a detector element and a readout circuit or may be separate layers in which each detector element is electrically coupled to a corresponding readout circuit.
It is common for the readout circuit within the pixel to be able to accumulate charge from a photo-diode, corresponding to the total flux of light of various wavelengths. Often, the charge is accumulated on a capacitive element that effectively integrates charge, producing a voltage, the voltage corresponding to the intensity of the flux over a given time interval called an integration interval. The photo-diode may be coupled to the capacitive element via a MOS transistor or direct injection gate that is biased with a voltage. A circuit element comprises circuitry capable of resetting the voltage of capacitive element back to an initial condition and circuitry capable of conveying a charge or voltage to a column (or row) wire for transfer to an output of the array. This ROIC configuration is referred to here as an "analog pixel". Such a voltage or charge can be digitized by circuitry associated with the focal plane array resulting in binary values, at least one value for each pixel of the focal plane array. Thus, a focal plane array can be used to convert a two-dimensional pattern of flux into a two-dimensional array of binary values, such resulting array often called a digital image.
The effective amount of charge, (i.e., signal), that is accumulated by an analog pixel over an integration interval can be increased by the addition of a digital counter circuit thereby forming a "digital pixel". In some examples, each digital pixel is given a unique digital counter circuit. Additional circuitry can be added to the digital pixel to allow a predetermined amount of charge to be removed from the capacitive element of the pixel and correspondingly to increase the value of the digital counter by one count. Thus, over the lapsed period of time of an integration interval, the capacitive element of the pixel can integrate photo charge, a circuit within the pixel can remove predetermined quantities of charge, and a digital counter can count the number of charge removals, and thereby accumulate the applied signal. In this manner, the effective amount of signal that is accumulated by the digital pixel over an integration interval can be increased relative to an analog pixel because the digital counter extends the integration range of the capacitive element. The type of digital counter used can be of any logical variation, including binary, gray code, Linear-Feedback-Shift-Register (LFSR), or any other digital count circuit that can count charge removals.
As described in Brian Tyrell et al. "Design Approaches for Digitally Dominated Active Pixel Sensors: Leveraging Moore's law Scaling in Focal Plane Readout Design" Quantum Sensing and Nanophotonics Devices V. Proceedings of the SPIE, Vol. 6900 2008, in-pixel Orthogonal Transfer Structures can be incorporated into the digital FPA architecture. A multiplexed input is added to the counter/register structure to enable orthogonal transfer of digital data between adjacent pixels. The digital data or "count" in an FPA moves left or right, up or down from one adjacent pixel to the next. This in-pixel structure results in a large number (size of the array) of simultaneous register transfers that increases complexity and power consumption and produces a large noise spike.

Address mapped repartitioned digital pixel with sub-frame residual accumulation


A switch assembly for triggering the release of a door latch that provides improved tactile feedback to a user when actuated is disclosed. The switch assembly provides a tactile response to the user that indicates proper actuation by the force feedback that is provided to the user as the button is displaced during actuation. The switch assembly includes an elastomeric button and a base supporting the button. An electrically conductive static contact is supported by the base. An electrically conductive moveable contact, also supported by the base, is operatively disposed between the button and the static contact. A film is disposed over the moveable contact and fixed to the edge of the base, sealing both contacts from the atmosphere. The film thereby effectively divides the interior of the switch assembly into an open first chamber located between the film and the button, and a closed second chamber located between the film and the base.

Traditionally, mechanical devices have been used to latch and unlatch closures such as doors, trunks, hoods, lift gates and hatches and the like in automobiles and other vehicles. It is known, however, to utilize an electro-mechanical door latch mechanism for such applications for a variety of reasons including ease of operation, lower cost and weight, improved styling opportunities, and reduced complexity. For example, a user actuated switch can be employed to trigger the release of a mechanical latch. In this regard, an electrical switch is operable to provide an input to a controller for operating the mechanical latch when the switch is actuated. In addition, modern styling and ergonomic requirements may dictate the physical configuration of the switch. For example, the switch may need to comprise an aesthetically pleasing user actuation component (e.g., a low profile button) that is of adequate size and shape so as to be easily operated by a user under a wide variety of operating conditions in a wide variety of environments.
Known switch technology for such applications generally incorporates a button having a first electrically conductive material comprising protrusions having the shape of "pills" or spring-like "fingers" that are insert molded or otherwise attached to the underside of the button. A second electrically conductive material comprising a set of contacts is located opposite the button on a base portion of the switch assembly. The second electrically conductive material may typically be in the form of a plate, tracks or a printed circuit board, for example. The first electrically conductive material completes a circuit in the switch when the switch is actuated by depressing the button. For example, when the button is depressed, the first conductive material bridges the contacts of the second electrically conductive material thereby closing an electric circuit.
In one such known switch assembly configuration, the switch assembly is also sealed from the atmosphere. During its manufacture, a fixed volume air is captured in the space between the button and the base portion of the switch assembly. As such, when the ambient temperature of the switch assembly changes, so too does the volume of the air trapped within the switch assembly. Under hotter ambient temperature conditions the volume of air within the switch assembly expands; under colder ambient temperature conditions, the volume of air within the switch assembly contracts.
In such a design, changes in the switch assembly's operating environment, such as extreme changes in ambient temperature, for example, can impact the perceived operation of the switch to a user. For example, the switch assembly may not reliably provide satisfactory and perceptible tactile feedback to the user signifying actuation of the switch. In such a case, depression of the button may instead provide an unsatisfactory continuous resistance to the user causing the user to be unsure whether the switch has been properly actuated.
Consequently, it is desirable to provide a switch assembly having a reliable and cost-effective actuation mechanism that also provides satisfactory tactile feedback to a user for signifying proper actuation of the switch.

Low profile automotive latch release switch assembly


A loss-of-signal (LOS) condition is detected by sampling input data for a predetermined time period, comparing a magnitude of the sampled input data to a threshold signal strength level, and asserting a LOS indication if the number of samples that have signal strength less than the threshold signal strength level is less than a predetermined value.

1. Field of the Invention
This invention relates to integrated circuits used in communication systems and more particularly to detection of loss of signal conditions associated therewith.
2. Description of the Related Art
Interruptions occur in data transmission for a variety of reasons such as equipment failure, a cut cable or excessive attenuation of the signal. When such an interruption occurs, it is typical for the intended receiver in the data transmission system to detect the failure condition and inform the communication system of the existence of the failure. Many communication systems specify various aspects of detecting such loss of signal (LOS) conditions. For example, the Synchronous Optical Network (SONET) specification requires that LOS be raised when the synchronous signal (STS-N) level drops below the threshold at which a bit error rate (BER) of 1×10−3 is predicted.
A clock and data recovery circuit operating in such a communication system typically receives the input data stream as a differential signal. One approach to detecting loss of signal conditions has been to rectify the received signal and compare the received signal to a reference level. Peak detection has also been used. However, such loss of signal techniques has been typically implemented in bipolar technologies. Their implementation in CMOS technologies is difficult. Since it may be desirable to implement various designs in CMOS from cost and ease of manufacturing as well as for power and performance reasons, it would be desirable to have a loss of signal approach that could be implemented in CMOS.

Method and apparatus for determining a loss of signal condition


An air cushioned shoe is provided including a sole with an upper coupled thereto for containing a foot of a user. Also included is an air flow chamber situated within a heel portion of the sole. The air flow chamber further includes an aperture formed in a top face thereof which remains in communication with the shoe. The air flow chamber further has a plurality of bellows situated between a rear of the air flow chamber and a rear of the sole for directing a flow of air through the aperture of the air flow chamber when the user walks.

1. Field of the Invention
The present invention relates to air filled shoe soles and more particularly pertains to a new vented shoe sole for providing a foot of a user with ventilation.
2. Description of the Prior Art
The use of air filled shoe soles is known in the prior art. More specifically, air filled shoe soles heretofore devised and utilized are known to consist basically of familiar, expected and obvious structural configurations, notwithstanding the myriad of designs encompassed by the crowded prior art which have been developed for the fulfillment of countless objectives and requirements.
Known prior art air filled shoe soles include U.S. Pat. No. 5,400,526; U.S. Pat. No. 5,408,760; U.S. Pat. No. 5,282,324; U.S. Pat. No. 5,295,313; U.S. Pat. No. 5,299,368; and U.S. Pat. Des. 268,710.
In these respects, the vented shoe sole according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of providing a foot of a user with ventilation.


The invention relates to a mobile telephone and a smart card transaction system in combination, where the functionality of a mobile telephone is increased so that the phone can be used in a large range of transactions for which smart cards are normally used. The phone may also be provided with a slot to receive smart cards and recharge them with funds for cashless transactions, by communicating with a bank account or the like.

Whereas the mobile phone market remains buoyant it may win additional patronage if the communication system and its devices could relate to the frequently arising need to interact with a smart card terminal, be it to execute a purchase or to verify a right to access a predefined service, or for some other function.
However, standard VHF antennas are almost useless to meet the condition for a transactional data transfer. It is and must remain a bilateral process. Radio antennas radiate into all directions, and can also receive from all directions.
The present invention has as an objective, the modification of a mobile telephone to increase its functionality. The modified telephone may be used in e.g. point of sale and access control transactions.
GB 2321551 discloses power transfer using a twin-loop antenna configuration capable to operate in-phase and in anti-phase. The adaptation of the principle to mobile phones makes extra demands and calls for additional inventive effort. For example, if the particulars of a travel entitlement, or of a routing instruction have to be surveyed quickly, the display area needs to be larger than that normally provided by a mobile phone device. Again, this objective must be attained without making the "pocket size data carrier" clumsy to use.
It will be seen from the description that various modes are feasible. In the foreground are concepts for dividing the device into two parts linked by a hinge or a piece of flexible material as disclosed in GB 2348521. Then, the question arises, how to convey the signals from the microprocessor to the display screen? Could some fibres of the flexible material be used as a conductor? this invention includes proposals to this effect.

Mobile phone communications system with increased functionality


A thin film transistor substrate (20a) includes an insulating substrate (10a), a semiconductor layer (13a) provided on the insulating substrate (10a) and having a channel region (C), and a channel protection layer (25) provided in the channel region (C). The channel protection layer (25) is made of a multilayer film in which first insulating films and second insulating films are alternately layered. A relationship between a refractive index Ra of the first insulating film and a refractive index Rb of the second insulating film is Rb/Ra≧1.3.

A thin film transistor (hereinafter also referred to as "TFT") as a switching element, for example, is provided on a thin film transistor substrate for each pixel which is a minimum unit of an image.
Further, in general, a thin film transistor using a semiconductor layer made of amorphous silicon is used in a thin film transistor substrate, as a switching element of each pixel which is a minimum unit of an image.
A general TFT having a bottom gate structure includes, for example, a gate electrode provided on an insulating substrate, a gate insulating film provided so as to cover the gate electrode, an island-shaped semiconductor layer located on the gate insulating film so as to overlap the gate electrode, and a source electrode and a drain electrode facing each other on the semiconductor layer.
In the TFT having the bottom gate structure, an upper portion of a channel region is covered by an interlayer insulating film made of SiO2, etc., and a pixel electrode is provided on the interlayer insulating film to fabricate a thin film transistor substrate. A counter substrate is provided so as to face the thin film transistor substrate, and a liquid crystal layer is provided between the thin film transistor substrate and the counter substrate, thereby forming a liquid crystal display device.
In a conventional TFT structure, the semiconductor layer is located above the gate electrode, and therefore the gate electrode serves as a light shielding film. However, in the liquid crystal display device, a display region is irradiated with light of a backlight unit from the thin film transistor substrate side. Thus, once the light coming through a portion other than the light shielding film reflects on the counter substrate, etc., and comes into the semiconductor layer from above the TFT, the channel region of the semiconductor layer made of amorphous silicon is irradiated with the light due to lack of the light shielding film. As a result, because of the photoexcitation, a leakage current may be present when the TFT is off, or the amorphous silicon may be degraded by the light. This may result in a reduction in TFT properties and display quality of the liquid crystal display device.
Thin film transistor substrates configured to avoid such a disadvantage have been suggested. More specifically, in a thin film transistor substrate in which a TFT is located near an intersection between a gate line and a source line and in which the TFT and a pixel electrode are connected to each other, a metal layer for blocking light is provided above a channel region of the TFT via an insulating film (see, e.g., Patent Document 1).

Display device substrate and method for fabricating same, and display device


A system and method for performing Lifetest over a cable network system is provided which minimizes bandwidth usage by the Lifetest procedure while increasing the number of devices that the EMS may support. In accordance with the system and method, the EMS obtains device state information from the CMTS. Since the CMTS is constantly ranging its device population for state information, and since this information is stored in the DOCSIS Radio Frequency MIB, the EMS may obtain device state information by going to the MIB instead of directly to the device. This approach utilizes the distributed process inherently built into the system by taking advantage of the ranging that is already being performed by the CMTS. Since the EMS does not have to interact with every device in the system while performing Lifetest, consumption of bandwidth and processing resources is minimized.

In recent years, the use of cable networks for Internet access has increased dramatically. This is due, in part, to the higher access speeds possible with cable modems as compared to traditional analog modems. In particular, a typical cable modem can operate at speeds about 500 times faster than those afforded by a conventional digital analog modem.
Cable networks are, by their nature, complex assemblies with a large number of components. These components include a multitude of Network Elements (NEs) such as Broadband Telephony Interfaces (BTIs), multimedia terminal adaptors and cable modems. In order to keep the network running properly, it is important for the cable provider to be aware of the state of all of the NEs.
One tool for monitoring the state of NEs on a network is a feature of the DOCSIS device manager called Lifetest, which is reponsible for obtaining the state of every NE in the system. This feature is implemented by the Element Management System (EMS), which is the operations system designed to manage a Cable Modem Termination System (CMTS) and the cable modems associated with it. The cable operator can schedule Lifetest to run on a periodic basis. The results of Lifetest will be displayed to the user, providing him with the state of all of the network elements on the network.
The current version of Lifetest requires the EMS to communicate directly with each NE in the system via a protocol called the Signaling Network Management Protocol (SNMP). During the procedure, the EMS polls each device in the system via an SNMP GET command in order to obtain its status. Since the Lifetest procedure, as it is currently implemented, involves communication with each NE in the system, it consumes substantial bandwidth and processing resources, especially in large networks, which in turn limits the number of NEs that a single EMS may support.
There is thus a need in the art for a system and method for implementing Lifetest, or a similar procedure for monitoring or tracking the status of network elements, over a cable network system in a way that minimizes consumption of bandwidth and processing resources, while increasing the number of devices that the EMS may support. These and other objectives are achieved by the present invention, as hereinafter described.

Performance of lifetest using CMTS as a proxy


An interlaced storage method for storing data in multi-level flash memory cells so that data bits from multiple addresses are encoded and stored in a single flash memory cell, and a method for reading and decoding the stored data. In the method for storing data, the data bit values for each address are multiplied by a weight having a greater value for each successively higher address to provide weighted bit values. The weighted bit values for the same order bits from the addresses are then added together to provide results, each result being programmed as a threshold voltage vt in a flash memory cell. To read the stored data, a weight comparison is set equal to the greatest weight and compared with the vt value in a first pass. If the vt value is equal to the weight comparison value, the data bits represented by the vt value are identified. If the vt value is greater than the weight comparison value, the most significant bit stored is identified as a "1" and the next lower weight is added to the weight comparison value for a second pass. If the vt value is less than the weight comparison value, the most significant bit stored is identified as a "0" and the next lower weight is subtracted from the weight comparison value for a second pass. Second and subsequent passes proceed in a similar manner with either all bits being identified, or only one bit identified and the weight comparison value being modified for a next pass. Passes proceed until all bits are identified.

1. Field of the Invention
The present invention relates to a method for storing data in multi-level flash memory cells and a sensing method for reading the stored data.
2. Description of the Related Art
FIG. 1 shows a typical configuration for an integrated circuit including a flash memory array 100 and circuitry enabling programming, erasing, and reading for memory cells in the array 100. The flash memory array 100 is composed of individual cells, such as 102. Each cell has a drain connected to a bitline, such as 104, each bitline being connected to a bitline pull up circuit 106 and column decoder 108. Sources of the array cells are connected to Vss, while their gates are each connected by a wordline to a row decoder 110.
The row decoder 110 receives voltage signals from a power supply 112 and distributes the particular voltage signals to the wordlines as controlled by a row address received from a processor or state machine 114. Likewise, the bitline pull up circuit 106 receives voltage signals from the power supply 112 and distributes the particular voltage signals to the bitlines as controlled by a signal from the processor 114. Voltages provided by the power supply 112 are provided as controlled by signals received from processor 114.
The column decoder 108 provides signals from particular bitlines to sense amplifiers or comparators 116 as controlled by a column address signal received from processor 114. The sense amplifiers 116 further receive voltage reference signals from reference 118. The outputs from sense amplifiers 116 are then provided through data latches or buffers 120 to processor 114.
To program a cell in the flash memory array 100, high gate-to-drain voltage pulses are provided to the cell from power supply 112 while a source of the cell is grounded. For instance, during programming typical gate voltage pulses of 10V are each applied to a cell, while a drain voltage of the cell is set to 5.5V and its source is grounded. This programming procedure results in an increase of a threshold voltage for the cell, the threshold being the gate-to-source voltage required for the cell to conduct.
To erase a cell in the flash memory array 100, relatively high negative gate-to-source voltage pulses are applied. For instance, during erase gate voltage pulses of -10V are applied to a cell, while a drain of the cell is set to 5.5V and its source is floated. The large negative gate-to-source voltage pulses reduce the threshold of the cell.
To read the state of a cell, a typical control gate voltage of 5V is applied to the cell. The current output from the cell being read is received at an input of a number of the sense amplifiers 116 connected to the same bitline as the cell being read. A second input to each sense amplifier is provided from the reference 118. The reference 118 provides a different reference current to each sense amplifier connected to a bit line, with a current level set equal to current expected from a cell being read when programmed to a desired threshold voltage state. Binary outputs of the sense amplifiers 116 indicate if the cell being read is in a state which is greater than or less than the state of the reference signal received. Outputs of the sense amplifiers are provided through data latch/buffers 120 to the processor 114, enabling the processor 114 to determine from the sense amplifier outputs the threshold state of the cell being read.
Multi-level storage refers to the ability of a single memory cell to represent more than a single binary bit of data. A conventional memory cell depicts two states or levels, usually referred to as logic "0" and logic "1". A multi-level cell could represent as many as 256 states, or a byte of information.
Multi-level cell storage is obtainable in flash design because a flash memory cell can be programmed to provide multiple threshold voltage (vt) levels. The different vt levels can be sustained over time in a flash memory cell, even after repeated accesses to read data from the cell. For example, 16 vt levels stored in a flash memory cell can represent data in four conventional memory cells. Thus, an array of multi-level flash memory cells which can store up to 16 vt levels can provide 4 times the storage capacity of conventional memory cells which only store a binary bit per cell.
Table 1 below shows typical vt levels of a flash memory cell capable of storing up to 16 vt levels, along with a hexadecimal representation of the data stored. The hexadecimal number can be represented by 4 binary bits, or a nibble, as indicated by the data indication D(3:0) in Table 1.
TABLE 1 ______________________________________ Vt(V) D(3:0) Vt(V) D(3:0) ______________________________________ 0 0 1.0 8 0.125 1 1.125 9 0.250 2 1.250 A 0.375 3 1.375 B 0.500 4 1.500 C 0.625 5 1.625 D 0.750 6 1.750 E 0.875 7 1.875 F ______________________________________
Table 2 below shows typical data stored in four addresses 100-103, the four address being shown in a first column of Table 2. With data in each address being represented by two 16 vt level flash memory cells, the data for each address is represented with two hexadecimal numbers, as shown in a second column of Table 2 beneath the indication D(7:0). The D(7:0) indication shows that 8 binary bits would be required to represent the data in each address. A third column beneath the heading D(7:4), and fourth column beneath the heading D(3:0) in Table 2 show an equivalent binary representation of data stored in the addresses 100-103.
TABLE 2 ______________________________________ Address D(7:0) D(7:4) D(3:0) ______________________________________ 100 AA 1010 1010 101 55 0101 0101 102 84 1000 0100 103 OF 0000 1111 ______________________________________
Table 3 below shows another representation of the data of Table 2, with eight 16 vt level flash memory cells, labeled B0-B7, represented for storing the data in a conventional fashion. In a first row of Table 3, the addresses 100-103 are shown, in a second row the multi-level flash memory cells B0-B7 used to store data for each of the addresses 100-103 are represented, and in a third row the hexadecimal representation for the data stored by each of the multi-level flash cells B0-B7 is shown.
TABLE 3 ______________________________________ Address 100 101 102 103 ______________________________________ Physical cell B0 B1 B2 B3 B4 B5 B6 B7 Stored Data(HEX) A A 5 5 8 4 0 F ______________________________________
With conventional programming of multi-level flash memory cells to store data as illustrated in Table 3, to read the data stored at address 102 requires 2 bit lines, one for each flash memory cell B4 and B5, and 30 sense amplifiers. Each bit line is connected to an input of 15 sense amplifiers. Each sense amplifier for a bit line in turn has another input receiving a unique reference corresponding to threshold states between the 16 possible vt states for the flash memory cells. By monitoring the output of the sense amplifiers, the data stored by each flash memory cell can be determined.
The possibility to reduce the number of sense amplifiers exists, but is detrimental to the access time required to read data. For example, in the above case with 8 sense amplifiers per bit line, two sensing operation passes would be required to determine the state stored by a flash memory cell. Multiplexing to select proper references to each sense amplifier during each pass would also be needed. If 4 sense amplifiers are utilized, 4 passes would be required to identify the data stored in a multi-level memory cell.

Interlaced storage and sense technique for flash multi-level devices