A prefetch cancelation arbiter improves access to a shared memory resource by arbitrarily canceling speculative prefetches. The prefetch cancelation arbiter applies a set of arbitrary policies to speculative prefetches to select one or more of the received speculative prefetches to cancel. The selected speculative prefetches are canceled and a cancelation notification of each canceled speculative prefetch is sent to a higher-level memory component such as a prefetch unit or a local memory arbiter that is local to the processor associated with the canceled speculative prefetch. The set of arbitrary policies is used to reduce memory accesses to the shared memory resource.

In computer architecture applications, processors often use caches and other memory local to the processor to access data during execution. The processors more efficiently execute instructions when, for example, program data (e.g., machine code) and data (e.g., operands) accessed by a processor are stored locally in a cache. However, a local cache often accesses a shared memory which can result in contention issues that arise when multiple requesters try to access a shared memory resource. The problem is compounded when multiple caches (often having differing line sizes and timing requirements) of multiple processors are used together in a multiprocessor system. Speculative fetches from various memory controllers in a multiple processor system also contend for the same downstream memory resources.
The problems noted above are solved in large part by a prefetching system that allows downstream memory controllers to arbitrarily cancel various speculative prefetches. The disclosed prefetch cancelation arbiter improves access to a shared memory resource by arbitrarily canceling speculative prefetches. The prefetch cancelation arbiter applies a set of arbitrary policies to speculative prefetches to select one or more of the received speculative prefetches to cancel. The selected speculative prefetches are canceled and a cancelation notification of each canceled speculative prefetch is sent to a higher-level memory component such as a prefetch unit or a local memory arbiter that is local to the processor associated with the canceled speculative prefetch. The set of arbitrary policies is used to reduce memory accesses to the shared memory resource in certain conditions.

Prefetcher with arbitrary downstream prefetch cancelation


A screening screen assembly for a vibratory screening machine including an apertured plate having side edge portions with first apertured bands extending between the side edge portions and second unapertured bands alternating with the first bands, the second bands having a wider width than the borders between the apertures in the first band, and an undulating screening screen having ridges and troughs between the ridges extending crosswise to the first and second plate bands and being secured thereto.

The present invention relates to an improved screening screen assembly for a vibratory screening machine.
Undulating screening screen subassemblies adhesively bonded to apertured plates are shown in U.S. Pat. Nos. 5,417,859, 5,417,853 and 5,417,793. The plates such as shown in these patents have apertures bounded by relatively narrow plate members or strips, each of which provides a very limited area of adhesive securement or bonding to the undersides of troughs of undulating screens. While the foregoing adhesive securement to relatively narrow frame members is satisfactory for most environments, if it is utilized in corrosive environments, the adhesive bond between the undersides of the troughs and the narrow strips of the plate could be eroded because of the relatively small areas of adhesive contact therebetween. In the past there have also been in use plates or frames which comprised elongated relatively wide strips between the side edges of the plates or frames, with elongated openings or apertures between the strips, and such elongated openings extended substantially the entire length between the side edges. However, in screening screen assemblies of this type, there was no support for the elongated strips between their ends because of the fact that the openings between the strips extended substantially the entire distance between the side edges. Thus the elongated strips were essentially adhesively bonded to each other by the undulating screen, and when the screening screen assemblies were handled, the elongated plate strips could flex relative to each other with the attendant possibility that the bond between the undulating screen subassembly and the elongated strips could be broken.

Screen assembly for vibratory screening machine


An automatically configuring storage array includes a plurality of media storage devices coupled together within a network of devices. Preferably, the network of devices is an IEEE 1394-2000 serial bus network of devices. The media storage devices are utilized to record and retrieve streams of data transmitted within the network of devices. The media storage devices communicate with each other in order to store and retrieve streams of data over multiple media storage devices, if necessary. When a record or playback command is received by any one of the media storage devices, the media storage devices send control communications between themselves to ensure that the stream of data is recorded or transmitted, as appropriate. Control of the record or transmit operation is also transferred between the media storage devices in order to utilize the full capacity of the available media storage devices. Preferably, streams of data are recorded utilizing redundancy techniques. An internal file system is included within each media storage device. A file table associated with each recorded stream of data is stored within the internal file system of each media storage device to facilitate search and retrieval of the recorded streams of data throughout the media storage devices. Preferably, the media storage devices accept control instructions directly from devices within the network. Alternatively, a control device is utilized to provide a control interface between the media storage devices and the other devices within the network.

The IEEE 1394-2000 standard, "1394 Standard For A High Performance Serial Bus," is an international standard for implementing an inexpensive high-speed serial bus architecture which supports both asynchronous and isochronous format data transfers. In addition, the IEEE 1394-2000 bus has a universal clock called the cycle timer. This clock is synchronized on all nodes. Isochronous data transfers are real-time transfers which take place based on the universal clock such that the time intervals between significant instances have the same duration at both the transmitting and receiving applications. Each packet of data transferred isochronously is transferred in its own time period. An example of an ideal application for the transfer of data isochronously would be from a video recorder to a television set. The video recorder records images and sounds and saves the data in discrete chunks or packets. The video recorder then transfers each packet, representing the image and sound recorded over a limited time period, during that time period, for display by the television set. The IEEE 1394-2000 standard bus architecture provides multiple independent channels for isochronous data transfer between applications. A six bit channel number is broadcast with the data to ensure reception by the appropriate application. This allows multiple applications to simultaneously transmit isochronous data across the bus structure. Asynchronous transfers are traditional reliable data transfer operations which take place as soon as arbitration is won and transfer a maximum amount of data from a source to a destination.
The IEEE 1394-2000 standard provides a high-speed serial bus for interconnecting digital devices thereby providing a universal I/O connection. The IEEE 1394-2000 standard defines a digital interface for the application thereby eliminating the need for an application to convert digital data to analog data before it is transmitted across the bus. Correspondingly, a receiving application will receive digital data from the bus, not analog data, and will therefore not be required to convert analog data to digital data. The cable required by the IEEE 1394-2000 standard is very thin in size compared to other bulkier cables used to connect such devices in other connection schemes. Devices can be added and removed from an IEEE 1394-2000 bus while the bus is operational. If a device is so added or removed the bus will then automatically reconfigure itself for transmitting data between the then existing nodes. A node is considered a logical entity with a unique address on the bus structure. Each node provides in a standard address space, an identification ROM, a standardized set of control registers and in addition, its own address space.
The IEEE 1394-2000 standard defines a protocol as illustrated in FIG. 1. This protocol includes a serial bus management block 10 coupled to a transaction layer 12, a link layer 14 and a physical layer 16. The physical layer 16 provides the electrical and mechanical connection between a device and the IEEE 1394-2000 cable. The physical layer 16 also provides arbitration to ensure that all devices coupled to the IEEE 1394-2000 bus have arbitrated access to the bus as well as actual data transmission and reception. The link layer 14 provides data packet delivery service for both asynchronous and isochronous data packet transport. This supports both asynchronous data transport, using an acknowledgment protocol, and isochronous data transport, providing an un-acknowledged real-time guaranteed bandwidth protocol for just-in-time data delivery. The transaction layer 12 supports the commands necessary to complete asynchronous data transfers, including read, write and lock. The serial bus management block 10 contains an isochronous resource manager for managing the resources associated with isochronous data transfers. The serial bus management block 10 also provides overall configuration control of the serial bus in the form of optimizing arbitration timing, guarantee of adequate electrical power for all devices on the bus, assignment of the cycle master, assignment of isochronous channel and bandwidth resources and basic notification of errors.
The AV/C Command Set is a command set used for transactions to and from consumer audio/video equipment over an IEEE 1394-2000 serial bus. This AV/C command set makes use of the Function Control Protocol (FCP) defined by IEC-61883, the ratified international standard for the transport of audio/video command requests and responses. AV/C commands are transmitted through AV/C transactions. An AV/C transaction consists of one AV/C command frame addressed to the target node's FCP_Command register and zero or more AV/C response frames addressed to the requesting node's FCP_Response register.
Each audio/video unit or subunit can implement a subset of the AV/C command set. An unsupported command received by an audio/video unit is rejected with a not implemented response. Support for the different commands is characterized as mandatory, recommended, optional and vendor-dependent. A mandatory command is supported by any audio/video device that claims compliance with the AV/C command set and that implements the audio/video unit or subunit type for which the command is defined. An AV/C compliant device is identified by an entry within its configuration read-only memory (ROM). A recommended command is optional for an AV/C compliant device, but represents a basic functionality, such as video and audio insert modes for a VCR subunit's record command. If the device supports a unit or subunit type that has the functionality corresponding to the command, it is recommended that the command be implemented. An optional command is optional for an AV/C compliant device. Support for and interpretation of a vendor-dependent command are defined by the device vendor.
AV/C commands are grouped into four command types including control, status, inquiry and notify command types. A control command is sent by a controller to another audio/video device, the target, to instruct the target to perform an operation. A target that receives a control command will return an AV/C response frame including either a not implemented, accepted, rejected or interim response code. The target will return a not implemented response code when the target does not support the control command specified or the command is addressed to a subunit not implemented by the target. The target will return an accepted response code when the target implements the control command specified and the current state of the target permits execution of the command. The target will return a rejected response code when the target implements the control command specified but the current state of the target does not permit execution of the command. The target will return an interim response code if the control command specified is implemented by the target, but the target is unable to respond with either an accepted or rejected response code within 100 milliseconds. Unless a subsequent bus reset causes the AV/C transaction to be aborted, the target will ultimately return a response frame with an accepted or rejected response code after returning an interim response code.
A status command is sent by a controller to an audio/video device to request the current status of the target device. Status commands may be sent to either audio/video units or subunits. A target that receives a status command will return an AV/C response frame including either a not implemented, rejected, in transition or stable response code. A target will return a not implemented status response code when the target does not support the status command specified or the command is addressed to a subunit not implemented by the target. A target will return a rejected status response code when the target implements the status command specified but the target state does not permit the return of status for the command. The target will return an in transition status response code when the target implements the status command specified, but the current state of the target is in transition. The target will return a stable status response code when the target implements the status command specified and the information requested is reported in the values in the AV/C response frame.
An inquiry command is used by a controller to determine whether or not a target audio/video device supports a particular control command. A controller can reliably use inquiry commands to probe the capabilities of a target, since the target shall not modify any state nor initiate any command execution in response to an inquiry command. A target that receives an inquiry command will return an AV/C response frame including either an implemented or a not implemented response code. An implemented response code notifies the controlling node that the corresponding control command specified is implemented by the target audio/video device. A not implemented response code notifies the controlling node that the corresponding control command specified is implemented by the target audio/video device.
A notify command is used by a controller to receive notification of future changes in an audio/video device's state. Responses to a notify command will indicate the current state of the target and then, at some indeterminate time in the future, indicate the changed state of the target. A target that receives a notify command will return an immediate response frame including either a not implemented, rejected or interim response code. A target will return a not implemented response code when the target does not support the notify command specified or the command is addressed to a subunit not implemented by the target. A target will return a rejected response code when the target implements event notification for the condition specified but is not able to supply the requested information. A target will return an interim response code when the target supports the requested event notification and has accepted the notify command for any future change of state. The current state is indicated by the data returned in the response frame. At a future time, the target will then return an AV/C response frame with either a rejected or changed response code.
A traditional hard disk drive records data and plays it back according to commands received from an external controller using a protocol such as the serial bus protocol (SBP). The external controller provides command data structures to the hard disk drive which inform the hard disk drive where on the media the data is to be written, in the case of a write application, or read from, in the case of a read operation.
Use of a media storage device, such as a hard disk drive, for storing streams of audio and video data is taught in U.S. patent application Ser. No. 09/022,926, filed on Feb. 12, 1998 and entitled "MEDIA STORAGE DEVICE WITH EMBEDDED DATA FILTER FOR DYNAMICALLY PROCESSING DATA DURING READ AND WRITE OPERATIONS," which is hereby incorporated by reference. When storing audio and video data streams on such a hard disk drive, the available capacity of the device can be quickly utilized, due to the large amounts of data included in typical audio and video data streams. If multiple traditional hard disk drives are utilized to store large streams of data, then the user must typically be responsible for management of these storage and retrieval procedures. This storage management responsibility adds complexity to operations such as record and playback and requires the user to monitor and control storage and retrieval operations.

This patent is subject to a terminal disclaimer.

Method of distributed recording whereby the need to transition to a second recording device from a first recording device is broadcast by the first recording device


In an image processing device, an edge image generation part detects an edge in an original image and generates an edge image constituted from the detected edge. A connected pixel extraction part extracts connected pixel groups in the edge image. A binary image generation part classifies the connected pixel groups under respective colors of the connected pixel groups, and generates a character image for each color. A background image generation part generates a background image of the original image based on the character image so that a pixel value at the position of the character image in the original image is set by an average value of the pixel values in the original image with regard to at least a portion of pixels around a rectangle circumscribing the connected pixel groups. An image compression part compresses respective image data of the character image and background image by different compression manners.

The present disclosure relates to an image processing device.
When a character and a background image are separated from an original image and then image data of the character and image data of the background image are separately compressed, in a certain image processing device, the character and the background image are separated from the original image by region analysis processing. Then, a pixel value at the position of the character in the background image is determined by values of pixels around the character (i.e., pixels in contact with the outer periphery of the character).
Another image processing device identifies the position of a predetermined region containing a character portion in the background image by layout information, such as the line of a sentence, and fills the region with a color based on a color around the region.
However, in the technique of the former image processing device mentioned above, a processing speed is comparatively reduced due to the use of the region analysis processing. Further, because the values of the pixels around the character are used, when the color of the character runs to the pixels around the character in the original image, image quality after the compression will be degraded.
The technique described in the latter image processing device mentioned above cannot be used when the layout information is not present. Further, because the entire region is filled with the color around the region, image quality of the region filled with the color will be degraded.

Image processing device generating character image and background image on the basis of connected pixel group


In one aspect, GPS data, ambient signal data, radio frequency data and/or other types of data are used to determine the location of an entrance to an area or a building. In another aspect, sequential trajectory data is collected and the data is analyzed and/or processed to determine the location of an area of interest.

There are a wide variety of mapping and positioning technologies. By way of example, many modern smartphones and mobile devices use the Global Positioning System (GPS). In a typical implementation, the smartphone receives signals from multiple GPS satellites. The GPS signals help indicate the distance between the smartphone and the satellites. The smartphone then uses the GPS data to determine its location, which is typically represented as a geocoordinate or GPS coordinate (e.g., a pair of latitude and longitude coordinates.) The GPS system is used in a wide variety of mapping applications and can be used to pinpoint the location of almost any outdoor landmark, region or building.
One disadvantage of the GPS system, however, is that it is ineffective or substantially less effective in indoor environments, because the walls and ceilings of a building may block the satellite signals. Thus, there are ongoing efforts to develop systems that can identify the location of indoor rooms, structures and other areas where a GPS signal cannot be received.

System for determining the location of entrances and areas of interest


An orthopedic brace having length adjustable supports is provided. The brace comprises upper and lower supports rotatably connected by a hinge. Each of the supports comprises an elongate portion having a channel along part of its length, and a sliding upright that nests within the channel. The upright is incrementally longitudinally translatable within the channel so that the length of the support is adjustable. Flanges are provided along the edges of the channel to prevent lateral separation of the upright from the stationary portion. A spring-biased button protrudes from an upper surface of the channel. The button cooperates with one of a plurality of holes in the upright, providing a positive lock to retain the upright in one of a number of predetermined positions within the channel. The upright is also completely removable from the channel. Removal of the upright from the channel shortens the brace. Straps cooperate with brackets on the supports and/or uprights to secure the brace to a patient's leg.

1. Field of the Invention
The present invention relates to orthopedic braces and, more particularly, to orthopedic braces having length adjustment capability.
2. Description of the Related Art
Orthopedic braces are commonly employed after surgery or for treatment of injury to a joint. Such braces generally serve to stabilize the joint. In certain cases orthopedic braces limit joint flexion and/or extension in a controllable and adjustable manner to prevent re-injury of the joint and to promote rehabilitation.
Some prior art orthopedic braces include length-adjustable support members. However, these braces typically comprise sidebar components that are merely sandwiched together. This configuration makes them susceptible to prying forces that tend to separate the components.
In addition, some prior art braces use threaded fasteners to connect the sidebar components. Adjusting these braces requires a screwdriver or turning a manual thumbscrew, both of which are inconvenient and time consuming. Such braces are also typically prone to failure due to stripped fastener threads. Other braces rely upon friction, as from tightening a lead screw, to hold the components of the brace in the desired position. These braces, however, do not provide a positive lock, and are thus prone to disadvantageous slippage.
Some prior art braces use an all-aluminum construction. Machining and forming aluminum, however, is relatively expensive and has certain physical limitations. Aluminum thus limits the range of features and style that may be incorporated into the brace.

Orthopedic brace having length-adjustable supports


A zoom lens includes a function of preventing blurring of an image due to movements, such as shaking of the zoom lens, by moving the second lens group, in order from the object side, orthogonally to the optical axis in order to correct for blurring of an image due to movements of the zoom lens. The zoom lens includes a first lens group having negative refractive power, a second lens group having positive refractive power, and a third lens group having positive refractive power. The first and second lens groups move along the optical axis during zooming, as does the third lens group in all but one embodiment of the invention. The zoom lens satisfies certain conditions related to the configuration of the lens elements and lens groups of the zoom lens in order to prevent blurring and to provide a compact zoom lens having excellent correction of aberrations.

During photography using a digital camera or a video camera for consumers, recorded images are sometimes blurred due to movements of the zoom lens during image capture caused by the hands of the operator of the camera shaking or by other factors. In a known prior art technique for preventing such blurring of images, specified lenses of the imaging optical system are moved orthogonally to the optical axis in order to provide a function of preventing blurring of an image.
For example, a zoom lens including a function of preventing blurring of an image is disclosed in Japanese Laid-Open Patent Application No. H06-337374. The zoom lens of Japanese Laid-Open Patent Application No. H06-337374 is a two-group zoom lens including, in order from the object side, a first lens group having negative refractive power and a second lens group having positive refractive power. In this zoom lens, the second lens group is moved orthogonally to the optical axis in order to prevent blurring of images due to movements of the zoom lens during image capture.
Japanese Laid-Open Application No. H01-167724 discloses an imaging optical system including multiple lens groups wherein a specified lens group is moved orthogonally to the optical axis in order to prevent blurring of images due to movements of the zoom lens during image capture. In Japanese Laid-Open Application No. H01-167724, the image magnification of this specified lens group is limited to be no larger than a certain value in order to limit the movement off the optical axis in a direction orthogonal to the optical axis required for the specified lens group to prevent blurring of the image being captured.
Additionally, the applicant of the present application disclosed a three-group zoom lens having high resolution in Japanese Laid-Open Patent Application No. 2004-240222. However, this zoom lens does not include a function of preventing blurring of an image.
Recently, there has been increased demand for zoom lenses that are compact overall and include a function of preventing blurring of an image accurately. However, the two-group zoom lens disclosed in Japanese Laid-Open Patent Application No. H06-337374, discussed above, wherein light emerging from the second lens group is nearly collimated before it reaches the image pickup surface, such as a CCD (charge coupled device), tends to have a large overall length, making it difficult to reduce the size of the zoom lens. On the other hand, quick response is required to accomplish highly accurate correction when image blurring movements, such as movements caused by hands shaking, occur. In order to obtain this quick response, it is desirable that the movement off the optical axis of the lenses being used to prevent blurring of a captured image be as small as possible. The imaging optical system of Japanese Laid-Open Application No. H01-167724, discussed above, has successfully reduced the movement off the optical axis required of the lenses being used to prevent blurring of a captured image. However, it does not provide sufficiently accurate correction for movements that cause blurring of a captured image as is desired for future use. Therefore, a zoom lens that more efficiently prevents blurring of a captured image while achieving more compactness is desired.

Zoom lens including a function of preventing blurring of an image


A semiconductor integrated circuit comprises: a latch circuit constituted with a drive inverter and a feedback inverter so as to be connected in a cyclic form, wherein at least one of the drive inverter and the feedback inverter comprises a MOS transistor; and

1. Field of the Invention
The present invention relates to a latch circuit having a function of monitoring process variations of semiconductor chips and to a scan chain circuit that comprises the latch circuit. Furthermore, the present invention relates to a semiconductor integrated circuit device that comprises the scan chain circuit, and a process variation judging method of the same.
2. Description of the Related Art
Recently, process variation of semiconductor chips has been increased in accordance with advanced micropattern of semiconductor integrated circuit devices. As a result, process variations tend to go out of the process control and deteriorate the yield of the products. In order to improve the yield, it is important to monitor the process variations, analyze the information, and feed it back to the manufacturing steps.
Consequently, there is a conventional technique in which an exclusive characteristic evaluation element is mounted on a semiconductor wafer, and process variation is measured with a measuring device provided outside thereof. However, as the characteristic evaluation element is formed on a scribe lane (cutting line), the process variation cannot be measured after packaging. In addition, a prober is required and a large number of measuring steps are required as well.
As a measure taken for the problems described above, conventionally, there is a first proposal for a process variation judging circuit that is capable of judging process variations automatically at a high speed, as disclosed in Japanese Published Patent Literature (Unexamined Patent Publication H11-145237). In this proposal, the process variation judging circuit is mounted within a semiconductor chip, and the process variation of the chip can be measured by outputting information of the process variation of each semiconductor chip through being converted to binary signals.
Further, conventionally, there is a second proposal for a substrate bias control circuit that reduces the process variations. In the second proposal, a device for monitoring the process variation is formed within a semiconductor chip, and a substrate bias is applied to a substrate terminal of a MOS transistor of the semiconductor chip to improve the characteristic of the device. Herewith, the process variation of the MOS transistor can be reduced.
However, it becomes a factor for increasing the size (area) of the semiconductor chip to mount the process variation judging circuit to each semiconductor chip as in the first proposal. Furthermore, the second proposal cannot deal with such a fault that it does not work at a desired operating frequency due to the process variation within the chip, since it has no device improving unit such as a substrate bias control circuit. However, it is more difficult to mount a plurality of process variation judging circuits within a semiconductor chip in terms of the area as described above. Therefore, it is not possible in the first proposal to deal with a plurality of process variations.
In the structure of the second proposal, the monitor circuit monitors the process characteristic only at a certain point within the chip. Therefore, when that certain point does not reflect the process characteristic within the chip, the effect of correcting the variation is diminished.

Latch circuit and semiconductor integrated circuit device that has it

Abstract: a current source connected to at least one of latch nodes of the latch unit. The magnitude relation of electric current flown in the MOS transistor and electric current flown in the current source is judged based on presence or absence of inversions in data values latched in the latch node.


A header assembly for coupling a cardiac lead to a cardiac stimulator is provided. The header assembly includes a header that has a bore for receiving one end of the cardiac lead. The bore has a first longitudinal axis. A connector housing is coupled to the header and has a second bore substantially aligned with the first bore. A biasing member is disposed within the connector housing and has a portion projecting into the second bore to bias the end of the cardiac lead against the walls of the second bore. A set-screw is threadedly coupled to the housing and is operable to secure the cardiac lead to the connector housing when tightened.

1. Field of the Invention
This invention relates generally to cardiac stimulation devices, and more particularly to apparatus for connecting a cardiac lead to a cardiac stimulator, such as a pacemaker or defibrillator.
2. Description of the Related Art
The course of treatment indicated for patients suffering from cardiac arrhythmia normally depends on a number of factors, such as the age of the patient, the type and severity of the arrhythmia, as well as other factors. Many patients may be successfully treated using drug therapy, surgical intervention, or a combination of the two. However, for some patients, the best course of treatment involves direct electrical stimulation of the affected area of the heart by means of an implanted cardiac stimulator.
Conventional implantable cardiac stimulator systems typically consist of a cardiac stimulator and one or more elongated leads. The cardiac stimulator may be a pacemaker, a defibrillator, a sensing instrument, or some combination thereof. The circuitry, batteries, and other components of the cardiac stimulator are ordinarily encased within a metallic housing commonly referred to as a "can." Most of the circuitry of the cardiac stimulator is mounted on a small electronic circuit board commonly known as a multi-chip module or hybrid microcircuit.
The proximal ends of the leads of the cardiac stimulator system are connected physically and electrically to the cardiac stimulator can via a structure commonly known as a header. The distal end of each lead is implanted near the site requiring electrical stimulation or sensing. The leads function to carry electrical stimulation signals from the cardiac stimulator can to the targeted tissue and to transmit sensing signals from the targeted tissue back to the cardiac stimulator can.
A typical header consists of a molded plastic or epoxy structure that encases one or more conductor wires emanating from the cardiac stimulator can. The header also includes one or more longitudinally disposed bores that are dimensioned to receive the proximal ends of the cardiac leads. One or more electrical contacts are provided inside the header and connected to the conductor wires of the header. The contacts are positioned near or around the bore to contact the metallic parts of the proximal ends of the leads. The proximal end of each lead is retained in the header by a set screw that is tightened by the physician at the time the cardiac stimulator system is implanted or by some other retention mechanism.
In a common procedure used by physicians to implant a new cardiac stimulator system, a lead is first implanted inside the body and manipulated so that the distal end of the lead is positioned proximate the targeted tissue. The proximal end of the lead is normally left protruding from the body during the implantation procedure so that it may be readily connected to the cardiac stimulator. After the distal end of the lead has been positioned inside the body, the proximal end of the lead is connected to the header by inserting it into a bore and tightening the set screw. Following connection of the lead, the cardiac stimulator is implanted under the patient's skin.
The electrical contacts inside the header are commonly tubular in shape or are provided with tubular passages and are fabricated with inner diameters that are larger than the outer diameters of the proximal ends of the leads to provide sliding fits between the contacts and the proximal ends of the leads. A sliding fit is preferable to enable the implanting physician to insert the proximal end of the lead with minimal effort and with little risk of damaging the lead or the header. As a result of the relatively loose fit between the contacts and the proximal ends of the leads, the leads may make only intermittent electrical contact or no contact at all with the header until the set screw is tightened. Reliable electrical conduction by the lead is not ensured until the set-screw is tightened. There will normally be some time lag between the moment when the proximal end of the lead is inserted into the header and when the set screw is tightened by the physician.
Most cardiac stimulator system patients will require replacement of all or part of their cardiac stimulator systems at some point in their lifetimes. Replacement may be indicated where the cardiac stimulator has exceeded its useful life span due to battery depletion or malfunction, or where the capabilities of the cardiac stimulator no longer match the arrhythmia condition of the patient. This may occur where the patient has undergone physiological changes as a result of disease, trauma, surgery or other causes. Replacement of a typical cardiac stimulator involves surgical excision of the stimulator, disconnection of the stimulator from the cardiac lead, and connection and implantation of a replacement cardiac stimulator.
Electrical stimulation of the heart will be interrupted from the time the old cardiac stimulator is disconnected from the lead until the new cardiac stimulator is fully connected to the lead and activated. As noted above, complete connection may not be reliably achieved until the set-screw is tightened. In most cases, the duration of the interruption will depend on the skill and speed of the surgeon, and on whether the surgeon must perform any diagnostic procedures on the lead or cardiac stimulator prior to tightening the set screw.
There are several disadvantages associated with conventional lead connection systems. As noted above, the mere insertion of the proximal end of the lead into the header does not guarantee immediate electrical stimulation of the heart. In situations where the lead does not make good contact upon insertion into the header, the patient may not receive electrical stimulation from the cardiac stimulator until the set screw is tightened. Some arrhythmia patients may be adversely impacted by even short interruptions in the application of electrical stimulus to the heart, even in circumstances where the surgeon has made efforts to minimize the disconnection time.
Another disadvantage stems from the way in which conventional leads are held in place in the header. The primary mechanism for retaining the lead in the header is the set screw. Many modern cardiac stimulators have an anticipated implant life span of five years or longer. Following implantation, the connection between the cardiac stimulator and the cardiac lead is subjected to a variety of stresses that stem from the patient's physical activity and/or the rhythmic motion of the patient's breathing and heart beat. Some patients even place stress on the connection by habitually palpating their implanted cardiac stimulators with their hands. High stresses may be imparted by physical trauma to the body. Years of exposure to such stresses may loosen the set screw. In the absence of some other engaging mechanism, the lead may disconnect from the header.
The present invention is directed to overcoming, or reducing the effect of one or more of the foregoing disadvantages.

Connector for implantable medical device


A torque fluctuation absorbing device includes a damping mechanism connected with an input shaft of a transmission. The damping mechanism has an approximately annular-shaped frictional member, which is fixed to both surfaces of a disc disposed at outer peripheral portion. The torque fluctuation absorbing device further includes a flywheel for transmitting driving force from a driving power source, a first plate rotated with the flywheel and abutting on a first surface of the frictional member, a second plate abutting on a second surface of the frictional member, a coned disk spring for biasing the second plate against the frictional member, a supporting member rotated with the first plate and supporting the coned disk spring, and a plurality of fixation members for fixing the first plate with the supporting member. The first plate includes a reinforcement portion which reinforces rigidity of the first plate at an inner circumference portion located radially inwardly relative to the frictional member.

Torque fluctuation absorbing devices, which can absorb torque fluctuation generated between a driving power source (e.g., an internal combustion engine or an electric motor) and transmission, are widely known. Conventional torque fluctuation absorbing devices are provided with a damping mechanism, which can absorb fluctuation of driving torque transmitted to a flywheel from the driving power source, and a limiter portion, which limits torque to be transmitted from the flywheel to a transmission input shaft when fluctuating torque between the damping mechanism and the flywheel reaches a predetermined value, i.e., a limit torque value. The flywheel is connected to the driving power source, such as a crankshaft of the internal combustion engine. The damping mechanism is connected to the transmission input shaft. The damping mechanism includes frictional members that are respectively fixed to both sides of a disc at an outer circumferential portion. At the limiter portion, the frictional members of the damping mechanism are frictionally engaged with the flywheel in a direct manner or in an indirect manner via a frictional plate.
The limit torque value, at which the frictional members at the limiter portion start slipping, varies with the ages in response to the number of the operations of the limiter portion. Therefore, when the limit torque value widely increases, an excessive torque may be inputted to the transmission. As a result, the transmission may be damaged. On the other hand, when the limit torque value widely decreases, the frictional members may start slipping with a torque smaller than normal transmitting torque. In this case, torque may not be transmitted to the transmission.
Frictional powder of the frictional members, which composes of a torque limiter, seems to be one of the factors causing the above problem. In light of the foregoing, JP2003-194095A2 discloses a torque fluctuation absorbing device which forms slits communicating with the frictional member from an inner circumference portion to an outer circumference portion so as to discharge generated frictional powder into an external ambient environment by centrifugal force. The limit torque value can be stable by disposition of slits.
However, in the conventional torque fluctuation absorbing devices, frictional members, which are disposed at an outer circumference of the damping mechanism, are sandwiched by two plates. One plate is biased by a coned disk spring and the other plate is fixed to members, which rotate with the flywheel via rivets or other fixing means. This will raise the following problems.
Even when a coned disk spring 133 abuts on the opposite surface in a region wherein a second plate 132 provided at the coned disk spring 133 side and a frictional member 126 abut, if the abutting portion between the second plate 132 and the coned disk spring is deviated to the inner peripheral side (see FIG. 8A), or to the outer peripheral side (see FIG. 8B), a surface pressure distribution of the frictional surface pressure is not uniform and frictional torque is not stable. In the worst case, the second plate 132 floats up from the frictional member 126 at a portion of low surface pressure.
Within a region wherein a first plate 131, which rotates with the flywheel and the frictional member 126 abut, the bending amount at riveting area by rivets 134 is different from the area away from the riveting area in the first plate 131. This will cause the first plate 131 to be in wave shape in circumferential direction. As a result it, there is a problem wherein a high portion and a low portion are formed on an outer surface of the first plate 131. Thus the surface pressure distribution of the frictional surface pressure becomes inconstant. Therefore stability of frictional torque falls.
A need exists for providing an improved torque fluctuation absorbing device wherein a surface of a plate is flat and smooth relative to a surface of the frictional member and the surface pressure distribution is constant and frictional torque is stable.


An MTJ (magnetic tunneling junction) MRAM (magnetic random access memory) cell is formed on a conducting lead and magnetic keeper layer that is capped by a sputter-etched Ta layer. The Ta capping layer has a smooth surface as a result of the sputter-etching and that smooth surface promotes the subsequent formation of a lower electrode (pinning/pinned layer) with smooth, flat layers and a radical oxidized (ROX) Al tunneling barrier layer which is ultra-thin, smooth, and to has a high breakdown voltage. A seed layer of NiCr is formed on the sputter-etched capping layer of Ta. The resulting device has generally improved performance characteristics in terms of its switching characteristics, GMR ratio and junction resistance.

1. Field of the Invention
This invention relates generally to magnetic tunneling junction (MTJ) MRAMs and more particularly to the use of a simple fabrication process that leads to a smooth bottom electrode and superior performance properties.
2. Description of the Related Art
The magnetic tunneling junction device (MTJ device) is essentially a variable resistor in which the relative orientation of magnetic fields in an upper and lower magnetized electrode controls the flow of spin-polarized tunneling electrons through a very thin dielectric layer (the tunneling barrier layer) formed between those electrodes. As electrons pass through the lower electrode they are spin polarized by its magnetization direction. The probability of an electron tunneling through the intervening tunneling barrier layer then depends on the magnetization direction of the upper electrode. Because the tunneling probability is spin dependent, the current depends upon the relative orientation of the magnetizations of magnetic layers above and below the barrier layer. Most advantageously, one of the two magnetic layers (the pinned layer) in the MTJ has its magnetization fixed in direction, while the other layer (the free layer) has its magnetization free to move in response to an external stimulus. If the magnetization of the free layer is allowed to move continuously, as when it is acted on by a continuously varying external magnetic field, the device acts as a variable resistor and it can be used as a read-head. If the magnetization of the free layer is restricted to only two orientations relative to the fixed layer (parallel and anti-parallel), the first of which produces a low resistance (high tunneling probability) and the second of which produces a high resistance (low tunneling probability), then the device behaves as a switch, and it can be used for data storage and retrieval (a MRAM).
Magnetic tunneling junction devices are now being utilized as information storage elements in magnetic random access memories (MRAMs). Typically, when used as an information storage or memory device, a writing current orients the magnetization of the free layer so that it is either parallel (low resistance) or anti-parallel (high resistance) to the pinned layer. The low resistance state can be associated with a binary 0 and the high resistance state with a binary 1. At a later time a sensing current passed through the MTJ indicates if it is in a high or low resistance state, which is an indication of whether its magnetizations are, respectively, antiparallel or parallel and whether it is in a 0 or 1 state. Typically, switching the magnetization direction of the free layer from parallel to antiparallel and vice-versa is accomplished by supply currents to orthogonal conductor lines, one which is above the MRAM cell and one which is below it. The line below the cell is referred to as the word line and it is electrically isolated from the cell. The line above the cell, called the bit line, is in direct electrical contact with the cell and is used for both writing on the cell, ie changing the direction of the free layer magnetization and reading the cell, ie detecting the free layer magnetization direction. The two lines pass each other orthogonally, in separated vertical planes, with the cell lying between them. Thus their combined field peaks just above the switching threshold of the cell, the field required to cause a transition from parallel to antiparallel orientations of the free layer and pinned layer magnetizations.
For fast operation, the cell must have a high magnetoresistance ratio (DR/R), where DR represents the resistance variation when the free layer switches its magnetization direction and R represents the total minimum resistance of the cell. For stable operation, the cell's junction resistance, RA, where A is cell cross-sectional area, must be well controlled. When the MRAM device is used as the basic element of a memory, it is replicated to form an array of many such devices and integrated with associated CMOS circuitry which accesses particular elements for data storage and retrieval.
When fabricating an MRAM element or an array of such elements, the necessity of creating a high value of DR/R and maintaining a high degree of control over the junction resistance requires the formation of thin, smooth layers of high quality.
Slaughter et al. (U.S. Pat. No. 6,544,801 B1) teaches a method of fabricating such a magnetic tunneling device wherein the problem of interdiffusion between layers of different metals during high temperature annealing processes is significantly reduced. Such interdiffusion would adversely affect the properties of the various layers because of the tendency of the various metals to alloy with each other.
Dill et al. (U.S. Pat. No. 6,114,719) teaches a method of effectively biasing an MTJ device using biasing layers disposed within the device stack, so that its magnetic states are stable, yet there is not required the addition of adjacent magnetic structures which would adversely affect the high device density required for an MRAM array.
In a "standard process" MRAM array structure the MTJ stack (lower electrode/AlOx tunneling barrier/upper electrode) is deposited on top of the bottom conductor, which is typically a tri-layer such as Ta/Cu/Ta or NiCr/Ru/Ta. In the latter tri-layer, the Ta that caps the Ru is grown with an α-phase structure, in the former tri-layer, the Ta that caps the Cu is grown with a β-phase structure. Prior to depositing the MTJ stack it is necessary to sputter-etch the TaO which grows on the Ta capping layer. This sputter-etch not only removes the surface TaO, but the energetic Ar sputtering ions also alter the Ta surface structure. The resulting sputter-etched Ta surface appears to be "amorphous-like", similar to that of amorphous Al2O3. In our experiments we have found that an altered Ta surface is necessary for forming a flat, smooth bottom electrode on which to most advantageously form an oxidized Al tunneling barrier layer of high integrity. It was also noted by us that refilling the sputter-etched Ta surface by a Ta sputter-deposition actually results in a rougher surface structure of the bottom electrode. The integrity of the oxidized Al barrier layer is an essential element in fabricating a high quality MTJ device.
Formation of a high-speed MRAM array is quite complicated. Normally its word line structure is surrounded by a dielectric layer, so the line essentially lies within a cavity. This cavity has a back (or bottom) surface and two parallel side surfaces that are spaced apart. The back and/or side surfaces of the cavity are covered with an NiFe magnetic layer which acts as a field keeper (it contains the magnetic flux). The conducting portion of the line, surrounded by the magnetic keeper structure, is formed within the cavity. A polishing process is then used to remove any portion of the keeper or conducting portion of the line that extends above the level of the dielectric surface and to generally render that surface planar.
A novel MRAM array structure, not using the conducting lead structure of the standard process, has been developed in which the word line is constructed on top of the MTJ. The MRAM configuration of this novel array structure is:NiCr50/NiFe100/NiCr30/Cu50/MnPt100/CoFe18/Ru7.5/CoFe15/Al(8–10)/ROX/free/capThe NiCr50/NiFe100/NiCr30/Cu50 portion is the bottom conducting lead (the numerals representing thicknesses in angstroms), which includes a NiCr 50 seed layer, a 100 angstrom NiFe soft adjacent keeper layer, a second NiCr 30 seed layer and a Cu 50 conducting layer; the MnPt100/CoFe18/Ru7.5/CoFe15 portion is the bottom electrode (a synthetic pinned structure), the Al(8–10)/ROX is a tunneling barrier layer formed by radical oxidation of an 8–10 angstrom thick Al layer and then there is the upper electrode, which includes a free layer and a capping layer formed thereon but not described here in detail. The entire stack is advantageously formed by magnetron sputtering in a single pump-down of the sputtering chamber.
In initial testing of this single pump-down fabrication, RA (junction resistance), DR/R and Vb (breakdown voltage of the barrier layer) were found to be much lower than values obtained from the standard (prior art) process in which the patterned conductor lead and the MRAM stack are formed separately. Further, high resolution TEM analysis of the single pump-down layers showed that the bottom electrode layers had a columnar grain structure, which tended to create rough surfaces. In contrast, the surfaces of layers formed in the standard process were relatively smooth and flat. The essential difference in the two processes is that the standard process configuration includes a Ta capping layer that is sputter-etched.
The object of this invention is to modify the single pump-down process so that a smooth, flat layered structure (as in the standard process) is obtained while still maintaining the advantages of the single pump-down of the novel process.

Structure/method to fabricate a high-performance magnetic tunneling junction MRAM


A container for holding a smoker's article. The container has a lid and a body. The body includes a first chamber for holding smoker's articles, and a second chamber for holding a cigarette or a pipe. The lid is rotatably supported atop the container and is rotatable between the position covering both, or at least partially covering one or the other of the two chambers. A magnet in the body cooperates with a magnet in the lid for retaining the lid in the closed position over both chambers. A third small hole or chamber in the body is shaped to receive a magnetized element such as a poker. A magnet at the top of the body removably magnetically retains the poker in its chamber.

The invention concerns a smoking system and more particularly a smoking system to hold smoking tobacco, a pipe and/or a cigarette and additionally a metallic poker. The invention concerns a container or case and lid with a novel closure. It has a similar purpose to and is an improvement on the smoking system disclosed in U.S. Pat. No. 4,214,658.
U.S. Pat. No. 4,214,658 discloses a container with separate chambers for receiving a pipe, or a tubular item in one chamber and for receiving other smoking material, such as loose tobacco, in another chamber. A lid over the container covers the openings into the two chambers and the lid is slid laterally in a slideway to allow access to one or the other chamber.
In the '658 patent and other prior art, the lid of a container for a smoking system is attached mechanically, e.g., by being slid between positions or by being otherwise attached to the top of the container. The present invention concerns another mode of attachment of a lid.
Further, if a smoking system includes a metal poker, which would be used for example to clean a pipe or to work with tobacco in a pipe bowl, and the poker is made of metal, particularly steel, the prior art does not disclose a manner of using the material of the poker for securely retaining the poker in the container of the system. In contrast, the present invention provides the possibility of securely retaining a metal poker in the container by using the material of the poker.

Tobacco and cigarette container with poker and magnetic closure


A story describing an activity performed by an interacting user is distributed to viewing users according to the influencer scores for the viewing users. Each influencer score can be calculated based at least in part on the influence of a viewing user on those users connected to the viewing user, and on the influencer scores for the users connected to the viewing user. Based on the determined influencer scores, at least one of the viewing users can be provided with the story describing the activity performed by the interacting user.

This invention generally pertains to social networking, and more specifically to computing influencer scores for users of a social networking system and targeting stories describing a user activity based on influencer scores.
Social networks, or social utilities that track and enable connections between users (including people, businesses, and other entities), have become prevalent in recent years. In particular, social networking systems allow users to communicate information more efficiently. For example, a user may post contact information, background information, job information, hobbies, and/or other user-specific data to a location associated with the user on a social networking system. Other users can then review the posted data by browsing user profiles or searching for profiles including specific data. The social networking systems also allow users to associate themselves with other users, thus creating a web of connections among the users of the social networking system. These connections among the users can be exploited by the social networking system to offer more relevant information to each user in view of the users' own stated interests.
Social networking systems typically incorporate a system for connecting users to content that is most likely to be relevant to each user. For example, users may be grouped according to one or more common attributes in their profiles, such as geographic location, employer, job type, age, music preferences, interests, or other attributes. Users of the social networking system or external parties can then use these groups to customize or target information delivery so that information that might be of particular interest to a group can be communicated to that group.
Advertisers have attempted to leverage this information about members by targeting their ads to members whose interests best align with the ads. For example, a social networking system may display banner ads for a concert to members who include an affinity for the performing band in their social networking system profile and live near a concert venue where that band might be performing. However, these attempts are no different than targeting of ads that exist in many other contexts. Advertisers have not yet been able to exploit the relationships and connections among members of a social networking system in a meaningful way to increase user engagement with an advertisement, advertised product, or brand.

Targeting stories based on influencer scores


Systems and methods for a split phase accumulator having a plurality of sub phase accumulators are provided. Each sub phase accumulator receives a portion of a frequency control word. The first sub phase accumulator includes a first register and the remaining sub phase accumulators include a register and an overflow register. At each discrete point in time, the first sub phase accumulator is configured to be responsive to the first portion of the frequency control word at that discrete point in time and to the first sub phase accumulator value at the immediately previous discrete point in time, and each of the remaining sub phase accumulators is configured to be responsive to a value of its corresponding portion of the frequency control word at that discrete point in time and to the same second sub phase accumulator value at the immediately previous discrete point in time.

Direct digital synthesizers, commonly referred to as DDS or DDFS, are widely used in digital devices. A direct digital frequency synthesizer (DDS) can be considered a special case of a digital mixer. While the mixer rotates an arbitrary point in the plane by an angle specified by the normalized rotation angle, θ, the DDS always rotates a fixed point, which can be considered to be the point (1, 0).
The phase accumulator in a DDS employs a relatively long phase word (e.g., the word length M=32 bits for the examples we have been using here, and M=48 bits has been used in commercial products described in "1 GSPS Direct Digital Synthesizer with 14-Bit DAC," AD9912 Data Sheet, Analog Devices, Inc., 2007-2010 and "2.7 GHz DDS-Based AgileRF™ Synthesizer," AD9956 Data Sheet, Analog Devices, Inc., 2004). When incrementing the phase accumulator by adding a frequency control word (FCW) to it, a long carry-ripple delay can be problematic. For example, the use of Artisan library cells for TSMC 0.18-μm CMOS can require a carry-ripple delay that is sufficiently long as to make running the phase accumulator at a desired 250-MHz speed expensive in terms of power dissipation. A well-known technique for increasing the frequency at which a DDS phase accumulator can be updated is to employ some form of pipelining of the phase accumulator.
When pipelined, a 32-bit phase accumulator can run at 250-MHz in TSMC 0.18-μm CMOS. In addition to the increased hardware expense incurred by the pipelining circuitry, one residual problem remains: the inherent pipeline-induced delay and/or complexity when one desires to instantaneously change the frequency being generated by changing FCW. (Instantaneous frequency changing is one of the very desirable capabilities of a DDS; indeed, such a feature is perhaps unique to a DDS, in comparison with other types of oscillators.) When changing to a new FCW value, in a pipelined-phase-accumulator system, it can be a problem that the least-significant part of the phase accumulator must be incremented in a previous output-data cycle to that in which the most-significant part of the phase accumulator is incremented, and solving this and related problems can require additional and more complicated circuitry and/or performance compromises.
What is therefore needed is a DDS that solves the phase accumulator speed-up problem.
The present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers can indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number may identify the drawing in which the reference number first appears.

Excess-fours processing in direct digital synthesizer implementations


The present invention is an address mapping gateway, used in an internetwork link, that associates all nodes in a domain with a single network number (referred to as a domain network address), and provides gateway-mapped node addresses that are unique within the domain. The address mapping gateway dynamically substitutes the "globally-unique" domain network address and the "domain-unique" gateway-mapped node address for a network number and node address, respectively, of a network layer address of a packet header received from a source node in the domain. Conversely, when a packet is received for a destination node in the domain, the address mapping gateway substitutes the originally-assigned network number and node address for the domain network address and gateway-mapped node address, respectively, prior to forwarding the packet to the node. Specifically, the address mapping gateway maintains an address mapping table that provides a cross-reference between (1) a source node address and the network number of the local network in which the node resides, and (2) a gateway-mapped node address generated by the address mapping gateway. Upon receipt of a packet from the source node, the address mapping gateway creates a mapping entry in the address mapping table that node and performs an address translation to a globally-unique network layer address. On the other hand, upon receipt of a packet destined for a destination node in the domain, the address mapping gateway locates the mapping entry for the packet's gateway-mapped node address and performs a reverse address translation to the originally-assigned network layer address.

1. Field of the Invention
The present invention relates generally to computer networks and, more particularly, to routing packets in an internetwork.
2. Description of the Related Art
Internetworking is the process of establishing and maintaining communications and transferring data among multiple local networks in a distributed network system. The purpose of an internetwork is to provide end-to-end service between one user (a source node) and another user (a destination node).
FIG. 1 depicts an exemplary embodiment of an internetwork system 100, comprising a plurality of routing domains 104-108 coupled to a backbone network 102. In the hierarchically-arranged distributed internetwork system 100, backbone 102 is the top-level, or central, connection path shared by the nodes and networks connected to it, managing the bulk of the traffic between communicating nodes.
Each routing domain 104-108 is a collection of routers that are part of a larger network, such as internetwork 100. Routing domains are also referred to as customer networks or autonomous systems. Domains 104-108 are connected to the backbone 102 through nodes referred to as routers 110, 112 and 114, respectively.
Each routing domain is a collection of one or more local networks, such as local area networks (LAN), metropolitan area networks (MAN), wide area networks (WAN), etc., that are attached to the backbone through one or more routers. In the following discussion, the term "local network" shall be used to refer to all types of networks that may be included in a domain. For example, domain 104 includes local networks 116, 118, and 120. A local network is depicted as a line to which stations can be attached. If a station, or end node, attaches to the bold line, it can transmit packets to, and receive packets from, every other station attached to that same bold line. The source and destination nodes are, typically, computers (workstations and servers) but may be any type of device that can include a network interface card (NIC), such as a printer or modem. Each domain may contain intradomain routers for managing communications among local networks within a particular domain. The routers within a routing domain communicate with each other using a common intradomain routing protocol, such as Routing Information Protocol (RIP) and Integrated IS-IS (Intermediate System-to-Intermediate System) protocols.
In order to reduce design complexity, most networks are organized as a series of hardware and software levels or "layers" within each node. These layers interact to format data for transfer between, for example, a source node and a destination node communicating over the network. Specifically, predetermined services are performed on the data as it passes through each layer and the layers communicate with each other by means of predefined protocols. This layered design permits each layer to offer selected services to other layers using a standardized interface that shields those layers from the actual implementation details of the services.
In an attempt to standardize network architectures, that is, the sets of layers and protocols used within a network, a generalized model has been proposed by the International Standards Organization (ISO). The model, called the Open Systems Interconnection (OSI) reference model, is directed to the interconnection of systems that are "open" for communication with other systems. The proposed OSI model has seven layers which are termed, in ascending interfacing order, the physical, data link, network, transport, session, presentation, and application layers. These layers are arranged to form a "protocol stack" in each node of the network.
FIG. 2 illustrates a schematic block diagram of OSI protocol stacks 202-208 used to transmit data between, for example, a source node 123 and a destination node 126 through routers 130 and 132, all of which are elements of internetwork 100. Each protocol stack is structured according to the OSI seven-layer model; accordingly, each stack comprises a collection of protocols, one per layer. The routers will make use of the lower three OSI layers, known as the subnet layers, to move the data along to the next router or the destination node. As can be seen, the protocol stacks 202-208 are physically connected through communications channels 118 at physical layers 230-250; 117 at physical layers 250-260; and 120 at physical layers 260-270. Data flow is schematically illustrated by solid arrows. For ease of description, the protocol stack 202 will be described.
Broadly stated, the physical layer 230 transmits a raw data bit stream over a communication channel 118, while the data link layer 232 manipulates the bit stream and transforms it into a datastream that appears free of transmission errors. This latter task is accomplished by dividing the transmitted data into frames and transmitting the frames sequentially, accompanied with error correcting mechanisms for detecting or correcting errors. The network layer 234 routes data packets from the source node 123 to the destination node 126 by selecting one of many alternative paths through the physical network. The transport layer 236 accepts the datastream from the session layer 238, apportions it into smaller units (if necessary), passes the smaller units to the network layer 234 and provides appropriate mechanisms to ensure that all the units arrive correctly at the destination node.
The session layer 238 establishes data transfer "sessions" between software processes on the source and destination nodes, along with management of such sessions in an orderly fashion. That is, a session not only allows ordinary data transport between the nodes, but it also provides enhanced services in some applications. The presentation layer 240 performs frequently-requested functions relating to the presentation of transmitted data, including encoding of data into standard formats, while the application layer 242 contains a variety of protocols that are commonly needed by processes executing on the nodes.
Data transmission over the internetwork 100 therefore consists of generating data in, for example, a sending process 210 executing on the source node 123, passing that data to the application layer 242 and down through the layers of the protocol stack 202, where the data are sequentially formatted as a packet for delivery onto the channel 118 as bits. Those packet bits are then transmitted to the protocol stacks 204 and 206 of the routers 130 and 132, respectively, and finally to stack 208 of the destination node 126, where they are passed up that stack to a receiving process 212.
Although actual data transmission occurs vertically through the stacks, each layer is programmed as though such transmission were horizontal. That is, each layer in the source node 123 is programmed to transmit data to its peer layer in the destination node 126, as schematically shown by dashed arrows in FIG. 2. To achieve this effect, each layer of the protocol stack 202 in the source node 123 typically adds information (in the form of a header field) to the data packet generated by the sending process as the packet descends the stack. At the destination node 126, the various headers are stripped off one-by-one as the packet propagates up the layers of protocol stack 208 until it arrives at the receiving process 212.
The source and destination network layer addresses are typically hierarchical and consist of a plurality of elements, including a network number and a node address. Within each local network, each node has a unique node address that identifies a particular node in a particular local network. The node address is also known as a node ID or node number.
In addition to a unique node address, each node in a local network has a common network number. Within each domain, routing is based on this network number and, therefore, these numbers are assigned so that they are unique within each particular local network. That is, the network numbers are arbitrary values that are assigned identically to each node in a local network. Routers 110-114 (FIG. 1) "advertise" to the backbone the network numbers in their domain networks that they can access. A network number is also referred to as a local network number or Internetwork Packet Exchange.TM. (IPX.TM.) network number. The network layer address, which includes both the network number and the node address, is also referred to as the local network address or IPX network address.
Presently, in order to support end-to-end connectionless communications between all nodes in an internetwork, every local network must have a unique network number to distinguish the nodes in that network from other nodes in other local networks in the internetwork. Thus, no two local networks in an entire internetwork may have the same network number.
However, there has been no global enforcement regarding the assignment of network numbers to local networks, resulting in arbitrarily-assigned network number values within an internetwork. Accordingly, as the number of local networks in the internetwork increases, so does the incidence of conflicting network layer addresses due to the assignment of non-unique network numbers. This phenomenon results in address collisions, adversely affecting the ability of the internetwork to reliably route packets to a particular destination node.
In addition, in recent times, the size of internetworks has increased dramatically, placing a burden on routers to support large numbers of local networks. For example, some routers perform route aggregation as a technique for summarizing a large quantity of network numbers by associating them with a particular domain, enabling an implementing router to identify a range of network numbers with a relatively small amount of information. Oftentimes however, conventional routing protocols such as IPX RIP do not support route aggregation. Thus, in order to provide the ability to communicate with every node, the backbone must allocate resources for storing and retrieving every network number for every local network in the internetwork.
Although some routing protocols such as IS-IS and NetWare.RTM. Link Services Protocol.TM. (NLSP.TM.) software implement some form of aggregation, such protocols still suffer from the above drawback of being unable to properly identify local networks when non-unique network numbers exist. Furthermore, although aggregation may be possible, oftentimes the manner in which the network numbers are assigned does not necessarily lend itself to summarization.
One conventional approach to ensuring that all local networks have a unique network number has been to require all nodes in a local network to change the network number associated with that local network prior to connecting to the internetwork. One drawback to this approach is that the routers must be reconfigured to support these new network numbers. In addition, once all the local networks in the internetwork have a globally-unique network number, the backbone must still provide the resources necessary to maintain the large number of network numbers in the internetwork. Furthermore, routers that cannot aggregate are incapable of servicing the resulting large number of network numbers.
In order to maintain unique network layer addresses in an internetwork having local networks with redundant network numbers, some routing protocols, such as AURP (AppleTalk.RTM. Update Routing Protocol) of the AppleTalk Protocol Suite, provide a unique network number for every local network in the internetwork. This information, typically maintained as part of the routing table, simply provides a one-to-one mapping of a non-unique network number to a unique network number. Although these types of protocols result in a unique network number for each local network, they do not address the inability of certain routers to support the large number of network numbers that must be addressed by the router. In other words, a router unable to support the large number of potentially non-unique network numbers will also be unable to support the same number of globally-unique network numbers. Furthermore, conflicts often arise between the new network number and certain upper-layer protocols that are sensitive to address changes.
Another conventional approach is to expand the address space of nodes coupled to the internetwork to provide new and modified elements to a conventional hierarchical network layer address. This approach is described in pending U.S. patent application Ser. No. 08/499,103, entitled "Network Addressing Arrangement For Backward Compatible Routing of an Expandable Address Space," naming as inventors Radia J. Perlman and Neal D. Castagnoli, filed on Jul. 6, 1995, and assigned to the assignee of the present invention. However, this approach requires time consuming and costly upgrading of all nodes in a domain to support this expanded address space.
What is needed, therefore, is a means for providing addressing information to reliably route communications among local networks of an internetwork in a manner that is not adversely affected by redundant network numbers and that does not require large amounts of addressing information to be maintained by the backbone or routers.


The present invention relates to the selection and development of superior strain of Bacillus spp for improving plant growth and health by inhibiting pathogenic fungi.

Crops under cultivation suffer from many diseases caused by plant pathogenic fungi. One particularly damaging plant phytopathogenic fungus is Rhizoctonia solani which is widely distributed and causing common diseases of greenhouse-grown crops, field crops, vegetables, ornamentals, and fruits throughout the world. It also causes root rot and wilt disease of pyrethrum and geranium. Other detrimental fungal plant pathogens include Sclerotinia sclerotiorum, Thielavia basicola, Fusarium oxysporum, causing wilt, Pythium aphanidermatum causing lethal yellowing and damping off in numerous plants.
The incidence of various kinds of fungal diseases cause considerable damage to the medicinal and aromatic plants (MAPS) in different part of India. The occurrence in severe form may either kill emerging seedlings or reduce plant growth and adversely affect the crop yield. Among fungal pathogens, species of Rhizoctonia, Sclerotinia, Fusarium, Thielavia, Pythium, Helminthosporium, Curvularia, Alternaria and Colletotrichum are most important and common. They produce different kinds of diseases such as stem rot and twig blight (Sclerotinia sclerotiorum) on periwinkle, Egyptian henbane and Ammi majus; root rot & wilt (Rhizoctonia solani) diseases on pyrethrum, leaf blight (Curvularia andropogonis); lethal yellowing (Pythium aphanidermatum) and collar rot (Fusarium moniliforme) on Java citronella; damping-off (Pythium dissotocum), collar rot (Rhizoctonia solani) and leaf blight (Alternaria alternata) on opium poppy, stolon and root rot (Thielavia basicola), wilt (Fusarium oxysporum), leaf blight (Corynespora cassiicola) on mints and anthracnose (Colletotrichum acutatum) and wilt (Rhizoctonia solani) on geranium; (Alam et al 1983, Indian Phytopath. 367: 480–483; ibid 1992, Plant Disease 43:10578–1061; ibid 1994, Plant Pathology 43:1057–1061; ibid 1996, Indian Phytopath. 49:94–97; Sattar et al. 1993, Indian J. Plant Pathol 10: 10–11; ibid 1999, Indian J. Plant Pathol. 17:74–76; ibid 2002, J. Mycol. & Pl. Pathol. 32: 31–34).
The use of huge amount of fertilizers and chemical pesticides for maintaining the high productivity of crop has become fatal to human and animal health. They also poses many other serious problems including i) development of resistant strains of pathogen (Schwinn et al., (1991) "Control with Chemicals" Advances in Plant Pathology: vol. 7: Phytophtohora infestans, the Cause of Late Blight of Potato, Ingram et al., eds., Academic Press, 8: 255–266) ii) build up of harmful residues in the edible plant and iii) non-target side effect of beneficial micro flora. It is desirable to replace them with biopesticides derived from the microorganisms. They are as effective as broad-spectrum chemical pesticides, easily degradable and have low cost production. They are a distinct possibility for the future and can be successfully exploited in modern agriculture without affecting our precious ecosystem.
Plant growth promoting rhizobacteria (PGPR) exert a beneficial effect on the plant by causing plant growth promotion and/or suppressing plant pathogen population to avoid infection. Efforts to select and apply PGPR for control of specific soilbome fungal pathogens have been reviewed (Kloepper, 1993; Glick and Bashan, 1997 Biotechnology Advances 15, 353–378). In most of the cases, activity is due to production of metabolites such as antibiotics, hydrogen cyanide, iron-chelating siderophores, and cell wall-degrading enzymes, which directly inhibit the pathogen. Plant growth promotion by PGPR may also be an indirect mechanism leading to a reduction in the probability of a plant contracting a disease when the growth promotion results in shortening the time that a plant is in a susceptible state. An alternative mechanism for biological control by PGPR is by induced systemic resistance.
Bacillus subtilis and few other Bacillus spp. are used as biocontrol agents of fungal diseases caused by different plant pathogens (Swinburne et al. (1975) Trans. Brit. Mycol. Soc. 65:211–217, Baker et al. (1983) Phytopathology 73:1148–1152, Singh and Deverall, (1984) Trans. Br. Mycol. Soc. 83:487–490, Cook (1987) Proceedings Beltwide Cotton Production—Mechanization Research Conference, Cotton Council, Memphis, pp. 43–45, Gueldner, et al., (1988) J. Agric. Food Chem. 36:366–370, Pusey et al. (1988) Plant Dis. 72:622–626, Ferreira et al. (1991) Phytopathology 81:283–287, Sholberg et al. (1995) Can. J. Microbiol. 41:247–252, Asaka, and Shoda, (1996), Appl. Environ. Microbiol. 62:4081–4085). McKeen et al. (1986) Phytopathology 76:136–139 and Pusey and Robins (1991) U.S. Pat. No. 5,047,239 disclose control of post harvest fruit rot using B. subtilis. Among different Bacillus spp (B. subtilis, B. megaterium B. cereus, B. polymyxa and B. pumilus), B. subtilis is most exploited as biocontrol agent because it is considered to be a safe and potential biological control agent due to high thermal tolerance, rapid growth in liquid culture, ready formation of resistant spores. Handelsman (1991) U.S. Pat. No. 5,049,379 disclose that Zwittermicin-A producing B. cereus control damping off in alfalfa and soybeans by inhibiting root rot fungus. A Bacillus subtilis GBO3 strain is commercially used as seed dresser under the names KODIAC.™. HB. or GUS 2000.™. by Gustafson, Inc. Plano, Tex. 75093 (EPA Reg. No. 7501–146, 1992). This product is available as a 2.75% powder formulation containing not less than 5.5.times10. sup. 10 viable spores per gram and is to be applied at a rate ranging from 2–4 ounces per 100 pound of seed. The bacteria is said to colonize the developing root systems and compete with pathogens that would attack the roots. Huang et. al (1993), Can. J. Microbiol. 39: 227–233 investigated antagonistic behavior of two strains of Bacillus cereus; alf-87A & B-43 against Sclerotinia sclerotiorum, the causal agent of basal pod rot & end rot disease on dry pea. The vegetative growth & ascosporic germination of S. sclerotiorum are inhibited by diffusible metabolite produced by alf-87A but are unaffected by strain B-43 The spraying on pea plants at the pod development stage with alf-87A reduce the incidence of basal rot. The treatment of soybeans with B. cereus has been shown to improve soybean yield at field site (Osburn et al. 1995 Am. Phytopathol. Soc. 79: 551–556). Chen et al (2002) Chinese J. Biol. Control 18:45–46 report that antagonistic activity of B-916 strain of B. subtilis against R. solani is due to proteins because addition of ammonium sulphate in culture solution destroys its antagonistic ability. The application of B. subtilis reduced the stem canker disease caused by R. solani and common scab disease caused by Streptomyces scabies up to 63% and 70%, respectively. Liu et al. (1995) U.S. Pat. No. 5,403,583 disclosed a Bacillus sp., ATCC 55000 and a method to control the fungal plant pathogen, Rhizoctonia solani. Leifert et al. (1995), J. Appl Bacteriol. 78:97–108, reported the production of anti-Botrytis and anti-Alternaria antibiotics by two Bacillus strains, B. subtilis CL27 and B. pumilus CL 45. The whole broth and cell-free filtrates were active against Botrytis and Alternaria in in vitro tests and were active against Botrytis in in vivo small plant tests. Leifert et al. (1997) U.S. Pat. No. 5,597,565 disclosed that B. subtilis, B. pumilus and B. polymyxa are effective against post harvest disease caused by Alternaria brassicicola and Botrytis cinerea. They also disclose the presence of antibiotics produced in the cell-free culture filtrate and their activity at different pH values, but they do not identify these compounds. The compounds from B. subtilis lose activity at low pH, while the activity from the B. pumilus extracts occurs only at pH values below 5.6. Leifert, et al. (1998) U.S. Pat. No. 5,780,080 disclose that the growth of Botrytis cinerea and Alternaria brassicicola causing post-harvest disease is inhibited by applying isolates of Bacillus pumilus NCIMB 40489 and Bacillus subtilis NCIMB 40491 to cabbage at temperatures of about 20.degree C.
Bacilli are known to produce antifungal and antibacterial secondary metabolites (Korzybski, et al., 1978 "Section C: Antibiotic isolated from the genus Bacillus (Bacilliaceae)" In: Antibiotics—Origin, nature and properties, American Society for Microbiology, Washington D.C. Vol. III, pp. 1519–1661). The chemical nature of antibiotics produced by Bacillus spp. are peptide by the action of which they inhibit the growth of fungal plant pathogens in the microenvironment (Katz and Demain 1977 Bacteriological Reviews, 41, 449–474; Singh & Deveral 1984; McKeen et al. 1986; Utkhede et al (1986) Can. J. Microbiol. 32: 963–967; Wilson et al. (1989) Annual Review of Phytopathology. 27, 425–441, Hiraoka et al., (1992) J. Gen. Appl. Microbiol. 38:635–640.). Islam and Nandi (1985) J. Plant Dis. Protect. 92:241–246, disclose a Bacillus sp. with antagonism to Drechslera oryzae, the causal agent of rice brown spot. The same authors, Islam and Nandi (1985) J. Plant Dis. Protect. 92(3):233–240, also disclose in-vitro antagonism of Bacillus sp. against Drechslera oryzae, Alternaria alternata and Fusarium roseum. They discussed three components in the culture filtrate. The most active antibiotic was highly soluble in water and methanol with a UV peak at 255 nm and a shoulder at 260 nm, that proved to be a polyoxin-like lipopeptide. Loeffler et al. (1986) J. Phytopathology 115:204–213, disclose B. subtilis, B. pumilus, B. licheniformis, and B. coagulans strains that produce various antibiotics with antifungal and antibacterial activity. B. pumilus produces bacilysin and iturin A. Bacilysin is a very small compound with a molecular weight of 270, that inhibits only yeast. The iturins, which are soluble in polar solvents, have broad antifungal and antibacterial activity. McKeen et al. (1986), have shown that antibiotics similar to the low molecular weight iturin cyclic polypeptides contribute to the fungicidal activity of B. subtilis. Rossall's (1991) U.S. Pat. No. 5,061,495 provides a novel antibiotic from B. subtilis that is 63,500 Dalton, precipitates at a pH below 5 and has activity against gram positive bacteria and fungi (Botrytis and Erysiphe). Rossall's (1994) U.S. Pat. No. 5,344,647 discloses Bacillus subtilis strains with broad anti-fungal activity. Stabb et al. (1994), Applied Environ. Microbiol. 60: 4404–4412 have identified different strains of B. subtilis, B. cereus, B. mycoides, B. thuringiensis that exhibit antifungal activity. These strains have been shown to produce zwittermicin-A and/or kanosamine (Milner et al. 1996, Applied Environ. Microbiol. 62: 3061–3066), that are effective against damping off disease caused by Phytophthora medicagenis, P. nicotianae, Pythium aphanidermatum or Sclerotinia minor. Zwittermicin-A is a water soluble, acid stable linear aminopolyol molecule (He et al. 1994, Tetrahedron Lett. 35: 2499–2502) with broad spectrum activity against many fungal and bacterial plant pathogens. Kanosaminealso inhibits a broad range of fungal plant pathogens and a few bacterial species (Milner et al. 1996).
Germida, et al. U.S. Pat. No. 6,015,553 disclosed Bacillus subtilis strain AQ743 that produces a metabolite exhibiting pesticidal activity against corn rootworm. Hassanein and El-Goorani (1992) J. Plant Pathol. 133: 239–246 reported that application of B. subtilis on wounded caster bean plants 30 min. before or simultaneously with inoculation of Agrobacterium tumefaciens, resulted in good control of crown gall without any phytotoxic injury or growth retarding side effect.
So in the present invention systematic experiments were planned to isolate and select superior strain of Bacillus strain for promoting the growth of medicinal and aromatic plants as well as inhibiting the growth of plant pathogenic fungi.

Council of Scientific and Industrial Research


A display apparatus includes a liquid crystal panel including a pair of substrates and a liquid crystal layer sandwiched between the substrates; a polarizing plate provided on the side of the liquid crystal panel from which display light is to be extracted; and a common electrode and a plurality of pixel electrodes disposed in an insulating state on a face of one of the substrates adjacent the liquid crystal layer. The transmission axis of the polarizing plate extends obliquely with respect to outer peripheral sides of a display screen. Each pixel electrode has a substantially quadrilateral outer shape having two major sides substantially parallel or perpendicular to the transmission axis of the polarizing plate. Each pixel electrode has plural electrode portions extending in parallel to the major sides of the outer shape of the pixel electrode in the outer shape.

1. Field of the Invention
This invention relates to a display apparatus, and particularly to a display apparatus wherein liquid crystal molecules are driven in an in-plane switching mode.
2. Description of the Related Art
A liquid crystal display apparatus of an in-plane switching mode attracts attention as a liquid crystal mode which implements a wide viewing angle and a high contrast. FIG. 13 illustrates operation of a liquid crystal display apparatus of a fringe field switching (FFS) mode which is one of in-plane switching modes. In FIG. 13, an optical axis is indicated by a double-sided arrow mark.
Referring to FIG. 13, the liquid crystal display apparatus of the FFS mode shown includes a common electrode 201 provided on a driving substrate not shown. Electrode portions 202a of a pixel electrode 202 are formed by patterning on the common electrode 201 with an insulating film interposed therebetween, and an orientation film 203 is provided in such a manner as to cover the pixel electrode 202. A liquid crystal layer 205 is sandwiched between the orientation film 203 on the driving substrate side and a face of an opposing substrate (not shown) on which an orientation film 204 is formed. Further, two polarizing plates 206 and 207 are disposed under crossed Nicols with the substrates sandwiched therebetween. Here, the rubbing direction of the two orientation films 203 and 204 coincides with the direction of one of transmission axes of the two polarizing plates 206 and 207. Further, the rubbing direction of the two orientation films 203 and 204 and the transmission axis of one of the polarizing plates 206 and 207 here, the polarizing plate 207 are set so as to be substantially in parallel to the extension direction of the electrode portions 202a of the pixel electrode within a range within which the direction in which liquid crystal molecules m rotates is defined.
In the liquid crystal display apparatus of the FFS mode, when no voltage is applied between the common electrode 201 and the electrode portions 202, the axis of liquid crystal molecules m which form the liquid crystal layer 205 is directed perpendicularly to the transmission axis of the polarizing plate 206 on the incidence side but parallelly to the transmission axis of the polarizing plate 207 on the emergence side. Thus, light incident from the polarizing plate 206 comes to the polarizing plate 207 on the emergence side without any phase difference provided thereto by the liquid crystal layer 205 and is absorbed by the polarizing plate 207 thereby to display the black. On the other hand, if a voltage is applied between the common electrode 201 and the pixel electrode 202, then the orientation direction of the liquid crystal molecules m is rotated to an oblique direction with respect to the extension direction of the pixel electrode 202 by an in-plane electric field generated between the common electrode 201 and the pixel electrode 202. Thereupon, the field strength upon white display is optimized so that the axis of the liquid crystal molecules m at a central location in the thicknesswise direction of the liquid crystal layer 205 may exhibit rotation by 45°. Consequently, when the light h incident from the polarizing plate 206 of the incidence side passes through the liquid crystal layer 205, it is converted into linearly polarized light rotated by 90° and passes through the polarizing plate 207 on the emergence side thereby to display the white.
In such a liquid crystal display apparatus of the FFS mode as described above, a plurality of scanning lines 213 and a plurality of signal lines 215 are wired in a matrix along outer peripheral sides of a rectangular display screen of a driving substrate 211, and a pixel electrode 202 is provided at each of intersecting locations of the scanning lines 213 and the signal lines 215. Each pixel electrode 202 is provided in a substantially rectangular outer shape within a pixel region a of a substantially rectangular shape defined by scanning lines 213 and signal lines. The pixel electrodes 202 are patterned in a comb-like shape such that they have a plurality of electrode portions 202a extending in parallel to the major sides of the outer shape as disclosed in Japanese Patent No. 3,742,837.
Another example of a configuration of a pixel electrode is shown in FIG. 15. Referring to FIG. 15, a pixel electrode 202 having a substantially rectangular outer shape is provided in a pixel region a of a substantially rectangular shape defined by scanning lines 213 and signal lines 215 wired along outer peripheral sides of a display screen. A plurality of electrode portions 202a extend obliquely with respect to the outer shape of the pixel region a. The configuration of the pixel electrode just described is disclosed, for example, in U.S. Pat. No. 7,145,621.
Both of the configurations described above with reference to FIGS. 14 and 15 have an optical configuration similar to that described hereinabove with reference to FIG. 13. In short, the rubbing direction of the two orientation films 203 and 204 and the direction of the transmission axis of one of the polarizing plates 206 and 207, in FIG. 13, of the polarizing plate 207, are set substantially in parallel to the pixel electrode 202, that is, the comb-shaped electrode portions 202a.