The present invention provides an image display capable of reducing power used up or consumed by a thin-film electron-emitter matrix. As a typical one, there is provided an image display which comprises a display device including a first plate which has a plurality of electron-emitter elements each having a structure comprised of a base electrode, an insulating layer and a top electrode stacked on one another in this order, the electron-emitter element emitting electrons from the surface of the top electrode when a voltage of positive polarity is applied to the top electrode; a plurality of first electrodes for respectively applying driving voltages to the base electrodes of the electron-emitter elements lying in a row direction, of the plurality of electron-emitter elements; and a plurality of second electrodes for respectively applying driving voltages to the top electrodes of the electron-emitter elements lying in a column direction, of the plurality of electron-emitter elements, a frame component, and a second plate having phosphors, wherein a space surrounded by the first plate, the frame component and the second plate is brought into vacuum. In the image display, the first electrode and/or the second electrode held in a non-selected state is set to a high-impedance state.

The present invention relates to an image display and a method of driving the same, and particularly to a technology effective for application to a display apparatus which has thin-film electron emitters having an electrode-insulator-electrode structure to emit electrons into vacuum.
The thin-film electron emitters are electron-emitter elements each using hot electrons produced by applying a high electric field to an insulator.
As a typical example, an MIM (Metal-Insulator-Metal) electron emitter comprising a three-layer thin-film structure of a top electrode-insulating layer-base electrode will be explained.
FIG. 13 is a diagram for describing the principle of operation of an MIM electron emitter illustrated as a typical example of a thin-film electron emitter.
A driving voltage is applied between a top electrode 11 and a base electrode 13 to set an electric field in a tunneling insulator 12 to 1 MV/cm to 10 MV/cm and over. Thus, electrons placed in the neighborhood of a Fermi level in the base electrode 13 are transmitted through a barrier by tunneling phenomena. Thereafter they are injected into a conduction band of the tunneling insulator 12 and further injected into the top electrode 11, thus resulting in hot electrons.
Some of these hot electrons are subjected to scattering under interaction with a solid in the tunneling insulator 12 and the top electrode 11, thus leading to the loss of energy.
As a result, hot electrons having various energies exist when they have reached an interface between the top electrode 11 and vacuum 10.
Of these hot electrons, ones having energy of a work function φ or more of the top electrode 11 are emitted into the vacuum 10, and ones other than the above ones flow into the top electrode 11.
Assuming that a current based on the electrons that flows from the base electrode 13 to the top electrode 11, is called a diode current (Id), and a current based on the electrons emitted into the vacuum 10 is called an emission current (Ie), an electron emission efficiency (Ie/Id) ranges from about 1/103 to about 1/105.
Incidentally, the MIM thin-film electron emitter has been described in, for example, Japanese Patent Application Laid-Open No. Hei 9-320456.
Now, the top electrode 11 and the base electrode 13 are provided in plural form and these plural top electrodes 11 and base electrodes 13 are made orthogonal to one another to thereby form thin-film electron emitters in matrix form. Consequently, electron beams can be produced from arbitrary locations and hence they can be used as electron emitters for a display apparatus.
Namely, a display apparatus can be constructed wherein thin-film electron-emitter elements are placed every pixels and electrons emitted therefrom are accelerated in vacuum and thereafter applied to each of phosphors to thereby allow the applied phosphor to emit light, whereby a desired image is displayed thereon.
The thin-film electron emitters have excellent features as electron-emitter elements for the display apparatus in that they are capable of implementing a high-resolution display apparatus because the emitted electron beams are excellent in directionality, and they are easy to handle because they are insusceptible to the influence of their surface contamination, for example.
Even except for the above-described MIM thin-film electron emitter, there are known, as thin-film electron emitters, a MIS (Metal-Insulator-Semiconductor) type (described in, for example, Journal of Vacuum Science and Technologies B, Vol. 11, pp. 429–432) using a semiconductor as a base electrode, one (described in, for example, Japanese Journal of Applied Physics, Vol. 36, Part 2, No. 7B, pp L939–L941 (1997)) using a semiconductor-insulator multi-layer film as a tunneling insulator, one (described in, for example, Japanese Journal of Applied Physics, Vol. 34, Part 2, No. 6A, pp. L705–L707 (1995)) using porous silicon as a tunneling insulator, etc.
A display apparatus using a thin-film electron-emitter matrix makes no use of a shadow mask like a cathode-ray tube (Cathode-ray tube; CRT) and has no beam deflection circuit. Therefore power consumption thereof is slightly lower than that of CRT or the same degree as that.
Power used up or consumed by the thin-film electron-emitter matrix is roughly calculated according to a conventional driving method for the display apparatus using the thin-film electron-emitter matrix.
FIG. 14 is a diagram showing a schematic configuration of a conventional thin-film electron-emitter matrix.
Thin-film electron-emitter elements 301 are respectively formed at points where row electrodes (base electrodes) 310 and column electrodes (top electrodes) 311 intersect respectively.
Incidentally, while the thin-film electron-emitter matrix is illustrated with 3 rows and 3 columns in FIG. 14, the thin-film electron-emitter elements 301 are actually placed by the number of pixels constituting a display apparatus, or the number of sub-pixels in the case of a color display apparatus.
Namely, as the number of rows N and the number of columns M, N ranges from several hundreds of rows to a few thousand rows and M ranges from several hundreds of columns to a few thousand columns as typical examples, respectively.
Incidentally, while one pixel is formed of a combination of respective sub-pixels of red, blue and green in the case of a color image display, ones equivalent to sub-pixels employed in the case of the color image display will be called "pixels" in the present specification. In the present specification, the pixels or sub-pixels are also called "dots".
FIG. 15 is a timing chart for describing the conventional method of driving the display apparatus.
A row electrode driving circuit 41 applies a negative polarity pulse (scan pulse) having amplitude (Vrow) to one of the row electrodes 310 (a selected scan electrode). Simultaneously column electrode driving circuits 42 apply positive polarity pulses (data pulses) each having amplitude (Vcol) to some (their corresponding selected column electrodes) of the column electrodes 311.
Since a voltage enough to emit electrons is applied to each thin-film electron-emitter element 301 in which the two pulses overlap each other, the electrons are emitted therefrom. The electrons excite each of phosphors to emit light therefrom.
In the case of the thin-film electron-emitter element 301 free of the application of the positive polarity pulse having the amplitude (Vcol) thereto, a sufficient voltage is not applied thereto and hence no electron emission is produced.
The row electrodes 310 to be selected, i.e., the row electrodes 310 to which the scan pulse is applied, are successively selected and the data pulses applied to the column electrodes 311 in association with rows for the selected row electrodes are also changed.
When all the rows are scanned in this way during one field period, an image corresponding to an arbitrary image can be displayed.
During a given period in one field, pulses of reverse polarity (reverse pulses) are respectively applied to all the row electrodes.
Thus, the thin-film electron-emitter elements 301 can be operated stably.
Dissipation power of each driving circuit is calculated according to the conventional driving method when the electrostatic capacitance per one of the thin-film electron-emitter elements 301 is represented as Ce, the number of the column electrodes 311 is represented as M and the number of the row electrodes 310 is represented as N.
The dissipation power is equivalent to power used up or consumed to charge the electrostatic capacitance of each driven element and discharge the same therefrom. The dissipation power does not contribute to light emission.
Dissipation power produced with the application of scan pulses will first be determined.
Dissipation power at the time that a pulse having amplitude (Vrow), is applied to the corresponding row electrode 310 once, is expressed in the following equation (1):M·Ce·(Vrow)2  (1)
Assuming that the number of refreshing images (field frequency) per second is given as f, the whole dissipation power (Prow) for N row electrodes is expressed in the following equation (2):Prow=f·N·M·Ce·(Vrow)2  (2)
Similarly, dissipation power (Pr) consumed with the application of reverse pulses is given by the following equation (3):Pr=f·N·M·Ce·(Vr)2  (3)
where Vr indicates the voltage amplitude of the reverse pulse applied to the row electrode 310.
Since N thin-film electron-emitter elements 301 are connected to one column electrode 311, the whole dissipation power (Pcol) for M column electrodes is given by the following equation (4) where pulse voltages are applied to all of the M column electrodes 311:Pcol=f·M·N·(N·Ce·(Vcol)2)  (4)
Since the pulses are applied to the column electrodes N times during a screen-refreshing period (one field period), Pcol is additionally multiplied by N as compared with Prow.
Incidentally, when pulse voltages are respectively applied to m of the M column electrodes 311, M in the equation (4) is substituted with m.
Using f=60 Hz, N=480, M=1920, Ce=0.1 nF, and Vrow=Vr=Vcol=4V as typical values, for example, results in Prow=Pr=0.09 [W] and Pcol=42[W].
Since, in this case, the power consumption of the thin-film electron-emitter element per se becomes about 1.6[W], the total power consumption results in about 44[W]. This is practically problem-free power consumption.
It is however understood that when it is desired to further achieve low power consumption, a reduction in dissipation power Pcol consumed with the application of the data pulse is effective.
Thus, even the prior art presents no problem in terms of power consumption when used as the display apparatus in a similar use as the CRT.
However, the feature of the display apparatus using the thin-film electron emitters is to enable the implementation of a thin flat-panel display.
This type of thin flat-panel display has a use as for a portable display apparatus. In this case, power consumption may preferably be further reduced.

Image display and method of driving image display


A biologically implantable prosthesis is disclosed. The prosthesis can have a circumferentially expandable wall and elements that prevent the wall from collapsing once the wall is expanded. Methods of making and using the prosthesis are also disclosed.

1. Field of the Invention
The present invention relates generally to a biologically implantable prosthesis, a heart valve assembly using the prosthesis, and methods of using the same within an annulus of the body.
2. Description of the Related Art
Prosthetic heart valves can replace defective human valves in patients. Prosthetic valves commonly include sewing rings or suture cuffs that are attached to and extend around the outer circumference of the prosthetic valve orifice.
In a typical prosthetic valve implantation procedure, the heart is incised and the defective valve is removed leaving a surrounding area of locally tougher tissue. Known heart valve replacement techniques include individually passing sutures through the tough tissue to form an array of sutures. Free ends of the sutures are extended out of the thoracic cavity and laid, spaced apart, on the patient's body. The free ends of the sutures are then individually threaded through an edge around the circumference of the sewing ring. Once all sutures have been run through the ring, all the sutures are pulled up taught and the prosthetic valve is slid or "parachuted" down into place adjacent the tough tissue. Thereafter, the prosthetic valve is secured in place by traditional knot tying with the sutures.
The sewing ring is often made of a biocompatible fabric through which a needle and suture can pass. The prosthetic valves are typically sutured to a biological mass or annulus that is left when the surgeon removes the existing valve from the patient's heart. The sutures are tied snugly, thereby securing the sewing ring to the annulus and, in turn, the prosthetic valve to the heart.
Sewing rings can be tedious to secure to the valve orifice. Further, attaching the sewing ring to the annulus can be time consuming and cumbersome. The complexity of suturing provides a greater opportunity for mistakes and requires a patient to be on cardiopulmonary bypass for a lengthy period. It is also desirable to provide as large of a lumen through the prosthetic valve as possible to improve hemodynamics. However, techniques for attaching the sewing ring to the orifice typically require the area of the valve lumen be reduced to accommodate an attachment mechanism. For example, the sewing ring is typically retained on top of the annulus, resulting in a lumen that is, at the largest, the size of the original lumen.
A patient can also have a natural valve lumen that is detrimentally small. In these cases, the natural valve can be gusseted before the prosthetic valve is implanted. To gusset the natural valve, a longitudinal incision can be made along the wall of the lumen. The lumen can then be circumferentially expanded and the now-expanded incision can be covered with a patch graft or other membrane and stitched closed.
U.S. Pat. No, 4,743,253 to Magladry discloses a suture ring with a continuous compression ring. Magladry's ring is ductile, but provides a compressive, not expansive, force. In fact, the ring taught by Magladry is intended for placement over a heart valve and provides compression on the heart valve.
U.S. Pat. No. 6,217,610 to Carpentier et al. discloses an expandable annuloplasty ring. Carpentier et al. teach expanding the ring over the life of a patient by increasing the size of the ring by balloon dilatation. The ring is intended to remodel the shape of the valve annulus, not serve as a foundation to attach a second prosthesis and form a heart valve.
U.S. Pat. No. 5,984,959 to Robertson et al. discloses an expandable heart valve ring for attaching a synthetic valve thereto and a tool for attaching the ring to the synthetic valve. Robertson et al. teach the ring as having tabs that are used to attach to the second prosthesis by using a second device to engage the tabs.
There is a need for a circumferentially expandable bio-prosthesis. There is also a need for a prosthesis and method that can expand an annulus and maintain an enlarged annulus circumference. Furthermore, there is a need for a minimally invasive heart valve replacement procedure. Also, there is a need for a prosthesis that can provide for the above and engagement with a second prosthesis, for example, the crown of a heart valve. Furthermore, there is a need for the above prosthesis that can self-engage a second prosthesis to improve implantation time.

This patent is subject to a terminal disclaimer.

Biologically implantable heart valve system


In a hybrid magnetic bearing, the electromagnet has a core wound with a control coil and has a main pole and a commutating pole with a commutating pole permanent magnet provided approximately parallel to each other at predetermined intervals in a protruding condition radially or axially to the rotor. In the magnetic bearing provided radially, two electromagnets are placed oppositely to each other across the rotor in an approximately horizontal position, and the rotor is arranged so as to have a predetermined gap with the main pole and the commutating pole, and the permanent magnet is provided between the adjacent electromagnets. In the magnetic bearing provided axially, two electromagnets are placed in parallel in an approximately horizontal position, and the rotor is arranged so as to have a predetermined gap with the main pole and the commutating pole, and the permanent magnet is provided between the adjacent electromagnets.

With the technological development in recent years of a magnetic bearing that suspends a rotor without contact, magnetic bearings are being used for various types of bearings. A magnetic bearing utilizes an electromagnet and requires a large amount of electrical current to levitate a rotor, resulting in a large power consumption. Therefore, in order to obtain a large amount of magnetic force with a small amount of current, the space between the rotor and stator is required to be narrow. Additionally, a high work accuracy is required. For those reasons, a hybrid magnetic bearing utilizing the bias flux of a permanent magnet is used.
One basic configuration of the hybrid magnetic bearing has a magnetized permanent magnet sandwiched in the axial direction between two radial magnetic bearings disposed at a distance from each other in the rotation axis direction of the rotor, and one of the radial bearings is made to be the positive pole. Another radial bearing is bias-magnetized to have the negative pole. By increasing the bias flux generated in the above manner in one of the radial directions and decreasing the bias flux in the other direction with a magnetizing coil, radial attraction is controlled.
A single radial magnetic bearing modified to be a hybrid type for the purpose of size reduction is also known. A magnetic bearing disclosed in Patent Document 1 has a first magnetic pole face that is one of the outer peripheral faces of a group of magnetic members in a ring-shaped rotor that consists of a permanent magnet magnetized in an axial direction sandwiched between the magnetic members from the axial direction. Another outer peripheral face of the magnetic members is the second magnetic pole face. The periphery of the rotor has a stator with four electromagnets, and each of the four electromagnets is mounted oppositely to the magnetic pole face of the rotor. It has been proposed to have passive magnetic support of the axial direction and to allow a tilting in the rotor by having such a configuration that connects the rotor and the stator by strong magnetic force.
Patent Document 2 proposes a magnetic bearing having a configuration of a magnetic bearing in which a rotor in the center has angulated U-shaped electromagnets arranged around its circumference at regular intervals, and the electromagnets are connected so that the magnetized directions are arranged alternately, said arranging being performed by a permanent magnet magnetized in the circumferential direction.
Patent Document 3 proposes a magnetic bearing having a configuration in which a permanent magnet magnetized in a radial direction is placed so as to cover the end of a stator having plural salient poles, providing a bias flux.
However, the magnetic bearings disclosed in Patent Documents 1 and 3 are of configurations in which a permanent magnet is arranged on a magnetic path where the flux of a control coil travels, and because the permanent magnet is a gap for the control flux, there is a limit to the amount that the control force can be increased by increasing the bias flux and increasing the thickness of the permanent magnet.
Although the magnetic bearing disclosed in Patent Document 2 can generate a strong control force if the control is in the X axis direction only or in the Y axis direction only, the simultaneous control of the X axis and Y axis causes a problem such that the strong control force cannot be generated because the control flux is being interfered with.
Because the magnetic bearing suspends a rotor without contact, the magnetic levitation is normally unstable and therefore needs to be stabilized by detection of the position of levitation and by feedback control. As a sensor detecting the position of levitation, an eddy-current sensor and an inductor sensor are used; however, these are generally expensive. In addition, if the magnetic bearing and the sensor have to be separately placed, the stability range of the feedback system will be small and there might be difficulty in stabilization. In particular, magnetic bearings for ultra-small rotors have been sought in recent years, and limitations in the sensor placement space are a problem in reducing the size.
There exists position detection of the magnetic bearing using a self-sensing technology that utilizes the electromagnet of the magnetic bearing as a sensor. When the position of a rotor changes, the magnetic pole inductance changes as the distance (gap) from the magnetic pole of the magnetic bearing to the rotor changes. By detecting the change in the inductance using any appropriate method, the gap can be estimated. The methods that have been attempted include a method of estimating displacement of a rotor on the basis of the electrical current or voltage of the high-frequency component by overlapping the magnetizing coil of an electromagnet with a high-frequency signal, and a method of establishing a mathematical model of the rotor/magnetic bearing system and generating an observation of the displacement estimation on the basis of the model. However, the magnetic bearing employing the self-sensing has a problem in that estimation accuracy of the position is lower than that of a method that employs a displacement sensor separately.
Patent Document 1:
    Japanese Patent Application Publication No. 2005-121157Patent Document 2:    Japanese Patent Application Publication No. 2001-41238Patent Document 3:    Japanese Patent Application Publication No. H11-101234


In an embodiment, a pluggable optical host and network I/O optoelectronic module (hereinafter “module”) includes a first optical-electrical-optical (OEO) converter and a second OEO converter. The first OEO converter is configured to convert N inbound optical signals to M inbound optical signals and includes N network-side optical receivers, first signal processing circuitry communicatively coupled to the N network-side optical receivers, and M host-side optical receivers communicatively coupled to the first signal processing circuitry. The second OEO converter is configured to convert M outbound optical signals to N outbound optical signals and includes M host-side optical receivers, second signal processing circuitry communicatively coupled to the M host-side optical receivers, and N network-side optical receivers communicatively coupled to the second signal processing circuitry.

Computing and networking technology have transformed our world. As the amount of information communicated over networks has increased, high-speed transmission has become ever more critical. Many high-speed transmission networks rely on optical communication devices for facilitating transmission over long distances through optical fiber links. Optical networks are thus found in a wide variety of high-speed applications ranging from data center Local Area Networks (LAN) to metro and long haul optical fiber links for Internet, voice and video communications.
Although data is transported in optical networks optically over optical fibers, the data is still processed mainly in the electrical domain at host cards by Application-Specific Integrated Circuits or Physical layer chips (ASIC/PHY chips). As such, the data may be transmitted through electrical traces with losses that increase dramatically with increasing bit rate and traces' lengths. One solution to this problem is to use an electro-optical (EO) conversion chip, also referred to as an EO chip, on the host card, between the ASIC/PHY chip and optical ports facing the optical links, but this solution typically limits the communication to specific link lengths and wavelengths.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one exemplary technology area where some embodiments described herein may be practiced.

Pluggable optical host and network I/O optoelectronic module


An illumination apparatus is provided that can achieve light distribution towards the front, and light illumination in a direction other than the front direction, without using a light source other than the light source for frontward illumination. The illumination apparatus includes a light emitting diode located at the front side of the illumination apparatus, corresponding to one end, a side transmission unit having a surface exposed at a gap in the casing, located rearward of the light emitting diode to transmit light from the side, and a light path modification unit, located rearward of the light emitting diode to modify the direction of light output from the light emitting diode towards the side transmission unit.

1. Field of the Invention
The present invention relates to illumination apparatuses, and more particularly, to an illumination apparatus employing LED (Light Emitting Diode).
2. Description of Related Art
The lighting apparatus attached to a bicycle must ensure favorable field of view in the frontward direction while suppressing excessive glare with respect to vehicles coming from the opposite direction. A conventional illumination apparatus is implemented as set forth below.
(a) The light emitted from the filament arranged in the proximity of the focal point of the parabolic mirror diverges in all directions. All the light other than the light emitted directly frontward is reflected at the parabolic mirror to form frontward parallel light rays. These light rays are set to form a predetermined light distribution by the front lens together with the light directly output frontward (for example, refer to Japanese Patent Laying-Open Nos. 2002-50212 and 2002-50213).
(b) The light emitted from the filament is set to form a desired light distribution by a multi-surface mirror to be output in the frontward direction. The front lens simply functions as a cover. In such a multi-surface mirror, the size and angle arrangement of respective portions are determined so that respective portions reflect the light from the filament to a predetermined direction and a desired light distribution can be achieved by the integration of respective portions (refer to Japanese Patent Laying-Open Nos. 2002-50212 and 2002-50213).
By using such illumination apparatuses, a desired light distribution can be achieved efficiently.
It is to be noted that if the illumination apparatus, whether employed for a bicycle or carried as a general illumination apparatus while walking, allows light to be emitted from the circumferential side region, for example, in addition to the forward direction, visual confirmation by a vehicle, particularly by an automobile, approaching from the lateral direction, i.e. from the side, is facilitated in the dark. Thus, the safety of the carrier of the illumination apparatus can be improved.
In the case where light is to be output from a region other than the frontward region, another light source, different from the light source for the frontward direction such as a side circumferential light source was conventionally employed. However, use of another light source is not preferable from the standpoint of reducing the size, weight and energy, as well as the fabrication cost.


A method of parallel processing in which there is first provided a first thread which represents an independent flow of control managed by a program structure, the first thread having two states, a first state processing work for the program structure and a second state undispatched awaiting work to process; and a second thread which represents an independent flow of control managed by a program structure separate from the first thread. The method includes using the second thread to prepare work for the first thread to process and placing the work prepared by the second thread in a queue for processing by the first thread. If the first thread is awaiting work to process when the work prepared by the second thread is placed in the queue, the method includes dispatching the first thread and using it to process the work in the queue. If the first thread is processing other work when the work prepared by the second thread is placed in the queue, the method includes using the first thread to complete processing of the other work, access the work in the queue, and then process the work in the queue.

1. Field of the Invention
The present invention relates to computer processing and, in particular, to parallel computer programming or processing.
2. Description of Related Art
In prior art computing using separate, non-parallel processing, the programs often share data and other services. An example of this is shown in FIG. 1 where separate process memories 19a, 19b, which may be physically separated in different memory storage, or logically separated in the same memory storage, contain global variable memory 20a, 20b for data items visible to the entire process, heap memory 21a, 21b for data structure, stack memory 23a, 23b for function arguments, and local data items, and free memory space 22a, 22b which may be utilized as needed for either heap or stack memory space. A portion of the free memory space may be designated as common memory 22c available to both program A, 24a, or program B, 24b, which operate in the separate process memories 19a, 19b, respectively. Each program A and B can access in the process memory only is what is designated in the common area 22c, but cannot access other memory between the programs. A programmer utilizing the system of FIG. 1 has relatively little assistance from the system in restricting access to data structures in common memory.
Parallel processing offers improvements in that a single program can run simultaneously different threads or independent flows of control managed by the program. Multiple threads may execute in a parallel manner, and the threads may share information in either a loosely or tightly coupled manner. An example of a parallel processing arrangement is shown in FIG. 2 where a single process memory 119 having a common global memory 120 and a common heap space 121 contains a plurality of stack spaces 123a, 123b, with a single program 124 operating a plurality of threads, with one stack per program thread. The process memory structure shown can operate any number of threads 1-N and contain any number of corresponding stacks 1-N, as shown.
Coordinated data access between threads usually requires operating system assistance (with associated penalties), such as semaphores or locks. However, in typical parallel processing applications, serialization caused by use of system services such as storage management, and coordination of access to memory often significantly reduces the attainable performance advantages of a parallel algorithm. Serialization occurs when more than one thread accesses or requests a data object or other system resource. If such a conflict occurs, only one thread has access and all other threads are denied access until the first thread is finished with the system resource. For example, the structure shown in FIG. 2 is error-prone because heap space, which contains information that is being manipulated by the program, is subject to collision as different threads attempt to access the same data structure at the same time. When this occurs, one or more threads have to wait while the data structure is accessed by another program thread.
In current practice, memory management in parallel software is also an area where complexity and inefficiency are major drawbacks. The benefits of parallel execution can be nullified, or even degraded to where sequential execution is faster, when calls are made to allocate or free memory. This is due to current serialization techniques, which must be employed to prevent collisions when two or more flows of control, i.e., threads, attempt to obtain or free memory areas. This can significantly degrade the performance of parallel programs, forcing unnatural exercises in program design and implementation. These contortions compromise maintainability, extensibility, and are a source of errors. Worse yet, the costs associated with these problems can deter developers from even considering otherwise viable parallel solutions.
In parallel programming, as described above, each thread is assigned a specific unit of work to perform, generally in parallel, and when the work is finished, the threads cease to exist. There is a cost to create a thread, terminate a thread, and to manage a thread. The cost has both machine-cycle components and programming complexity components. The programming complexity components are a source of errors in implementation and design of the software. The prevailing paradigm in the use of threads treats the threads and data differently. There is control flow (threads), and there is data. The resulting dichotomy creates an environment which tends to place fetters on the kinds of solutions envisioned, and creates complexity and resulting error-proneness during implementation.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a parallel processing structure which is less subject to error.
It is another object of the present invention to provide a parallel processing structure which is less subject to serialization limitations in accessing common system services such as data structures.
A further object of the invention is to provide a parallel processing structure which is less subject to serialization limitations in allocating or freeing memory.
It is another object of the present invention to provide a parallel processing structure in which there is less interaction between different threads.
It is another object of the present invention to provide a parallel processing structure which reduces cost and errors in creating, managing and terminating a thread.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.

Method of using a distinct flow of computational control as a reusable abstract data object

International Business Machines Corporation


A two layers half automatic foldable tent is comprised of a framework, an umbrella surface, and a tent cloth. The framework is enclosed on the outside of the tent, while the umbrella surface is expanded on the framework above the tent cloth, wherein the framework is presented as an expanding structure. The opening and closing of the umbrella frame is completed by a controlling rope. Any user may easily install the tent, the lower primary frame of the umbrella frame may be folded upwards as the framework is closed, thus it may be stored conveniently and may be carried. Another, since in the present invention, the umbrella surface and tent cloth are designed as the two layers type thus the sunlight, rain water and snow will not contact the tent directly, and the people within the tent will be safe and comfortable and the lifetime of a tent is prolonged.

1. Field of the Invention
The present invention relates to an umbrella type two layers foldable tent, especially to a foldable tent which is easy to operate and carry, may be installed quickly, has a compact volume after being folded, and is safe, comfortable and endurable in usage.
2. Description of the Prior Art
In the prior tent, the exemplary tent is formed by a multi-nodes framework to match with connectors, wherein the framework is assembled one node by one node, and finally the tent cloth is covered. The primary defect of this tent is the complicated structure so that the assembled time is too long and too wasted, not easy to assemble and dangerous. This kind of tents are generally sold in the market.
Further, there are also some brand new tent product, such as U.S. patent application Ser. No. 5,479,954, which is appended by the inventor of the present invention, in which the original complicated assembling operation of the tent is simplified. However, in that patent application, the framework structure is slightly complicated, and for the living quality, such as the sunlight, wind and snow are not completely considered, thus there are still some points being necessary to be improved. Moreover, in U.S. patent application Ser. No. 2,864,389, a structure is disclosed in that the operating process is similar to that in aforementioned Patent Application of the inventor of the present invention, thus there still are some drawbacks about the comfort and safety. However, since the framework in that Patent Application is covered within the tent, it is not easy to be folded. Furthermore, the framework will probably penetrate through the tent cloth so that the tent will probably be destroyed. Another, U.S. patent application Ser. Nos. 420,690, 1,680,090, 3,874,397, 4,033,366, 5,117,851, 5,216,948, in which the operation has no practically improved, it is needless to say about the comfort and safety.

No. 10 Cui-Ping Lane, Zhen-Nan St., Ching-Shui Town


A two wheeled throwable robot comprises an elongate chassis with two ends, a motor at each end, drive wheels connected to the motors, and a tail extending from the elongate chassis. The throwable robot includes an enable/disable arrangement comprising a pair of magnets generating a magnetic field and a magnetic field sensor positioned in proximity to the pair of magnets. The sensor is activated upon the occurrence of a specific modification of the magnetic field. The throwable robot may include a key member formed of a material to modify the magnetic field to enable the robot.

Throwable robots used in military and policing operations need to be robust and able to survive exposure to rugged conditions including water and vertical drops. Robots used in hostile military and policing operations require robust, reliable, and secure control systems, including enable-disable switches. Improvements in reliability and performance for robots used in high stakes military and police operations are desirable.


A singulation metal mold for singulating a plurality of semiconductor devices arrayed on a TAB tape has a punch as an upper metal mold of the singulation metal mold, a die block as a lower metal mold of the singulation metal mold, a knockout disposed to be slidable vertically inside a vertical hole formed in the die block, the knockout being operable to press up above the die block each of the singulated semiconductor devices left on the die block after the singulating, a press-up plate positioned under the knockout to support the knockout and linked mechanically to the knockout, and being operable to forcibly move the knockout vertically when the press-up plate moves vertically; and a press-up plate descent forcing mechanism that is operable to forcibly pull down the press-up plate.

1. Field of the Invention
The invention relates to a singulation metal mold used for producing a semiconductor device packaged in a package such as BGA (Ball Grid Array) which is thin and compact and has outer dimensions close to that of a semiconductor chip, and a method for producing the semiconductor device including a singulation step by using the singulation metal mold. Herein "singulation" means dividing or cutting a base film or tape on which plural semiconductor chips are mounted into pieces on each of which the single semiconductor chip is mounted.
2. Description of the Related Art
Heretofore, a TAB (Tape Automated Bonding) system is used to produce such type of a semiconductor device for improving the productivity.
FIG. 4 shows an example of a semiconductor device having a mounting structure in BGA or CSP (Chip Size Package) system. The semiconductor device 100 is constructed such that a wiring 102 is formed on the surface of an insulating substrate 101 with an opening 120 where a circuit board 103 is composed of the 101 and 102, and a semiconductor chip 105 is mounted on the circuit board 103 through an elastic material 104. Furthermore, the whole circumference of the semiconductor chip 105 and the opening 120 as a space housing an electrode pad 108 is sealed with a sealing resin 106 by transfer molding.
In detail, the wiring board 103 is arranged such that apertures 121 for attaching solder balls 107 for external connection are defined on the lengthy insulating substrate 101 called also a carrier tape, and the wiring 102 is formed by photo-etching a copper foil which is previously laminated on a surface for mounting the semiconductor chip 105. The solder balls 107 are attached to the back surface opposite to the surface for mounting the semiconductor chip 105.
The semiconductor chip 105 is mounted on the circuit board 103 through the elastic material 104, and the electrode pad 108 disposed on the bottom of the semiconductor chip 105 is connected to the wiring 102, whereby the electrical connection is made therebetween.
The plural semiconductor devices 100 arrayed and formed on the single continuous and lengthy carrier tape according to the TAB system as described above need to be finally separated into single chip-mounted packages. Namely, it is necessary to conduct a singulation step for singulating the semiconductor devices 100 on the carrier tape (insulating substrate 101).
FIGS. 5A to 5C are cross sectional views showing steps for singulating semiconductor devices as described above and the singulation metal mold used therefor.
In the singulating steps, at first, as shown in FIG. 5A, a TAB tape 111 with the semiconductor devices 100 sealed but not separated into the respective pieces is mounted on a singulation metal mold 110.
Then, as shown in FIG. 5B, punches 112 as a upper metal mold of the singulation metal mold 110 descend to sandwich the semiconductor devices 100, which are arrayed and formed at predetermined regions on the TAB tape, between the punches 112 and a die block 113, and, while engaging the punches 112 with the die block 113 as a lower metal mold, a predetermined pressure is applied thereon by press work. Thus, the insulating substrate 101, the elastic material 104, the sealing resin 106 and, optionally, a plating electric current supplying extension line (not shown) for the wiring 102 are punched simultaneously. As a result of the punching, the respective semiconductor devices 100 are separated one another as so-called individual piece.
Here, the respective semiconductor devices 100 are left on a knockout 114 inside the die block 113. Then, the knockout 114 located on a knockout press-up plate 115 is pressed up by elevating the knockout press-up plate 115 as shown in FIG. 5C, so that the semiconductor devices 100 left on the surface of the knockout 114 are disposed higher than the upper surface of the die block 113. In this state, a suction collet 116 is brought close to the semiconductor device 100 from above, and the semiconductor 100 is picked up by applying suction force by air pressure (negative pressure).
When the pick-up work is completed, the knockout press-up plate 115 is moved down by an actuator (not shown) such as an air cylinder disposed outside the singulation metal mold 110. Thus, since nothing supports the knockout 14, the knockout 114 freely falls with its own weight to return to a regular low position. Alternatively, as a power source for pressing up the knockout 114, spring force is proposed instead of the air cylinder (See JP-A-H01-183830).
However, irrespective of which types of the power source is used to press up the knockout 114, a very thin and fine chip of the sealing resin etc. may be produced unavoidably during the singulation, where the chip can penetrate the clearance between the knockout 114 and the die block 113 to clog it.
In the chip-clogged state, the smooth vertical movement of the knockout 114 in the die block 113 is highly disturbed. Thus, as shown in FIG. 6A, the knockouts 114b and 114c being normally movable in the vertical direction freely falls down to a normal low position, and only the knockout 114a which cannot be smoothly moved due to the clogging with the chip 117 is left at an upper position.
When the singulation is conducted under the above conditions, as shown in FIG. 6B and FIG. 7 which is an enlarged cross sectional view of FIG. 6B, while the semiconductor device 100 is clamped between the punch 112 and the knockout 114a, an excessive pressure will be applied to the semiconductor device 100. When the excessive pressure is applied thereto, the serious defect in the semiconductor device 100 as a target product is more likely to occur. Namely, cracks may be caused on the outer shell (the sealing resin 106 and the like) of a mounting package of the semiconductor device 100, or the breakage or serious damage of the semiconductor chip 105 may be caused inside the sealing resin 106.
Under the circumstances, it may be considered that such a minute dimension that the chip 117 cannot absolutely intrude into a clearance between the knockout 114 and the die block 113 is adopted in order to avoid the clogging with the chip 117. In fact, however, it is required that the clearance between the knockout 114 and the die block 113 is at least 0.5 mm, or more in order to assure the smooth vertical movements of the knockout 114. Consequently, it is extremely difficult or impossible to avoid the incidence of clogging with the thin chip 117 of 0.5 mm or less, and further it makes more difficult to overcome the problem of the incidence of serious defects in the semiconductor device 100 in the singulating step.
As mentioned above, in the conventional singulation metal mold and the conventional method for producing the semiconductor device using the singulation metal mold by the conventional TAB system, there is the problem that the breakage, damage or the like of the semiconductor device may be caused by a failure in the free fall of the knockout inside the metal mold during the singulation. It is very difficult to solve the above problem.

Singulation metal mold and method for producing semiconductor device


Systems and methods for detecting component rotation within a communication assembly are provided. In certain embodiments, a system includes a module; an adapter block that includes multiple front ports and multiple rear ports configured to receive an optical connector; a managing entity configured to control port identification for the front and rear ports; and a circuit board mounted to the adapter block, wherein the circuit board comprises multiple front contact assemblies and multiple rear contact assemblies, wherein each front port is associated with a front contact assembly and each rear port is associated with a rear contact assembly, wherein when a rear contact assembly is electrically coupled to a connector, the connector generates an event that is sent to the managing entity, whereupon the managing entity remaps the port identification for the front and rear ports.

Telecommunications networks typically include numerous logical communication links between various items of equipment. Often a single logical communication link is implemented using several pieces of physical communication media. For example, a logical communication link between a computer and an inter-networking device such as a hub or router can be implemented as follows. A first cable connects the computer to a jack mounted in a wall. A second cable connects the wall-mounted jack to a port of a patch panel, and a third cable connects the inter-networking device to another port of a patch panel. A "patch cord or cable" cross connects the two together. In other words, a single logical communication link is often implemented using several segments of physical communication media.
Various types of physical layer management (PLM) systems can be used to track connections made at patch panels and other types of equipment used to make connections in communication networks. Generally, such PLM systems include functionality to track what is connected to each port of such equipment, trace connections that are made using such equipment, and provide visual indications to technicians at such equipment (for example, by illuminating an LED that is associated with a patch panel or a port thereof).
One exemplary type of PLM system makes use of an Electrically Erasable Programmable Read-Only Memory (EEPROM) or other storage device that is integrated with or attached to a connector on a cable, fiber, or other segment of communication media. The storage device is used to store information about the connector or cable along with other information. The port (or other connector) into which the associated connector is inserted is configured to read the information stored in the EEPROM or other storage device when the connector is inserted at that port. One example of such technology includes the QUAREO family of products that are commercially available from TE Connectivity.
Another type of PLM system makes use of so-called "ninth wire" technology. Ninth wire technology makes use of special cables that include an extra conductor or signal path (also referred to here as the "ninth wire" conductor or signal path) that is used for determining which port each end of the cables is inserted into. Ninth wire technology can be used with various types of cables, such as, twisted-pair copper cables and optical cables (in the latter case using hybrid optical cables that include one or more copper wires that serve as the ninth wire). One example of ninth wire technology includes the AMPTRAC family of products that are commercially available from TE Connectivity.
Another type of PLM system makes use of radio frequency identification (RFID) tags and readers. With this type of RFID PLM system, an RFID tag is attached to or integrated with a connector on a cable, fiber, or other segment of communication media. The RFID tag is used to store information about the connector or segment of communication media along with other information. The RFID tag can be read after the associated connector is inserted into a corresponding jack or other port using an RFID reader.
PLM systems typically include management software that aggregates the captured information and stores it in one or more databases. One example of such management software is the Infrastructure Configuration Manager (ICM) software that is commercially available from TE Connectivity.
In addition to information about the connections and cabling used to make them, these databases also typically store information about the other equipment used to make the connections. Examples of such equipment include patch panels, distribution frames, and active networking devices such as switches, routers, and gateways. Examples of information that is stored in the database about such equipment include information about the make and model of the equipment and where it is installed in the network.
Typically, information about where such equipment is installed in the network must be manually entered. This is commonly the case even for "intelligent" equipment that can be automatically discovered by the PLM management software and queried for its identification information (for example, serial number and make and model).
For example, in one common usage scenario, a frame is installed in an equipment room or data center of an enterprise or in a central office of a telecommunication service provider. The frame is designed to house multiple sub-assemblies that are used to make connections between cables. One example of such a frame is an optical distribution frame (ODF) into which multiple chassis can be inserted. In this example, each chassis is designed to hold multiple adapter packs on one or more trays that slide in and out of the chassis. Each adapter pack comprises multiple optical adapters, where each of the optical adapters is configured to optically connect an optical cable terminated with an optical connector (such as an LC or SC connector) with another optical cable terminated with a corresponding optical connector.
Each optical adapter in each adapter pack can be designated as a port in the adapter pack. When an adapter pack is installed in a chassis, there is a chance that the adapter pack may be installed in a reversed position because, in certain applications, one side of an adapter pack that connects to optical connectors may be indistinguishable from an opposite side that likewise connects to optical connectors. When an adapter pack is in a reversed position, the management software may incorrectly identify the different ports in the adapter pack.
As noted above, even when the frame includes some type of PLM intelligence that enables the frame to be discovered by PLM management software and queried for identification information associated with that frame (for example, a serial or other identification number and a make and model), location information for that frame typically must be manually entered into the PLM management system (for example, using a Web interface or mobile application). This is because the frame is typically not aware of where it is located. The PLM management system is then able to associate the manually entered location information with the identification information that the PLM management software was able to automatically discover.
Also, whenever a sub-assembly (for example, an optical chassis of the type noted above) is installed in the frame, location information for that sub-assembly must also be manually entered into the PLM management system. The location information for each sub-assembly includes where that sub-assembly is located (for example, a physical location and/or which frame the sub-assembly has been inserted into) as well as which slot or position within the frame into which the sub-assembly has been inserted.
The location information for each such sub-assembly typically must be manually entered even if the sub-assembly otherwise includes PLM intelligence that enables the sub-assembly to be discovered and queried by the PLM management software for its identification information. This is because the sub-assembly typically is not aware of where it is located. The need to manually enter location information for the sub-assembly adds an additional manual step to the work-flow associated with installing the sub-assembly, which increases the time required to complete the work flow and which can result in incorrect data being manually entered. Moreover, it is common that when a frame is initially deployed, less than the maximum number of sub-assemblies that could be housed in that frame are actually installed in the frame during the initial deployment. As a result, location information for the various sub-assemblies in a given frame might be manually entered by different people at different times.
In accordance with common practice, the various described features are not drawn to scale but are drawn to emphasize specific features relevant to the exemplary embodiments.


A general-purpose electronic device, a method of controlling the same, and an information processing system are provided. This electronic device has a function of automatically installing its driver in the information processing system. The driver is stored in the electronic device. The electronic device includes a first device and a second device in which the driver of the first device is stored. The first and second devices generate transactions on a common interface for external connection. The operation of the second device is started before the operation of the first device, and a means is employed to make the driver readable from the second device through the common interface.

1. Field of the Invention
The present invention generally relates to an electronic device that has a driver stored therein and a method of controlling the electronic device, and more particularly, to a technique of installing the driver of the electronic device in an information processing apparatus to which the electronic device is to be connected as a peripheral device.
2. Description of the Related Art
There is a type of information processing system that includes an information processing apparatus and an electronic device connected to the information processing apparatus. The electronic device serves as a peripheral device for the information processing apparatus, and is controlled by the operating system (OS) of the information processing apparatus. The OS requires dedicated software to control the peripheral device. This software is referred to as a device driver or simply as a driver. The device driver is installed in the information processing apparatus, so that the peripheral device can exhibit its performance on the information processing apparatus.
FIG. 1 is a block diagram of a conventional information processing process. A peripheral device 20 having an USB (Universal Serial Bus) interface is connected to an information processing system 10 with a USB. The information processing system 10 will be hereinafter referred to simply as the "PC 10", and the peripheral device 20 as the "USB device 20". The USB device 20 shown in FIG. 1 is a keyboard. The PC 10 includes a USB host controller 14 and a storage device 15. The storage device 15 is a flexible magnetic disk (FD) or a CD-ROM, for example. A keyboard driver 12 and a storage device driver 13 are installed in the OS 11 of the PC 10, and are connected to the USB host controller 14 and the storage device 15 via internal buses 16 and 17, respectively. The USB device 20 includes a keyboard device 21 so as to function as a keyboard. The keyboard device 21 is connected to the USB host controller 14 via a USB cable 18. The OS 11 may be the Windows (a trademark), which is produced by Microsoft Corporation.
As the USB device 20 is connected to the PC 10 with the USB cable 18, the USB host controller 14 detects the connection of new software. To install a driver of the USB device 20, the USB host controller 14 requests for a FD or CD-ROM storing a driver to be mounted to the driver of the storage device 15. The driver (the keyboard driver 12 in this case) of the USB device 20 is read from the mounted FD, and is installed in the OS 11. In this manner, the software to control the peripheral device is installed by a recording medium and a device different from the peripheral device.
In a notebook-type personal computer or a PDA (Personal Digital Assistant), an FD drive and a CD-ROM drive are not mounted on the PC 10. Therefore, to install the keyboard driver 12 by the above method, an external device such as a USB external storage device 22 shown in FIG. 2 needs to be employed so as to connect the keyboard driver 12 to the USB host controller 14 of the PC 10 with a USB 19.
To solve this problem, Japanese Unexamined Patent Publication No. 2000-322241 discloses a structure in which the peripheral device holds software. This publication teaches that a driver is read from a storage device in a peripheral device and is automatically installed in the OS.
However, the art disclosed in this publication is based on the assumption that the storage device mounted on the peripheral unit can be always read and written, with the peripheral device being connected to a host device. Therefore, according to the art disclosed in the above publication, read and write cannot be performed when the storage device mounted on the peripheral device is disabled.
Taking as an example a case where a USB is employed as an interface with a peripheral device in the "Windows" (a trademark of Microsoft Corporation), which has the largest marketing share as the OS operating on PCs, the above-described problem of the prior art will be described below with reference to FIG. 3.
A peripheral device 23 shown in FIG. 3 is a USB device that includes a keyboard device 24 and a USB external storage device 25. The USB external storage device 25 has a keyboard driver stored therein. Before the USB external storage device 25 is connected, the keyboard driver 12 has not been installed in the OS 11. As soon as the USB device 23 is connected to the PC 10 for the first time, the USB host controller 14 automatically recognizes that the keyboard device 24 has been connected to the USB external storage device 25 via the USB host controller 14. This is because the keyboard device 24 and the USB external storage device 25 can generate transactions (operations to be performed by the PC) on a common USB interface. Since the keyboard driver has not been installed in this case, the USB host controller 14 requests for the input of the location of the file in which the driver of the keyboard device 24 is stored. Even if the OS 11 has the driver of the USB external storage device 25, it is impossible for the USB structure to read the keyboard driver from the USB external storage device 25, with an unknown keyboard driver existing, i.e., with the USB device 23 having not been recognized. Accordingly, the USB device 23 mounted on the USB external storage device 25 cannot be put into practical use.
In this case, the OS 11 requests the operator to input the location of the file in which the keyboard driver is stored. As the USB device 23 has not been recognized at this point, the USB external storage device 25 cannot be of course designated. The operator therefore needs to prepare a separate recording medium in which the keyboard driver is stored. Receiving this request, the operator inputs the location of a suitable recording medium or a file in which a suitable driver is stored, so that the installation of the keyboard driver can be resumed.
As described above, the USB external storage device 25 mounted on the USB device 23 cannot be used unless the use of the USB device 23 is allowed. Accordingly, the keyboard driver cannot be read from the USB external storage device 25 and then installed.
This problem can be seen not only with USB interfaces, but also with other type of interfaces.
Japanese Unexamined Patent Publication No. 2000-194645 discloses a technique of facilitating installation and rewrite of a driver of a peripheral device with a USB. This publication teaches that a ROM having a plurality of device drivers stored therein is installed in the USB device. When the USB device is connected to a PC, the corresponding control data is read from the ROM under the control of a USB host device, so that the USB device is set to the first configuration. The first configuration defines the state in which data can be transferred from the USB device to the host device. In this defined state, a device driver is read from the ROM, and is then transferred to the USB host device. The transferred device driver is stored in the memory of the host device. The USB host device then sends a request for another configuration to the USB device. Receiving this request, the USB device is set to the second configuration from the first configuration. Thus, the use of the function of the USB device can be allowed.
However, this method requires a special step of issuing an instruction from the USB host device to the USB device so as to switch configurations. For this reason, this method cannot be applied to a conventional PC having a USB host device installed therein as it is.

Hub controller with connected first and second device wherein second device contains drivers and first device in disable state before driver read from second device


Methods for reducing chronic pain caused by a disrupted spinal disc are described. In one method, a physiologically acceptable amount of an injectable is injected into the disc. The injectable is obtained from a stock solution comprising chondroitin sulphate, glucosamine HCl, aqueous solution of dextrose; sodium carboxymethylcellulose, and a buffer substance in quantity to bring the pH of the stock solution to a value above about 6.0. Water is also added to dilute the stock solution. The stock solution may further comprise an anesthetic such as bupivicaine.

The human skeleton has evolved to allow for upright posture and bipedal motion. The human spine in its development to support the upright body has developed areas of stress particularly at the base of the neck, the apex of the mid back (thoracic spine) and in the lower back (lower lumbar spine). The spine is formed by bony elements, the vertebrae, and cushions between vertebrae, the intervertebral discs. The spine is then supported by ligaments, fibrous bands of tissue that join bones together, and muscles and fascia, which provide dynamic support and zygapophyseal joints, two at each level posteriorly which join the vertebrae together. Anteriorly the intervertebral disc serves as a cushion between the vertebrae but also helps join the vertebrae together and provides stability.
When neck or back pain becomes chronic, usually due to injury or repetitive stress, and the pain becomes severe and limiting or disabling the intervertebral disc(s) is/are the source of pain.
The most common cause of disability below the age of forty-five is chronic low back pain. Chronic low back pain is due to intervertebral disc disease in forty percent of patients, zygapophyseal joint dysfunction is fifteen to thirty percent of patients, sacra-iliac joint complex dysfunction in fifteen percent of patients, and in the remaining fifteen percent, multiple causes.
When an intervertebral disc becomes injured, the natural reparative process is often hindered due to limited blood supply to the inner portion of the intervertebral disc. Normally blood vessels are found only in the outer third of the peripheral portion of the disc, the annulus. However nutrition to the central portion of the disc depends upon perfusion of nutrients through the vertebral end-plate which separates the disc from the body of the vertebra above and below.
When nutrition becomes impaired the disc tissue becomes acidic and a degenerative process usually ensues. If the normal reparative process is inadequate, the disc can continue to degenerate and be the source of pain. The degenerative process varies in extent in every intervertebral disc that is chronically painful. A chemical reaction occurs within the disc usually at the site of injury. The chemicals cause further breakdown of the disc and when the chemicals escape into the spinal canal inflammation occurs and affects the spinal nerves causing further pain. In older patients (35 years plus) where degeneration is present the pain is not only due to a chemical reaction within the disc but instability of the disc secondary to previous degeneration.
Low back pain is reaching epidemic proportions in the Western world. Traditionally the treatment for severe discogenic pain has been surgical removal of the injured intervertebral disc and fusion of the spine surgically by replacing the disc with bone graft or various metal implants containing bone graft. This procedure is very expensive. Costs can range up to one hundred thousand dollars. It requires from six months to one year to recover. Up to eighty percent of the fusions become solid. However pain improvement is problematical. At best fifty to sixty percent of patients experience pain reduction, not always completely. Up to fifty percent remain with the same degree of pain or worse. The latter group often becomes permanently disabled and dependent upon opioid medications.
Upon evaluation of back pain many factors must be considered: age, severity of pain, radiation of pain into buttock or legs, and the presence of leg numbness or weakness. Commonly most patients who suffer an initial injury can recover fully if they rest appropriately, and inflammation within or about the disc is addressed. Thereafter a conditioning program becomes important in order to strengthen the muscles for supporting the trunk and providing controlled movement. When there is recurrence of low back pain after injury or stress the condition usually becomes more serious.
When an intervertebral disc can be identified as a source of pain usually by combination of a MRI scan of the lumbar spine as well as lumbar discography, the latter is a provocative test for discogenic pain by placing a needle into the center of the disc and injection of radiographic contrast under pressure. In a normal disc there is no pain provoked. In an abnormal disc pain is provoked, and if it causes the pain that is experienced by the patient, then the disc is concordantly painful.
At the same time fissures to the outer portion of the disc, the annulus, or multiple tears radiating from the center of the disc, the nucleus, to the periphery of the disc through the annulus are visualized. If the intervertebral disc has normal height, and there is a single fissure, and there is severe pain on low pressure by discogram, then a highly chemically sensitive disc is present. This condition is called an internal disc disruption. If multiple tears are identified, the disc has become narrowed by degeneration, and the pain is less severe but still significant, the condition is often called symptomatic degenerative disc disease.
The traditional treatment to the present time for severe painful discogenic disease has been spinal fusion. Successful results are modest. Therefore it is essential to find simpler and better ways to treat painful intervertebral discs. Several devices have been developed in recent years. At present there are two devices that are used relatively commonly, the first is the IDET (intra-discal electrothermal therapy) and the other is the nucleoplasty.
These two devices have limited use. They can only be used on intervertebral discs that have nearly normal height, have a single fissure and are chemically sensitive. The nucleoplasty is also used when there is posterior bulging of the disc for it will remove or ease the central pressures within the disc and therefore the pressure upon the periphery of the disc is reduced. Their success is partial. No alternative treatment for internal disc disruption or symptomatic degenerative disc disease has been developed until the chemical disc injection treatment (disc restorative solution) of this invention.

Method and pharmaceutical to treat spinal discs


Energy storing starter assembles include a hub, a pulley, and a torsion spring adapted to resiliently link the hub to the pulley. The torsion spring includes a first end portion adapted to be linked to the hub and a second end portion adapted to be linked to the pulley. The torsion spring further includes at least one resilient member with a first section including a first winding and a second section including a second winding.

Conventionally, a recoil starter is used with a manually started internal combustion engine, such as a small two-stroke engine, for example. A pulley is provided with a rope wound thereon. During a starting procedure, a handle attached to the distal end of the rope is pulled such that a ratchet and/or clutch mechanism couples the pulley to the flywheel and crankshaft. Continued pulling of the handle allows transmission of rotational energy to a flywheel and crankshaft to facilitate reciprocation of the piston within the piston cylinder. Rotation of the crankshaft drives a piston and helps provide fuel for ignition. Rotation of the flywheel causes a magneto to power a spark plug, creating a spark for ignition of the engine fuel.
In operating such a starter mechanism, abrupt changes in the engine torque may occur due to piston compression of an air/fuel mixture in the piston cylinder. Such abrupt changes can contribute to uneven, jarring, and/or kickback forces when pulling the handle during the starting procedure. These forces can inhibit engine ignition, generate damaging stresses within certain engine components, and the like.
To reduce these fluctuations in pulling force, conventional starter mechanisms are known to include a second rotating member coupled to the pulley by way of a spring. The second rotating member engages with the engine crankshaft, typically using a ratchet mechanism, for transmission of rotational energy. Rotational energy stored within the spring can be used to assist in transmitting a rotational force to the engine crankshaft during periods of higher required torque. Storing rotational energy within the spring can beneficially dampen the pulling force required by the operator and smooth the starting operation. Such a system can be referred to as a buffered recoil system.
Despite this modification, drawbacks in the typical buffered recoil starter systems remain. There is a need to provide a starter device that utilizes a spring to enable starting the engine with a reduced pulling force, while at the same time reducing the inevitable stresses on components of the spring to provide greater durability and reliability.


An electrostatic discharge (ESD) protective circuit for reducing the electron-tunneling phenomena in NMOS devices. Several complementary metal oxide semiconductor (CMOS) devices act as an ESD protective circuit from being destroyed. The CMOS devices are connected to an internal circuit and a power line provide a bias voltage for the devices. The drains of the CMOS devices are connected to a pad to output a driving current. A NMOS device is connected between the internal circuit and the ESD protective circuit for protecting the NMOS devices in the circuit. As an ESD pulse is input into the ESD protective circuit, the NMOS device is then turned on by the pulse. Thus, positive charges on the gate of the NMOS devices in the ESD circuit is conducted into ground. Therefore, the NMOS device between the internal circuit and the ESD circuit can prevent the gate oxide of the NMOS device in the circuit from damage.

With the advent of the technology to fabricate integrated circuits, it becomes a trend to scale down the geometry size of semiconductor devices and increases the density of semiconductor devices per unit area of a silicon wafer. Electrostatic discharge (ESD) protection is an important issue for the design of integrated circuits. Electrostatic discharge is also a significant problem of the fabrication of integrated circuits. Such as, human or machine handling of the semiconductor wafer or chip during the assembly or processing of a wafer could produce electrostatic charges in integrated circuits. These electrostatic charges will cause destructive electrostatic pulse to destroy devices in integrated circuits.
As the development in the formation of sub-micron semiconductor technologies has been quite modest in comparison, the thickness of the gate oxide and the length of the device's channel have become thinner or shorter than ever. The failure susceptibility of integrated circuits to ESD protection increases due to the IC fabrication towards sub-micron feature lengths.
Typically, input/output signals to a metal oxide semiconductor (MOS) are input into or output from input/output pads. The input/output pads are generally connected to the gates of MOS devices. All pins for input/output of MOS IC must be protected by ESD protective circuits to prevent harmful static discharge voltages from damaging the IC.
Referring to FIG. 1, it is demonstrated an electrostatic discharge (ESD) circuit of integrated circuits. The ESD circuit is consisted of several first pairs that each of the first pairs further comprises a used NMOS device and a used PMOS device, and several second pairs, that each of the second pairs further comprises a unused NMOS device and a unused PMOS device. The ESD circuit is connected between an internal circuit 2000 and a pad 1000.
Referring to FIG. 1 again, a used PMOS device P1 and a used NMOS device N1 are connected together for discharging. Besides, a used PMOS device P2 and a used NMOS device N2 are coupled together for discharging. In detail, the gates of the PMOS P1, the NMOS N1, the PMOS P2 and the NMOS N2 are coupled together and with the internal circuit 2000. The sources of the PMOS P1 and the PMOS P2 are coupled with a power line V.sub.cc. The sources of the NMOS N1 and the NMOS N2 are coupled with ground. In addition, the drains of the PMOS P1, the PMOS P2, the NMOS N1 and the NMOS N2 are coupled together and these drains are coupled with the pad 1000.
Referring to FIG. 1 again, a unused PMOS device P3, a unused NMOS device N3, a unused PMOS device P4 and a unused NMOS device N4 are coupled together and these devices are functionless during the discharging of the internal circuit 2000. The drains of the PMOS device P3, the PMOS device P4, the NMOS device N3 and the NMOS device N4 are coupled together with the pad 1000. Besides, the sources of the PMOS device P3 and the PMOS device P4 are coupled with the power line V.sub.cc, and the source of the NMOS device N3 and the NMOS device N4 are coupled with ground. The gates of the PMOS device P3 and the PMOS device P4 are coupled with the power line V.sub.cc through a resistor RP3 and RP4, respectively. Besides, the gates of the NMOS device N3 and the NMOS device N4 are coupled with ground through a resistor RN3 and RN4, respectively.
Referring to FIG. 1, the power line V.sub.cc provides a voltage bias for the PMOS devices P1, P2, P3 and P4. Static charges are conducted from the internal circuit 2000 to ground through the NMOS devices N1 and N2.
Referring to FIG. 2, it is demonstrated a cross-section view of an NMOS device. The NMOS device has a gate oxide 110 on a substrate 100 and a gate 120 is formed on the gate oxide 110. Two N-type source/drain regions 200 and 210 are formed in the substrate 100 adjacent to the gate oxide 110. Besides, spacers 130 are formed on the sidewalls of the gate oxide 110 and the gate 120 and two N-type light doped drain (LDD) 220 are formed in the substrate 100 below the spacers 130. A positive power line V.sub.D is connected to one of the source/drain regions 200 to serve as a drain region and a power line V.sub.ss is connected to another one of the source/drain regions 210 to act as a source region. In this figure, a typical structure of an NMOS device is shown.
In general, the power line V.sub.ss of an NMOS device is connected to ground. When a voltage difference is applied between the gate 120 and the power line V.sub.D, the fermi-energy band E.sub.F of the metal region A is raised. Furthermore, the voltage different includes a horizontal electrical field E.sub.h 300 and a vertical electrical field E.sub.v 310 and the vertical electrical field E.sub.v is applied to the N-type light doped drain regions 220. Referring to FIG. 3, it shows an energy-band diagram of an NMOS device during a positive voltage is applied on the gate. In this figure, the metal region of an NMOS device is in the region A, the oxide region of this is in the region B and the semiconductor region of this is in the region C. The semiconductor region C has four energy bands to represent the energy-band characteristic of the region. The energy bands include an eigen-energy band E.sub.i, a conducting-energy band E.sub.C, a Fermi-energy band E.sub.F and a valence-energy band E.sub.v. When a positive voltage difference is applied on the metal region A, the valence band of the region C is raised. The valence band in the interface state between the region B and the region C may be higher than the conduction band of the region A. Thus, electrons on the interface state can move from the valence band to the conduction band and these electrons flow out from the drain. This phenomenon is indicated as the band-to-band tunneling. As electrons move from the valence band to the conduction band, electrical holes are produced at the same time. The holes will be accelerated by the horizontal electrical field E.sub.h 300 and these holes become hot carriers. Additionally, the energy of the hot carriers is high enough to tunnel through the region B, the oxide layer, and into the region A. The hot carriers will accumulate on the gate region. Therefore, electrons can easily cross over the barrier layer in the region B from the region A to the region C.
Referring to FIG. 4, it demonstrates a curve that is the relation of the gate voltage V.sub.g to the drain current I.sub.d in an NMOS device. As the gate voltage V.sub.g is less than -0.3 volts, the drain current I.sub.d raises up and it is indicated as a band-to-band tunneling current. That is, the band-to-band tunneling current is a flow of the electrons, which are on the interface state, through the energy gap between the valence band and the conduction band into the drain. Simultaneously, some electrical holes are produced and these holes are accelerated so as to become the hot holes. Because the energy of the hot holes is very high, these holes can tunnel through the oxide layer. Thus, the current is typically caused by positive charges accumulated on the gate region of the device.
Referring to FIG. 5, it shows a voltage-time curve diagram of an NMOS device that an electrostatic discharge (ESD) pulse is applied. Besides, the gate of the NMOS device is floating and it is not coupled with any power line. During the experiment, the ESD pulse is input into the drain of an NMOS device, the floating voltage of the gate and the drain is simultaneously measured. Besides, the total width of the device is 150 or 400 micrometers. For the total width 150 micrometers NMOS under an HBM ESD pulse, the voltage on the drain and the gate is demonstrated in the curve A and B, respectively. For the total width 400 micrometers under an HBM ESD pulse, the floating voltage of the drain and the gate is presented in the curve C and D, respectively. During an ESD pulse is input into the drain, the gate is floating and the ESD pulse input into the drain is about 500 volt. After the voltage on the drain is drop down, the voltage on the gate still maintains at a positive level. That is, even an ESD pulse had been output from the drain, a positive voltage is still induced in the gate. Consequently, the phenomenon proves that the above theory is right. As an NMOS device is operated during the electrostatic discharge, the electrical holes accumulate in the gate to induce a positive voltage difference.
Referring to FIG. 6, it shows two voltage-time curve diagram of an NMOS device. An ESD pulse is input into the drain of an NMOS device and the gate of the NMOS device is floating. As the input ESD pulse is about 1000 volt and 1500 volt, the voltage of the gate is demonstrated by the curve A and the curve B according to FIG. 6, respectively. As mentioned in FIG. 6, after an ESD pulse input into an ESD protection device, the maximum voltage difference in the device could reach 16 volts and the period of the maximum is longer as the voltage pulse is higher. As the ESD voltage input into the device is about 1 kV, the period of the maximum voltage is about 3 nanoseconds. Furthermore, the ESD voltage input into the device is about 1.5 kV, the period of the maximum voltage is about 10 nanoseconds.
According to the above discussion, the ESD protective circuit using NMOS device has a band-to-band tunneling issue. When a positive voltage is applied on the gate of the NMOS device, the channel of the device is turned on and the static charges mainly flow out from the turn-on channel. The current will localize on the channel and that damages the device. Thus, a new ESD protective circuit is needed for preventing the NMOS device of the circuit from destroyed.

Electrostatic discharge protective circuit for reducing an undesired channel turn-on

Taiwan Semiconductor Manufacturing Co., Ltd.


Null detectors 108-1 to 108-3 detect the directions of null points of the respective radiation patterns formed for mobile stations 101-1 to 101-3 and output information indicative of detected null-point directions to notifying section 109, notifying section 109 notifies estimators 110-1 to 110-3 of all null information, and estimators 110-1 to 110-3 estimate the directions where mobile stations that cause interference with the respective stations 101-1 to 101-3 exist, and generate reception weights using null information.

An array antenna radio communication apparatus is a radio communication apparatus that comprises a plurality of antennas and is capable of setting directivity freely by making an adjustment of each of amplitude and a phase to signals received via the respective antennas. The adjustments of amplitude and the phase to a received signal is carried out by multiplying the received signal by weight coefficient (hereinafter referred to as "weight").
The array antenna radio communication apparatus adjusts weights to multiply, making it possible to receive only a signal incoming from a desired direction intensively. It is thereby possible for the array antenna radio communication apparatus to maintain a reception SIR (Signal to Interface Ratio) on the signal incoming from the desired direction.
The conventional array antenna radio communication apparatus, however, has the following problems when it is applied to a mobile communication base station apparatus (hereinafter referred to "base station") used in a CDMA radio communication system.
More specifically, in the CDMA radio communication system, communication between the base station and each mobile communication terminal apparatus (hereinafter referred to as "mobile station") is performed in such a way that a different spread code is assigned to each mobile station and the same frequency band is used at each mobile station.
In the case where a mobile station that transmits signals having high reception power in the base station and a mobile station that transmits signals having low reception power in the base station exist, the signals having high reception power cause interference with signals having low reception power since communications are performed using the same frequency band. For this reason, the base station cannot maintain the reception SIR of signals having low reception power high, with the result that the base station cannot find out the direction where the mobile station that transmits signals having low reception power exists.
Accordingly, this causes a problem in which the base station can form directivity to the mobile station that transmits signals having high reception power but cannot form directivity to the mobile station that transmits signals having low reception power.
Further, in the case where the base station cannot form directivity to the mobile station that transmits signals having low reception power, the base station transmits signals in all directions when transmitting signals to the mobile station that transmits signals having low reception power. This causes a problem in which the signals, which are sent to the mobile station that transmits signals with low reception power, result in interference signals with other mobile stations.
Furthermore, in the base station that performs weight control using an algorithm of MMSE (Minimum Mean Square Error) standard, the signals with low reception power do not occur interference with the signals with high reception power in some instances. In this case, the base station can maintain reception SIR of signals with high reception power sufficiently high without forming directivity to the mobile station that transmits signals with high reception power. Namely, the base station does not form directivity to the mobile station that transmits signals with high reception power. In the case where the base station does not form directivity to the mobile station that transmits signals with high reception power, the base station transmits signals in all directions when transmitting signals to the mobile station that transmits signals with high reception power. Hence, this causes a problem in which the signals, which are sent to the mobile station that transmits signals with high reception power, result in interference signals with other mobile stations.

Array antenna radio communication apparatus and weight coefficient generating method

Matsushita Electric Industrial Co., Ltd.


Tracking a boring tool is performed within an underground region using a locating signal. The boring tool is moved through the ground during a series of distance movements such that potential movement of the boring tool during any one of the distance movements is less than a maximum movement value. A current positional relationship is determined for a current one of the distance movements based on: a last-determined positional relationship established for an immediately preceding one of the distance movements, certain orientation parameters, the maximum movement value and the determined signal strength of the locating signal in the current positional relationship. Target coordinates are accepted and a target position, based on the target coordinates, is included as part of the current positional relationship. The position of the target is unconstrained with respect to system geometry. Steering command features are provided along with steering warnings.

The present application is a continuation application of co-pending application Ser. No. 11/452,474, filed on Jun. 13, 2006 and issued as U.S. Pat. No. 7,218,116 on May 15, 2007; which is a continuation application of application Ser. No. 11/247,300, filed on Oct. 11, 2005 and issued as U.S. Pat. No. 7,084,636 on Aug. 1, 2006; which is a divisional application of application Ser. No. 11/135,968, filed on May 24, 2005 and issued as U.S. Pat. No. 6,975,119 on Dec. 13, 2005; which is a divisional of application Ser. No. 10/971,662, filed on Oct. 22, 2004, and issued as U.S. Pat. No. 6,971,202 on Feb. 15, 2005; which is a divisional of application Ser. No. 10/792,476, filed on Mar. 3, 2004, and issued as U.S. Pat. No. 6,856,135 on Feb. 15, 2005; which is a divisional of Ser. No. application 10/001,854, filed on Nov. 20, 2001, and issued as U.S. Pat. No. 6,727,704 on Apr. 27, 2004; the disclosures of which are incorporated herein by reference.
The present invention relates generally to the field of tracking and/or guiding a boring tool to an underground location using an electromagnetic locating signal and, more particularly, to a system and method which provides for guiding the boring tool to any selected location within an underground region. The target location is unconstrained with respect to any system component geometric arrangements so long as the receiving position is within a receiving range of the boring tool.
One early approach taken by the prior art in tracking a boring tool employs accelerometer and magnetometer sensors in the boring tool. Information is sent to an above ground display through the use of a cable to display pitch and yaw information. In one improvement, the pitch and yaw angles of the boring tool are integrated to estimate the position of the boring tool. It should be appreciated that boring tool position relative to a target is not available in this system. Moreover, accumulation of pitch and yaw measurement errors adversely influences the estimated boring tool position.
Another, more recent, approach taken in the prior art, with regard to guiding an in-ground boring tool, embodies a "homing" configuration. In such a configuration, the boring tool homes-in on a receiving position at which a receiver is located. Homing configurations are generally incapable of homing-in on anything other than the receiving position itself. That is, the target of the boring tool is necessarily limited to the position of the receiver. In one improvement, U.S. Pat. No. 4,881,083 (hereinafter the '083 patent), describes a homing configuration wherein the boring tool homes-in on a vertically oriented line extending through the receiver, in one embodiment, or homing in on the receiver itself, in another embodiment. In accordance with the former embodiment (see FIG. 1 of the '083 patent), the receiver is positionable above a pit for purposes of drilling to some previously underground point on the vertical line below the previous surface of the ground. The system, however, does nothing with respect to monitoring the depth of the boring tool. The depth of the boring tool must be independently established or controlled for the boring tool to properly emerge in the pit. In the latter embodiment (see FIG. 8 of the ('083 patent) and consistent with the prior art in general, the system is incapable of doing any thing other than homing on the receiving position. That is, no target other than the receiving position is possible.
A marked improvement over the general state of the prior art is described as one aspect of U.S. Pat. No. 6,250,402 (hereinafter the '402 patent) which is co-assigned with the present application and which is incorporated herein by reference. In contrast with the prior art, the '402 patent provides for steering a boring tool to specified depth target locations that are directly below the receiver (see FIG. 9 of the '402 patent). As described at column 27, lines 18-20 of the '402 patent, however, even this technique is limited in that the target may not be positioned beyond or in front of the receiver. It should also be appreciated that the target may not be positioned to the side (i.e., laterally displaced) of the receiver.
The present invention serves to remove the foregoing constraints with respect to the prior art while providing still further advantages, as will be described.

Boring tool tracking/guiding system and method with unconstrained target location geometry


Embodiments of the present invention disclose system to determine the best model to perform lead scoring for a given data set. The system can perform a multi-step iterative procedure including variable selection, feature set selection, training data selection, model development, model validation and process optimization. The system also performs local and global optimizations iteratively to determine the best possible model for a given scenario.

A business may rely on lead scoring to prioritize its response to a plurality of leads. Business leads may have different propensities to take an action in relation to business. Such actions may include buying a product sold by the business, signing up for a product or a service of the business, or signing up for a promotion associated with the business. Based on these propensities or scores, the business may tailor its approach to a user or customer.

Predictive modelling to score customer leads using data analytics using an end-to-end automated, sampled approach with iterative local and global optimization


A hybrid photovoltaic and radiant heating and cooling device is provided, wherein the device comprises a photovoltaic panel; a radiant heating and cooling panel; a first heat-exchanging pipe in direct contact with a back surface of the photovoltaic panel; a second heat-exchanging pipe in direct contact with a back surface of the radiant heating and cooling panel; and a thermal storage tank fluidly connecting the first and the second heat-exchanging pipes, wherein the tank is arranged between the first and second heat-exchanging pipes.

Radiant cooling and heating systems are becoming more popular due to the achievable high thermal comfort, low energy demand, quiet operation, and space saving. In these solutions, water pipes are attached to the back of a radiating metal panel. Circulating water is delivered through the pipe to cool down or heat up the panel. The tempered surface extracts a great portion of the heat (in the cooling mode) or adds heat (in the heating mode) inside a room via radiation and transports it to the heat transfer medium which is water via conduction [4], [5]. Convection also plays a role in the heat transfer. As the specific heat capacity of water is much higher than that of air, using water for room heat extraction is 4,000 times more energy efficient [6]. Furthermore, in hybrid cooling, the supplied and conditioned air volume is reduced to the adequate level to maintain a desired indoor air quality. While this is called an air-water cooling system, the conventional air conditioning approach is called an all-air system. Radiant cooling and heating can be integrated in floors, ceilings, walls, or any room surface. However, in the cooling mode, the surface temperature of the radiating panel needs to remain above the dew point temperature of the room air to avoid condensation on the surface. Several studies have explored methods to eliminate the risk of condensation [7]-[12]. However, novel technologies combining heating, cooling, and electricity generation while utilizing renewable resources are needed.

Hybrid photovoltaic device and radiant heating and cooling device with thermal storage


An insulating mount structure for a fuel cell, which includes insulating mounts (2) for mounting the fuel cell stack (1) on a grounded structure (7), and a water barrier (3) extending in a space between the fuel cell a stack (1) and the grounded structure (7), being electrically isolated from both of the fuel cell (1) and the grounded structure (7). The water barrier (3) is formed in a container shape having an opening (3a) on upper side thereof.

Fuel cells or a fuel cell stack are required, in practical use, to be isolated electrically from a surrounding structure thereof.
Japanese Patent Application Laid-Open Publication No. 2002-367651 discloses an insulating mount for electrically isolating a fuel cell stack inside a housing thereof. The insulating mount has an insulator provided between mounting bolts and the bottom wall of the housing.

Insulating mount structure, insulation monitoring system, and insulation monitoring method for fuel cells