A cellular communications network comprises a plurality of gateways for controlling cells in the cellular communications network, the gateways being arranged to receive RF information from at least one mobile station in the network, at least one gatekeeper connected to said gateways by a switched packet communication path, wherein each gateway includes means for generating a handover required indication for a call in which the gateway is engaged and packet generating means for generating a packet addressed to said gatekeeper and including control information comprising a candidate list of alternative cells to which the call could possibly be transferred and wherein the gatekeeper includes packet generating means for generating a packet for sending a handover request for handing over the call to one of said alternative cells.

1. Field of the Invention
The present invention is related to handovers in a communication system and particularly, but not exclusively, to mobile telephone station handovers in an IP-based telecommunications network.
2. Description of the Related Art
Prior art office-based communications systems usually operate conventional fixed-line telephone units linked via an internal switchboard or PBX (private branch exchange). Such fixed-line systems are able to provide relatively high voice quality. However, user mobility is severely impaired.
The advent of digital mobile technologies such as GSM, however, means that mobile systems can now provide equivalent, if not higher, voice quality than fixed-line systems. Mobile systems also allow greater freedom of movement for the user within the office than do fixed-line systems.
WIO (Wireless Intranet Office) is a proprietary communications system developed by the applicants which introduces the concept of utilising mobile telephone units, such as conventional GSM mobile stations, in an office environment. The system makes use of a known concept called Internet Telephony or Voice-over-IP.
Voice-over-IP is a technology which allows sound, data and video information to be transmitted over existing IP-based Local or Wide Area Networks or the Internet. The technology thus provides for convergence and integration of three different media types over the same network.
Prior to the advent of Voice-over-IP, offices often operated three separate networks for the transmission of these media types. As indicated above, fixed-line telephone systems coupled to an in-house PBX provided for voice communication, an office-based LAN or Intranet (i.e. a packet-switched internal network), comprising computer terminals linked via network cards and under the control of a server station, provided for the transmission of "conventional" computer data and video cameras linked to monitors via fixed line or remote transmission link provided for video communication.
Voice-over-IP effectively combines these three media types such that they can be transmitted simultaneously on the same packet-switched network or IP-router throughout the office environment and beyond the confines of the office.
In order to provide for such media convergence, Voice-over-IP often uses a specific ITU (International Telecommunication Union) standard protocol to control the media flow over the Intranet. One common standard protocol used in Voice-over-IP systems, and the one used in the WIO system, is termed H.323.
H.323 is an ITU standard for multimedia communications (voice, video and data) and allows multimedia streaming over conventional packet-switched networks. The protocol provides for call control, multimedia management and bandwidth management for both point-to-point (2 end-users) and multipoint (3 or more end-users) conferences. H.323 also supports standard video and audio codecs (compression/decompression methods such as MPEG) and supports data sharing via the T.120 standard.
Furthermore, H.323 is network, platform and application independent allowing any H.323 compliant terminal to operate in conjunction with any other terminal.
The H.323 standard defines the use of three further command and control protocols:                a) H.245 for call control;        b) Q.931 based protocol for call signalling; and        c) The RAS (Registrations, Admissions and Status) signalling function.
The H.245 control protocol is responsible for control messages governing the operation of the H.323 terminal including capability exchanges, commands and indications. Q.931 is used to set up a connection between two terminals. RAS governs registration, admission and bandwidth functions between endpoints and gatekeepers (defined later).
For a H.323 based communication system, the standard defines four major components:    1. Terminal    2. Gateway    3. Gatekeeper    4. Multipoint Control Unit (MCU).
Terminals are the user end-points on the network, for example a telephone or fax unit or a computer terminal. All H.323 compliant terminals must support voice communications, but video and data support is optional.
Gateways connect H.323 networks to other networks or protocols. For an entirely internal communications network, i.e. with no external call facility, gateways are not required.
Gatekeepers are the control centre of the Voice-over-IP network. It is under the control of a gatekeeper that most transactions (communication between two terminals) are established. Primary functions of the gatekeeper are address translation, bandwidth management and call control to limit the number of simultaneous H.323 connections and the total bandwidth used by those connections. An H.323 "zone" is defined as the collection of all terminals, gateways and multipoint-control units (MCU—defined below) which are managed by a single gatekeeper.
Multipoint Control Units (MCU) support communications between three or more terminals. The MCU comprises a multipoint controller (MC) which performs H.245 negotiations between all terminals to determine common audio and video processing capabilities, and a multipoint processor (MP) which routes audio, video and data streams between terminals.
A conventional Voice-over-IP system described hereinabove normally utilises standard fixed-line telephone systems which are subject to the disadvantages outlined above, namely the lack of mobility and the lack of user features.
The WIO system improves on the Voice-over-IP concept in that it provides for the use of conventional mobile telephone units, such as GSM mobile stations, within the Voice-over-IP system. To provide for such mobile communications within an office-based communication network, WIO combines known Voice-over-IP, as described above, with conventional GSM-based mobile systems.
Thus, internal office calls are routed only through the office intranet and external calls are routed through both the intranet and the GSM network. Such a system provides most or all of the features supported by the mobile stations and the GSM network such as telephone directories, short messaging, multiparty services, data calls, call barring, call forwarding etc. WIO, therefore, provides for integrated voice, video and data communications by interfacing an H.323-based voice-over-IP network with a GSM mobile network.
The WIO system is a cellular network, similar to the conventional GSM network and is divided into H.323 Zones, defined in more detail later. One H.323 Zone may comprise a number of cells.
Given the cellular nature of the WIO system, a major issue to be addressed is that of handovers. As a mobile station moves from cell to cell it reports its location to the BTS or equivalent controller. When it moves from one zone to another, a handover is needed to a different gateway. A similar consideration applies to mobile stations in the conventional GSM network.
In such conventional GSM systems, the need for a handover of a mobile station to a different cell of the network is normally determined by a number of parameters but predominantly including the mobile station measuring the strength of signals transmitted from several base transceiver stations.
Similarly, a mobile station operating in the WIO system is able to compare the signal strengths of the signals received by several base stations, in different cells, in the network.
However, added complexities arise in the WIO system since a mobile unit operating within such a system is not only able to move between cells within the system, but also between zones and even between the system itself and an external GSM network.
It can be seen, therefore, that there are several different types of handovers which may need to be executed in the normal operation of a WIO system. These types of handovers are:                a) The handover of a mobile from one WIO cell to another whilst engaged in a call.        b) The handover of a mobile from one WIO zone to another whilst engaged in a call.        c) The handover of a mobile from a cell within the WIO system to a cell within an external GSM system.        d) The handover from a cell within an external GSM system to a cell within the WIO system.

Handover in a mobile communication system


A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon. Only the second layer of the bi-layer nFET embedded stressor element includes the implanted source/drain regions.

The present invention relates to a semiconductor structure and a method of fabricating the same. More particularly, the present invention relates to a bi-layer embedded stressor element for n-channel field effect transistors (nFETs) which greatly minimizes defect density and is implant damage free as well as a method of fabricating the bi-layer nFET embedded stressor element.
Mechanical stresses within a semiconductor device substrate have been widely used to modulate device performance such as, for example drive current. For example, in common silicon technology, the channel of a transistor is oriented along the {110} planes of silicon. In this arrangement, hole mobility is enhanced when the channel is under compressive stress in the film direction and/or under tensile stress in a direction normal of the channel, while the electron mobility is enhanced when the silicon film is under tensile stress in the film direction and/or under compressive stress in the direction normal of the channel. Therefore, compressive and/or tensile stresses can be advantageously created in the channel region of a p-channel field effect transistor (pFET) and/or an n-channel field effect transistor (nFET) in order to enhance the performance of such devices.
One possible approach for creating a desirable stressed silicon channel region is to form embedded SiGe or Si:C stressors (i.e., stress wells) within the source and drain regions of a complementary metal oxide semiconductor (CMOS) device to induce compressive or tensile strain in the channel region located between the source region and the drain region. For example, it has been demonstrated that hole mobility can be enhanced significantly in p-channel silicon transistors by using an embedded SiGe stressor in the source and drain regions. For re-channel silicon transistors, it has also been demonstrated that the electron mobility can be enhanced by using selective Si:C in which C is substitutional.
When the Si:C stressor includes a high content of C in substitutional sites of Si, a higher tensile strain can be applied to the Si channel. However, it is extremely difficult to obtain selectivity to oxide and nitride with a high content of C in the substitutional sites of Si due to extremely low carbon solubility (on the order of less than 10−6) in Si and the incompatibility of the Si:C precursor reactant gas to obtain selectivity.
Moreover, the integration of embedded Si:C into a typical complementary metal oxide semiconductor (CMOS) process is difficult because either the implantation process or the anneal process can completely relax the embedded Si:C. In prior art processes including an embedded Si:C stressor, high defect density is generated and dopant diffusion is uncontrollable in the embedded Si:C stressor.

Bi-layer nFET embedded stressor element and integration to enhance drive current

International Business Machines Corporation


Provided is a speaker apparatus including a first speaker having a first surface communicating with an interior and a second surface not communicating with the interior; a second speaker having a first surface communicating with an exterior and a second surface not communicating with the exterior; and a cabinet having boundary surfaces that form an enclosed space. The second surface of the first speaker and the second surface of the second speaker are arranged on the boundary surfaces and are facing the enclosed space.

The present disclosure relates to a speaker apparatus and an acoustic system.
There is a technology related to a speaker apparatus for forming an infinite baffle with a speaker back surface disposed so as to be directed to the outside of a vehicle (see Japanese Patent No. 5988874, for example). There is a technology related to a speaker apparatus including a main speaker and an auxiliary speaker, for installing a sound emitting surface of the auxiliary speaker so as to be directed to a back surface of the main speaker (see Japanese Patent Laid-Open No. Hei 9-74599 and Japanese Patent No. 4079827, for example).


The invention is a drawer with Zargen drawer slide system. The side walls of the drawer are simultaneously the Zargen drawer slides, and the Zargen drawer slide system has horizontal flanges that support and hold the drawer bottom. There are fastening devices on the Zargen drawer that connect the Zargen drawer together with the drawer bottom. These fastening devices take the form of latch connectors, which are anchored, swinging, in the Zargen drawer slide system and can be engaged or disengaged manually with the corresponding notches in the drawer bottom.

A drawer of a similar type was made known by DE-A-38 05 669. The drawer has a metallic Zargen drawer slide system, whose vertical member forms the side of the drawer, and under each one is a horizontal member on which the drawer bottom fits. Hooks, which project into the corresponding notches on the bottom panel, are pressed out of the Zargen drawer slide system's horizontal members. The hooks can be bent with the appropriate tool and are anchored in the notch's panel, connecting the bottom panel securely with the Zargen drawer slide system.
Publication EP-A-0 429 428, likewise, makes known a metallic Zargen drawer slide system that has support flanges on which the drawer bottom fits. Holding tabs are pressed from the support flanges. Grooves are located in the holding tabs to engage the drawer bottom. Here, again, the holding tabs can be bent with the appropriate tool, so that they can dig into the groove's flanks and securely connect the drawer bottom to the Zargen drawer slide system.
The connection, previously made known, between the Zargen drawer slide system and the drawer bottom has the disadvantage that the assembly (especially the insertion of the bottom panel) requires an appropriate tool. Another disadvantage is that once the connection is made between the Zargen drawer slide system and the drawer bottom, it is impossible or difficult to undo the connection without great effort and expense or without the connection components being damaged.


The present disclosure describes expansion card interfaces for a printed circuit board and methods of making the same. The methods include forming electrical pads of the expansion card interface on a substrate, and dividing at least one electrical pad into a first portion and a second portion. The resulting expansion card interfaces have the first portion conductively coupled to a circuit on the printed circuit board, and the second portion conductively isolated from the first portion.

Expansion cards and other add-on cards can have interfaces, hereinafter expansion card interfaces. These expansion card interfaces are used extensively in computer systems. For example, many expansion cards (daughter cards) use expansion card interfaces for connecting to a bus on a main board (motherboard) of a computer system. One specific type of connector that can receive an expansion card is a peripheral component interconnect express (PCIe) connector, such as a PCIe Gen 4 or Gen 5 connector.
FIG. 1 illustrates a conventional connection of an expansion card 100 with a bus 102, such as a PCIe bus. The bus 102 includes connector pins 104 within a slot 106 defined by a housing 108. The connector pins 104 contact both sides of the expansion card 100, when the expansion card 100 is inserted into the slot 106. At least one side of the expansion card 100 includes electrical pads (FIG. 2), which are commonly referred to as golden fingers. The connector pins 104 contact the electrical pads, which forms an electrical connection between the expansion card 100 and the bus 102.
FIG. 2 illustrates an interface region 200 of a conventional expansion card, such as the expansion card 100 of FIG. 1. The interface region 200 includes four electrical pads, including two signal pads 202 and two ground pads 204 (collectively referred to as "contact pads" or "pads"). The signal pads 202 and the ground pads 204 are formed on a substrate 206 of a printed circuit board (PCB) having the interface region 200. The signal pads 202 and the ground pads 204 extend to the edge 206a of the substrate 206. The signal pads 202 carry one or more signals to and from the electrical circuit 205 on the printed circuit board and the corresponding bus (e.g., bus 102 of FIG. 1), within which the interface region 200 is inserted.
Connector pins (e.g., connector pins 104 of FIG. 1) of the bus (e.g., bus 102 of FIG. 1) are configured to contact the signal pads 202 and the ground pads 204 at contact points 208 (represented by the dotted circles). Based on the lengths of the signal pads 202 and the ground pads 204, and the depth of the corresponding bus (e.g., bus 102 of FIG. 1), the contact points 208 are generally in the middle 214 of the signal pads 202 and the ground pads 204 (represented approximately by the dotted line).
The lengths of the signal pads 202 and the ground pads 204, from generally the contact points 208 to the distal ends 202a and 204a, form signal stubs 210 and ground stubs 212, respectively (collectively referred to as contact stubs or stubs). The lengths of the signal pads 202 from generally the contact points 208 to the proximal ends 202b, opposite from the distal ends 202a, form signal electrical contacts 216. The lengths of the ground pads 204 from generally the contact points 208 to the proximal ends 204b, opposite from the distal ends 204a, form ground electrical contacts 218. The signal electrical contacts 216 and the ground electrical contacts 218 are collectively referred to as electrical contacts.
The signal stubs 210, the ground stubs 212, or both can cause reflections in the signal electrical contacts 216, the ground electrical contacts 218, or both; thereby potentially reducing signal margins. For connections of high-frequency signals using the conventional expansion card with interface region 200, the longer the signal stubs 210, the ground stubs 212, or both; the greater the reduction in the signal margin.
FIG. 3 illustrates a plot 300 of signal loss measurements for different lengths of signal stubs 210 and ground stubs 212 (both from FIG. 2) as a function of signal frequency. The line 302 represents an 80 millimeter (mm) stub; the line 304 represents a 110 mm stub; and the line 306 represents a 160 mm stub. As shown, the increase of signal loss measurements coincides with the increase in the length of the contact stubs.
Accordingly, there is a need for expansion card interfaces for use in connections of high-frequency signals that do not suffer from a reduction in signal margin, and methods for making such expansion card interfaces.

Expansion card interfaces for high-frequency signals and methods of making the same


A refrigerator in which an opening having a size corresponding to the size of a refrigerator compartment is provided in a refrigerator compartment door and an outer door to open/close the opening is rotatably coupled to the refrigerator compartment door so that a plurality of door guards provided in a space corresponding to the size of the refrigerator compartment may be used by only opening/closing the outer door, and the refrigerator compartment door and the outer door may be rotated on one hinge shaft and the outer door has an auto closing structure so that the outer door may be automatically closed when a predetermined portion of the outer door is opened.

1. Field
The following description relates to a refrigerator.
2. Description of the Related Art
In general, a refrigerator is a home appliance that keeps food fresh by including a storage compartment and a cold air supply device to supply cold air to the storage compartment.
The temperature of the storage compartment is maintained in a predetermined range of temperature required to keep food fresh.
The storage compartment of the refrigerator is disposed in such a way that a front portion of the storage compartment is opened, and the open front portion of the storage compartment is closed by a door so as to maintain the normal temperature of the storage compartment.
The storage compartment is partitioned in right and left directions by a partition, and the storage compartment that is partitioned in right and left directions is opened/closed by doors, for example, side-by-side doors that are rotatably hinge-coupled to each other.
An opening is provided in a refrigerator compartment door that opens/closes a refrigerator compartment of the storage compartment, and the opening is opened/closed by a home bar door.
Since the opening that is opened/closed by the home bar door is provided to a size at which only a predetermined space of the refrigerator compartment may be used, there are inconveniences of opening the whole refrigerator compartment door so as to take out food accommodated in a space other than the predetermined space that may be used through the opening.


A clockspring assembly is provided having means to indicate that the clockspring assembly is properly centered upon installation in a motor vehicle. The clockspring assembly includes a hub and a rotor that is rotatable relative to the hub. A ribbon cable is wound about the rotor and provided with one end attached to the rotor and another end attached to the hub. An electronic centering indicator is mounted to the hub and is configured to indicate a centered position of the hub relative to the rotor as a result of a condition occurring when the hub becomes centered with the rotor. Upon the occurrence of the condition, the centering indicator is configured to provide an electronic signal indicating that the clockspring is properly centered.

1. Field of the Invention
The present invention generally relates to clockspring assemblies. More specifically, the invention relates to an electronic centering indicator for a clockspring assembly.
2. Description of Related Art
Substantially all automotive vehicles are now manufactured with one or more airbags. Typically, a driver's side airbag is provided in the steering wheel facing the driver of the vehicle, and a second airbag is provided in the portion of the instrument panel facing the front passenger seat of the vehicle. The present discussion concerns the airbag located in the steering wheel.
Because the various collision sensors of an automotive vehicle provide a signal causing inflation of the airbag instantaneously with initiation of a collision event, and sometimes prior to the collision event, the airbag must be in continuous electrical connection with the collision sensors and other electronics in the vehicle body. Thus, a driver side airbag requires that an electrical connection be continuously provided between the airbag, as it rotates with the steering wheel, and the stationary sensors and other electronics.
Electrical connections between rotatable and stationary parts are known. In one well known connection, an electric brush rests upon a conductive ring, with one of the parts being rotatable. However, with this type of connection there is a risk, during the early or pre-stages of a collision, that the brush may separate or lose contact with the conductive ring. This loss of contact may create a transient failure in the electrical connection, resulting in delayed deployment of the airbag.
Another type of connection between rotatable and stationary parts is a clockspring assembly or connector. Clockspring assemblies typically include an outer housing, a rotor member and a "clockspring." The clockspring is a coil of flat cable having one end connected to a plug or terminal on the outer housing and the other end connected to a plug or terminal on the rotor. The terminal on the outer housing, also referred to as the hub, is further connected to the electronics in the car body and the terminal on the rotor is connected to other electronics on the steering wheel associated with the airbag. As the steering wheel rotates, the clockspring of the clockspring assembly is wound and unwound, depending on the direction of rotation, and provides a continuous wired connection between the two parts.
Clockspring assemblies are typically manufactured at the site of a specialty manufacturer and then shipped to the vehicle manufacturer where they are further installed with the steering wheel. Because of this, it is important that the position of the outer hub with respect to the rotor member remain in a known position so that the clockspring assembly can be installed in a centered position on the steering wheel. Such a position is one where the clockspring is capable of an equal amount of rotation in either direction, without the clockspring becoming completely wrapped or unwrapped around the rotor.
In view of the above, it is apparent that there is a need for a mechanism that ensures that the clockspring assembly is properly centered once installed on the column of the steering wheel, before the vehicle leaves the assembly plant, removing the possibility of over rotation of the clockspring assembly due to misassembly.

Electronic centering indicator for clockspring assembly


The present application provides “hot desking” features for multi-device users. A number of automatic hot desking registrations are provided in which users are assigned multiple devices on a permanent basis. A private branch exchange or central switch can be provided with a list of these devices and can relieve the user of the requirement of registration by detecting use of these devices and assigning user features and other pertinent system properties e.g. as an indication of location for find me/follow me services. The extension allows for automatically hot desking using a listed device, hot desking based on a location associated with a listed device, and hot desking using declared associations of listed devices.

U.S. Pat. No. 5,657,377 ('377 Patent) titled PORTABLE TELEPHONE USER PROFILES, which is assigned to Mitel Networks Corporation, Canada, describes how a user can register for feature services on a central switch from devices located anywhere in the network including that switch. As taught, when a user signals the central switch from a device on that switch, or from a device on another switch, features can be assigned to them on calls to and from that device. This is commonly termed "hot desking" and allows features to be assigned to a user rather than a specific device. With this, users can roam from device to device and receive the features that they require.
Hot desking can provide a user with their enterprise features from devices that are connected anywhere in the public switched telephone network. This can provide a form of registration which allows the system to route incoming calls to a roaming user. It can also allow the user to declare the device at which they can be found and allow the system to supply the user with their preferred features at that device.
The '377 Patent was developed to provide services to a single device. Today, however, users are often associated with multiple devices. For example, a user can have a cell phone, a residence telephone, an office telephone, etc. The provision of multiple devices extends the scenario in which the '377 Patent can be used, which as disclosed within the present application can maintain multiple devices that are permanently associated with the user but can shift registrations for the central switch (PBX) features among them. A user can at one time wish to receive their PBX calls on their cell phone and at another time have them routed to their residence telephone. This can provide the opportunity for extending the functionality of the '377 technology to provide more benefits to the user.

Extended hot desking features for multi-device users


A process for producing semiconductor chips having a protective film on the back surface includes the steps of: providing a sheet to form the protective film having a release sheet and a protective film-forming layer formed on a detachable surface of the release sheet, wherein the protective film-forming layer includes a thermosetting component, an energy ray-curable component and a binder polymer component; adhering a protective film-forming layer of the sheet to form the protective film onto a back surface of a semiconductor wafer having circuits on its surface; curing the protective film-forming layer by irradiation with an energy ray, and thereafter, further conducting the additional steps of (in any order): detaching the release sheet from the protective film-forming layer; further curing the protective film-forming layer by heating; and dicing the semiconductor wafer together with the protective film-forming layer with respect to each circuit.

1. Field of the Invention
The present invention relates to a sheet to form a protective film for chips, which enables to efficiently form a protective film on a back surface of a semiconductor chip, and thereby contributes to improvement in production efficiency of chips. More particularly, the present invention relates to a sheet to form a protective film for chips, which is used in production of semiconductor chips by face down mounting process.
The present invention also relates to a process for producing semiconductor chips, using the sheet to form a protective film for chips.
2. Description of the Prior Art
Recently, production of semiconductor devices is made through a so-called face down mounting process. In the face down process, chips are electrically connected with a substrate through a convex portion (bump) formed on a circuit surface of the chip to ensure its conductivity to the substrate.
Semiconductor devices are generally produced though the following steps:
(1) forming a circuit on a surface of a semiconductor wafer by etching or the like and providing a bump on the appointed position of the circuit surface;
(2) grinding the back surface of semiconductor wafer to have a given thickness;
(3) fixing the back surface of semiconductor wafer onto a dicing sheet which is tautly supported by a ring frame, and dicing the wafer to separate each circuit by the use of a dicing saw to obtain semiconductor chips; and
(4) picking up the semiconductor chips to mount them face down on a prescribed substrate and sealing the chip in a resin or coating the back surface of chip with a resin according to necessity for chip protection, thereby obtaining a semiconductor device.
The resin sealing is performed by dripping resin in a proper amount on the chip (potting method) or using a mold (molding method), both followed by curing. The potting method has a drawback of difficulty in dripping a proper amount of resin. The molding method involves washing of the mold, which will require additional costs for equipment and operation thereof.
The resin coating may cause uniform quality because of the difficulty in spreading a proper amount of resin evenly on the chips.
Therefore, the technique which is capable of forming a highly uniform protective film on a back surface of chip by simplified operation, has been desired.
In the grinding of the back surface of the wafer in step (2), minute streaky scratches are formed on the back surface of the chip owing to the use of a grinding machine. The minute scratches may cause cracks during the dicing in step (3) or after the device is packaged. As such, it has been conventionally required in some cases to perform chemical etching after the mechanical grinding to eliminate the minute scratches. The chemical etching, as a matter of course, raises problems related to the cost increase for its equipment and operation.
Therefore, the technique for prevailing adverse effects resulting from minute scratches has been desired, even if minute scratches are left on the back surface of wafer as a result of mechanical grinding.
In light of the above prior art, it is an object of the present invention to provide a process through which a highly uniform protective film can be readily formed on a back surface of chip, and, even if minute scratches are formed on the back surface of chip as a result of mechanical grinding, the chip is prevailed over adverse effects resulting from the scratches. It is another object of the invention to provide a sheet to form a protective film for chips employable in the above process.

Process for producing semiconductor chips having a protective film on the back surface


An exhaust gas containing a perfluoride component (PFC) and SiF4 is conducted into a silicon remover and brought into contact with water. A reaction water supplied from a water supplying piping and air supplied from an air supplying piping are mixed with the exhaust gas exhausted from the silicon remover. The exhaust gas containing water, air, and CF4 is heated at 700° C. by a heater. The exhaust gas containing PFC is conducted to a catalyst layer filled with an alumina group catalyst. The PFC is decomposed to HF and CO2 at a high temperature exhausted from the catalyst layer is cooled in a cooling apparatus. Subsequently, the exhaust gas is conducted to an acidic gas removing apparatus to remove HF. In this way, the silicon component is removed from the exhaust gas before introducing the exhaust gas into the catalyst layer. Therefore, the surface of the catalyst can be utilized effectively, and the decomposition reaction of the perfluoride compound can be improved.

The present invention relates to a method of processing perfluorocarbon and an apparatus therefor, and more particularly, the invention relates to a preferable method for use in processing perfluorocarbon (hereinafter, called PFC) contained in an exhaust gas from a semiconductor manufacturing plant, and an apparatus therefor.
In a known semiconductor manufacturing process, various uses are made of PFC gases, which are harmless to a human being, are non-explosive, and are easy to handle, such as CF4 and the like, which are used as an etchant in a dry etching process, and C2F6 and the like, which are used as a cleaning gas in a CVD process. These PFC gases are ionized by a plasma discharge of a high voltage after being introduced into an etching apparatus or a CVD apparatus, and are used to perform etching or cleaning of wafers in an active radical state.
However, the amount of PFC gas actually consumed in the etching or the cleaning is several % to tens % by volume.
The rest of the PFC gas is exhausted outside the system in an unreacted state.
TABLE 1Properties of gasConsumePFCWarmLife.2)Toxic.in JapanNogascoeff.1)(year)react.3)(t/year)Main use1CF44)6,30050,000low-300(′94)Etchingtoxic.394(′95)gas:75%non-CVDflam.5)cleaninggas: 25%2CF66)12,50010,000low-4(′94)P-CVDtoxic.200(′95)cleaningnon-gasflam.5)3CF37)9.720179toxic25(′94)CVD39(′95)cleaninggas: 92%IC-Etchinggas: 8%4CHF38)12,100250—55(′94)dryetching5C4F89)8.7003,200——etching6C3F810)7,0002,600——P-CVDcleaninggas7SF611)24,9003,200—26(′94)dryetching:90% CVDcleaninggas: 10%Remarks:1)Warming-up coefficient2)Life time in atmosphere3)Toxicity and reactivity4)Flon 145)Non-flammable6)Flon 1167)Nitrogen trifluoride8)Flon 239)Flon C 31810)Flon 21811)Sulfur hexafluoride
Because a fluorine atom has a small atomic radius and a strong bonding force, PFC, a compound of fluorine atoms, has stable characteristics. PFC includes flon, such as FC (fluorocarbon) and HFC (hydrofluorocarbon), which do not include chlorine, and perfluoride compounds, such as nitrogen trifluoride (NF3) and sulfur hexafluoride (SF6). Main materials of PFC, and their characteristics and main use, are indicated in Table 1.
PFC exists stably in the atmosphere for a long time, and, because it does not contain chlorine, its molecular structure is compact, and its bonding force is strong. For instance, the life of CF4 is as long as 50,000 years, the life of C2F6 is 10,000 years, and the life of SF6 is 3,200 years. However, PFC has a large warming-up coefficient. In comparison with C02, CF4 is 6,500 times, C2F6 is 9,200 times, and SF6 is 23,900 times. Therefore, although a smaller amount of PFC is released than C02, which is required to be decreased since it is a cause of warming-up of the earth, it is anticipated that the release of PFC will be certainly restricted in the near future. In this case, a countermeasure against release of the exhaust gas from semiconductor manufacturing plants, which is the source of a majority of the PFC being released, will become an important consideration.
For instance, in an etching step performed in a semiconductor manufacturing plant, a PFC gas for etching is supplied into a chamber. A part of the PFC gas is converted to highly corrosive fluorine atoms by applying a plasma thereto. The fluorine atoms perform an etching of silicone wafers. The exhaust gas from the chamber is pumped out continuously by a vacuum pump. In order to prevent corrosion by the acidic gas, purging of the exhaust gas with nitrogen gas is performed. The exhaust gas contains nitrogen in the amount of 99% and PFC in a residual amount of 1%, which has not been used for the etching. The exhaust gas pumped out by the vacuum pump is conducted to an acid removing apparatus, through the duct for removing the acidic gas, and is released into the atmosphere in a state in which it contains PFC.
In the semiconductor manufacturing plants, a reagent method and a combustion method have been used practically as a method of decomposition of PFC. The former is a method wherein fluorine is chemically fixed at approximately 400–900° C. by using a special reagent. In accordance with this method, exhaust gas processing is not necessary, because no acidic gas is generated by the decomposition. The latter is a method wherein the PFC gas is conducted to a combustor and is decomposed thermally in a flame of at least 1,000° C. generated by combustion of LPG and propane gas.
In accordance with the above reagent method, the reagent which is reacted chemically with the PFC can not be re-used, and the expensive reagent, which is consumed in the reaction as a consumable article, is required to be supplied frequently. Therefore, the operation cost is 10 to 20 times in comparison with that of the combustion method. Furthermore, because an amount of the reagent equivalent to the amount of the PFC to be processed is necessary, practical equipment for performing the reagent method requires a large area, such as approximately 3–5 m2.
In accordance with the above combustion method, thermal decomposition is performed at a high temperature, such as at least 1,000° C. for C2F6 and at least 1,100° C. for CF4, and a large amount of thermal energy is required. Furthermore, the combustion method generates NOx and a large amount of C02 by combustion at a high temperature. Because the PFC is exhausted in a state in which it is diluted with inactive N2 gas, a potential for miss-fire is high, and a sufficient operation control is required.
An application of the combustion method to the semiconductor manufacturing process has been studied. The PFC is exhausted as a mixed gas diluted with N2 gas having a concentration of several %. Accordingly, in the combustion of the mixed gas, a large amount of air for combustion is required in addition to a fuel gas. Consequently, because the amount of gas to be processed is increased, the size of the apparatus is increased, and the area for the apparatus is required to be as large as approximately 0.7–5 m2.
For instance, when C2F6 is contained in the amount of 1% in an exhaust gas exhausted at 100 liter/min. from a semiconductor manufacturing process, the necessary amount of LPG to make the thermal decomposition temperature at temperature at least 1,000° C. is 10 liter/min. and the necessary amount of air is approximately 400 liter/min. with an excessive ratio of 1.5. The total amount of the exhaust gas after the combustion becomes approximately 500 liter/min., because oxygen in the air is consumed and CO, is generated at a rate of 30 liter/min. The total amount of the exhaust gas is increased almost 5 times that of the exhaust gas exhausted from the semiconductor manufacturing process. The typical semiconductor manufacturing plant has a large restriction on space, because the plant must be provided with clean rooms. Accordingly, it is difficult to keep the necessary area for installing a new exhaust gas processing apparatus in a previously built semiconductor manufacturing plant. on the other hand, a catalytic method, wherein PFC is decomposed at approximately 400° C., has been applied to CFC (chlorofluorocarbon) and HCFC (hydrochlorofluorocarbon), which have similar chemical compositions with PFC and an ozone destruction effect. Because CFC and HFC contain chlorine atoms having a large atomic radius in their compositions, the molecular structures composed by bonding fluorine atoms and hydrogen atoms having a small atomic radius are distorted. Therefore, CFC and HFC can be decomposed at a relatively low temperature.
A method of decomposing CFC (or HFC) using a catalyst was disclosed in JP-A-9-880 (1997). In accordance with this method, a mixed gas of heated air, which is made up of a carrier gas, steam and CFC, is conducted to a catalyst layer. The temperature of the catalyst layer is approximately 430° C., because CFC has a low decomposition temperature. The exhaust gas containing decomposed gases exhausted out of the catalyst layer is cooled rapidly with cooling water, in order to prevent generation of dioxine.

Apparatus for processing perfluorocarbon


Optical encoders having one or more of a number of disclosed features are disclosed. The features of the optical encoder in accordance with the present invention include a symmetrical (for example, circular) emitter; baffle between the emitter and a detector; double-dome or single-dome encapsulant; multiple detector; and multiple (at least three) data channels.

The present invention relates generally to optical encoders. More particularly, the present invention relates to optical encoders having various orientations.
Optical encoders detect motion and typically provide closed-loop feedback to a motor control system. When operated in conjunction with a code scale, an optical encoder detects motion (linear or rotary motion of the code scale), converting the detected motion into digital signal that encode the movement, position, or velocity of the code scale. Here, the phrase "code scale" includes code wheels and code strips.
Usually, motion of the code scale is detected optically by means of an optical emitter and an optical detector. The optical emitter emits light impinging on and reflecting from the code scale. The reflected light is detected by the optical detector. A typical code scale includes a regular pattern of slots and bars that reflect light in a known pattern.
FIGS. 1A through 1C illustrate a known optical encoder 100 and a code scale 120. FIG. 1A is a cutaway side view of the optical encoder 100 and the code scale 120. FIG. 1B is the code scale 120 as viewed from the optical encoder 100. FIG. 1C is the optical encoder 100 as viewed from the optical encoder 100.
FIGS. 1A through 1C include orientation axes legend for even more clarity.
Referring to FIGS. 1A through 1C, the encoder 100 includes an optical emitter 102 and an optical detector 104 mounted on a substrate 106 such as a lead frame 106. The optical emitter 102 and the optical detector 104 as well portions of the lead frame 106 are encapsulated in an encapsulant 108 including, for example, clear epoxy. The encapsulant 108 defines a first dome-shaped surface 110 (first lens 110) over the optical emitter 102 and a second dome-shaped surface 112 (second lens 112) over the optical detector 104.
The optical emitter 102 emits light that leaves the encapsulant 108 via the first lens 110. The first lens 110 concentrates or otherwise directs the light toward the code scale 120, the light reflecting off of the code scale 120. The reflected light reaches the optical detector 104 via the second lens 112. The second lens 112 concentrates or otherwise directs the reflected light toward the optical detector 104. The optical detector 104 can be, for example only, photo detector that converts light into electrical signals.
In the illustrated example, the optical emitter 102 is a slit-type light emitter, the slit along the Y-axis. As illustrated, the optical detector 104 is placed along the Y-axis. Further, the slots and bars of the code scale 120 runs along the Y-axis.
Accordingly, the optical encoder 100 and the code scale 120 are oriented and positioned relative to each other in order to detect movements of the code scale 120 in the X-axis direction.
This design has several weaknesses. For example, the optical encoder 100 is sensitive to misalignments. Even slight misalignments of the slit emitter 102 lead to contrast degradation, thus degradation of the performance of the optical encoder 100. Further, the optical encoder 100 detects movements in only one direction (for example, along the X-axis direction in the illustrated example), limiting flexibility in orientation of the encoder package. Moreover the existing optical encoder has limited number (typically at most two) of data channels on one side of the emitter.
Accordingly, there remains a need for improved optical encoder that alleviates or overcomes these shortcomings.

Reflective encoders with various emitter-detector configurations


A master video server may deliver video streams to multiple sub-master video servers pursuant to the request of each sub-master video server. Each sub-master video server, in turn, may deliver video steams to multiple slave video servers pursuant to the request of each slave video server. Each sub-master video server may also deliver video streams to one or more other sub-master video servers pursuant to the request of each of the other sub-master video servers.

This disclosure relates to content delivery networks, such as content delivery networks that deliver streaming videos.
Some content delivery networks include a master server and several slave servers. Each slave server receives requests from a group of user stations for video streams. After receiving each request, each slave server delivers its own request for the streaming video to the master server. In turn, the master server delivers the requested streaming video to the slave server which, in turn, delivers it to the requesting user station.
This content delivery network architecture can present challenges as the number of user stations grow. Each slave server may be limited in the number of user stations that it can simultaneously service. As a result, additional slave servers may need to be added as the number of user stations grows.
The master server may also be limited in the number of slave servers that it can simultaneously service. As a consequence, this architecture can quickly grow to a size that can no longer be adequately supported by the master server. In turn, this can restrict the number of user stations that can be added to the system. It can also result in poor performance, causing undesirable disruptions during delivery of the video streams.

Distributed content delivery network architecture


An article that uses a magnetoresistive material comprising one or more CrO.sub.2 grains having an insulating material, advantageously Cr.sub.2 O.sub.3, along at least a portion of the grain boundary or boundaries, the magnetoresistive article advantageously exhibiting a magnetoresistance ratio greater than 12% at 5K and 20 kOe.

1. Field of the Invention
The invention relates to articles comprising a magnetoresistive material.
2. Discussion of the Related Art
The magnetoresistance (MR) of a material is typically measured by the resistivity pH of the material in an applied magnetic field H minus the resistivity .rho..sub.o in the absence of an applied magnetic field. This resistivity difference .DELTA..rho. (equal to .rho..sub.H -.rho..sub.o) may be normalized by dividing by .rho..sub.H or .rho..sub.o, and is thereby expressed as a magnetoresistance ratio in percent. Resistance values may alternatively be used. Conventional materials such as permalloy typically have a MR ratio of a few percent when normalized by either value.
Materials exhibiting magnetoresistance ratios of greater than a few percent are useful in a variety of devices. The devices utilize the magnetoresistive materials' ability to respond, by way of resistive changes, to small changes in applied magnetic field. This effect is useful, for example, in magnetic sensing devices, current sensing devices, memory elements, or even acoustic devices. Examples of useful devices are discussed, for example, in co-assigned U.S. Pat. Nos. 5,450,372 and 5,461,308, the disclosures of which are hereby incorporated by reference.
Desirable MR has been observed in mixed metal oxides, e.g., La--Ca--Mn--O, La--Ba--Mn--O, and La--Sr--Mn--O. See, e.g., K. Chahara et al., Applied Physics Letters, Vol. 63 (14), at 1990; R. von Helmholt et al., Physical Review Letters, Vol. 71 (14), at 2331; and co-assigned U.S. Pat. Nos. 5,549,977 and 5,538,800. The magnetoresistance of La-Sr-Mn-O perovskites appears to be better in polycrystalline samples, as opposed to single crystals, possibly due to spin-polarized tunneling of electrons between grains. See H. Y. Hwang et al., Physical Review Letters, Vol. 77 (10), at 2041. In particular, it has been found that trilayer structures using La--Ca--Mn--O and La--Sr--Mn--O perovskites undergo a change in resistance by a factor of 2 in a low applied field of 200 Oe, indicating the potential use of such materials in field sensors. See J. Z. Sun et al., Applied Physics Letters, Vol. 69 (21), at 3266.
These manganite perovskites, however, have a relatively low Curie temperature, the highest achieved being about 105.degree. C. See, e.g., H. Y. Hwang et al., Physical Review Letters, Vol. 75 (5), at 914. The Curie temperature is the temperature above which ferromagnetism disappears. As the temperature moves above and beyond the Curie temperature, magnetoresistance becomes smaller. Devices using such manganite perovskites must therefore be placed in a working environment below the Curie temperature to ensure that the requisite magnetoresistive properties are present. Clearly, magnetoresistive materials having a Curie temperature higher than 105.degree. C. offer commercial potential for a wider range of applications. In addition, the manganite perovskites are relatively difficult to prepare and incorporate into devices such as those discussed above, compared to more conventional metals and oxides.
Thus, magnetoresistive materials that have higher Curie temperatures than current magnetoresistive materials, and which can be produced and incorporated into devices more easily, are desired.

Article comprising magnetoresistive material


An electrical connector includes a housing and a plurality of contact modules in the housing. Each contact module includes a mating edge and a mounting edge. Each mating and mounting edge has a row of contacts including signal and ground contacts arranged in one of a first and second pattern. Adjacent contact modules in the housing have a different one of the first and second patterns. The first and second patterns each include pairs of signal contacts and individual ground contacts arranged in an alternating sequence. Each mating edge contact is electrically connected to a corresponding mounting edge contact by signal conductors and ground conductors extending along a predetermined path within the contact module. Each ground conductor has a width transverse to the predetermined path that is substantially equal to a combined transverse width across a pair of signal conductors in an adjacent contact module. The ground conductor shields the pair of signal conductors in the adjacent contact module.

The invention relates generally to electrical connectors and, more particularly, to an electrical connector for transmitting signals in differential pairs.
With the ongoing trend toward smaller, faster, and higher performance electrical components such as processors used in computers, routers, switches, etc., it has become increasingly important for the electrical interfaces along the electrical paths to also operate at higher frequencies and at higher densities with increased throughput.
In a traditional approach for interconnecting circuit boards, one circuit board serves as a back plane and the other as a daughter board. The back plane typically has a connector, commonly referred to as a header, that includes a plurality of signal pins or contacts which connect to conductive traces on the back plane. The daughter board connector, commonly referred to as a receptacle, also includes a plurality of contacts or pins. Typically, the receptacle is a right angle connector that interconnects the back plane with the daughter board so that signals can be routed between the two. The right angle connector typically includes a mating face that receives the plurality of signal pins from the header on the back plane, and contacts that connect to the daughter board.
At least some board-to-board connectors are differential connectors wherein each signal requires two lines that are referred to as a differential pair. For better performance, a ground contact is associated with each differential pair. The receptacle connector typically includes a number of modules having contact edges that are at right angles to each other. The modules may or may not include a ground shield. As the transmission frequencies of signals through these connectors increase, it becomes more desirable to maintain a desired impedance through the connector to minimize signal degradation. A ground shield is sometimes provided on the module to reduce interference or crosstalk. In addition, a ground shield may be added to the ground contacts on the header connector. Improving connector performance and increasing contact density to increase signal carrying capacity without increasing the size of the connectors is challenging.
Some older connectors, which are still in use today, operate at speeds of one gigabit per second or less. By contrast, many of today's high performance connectors are capable of operating at speeds of up to ten gigabits or more per second. As would be expected, the higher performance connector also comes with a higher cost.
A need remains for a low cost differential connector with improved electrical characteristics such as reduced crosstalk and increased throughput.


A seat for a motor vehicle includes a seat bottom having a seat cover, an upholstery and a support structure, and a seat back having a seat cover, an upholstery and a support structure. Two lateral support parts are fastened to a front section of the support structure of the seat back for increasing the lateral support of an occupant on the seat. The lateral support parts are fastened to the support structure of the seat back.

Motor vehicles include a body defining an interior occupant compartment and seats arranged within the interior. Front seats include a seat part or seat bottom and a back part or seat back. The seat back can be pivoted around a swivel axis. Rear seats are arranged behind the front seats within the interior of the motor vehicle. The seat back of the front seats includes a support structure, which is fastened to or rests against an upholstery and a seat cover. In order to increase the lateral support far the seats, in particular for the front seats, lateral support parts in the form of a U-shaped frame or U-shaped strut made out of metal can be fastened to the support structure of the seat back by means of a welded joint. Such lateral support parts fastened to the support structure, in particular to vertical struts of the support structure of the seat back, increase the lateral support for individuals on the seat during cornering maneuvers and exposure to resultant lateral accelerations. Seats, in particular front seats, with the additional lateral support parts, are also referred to as sports seats. The vertical struts and U-shaped lateral support parts are joined together by means of a welded joint. A larger opening is present between the bracket- or U-shaped lateral support parts and the vertical struts of the support structure of the seat back. In the process of manufacturing the seat, the lateral support parts made out of metal are to be joined with seat by means of a welded joint in an initial phase of the manufacturing process. Seats with and without lateral support parts are here fabricated. Because the lateral support parts are already fastened by means of the welded joint in the initial phase of manufacturing the seat, an expensive warehousing of the seats both with and without lateral support parts is required, thereby increasing the costs for manufacturing the seats. Manufacturing the lateral support parts as U-shaped struts made out of metal is expensive, and the welded joint is also cost-intensive to fabricate.


An automated loan underwriting system and method automates the logic implemented by a loan underwriter, saving the loan originator time and money. Each lending institution can set up its own decisioning criteria, enabling customers to customize the process in which a proper evaluation, owners and encumbrance report, or title product is selected for a loan application within a given set of characteristics. The system and method allow for the automatic upgrading to another product without involvement of the loan processor, helping to reduce time delays in the loan origination process. The speed and automation allow for more underwriting checks to be applied against each loan.

The process of applying for a loan, such as a mortgage loan, can be time consuming and costly. Moreover, each loan underwriter may have its own decisioning criteria resulting in nonuniformity in the decision making process both universally and within any particular loan originator.
There are two basic types of processes that have been used by loan processors. These are a manual process of decisioning logic and a partially automated process for decisioning logic.
In the first conventional process, a lending institution has pre-established rules for underwriting product selection. Loan processors handle each application manually. When a loan request is received from a borrower it sits in queue until the loan processor gets to it. The loan processor manually interprets the decisioning logic established by the lending institution to determine the appropriate products to be ordered. The loan processor then generates a request for an automated valuation model (AVM) or a manual product such as a drive by valuation or a full appraisal. When the completed product is returned to the loan processor, usually via fax or electronically, it again sits in queue until it gets to the top of the list. At that point, the product is reviewed against underwriting guidelines. If the lender requires an additional or supplemental product, the lender sends the request back to the vendor and the process repeats.
The manual process can be problematic from an efficiency and accuracy standpoint. Time delays are inherent in the process. Time is wasted every time the loan application or product work sits in queue until the loan processor is able to handle it. Other time delays occur when the borrower is deciding whether or not to order a supplemental or additional product. Since that decision involves a manual review, more time elapses than is necessary.
Moreover, there is not certainty that the loan processor will use or interpret the lending institution's logic correctly. A mistake of this kind may go unchecked, and the product that the lending institution decided should be ordered might not be the product that is actually ordered. A loan processor may intentionally decide to break company policy and choose whichever product seems appropriate at the time, regardless of the lending institutions established rules and risk guidelines. These problems result in wasted time and money, and increase the amount of time between when the application is made and closing of the loan. These problems can also expose the lender to greater risk based on inaccurate underwriting decisions being made.
The second type of process automates some of the decisioning logic. In these types of systems, the lending institution automates a part of the product ordering process. For instance, a loan processor might have the ability to input just a few of the elements of information about the borrower or property into an automated decisioning logic system. This information might include credit tier, geographic location and loan amount. When the loan processor enters this information the system returns the name of a product, or perhaps the names of several products, which then have to be sorted through manually by the loan processor. Thereafter, the loan processor must order the product by sending the information to an AVM vendor or a vendor in the field for a manual product. While the second type of process is more advanced, and decreases the inaccuracies, it still may have problems. Only a few determinates are used to determine the appropriate products to order. This system does not allow for more specific differences between properties that might aid in determining product selection. Also, recent changes to lenders risk policy may not have been received by the underwriting.
The present invention is directed to solving one or more of the problems discussed above, in a novel and simple manner.


A method for identifying a selected playing ball from a prescribed number of playing balls, wherein each of the playing balls is provided with a different symbol, wherein: a) the selected playing ball is moved from a starting position past an image recording unit pickup, b) the mass center of the depiction of the selected playing ball in the image is kept unaltered for a prescribed, c) the image position and size of the depiction of the playing ball is ascertained, and a check is performed to determine whether portions of the depiction of the playing ball are situated outside a lateral of the image, and d) if portions of the depiction of the playing ball are situated outside said lateral edge, the playing ball is returned to the pickup area of the image recording unit and/or is repositioned and steps b) to d) are repeated.

The background of the invention is the automated detection of playing balls after they have been selected or drawn from a prescribed number of playing balls. To allow them to be played, typical games with playing balls to be drawn, such as for example lotto, bingo, etc., require an automatic gaming machine, by which an objective generation of random numbers is ensured. For the player, the randomness of the result of the game should be clearly evident, in particular the player should be given the feeling that the drawing is carried out without any manipulations to his or her detriment. For this reason, gaming machines which, in addition to the automated drawing of playing balls, also perform an automated identification of the playing balls, are used in the prior art.
The prior art discloses many different procedures in which the playing balls are provided with transponder chips and the identification is performed by way of RFID. Other systems use barcodes for identifying the playing balls. Yet other systems use cameras and special algorithms in order to identify the symbols printed or stamped on the playing balls.
What is problematic about all these methods is that the positioning of the balls for being recorded by the camera must take place very precisely, in order to achieve a clear identification of the symbols depicted on the balls.
The invention therefore addresses the problem of improving the identification or an identification of the balls and providing a method and an apparatus with which the detection of the balls is improved and is less susceptible to errors.
The invention solves the problem in the case of a method of the type mentioned at the beginning by the features of the characterizing part of patent claim 1.
The invention solves this problem in the case of an apparatus of the type mentioned at the beginning by the features of the characterizing part of patent claim 9.

Method and apparatus for identifying symbol bearing gaming balls


Embodiments of a method and system for improved microbiome sequencing can include: generating guide RNA complexes for a set of targets corresponding to a set of taxa associated with the microorganism-related condition; processing the biological sample with the gRNA complexes to generate microorganism nucleic acid fragments comprising a set of end regions associated with the set of targets; ligating the set of end regions with a set of adapters sharing an adapter sequence; and amplifying the set of targets based on the ligated set of end regions and a set of primers sharing a primer sequence associated with the adapter sequence.

Processes involving identification, amplification and analysis of nucleic acid targets within a sample can be used for sample characterization and/or diagnostic testing in research or clinical environments. Identification, detection, amplification, and analysis of multiple nucleic acid targets are thus particularly useful in characterizing multiple sample components and or enabling diagnostics associated with multiple targets (e.g., health condition biomarkers). Current methods and systems for multiplexed amplification, detection, sequencing, and/or analysis of multiple nucleic acid targets in a high throughput manner are, however, subject to limitations in terms of fragment assembly and sequence identification, especially in the context of highly polymorphic sequences.
Sequencing of multiple targets, in particular, is also typically limited by the number of reactions that can be performed within a single system (e.g., process chamber), downstream assembly, and interference factors associated with multiplexed reactions. Furthermore, current methods of multiplex sample processing are time consuming, labor intensive, and can be prohibitively expensive to implement.
As such, there is a need in the field of molecular diagnostics for a new and useful method and system for CRISPR-based library preparation and sequencing. This invention creates such a new and useful method and system.

Method and system for CRISPR-based library preparation and sequencing


Disclosed herein are representative embodiments of methods, systems, and apparatus for performing synthesis. For example, in one exemplary method disclosed herein, a high-level description of a complete circuit design is partitioned into a plurality of sections. Two or more synthesis engine configurations are selected for a respective one of the sections. The respective one of the sections is synthesized using the two or more selected synthesis engine configurations, thereby generating two or more gate-level descriptions. A gate-level description of the complete circuit design is generated that includes at least a portion of one of the gate-level descriptions. Computer-readable media storing instructions for causing a computer to perform any of the disclosed methods are also disclosed herein.

The design of complex circuits no longer begins with a circuit diagram. Instead, a circuit designer typically will start with a high-level description or representation of the logic functions required for a new circuit. These logic function definitions will often be described using a hardware description language ("HDL") (e.g., a SystemVerilog, Verilog, VHDL, or other register-transfer level ("RTL") description) or even using an algorithmic description (e.g., a C++, SystemC, or other algorithmic description). The designer will then use this functional description to generate a lower-level description or representation of the circuit that describes how the desired functionality is to be implemented. This lower-level representation is typically a gate-level netlist, such as a mapped netlist. Furthermore, the mapped netlist may then be placed and routed, thereby generating a placed and routed netlist. If the design is to be implemented by one or more field programmable gate arrays ("FPGAs"), the placed and routed netlist can then be transformed into one or more binary configuration files suitable for programming the FPGAs.
In general, the process of generating a lower-level circuit description or representation (such as a gate-level netlist) from a high-level description of logic function (such as an RTL or algorithmic description) is referred to as "synthesis." Similarly, a software application used to generate a lower-level circuit description or representation from a high-level description of logic function is referred to as a "synthesis tool." Furthermore, when the design is to be implemented using one or more FPGAs, the synthesis process is referred to as "FPGA synthesis," and the synthesis tools for performing the synthesis are referred to as "FPGA synthesis tools."
An FPGA is a type of integrated circuit device that can be programmed by a user to perform a specific function after it has been manufactured. Because of their flexibility, FPGAs are employed for a wide variety of uses, including telecommunications, digital signal processing, and image and speech recognition. In addition to being employed in end-user products, many designers use FPGAs to emulate a proposed design for an application-specific integrated circuit ("ASIC"). The accuracy of the design can then be tested and verified using the FPGAs before the actual ASIC is manufactured. An FPGA device typically includes an array of configurable logic blocks, routing channels for interconnecting the configurable logic blocks, and programmable switch boxes for connecting the channels. Some FPGA devices also may include other specialized circuit structures, such as memory circuits, input/output logic circuits, and digital signal processor ("DSP") circuits. With this arrangement, a designer can program the configurable logic blocks and the switch blocks so as to configure the FPGA device to provide the desired functionality.
While a variety of synthesis tools have been available for many years, many of these tools still have some difficulty generating an efficient configuration of circuit components from high-level logic functions. For example, a recent article estimated that some FPGA synthesis tools produce circuit configurations that are 70 to 500 times larger than known synthesis solutions. See Richard Goering, "Huge FPGA Synthesis Gap Seen," EE Times (Feb. 20, 2006). Inefficient circuit configurations require more area of an FPGA, which in turn may lead to the need for more FPGA devices to implement desired functionality. Further, inefficient circuit configurations may inadvertently create timing problems for the implemented functionality. Similar problems exist for synthesis tools used to implement ASIC designs.
To address these problems, synthesis tool manufacturers continuously seek to develop algorithms that will improve the synthesis process. Due to the complexity and uniqueness of the synthesis algorithms, however, no single synthesis tool is likely to provide an optimal circuit configuration for every given HDL design. Instead, each synthesis tool typically will perform better than other synthesis tools in limited circumstances (e.g., for particular types or portions of circuit designs, or for FPGA synthesis targeting particular types of FPGA architectures).
Accordingly, there is a need for improved synthesis tools that can use multiple synthesis engine configurations (including synthesis engine configurations from different vendors) and can exploit the relative strengths of these various synthesis engine configurations during synthesis.

Synthesis using multiple synthesis engine configurations


Floor finishes are stripped or deep scrubbed using a floor stripper/cleaner composition containing sparingly water-soluble floor finish solvent; water; sulfonic acid, sulfate acid, phosphonic acid, phosphate acid or aromatic acid coupler in an amount sufficient to provide a homogenous aqueous liquid phase and no or low foaming during shaking; and sufficient organic amine so that the composition pH is about 2 to about 11.

Floor strippers are used to remove worn or discolored floor finishes from flooring substrates (e.g., vinyl composition tiles) so that a new finish may be applied. Floor scrub and recoat materials are used to carry out a procedure sometimes referred to as "deep scrubbing" so that a fresh layer of floor finish may be applied atop an existing floor finish. References relating to various stripping or cleaning agents (some of which are said to be floor strippers or floor cleaners) include U.S. Pat. No. 3,993,804 (McReady et al.) U.S. Pat. No. 4,187,191 (Simpson, Jr.), U.S. Pat. No. 5,080,831 (VanEenam '831), U.S. Pat. No. 5,342,551 (Ruckle), U.S. Pat. No. 5,419,848 (VanEenam '848), U.S. Pat. No. 5,637,559 (Koreltz et al.), U.S. Pat. No. 5,728,666 (Vitomar '666), U.S. Pat. No. 5,744,440 (Liu), U.S. Pat. No. 5,849,682 (VanEenam '682), U.S. Pat. No. 5,851,972 (Distaso et al.), U.S. Pat. No. 6,465,405 B1 (Vitomar '405), U.S. Pat. No. 6,544,942 B1 (Smith et al.), U.S. Pat. No. 6,583,101 B1 (Wiseth et al.) and U.S. Pat. No. 6,586,380 B2 (Marquis et al.), U.S. Patent Application Publication No. US 2003/0125226 A1 (Lewis), Published PCT Application Nos. WO 98/17734 (Brent International PLC) and WO 2004/090085 A1 (Vocfree, Inc.), Henkel Surface Technologies Technical Process Bulletin No. 238828 (Form Revised 4 Jun. 2001) and Benzyl Alcohol Paint Stripping, available on the Internet at http://p2library.nfesc.navy.mil/P2 Opportunity Handbook/5—9.html (Revision Date 8/03).

Floor stripper/cleaner containing organic acid-base pair


A system and method for image segmentation using statistical clustering with saddle point detection includes representation means for representing the image data in a joint space of dimension d=r+2 that includes two special coordinates, where r=1 for gray-scale images, r=3 for color images, and r>3 for multi-spectral images; partitioning means for partitioning the data set comprising a plurality of image data points into a plurality of statistically meaningful clusters by decomposing the data set by a mean shift based data decomposition; and characterization means for characterizing the statistical significance of at least one of a plurality of clusters of data points by selecting a cluster and computing the value of a statistical measure for the saddle point lying on the border of the selected cluster and having the highest density.

Data clustering as a problem in pattern recognition and statistics belongs to the class of unsupervised learning. It essentially involves the search through the data for observations that are similar enough to be grouped together. There is a large body of literature on this topic. Algorithms from graph theory, matrix factorization, deterministic annealing, scale space theory, and mixture models have all been used to delineate relevant structures within the input data.
However, the clustering task is inherently subjective. There is no accepted definition of the term "cluster" and any clustering algorithm will produce some partitions. Therefore, the ability to statistical characterize the decomposition and to assess the significance of the resulting number of clusters is an important aspect of the problem.
Approaches for estimating the number of clusters can be divided into global and local methods. The former evaluate some measure over the entire data set and optimize it as function of the number of clusters. The latter consider individual pairs of clusters and test whether they should be joined together. A general descriptions of methods used to estimate the number of clusters are provided in the literature, while one study conducts a Monte Carlo evaluation of 30 indices for cluster validation. These indices are typically functions of the "within" and "between" cluster distances and belong to the class of "internal" measures, in the sense that they are computed from the same observation used to create a partition. Consequently, their distribution is intractable and they are not suitable for hypothesis testing.
Thus, the majority of existing methods for estimating the validity of the decomposition do not attempt to perform a formal statistical procedure, but rather look for a clustering structure under which the statistic of interest is optimal, such as maximization or minimization of an objective function. Validation methods that do not suffer from this limitation were recently proposed, but are computationally expensive since they require simulating multiple datasets from the null distribution.

Image segmentation using statistical clustering with saddle point detection


A target tracking method applicable to a shooting device including a first shooting assembly and a second shooting assembly. The method includes calling the second shooting assembly to shoot an environment to obtain an image, performing target object recognition on the image to obtain a tracking position area of a target object to be tracked in the image, and adjusting a shooting attitude of the shooting device according to the tracking position area of the target object in the image to locate the target object in a shooting frame of the first shooting assembly.

Currently, target tracking generally includes performing target recognition on an image captured by a shooting device to determine a target object in the image, and adjusting a shooting attitude of the shooting device to keep the target object in a shooting frame of the shooting device, to realize tracking of the target object in a monitoring environment.
The tracking method used in current technologies is to perform the image recognition on the image shot by a visible light shooting device to determine the target object in the image, and adjust the shooting attitude of the visible light shooting device to keep the target object in the shooting frame of the visible light shooting device, to realize tracking of the target object by the visible light shooting device. Since the image captured by the visible light shooting device has rich feature information to facilitate an identification of the target object, the visible light shooting device can accurately track the target object. However, at present, the target object cannot or cannot accurately be recognized in the image output by certain types of shooting devices, and hence these types of shooting devices cannot or cannot accurately track the target object.

Target tracking method and device, movable platform, and storage medium


A preemptive reloading technique is employed in a test program generator. Initialized resources are reset with needed values by reloading instructions. The actual reloaded value is chosen later, when the instruction that actually needs the value is generated. The test program generator distances the reloading instruction from the instruction that actually needs the value, thus making it possible to avoid fixed test patterns and to generate interference-free test segments during design verification.

1. Field of the Invention
This invention relates generally to design verification, and more particularly to verification of a processor architecture of a computer system.
2. Description of the Related Art
An important aspect of designing an advanced computer processor is the ability to test the design of the processor thoroughly, in order to assure that the design complies with desired architectural, performance and design specifications. One known verification technique requires the generation of a large number of instruction sequences to assure that the processor behave properly under a wide variety of circumstances.
Test program generators are basically sophisticated software engines, which are used to create numerous test cases. By appropriate configuration, it is possible for test generation to be focused on very specific ranges of conditions, or broadened to cover a wide range of logic. Today, large numbers of test cases can be created automatically in the time that a single test case could be written manually, as was done prior to the advent of test case generators. Modern test program generators are sophisticated enough to evaluate the microarchitectural implementation of a processor.
Typically, the input to the test program generator is a user-defined sequence of partially specified instructions, known as an instruction stream, which acts as a template for the test to be generated. The instruction stream is generally incomplete, in that various details of each instruction, such as the specific source and the target resources to be used, the data values of each uninitialized resource, and even the exact instruction to be generated, may be left unspecified. The test program generator then generates a complete test by filling in the missing information with random values. The choice of random values is often biased, so as to increase the likelihood of detecting a design flaw. The use of templates in this manner allows the creation of numerous test cases that stress the implementation of the logic, creating various conditions such as "buffer full", or "pipe stall".
An example of a conventional test program generator is the IBM tool, Genesys, which is disclosed in the document Model-Based Test Generation for Process Design Verification, Y. Lichtenstein et. al., Sixth Innovative Applications of Artificial Intelligence Conference, August 1994, pp. 83–94. An updated version, of Genesys, known as Genesys-Pro, is a generic random test generator, targeted at the architectural level and applicable to any architecture.
Another conventional test program generator, AVPGEN, is disclosed in the document AVPGEN—A Generator for Architecture Verification Test Cases, A. Chandra, et al., IEEE Trans. Very Large Scale Integration (VLSI) Syst. 3, No. 2, pp. 188–200 (June 1995).
Still another test generator is disclosed in the publication B. O'Krafka, et al., "MPTG: A Portable Test Generator for Cache-Coherent Multiprocessors", International Conference on Computers and Communications, 1995, pp. 38–44. This generator is capable of generating tests that include scenarios with unpredictable results and relies on checks carried out for intermediate points in the test.
Test program generation typically involves the resolution of constraints to make the tests legal and interesting for verification. This is often achieved through the values of resources that are used by the instructions in the test. A difficulty is that the number of available resources is limited, and there may be fewer available resources than needed values, especially in long tests.
Commonly, the process of generating an instruction in a test includes the selection of the resources used by the instruction and the initialization of any uninitialized resource with some desired value. Constraints may also be placed on the value of instruction resources. Some of these constraints are imposed by the definition of the instruction itself, while others may have been requested by the user. The value contained in a resource significantly impacts the ability of the generator to satisfy these constraints, and as a result, the quality or legality of the test generated.
All processors contain resource families bounded in the number of elements they contain. For example, a processor may have only 32 floating point registers. Once a resource is initialized, its value is determined solely by instructions that cause its modification. After all the registers in the family have been used, generating any instruction that requires an element from this family becomes harder because the selection of data for the resources is restricted to their current values. These restricted values often prevent certain constraints from being satisfied when generating a new instruction. As a result, either the instruction generation fails or the generated instruction does not achieve its intended verification purpose. The problem becomes more acute when long tests need to be generated. Long tests are required to reach complex microarchitectural states, e.g., states in which there is high utilization of resources. Long tests are also desirable in order to test uncommon paths between states. Advantages of long tests are suggested in the document Short vs. Long: Size Does Make a Difference, A. Hartman, S. Ur, and A. Ziv, in IEEE International High Level Design Validation and Test Workshop (HLDVT), 1999. Long tests are shown to give better coverage of events that occur randomly, i.e., with no explicit intention of the generator, with a smaller total number of instructions than are used for a similar set of short tests.
Previous approaches to solving the problem of resource limitations are typified by the Genesys Test-Program generator described in the document Test Program Generation for Functional Verification of PowerPC Processors in IBM, A. Aharon, D. Goodman, M. Levinger, Y. Lichtenstein, Y. Malka, C. Metzger, M. Molcho, and G. Shurek, in 32nd Design Automation Conference, pages 279–285, 1995, and by the Sysgen Test-Program generator referred to by the document A Methodology for the Verification of a 'System On A Chip', D. Geist, G. Biran, T. Arons, M. Slavkin, Y. Nustov, M. Farkas, K. Holtz, A. Long, D. King, and S. Barret, in 36th Design Automation Conference, pages 574–579, 1999. There it is proposed to inject unsolicited instructions into the test for the sole purpose of loading new values into a resource. These are called reloading instructions. In Genesys, when the generator generates an instruction that turns out to need some value in a register, then the generator generates the extra reloading instruction so as to immediately precede the client instruction. Sysgen solves the problem by generating fixed instruction stream patterns that include all the required reloading instructions followed by the client instructions. The major drawback to these approaches is that such interposed instructions interfere with the test. Indeed, the interference can spoil the scenario that the test was originally designed to check. In addition in the above mentioned two approaches interference caused by reloading instructions typically occurs in a fixed pattern.
Other possible approaches to obtain many values from a limited resource in the same test program may be considered. One of these involves the introduction of planning into the test generation process. For example, while generating an early instruction, the generator can look ahead in order to know what values would be needed later on. This knowledge can be regarded as an induced constraint, and can be taken into consideration at the time the early instruction is generated. Another possibility is to treat the entire test as a single problem of constraint satisfaction, and to coordinate all the values used and produced by all the instructions. The problem with both of these approaches is that the constraint problem becomes very large. In addition, the individual constraints themselves can be difficult to express and to solve, since they may be induced from intricate instruction semantics. Test generators that generate tests one instruction at a time, or one section at a time, as well as test generators that make use of planning are known to employ reloading techniques. However, conventional reloading approaches inject reloading instructions immediately before the client instruction, which causes interference, fixed instruction stream patterns and results in the neglect of many test patterns that could expose design flaws.

Test quality through resource reallocation


A computer program product is for use with a computer that includes a communication interface for sending and receiving information over a communication network and that is connected to an uninterruptible power supply (UPS) that monitors and supplies information regarding power status associated with the UPS. The computer program product resides on a computer-readable medium and includes computer-executable instructions for causing the computer to process data received from the UPS to which the computer is coupled to produce indicia of changes in power status associated with the UPS, provide the indicia of changes in power status associated with the UPS to the communication interface destined for a remote device, and provide geographic information associated with the indicia of changes in power status that indicates a geographic location associated with the UPS.

Today's companies and persons rely on having power more than ever before. Without power, companies may be unable to manufacture goods, or to operate at all, such as if the company is in the business of supplying information over the Internet. Without power, businesses and individuals may be completely incapacitated regarding critical activities, such as making goods, providing services, and transacting personal finances (e.g., filing tax returns, and paying bills).
With such a heavy reliance on power, individuals and companies frequently need to be able to have power outages corrected in short order, and/or have backup power supplies so that their affairs and/or businesses are not significantly affected. Correcting power outages typically involves calling a local power company to report a power outage and/or troubleshooting a local power supply/conveyance system, e.g., internal to a company or residence, that has gone out. Uninterruptible power supplies (UPSs) are often used to provide backup power in case of a power outage. UPSs are commonly used on computing equipment to guard against data being lost due to a power outage before the data are saved. UPSs used with computing equipment also help to guard against a loss in service by providers of information over the Internet, such as by servers, e.g., hosting web pages.