A support cushion has an elastic core having a first surface, a second surface and a thickness defined by the first surface and the second surface. A first cover portion substantially entirely encloses the elastic core. A pillow top surface is positioned adjacent the first surface of the elastic core. The pillow top surface includes a plurality of foam portions. A second cover portion at least partially covers the pillow top surface and the second cover portion attached to at least one of the first cover portion and the elastic core.

A typical cushion uses elastic foam material for suitably distributing pressure from the body over a relatively large surface area of the body being supported by the cushion, such as a person lying on a mattress, a person seated in a couch, or an animal resting on a veterinary surgeon's table.
When used in combination with some type of less elastic overlying layer, the elastic foam underlying layer in the cushion counteracts the deepest depressed parts in the overlying layer in order to provide an increased counter-pressure against the body. To achieve a reasonably limited cushion thickness, the underlying layer is typically arranged in the form of a highly-elastic foam layer or a spring base with mechanical springs to provide suitable support to the user.
Some conventional cushions have a "pillow top" surface or layer on top of or in place of the less elastic-overlying layer. In the mattress industry, conventional pillow top layers have been formed by inserting soft resilient filling materials into an enclosure that is interconnected with a top surface of a mattress core. Normally, when an innerspring coil mattress core is employed, the pillow top construction serves to essentially cushion the innerspring coils and to allow for more independent and unrestrained articulation resulting in improved conformability and interface pressure, thus improving overall comfort levels for a user of the mattress.


A process is provided for removing metal salt co-constituents from an iron-containing solution comprising: (a) decreasing the free acidity of the solution to produce a slurry; (b) optionally heating the solution or the slurry to a temperature at least 30° C.; (c) optionally aging the slurry; (d) adding one or more cationic polyelectrolyte flocculants to the slurry; and (e) separating a solid-containing portion from a liquid portion of the slurry.

Solutions of ferrous and ferric iron salts have well established utility in numerous scenarios in the treatment of potable water and wastewaters. Ferrous solutions can also be used as base material in the manufacture of ferric chloride solution products which have separate market values in potable water and wastewater treatment applications.
One of the major sources of these iron salt solutions, of both sulfate and chloride anion, is from the titanium dioxide (TiO2) manufacturing processes, wherein the use of various grades of ilmanite or rutile type ores produces iron salt side streams with varying amounts of metal salt co-constituents. These metal salt co-constituents can include salts of a variety of metals, including titanium, chromium, zirconium, niobium, manganese and other metals in relatively high concentrations. In the TiO2 industry, these iron solutions are generally disposed by neutralization, dewatering, and landfill, or deepwelled as hazardous waste. In some cases, the solutions are purified and sold as ferrous chloride or ferric chloride solution for wastewater and potable water treatment. However, the chlorides and hydroxychlorides of titanium, niobium, and zirconium in these solutions slowly precipitate as fine solids. As these fine precipitates accumulate they will cause problems in storage and handling of the solutions at the customers' sites as the fine precipitates settle and subsequently clog tanks, strainers, and pumping lines. This equipment then needs to be taken out of service for cleaning, incurring costs and interruption of service.
All methodologies, to date, have been relatively ineffectual or are very inefficient in preventing or removing these precipitates from the materials and the industry has learned to adjust to the issue but with significant cost. Accordingly, the marketable value of the iron solution to the water treating industry will generally be inversely proportionate to the levels of co-constituents carried in the solution. Therefore, there is value in discovering methods of reducing the levels of co-constituents in the iron solutions. Furthermore, these iron solutions are produced in concentrations that are too low to provide viable market access. It is therefore advantageous to determine beneficial methods of concentrating iron.
There exists a need for an improved process for separating impurities, including metal salt co-constituents such as niobium, titanium, zirconium and other metal salt co-constituents, from these iron chloride solutions, leaving a stable iron chloride solution that does not precipitate fine solids.

Process for the purification of iron salt solutions


DC/DC converter includes a voltage converting circuit connected between the input terminal and output terminal, a fast transient response circuit, a step-up and step-down operation determining circuit, a voltage comparator, and a switch control circuit.

FIG. 11 is a block diagram of a conventional step-down type DC/DC converter used in a handy phone. As shown in FIG. 11, a series circuit of first switch circuit 100, inductor 102, and smoothing capacitor 104 is connected between input terminal 111 and output terminal 112. Output voltage 120 from the smoothing capacitor 104 and control voltage 121 from output voltage control terminal 113 are put into comparator 105. Output signal from this comparator 105 and output signal from oscillation circuit 106 are put into switch condition determining circuit 107. Output voltage 120 and switch current detection signal 122 from the first switch circuit 100 are put into control operation determining circuit 110, and the control operation determining circuit 110 judges the load, and feeds its output signal 123 into the oscillation circuit 106 and switch control circuit 108. The switch control circuit 108 receives the output of the switch condition determining circuit 107 and output signal 123 of the control operation determining circuit 110. Thus, the switch control circuit 108 supplies a signal for controlling the first switch circuit 100 to the first switch circuit 100. Feedback is composed in this manner.
Such prior art is disclosed, for example, in Japanese Laid-open Patent No. H7-322608.
In this conventional step-down type DC/DC converter, however, transient response time is long when lowering the voltage in step-down process of output voltage, and the output voltage cannot be lowered in a short time. As a result, power loss occurs during transient response time, and the battery voltage is decreased, and it is hard to extend the call time.
The conventional step-down DC/DC converter operates only in step-down process. That is, the conventional DC/DC converter cannot be used in step-up operation. Further, the conventional DC/DC converter is slow in response speed in transient response depending on the load situation, and wasteful power consumption occurs.

Voltage step-up and step-down DC/DC converter

Matsushita Electric Industrial Co., Ltd.


A new and distinct cultivar of Gerbera plant named `Terkarola`, characterized by its semi-double type, a distinctive orange ray floret which is a solid orange throughout, a red-purple disc floret the outermost petaloids of which fade to orange and display yellow stigmas and anthers, orange perianth lobe color and 110 mm overall flower diamter is disclosed.

The present invention comprises a new and distinct cultivar of Gerbera jamesonni, referred to by the cultivar name `Terkarola`. `Terkarola` was originated from a hybridisation program in De Kwakel, The Netherlands in 1984. The female parent was unnamed seedling 83.1, and the male parent was unnamed seedling 81.178. Female parent 83.1 has a higher and earlier production, less petals and a lower overall flower quality, shorter stems, and a red black center. Of the male parent 81.178 is no description available. Both have not been available outside Terra Nigra and aren't registered in the USA. The new cultivar was selected by me from the progeny of the stated parentage on or about November 1984. The first asexual reproduction of `Terkarola` was accomplished when vegetative cuttings were taken on May 1985 in De Kwakel. The new cultivar is presently being propagated by cuttings and tissue culture. Horticultural examination of selected units initiated November 1986 has demonstrated that the combination of characteristics as herein disclosed for `Terkarola` are firmly fixed and are retained through successive generations of asexual reproduction.
The following observations, measurements and comparisons describe plants grown in De Kwakel, The Netherlands, under greenhouse conditions which closely approximate those generally used in commercial practice. The following traits have been repeatedly observed and are determined to be basic characteristics of `Terkarola`, which in combination distinguish this Gerbera from its parents and all other varieties of which I am aware:
1. Type: Semi-double. PA0 2. Color of ray floret: Distinctive orange. PA0 3. Color of disc floret: Red-purple. PA0 4. Color of perianthy lobe: Orange. PA0 5. Diameter of flower head: Medium 110 mm.
Of the many commercial cultivars known to me, there is no cultivar similar in comparison to `Terkarola`. The patent plant `Terikatir` (U.S. Plant Pat. No. 7,984) appears to be similar to "Terkarola`. However, `Terikatir` is a Germini type with a diameter of 6.5 cm, has a dark yellow color, with an average flower production of 55 per plant, whereas `Terkarola` has a flower diameter of 11-12 cm, a distinctive orange color, and an average flower production of 25 per plant.


Particle removal structure is employed with a scribing tool to remove particles from the surface of a semiconductor wafer being scribed and transport the particles to another location.

In the very early days of semiconductor device fabrication, the individual devices were separated from the other devices fabricated on the wafer by using the dicing process of scribing and breaking. The scribing process was carried out using a sharp-tipped diamond tool and initially done by hand. Later, automatic scribing machines such as those described in U.S. Pat. Nos. 3,094,785 and 5,820,006 were developed. These scribing machines provided a way to precisely position the diamond scribe tip as it traversed the width of the wafer and created the scribe line. This is necessary because the scribe line must stay within the scribe street that can be as narrow as 50 microns in width. Problems were observed with these scribe machines when hard semiconductor materials such as silicon were scribed. The diamond tips used in the machines would wear down quickly and have to be changed frequently at some expense. A new technology developed to dice these hard semiconductor materials using very thin saw blades made up of diamond particles embedded in a metal or resin matrix. Most silicon devices are currently diced using this sawing technology. The fact that the saw blade requires a wider scribe street due the width of the blade was generally not considered a problem, as silicon material is not too costly to produce. At this time, scribing with a sharp-tipped diamond tool is used primarily in niche applications in which the material is relatively soft so as not to cause a problem with diamond scribe tool life and in which the material is relatively expensive to produce. The materials that fit these criteria are generally compound semiconductors like gallium arsenide and indium phosphide.
For many decades, scribing and breaking of glass has been done using a wheel fabricated of steel or tungsten carbide. This wheel has an angle formed along its periphery that is pressed into the glass as it rolls along to create the scribe line. In the assembly of the scribe tool, the scribing wheel is mounted on an axle through a hole in its center. Then the axle and scribing wheel are placed in a tool body with holes on both sides to support the axle. The scribe tool is typically placed in a glass scribing machine similar to the one described in U.S. Pat. No. 4,221,150. In a glass scribing tool there are at least 50 to 100 microns clearance between the sides of the scribe of the scribe wheel and the inside of the yoke to allow the scribe wheel to turn freely. Therefore, when the scribe wheel tool traverses the glass to form the scribe line, the scribe wheel can move laterally back and forth between the inside edges of the yoke. This causes the scribe line to vary from a straight line by 50 to 100 microns. In glass scribing this variation is not considered a problem because the size of the scribed glass does not need to be held to any tighter tolerances.
In certain new types of semiconductor devices made out of silicon materials, the use of saws to dice wafers has proven to be unsatisfactory. In MEMS devices, the debris created by the sawing processing can prevent the mechanisms from operating properly. In very thin integrated circuits, such as those used in smart cards, the protruding diamond particles in the blade can cause chipping and fracturing of the device die. In trying to develop a process to dice these devices, conventional scribing using a sharp-tipped diamond tool was tried. While this approach solved the problem with debris and reduced chipping and fracturing, short diamond tool life when scribing a hard material like silicon is still a problem.
The purpose of the invention of above-identified application Ser. No. 11/041,841 is to achieve longer tool life, while maintaining the advantages of scribing over sawing in certain applications. The invention encompasses a new scribing tool and a new method of scribing semiconductor wafers employing the tool.
The scribing tool of above-identified application Ser. No. 11/041,841 is for use in semiconductor scribing apparatus for dicing semiconductor wafers. The scribing tool includes a tool body for movement relative to a semiconductor wafer, the tool body having a yoke with yoke legs defining a space therebetween.
A semiconductor wafer scribing wheel is located in the space having opposed scribing wheel sides an outer peripheral angularly disposed, converging scribed surfaces extending outwardly from the sides engageable with the semiconductor wafer to form scribed lines therein when the tool moves relative to the semiconductor wafer and exerts pressure thereon. The semiconductor wafer scribing wheel defines a central opening extending between the opposed scribing wheel sides.
An axle passes through the central opening and projects from the opposed scribing wheel sides, the axle cooperable with the yoke legs to rotatably support the semiconductor wafer scribing wheel within the space whereby the semiconductor wafer scribing wheel rotates when in engagement with the semiconductor wafer and the tool moves relative thereto.
Bearings are engageable with the opposed scribing wheel sides to resist sideways deflection of the semiconductor wafer scribing wheel during rotational engagement thereof with the semiconductor wafer.
The method of above-identified application Ser. No. 11/041,841 includes the step of supporting a semiconductor wafer on a support.
A scribing tool is positioned above the supported semiconductor wafer, the scribing tool including a tool body having a yoke with yoke legs defining a space therebetween, a semiconductor wafer scribing wheel in the space and an axle having a longitudinal axis extending between the yoke legs and supporting the semiconductor wafer scribing wheel for rotation about a rotational axis coaxial with the longitudinal axis.
The method also includes the step of bringing the semiconductor wafer scribing wheel into engagement with the semiconductor wafer.
Pressure is exerted on the semiconductor wafer with the semiconductor wafer scribing wheel.
While maintaining the pressure on the semiconductor wafer with the semiconductor wafer scribing wheel, relative movement is caused between the scribing tool and the semiconductor wafer to move the semiconductor wafer scribing wheel across a surface of the semiconductor wafer while rotating the semiconductor wafer scribing wheel about the rotational axis to form a scribe line in the semiconductor wafer.
During any dicing process of semiconductor wafers or similar substrates, including the process disclosed in application Ser. No. 11/041,841, small particles of the substrate material are sometimes created by the dicing tool cutting into the material of the substrate. In some types of devices these particles can cause problems in the functioning of the devices fabricated on the substrate. For example, MEMS devices may have intricate mechanisms fabricated on the surface of the substrate. Particles of material from the substrate can get into the mechanisms and prevent them from operating properly. Once particles are deposited on the surface of the substrate they may be held in place by static electricity and can be very difficult to remove without damaging the devices.


Provided is a computer system capable of identifying a seat position of a user even in a network to which an individually-assigned device and a device used by a plurality of users are connected coexistently. The computer system for identifying a seat position of a user, includes: a device used by the user; a network device to which the device is connected, for coupling the device to a network; and a management computer coupled to the network. In the computer system, the management computer judges which of an individually-assigned device and a shared-use device the device connected to the network device is, obtains a unique identifier of the user and information indicating a connection relationship between the network device and the device connected to the network device from the network device, and identifies the seat position of the user based on the unique identifier of the user and the information indicating the connection relationship.

This invention relates to a computer system for identifying a seat position of a user who uses a device, and more particularly, to a computer system for identifying a seat position of a user of a device used by a plurality of users.
In recent years, ongoing measures for reducing office costs include introduction of a "free-address office" in which a plurality of employees share seats in an office instead of being assigned with fixed seats. This allows remarkable reduction of spaces within the office particularly in a section with those who are often away on business, which leads to the reduction of the office costs. Other expected effects of the free-address office include prevention of accumulation of unnecessary documents because there is no fixed seat provided in the office.
However, when there is no fixed seat provided in the office, it is impossible to identify a seat position of the employee. This creates the need for confirming whether or not the employee is seated somewhere in the office and identifying where a given employee is seated in a case where a face-to-face conversation with the given employee is intended. To meet the need, there are proposed systems for identifying the seat position of an employee and displaying the seat position.
To be specific, as disclosed in JP 08-195769 A, there is known a technique in which such a database that a correspondence relationship between a MAC address of a device connected to a network line concentrator and a user ID of a user who uses the device is previously registered is used to identify a position of the user by identifying the user ID of the user who uses the device based on the MAC address of the device when the device is connected to a network.
However, the conventional technique has a problem in that a device and users do not correspond to each other on a one-to-one basis in a case where a single device is shared by a plurality of users through user authentication or the like. Thus, it is impossible to create such a database that a one-to-one correspondence relationship between the MAC address of the single device and the user IDs of the plurality of users who use the device is previously registered. Accordingly, the seat position of the user cannot be identified in a computer system including a device used by a plurality of users.
In addition, management costs increase in the case where the correspondence relationship between the MAC address of the device and the user ID of the user of the device is previously registered in the database.

Computer system and management computer for identifying seat position


A shift register, a gate driving circuit and a gate driving method are provided. The shift register includes: a display pre-charging reset circuit, a display noise reduction circuit and an output circuit, the output circuit is provided with at least one signal output terminal, and includes at least one output sub-circuit; the display pre-charging reset circuit is configured to write a first scanning voltage into a pull-up node in response to a control of a first signal input terminal; and write a second scanning voltage into the pull-up node in response to a control of a second signal input terminal; the display noise reduction circuit is configured to write the second scanning voltage into a pull-down node in response to the control of the first signal input terminal; and write the first scanning voltage into the pull-down node in response to the control of the second signal input terminal.

In the related art, transistors are integrated on an array substrate by using a Gate Driver on Array (GOA) technology, so as to scan and drive gate lines in a display panel, and thus a Gate Driver IC can be omitted, which facilitates to implement a narrow bezel.
For a display panel with an external compensation function, each gate driving element in a gate driving circuit (including a plurality of gate driving elements cascaded) is required to not only output a driving signal for controlling a display switch transistor to be turned on in a display driving stage, but also output a driving signal for controlling a sensing switch transistor to be turned on in a sensing stage, that is, the gate driving element is required to have a function of outputting a double pulse signal. However, since a shift register in the related art can output only a single pulse signal, a case where one gate driving element includes only one shift register cannot satisfy driving requirements.
In order to solve the above technical problem, in the related art, two shift registers and a signal combining circuit are often used to form a gate driving element, and the gate driving element has a function of outputting a double pulse signal. However, for a design that the gate driving element includes two shift registers and one signal combining circuit, the number of transistors required to be arranged is relatively large, which is not favorable for implementing a narrow bezel.

Shift register, gate driving circuit, display device and gate driving method

BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.


An interface apparatus for transferring substrates between processing apparatus which provide various treatments for the substrates. The interface apparatus includes a transfer mechanism which, during a normal operation, receives substrates from an upstream processing apparatus and delivers the substrates to a downstream processing apparatus. Upon occurrence of a trouble in the downstream processing apparatus, the substrates transported from the upstream processing apparatus to the transfer mechanism are deposited in a substrate storage by a depositing and fetching mechanism. After the trouble is eliminated, the transfer mechanism delivers the substrates taken out of the storage to the downstream processing apparatus.

(1) Field of the Invention
The present invention relates to an interface apparatus for transporting substrates between substrate processing apparatus that successively carry out processing, including photoresist application, exposure, development and etching, of various types of substrates such as semiconductor wafers and glass substrates for liquid crystal displays.
(2) Description of the Related Art
Several types of processing apparatus are arranged serially to form a required processing line. These apparatus include an application processing apparatus for applying photoresist to the substrates, an exposure apparatus for exposing the substrates with the photoresist applied thereto, and a developing apparatus for developing the exposed substrates.
Each of these processing apparatus includes a single processing unit or a plurality of processing units. The application processing unit, for example, includes a contact promoting unit for causing vapor of a resist contact promoting agent to contact substrate surfaces, a rotary coating unit, a heating unit, and a cooling unit for reducing substrate temperature to room temperature. Each processing apparatus also includes a substrate transport mechanism having a movable arm for carrying the substrates, with the various processing units arranged around the transport mechanism.
The substrates are transported from one processing apparatus to another by an interface apparatus disposed therebetween. In this transportation, the substrates are once transferred from the substrate transport mechanism of one processing apparatus to the interface apparatus. Subsequently, the substrate transport mechanism of the next processing apparatus receives the substrates from the interface apparatus.
The known system as constructed above has the following disadvantage.
When the processing apparatus that receives the substrates (hereinafter referred to as a downstream apparatus) becomes inoperable owing to some trouble, the interface apparatus cannot dispose of the substrates. Consequently, the processing apparatus that gives the substrates (hereinafter referred to as an upstream apparatus) must also stop operating. All the processing must be suspended until the trouble is eliminated, which results in a low operating efficiency of the processing apparatus.

Interface apparatus for transporting substrates between substrate processing apparatus


A medical device system includes an elongated body with a distal end that is configured and arranged for insertion into a patient. A housing is disposed in the distal end of the body. A rotatable magnet is disposed in the housing. At least one magnetic field winding is configured and arranged to generate a magnetic field at the location of the magnet. The magnetic field causes rotation of the magnet at a target frequency. An array of magnetic field sensors is disposed external to the patient. The magnetic field sensors are configured and arranged to sense the location and orientation of the magnet in relation to the array of magnetic field sensors.

Medical devices that are insertable into patients, such as imaging pills and catheters have proven diagnostic and therapeutic capabilities. Some medical devices are designed to perform one or more functions at one or more locations within a patient's body. Position and orientation systems may be used to determine the location of the medical device within the patient.

Systems and methods for determining the position and orientation of medical devices inserted into a patient


A semiconductor device including a semiconductor substrate having a main surface, an insulating layer formed on the main surface of the semiconductor substrate, and lower electrode film embedded in the insulating layer. A dielectric film embedded in the insulating layer covers the lower electrode film. An upper electrode film is embedded in the insulating layer and is opposed to the lower electrode film through the dielectric film. A conductor plug electrically connects the lower electrode film and the semiconductor substrate with each other through a lower contact hole selectively formed in the insulating layer. A conductor layer is embedded in the insulating layer and is electrically connected to the upper electrode film on a first portion defining a part of the upper surface of the conductor layer. A wire arranged on the insulating layer is connected to a second portion defining another part, different from the first portion, of the upper surface of the conductor layer through an upper contact hole selectively formed in the insulating layer.

1. Field of the Invention
The present invention relates to a semiconductor device suitable for a DRAM (dynamic random access memory) having a capacitor (capacitive element): employing a high dielectric film or an SRAM (static random access memory) having a capacitor employing a ferroelectric film and a method of manufacturing the same.
2. Description of the Background Art
First, a term employed in this specification is described. Throughout the specification, the term xe2x80x9cnoble metalxe2x80x9d stands for a metal belonging to a group consisting of gold, silver and the platinum metals (Ru, Rh, Pd, Os, Ir and Pt).
A DRAM is generally known as a semiconductor memory device capable of inputting/outputting stored information at random. In general, such a DRAM has a memory cell array serving as a storage area storing numerous information and a peripheral circuit necessary for inputting/outputting the information from/to an external device. A group of memory cells is arranged on the memory cell array, occupying a large area in a semiconductor chip, in the form of a matrix.
A known memory cell for storing unitary memory information has a single MOS (metal oxide semiconductor) transistor and a single capacitor connected thereto. Such a memory cell is referred to as a one-transistor one-capacitor memory cell. This type of memory cell having a simple structure can readily improve the degree of integration of the memory cell array, and is hence widely employed in a DRAM having a large capacity.
Memory cells of the DRAM are classified into some types depending on capacitor structures. A known capacitor is referred to as a stacked capacitor. A principal part of the stacked capacitor is extended onto a gate electrode or a field oxide film, thereby ensuring a large facing area between electrodes.
Due to the aforementioned characteristic, the stacked capacitor can ensure a high capacitance also when elements are refined following integration of the semiconductor memory device. Therefore, the stacked capacitor is increasingly employed following integration of the semiconductor memory device.
However, the stacked capacitor must be more highly formed over a semiconductor substrate in response to refinement of the elements. Following the recent progress of refinement of the elements, it is now becoming difficult to ensure the capacitance required to the capacitor by this method. This also applies to a trench capacitor or a cylindrical capacitor, which is another representative three-dimensional capacitor structure.
Therefore, an attempt of employing a dielectric film consisting of a high dielectric constant material such as BST (barium strontium titanate) as a capacitor dielectric film is made in order to increase the capacitance of the capacitor. FIG. 28 is a sectional view partially showing a memory cell of a DRAM 150 employing a high dielectric constant material such as BST as a capacitor dielectric film. This semiconductor device 150 comprises a semiconductor substrate 1, a lower insulating layer 2, a conductor plug 3, a barrier metal layer 5, a lower electrode film 6, side walls 7, a dielectric film 8, an upper electrode film 9, an upper insulating layer 11, a,barrier metal layer 60 and a wire 20. Platinum is employed as the material for the lower electrode film 6 and the upper electrode film 9, and titanium nitride is employed as the material for the barrier metal layers 5 and 60. The dielectric film 8 is formed as a BST dielectric film, and the wire 20 is an aluminum wire. The lower insulating layer 2 and the upper insulating layer 11 are formed as interlayer isolation films.
The semiconductor device 150 is characteristically different from any preceding DRAM in that not polycrystalline silicon but a noble metal such as platinum is employed as the material for a capacitor electrode film of a memory cell. In the DRAM preceding the semiconductor device 150, a silicon oxide film obtained by thermally oxidizing silicon or a silicon nitride film formed by CVD (chemical vapor deposition) is employed as the capacitor dielectric film. Both of silicon oxide and silicon nitride are compounds of silicon, and hence the capacitor dielectric film can be readily formed on a lower electrode film prepared from polycrystalline silicon.
When a dielectric film consisting of a high dielectric constant material such as BST (barium strontium titanate) is formed on a polycrystalline silicon film, however, the electrochemically base polycrystalline silicon film is so readily oxidized that a silicon oxide film is formed on the interface between the dielectric film of BST and the lower electrode film of polycrystalline silicon. This silicon oxide film remarkably reduces electrostatic capacitance of the capacitor due to its low dielectric constant.
In order to prevent this, a noble metal such as electrochemically noble platinum having high oxidation resistance is employed for the upper electrode film 6 and the lower electrode film 9 in the semiconductor device 150. Further, the conductive barrier metal layers (anti-diffusion films) 5 and 60 are interposed on the interfaces between the upper and lower electrode films 6 and 9 and the conductive materials mainly composed of silicon and aluminum, which are electrically connected with the electrode films 6 and 9, for preventing mutual diffusion between silicon and platinum and between aluminum and platinum.
In a process of manufacturing the semiconductor device 150, the upper insulating layer 11 covering the upper electrode film 9 consisting of a noble metal such as platinum must be etched for forming a contact hole 61 and electrically connecting the upper electrode film 9 and the wire 20 with each other through this contact hole 61. In this etching step, however, it is disadvantageously difficult to precisely control etching conditions so that the etching is stopped when the upper surface of the thinly formed upper electrode film 9 is exposed not to cause over-etching. Further, a re-deposition film 12 consisting of a component of a resist film and platinum is disadvantageously formed around the bottom portion of the contact hole 61. The re-deposition film 12 consisting of the component of the resist film and platinum, which is chemically stable and adheres to a portion of the inner wall surface of the contact hole 61 around the bottom portion, is hard to remove. The re-deposition film 12 increases contact resistance.
In order to solve the aforementioned problems, it is possible to assume a capacitor structure obtained by forming an etching stopper layer (not shown) on the upper surface of the upper electrode film 9. When the etching stopper layer is thickly set to a necessary degree in this structure, however, the effective capacitor height is increased. Consequently, an absolute step is disadvantageously increased between a memory cell array having the capacitor and a peripheral circuit having no capacitor. When the material for the upper electrode film 9 is patterned for forming the upper electrode film 9, further, a composite film of a three-layer structure including the etching stopper layer and the dielectric film 8 must be etched. Consequently, the upper electrode film 9 cannot be readily finely worked.
Thus, an object of the present invention is to provide a semiconductor device capable of preventing over-etching in formation of a contact hole and preventing formation of a re-deposition film without providing an etching stopper layer and a method of manufacturing the same.
A semiconductor device according to a first aspect of the present invention comprises a semiconductor substrate having a main surface, an insulating layer formed on the main surface of the semiconductor substrate, a lower electrode film embedded in the insulating layer, a dielectric film embedded in the insulating layer and covering the lower electrode film, an upper electrode film embedded in the insulating layer and opposed to the lower electrode film through the dielectric film, a conductor plug electrically connecting the lower electrode film and the semiconductor substrate with each other through a lower contact hole selectively formed in the insulating layer, a conductor layer embedded in the insulating layer and electrically connected to the upper electrode film on a first portion defining a part of its upper surface and a wire arranged on the insulating layer and connected to a second portion defining another part, different from the first portion, of the upper surface of the conductor layer through an upper contact hole selectively formed in the insulating layer.
In the semiconductor device according to the first aspect, electrical connection between the upper electrode film and the wire is implemented by electrically connecting the upper electrode film to the first portion of the upper surface of the conductor layer and connecting the wire to the second portion through the upper contact hole.
Dissimilarly to the prior art forming the upper contact hole on the upper electrode film, therefore, allowance for over-etching is improved in formation of the upper contact hole. In other words, manufacturing errors in the semiconductor device can readily be suppressed.
According to a second aspect of the present invention, the conductor plug includes another conductor layer, and the another conductor layer and the conductor layer are identical in height to each other with reference to the main surface of the semiconductor substrate, identical in thickness to each other, and made of the same material.
In the semiconductor device according to the second aspect, the conductor plug includes another conductor layer, which can serve as a barrier layer preventing mutual diffusion between elements forming the lower electrode film and the semiconductor substrate. Further, the conductor layer and the other conductor layer, which are the same in height with each other with reference to the main surface of the semiconductor substrate, identical in thickness to each other and made of the same material, can be simultaneously formed through a single manufacturing step.
According to a third aspect of the present invention, the lower electrode film and the conductor layer are identical in height to each other with reference to the main surface of the semiconductor substrate, identical in thickness to each other, and made of the same material.
In the semiconductor device according to the third aspect, the lower electrode film and the conductor layer, which are the same in height with each other with reference to the main surface of the semiconductor substrate, identical in thickness to each other and made of the same material, can be simultaneously formed through a single manufacturing step.
According to a fourth aspect of the present invention, the semiconductor device further comprises a conductive side wall formed on a side wall surface of the upper electrode film and the dielectric film, and the side wall is connected to the first portion of the conductor layer.
In the semiconductor device according to the fourth aspect, the side wall electrically connects the upper electrode film and the conductor layer with each other, whereby neither mask pattern nor a transfer step therefor is required for electrically connecting the upper electrode film and the conductor layer with each other. In other words, the upper electrode film and the conductor layer can be electrically connected with each other through a simple step.
According to a fifth aspect of the present invention, the dielectric film covers the first potion of the conductor layer and is chemically converted to a conductor in a portion covering the first portion, and the first portion of the conductor layer is electrically connected to the upper electrode film through the portion of the dielectric film converted to a conductor.
In the semiconductor device according to the fifth aspect, the upper electrode film and the conductor layer are electrically connected with each other through the portion of the dielectric film converted to a conductor, whereby neither a mask pattern nor a transfer step therefor is required for electrically connecting the upper electrode film and the conductor layer with each other. In other words, the upper electrode film and the conductor layer can be electrically connected with each other through a simple step.
According to a sixth aspect of the present invention, material of the lower electrode film and the upper electrode film includes a noble metal.
In the semiconductor device according to the sixth aspect, the material for the electrode films includes a noble metal, whereby a high dielectric film can suitably be used for the dielectric film. The upper electrode film is electrically connected to the wire through the conductor layer, whereby no adhesion film results from the noble metal with no etching stopper but connection resistance can be suppressed.
The present invention is also directed to a method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to a seventh aspect of the present invention comprises steps of (a) preparing a semiconductor substrate having a main surface, (b) forming, on the semiconductor substrate, a lower insulating layer selectively formed with a lower contact hole passing through upper and lower surfaces thereof and an opening defined at least in the upper surface so that a conductor plug is embedded in the lower contact hole and a conductor layer is embedded in the opening, (c) forming a first conductor material film on the lower insulating layer, (d) patterning the first conductor material film thereby forming a lower electrode film to be electrically connected to the conductor plug, (e) forming a dielectric film covering the lower electrode film and an upper electrode film covering the dielectric film while electrically connecting the upper electrode film to a first portion defining a part of an upper surface of the conductor layer, (f) forming an upper insulating layer covering the upper electrode film, the conductor layer and the lower insulating layer, (g) selectively forming an upper contact hole passing through upper and lower surfaces in the upper insulating layer by etching to open in a second portion, different from the first portion, of the upper surface of the conductor layer, and (h) forming a wire embedded in the upper contact hole and arranged on the upper insulating layer.
In the manufacturing method according to the seventh aspect, electrical connection between the upper electrode film and the wire is implemented by electrically connecting the upper electrode film to the first portion of the upper surface of the conductor layer and connecting the wire to the second portion through the upper contact hole. Dissimilarly to the prior art forming the upper contact hole on the upper electrode film, therefore, allowance for over-etching is improved in formation of the upper contact hole. In other words, manufacturing errors in the semiconductor device can readily be suppressed.
A method of manufacturing a semiconductor device according to an eighth aspect of the present invention comprises steps of (a) preparing a semiconductor substrate having a main surface, (b) forming, on the semiconductor substrate, a lower insulating layer selectively formed with a lower contact hole passing through upper and lower surfaces thereof so that a conductor plug is embedded in the lower contact hole, (c) forming a first conductor material film on the conductor plug and on the lower insulating layer, (d) patterning the first conductor material film thereby forming a lower electrode film electrically connected to the conductor plug while simultaneously forming a conductor layer separated from the lower electrode film on the lower insulating layer, (e) forming a dielectric film covering the lower electrode film and an upper electrode film covering the dielectric film while electrically connecting the upper electrode film to a first portion defining a part of an upper surface of the conductor layer, (f) forming an upper insulating layer covering the upper electrode film, the conductor layer and the lower insulating layer, (g) selectively forming an upper contact hole passing through upper and lower surfaces in the upper insulating layer to open in a second portion, different from the first portion, of the upper surface of the conductor layer, and (h) forming a wire embedded in the upper contact hole and arranged on the upper insulating layer.
In the manufacturing method according to the eighth aspect, electrical connection between the upper electrode film and the wire is implemented by electrically connecting the upper electrode film to the first portion of the upper surface of the conductor layer and connecting the wire to the second portion through the upper contact hole. Dissimilarly to the prior art forming the upper contact hole on the upper electrode film, therefore, allowance for over-etching is improved in formation of the upper contact hole. In other words, manufacturing errors in the semiconductor device can readily be suppressed. Further, the lower electrode film and the conductor layer are simultaneously formed through a single manufacturing step, whereby the manufacturing. steps are simplified.
According to a ninth aspect of the present invention, the step (b) comprises steps of (b-1) forming an insulator material layer serving as the material for the lower insulating layer on the semiconductor substrate, (b-2) etching the insulator material layer thereby selectively forming the lower contact hole and the opening to pass through upper and lower surfaces together, (b-3) forming a first conductor material layer to fill up the lower contact hole and the opening, (b-4) etching the first conductor material layer thereby retracting its upper surface into the inner parts of the contact hole and the opening, (b-5) forming a second conductor material layer to fill up the lower contact hole and the opening and cover the insulator material layer after the step (b-4), and (b-6) retracting an upper surface of the second conductor material layer to be flush with the upper surface of the insulator material layer.
In the manufacturing method according to the ninth aspect, the conductor plug is formed by the first and second conductor material layers, whereby the second conductor material layer can serve as a barrier layer preventing mutual diffusion between elements forming the lower electrode film and the semiconductor substrate. Further, the lower contact hole and the opening are simultaneously formed through a single manufacturing step while the conductor layer and the second conductor material layer are also simultaneously formed through a single manufacturing step, whereby the manufacturing steps are simplified.
According to a tenth aspect of the present invention, the step (b) comprises steps of (b-1) forming a first insulator material layer on the semiconductor substrate, (b-2) etching the first insulator material layer thereby selectively forming a first lower contact hole defining a part of the lower contact hole to pass through upper and lower surfaces of the first insulator material layer, (b-3) forming a first conductor material layer to fill up the first lower contact hole and cover the first insulator material layer, (b-4) retracting an upper surface of the first conductor material layer to be flush with the upper surface of the first insulator material layer, (b-5) forming a second insulator material layer to cover the upper surfaces of the first conductor material layer and the first insulator material layer after the step (b-4), (b-6) etching the second insulator material layer thereby selectively forming a second lower contact hole communicating with the first lower contact hole and defining another part of the lower contact hole and the opening to pass through upper and lower surfaces of the second insulator material layer together, (b-7) forming a second conductor material layer to fill up the second lower contact hole and the opening and cover the second insulator material layer, and (b-8) retracting an upper surface of the second conductor material layer to be flush with the upper surface of the second insulator material layer.
In the manufacturing method according to the tenth aspect, the conductor plug is formed by the first and second conductor material layers, whereby the second conductor material layer can serve as a barrier layer preventing mutual diffusion between elements forming the lower electrode film and the semiconductor substrate. Further, the conductor layer and the second conductor material layer are simultaneously formed through a single manufacturing step, whereby the manufacturing steps are simplified.
According to an eleventh aspect of the present invention, the step (e) comprises steps of (e-1) forming a dielectric material film to cover the upper surface of the lower insulating layer, the lower electrode film and the conductor layer, (e-2) forming a second conductor material film on the dielectric material film, (e-3) patterning the dielectric material film and the second conductor material film thereby forming the dielectric film covering the lower electrode film and the upper electrode film covering the dielectric film so that side wall surface thereof is adjacent to the first portion of the conductor layer, (e-4) forming a third conductor material film covering the upper electrode film, the conductor layer and the lower insulating layer, and (e-5) etching the third conductor material film thereby removing the third conductor material film while leaving a side wall covering the first portion of the conductor layer as well as the side wall surfaces of the upper electrode film and the dielectric film adjacent to the first portion.
In the manufacturing method according to the eleventh aspect, the upper electrode film and the conductor layer are electrically connected with each other by forming the side wall with no requirement for a mask pattern and a transfer step therefor.
In other words, the upper electrode film and the conductor layer can be electrically connected with each other through a simple step.
According to a twelfth aspect of the present invention, the step (e) comprises steps of (e-1) forming a dielectric material film to cover the upper surface of the lower insulating layer, the lower electrode film and the conductor layer, (e-2) forming a second conductor material film on the dielectric material film, (e-3) patterning the dielectric material film and the second conductor material film thereby forming the dielectric film covering the lower electrode film and the upper electrode film covering the dielectric film to also cover the first portion of the conductor layer, and (e-4) performing heating in any of the steps (e-1) to (e-3) or after the step (e-3), while the material for the conductor layer and the material for the dielectric material film are so selected that a portion of the dielectric material film covering the conductor layer is converted to a conductor due to reductive action of the conductor layer, and a portion of the dielectric material film or the dielectric film covering the conductor layer is converted to a conductor through the step (e-4).
In the manufacturing method according to the twelfth aspect, the upper electrode film and the conductor layer are electrically connected with each other by partially converting the dielectric film to a conductor with no requirement for a mask pattern and a transfer step therefor. In other words, the upper electrode film and the conductor layer can be electrically connected with each other through a simple step.
According to a thirteenth aspect of the present invention, a material including a noble metal is employed for the lower electrode film and the upper electrode film.
In the manufacturing method according to the thirteenth aspect, the material including a noble metal is employed for the electrode films, whereby a high dielectric film can suitably be used for the dielectric film. The upper electrode film is electrically connected to the wire through the conductor layer, whereby no adhesion film results from the noble metal with no etching stopper but connection resistance can be suppressed.
Thus, an object of the present invention is to provide a semiconductor device capable of preventing over-etching in formation of a contact hole and preventing formation of a re-deposition film without providing an etching stopper layer and a method of manufacturing the same.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

Semiconductor device with capacitor using high dielectric constant film or ferroelectric film

Matsushita Electric Industrial Co., Ltd.


A recessed light liner assembly according to the principles of the present disclosure includes a hollow body and an annular flange. The hollow body is configured to fit within the recessed light to prevent airflow through the recessed light, the body having an open bottom, a closed top, and a sidewall extending between the open bottom and the closed top. The annular flange is connected to the body and extends around the open bottom of the body.

This section provides background information related to the present disclosure which is not necessarily prior art.
A recessed light is a light fixture that is installed into an opening in a ceiling. When the recessed light is installed, the recessed light provides the appearance of light shining from a hole in the ceiling. The light is concentrated in a downward direction as a broad floodlight or a narrow spotlight.
A recessed light includes housing and trim. The housing can be mounted between ceiling joists. Alternatively, the housing can be mounted directly to the ceiling, which may occur when the recessed light is retrofitted to an existing ceiling. The housing contains a lamp holder for holding a light bulb and providing electricity to the light bulb. The trim is typically a ring that fits within the opening in the ceiling and extends around the light bulb to hide the housing.
Air may leak through a recessed light between a conditioned space of a building and an unconditioned space of the building, especially if the recessed light is older. Older recessed lights are typically very porous, and newer lights typically provide a better seal or barrier. However, even some newer, inexpensive recessed lights may not be sealed well.
Liners have been developed that can be retrofitted in a recessed light to prevent airflow through the recessed light. However, these liners require mounting hardware such as screws and brackets, and are therefore costly and difficult to install. Therefore, a need exists for a liner that has a simple design and is easy to install.

Liner for preventing airflow through a recessed light and a method for installing the liner


Data cleansing of a data management system involves merging two data objects by copying one or more attribute values associated with one a source object to a target data object and reassigning any instances that refer to the source object to the target object. The source object may be deleted. A user interface is developed that allows a user to select from a list of possible source objects and target objects, view attribute values for an object, view dependent relationships as dependency trees, indicate any attribute values that should be copied and any referring objects that should be reassigned to the target instance.

A database, such as relational database or an object-oriented database, or an other type of data management system may be used for the administration of data processed by a computer system running one or more application programs. Some data in the data management system may be incorrect because data is duplicated in the data management system. Data may be duplicated when two or more identical records exist in the data management system, when two or more records that represent the same entity exist in a data management system in which only one record for a particular entity is permitted, or when two records exist that incorrectly represent the same entity or event even when the records are not identical and more than one record for a particular entity or event is permitted. Duplicated data or incorrect data may be removed from the data management system to improve the accuracy of the data stored.


An embodiment of a dual-channel switching power system comprises a standby power supply and a main power supply both regulated by an eight-pin control chip. The control chip generates two sets of pulse-width modulation signal from a common clock oscillator and regulates the two power supplies during alternate clock cycles. The switching frequency and over-current limits of the two power supplies are adjustable by selecting different resistance values for two external resistors. The control chip provides an independent over-current protection to each power supply by monitoring the input power flow of the two power supplies via a common current-sense resistor.

The typical usage pattern of a personal computer is a period of active use followed by a period of idle state when the computer user is away tending other work. Further, many people leave their computers and monitors on after a working day, sometimes even over weekends. The total wasted power associated with all idling computers in an office can be very substantial. Further, many constituent electronic and mechanical components such as electrolytic capacitors, CRT monitors, and DC fans have finite life expectancy. Leaving computers on throughout after-work hours will shorten their usable life.
To promote energy saving of computers and to enhance the usable life of constituent components, a commonly used approach is to divide a computer power system into a standby power supply and a main power supply. FIG. 1 illustrates such a dual-channel computer power system. A standby power supply 10, typically with 5 to 10 watts of output power, supplies the operating power to a system supervisory circuit, volatile memory such as Dynamic RAM (DRAM), and a power management controller 90. A main power supply 20, typically with 100 to 300 watts of output power, on the other hand, supplies the operating power to a central processing unit (CPU), a hard-disk drive, a CD-ROM drive, a modem, DC fans, and other loads.
Upon detecting the computer has entered a long period of idle state, power management controller 90 pulls a SLEEP command line 92 to high state, thereby turns off main power supply 20 via a photo-coupler 93. The system power is reduced to less than 10 watts. Standby power supply 10 remains on, keeping the system supervisory circuit and power management controller 90 active. Upon the return of user activity, power management controller 90 pulls SLEEP command line 92 to low state, thus revives main power supply 20.
FIG. 2 illustrates a prior art embodiment of a dual-channel power system. A bridge rectifier 31 and a filter capacitor 32 rectify the incoming AC line voltage into a bulk DC voltage 30 and supply it to standby power supply 10 as well as to main power supply 20.
A pulse-width modulation chip 80, exemplified by a UC3842 current-mode PWM chip marketed by Unitrode Corporation (Merrimack, N.H.), controls standby power supply 10. A transformer 40 with a primary winding 41, a pair of secondary windings 42 and 43, is energized by DC voltage 30 through the control of a power MOSFET 35, which is in turn driven by a pulse-width modulation signal 37 from PWM chip 80. By using a proper turns-ratio, the voltage levels of two outputs, a +5V STANDBY 50 and a VCC supply 52, track each other closely under varying line and load conditions.
A boot-strap resistor 33 provides initial start-up power to PWM chip 80. PWM chip 80 has several internal functional circuit blocks. An under-voltage lockout circuit 81 ensures a proper starting-up voltage level from VCC supply 52. A 5V band-gap reference circuit 82 generates a 5V reference voltage 60. A clock oscillator 83 generates a continuous stream of pulses 88, whose frequency can be set by an external timing resistor 61 and an external timing capacitor 62. An error amplifier 84, a current-sense comparator 85, an R-S flip-flop 86, and a gate drive 89 combine to provide a current-mode PWM control for regulating VCC supply 52, thereby cross regulating +5V STANDBY 50. A current-sense resistor 36, connected between MOSFET 35 and the ground, provides an input current signal 38 for PWM chip 80 to monitor input current waveform and to detect any over-current condition. Each clock pulse 88 sets flip-flop 86 to high state and initiates a new PWM cycle. A PWM cycle is ended when input current signal 38 overtakes the scaled-down output of error amplifier 84 at the input of current-sense comparator 85.
In the event of an over-load or a short-circuit condition on standby power supply 10, the input current, Iin, flowing through MOSFET 35 and current-sense resistor 36 ramps up quickly. Input current signal 38, which is the product of Iin and the resistance of current-sense resistor 36, ramps up quickly. As soon as input current signal 38 exceeds 1.0V, current-sense comparator 85 output goes high, thus resets flip-flop 86. Gate drive 89 and MOSFET 35 shuts down immediately, thereby pre-empts the turn-on period. By using a fast current-sense comparator, the UC3842 is capable of a pulse-by-pulse current limiting. Further, simply by using different resistance values for current-sense resistor 36, UC3842 allows flexible adjustment of over-current protection level to match different power supplies' full-load current ratings.
An identical PWM chip 180 controls main power supply 20, which shares bulk DC voltage 30 with standby power supply 10. A transformer 140, energized by a power MOSFET 135, produces a +5V MAIN 150 output. A secondary-side error amplifier 112 senses +5V MAIN 150 and compared it with a secondary-side 2.50V reference 110. The output of error amplifier 112 is transmitted to PWM chip 180 via a photo-coupler 114, which provides a required primary-to-secondary isolation. A current-sense resistor 136 provides an input current signal 138 for PWM chip 180 to monitor input current waveform and to detect any over-current condition.
PWM chip 180 derives its VCC supply 98 from VCC supply 52 via a pair of transistors 94 and 95 and a self-bias resistor 96. SLEEP command line 92 controls the on-off of main power supply 20 by controlling VCC supply 98. When SLEEP command line 92 is pulled high by the system's power management controller, photo-coupler 93 turns on and diverts the base current of transistor 95 to ground. Transistors 94 and 95 are both turned off. PWM chip 180 shuts down as its VCC supply 98 is cut off.
Another prior art, exemplified by a UCC3810 dual-channel synchronized current-mode PWM controller, also marketed by Unitrode Corporation, integrates the equivalent of two UC3842 chips into a 16-pin package. FIG. 3 is a block diagram of UCC3810 PWM controller. The UCC3810 is capable of driving and regulating two power supplies. However, as a rule of thumb, the cost of packaging and testing is proportional to the number of pins of an IC. Therefore, there is a need for a dual-channel PWM control chip that has a minimum number of pins. Further, the industry standard packages are available in the form of 8-pin, 14-pin and 16-pin. Non-standard packages such as 6-pin, 10-pin and 12-pin require special tooling and customized test handlers.
The disclosure of U.S. Pat. No. 5,313,381 to Balakrishnan describes a three-terminal switched mode power supply IC wherein a PWM controller and a power MOSFET are integrated into a 3-pin package such as TO-220. However, this prior art relies on a built-in oscillator and current-sense circuit to reduce its pin counts. There is no flexibility to adjust its switching frequency or synchronize it to an external clock frequency. And since it uses an internal fixed over-current limit, a power supply IC according to this prior art can not be adjusted to match different full-load current ratings. Further, since it integrates a power MOSFET of pre-defined power and voltage ratings, there is no flexibility of using external power MOSFETs of various sizes, ratings, or packaging styles.
Thus there is a need for a dual-channel PWM control chip that has a minimum number of pins, uses few external components and yet maintains adjustable over-current limits and adjustable switching frequency. Preferably, the dual-channel control chip is packaged in an industrial standard 8-pin semiconductor package such as DIP-8 (8-pin Dual Inline) or SO-8 (8-pin Small Outline).

Dual-channel power system with an eight-pin PWM control chip


To provide an optical disk drive having an enhanced replaying capability in case of an abnormality occurring in various kinds of synchronization of the optical disk drive or in replay of a defective sector. A frame synchronization counter value address translation decoder, low order ID address translation decoder, adder/subtracter, high order ID address translation decoder, and adder are used to translate information read from an optical disk medium into an absolute storage address in a storage medium, and thus data that is highly replayed can be stored in the storage medium.

In a conventional optical disk drive, as disclosed in Japanese Patent Laid-Open No. 10-302402 and Japanese Patent Laid-Open No. 11-162105, generation of a data storage address in a buffer memory that is storage means used for an error correction processing of data read from an optical disk and data transfer to a host computer is carried out in the following manner.
That is, detection and interpolation of various synchronization patterns indicating a beginning of data structure (ECC block synchronization, sector synchronization, frame synchronization) are carried out, and the data storage address in the buffer memory is controlled according to the various synchronization detection and interpolation signals.
That is, the address generation has been carried out in such a manner that the number of various synchronization detection and interpolation signals is reflected as is in the data storage address in the buffer memory.
Furthermore, in order to prevent an abnormality from occurring in the data storage address in the buffer memory, the detection and interpolation of the various synchronization signals have been enhanced.
In the case where such an optical disk drive is used that the number of the various synchronization detection and interpolation signals corresponds to the data storage address in the buffer memory as described above, there has been a problem that the correspondence between pieces of data stored in the buffer memory is lost before and after the abnormality in the synchronization signals by an abnormality occurring in the synchronization detection and interpolation signals, such as omission or error in detection, or failed interpolation, that is caused by factors such as a fingerprint or scratch on the optical disk medium.
That is, there is a problem (first problem) that when an abnormality is caused in the synchronization detection and interpolation signals by factors such as a fingerprint or scratch on the optical disk medium, the correspondence between pieces of data stored in the buffer memory is lost.
Furthermore, there has been a problem that if the correspondence between pieces of data stored in the buffer memory is lost by the above-described factors, the data read from the optical disk medium is difficult to be properly replayed even with error correcting means.
That is, there is a problem (second problem) that if the correspondence between pieces of data stored in the buffer memory is lost by the above-described factors, the data read from the optical disk medium is difficult to be properly replayed even with error correcting means.
In addition, there has been a problem that in case of the optical disk medium having defective sector information recorded therein, there has been a problem that it is difficult to read data from the optical disk medium unless the defective sector information is acquired from the optical disk medium and the defective sector is indicated.
That is, there is a problem (third problem) that in case of the optical disk medium having defective sector information recorded therein, there has been a problem that it is difficult to read data from the optical disk medium unless the defective sector information is acquired from the optical disk medium and the defective sector is indicated.

Defective sector determination device and optical disk drive


A washable, reusable mat that serves as a stimulation device for animals, the mat having a base with a pile thereon, the pile being formed from a plurality of fingers which are arranged to form a structure with a plurality of spaces. Food or treats for the animal (e.g., a dog), are placed on the mat, and the food or treats fall among the fingers and are captured within the spaces formed in the pile by the fingers. The animal locates the food or treats by employing the animal's olfactory senses, such as smell and taste, to locate the food within the mat pile. The animal may use its nose (or paws) to gain access to the captured food by tunneling among the fingers, moving the fingers aside, or other action to access the hidden food.

Non-domestic animals typically spend most of their time foraging for food. In contrast, pets engage in eating, which usually does not demand much time, and as a result, eating becomes an activity that provides little stimulation for the animal. Stimulation of animals kept as pets in the home, or in shelters or other controlled environments, has been attempted to reduce boredom and undesirable behavior that may result as a consequence of the animal needing to be active. A number of toys are produced and sold which are intended to occupy the animal by providing an activity that will engage the animal. Some toys have sound, clicking, lights or other responsive components. A number of different sizes and shapes of toys are available. There are also products which have been designed to require engagement of the animal in order to obtain food. These products typically are referred to as enrichment products. Enrichment products typically encompass the categories of manipulation and mealtime. A typical enrichment device captivates food and limits its distribution to the animal by requiring the animal to perform one or more tasks. The enrichment devices often take time to fill, requiring the owner or handler to insert food into small spaces or into multiple compartments. One example of an enrichment product involves a ball filled with food that is placed into a tube. The animal must reach into the tube and move the ball to release food from an opening in the ball. The ball remains captive in the tube and may be removed and refilled as needed by a caretaker of the animal. Refilling the device requires that the ball be unsecured, removed from the device tube, refilled, placed back into the tube, and then finally re-secured within the tube. Another example of an enrichment device is a bowl having protrusions, such as posts or grooves provided in the bottom surface. The food is placed into the bowl and occupies the grooves, or, in the case of an obstruction, such as a post, fills in around the post. The pet must move the food around the obstruction or post in order for the food to be accessible to the pet for consumption. In the case of the grooved device, grooves are formed which lead to spaces or terminations in which the food may pool or pile up for ease of access, so that the animal is encouraged to move the food along the groove to a location at which the animal may pick up the food.
Other stimulations include stimulation of the olfactory senses, which, for canines, involves the senses of smell and taste. For example, snuffling is the act of breathing noisily through the nose, which may be due to something such as a cold or crying. However, in terms of animals, snuffling is described as the making of repeated sniffing sounds as though smelling at something. There is a snuffle mat which is a mat with a rubber backing to which strips of felt are tied. Food or treats are inserted between fleece strips. The pet is provided with the mat and uses its nose and sense of smell to locate the food. Upon locating the food, the pet may consume the food or treat located, and, if there is food or treats remaining, it may continue the process to locate other items of food or treats.
A need exists for an improved product that will provide engagement of the animal, such as a dog, with activity that stimulates the olfactory senses, that may be used to distribute food and treats, and which may be cleaned and reused.
As mentioned, animals when not engaged will often become bored. Domestic animals are typically kept in an environment which is the same day in and day out. Although dogs may be taken for a walk, a dog in the home, even if taken for an hour walk per day, may not have the stimulation that it needs. In addition, a number of dogs, such as for example, police service dogs and dogs kept in shelters, are often confined to cages for extended periods of time. These animals become bored, and often there is little or no stimulation for the animal. When animals are young, particularly dogs at the puppy stage, they typically will occupy themselves with a variety of activities, some of which may be destructive to the environment around them. The young canine may chew on furniture, rip pillows, or damage shoes and other household articles. Aside from the damage done to the articles, this behavior also may be hazardous to the pet. When the pet is occupied with another activity, such as eating or playing with an appropriate toy, then the pet is less likely to engage in destruction or harmful conduct. In addition, dogs that may be confined to a cage or other area also may benefit from engaging in a stimulating activity.


A method for efficient image registration between two images in the presence of inlier-poor domains includes receiving a set of candidate correspondences between the two images. An approximate homography between the two images is generated based upon a first correspondence in the correspondences. The set of candidate correspondences is filtered to identify inlier correspondences based upon the approximate homography. A candidate homography is computed based upon the inlier correspondences. The candidate homography can be selected as a final homography between the two images based upon a support of the candidate homography against the set of candidate correspondences. An image registration is performed between the two images based upon the candidate homography being selected as the final homography.

Image registration is employed in various computer vision applications in order to relate images taken from different positions or at different times to one another. Image feature detectors have been developed that are configured to identify candidate correspondences that are indicative of a single point from each of two images that are likely to be representative of a same portion of a same object or image feature. A homography between two images defines a relationship between the two images by which points in a first image can be projected to corresponding points in a second image. A homography between two images can be estimated based upon candidate correspondences generated by image feature detectors.
In a conventional approach to homography estimation, a candidate homography is computed based on four correspondences randomly selected from a larger group of candidate correspondences. In general, it is not known a priori which of a set of candidate correspondences generated by a feature detector are inliers (i.e., true correspondences that indicate points in two images that are representative of a same real location depicted in the two images), and which are outliers (i.e., correspondences that indicate points in two images that are not representative of a same real location depicted in the two images). Therefore, conventionally a homography is estimated iteratively by repetitively computing candidate homographies and computing the support of each candidate homography, which can be taken as the number of candidate correspondences in the larger set of candidate correspondences that the candidate homography projects to their expected location, within a small threshold ε. The candidate homography with the largest support among the iteratively computed candidate homographies can be returned as an estimate of the homography. A number of iterations run can be varied based upon a desired probability of computing a homography based upon a random sample consisting entirely of inliers.
While this conventional approach can be efficiently executed when the inlier rate of the set of candidate correspondences is high (e.g., greater than 15%), when the inlier rate is low (e.g., less than or equal to 15%), the conventional approach becomes prohibitively computationally expensive. For example, and referring briefly to FIG. 6, a graph 600 is shown that depicts a number of iterations of a random sample consensus (RANSAC) algorithm required to achieve a 95% probability of drawing all inlier samples at least once, plotted against the inlier rate of the correspondence set from which samples are drawn. The graph 600 depicts a different plot for each of n=1, 2, 3, or 4, where n is a number of random samples from the correspondence set that are used to compute a candidate homography. As can be seen from the graph 600, for a conventional four-sample RANSAC algorithm, the number of required RANSAC iterations to assure a 95% probability of drawing all inliers at least once becomes very large when the inlier rate drops below about 15%. Even if a homography estimation algorithm required only two samples, the number of iterations required to assure 95% probability of sampling only inliers would become very large below an inlier rate of about 5%.
For some imaging applications, due to noise or other factors the inlier rate of correspondences may be very low (e.g., less than or equal to 10%, less than or equal to 5%, less than or equal to 2.5%). In such cases, an accurate homography often cannot be practically calculated with existing techniques within a useful amount of time given limitations of available computing resources.

Homography generation for image registration in inlier-poor domains

National Technology & Engineering Solutions of Sandia, LLC


A template representing a desired target is applied to response signals from an area including a plurality of targets and illuminated by electromagnetic radiation. The response signals include poles or damped sinusoids representing resonances (e.g., resonant frequencies) distinctly associated with each of the targets within the area. An embodiment of the present invention utilizes pole or damped sinusoid frequencies of a desired target to construct the template or comb-like pattern that is compared to the mixture of pole frequencies within the response signals from the area. The comparison yields a resulting score that indicates the presence of the desired target within the area.

1. Technical Field
The present invention pertains to target detection based on return or response signals from an electromagnetic transmission. In particular, the present invention pertains to discriminating targets within response signals from an area including a plurality of targets and illuminated by an electromagnetic transmission.
2. Discussion of Related Art
In order to detect target objects, an object or an area may be illuminated by an electromagnetic field. Electromagnetic signals are reflected from the object or area and received and processed to identify a target object. The scattered response or reflected signals typically exhibit a set of resonances (e.g., resonating frequencies, etc.) that may be represented by damped sinusoids or poles. This pattern is distinctive and may be used to identify the object. Several conventional mathematical techniques may be utilized to determine the parameters (e.g., frequencies, damping constants, etc.) of these sinusoids. For example, the Matrix Pencil Method (MPM) places sample data points from a waveform or response signal of interest within two matrices. The matrices are manipulated to provide pole parameters (e.g., frequencies, damping constants, etc.) as eigenvalues of a matrix equation. This technique is preferred since the technique provides greater stability and less sensitivity to noise relative to other techniques, such as Prony techniques.
When a desired target is part of a scene that includes several targets, the resulting scattering response contains poles from all objects in the illuminated scene, thereby hindering or preventing identification of the desired target.

Method and apparatus for target discrimination within return signals


The present invention is based upon the finding that the protein p300 has acetylation activity which is directed to the retinoblastoma tumour suppressor protein pRb by the presence in the cell of the adenovirus E1A protein. This represents a target for modulators of the cell cycle, to which end the invention provides an assay for a modulator of acetylation of pRb by p300, which comprises: a) bringing into contact a p300 protein a pRb protein and a putative modulator compound under conditions where the p300 protein, in the absence of said modulator is capable of acetylating the pRb protein; b) providing conditions for acetylation of said pRb protein; and c) measuring the degree of inhibition of acetylation caused by said modulator compound.

The product of the retinoblastoma tumour suppressor gene, pRb, mediates control of the G1 to S phase transition by interacting with growth-regulating transcription factors, such as the E2F family [1, 2]. The Rb gene is frequently mutated in tumour cells, and can be inactivated through the physical association with viral oncoproteins such as adenovirus E1A [3]. Post-translational phosphorylation control of pRb by G1 cyclin-dependent kinases plays an important role in regulating pRb activity [4]. The p300/CBP transcriptional co-activator proteins are endowed with histone acetyltransferase (HAT), which is involved in regulating chromatin [6].

Acetylation of pRb by p300 assay method for compounds which modulate this process

The University Court of the University of Glasgow


A method for generating an image of a region of interest in a biological sample comprising the steps of: generating a first image including the region of interest of the biological sample having undergone a first protocol but not a second protocol; and generating a second image including the region of interest of the biological sample after having undergone a second protocol; wherein the region of interest is smaller than said sample. Also provided is a method of analyzing a biological sample, comprising providing an image of the biological sample according to the method for generating an image of a region of interest in a biological sample, and analyzing the biological sample from the image. Further provided are system and kit that comprise the means for executing the novel methods.

Most diseases have a heterogeneous phenotype, and require complex characterization for patient assessment. Breast cancer, for example, consists of five distinct subtypes, with each subtype associated with different phenotypes, survival times, and therapy responsiveness. For example, luminal types have the best prognosis and respond well to hormonal therapies, whereas patients with HER2-positive and basal tumors fare poorly. While recent developments of targeted therapies have made significant impacts in the treatment of HER2-positive tumors, many of these patients fail to respond, or develop resistance. In many of these cases, mutations in the HER2 gene or the activation of other pathways, (e.g. PI3K/AKT) have been identified, and new therapies that target both normal and mutated-HER2 or combination therapies that also affect these other pathways have been suggested. Additionally, several studies have even indicated that changes in the same gene in different breast cancer subtypes may impact both the course of disease and therapy response differently. Thus, comprehensive profiling of a patient's tumor is of the utmost importance for a physician to be able to make the best treatment decision for that patient.
In a fraction of patients with breast cancer, the HER2 gene is amplified as part of the process of malignant transformation and tumor progression. HER2 gene amplification generally leads to overexpression of the HER2 protein on the surface of breast cancer cells. Amplification of the HER2 gene and/or overexpression of its protein have been demonstrated in 25-30% of breast cancers. Several studies have shown that HER2 status correlates with sensitivity or resistance to certain chemotherapy regimens. Demonstration of high HER2 protein overexpression or HER2 gene amplification is essential for initiating therapy with Herceptin™, a monoclonal antibody to HER2 protein. Clinical studies have shown that patients whose tumors have high HER2 protein overexpression and/or amplification of the HER2 gene benefit most from Herceptin™. There is a recommendation that both HER2 protein level and HER2 gene amplification should be measured. However, two patient samples are routinely used to conduct the IHC and FISH analysis, potentially resulting in a lack of concordance between the two results. Ideally both analyses would be conducted on the same sample and at a cell to cell level.
In patients with advanced or metastatic cancer of the stomach or gastro-esophageal junction, approximately 20% have a HER2-positive disease. Adenocarcinomas are more commonly HER2-positive than undifferentiated carcinomas and mixed tumors; cancers of the gastro-esophageal junction are more likely to be HER2-positive than the tumors of the stomach. Trastuzumab™ has been shown to improve survival of patients with HER2-positive advance or metastatic cancer of the stomach or gastro-esophageal junction. Studies demonstrated that gene amplification (FISH) and protein overexpression (using immunofluorescence detection) are not as correlated as with breast cancer, therefore a single method should not be used to determine HER-2 status.
Although various methods may be used in biology and in medicine to observe different targets in a biological sample, many of the current techniques may detect only a few targets at one time (such as, immunofluorescence (IF) where number of targets detectable is limited by the florescence-based detection system) in a single sample. Further analysis of targets may require use of additional biological samples from the source limiting the ability to determine relative characteristics of the targets such as the presence, absence, concentration, and/or the spatial distribution of multiple biological targets in the biological sample. Moreover, in certain instances, a limited amount of sample may be available for analysis or the individual sample may require further analysis for other proteins of interest such as cell cycle or other cancer biomarkers. Thus, methods, agents, and devices capable of iteratively analyzing an individual sample are needed.
Several laboratories have attempted to combine protein expression and DNA based analysis on a single sample. Lottner et al. described a protocol which performs FISH first, then perform IF of HER2 on a single tissue sample, followed by image analysis. J Pathol. 2005; 205(5):577-84; doi: 10.1002/path.1742. The authors noted that performing IF prior to FISH results in higher background fluorescence and weaker immunofluorescence. Reisenbichler et al. experimented on the combination of immunohistochemistry (IHC) and chromogenic in situ hybridization (CISH) for HER2 on a single sample. Am J Clin Pathol 2012; 137:102-110; doi: 10.1309/AJCPLNHINN9O6YSF. While the authors were able to obtain signal by first imaging CISH sample, followed by imaging IHC sample, they found that better images were obtained when not only IHC is performed after CISH, also the sample was only imaged until the completion of all wet lab experimentation (i.e. without an intermediate imaging step). Importantly, Reisenbichler et al. could not obtain CISH signal when they first performed IHC on the sample, then performed CISH.
Gaiser et al. described a method for the analysis of tissue structures localized by protein expression for gene amplification within the same tissue sample. The authors first detected CD133 expression in colon cancer tissue samples, using monoclonal antibody and FITC-labeled secondary antibody. Using 40× magnification, regions of interest were manually selected and recorded. After imaging, FISH analysis was performed simultaneously for amplified cMyc oncogene and ZNF217. The sample was again imaged in the same regions at 40× magnification. An automated microscope and custom designed classifier for tile based FISH analysis was used to analyze the images. Anal Cell Pathol (Amst). 2010; 33(2): 105-112; doi: 10.3233/ACP-CLO-2010-0532).
There is still a need for improved methods for the detection of multiple targets in the same biological sample and the creation of a composite image to compare expression on a cell by cell basis, allowing the inclusion or exclusion of cells based on protein expression, apoptosis etc.

Methods for generating an image of a biological sample


A process for regulating continuously variable transmissions in motor vehicles by means of a controller includes a first control circuit as a speed controller for regulating the transmission input speed as the product calculated from the transmission output speed and the transmission ratio, and a second control circuit post-connected to the first control circuit as a speed gradient controller for regulating the time derivative of the transmission input speed. A correction value, dependent on the functional value of a correcting function and obtained from a correction element, is added to the summation element at the controller input of one of the two control circuits. The correction value is obtained such that the regulating ranges are specified, respectively, with a different control behavior of the controller.

The drive unit of motor vehicles (engine and power transmission train) is increasingly subjected to regulating and control mechanisms in order to optimize the interplay of an engine and its associated transmission; thus, for instance, to reduce fuel consumption in motor vehicles it will be necessary not only to improve engine control systems but also to adapt transmission ratios. To achieve this, automatic transmissions present themselves as a solution, with CVTs (continuously variable transmissions) in particular being increasingly used; this type of transmission allows continuous transmission adjustment until the required transmission ratio has been set. By means of a transmission element (chain, band, belt, etc) located between the discs of two disc assemblies, the required transmission ratio can be continuously adapted: by applying the same contact pressure values on these two disc assemblies--this corresponds to the so-called pretensioning force--the force level for this transmission element will be adjusted; specifying different values for this contact pressure on the two disc assemblies will create an additional transport force component for moving this transmission element; by varying this contact pressure, and thus the transport force, the transmission ratio may be continuously varied in any number of steps.
The regulating processes employed in continuously variable transmissions normally use transmission or speed controllers to effect control. The transmission input or drive speed will be controlled by means of a control circuit designed as a speed controller, this transmission input or drive speed represents the product from transmission output speed, which is proportional to vehicle velocity, or drive speed (disturbance variable), and transmission ratio (control variable); the regulating processes incorporate adaptive strategies to adapt characteristic control fields to the type of driver on the one hand ("long-term strategy: engine performance required by the respective driver"), or to a given environment ("medium-term strategy": for example, slip detection, towing a trailer, climbing a hill), and, finally, to the current driving situation ("short-term strategy": for example, overtaking another vehicle). Furthermore, in order to improve control response, the speed controller can be provided with (post-connected to) a second control circuit of acceleration control type, where the time derivative (gradient) of the transmission input speed represents the controlled variable; that is, in addition to speed control, a speed gradient control will also be effected. The disadvantage of these regulating processes for controlling continuously variable transmissions is that it is not possible to effect (even though this might often be desirable) a control, limitation, or suppression of the control behavior in respect of the control variable transmission ratio, as only the controlled variable transmission input speed is monitored to provide a measure for the transmission ratio: for instance, it is possible that during acceleration or deceleration of the vehicle an unintended change in the transmission ratio, due to the underlying speed gradient control, and thus a change in the transmission settings can occur; in particular, this can lead to an unintentional movement into the so-called mechanical end position of the transmission where strength and/or service life of the transmission element may be detrimentally affected or where the transmission element can be destroyed.

Procedure for controlling continuous variable transmissions in motor vehicles