In a current command type PWM inverter apparatus including first to sixth main circuit switching power devices for supplying line currents to a three-phase motor, at a periodical state updating first timing, and at least one second timing when any one of first, second and third comparison signals between respective detected line currents and respective line current command signals change after the state updating first timing, a logic circuit generates and outputs first to sixth switching command signals to the main circuit switching power devices so as to minimize errors between respective line current command signals and respective detected line currents.

1. Field of the Invention
The present invention relates to a current command type PWM (Pulse Width Modulation) inverter apparatus, in particular, to a current command type PWM inverter apparatus for driving and controlling a three-phase motor based on periodical state updating timings.
2. Description of the Prior Art
In recent years, current command type PWM inverters are extensively used in driving and controlling three-phase motors such as induction motors, synchronous motors, reluctance motors, or the like.
In comparison with a voltage command type PWM inverter which commands a voltage to be applied to a motor and applies the voltage conforming to the command, to the motor, the current command type PWM inverter, which commands a current to be flowed into a motor and compulsorily flows the current conforming to the command through the motor, is advantageous in responsibility and controllability. In particular, for controlling an AC servomotor and the like, the current command type PWM inverter is adopted in almost all the cases.
A construction of a generic current command type PWM inverter system will be described here with reference to FIG. 9.
Referring to FIG. 9, first of all, a fundamental frequency f and an effective current value ip of a three-phase AC (Alternating Current) current waveform to be supplied to a three-phase motor 1 are set in a current command generator circuit 7, and based on these information, the current command generator circuit 7 internally generates line current command signals to be flowed into the three-phase motor 1 as a first line current command signal iTU, a second line current command signal iTV and a third line current command signal iTW.
Then, a motor current detector circuit 9 detects two line currents of the three-phase motor 1, obtains the remaining one line current by obtaining the sum of the detected two line currents and inverting the sign of the sum value, and outputs the resulting detected currents as a first detected line current iFU, a second detected line current iFV and a third detected line current iFW. It is to be noted that the motor current detector circuit 9 may detect the three line currents of the three-phase motor 1, and then output the first detected line current iFU, the second detected line current iFV and the third detected line current iFW.
Then, a current controller 106 receives the first line current command signal iTU, the second line current command signal iTV, the third line current command signal iTW, the first detected line current iFU, the second detected line current iFV and the third detected line current iFW, and generates a first switching command signal PU, a second switching command signal PV and a third switching command signal PW so that the first line current command signal iTU, the second line current command signal iTV and the third line current command signal iTW are made to respectively coincide with the first detected line current iFU, the second detected line current iFV and the third detected line current iFW as far as possible.
Further, a main circuit power controller 8 comprises:
(a) a main circuit DC (Direct Current) power source 3; and PA1 (b) a main circuit power device circuit 2 having a three-phase bridge connection, wherein the main circuit power device circuit 2 comprises: PA1 motor current detecting means for directly or indirectly detecting line currents flowing from respective lines of said PWM inverter apparatus into a three-phase motor and outputting a first detected line current, a second detected line current and a third detected line current; PA1 current command generating means for generating and outputting a first line current command signal, a second line current command signal and a third line current command signal for commanding the line currents to be flowed from said respective lines into the three-phase motor; PA1 first comparing means for comparing the first line current command signal with the first detected line current, outputting a first line current comparison signal having zero level when a difference between the first line current command signal and the first detected line current falls within an allowance range including zero, outputting the first line current command signal having a first level when the difference between the first line current command signal and the first detected line current falls outside the allowance range and when the first detected line current is equal to or greater than the first line current command signal, and outputting the first line current comparison signal having a second level when the difference between the first line current command signal and the first detected line current falls outside the allowance range and when the first detected line current is smaller than the first line current command signal; PA1 second comparing means for comparing the second line current command signal with the second detected line current, outputting a second line current comparison signal having zero level when a difference between the second line current command signal and the second detected line current falls within an allowance range including zero, outputting the second line current comparison signal having a first level when the difference between the second line current command signal and the second detected line current falls outside the allowance range and when the second detected line current is equal to or greater than the second line current command signal, and outputting the second line current comparison signal having a second level when the difference between the second line current command signal and the second detected line current falls outside the allowance range and when the second detected line current is smaller than the second line current command signal; PA1 third comparing means for comparing the third line current command signal with the third detected line current, outputting a third line current comparison signal having zero level when a difference between the third line current command signal and the third detected line current falls within an allowance range including zero, outputting the third line current comparison signal having a first level when the difference between the third line current command signal and the third detected line current falls outside the allowance range and when the third detected line current is equal to or greater than the third line current command signal, and outputting the third line current comparison signal having a second level when the difference between the third line current command signal and the third detected line current falls outside the allowance range and moreover the third detected line current is smaller than the third line current command signal; PA1 a main circuit DC power source; PA1 main circuit power device circuit having a three-phase bridge connection and comprising: PA1 until the next state updating first timing, said logic circuit generates and outputs either one group of the first, second and third switching command signals or the fourth, fifth and sixth switching command signals for respectively turning off the first, second and third main circuit switching power devices or the fourth, fifth and sixth main circuit switching power devices, and further generates and outputs the remaining group of the switching command signals for respectively turning on the remaining group of the main circuit switching power devices. PA1 said logic circuit maintains the on-state or off-state of the main circuit switching power devices obtained just before the state updating first timing, until the next state updating first timing. PA1 for a time interval from a second timing when the first line current comparison signal changes from the first level to the second level to the next state updating first timing, said logic circuit generates and outputs the first switching command signal for turning off the first main circuit switching power device and further generates and outputs the fourth switching command signal for turning on the fourth main circuit switching power device, PA1 wherein, when the first line current comparison signal has the second level, the second line current comparison signal has the first level and the third line current comparison signal has the second level at the state updating first timing, said logic circuit generates and outputs the first, third and fifth switching command signals for respectively turning off the first, third and fifth main circuit switching power devices, and further generates and outputs the second, fourth and sixth switching command signals for respectively turning on the second, fourth and sixth main circuit switching power devices, and PA1 for a time interval from a second timing when the first line current comparison signal changes from the second level to the first level to the next state updating first timing, said logic circuit generates and outputs the second switching command signal for turning off the second main circuit switching power device and further generates and outputs the fifth switching command signal for turning on the fifth main circuit switching power device, PA1 wherein, when the first line current comparison signal has the second level, the second line current comparison signal has the second level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the first, second and sixth switching command signals for respectively turning off the first, second and sixth main circuit switching power devices, and further generates and outputs the third, fourth and fifth switching command signals for respectively turning on the third, fourth and fifth main circuit switching power devices, and PA1 for a time interval from a second timing when the third line current comparison signal changes from the second level to the first level to the next state updating first timing, said logic circuit generates and outputs the third switching command signal for turning off the third main circuit switching power device and further generates and outputs the sixth switching command signal for turning on the sixth main circuit switching power device, PA1 wherein, when the first line current comparison signal has the second level, the second line current comparison signal has the first level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the first, fifth and sixth switching command signals for respectively turning off the first, fifth and sixth main circuit switching power devices, and further generates and outputs the second, third and fourth switching command signals for respectively turning on the second, third and fourth main circuit switching power devices, and PA1 for a time interval from a second timing when the first line current comparison signal changes from the first level to the second level to the next state updating first timing, said logic circuit generates and outputs the fourth switching command signal for turning off the fourth main circuit switching power device and further generates and outputs the first switching command signal for turning on the first main circuit switching power device, PA1 wherein, when the first line current comparison signal has the first level, the second line current comparison signal has the second level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the second, fourth and sixth switching command signals for respectively turning off the second, fourth and sixth main circuit switching power devices, and further generates and outputs the first, third and fifth switching command signals for respectively turning on the first, third and fifth main circuit switching power devices, and PA1 for a time interval from a second timing when the second line current comparison signal changes from the first level to the second level to the next state updating first timing, said logic circuit generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and further generates and outputs the second switching command signal for turning on the second main circuit switching power device, and PA1 wherein, when the first line current comparison signal has the first level, the second line current comparison signal has the first level and the third line current comparison signal has the second level at the state updating first timing, said logic circuit generates and outputs the third, fourth and fifth switching command signals for respectively turning off the third, fourth and fifth main circuit switching power devices, and further generates and outputs the first, second and sixth switching command signals for respectively turning on the first, second and sixth main circuit switching power devices, and PA1 for a time interval from a second timing when the third line current comparison signal changes from the first level to the second level to the next state updating first timing, said logic circuit generates and outputs the sixth switching command signal for turning off the sixth main circuit switching power device and further generates and outputs the third switching command signal for turning on the third main circuit switching power device. PA1 for a time interval from a second timing when the first line current comparison signal changes to the zero level to the next state updating first timing, said logic circuit generates and outputs the first switching command signal for turning off the first main circuit switching power device and further generates and outputs the fourth switching command signal for turning on the fourth main circuit switching power device, PA1 wherein, when the first line current comparison signal has the zero level, the second line current comparison signal has the second level and the third line current comparison signal has the zero level at the state updating first timing, said logic circuit generates and outputs the first, third and fifth switching command signals for respectively turning off the first, third and fifth main circuit switching power devices, and further generates and outputs the second, fourth and sixth switching command signals for respectively turning on the second, fourth and sixth main circuit switching power devices, and PA1 for a time interval from a second timing when the second line current comparison signal changes to the zero level to the next state updating first timing, said logic circuit generates and outputs the second switching command signal for turning off the second main circuit switching power device and further generates and outputs the fifth switching command signal for turning on the fifth main circuit switching power device, PA1 wherein, when the first line current comparison signal has the zero level, the second line current comparison signal has the zero level and the third line current comparison signal has the second level at the state updating first timing, said logic circuit generates and outputs the first, second and sixth switching command signals for respectively turning off the first, second and sixth main circuit switching power devices, and further generates and outputs the third, fourth and fifth switching command signals for respectively turning on the third, fourth and fifth main circuit switching power devices, and PA1 for a time interval from a second timing when the third line current comparison signal changes to the zero level to the next state updating first timing, said logic circuit generates and outputs the third switching command signal for turning off the third main circuit switching power device and further generates and outputs the sixth switching command signal for turning on the sixth main circuit switching power device, PA1 wherein, when the first line current comparison signal has the first level, the second line current comparison signal has the zero level and the third line current comparison signal has the zero level at the state updating first timing, said logic circuit generates and outputs the first, fifth and sixth switching command signals for respectively turning off the first, fifth and sixth main circuit switching power devices, and further generates and outputs the second, third and fourth switching command signals for respectively turning on the second, third and fourth main circuit switching power devices, and PA1 for a time interval from a second timing when the first line current comparison signal changes to the zero level to the next state updating first timing, said logic circuit generates and outputs the fourth switching command signal for turning off the fourth main circuit switching power device and further generates and outputs the first switching command signal for turning on the first main circuit switching power device, PA1 wherein, when the first line current comparison signal has the zero level, the second line current comparison signal has the first level and the third line current comparison signal has the zero level at the state updating first timing, said logic circuit generates and outputs the second, fourth and sixth switching command signals for respectively turning off the second, fourth and sixth main circuit switching power devices, and further generates and outputs the first, third and fifth switching command signals for respectively turning on the first, third and fifth main circuit switching power devices, and PA1 for a time interval from a second timing when the second line current comparison signal changes to the zero level to the next state updating first timing, said logic circuit generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and further generates and outputs the second switching command signal for turning on the second main circuit switching power device, and PA1 wherein, when the first line current comparison signal has the zero level, the second line current comparison signal has the zero level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the third, fourth and fifth switching command signals for respectively turning off the third, fourth and fifth main circuit switching power devices, and further generates and outputs the first, second and sixth switching command signals for respectively turning on the first, second and sixth main circuit switching power devices, and PA1 for a time interval from a second timing when the third line current comparison signal changes to the zero level to the next state updating first timing, said logic circuit generates and outputs the sixth switching command signal for turning off the sixth main circuit switching power device and further generates and outputs the third switching command signal for turning on the third main circuit switching power device. PA1 when said logic circuit has generated and outputted the third switching command signal for turning off the third main circuit switching power device and the sixth switching command signal for turning on the sixth main circuit switching power device, said logic circuit generates and outputs the second switching command signal for turning off the second main circuit switching power device and the fifth switching command signal for turning on the fifth main circuit switching power device, for a time interval from a second timing when the second line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the sixth switching command signal for turning off the sixth main circuit switching power device and the third switching command signal for turning on the third main circuit switching power device, said logic circuit generates and outputs the fourth switching command signal for turning off the fourth main circuit switching power device and the first switching command signal for turning on the first main circuit switching power device, for a time interval from a second timing when the first line current comparison signal changes to the second level to the next state updating first timing, PA1 wherein, when the first line current comparison signal has the zero level, the second line current comparison signal has the first level and the third line current comparison signal has the second level at the state updating first timing, said logic circuit generates and outputs the second and sixth switching command signals for respectively turning off the second and sixth main circuit switching power devices, generates and outputs the third and fifth switching command signals for respectively turning on the third and fifth main circuit switching power devices, generates and outputs either one of the first or fourth switching command signal for turning off the first or fourth main circuit switching power device, and generates and outputs the remaining one switching command signal for turning on the remaining one main circuit switching power device, PA1 when said logic circuit has generated and outputted the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device, said logic circuit generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device, for a time interval from a second timing when the third line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the fourth switching command signal for turning off the fourth main circuit switching power device and thefirst switching command signal for turning on the first main circuit switching power device, said logic circuit generates and outputs the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device, for a time interval from a second timing when the second line current comparison signal changes to the second level to the next state updating first timing, PA1 wherein, when the first line current comparison signal has the second level, the second line current comparison signal has the zero level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the third and fourth switching command signals for respectively turning off the third and fourth main circuit switching power devices, generates and outputs the first and sixth switching command signals for respectively turning on the first and sixth main circuit switching power devices, generates and outputs either one of the second or fifth switching command signal for turning off the second or fifth main circuit switching power device, and generates and outputs the remaining one switching command signal for turning on the remaining one main circuit switching power device, PA1 when said logic circuit has generated and outputted the second switching command signal for turning off the second main circuit switching power device and the fifth switching command signal for turning on the fifth main circuit switching power device, said logic circuit generates and outputs the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device, for a time interval from a second timing when the first line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device, said logic circuit generates and outputs the sixth switching command signal for turning off the sixth main circuit switching power device and the third switching command signal for turning on the third main circuit switching power device, for a time interval from a second timing when the third line current comparison signal changes to the second level to the next state updating first timing, PA1 wherein, when the first line current comparison signal has the second level, the second line current comparison signal has the first level and the third line current comparison signal has the zero level at the state updating first timing, said logic circuit generates and outputs the second and fourth switching command signals for respectively turning off the second and fourth main circuit switching power devices, generates and outputs the first and fifth switching command signals for respectively turning on the first and fifth main circuit switching power devices, generates and outputs either one of the third or sixth switching command signal for turning off the third or sixth main circuit switching power device, and generates and outputs the remaining one switching command signal for turning on the remaining one main circuit switching power device, PA1 when said logic circuit has generated and outputted the third switching command signal for turning off the third main circuit switching power device and the sixth switching command signal for turning on the sixth main circuit switching power device, said logic circuit generates and outputs the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device, for a time interval from a second timing when the first line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the sixth switching command signal for turning off the sixth main circuit switching power device and the third switching command signal for turning on the third main circuit switching power device, said logic circuit generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device, for a time interval from a second timing when the second line current comparison signal changes to the second level to the next state updating first timing, PA1 wherein, when the first line current comparison signal has the zero level, the second line current comparison signal has the second level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the third and fifth switching command signals for respectively turning off the third and fifth main circuit switching power devices, generates and outputs the second and sixth switching command signals for respectively turning on the second and sixth main circuit switching power devices, generates and outputs either one of the first or fourth switching command signal for turning off the first or fourth main circuit switching power device, and generates and outputs the remaining one switching command signal for turning on the remaining one main circuit switching power device, PA1 when said logic circuit has generated and outputted the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device, said logic circuit generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device, for a time interval from a second timing when the second line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the fourth switching command signal for turning off the fourth main circuit switching power device and the first switching command signal for turning on the first main circuit switching power device, said logic circuit generates and outputs the third switching command signal for turning off the third main circuit switching power device and the sixth switching command signal for turning on the sixth main circuit switching power device, for a time interval from a second timing when the third line current comparison signal changes to the second level to the next state updating first timing, and PA1 wherein, when the first line current comparison signal has the first level, the second line current comparison signal has the zero level and the third line current comparison signal has the second level at the state updating first timing, said logic circuit generates and outputs the first and sixth switching command signals for respectively turning off the first and sixth main circuit switching power devices, generates and outputs the third and fourth switching command signals for respectively turning on the third and fourth main circuit switching power devices, generates and outputs either one of the second or fifth switching command signal for turning off the second or fifth main circuit switching power device, and generates and outputs the remaining one switching command signal for turning on the remaining one main circuit switching power device, PA1 when said logic circuit has generated and outputted the second switching command signal for turning off the second main circuit switching power device and the fifth switching command signal for turning on the fifth main circuit switching power device, said logic circuit generates and outputs the third switching command signal for turning off the third main circuit switching power device and the sixth switching command signal for turning on the sixth main circuit switching power device, for a time interval from a second timing when the third line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device, said logic circuit generates and outputs the fourth switching command signal for turning off the fourth main circuit switching power device and the first switching command signal for turning on the first main circuit switching power device, for a time interval from a second timing when the first line current comparison signal changes to the second level to the next state updating first timing. PA1 when said logic circuit has generated and outputted the third switching command signal for turning off the third main circuit switching power device and the sixth switching command signal for turning on the sixth main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the third switching command signal for turning off the third main circuit switching power device and the sixth switching command signal for turning on the sixth main circuit switching power device, and further generates and outputs the second switching command signal for turning off the second main circuit switching power device and the fifth switching command signal for turning on the fifth main circuit switching power device for a time interval from a second timing when the second line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the sixth switching command signal for turning off the sixth main circuit switching power device and the third switching command signal for turning on the third main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the sixth switching command signal for turning off the sixth main circuit switching power device and the third switching command signal for turning on the third main circuit switching power device, and further generates and outputs the fourth switching command signal for turning off the fourth main circuit switching power device and the first switching command signal for turning on the first main circuit switching power device for a time interval from a second timing when the first line current comparison signal changes to the second level to the next state updating first timing, PA1 wherein, when the first line current comparison signal has the zero level, the second line current comparison signal has the first level and the third line current comparison signal has the second level at the state updating first timing, said logic circuit generates and outputs the second and sixth switching command signals for respectively turning off the second and sixth main circuit switching power devices, and further generates and outputs the third and fifth switching command signals for respectively turning on the third and fifth main circuit switching power devices, PA1 when said logic circuit has generated and outputted the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device, and further generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device, for a time interval from a second timing when the third line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the fourth switching command signal for turning off the fourth main circuit switching power device and the first switching command signal for turning on the first main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the fourth switching command signal for turning off the fourth main circuit switching power device and the first switching command signal for turning on the first main circuit switching power device, and further generates and outputs the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device, for a time interval from a second timing when the second line current comparison signal changes to the second level to the next state updating first timing, PA1 wherein, when the first line current comparison signal has the second level, the second line current comparison signal has the zero level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the third and fourth switching command signals for respectively turning off the third and fourth main circuit switching power devices, and further generates and outputs the first and sixth switching command signals for respectively turning on the first and sixth main circuit switching power devices, PA1 when said logic circuit has generated and outputted the second switching command signal for turning off the second main circuit switching power device and the fifth switching command signal for turning on the fifth main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the second switching command signal for turning off the second main circuit switching power device and the fifth switching command signal for turning on the fifth main circuit switching power device, and further generates and outputs the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device, for a time interval from a second timing when the first line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device, and further generates and outputs the sixth switching command signal for turning off the sixth main circuit switching power device and the third switching command signal for turning on the third main circuit switching power device, for a time interval from a second timing when the third line current comparison signal changes to the second level to the next state updating first timing, PA1 wherein, when the first line current comparison signal has the second level, the second line current comparison signal has the first level and the third line current comparison signal has the zero level at the state updating first timing, said logic circuit generates and outputs the second and fourth switching command signals for respectively turning off the second and fourth main circuit switching power devices, and further generates and outputs the first and fifth switching command signals for respectively turning on the first and fifth main circuit switching power devices, PA1 when said logic circuit has generated and outputted the third switching command signal for turning off the third main circuit switching power device and the sixth switching command signal for turning on the sixth main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the third switching command signal for turning off the third main circuit switching power device and the sixth switching command signal for turning on the sixth main circuit switching power device, and further generates and outputs the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device, for a time interval from a second timing when the first line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the sixth switching command signal for turning off the sixth main circuit switching power device and the third switching command signal for turning on the third main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the sixth switching command signal for turning off the sixth main circuit switching power device and the third switching command signal for turning on the third main circuit switching power device and further generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device, for a time interval from a second timing when the second line current comparison signal changes to the second level to the next state updating first timing, PA1 wherein, when the first line current comparison signal has the zero level, the second line current comparison signal has the second level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the third and fifth switching command signals for respectively turning off the third and fifth main circuit switching power devices, and further generates and outputs the second and sixth switching command signals for respectively turning on the second and sixth main circuit switching power devices, PA1 when said logic circuit has generated and outputted the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the first switching command signal for turning off the first main circuit switching power device and the fourth switching command signal for turning on the fourth main circuit switching power device, and further generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device, for a time interval from a second timing when the second line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the fourth switching command signal for turning off the fourth main circuit switching power device and the first switching command signal for turning on the first main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the fourth switching command signal for turning off the fourth main circuit switching power device and the first switching command signal for turning on the first main circuit switching power device, and further generates and outputs the third switching command signal for turning off the third main circuit switching power device and the sixth switching command signal for turning on the sixth main circuit switching power device, for a time interval from a second timing when the third line current comparison signal changes to the second level to the next state updating first timing, and PA1 wherein, when the first line current comparison signal has the first level, the second line current comparison signal has the zero level and the third line current comparison signal has the second level at the state updating first timing, said logic circuit generates and outputs the first and sixth switching command signals for respectively turning off the first and sixth main circuit switching power devices, and further generates and outputs the third and fourth switching command signals for respectively turning on the third and fourth main circuit switching power devices, PA1 when said logic circuit has generated and outputted the second switching command signal for turning off the second main circuit switching power device and the fifth switching command signal for turning on the fifth main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the second switching command signal for turning off the second main circuit switching power device and the fifth switching command signal for turning on the fifth main circuit switching power device, and further generates and outputs the third switching command signal for turning off the third main circuit switching power device and the sixth switching command signal for turning on the sixth main circuit switching power device, for a time interval from a second timing when the third line current comparison signal changes to the first level to the next state updating first timing, and PA1 when said logic circuit has generated and outputted the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device just before the state updating first timing, said logic circuit generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and the second switching command signal for turning on the second main circuit switching power device, and further generates and outputs the fourth switching command signal for turning off the fourth main circuit switching power device and the first switching command signal for turning on the first main circuit switching power device, for a time interval from a second timing when the first line current comparison signal changes to the second level to the next state updating first timing.
(b-1) a first main circuit switching power device Q1 which is connected to a positive electrode of the main circuit DC power source 3 and supplies a first line current IU to the three-phase motor 1; PA2 (b-2) a second main circuit switching power device Q2 which is connected to the positive electrode of the main circuit DC power source 3 and supplies a second line current IV to the three-phase motor 1; PA2 (b-3) a third main circuit switching power device Q3 which is connected to the positive electrode of the main circuit DC power source 3 and supplies a third line current IW to the three-phase motor 1; PA2 (b-4) a fourth main circuit switching power device Q4 which is connected to a negative electrode of the main circuit DC power source 3 and supplies the first line current IU to the three-phase motor 1; PA2 (b-5) a fifth main circuit switching power device Q5 which is connected to the negative electrode of the main circuit DC power source 3 and supplies the second line current IV to the three-phase motor 1; PA2 (b-6) a sixth main circuit switching power device Q6 which is connected to the negative electrode of the main circuit DC power source 3 and supplies the third line current IV to the three-phase motor 1; and PA2 (b-7) six reflux diodes each connected in parallel between the collector and the emitter of each of the main circuit switching power devices, and wherein PA2 the main circuit power device circuit 2 operates to turn on either the first main circuit switching power device Q1 or the fourth main circuit switching power device Q4 in accordance with the first switching command signal PU, turn on either the second main circuit switching power device Q2 or the fifth main circuit switching power device Q5 in accordance with the second switching command signal PV, and turn on either the third main circuit switching power device Q3 or the sixth main circuit switching power device Q6 in accordance with the third switching command signal PW. PA2 a first main circuit switching power device which is connected to a positive electrode of the main circuit DC power source and supplies a first line current to the three-phase motor; PA2 a second main circuit switching power device which is connected to the positive electrode of the main circuit DC power source and supplies a second line current to the three-phase motor; PA2 a third main circuit switching power device which is connected to the positive electrode of the main circuit DC power source and supplies a third line current to the three-phase motor; PA2 a fourth main circuit switching power device which is connected to a negative electrode of the main circuit DC power source and supplies the first line current to the three-phase motor; PA2 a fifth main circuit switching power device which is connected to the negative electrode of the main circuit DC power source and supplies the second line current to the three-phase motor; PA2 a sixth main circuit switching power device which is connected to the negative electrode of the main circuit DC power source and supplies the third line current to the three-phase motor; and PA2 six reflux diodes respectively connected in parallel with said first, second, third, fourth, fifth and sixth main circuit switching power devices; PA2 a logic circuit for receiving the first line current comparison signal, the second line current comparison signal and the third line current comparison signal, and generating first, second, third, fourth, fifth and sixth switching command signals for said first, second, third, fourth, fifth and sixth main circuit switching power devices; and PA2 timing generating means for giving a periodical state updating first timing to said logic circuit, PA2 wherein, when the first line current comparison signal has the second level, the second line current comparison signal has the first level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the second, third and fourth switching command signals for respectively turning off the second, third and fourth main circuit switching power devices, and further generates and outputs the first, fifth and sixth switching command signals for respectively turning on the first, fifth and sixth main circuit switching power devices, PA2 for a time interval from a second timing when the second line current comparison signal changes from the first level to the second level to the next state updating first timing, said logic circuit generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and further generates and outputs the second switching command signal for turning on the second main circuit switching power device, and for a time interval from a second timing when the third line current comparison signal changes from the first level to the second level to the next state updating first timing, said logic circuit generates and outputs the sixth switching command signal for turning off the sixth main circuit switching power device and further generates and outputs the third switching command signal for turning on the third main circuit switching power device, PA2 wherein, when the first line current comparison signal has the first level, the second line current comparison signal has the second level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the first, third and fifth switching command signals for respectively turning off the first, third and fifth main circuit switching power devices, and further generates and outputs the second, fourth and sixth switching command signals for respectively turning on the second, fourth and sixth main circuit switching power devices, PA2 for a time interval from a second timing when the first line current comparison signal changes from the first level to the second level to the next state updating first timing, said logic circuit generates and outputs the fourth switching command signal for turning off the fourth main circuit switching power device and further generates and outputs the first switching command signal for turning on the first main circuit switching power device, and for a time interval from a second timing when the third line current comparison signal changes from the first level to the second level to the next state updating first timing, said logic circuit generates and outputs the sixth switching command signal for turning off the sixth main circuit switching power device and further generates and outputs the third switching command signal for turning on the third main circuit switching power device, PA2 wherein, when the first line current comparison signal has the first level, the second line current comparison signal has the first level and the third line current comparison signal has the second level at the state updating first timing, said logic circuit generates and outputs the first, second and sixth switching command signals for respectively turning off the first, second and sixth main circuit switching power devices, and further generates and outputs the third, fourth and fifth switching command signals for respectively turning on the third, fourth and fifth main circuit switching power devices, PA2 for a time interval from a second timing when the first line current comparison signal changes from the first level to the second level to the next state updating first timing, said logic circuit generates and outputs the fourth switching command signal for turning off the fourth main circuit switching power device and further generates and outputs the first switching command signal for turning on the first main circuit switching power device, and for a time interval from a second timing when the second line current comparison signal changes from the first level to the second level to the next state updating first timing, said logic circuit generates and outputs the fifth switching command signal for turning off the fifth main circuit switching power device and further generates and outputs the second switching command signal for turning on the second main circuit switching power device, PA2 wherein, when the first line current comparison signal has the first level, the second line current comparison signal has the second level and the third line current comparison signal has the second level at the state updating first timing, said logic circuit generates and outputs the first, fifth and sixth switching command signals for respectively turning off the first, fifth and sixth main circuit switching power devices, and further generates and outputs the second, third and fourth switching command signals for respectively turning on the second, third and fourth main circuit switching power devices, PA2 for a time interval from a second timing when the second line current comparison signal changes from the second level to the first level to the next state updating first timing, said logic circuit generates and outputs the second switching command signal for turning off the second main circuit switching power device and further generates and outputs the fifth switching command signal for turning on the fifth main circuit switching power device, and for a time interval from a second timing when the third line current comparison signal changes from the second level to the first level to the next state updating first timing, said logic circuit generates and outputs the third switching command signal for turning off the third main circuit switching power device and further generates and outputs the sixth switching command signal for turning on the sixth main circuit switching power device, PA2 wherein, when the first line current comparison signal has the second level, the second line current comparison signal has the first level and the third line current comparison signal has the second level at the state updating first timing, said logic circuit generates and outputs the second, fourth and sixth switching command signals for respectively turning off the second, fourth and sixth main circuit switching power devices, and further generates and outputs the first, third and fifth switching command signals for respectively turning on the first, third and fifth main circuit switching power devices, PA2 for a time interval from a second timing when the first line current comparison signal changes from the second level to the first level to the next state updating first timing, said logic circuit generates and outputs the first switching command signal for turning off the first main circuit switching power device and further generates and outputs the fourth switching command signal for turning on the fourth main circuit switching power device, and for a time interval from a second timing when the third line current comparison signal changes from the second level to the first level to the next state updating first timing, said logic circuit generates and outputs the third switching command signal for turning off the third main circuit switching power device and further generates and outputs the sixth switching command signal for turning on the sixth main circuit switching power device, and PA2 wherein, when the first line current comparison signal has the second level, the second line current comparison signal has the second level and the third line current comparison signal has the first level at the state updating first timing, said logic circuit generates and outputs the third, fourth and fifth switching command signals for respectively turning off the third, fourth and fifth main circuit switching power devices, and further generates and outputs the first, second and sixth switching command signals for respectively turning on the first, second and sixth main circuit switching power devices, and PA2 for a time interval from a second timing when the first line current comparison signal changes from the second level to the first level to the next state updating first timing, said logic circuit generates and outputs the first switching command signal for turning off the first main circuit switching power device and further generates and outputs the fourth switching command signal for turning on the fourth main circuit switching power device, and for a time interval from a second timing when the second line current comparison signal changes from the second level to the first level to the next state updating first timing, said logic circuit generates and outputs the second switching command signal for turning off the second main circuit switching power device and further generates and outputs the fifth switching command signal for turning on the fifth main circuit switching power device.
In this case, when the first switching command signal PU becomes a High level (referred to as an H-level hereinafter), the first main circuit switching power device Q1 is turned on. On the other hand, when the first switching command signal PU becomes a Low level (referred to as an L-level hereinafter), the fourth main circuit switching power device Q4 is turned on. When the second switching command signal PV becomes the H-level, the second main circuit switching power device Q2 is turned on. On the other hand, when the second switching command signal PV becomes the L-level, the fifth main circuit switching power device Q5 is turned on. When the third switching command signal PW becomes the H-level, the third main circuit switching power device Q3 is turned on. On the other hand, when the third switching command signal PW becomes the L-level, the sixth main circuit switching power device Q6 is turned on.
As above is described the structure and operation of the generic current command type PWM inverter system.
A structure of a prior art current command type PWM inverter will be described below with reference to FIG. 10.
FIG. 10 shows a structure of the prior art current controller 106 of the current command type PWM inverter system shown in FIG. 9.
FIGS. 11A through 11E show an operation of the inverter system shown in FIG. 10.
First of all, the first, second and third line current command signals iTU, iTV and iTW and the first, second and third detected line currents iFU, iFV and iFW are subjected to a subtraction process respectively in subtracters 117, 118 and 119 to obtain the first, second and third line current error signals iEU, iEV and iEW. Then first, second and third current error amplifiers 120, 121 and 122 receive the first, second and third line current error signals iEU, iEV and iEW, respectively, and then, output amplified voltage command signals VU, VV and VW, respectively. Each of the current error amplifiers 120, 121 and 122 is generally implemented by a proportion and integration type amplifier as shown in FIG. 12, and a gain characteristic thereof can be represented by the Equation (1): EQU G=R2.times.(R3.times.C1.times.S)/R1.times.{(R2+R3).times.C1.times.S+1}!(1) .
The reference numeral 139 denotes a three-phase PWM signal generator comprised of first, second and third comparators 123, 124 and 125 and a triangular wave generator 126. The first, second and third comparators 123, 124 and 125 compare a triangular wave signal SC outputted from the triangular wave generator 126 with the respective voltage command signals VU, VV and VW, respectively, and then, output the first, second and third switching command signals PU, PV and PW, respectively.
In the present case, each of the first, second and third comparators 123, 124 and 125 outputs the H-level when each of the voltage command signals VU, VV and VW is greater than the triangular wave signal SC, while each of the first, second and third comparators 123, 124 and 125 outputs the L-level when each of the voltage command signals VU, W and VW is smaller than the triangular wave signal SC.
FIGS. 11A through 11E show an operation of the current controller 106 shown in FIG. 10, when the first, second and third line current command signals iTU, iTV and iTW are three-phase sine waves, respectively.
Considering the gains of the current error amplifiers 120, 121 and 122 shown in FIGS. 10 and 11A through 11E, it can be understood that each line current error can be reduced by increasing the gains of the current error amplifiers 120, 121 and 122 as a consequence of approach of the detected line currents to the respective line current command signals, and the responsibility of the detected line currents to the respective line current command signals is improved.
However, according to the structure of the above-mentioned prior art, owing to a phase delay due to an electric time constant of the three-phase motor, phase delays of the current error amplifiers, a waste time delay of the three-phase PWM signal generator and the like, an oscillation phenomenon will occur when the current error amplifier gain is made too great. Therefore, the gain of each of the current error amplifiers is generally set to a value which is as great as possible and falls within a range in which no oscillation occurs. The gain of each of the current error amplifiers is determined in the designing stage by examining a loop transfer function of the current control loop from the characteristics of the three-phase motor, the motor current detector circuit, the current controller and the main circuit power controller. In the present case, considering the manufacturing-dependent variation of the characteristics and temperature characteristics, it is required to reduce the gain to a level at which no oscillation phenomenon occurs at worst. The work for determining the gain requires much labor of the operators engaging in the designing, and even a current command type PWM inverter having the same structure requires gain adjustment depending on different motors to which the inverter is to be connected, incurring such a problem that much labor is required for the control of the manufacturing process.
Furthermore, when the specifications of the three-phase motor to be connected to the current command type PWM inverter have not yet determined in the designing stage (e.g., in the case of a general use inverter, a general use AC servo driver or the like), it is required to adjust the gain in accordance with the specifications of the three-phase motor upon determining and installing the three-phase motor to which the inverter is to be connected, and there is such a problem that this gain adjustment work is a bottleneck.
Furthermore, the offset and drift of the triangular wave generator and the current error amplifiers themselves deteriorate the current control error and narrow the dynamic ranges of the amplified error signals. Therefore, an operational amplifier having a small offset and drift is required as a component of them, and depending on the cases, offset adjusting work is required in the manufacturing stage, incurring the problem of cost increase.
FIG. 10 shows a prior art example of the current controller 106 implemented by an analog circuit, however, there exists a current controller implementing a similar structure by a digital circuit such as a microcomputer which subjects the first, second and third detected line currents iFU, iFV and iFW to an analog to digital conversion process by means of an A/D converter. In such a case, the gain of the current error amplifier is required to be determined by examining the loop transfer function of the current control loop from the characteristics of the three-phase motor, the motor current detector circuit, the current controller and the main circuit power controller, and their problems are the same as those of the current controller implemented by the analog circuit.
Furthermore, when the current error amplifier is implemented by a digital circuit such as a microcomputer or the like, the offset and drift of the current error amplifier itself can be eliminated because they are achieved by digital calculation. However, as the calculation processing time increases, the phase delay increases and the circuit tends to oscillate. This consequently means that the gain cannot be increased unless the processing time is reduced, and therefore, a microcomputer having a very high speed calculation processing capability or the like must be used, incurring the problem of cost increase.
Furthermore, the phase delay of the A/D converter for converting the first, second and third detected line currents iFU, iFV and iFW into digital data becomes greater as the time for conversion increases, and the circuit tends to oscillate. This consequently means that the gain cannot be increased unless the conversion time is reduced, and therefore, an A/D converter having a very high speed conversion capability must be used, incurring the problem of cost increase. Furthermore, the offset and drift of the A/D converter consequently deteriorate the current control error and narrow its dynamic range. Therefore, it is required to select an A/D converter having smaller offset and drift, incurring the problem of cost increase.
Furthermore, the three-phase PWM command signal generator implemented by a digital circuit has such problems that the three-phase PWM command signal generator has a complicated structure and costs much as shown in the digital three-phase PWM wave generating apparatus disclosed in the Japanese Patent Laid-Open Publication No. 4-312360.

Current command type PWM inverter apparatus for driving and controlling three-phase motor based on periodical state updating timings

Matsushita Electric Industrial Co., Ltd.


An apparatus and method for handling a LET binding used in a WHERE clause of an XQuery FLWOR expression during an XML pivot join procedure. XPath steps under a LET binding are identified and marked as bindings. During a match graph construction phase of the pivot join procedure, the bindings are linked to a first common non-LET binding ancestor, while traversing from the bottom up. A location identifier for each binding is truncated to the location identifier of the first common non-LET binding ancestor to create a truncated location identifier. The truncated location identifier is compared to a node identification of a FOR binding of the XQuery FLWOR expression. A match of the node identifications will qualify the XML document and the XML document is returned by the XML pivot join procedure.

1. Field of the Invention
This invention relates to XML pivot joins and more particularly relates to handling a LET binding used in a WHERE clause of an XQuery FLWOR expression during an XML pivot join procedure.
2. Description of the Related Art
XPath and XQuery are two common languages used to query an XML document. XPath is a path expression language for selecting data within XML documents. XQuery is a language for querying, transforming, and constructing XML data. An expression is a string of unicode characters which may be constructed from keywords, symbols, and operands. XPath allows expressions to be nested. XQuery uses XPath expression syntax to address specific parts of an XML document and is semantically similar to structured query language (SQL). The SQL-like XQuery syntax uses "For, Like, Where, Order by, and Return" clauses in a "FLWOR" expression.
XPath analyzes an XML document as an XML tree by representing each element of the XML document as a node in the XML tree. The XML tree may include parent-child nodes that directly correspond to the nested elements in the XML document. For more information regarding XPath and XQuery please visit their standards web pages which currently reside at http://www.w3.org/TR/xpath20/ and http://www.w3.org/TR/xquery/ respectively.
An XML pivot join procedure provides efficient filtering of XML documents that satisfy an XPath or XQuery expression. The XML pivot join procedure uses an XML index scan to filter an index for each leg in an expression. For example, given an XPath expression, "/a/b[(c=5) AND (d=6)]," and a collection of XML documents, an index will be filtered by performing an XML index scan on the index relating to "/a/b/c=5" (the first leg) as well as on the index relating to "/a/b/d=6" (the second leg). Each index will contain information from a qualifying XML document, which information includes the qualifying path, the XML document where the path is located, the node identification of the path, and the value received from the XML document. The XML pivot join procedure will "AND" the index scans thereby advancing the scan of one index based on the information of another.
Several structures are created during the XML pivot join procedure. From the query, a query tree is generated that describes the query in tree representation. Also, a paths table is created during the XML pivot join procedure to describe every unique path in the collection of XML documents. By nature, the paths table includes paths that are both relevant and non-relevant to the query. So, to summarize the relevant paths, a paths tree is created. Entries from the paths table are matched against the query tree and qualifying paths are combined to form the paths tree. A match graph is constructed by finding paths in the paths tree that match steps in the query tree. These structures are used at strategic points throughout the XML pivot join algorithm to identify qualifying documents.
XML pivot joining from an XPath expression produces expected results. However, XML pivot joining from an XQuery FLWOR expression may not produce expected results. That is, when pivot joining from an XQuery FLWOR expression, the information to be propagated may not compute properly. For example, given the XQuery FLWOR expression "FOR $a in doc( )//a LET $b in $a//b WHERE $b/c=5 and $b/d=6 RETURN $a," the LET binding $b describes the sequence of one or more "b" nodes underneath "a" nodes of a document. So, the XQuery FLWOR expression searches for "c" nodes and "d" nodes under any of the "b" nodes that are under "a." In other words, the "c=5" match and the "d=6" match does not necessarily need to be under the same "b" node.
Detrimentally, certain XML documents that, in theory, should satisfy the XQuery FLWOR expression do not. When the XML pivot join algorithm applies the "AND" operation on the indexes, evaluation of the subsequent leg of the expression relies on the information obtained from the evaluation of the prior leg. So, if the information obtained from evaluating the prior leg results in "Document 1" satisfying the "/a/b/c=5" path, then the subsequent expression would rely on that information to find the "/a/b/d=6" path by starting at the node location for the path "/a/b." This necessitates having the "c=5" match and the "d=6" match under the same "b" node. But, when evaluating an XQuery FLWOR expression, the "c=5" match and the "d=6" match are not required to be located under the same "b" node. The "c=5" match and the "d=6" match can be under different parent nodes to qualify a document; however, current implementations of the XML pivot join procedure exclude the document.
FIGS. 3 through 10 are provided as an example of the XML pivot join procedure. Using the XML documents in FIG. 3 and an XPath query: //x[.//v[b="b" and c="c"] and .//a="a"], a query tree (see FIG. 4) is constructed. A double bar represents a descendant axis and a single bar represents a child axis. A paths table (see FIG. 4) is also constructed. The paths table describes all the unique paths within the collection of XML documents in FIG. 3. To summarize all of the paths relevant to the query, a paths tree is created. The query tree facilitates parsing the XPath query into linear XPaths. The linear XPaths derived are //x[.//v[b="b"]], //x[.//v[c="c"]], and //x[.//a="a"].
Paths in the paths table matching the linear XPaths derived from the query tree comprise the paths tree. Thus, the paths tree summarizes all the unique paths in the collection of XML documents that are relevant to the XPath query. XML index entries are created for each linear XPath in the XPath query. Each index entry includes a path, which is the unique path that matched the linear XPath; a value, which is the value of the last document node in the path; a document identifier, which is the document identifier of the XML documents that contains the path; and a node identifier, which is the identifier of the node in the XML document that is in the path.
FIG. 5 depicts the XML index entry's relations to the XML documents and paths of the paths tree. For the first entry, the path z-e-x-p-v-b describes the first matching (unique) path for the linear XPath //x/v/b. For discussion purposes, the labels within the path with numbers have been subscripted in FIG. 5 to show the unique instances of that label. For the linear XPath //x/v/b for example, there are a number of matching paths: z-e-x-p-v-b is the first matching path, so it is subscripted with "1"; the paths tree has the z-e-x-p-v-b path so it is subscripted as z-e-x1-p1-v1-b1. The second match for //x/v/b is z-e-x-q-v-b, so it is subscripted as z-e-x1-q1-v2-b2. The "v2" indicates that this path is the second unique path for "v," and "b2" indicates that this path is the second unique path for "b."
From this point on, the paths that match a linear XPath will be referenced using the last subscripted label. For example, to refer to the path z-e-x1-p1-v1-b1 above, the reference will be to the "b1" path. Likewise, for the path z-e-x1-q1-v2-b2, the reference will be to the "b2" path.
The first entry in the XML index in FIG. 5 indicates that the "b1" path has the value "b" at document 1 at nodeID 126.96.36.199.1.1.1. An explanation of nodeIDs may begin at document 1. Node "z" has nodeID 1.1. Node "e" has nodeID 1.1.1, node "x" has 184.108.40.206 (because node "aa" is 220.127.116.11). Node "p" has 188.8.131.52.1, node "v" has 22.214.171.124.1.1 and node "b" has 0.1.1.2.1.1.1. Note that nodeIDs are ordered, that is 1.1.1<1.1.2<22.214.171.124 and so on, and that parent nodeIDs are easily computed from any descendant. That is from "b1" which has nodeID 188.8.131.52.1.1.1, the nodeID of "x1" can be computed by truncating the nodeID from 7 digits to 4 digits (7 nodes along the path to the "b" document node, and 4 nodes along the path to the "x" document node). So, the nodeID of "x1" is 18.104.22.168.
Note that for the "b1" path, there are a number of XML index entries. The first "b1" entry points to document 1, nodeID 188.8.131.52.1.1.1. The second "b1" entry points to document 2 nodeID 220.127.116.11.1.1.1. This says that the indexes have found the "b1" path in both document 1 and document 2. From here on, instead of showing the XML index entries and their paths and locations, the subscripted paths along the xml document paths will be shown (see FIG. 6).
In FIG. 6, the matches for the linear XPath //x//v/b can easily be seen. There is a path "b1" at document 1, "b3" at document 1, "b1" at document 2, and so on. For the linear XPath //x//v/c, there is a path "c1" at document 1, "c1" at document 1, "c1" at document 2, and so on. For the linear XPath //x///a, there is a path "a2" at document 2, "a2" at document 3, "a4" at document 4, and so on. Further referencing the way the algorithm advances the XML index scans will occur by saying that the "b1" scan is currently at the first "b1" in document 1, then at the first "b1" at document 2 and so on. The XML pivot join procedure has one index scan open for each unique path. So, the "b1" paths use one index scan, the "c1" paths use one index scan, the "b2" paths uses one index scan, and so on.
In FIG. 7, a query tree and a paths tree are used to construct a match graph. The match graph is constructed by finding matching paths in the paths tree with steps in the query tree. The "b1" node in the match graph, for example, signifies the match between the "b1" path in the paths tree with the "b" step in the query tree. The match graph is used to remember document and node locations while performing the XML index scans. For example, if the index scan for "b1" is advanced and the index scan returns document 1, the location will be remembered, document 1 (and the nodeID of the "b1" match) in the match graph node "b1." The match graph node "b1" is at location document 1.
A running example may be useful as it shows the XML pivot join procedure in detail. The following examples will show snapshots of the match graph and describe how the document locations are computed and how the index scans are advanced. The diagram of the xml documents in FIG. 6 will be used repetitively to help track what is being pointed to with the XML index scans.
In FIG. 8, the progress of the match graph occurs from left to right. The leaves of the match graph correspond to the index scans. For the initial match graph on the left of FIG. 8, the "b1" index scan is at "doc1." The "c1" index scan is also at "doc1." The "b2" index scan is at "doc2," the "c2" index scan is at "doc2," and the "a1" index scan is at "doc5." The locations for the index scans show that the first "b1" path is at document 1, the first "c1" path is at document 1, the first "b2" path is at document 2, the first "c2" path is at document 2, the first "a1" path is at document 5, and so on.
In the match graph snapshot to the right, the location of "b1" has been truncated to the level of "v1." It is apparent that this matched the nodeID computed from the truncation of the nodeID of "c1" to the level of "v1." This match is depicted in location with an asterisk (*) at "v1." This says that a "b1" path and a "c1" path are found to have the same "v1" ancestor at document 1, as can be seen in FIG. 6. A similar occurrence is seen for "v2." To compute for the location of "x1", the minimum locations of (a1, a2) and minimum locations of (v1, v2) are taken, then the maximum of these minimums is taken. So "x1" is at doc2. To compute for the location of "z," take the minimum of (x1 and x2), so "z" is at doc2. Note that neither "x1" nor "z" has the asterisk because "x1" does not have a "v" match and an "a" match under the same "x" match.
Now that all the index cursors at the leaves of the Match Graph have been advanced once (without returning results), the cursors may again be advanced. The initial match graph (the match graph on the left) in FIG. 9 now shows that the "b1" index cursor has been advanced to doc3 based on the maximums of the ancestor matches. In FIG. 9, doc2+ depicts the fact that the XML pivot join procedure advanced the "z" location to some location just above doc2, so the cursors on the leaves can be advanced beyond its previous location. In other words, the location of the "z" match needs to be advanced beyond doc2. By advancing "b1" to doc3, the subsequent match graph (the one on the right) in FIG. 9 is realized and the ability to compute the location of "x1" based on max(min(v1, v2), min(a1, a2)) is achieved. Here we see that there is an "a2," a "b2," and a "c2," at doc2 that have the same "x1" ancestor, while "b2" and "c2" have the same "v2" ancestor.
So, now "x1" has the asterisk (*). The location of "z" is computed from min(x1, x2) and the doc2 for "z" is received. A result for the XPath //x[.//v[b and c] and .//a] may be returned because a "b2" and a "c2" under the same "v1" has been found and the "v1" and "a2" have the same "x1" ancestor. So, the first match for the query //x[.//v[b and c] and .//a] is document 2.
Advancing the location of "z" to doc2+ to advance the index scans is required. This time a "b4" and a "c4" is found at document 5 with the same "v4," and an "a3" at document 5 with the same "x2" as "b4." So, document 5 can be returned as a match for the query //x[.//v[b and c] and .//a]. This example of the XML pivot join procedure was applied to an XPath query. The XML pivot join procedure produces expected results when applied to an XPath query. However, as noted above, desired results are not produced when the XML pivot join procedure handles a LET binding used in a WHERE clause of an XQuery FLWOR expression.
Using the collection of XML documents in FIG. 6 and an XQuery FLWOR expression: "for $x in doc( ) //x LET $v in $x //v WHERE $v /b="b" and $v /c="c" and $x //a="a" RETURN $x;", the undesired results will be apparent. The expression comprises a $v binding which is a LET binding. The expression "says" that for the predicate "$v /b='b' and $v /c='c'" the "b" and "c" matches are under a sequence of one or more "v" matches. Document 3 in FIG. 6 should now qualify because "b1" and "c1" are under a sequence of "v1" nodes under an "x1," and "a2" is under the same "x1." When applied to the XPath query, the XML pivot join procedure properly skipped Document 3 because "b1" and "c1" for Document 3 are not under the same "v1" node. However, when applied to the XQuery FLWOR expression, Document 3 is improperly skipped.
From the foregoing discussion, Applicants assert that a need exists for a method and apparatus that properly handles a LET binding used in a WHERE clause of an XQuery FLWOR expression during an XML pivot join procedure.

Method and apparatus for handling a LET binding

International Business Machines Corporation


An airbag apparatus to be applied to a vehicle includes airbags, a pre-crash determiner, an airbag deployment controller, and an airbag contraction controller. The airbags are configured to be deployed forward of a vehicle body front of the vehicle, and are disposed in a vehicle width direction. The pre-crash determiner is configured to establish a pre-crash determination when a probability of a collision with an object is a predetermined value or higher. The airbag deployment controller is configured to deploy the airbags in response to establishment of the pre-crash determination. The airbag contraction controller is configured to control contraction of the airbags individually, and perform side airbag contraction control by contracting one of the airbags that is on one side in the vehicle width direction and in a region where the collision with the object is occurring, and keeping deployed another one or more of the airbags in the region.

The disclosure relates to an airbag apparatus including airbags deployable outward from a vehicle body front of a vehicle such as an automobile.
As a technique regarding an airbag apparatus deployable out of a vehicle such as an automobile, for example, Japanese Unexamined Patent Application Publication No. 2006-219119 discloses use of a plurality of airbags, which are deployable in front of a front bumper and disposed in a vehicle width direction. In the event of a collision of the vehicle with a pedestrian or the like, the airbags serve to prevent the pedestrian or the like that has been bumped up from falling down and injuring the head and face, for example.
Japanese Unexamined Patent Application Publication (Translation of PCT Application) (JP-T) No. 2008-526593 discloses that a plurality of airbags are deployed around a vehicle body so as to prevent damage to the vehicle body during a collision.


A fuse element has a first region, a second region and a third region. The first region is a portion for isolating circuitry. The second region and the third region are respectively connected to both ends of the first region and have a wider pattern width than that of the first region. The second region, the first region and a part of the third region of the fuse element are formed on a thick insulating film, while the remaining part of the third region is formed on a thin insulating film. Heat generated in the fuse element is less likely to be released to a semiconductor substrate through the thick insulating film, but is more likely to be released to the semiconductor substrate through the thin insulating film. The fuse element therefore has a large temperature change and a large temperature gradient. This facilitates electrical blowing of the first region.

The present invention generally relates to a semiconductor device having a fuse element, and a manufacturing method thereof. More particularly, the present invention relates to a semiconductor device having a fuse element which is formed from a semiconductor layer such as polysilicon, a metal layer such as silicide, or a laminated structure of a semiconductor layer and a metal layer, and a manufacturing method thereof.
Fuse elements have been used in semiconductor devices in order to designate a bit for using a redundant circuit of memory circuitry, to adjust a resistance of analog circuitry, to activate functions of logic circuitry, and the like. By forming a fuse element simultaneously with elements such as a transistor in the same semiconductor device, an electric resistance of the fuse element can be adjusted from the outside after the semiconductor device is manufactured and tested, so that operation of a desired function can be controlled.
A polysilicon fuse element which is electrically blown by laser treatment, an anti-fuse element which is formed between lower and upper electrodes and blown by dielectric breakdown of a thin film insulator, and the like have been used in semiconductor devices. With recent improvement in integration and miniaturization of semiconductor devices, however, such kinds of fuse element are going to be replaced with a fuse element having a polysilicon resistor of an elongated shape. This kind of fuse element is blown by heating the polysilicon resistor to its melting point or higher by Joule heat generated by applying a current to the polysilicon resistor (for example, refer to Japanese Patent Laid-Open Publication No. 2000-40790). Hereinafter, this kind of fuse element is referred to as an electric fuse element in order to distinguish this kind of fuse element from a fuse element which is blown by laser treatment and an anti-fuse element.
In such an electric fuse element, a fuse portion (a portion of a fuse element for isolating circuitry) formed from a polysilicon resistor need not be completely blown. The fuse portion is melted and thinned by heat generated by applying a current, thereby increasing a resistance value.
FIGS. 7A and 7B show a semiconductor device having a conventional electric fuse element. FIG. 7A is a plan view and FIG. 7B is a cross-sectional view taken along line C-C in FIG. 7A. Note that FIG. 7A does not show a first interlayer insulating film 104 and a second interlayer insulating film 108 shown in FIG. 7B. Metal wirings 107a, 107b are shown by dotted line in FIG. 7A.
Referring to the plan view of FIG. 7A, the conventional electric fuse element 103 is formed from a first region 103a, a second region 103b and a third region 103c. The first region 103a serves as a fuse portion. The second region 103b and the third region 103c are provided on both sides of the first region 103a, and each serves as a region where a contact is to be formed (hereinafter, referred to as a contact formation region). The first region 103a of the electric fuse element 103 has a narrower pattern width (a width in the vertical direction of the figure) than that of the second region 103b and the third region 103c. Five contact plugs 106a, 106b are provided in a row in the vertical direction of the figure on the second region 103b and the third region 103c, respectively.
Referring to the cross-sectional view of FIG. 7B, the semiconductor device having the conventional electric fuse element 103 includes a semiconductor substrate 101, an insulating film 102, an electric fuse element 103, a first interlayer insulating film 104, contact holes 105a, 105b, contact plugs 106a, 106b, metal wirings 107a, 107b, and a second interlayer insulating film 108. The insulating film 102 is formed on the semiconductor substrate 101. The electric fuse element 103 is formed on a part of the insulating film 102. The first interlayer insulating film 104 is formed on the insulating film 102 and the electric fuse element 103. The contact holes 105a, 105b extend through the first interlayer insulating film 104 to the second region 103b and the third region 103c, respectively, each of which serves as a contact formation region. The contact plugs 106a, 106b are formed from a conductive material such as tungsten, and fill the contact holes 105a, 105b, respectively. The metal wirings 107a, 107b are formed on a part of the first interlayer insulating film 104 so as to contact the contact plugs 106a, 106b, respectively. The second interlayer insulating film 108 is formed on the first interlayer insulating film 104 so as to cover the metal wirings 107a, 107b.
In the above conventional electric fuse element 103, however, it is hard to blow the first region 103a which serves as a fuse portion, and therefore a desired resistance value can not be obtained.

Matsushita Electric Industrial Co., Ltd.


A method for operating a plurality of energy storage devices includes controlling operation of the plurality of energy storage devices connected in series by independently varying a current and/or bypassing and/or reversing a polarity of at least one of the plurality of energy storage devices without a corresponding change in current, bypass, or reversal of polarity of one or more of the other energy storage devices connected in series.

Electrical energy storage in the form of chemical batteries often expresses a wide range of voltage as a function of chosen chemistry, charge/discharge current and state of charge. While the simplicity of a power grid-tie inverter connected directly to battery cells stacked in some arrangement may be attractive, battery voltage characteristics often make this difficult

Series connected storage interface converter


A rocker arm is swingably supported by a control shaft that has an eccentric control cam formed thereon. The rocker arm is swung by a torque of a crankshaft of the engine. Two swing cams are swingably supported by a drive shaft and actuate respective engine valves to make an open/close operation of the same by receiving the swinging movement from the rocker arm. The rocker arm comprises a cylindrical base portion through which the control shaft passes; a first projected end that is provided at a first radially outside part of the cylindrical base portion in the vicinity of one axial end of the cylindrical base portion, the first projected end receiving the torque from the crankshaft for carrying out the pivotal movement of the rocker arm; and two second projected ends that are spaced from each other and provided at a second radially outside part of the cylindrical base portion, the second projected ends actuating the two swing cams when the rocker arm is swung. The first and second radially outside parts are opposite with respect to an axis of the cylindrical base portion.

1. Field of the Invention
The present invention relates in general to valve actuation devices of an internal combustion engine, and more particularly to valve actuation devices of a type that eliminates or at least minimizes dispersion in a valve lift degree of intake and/or exhaust valves of the engine.
2. Description of the Related Art
In order to clarify the task of the present invention, one known valve actuation device of an internal combustion engine will be briefly described, which is shown in Japanese Laid-open Patent Application (Tokkai) 2002-38913.
The valve actuation device of the publication generally comprises a drive shaft that is synchronously rotated by a crankshaft, an eccentric drive cam that is mounted on the drive shaft, and two swing cams that open and close two intake valves for each cylinder. The two swing cams are rotatably disposed on the drive shaft having the eccentric drive cam put therebetween.
A multi-link type power transmission mechanism is further provided for each cylinder, which swings the two swing cams by receiving a power from the eccentric drive cam.
The multi-link type power transmission mechanism generally comprises a rocker arm that is arranged above an intermediated position of the two swing cams and swingably disposed on a control shaft, a link arm that pivotally connects an end portion of the rocker arm to the eccentric drive cam and a link rod that pivotally connects a forked other end of the rocker arm to each of the swing cams.
The control shaft extends along a longitudinal axis of the engine, and is rotatably supported by bearings that are arranged on an upper part of a cylinder head of the engine. The control shaft has an eccentric control cam for each cylinder, which serves as a swing fulcrum of the rocker arm.
An electric actuator is further provided, which, in accordance with an operation condition of the engine, turns or pivots the control shaft changing an angular position of the control cam, so that the valve lift degree of each intake valve is varied in accordance with the engine operation condition.
The above-mentioned Laid-open Patent Application proposes several types of power transmission mechanism for achieving the above-mentioned function.

Valve actuation device of internal combustion engine