A method and system for servo error integration in read-channel equalization are described. In the present invention servo error is integrated into an equalizer. Also described in the present invention are methods and systems for determining the servo error.

1. Field of the Invention
The present invention relates to read-channel signal processing in media storage systems. More particularly, the present invention relates to a method and system for improved read-channel equalization through integration of servo information.
2. Description of Related Art
Data/media storage systems such as hard disk drives (HDDs), compact disks (CDs and CD-ROMs), digital video disks (DVDs), magneto-optical disks, etc., read and write data using magnetic or optical transfer techniques. In the case of magnetic media the process of reading the data involves measuring the magnetic field generated by the recorded data. In the optical media case the process of reading the data involves measuring the optical reflection properties of the recorded data as the data is lit by a laser beam.
Regardless of the technology used to read the data, once the data is read the measured signal is converted into an electrical signal (read signal). The electrical/read signal is then processed to infer the value of the data that was read (detected symbols). This is referred to as read-channel signal processing.
FIG. 1 illustrates a prior art read channel signal processing procedure. Data is stored in the media storage system as binary data 110. The data is accessed using either the magnetic or optical media processes. In FIG. 1, read-channel 120 represents the modulation process where the magnetic or optical flux is written on the medium and the magnetic or optical signal is measured. The read-channel 120 also represents the conversion of the measured magnetic or optical signal into a filtered and sampled electrical signal referred to herein as the read signal 130.
Next, the read signal 130 is processed to infer the value of the data that was read i.e., detected symbols 150. The read-channel processing scheme illustrated in FIG. 1 for inferring the value of the data that was read to arrive at the detected symbols 150 is referred to as Partial Response Maximum Likelihood (PRML) detection 140. PRML detection 140 incorporates a linear partial response equalizer 145 followed by a Viterbi detector 146. Other prior art methods for read-channel processing include Decision Feedback Equalizer (DFE) and Finite Delay Tree Search (FDTS). Such read-channel processes work in similar fashion to the PRML processes and are not discussed in detail herein.
Such read-channel signal processing systems suffer from Inter Symbol Interference (ISI) and noise that makes it difficult for the system to detect each written symbol. Thus, the read-channel processing systems have a corresponding error rate associated with the fact that the detected symbols 150 do not always match the values of the binary data 110 that was written. To decrease the error rate associated with read channel signal processing systems, such systems use models of the read channel to model the dynamic relationship between the actual value of the recorded data and the corresponding measured value of the electrical signal (read signal). The accuracy of these models greatly influences the Bit Error Rate (BER) of the read process. The BER is the ratio of the number of data bits whose inferred value was incorrect over the total number of data bits that were read and processed.
FIG. 2 illustrates a model used in prior art read-channel processing systems. Read channel model (model) 200 typically is a linear model 240 with additive white noise 220. The concepts and processes of modeling are known in the art and are not discussed in detail herein. Model 200 and the processes of model 200 would be used within the read channel 120 illustrated in FIG. 1. In FIG. 2, model 200 represents the assumption that the read signal 230 is produced by passing the binary data 210 through a linear filter 240 and then adding white noise 220.
In prior art media storage systems read-channel signal processing is performed separately from servo processing. Consequently, in prior art read-channel signal processing the only source of error considered is the additive white noise discussed above. By separating the read-channel signal processing from servo processing, the read-channel equalization does not take into account the servo error of the read-head (i.e., actuator head) during processing of the read data. The servo error is the error between the actual position of the head and the desired position of the head on the media storage device. As track pitch is reduced to increase density, the tracking (or position) errors become a significant portion of the track pitch. In systems with reduced track pitch, during real-time operation the actual value of the servo error fluctuates widely due to controller design limitations and external disturbances. The position of the actuator head during a read and/or write operation will affect the value of the data read and/or written.
The positioning and motion of the magnetic or optical heads that read and/or write the data are controlled using sophisticated feedforward and feedback control methods (control methods). The main objective of these control methods is to minimize the servo error and improve the data access time of the system. The servo error, as stated earlier, is the error between the actual position of the head and the desired position of the head on the media storage device. The data access time is the amount of time that passes from the moment the command for reading and/or writing the data is issued to the moment that the data is actually read and/or written.
FIG. 3 illustrates an example of servo error, or positioning error on a rotating media storage device, for example a disk drive. It should be noted that servo error occurs on other media storage devices and that the example of a rotating media storage device such as a disk drive is merely meant to be illustrative and not limiting. It should also be noted that the systems described herein exchange the information on the servo error or positioning error as signals and thus the discussions herein may refer to the servo error or positioning error as the servo error signal or positioning error signal (PES), respectively.
Illustrated in FIG. 3 is an enlarged version of a xe2x80x9ctrackxe2x80x9d 310 on a storage disk. In approximately the center of track 310 is a dashed line 320 which represents the data stored on track 310. Actuator head 330 is illustrated in FIG. 3 as being located directly above the center of track 310 where the data 320 is stored and is also located on a servo wedge 350.
A servo wedge is like a xe2x80x9cmarkingxe2x80x9d on a disk (usually placed there at the time of manufacture) that delineates position on a disk. For example, a servo wedge in a magnetic recording media has a stronger magnetic field than other regions of the magnetic disk so as to delineate position. In the magnetic disk example, when a system senses the stronger magnetic field (i.e., the actuator head passes over a servo wedge) the position of the actuator head can be measured (or xe2x80x9csampledxe2x80x9d) by the system. Based upon the signal detected at the servo wedge the position of the actuator head within the track can also be determined. In other words, the system is able to detect if the actuator head is on the center of the track or is off the center of the track. If the actuator head is off center, the system will also be able to determine which direction from center and by approximately how much the actuator head is off center. When a servo wedge passes under the actuator head, this occurrence is referred to as a xe2x80x9cservo burstxe2x80x9d.
It should be noted that the only time the position of the actuator head can be measured is at the point of a servo burst, and such measurements are referred to herein as xe2x80x9csampled dataxe2x80x9d. Based upon the sampled data the system can determine the position error (PES) of the actuator head.
In FIG. 3, servo bursts are represented as squares having an xe2x80x9cxxe2x80x9d thereon. The actuator head during read and/or write does not necessarily remain directly above the stored data 320 but instead fluctuates. For example, the path of the actuator head (positions 330-339) in FIG. 3 is illustrated as having an almost sinusoidal function as the head follows the track 310. It should be noted that the path of the actuator head may vary from system to system and that the path illustrated in FIG. 3 is meant merely to be illustrative and not limiting.
When the actuator head is not at the center of the track there is a positioning error 360 (servo error) that represents the distance the head is from the center of the track. This servo error 360 contributes to read channel errors. The further the actuator head is from the center of the track the greater the chance for error in reading and/or writing the stored data. As the servo error becomes larger, the ability of these prior art media storage systems to accurately read the data diminishes, and the BER increases. Additionally, as track pitch is reduced, and bits are packed more closely on the track, BER increases due to the combined effects of servo position error and intersymbol interference.
In other words, although seemingly unrelated, the servo error control system has a direct impact on the read-channel signal processing system of a media storage system. This is due to the fact that the read-channel model used for data processing is greatly influenced by the servo error. In particular, the magnetic or optical signal generated by the actuator head as it passes over the location of the data becomes weaker as the servo error becomes larger. Thus, the servo error plays a major role in the process of read-channel equalization, where the effects of the read-channel on the measured signals are removed or equalized before a decision is made about the value of the data (detected symbols).
However, most media storage systems have a separate design for the servo control system from the read-channel signal processing system. Without linking the two together, the read signal equalizer does not have access to the valuable information about head position which would enable the equalizer to improve the BER.
Because the prior art read-channel signal processing systems do not take into account the servo error there are several disadvantages. One disadvantage is the fact that in order to ensure that the BER on such read-channel systems will remain within pre-specified bounds, the performance requirements on the servo control loop become unnecessarily conservative, leading to increased data access times and decreased track density.
Another disadvantage is that, due to servo control limitations, the power in the servo error signal cannot be arbitrarily reduced. Since all the power from the servo error signal is perceived as noise in these prior art read-channel equalizers, the performance of the read-channel equalizers in terms of the BER is unnecessarily low. Consequently, this leads to lower linear bit density on the track.
What is needed is a method and/or system that integrates servo error estimation with read-channel equalization to improve the linear bit density and track density of a media storage system.
A method and system for servo error integration in read-channel equalization are described. Servo error is integrated into a read-channel equalizer.
Other features and advantages of the present invention will be apparent from the accompanying drawings, and from the detailed description, which follow below.

Servo error integration in read-channel equalization


For analysis of small quatities of target analytes in an environment, the gas flow can be delivered to a suitably fast analyzer and their concentration determined in a time period whose duration is dependent on the analyte, its concentration and the phase separation properties. A device having a sorbent bed that is essentially concentric with a passage way containing thermal fluid is used to concentrate the target analyte.

The present invention relates to an apparatus for sampling particle-laden gas flows and concentrating trace organic species within that flow for subsequent analysis by gas phase detectors.
Environmental sampling for target chemical species often requires knowledge of gas/particle phase partitioning. The partitioning of target chemicals such as pollutants between the gas phase atmosphere and the surfaces of particles has implications in study and analysis of transport model predictions, atmospheric reaction modeling, and evaluation of pollutant formation/evolution mechanisms. The actual partitioning of these target chemical species between gas phase and condensation/absorbed solid phase as a function of their vapor pressure, concentration and solubility are important aspects in such studies. System temperature and characteristics of the absorptive particle surfaces are also important factors in partitioning. Sampling methods to determine the concentration and/or partitioning of the target chemicals can affect the actual partitioning. Sampling systems which operate with a particle filter allow accumulation of particulate solids during the sampling episode, which may last over 3 hours. These particles can act as sorptive surfaces for gas phase targets through condensation or absorption/reaction phenomenon ("blow-on"), thereby transferring the target analytes to the solid phase. (See, for example, articles by Cotham & Bidleman in Eniron. Sci. Tech. 24, p 342 and Gundel, et al., Atmos. Environ. 29, p. 1795 (1995).) Alternatively, the filter surfaces can lose particle-bound volatile target analytes to the downstream collection media ("blow-off"), thereby biasing results toward gas phase partitions as described by Eatough, et al., (Organic Chemistry of the Atmosphere CRC Press, 1999). These sampling artifacts introduce bias into determinations of phase partitioning of volatile and semi-volatile compounds.
For analysis of target species, concentration methods are often employed to bring the quantity of target above the analytical detection limit of the apparatus. This includes methods such as cryogenic focusing, pressure swing absorption as described by Keefer in U.S. Pat. No. 4,968,329, which is incorporated herein by reference, and sorbent collection as described by Sides, et al., in U.S. Pat. No. 5,014,541 and Pleil, et al., U.S. Pat. No. 5,447,556 (extraction/solvent evaporation), both of which are hereby incorporated by reference. These methods teach gas phase target concentration, but do not address maintaining and preserving the distinction in the trace organic species phase (vapor or condensed on particles) as exists at the point of sampling.
There are some sampling methods that address phase partitioning of targets. The standard EPA (Environmental Protection Agency) method train (U.S. EPA, Test Method 0032A) consists of a filter housing through which the particle-laden gas stream passes followed by an absorbent media. This method can provide a gas versus particle phase distribution, but can suffer considerable bias from the blow-off and blow-on phenomena discussed above, and, hence, is not purported as a method for discerning analyte phase partitioning. As an alternative, denuder sampling has been developed in an effort to continually separate gas phase targets from the solid phase targets. Annular denuders consist of one or more channels through which both gasses and particles pass. The denuder surfaces may be coated with a thin layer of fine absorbent. The denuder principle relies on the relatively faster diffusion of the gas phase target to the denuder wall than that of the exposure of particles to the wall in this laminar flow regime. In this manner, the gas phase components are separated from the particle stream. In most denuder applications, the particle stream is filtered and followed by a sorbent that catches target analyte blow-off. The denuder surface can be solvent-extracted and analyzed for the target components in the vapor phase or vapor phase components can be determined simply by the difference of the post-denuder filter catch and a separate total sample catch. Bias in denuder operations results from fine particle diffusion to denuder walls (estimated at 10% for 0.1-0.05 m particles), volatilization of target analytes from particles during transit through the denuder channels, and breakthrough of the volatiles from the denuder to the downstream adsorbent.
A method of particle segregation of gas streams is taught to create a particle-free stream and a particle-rich stream in a method (U.S. Pat. No. 5,746,789 to Wright and Crouch, which is incorporated herein by reference). That method of segregation increases the relative gas to particle velocity, thus exacerbating concerns over particle blow-off and blow-on.
Many filters have been taught as providing means for avoiding pressure drop caused by the buildup of particles of simply as means of particle filtration. Some moving filters include self-cleaning processes (U.S. Pat. No. 5,560,835). The references show intent only to limit pressure drop due to particle buildup on the filter. None of the references teach a method for limiting gas flow through previously filtered particles, thereby minimizing blow-off and blow-on complications.

Apparatus and methods for use in concentration of gas and particle-laden gas flows

The United States of America as represented by Environmental Protection Agency


An inkjet printer in which an ink cartridge is allowed to communicate with a recording head through a hollow needle member when the ink cartridge is thrust and attached into a body casing. In a support member of the body casing which supports the ink cartridge, an ink outlet having a concave shape open at the top is provided in a position vertically under the needle member. An ink absorber is provided on at least the bottom surface of the ink outlet.

1. Field of the Invention
The present invention relates to an inkjet printer, and particularly relates to an inkjet printer in which ink in an ink cartridge is supplied to a recording head through a needle member.
2. Description of the Related Art
There has been hitherto known an inkjet printer in which an exchangeable ink cartridge is attached into a main body of the inkjet printer, and ink in the ink cartridge is supplied to a recording head through a hollow needle member, as disclosed in JP-A-Hei.11-58762 and the like.
According to JP-A-Hei.11-58762, a recording head for ejecting ink to thereby perform recording on a recording medium such as a sheet of paper is mounted on a carriage provided movably forward and backward in the width direction of the recording medium. An ink cartridge mounting portion where an ink cartridge for supplying ink to the recording head will be removably attached is provided on the carriage. A hollow needle member is provided in the cartridge mounting portion. Then, when the ink cartridge is attached to the cartridge mounting portion, the needle member is thrust into the ink cartridge so that the ink is guided to an ink channel through the needle member and supplied to the recording head.


When the output of the AFR ratio sensor is stable in a steady operating state, the amount of fuel is increased by step inputting to detect a point where the gradient of change in the sensor output exceeds a threshold value as a point of start of change. The time from the timing of increasing the fuel until the point of start of change is detected as a dead time. A response time is calculated until the amount of change in the sensor output reaches a predetermined ratio of the amount of change (AA−BA) of up to the steady value AA of the sensor output after the amount of the fuel is increased from the steady value BA of the sensor output before the amount of the fuel is increased. The fail condition in the AFR ratio sensor is determined based on the dead time TA and the response time TB.

In modern electronically controlled automobiles, a sensor is provided in an exhaust pipe to detect the air-fuel ratio or the oxygen concentration of the exhaust gas emitted from an internal combustion engine, and the amount of the fuel fed to the internal combustion engine is controlled by feedback relying upon the sensor output, so that the air-fuel ratio of the exhaust gas is maintained near a target air-fuel ratio in order to improve the engine performance such as emission of the exhaust gas and the fuel efficiency. The modern air-fuel ratio feedback control systems are designed by modeling the response characteristics according to which the air-fuel ratio of the exhaust gas varies following a change in the amount of feeding the fuel which is the object to be controlled, after the dead time+1st-order delay characteristics (or 2nd-order delay characteristics). Therefore, if the response characteristics of the sensor vary due to deteriorated characteristics of the sensor that detects the air-fuel ratio of the exhaust gas or due to the faulty sensor, the precision for detecting the air-fuel ratio is deteriorated and, hence, the precision for controlling the air-fuel ratio is deteriorated, causing a deterioration in the engine performance.
JP-8-177575A discloses a method according to which a change in the sensor output (rate of change) is detected after having detected a change in the amount of fuel fed into the internal combustion engine (beginning of fuel cut or end of fuel cut) to determine the deterioration in the response characteristics of the sensor.
According to the method of detecting sensor response characteristics disclosed in JP-8-177575A, however, a change in the sensor output is simply detected after a change in the amount of fuel supply without detecting the response characteristics (dead time and the 1st-order delay characteristics or the 2nd-order delay characteristics) on which the design of the air-fuel ratio feedback control system is based. It is therefore difficult to precisely detect the deterioration in the air-fuel ratio feedback controllability caused by the deteriorated response characteristics of the sensor or by the faulty sensor. Further, the above method is not detecting the response characteristics (dead time and the 1st-order delay characteristics or the 2nd-order delay characteristics) on which the design of the air-fuel ratio feedback control system is based. It is therefore difficult to detect the response characteristics or to correct the air-fuel ratio feedback control parameter relying upon the response characteristics that are detected.

Device for detecting response characteristics of sensor


Disclosed is a method of producing carbide and carbon nitride powders containing a binder, and cermet obtained from the same.

1. Field of the Invention
The present invention relates to a method of producing carbide and carbon nitride powders containing a binder, and cermet obtained from the same. In more particular, the present invention relates to a method of producing carbide and carbon nitride powders containing a binder, which are used in cermet serving as the material of a cutting tool or a mold, and cermet obtained from the same.
2. Description of the Related Art
Cermet is a compound word of ceramic and metal, which is expressed in English. The cermet refers to a sintered composite materials composed of ceramic mainly including Ti-based carbide, nitride, or carbon nitride, and metal such as nickel (Ni), cobalt (Cc), or iron (Fe).
Since the cermet has several superior properties such as abrasion resistance, the affinity with a workpiece, and a long-term stable life span, the cermet has been spotlighted in a machining field.
In detail, the cermet has a bonded phase of solid phase of carbide or carbon nitride based on transition metal such as Ti, Zr, Hf, V, Nb, Ta, Cr, Ho, or W, and metal such as Ni, Fe, or Co. When producing the cermet, the cermet is produced by sintering the mixture of the transition metal-based carbide and carbon nitride, and the metal.
According to the related art, when carbide and carbon nitride powders for the cermet are synthesized, the carbide and carbon nitride powders for the cermet are synthesized through the reaction between a single element and carbon (C) or nitrogen (N2.)
In addition, commercial cermet is produced in the form of the mixture of carbide and carbon nitride based on various elements, and metal such as nickel (Ni), cobalt (Co), or iron (Fe). Accordingly, in order to produce the commercial cermet, the process of mixing various carbides and carbon nitrides, and various metal components is required. However, generally, the mixing process requires a long time (mostly for 24 hours) to ensure the uniformity.
In this case, to produce cermet having uniform composition, the process of mixing single carbide and carbon nitride, with metal is essentially required.
Therefore, as the number of elements for the production of the cermet is increased, ensuring the uniformity of the material for the cermet is difficult. Accordingly, the mixing process to ensure the uniformity of the cermet may be prolonged.
As the related art of the present invention, there is Korea Patent Publication No. 10-1989-0004491 (published on Nov. 6, 1989).

Method of producing carbide and carbon nitride powders containing binder, and cermet obtained from the same

Abstract: The method includes preparing Ti—Ni alloy powders for Ti alloy powders and graphite, planetary-pulverizing the Ti—Ni alloy powders and the graphite, mortar-pulverizing the alloy powders and the graphite which are subject to the planetary-pulverizing, and performing heat treatment for the Ti—Ni alloy powders and the graphite that are pulverized.

Abstract: Cermet, which is made of the composite powders of carbide and carbon nitride/metal including both TiC which is ceramic material and Ni which is metal is provided.

KOREA INSTITUTE OF GEOSCIENCE AND MINERAL RESOURCES


A method and system for cycle slip framing is disclosed. The method includes receiving an asynchronous signal and generating a synchronous pulse after receiving the asynchronous signal. The method further provides that the synchronous pulse be used to affect a bit slip that results in the moving of a character frame in the recovered data of a deserializer. According to one embodiment of the invention, the moving of the character frame is prompted by a single control signal of a clock divider circuit which causes the removal of a single clock cycle of a clock signal supplied to said deserializer.

A particularly useful (and marketable) feature of data communication transceiver (PHY) chips is the receiver's ability to "frame" its outputs upon recognition of a special framing character in the incoming serial data stream. Framing is used in normal-mode to re-frame data in backplane transceivers and is an integral part of the IEEE 802.3z Gigabit Ethernet and Fiber Channel Standards.
Framing is also used for built-in-self-test (BIST) purposes and to this end many transceiver chips (both backplane and port-SONET/SDH) include a PRBS (pseudo-random bit stream) generator in the transmitter channel and a corresponding verification block in the receiver. The function of the verification block is to determine if the received character matches the framing character. If framing is not achieved, then the verification block requests the deserializer block to "slip a bit" from the incoming serial bit stream and thus move the imaginary frame forward by one bit. This process continues until the character presented at the outputs of the deserializer block matches up with the special framing character and at this point framing is said to be achieved. Irrespective of the application, a common and important requirement for the deserializer circuit in the receiver is the ability to move an imaginary character frame across the incoming serial data stream one-bit at a time until framing is achieved.
FIG. 1 is a diagram that illustrates a basic building block component of a pipelined deserializer that uses each cycle of a divided clock to grab successive bits from a serial bit stream. The basic building block of this architecture is the 1-to-2 DEMUX cell illustrated in FIG. 1. The cell consists of 2 D-type flip-flops (DFF) and a latch. FIG. 2 illustrates the functionality of the cell illustrated in FIG. 1 using waveforms.
As is shown in FIG. 1, incoming data 107 is wired to the data inputs of two DFFs 101 and 103. A negative-edge-triggered DFF 101 on the top row clocks the data on the falling edge of clock 109 thereby capturing the "odd" data bits (see FIG. 2, shown as bits a, c and e that are outputs of the negative-edge-triggered DFF) travelling in a serial bit data stream. The positive-edge-triggered DFF 103 on the bottom row clocks the data on the rising edge of clock thereby capturing the "even" data bits (See FIG. 2, shown as bits b, d and f that are outputs of the positive-edge-triggered DFF) travelling in the serial bit data stream. The output of the DFF 101 on the top-row is then passed to a latch 105. The latch 105 is connected so that it goes transparent when the clock goes high. This effectively delays the "odd" data stream by half a clock cycle (see three bottom waveforms in FIG. 2). The outcome of this half-cycle delay is that the "odd" and "even" data streams are both aligned to the rising edge of the clock at the outputs of the 1-to-2 DEMUX cell (see FIG. 2).
A pipelined deserializer is therefore constructed by connecting 1-to-2 DEMUX cells in a tree-like structure as shown in FIG. 3. FIG. 3 illustrates a configuration of four pipelined stages of DEMUX cells that form a 1-to-16 deserializer 50. As is illustrated in FIG. 3, the data streams out of each stage (n=4 stages) in the pipeline move at half the rate of the data streams moving into that stage. The clock rate for each stage is therefore derived by dividing the clock for the previous stage by two. The simplest implementation of the clock divider is a series of toggle flip-flops connected together to form a 4-bit binary ripple counter. The major advantage of this architecture over other architectures (such as full-rate or half-rate) is that each successive stage performs twice as many demultiplexing operations as the previous stage and each successive stage operates at half the speed of the previous stage. This means that most of the demultiplexing operations are performed at speeds much lower than the top-speed of the block which permits much lower power cells to be used.
FIG. 4 shows a conventional implementation as described in U.S. Pat. No. 5,128,940 of a slip-bit mechanism with a pipelined deserializer architecture 407 such as described in FIG. 3. As illustrated in FIG. 4, this architecture uses an EXOR gate (401a-401c) in the clock path of each stage n of the pipeline. The inputs to each EXOR gate are a respective control signal (403a-403c) and a clock signal for that particular stage. If the control signal to a particular EXOR gate is HIGH then the output of the EXOR gate is the inverse of the clock signal input and if the control signal is LOW then the clock signal is simply buffered by the gate (non-inverted). In a 1:2N demultiplexer (deserializer), 2N types of bit-shifts are required. Importantly, n control signals are required in order to effect these bit shifts.
The disadvantages of these conventional cycle-slip schemes include the necessity of employing N control signals and using a framing verification block that is capable of generating them and the requirement that N (EXOR) gates be used to produce the divided clock signals. It should be appreciated that the use of such gates render such circuits not "correct-by-design". This is because it is not feasible to perfectly synchronize both inputs to each EXOR gate (the N control signals and the clock signals). When these inputs are asynchronous, then glitches will appear at the outputs of the EXOR gates. Depending on how narrow or wide the glitches are, the effects on the deserializer will vary. These glitches can lead to one or more invalid data characters appearing at the outputs of the deserializer, which in turn can lead to unwanted system effects such as false framing. When the clock to a particular stage in the pipeline gets inverted, then the timing of the data outputs of that stage are correspondingly shifted. Thus to avoid metastability and to ensure the correct operation of successive stages, it is necessary to include N−1 D-Flip-Flops (DFF) along with the N EXOR gates in order to re-synchronize subsequent stages as is illustrated in FIG. 5, thereby introducing more complexity into the clock generation circuitry; See U.S. Pat. No. 5,128,940.

Method and system of cycle slip framing in a deserializer


The present invention provides a burglarproof lock core structure which forms a curved passage between a key slot of a plug and a lower pin chamber, such that at least a bending concave surface offsetting the center of the key slot is formed at one side, and cone apexes of a plurality of lower pins are extended out of the lower pin chamber and aligned in the wall edge of the key slot. Moreover, a control valve with a cone apex is located at the other end corresponding to the bending surface inside the key slot, such that a key with curvature corresponding to the passage and notches corresponding to the cone apexes is required to open the lock, thereby having the effect of high security of burglarproof.

a) Field of the Invention
The present invention relates to a burglarproof lock core structure, and more particularly to a burglarproof lock core structure which can largely increase the difficulty of being broken through.
b) Description of the Prior Art
Referring to FIG. 1, a conventional lock core comprises primarily a shell 11 and a plug 12 inside the shell 11, wherein an upper pin chamber 13 interconnected with a lower pin chamber 14 are located between the shell 11 and the plug 12. After orderly inserting a plurality of upper pins 131, lower pins 141, and springs 15 into the upper pin chamber 13, a lid 16 is covered on top of the upper pin chamber 13. In addition, a through hole 111 is inside the shell 11, and after inserting the plug 12 into the through hole 111, a C-shaped clip is used to fix at the end. Therefore, in order to open a lock (as shown in FIG. 1A), a key that matches every lower pins 141 and can completely extend into the upper pin chamber 13 is required to pass through a passage 18 formed inside a key slot 121 of the plug 12 to form an aligned gap between the shell 11 and the plug 12.
However, as the passage 18 of the aforementioned conventional lock core is in a straight-line shape, using a straight-line object such as an iron wire can also directly pass through the passage 18 to press every upper pins 131 and easily break through the lock, thereby causing compliant by users.
Furthermore, for inventions such as Taiwan patents 307294 and 403109, only by pressing pins at one side inside a key passage after inserting a flexible key into a lock core, the lock core can be easily broken by an object such as an iron wire. Moreover, as the lock core structure has no key fixing structure, the lock core can be damaged upon using a flexible key.


A medicine bottle for reminding a patient to take a dosage of medicine at a prescribed time includes a disposable bottle and a corresponding disposable cap. The system further includes a mechanism for recording and playing back instructions to take the medicine dosage at the prescribed time and an amplifier electrically coupled directly to the audio recording and playback device, and a transducer electrically coupled to the amplifier. A mechanism is further included for selectively unlocking the lock actuator from a locked position when a present time is within a predetermined number of hours of the prescribed time.

1. Technical Field
This invention relates to medicine bottles and, more particularly, to a medicine bottle for reminding a patient to take a dosage of medicine at a prescribed time.
2. Prior Art
The general purpose of an automated container is to improve patient compliance in taking the appropriate medication on schedule. While taking a particular medication on a regular schedule may seem a simple process, it is often difficult to accomplish, especially when the patient has been prescribed to take several medications. Dosing regimens that require the patient to take different doses of different medications at different times can be particularly confusing. Conventional medication containers designed for a patient's personal use on an out-patient basis do not assist the patient in taking the correct medication at the correct time, particularly when several medications have been prescribed. Based on the above mentioned needs, it would be advantageous to provide a means for assisting a user to verbally record intake instructions for medications.
U.S. Pat. No. 6,529,446 to de la Huerga discloses an interactive medication container or console that hold or otherwise organizes one or more medication vials or containers. Each vial has a memory strip containing medication and prescription information. Each vial can also include a reminder unit that is attached to and portable with the individual vials. The console or reminder unit reads the information strip of the vial and communicates this information to or interacts with a patient to remind them to take the medication. The medication container or reminder unit also gathers or tracks information such as consumption time, quantity remaining, patient feedback, and contraindication information. The medication container or reminder unit interacts with the patient by displaying questions or receiving and recording input from the patient before, during or after a dose of medication is taken. The patient input can be used to modify the dosing regimen for future doses of medication. The medication container reorders medication when the quantity remaining reaches a threshold level. Contraindication information in the memory strip is downloaded to a personal home computer or a hospital or nursing home computer.
Unfortunately, this prior art example is not designed to provide an audible reminder to tell a user to take their medication.
U.S. Pat. No. 6,845,064 to Hildebrandt discloses an improved device for timely medication administration that attaches to any original container cap and that measures and displays elapsed time in response to opening or closing of said original container cap is disclosed. Physical, chemical and labeled characteristics of the original medication vessel are thus preserved as dispensed. This device includes a timing unit, a compression reset switch and a thermoplastic housing for the above with a resilient, flexible, circumferential wall that permits operation of the enclosed compression reset switch. The thermoplastic housing also features a rigid lower lip that allows adhesive attachment to the original lid. Unfortunately, this prior art example is not designed to provide an audible reminder to tell a user to take their medication.
Accordingly, the present invention is discloses in order to overcome the above noted shortcomings. The present invention is convenient and easy to use, lightweight yet durable in design, and designed for reminding a patient to take a dosage of medicine at a prescribed time. The medicine bottle is simple to use, inexpensive, and designed for many years of repeated use.


A blasting cap simulator for use in bomb disposal training. The simulator has a bridge rectifier, a voltage regulator and an RF key fob transmitter. A fuse across the incoming power lines shorts the device and prevents it from activating until the fuse is blown. It then sends an RF signal to an instructor. The transmitter uses the power lines as an antenna to send out the RF signal. The transmitter is protected from the voltage of the power lines by a choke located on each powerline.

Explosive disposal is a dangerous profession. With advances in electronics, learning to disarm and defeat various explosive devices requires great expertise and years of training. There are numerous known electric circuits used to detonate these explosives. They can be activated by time, motion, location, remote control and numerous other triggers.
Explosive disposal technicians spend countless hours training on how to disarm these devices. This training occurs both in the classroom and in simulated real-life situations. It involves analyzing "black boxes" containing trigger circuits. During training the trigger circuit is typically wired to a signal device such as an LED, wire match, buzzer or other device to simulate the blasting cap and explosive. If the technician accidentally triggers the device while trying to disarm it, the signal device will be activated, telling the technician they have failed to disarm the device.
The traditional signal devices have several shortcomings. First, if the training is done in a real-world scenario, the technician will be wearing their bomb disposal protective gear. This protective gear includes a helmet and/or other armored shielding over the technician's head. This shielding restricts the technician's field of vision and ability to hear surrounding noises. If the device is triggered the technician may fail to hear or see the signal device.
Second, if the training is done in a real-world simulation the instructor will be hundreds of feet from the technician. Further the instructor will typically have several technicians each working on their own device. If one of the technicians triggers their device the instructor will only know it has occurred if the technician notices the signal and reports it to the instructor. A technician that is struggling to successfully complete a training course may have an incentive to not report their failed attempt to disarm the device.
What is needed, therefore, is a signal device for explosive disposal training which does not allow the technician receiving the training to cheat by resetting it. Second, the signal device should provide a signal to a remotely located instructor when triggered. Further, the signal should allow the instructor to monitor more than one student.


A light detector provides wavelength tracking, monitoring or similar function by forming a diffraction grating in a light waveguide. Diffracted light from the waveguide is received by a light detecting device having multiple detecting portions. Changes in the emission angle of the diffracted light caused by the wavelength or other fluctuation of the incident light are detected. The detected information can be used for wavelength tracking by injecting current into or applying a voltage to the waveguide to regulate the Bragg wavelength of the light waveguide, for monitoring and/or controlling the oscillation wavelength of a semiconductor laser or for other purposes.

1. Field of the Invention
This invention relates to light detecting apparatus to be used in optical communication and so forth. The light detecting apparatus detects or monitors wavelength fluctuations of a received light and the detected information is used for a wavelength tracking in a filtering or demultiplexing portion of the apparatus, or to control an oscillation wavelength and/or output power of a laser device coupled to the light detecting apparatus. The light detecting apparatus may preferably be used in a transmitter or receiver end office of an optical communication network or system.
2. Related Background Art
Conventionally, a wavelength band width per one signal wavelength is set considerably wide, such as 20 nm, in a wavelength division multiplexing communication system in which a plurality of signal wavelengths are distributed over a band arround 0.8 .mu.m, is consideration of the performance of a filter disposed at the side of a signal receiver. Therefore, even if the wavelength of a received light fluctuates to some extent in such wavelength band, a signal can be received well at the receiver side and there is no obstacle to the wavelength division multiplexing communication. As a result, a wavelength tracking operation is not needed for each signal wavelength at the receiver side.
In such a prior art example, however, it is difficult to increase the multiplexing degree or multiplicity of signal wavelengths since the band width per one signal wavelength is set wide, and hence the advantage of wavelength division multiplexing communication is not sufficiently utilized although the wavelength tracking operation is dispensable.

Light detecting apparatus having a diffraction grating


A semiconductor memory device includes: a memory cell region constructed of blocks and a memory cell region constructed of blocks. The blocks and the blocks are continuously disposed. A block decoder outputs block select signals to the respective blocks. As a result, power consumption of the semiconductor memory device is reduced.

1. Field of the Invention
The present invention relates to a semiconductor memory device capable of reducing power consumption or to a semiconductor memory device capable of performing a high speed burn-in test.
2. Description of the Background Art
In a prior art DRAM (Dynamic Random Access Memory), a shared sense amplifier configuration is adopted in which sense amplifiers are each shared by adjacent memory cell arrays on both sides thereof as shown in FIG. 21. Referring to FIG. 21, a memory cell array MCAL includes: a plurality of memory cells MCL1 and MCL2; a bit line pair BLL and /BLL; and word lines WL0L and WL1L. The memory cells MCL1 and MCL2 are each constructed of an N channel MOS transistor 151 and a capacitor 152. The source terminal of the N channel MOS transistor 151 is connected to the bit line BLL or /BLL, the gate terminal thereof is connected to the word line WL0L or WL1L and the drain terminal is connected to one electrode of the capacitor 152. The capacitor 152 is provided between the N channel MOS transistor 151 and a terminal 153 and the other electrode (a cell plate electrode) of the capacitor 152 is connected to the terminal 153. A cell plate voltage Vcp of about half a power source voltage Vcc is supplied to the terminal 153.
When a high boosted voltage Vpp higher than the power source voltage Vcc is supplied, the word line WL0L or WL1L is activated to turn on the N channel MOS transistor 151. By doing so, one electrode of the capacitor 152 is connected to the bit line BLL or /BLL, and an electric charge is supplied to the one electrode of the capacitor 152 from the bit line BLL or /BLL to perform data write, or alternatively an electric charge flows out from the one electrode of the electrode to the bit line BLL or /BLL to perform data read. Hence, the N channel MOS transistor 151 is an access transistor for access to the capacitor 152 in performing data write or data read.
A bit line equalize circuit 160L is constructed of N channel MOS transistors 161 to 163. The N channel MOS transistors 161 and 162 are connected in series between the bit line BLL and /BLL, the N channel MOS transistor 163 is connected between the bit lines BLL and /BLL. The N channel MOS transistors 161 to 163 receive a bit line equalize signal BLEQL at each of the gate terminals thereof. When the bit line equalize signal BLEQL is activated, the N channel MOS transistors 161 to 163 are turned on and an intermediate voltage VH supplied to a node 164 between the N channel MOS transistors 161 and 162 is supplied to the bit lines BLL and /BLL to equalize the bit line pair BLL and /BLL to a prescribed voltage. In this case, the N channel MOS transistor 163 exerts a function to equalize a potential on the bit line BLL and a potential on the bit line /BLL.
N channel MOS transistors 190L and 191L are both connected between the bit line equalize circuit 160L and a sense amplifier 170 in series with the respective bit lines BLL and /BLL. The N channel MOS transistors 190L and 191L are turned on/off by a bit line select signal BLIL to connect the bit line equalize circuit 160L and the sense amplifier 170 together.
The sense amplifier 170 is constructed of P channel MOS transistors 171 to 173; and N channel MOS transistors 174 to 176. The P channel MOS transistors 172 and 173 are connected in series between the bit lines BLL and /BLL and the N channel MOS transistors 174 and 175 are also connected in series therebetween. The P channel MOS transistor 171 is connected between a power source node 177 and a node 179A and receives a sense amplifier activating signal SEP at its gate. The N channel MOS transistor 176 is connected between a node 179B and a ground node 178 and receives a sense amplifier activating signal SEN. The sense amplifier 170 differentially amplifies a potential difference between the bit lines BLL and /BLL.
An IO gate circuit 180 is constructed of N channel MOS transistors 181 and 182. The N channel MOS transistor 181 connects the bit line BLL and an input/output line IO together and the N channel MOS transistor 182 connects the bit line /BLL and an input/output line /IO together. The N channel MOS transistors 181 and 182 are turned on/off by a column select signal SCL supplied from a terminal 183.
N channel MOS transistors 190R and 191R are both connected between the bit line equalize circuit 160R and the sense amplifier 170 in series with the respective bit lines BLL and /BLL. N channel MOS transistors 190R and 191R are turned on/off by a bit line select signal BLIR to connect the bit line equalize circuit 160R and the sense amplifier 170 together.
The bit line equalize circuit 160R has the same configuration as does the bit line equalize circuit 160L and is activated/deactivated by a bit line equalize signal BLEQR.
A memory cell array MCAR includes memory cells MCR1 and MCR2, a bit line pair BLR and /BLR and word lines WLOR and WL1R. Memory cells MCR1 and MCR2 have the same configuration as do the memory cell MCL1 and MCL2.
In the configuration shown in FIG. 21, when data is inputted/outputted to/from the memory cells MCL1 and MCL2 of the memory cell array MCAL, the N channel MOS transistors 190R and 191R are turned off by the bit line select signal BLIR while the N channel MOS transistors 190L and 191L are turned on by the bit line select signal BLIL. Then, the N channel MOS transistors 181 and 182 are turned on by the activated column select signal SCL and the bit lines BLL and /BLL are connected to the respective input/output lines IO and /IO by the IO gate circuit 180. Further, the power source voltage and the ground voltage are supplied by the respective sense amplifier activating signals SEP and SEN to activate the sense amplifier 170. In a standby state, the bit line equalize signal BLEQL is activated and the bit line pair BLL and /BLL are equalized to a precharge voltage. Thereafter, when a memory cycle gets started, the bit line equalize signal BLEQL is deactivated. Subsequent to the deactivation, the word lines WL0L and WL1L are activated to input/output data to/from the memory cells MCL1 and MCL2. When data input/output finishes, the bit line equalize signal BLEQL is activated to equalize the bit line pair BLL and /BLL to the precharge potential.
Then, when data is inputted/outputted to/from the memory cells MCR1 and MCR2 of the memory cell array MCAR, the N channel MOS transistors 190L and 191L are turned off by the bit line select signal BLIL, while the N channel MOS transistors 190R and 191R are turned on by the bit line select signal BLIR. The N channel MOS transistors 181 and 182 are turned on by an activated column select signal SCL and the bit lines BLR and /BLR are connected to the respective input/output lines IO and /IO by the IO gate circuit 180. Further, the power source voltage and the ground voltage are supplied by the respective sense amplifier activating signals SEP and SEN to activate the sense amplifier 170. In the standby state, the bit line equalize signal BLEQR is activated to equalize the bit line pair BLR and /BLR to the precharge voltage. Thereafter, when a memory cycle gets started, the bit line equalize signal BLEQR is deactivated. Subsequent to this deactivation, the word lines WLOR and WL1R are activated to input/output data to/from the memory cells MCR1 and MCR2. When data input/output finishes, the bit line equalize signal BLEQR is activated to equalize the bit line pair BLR and /BLR to the precharge potential.
In such a way, in the configuration using shared sense amplifiers, data is alternately inputted/outputted to/from memory cell arrays on both sides of the sense amplifier.
In a highly integrated semiconductor memory device, a chip with a plurality of memory cells arranged in the form of a matrix thereon, all of which cells are in a normal state, is difficult to be fabricated; therefore, spare memory cells substituted for a defective memory cell are provided and when a defective cell is specified by an address, a spare memory cell is activated instead of the defective memory cell such that a perfect operation is realized. That is, a configuration is adopted in which an address of a defective memory cell is programmed in a chip in advance, an inputted address is compared with the programmed address and if coincidence arises, then a spared memory cell is activated.
Therefore, a prior art DRAM in which spare memory cells are arranged on a chip thereof has had a configuration shown in FIG. 22. That is, a memory cell array is constructed of a plurality of blocks BLK0 to BLK15 and shared sense amplifiers 170 are each inserted between adjacent blocks. Each of the plurality of blocks BLK0 to BLK15 includes: spare rows activated/deactivated by a spare row decoder 192; and regular rows activated/deactivated by a regular row decoder 193. When a defective memory cell is included in memory cells connected to a regular row, a memory cell in a spare row is activated instead of the defective row by the spare row decoder 192. In the configuration shown in FIG. 22, however, since the plurality of blocks BLK0 to BLK15 each have spare rows and regular rows, the number of spare rows increases on the chip as a whole, thereby having led to a problem of being unsuitable for high integration.
Therefore, a semiconductor memory device of a configuration as shown in FIG. 23 is disclosed in Japanese Patent Laying-Open No. 2000-67595. That is, referring to FIG. 23, of the plurality of blocks BLK0 to BLK15, the blocks BLK0 and BLK15 each include: spare rows activated/deactivated by a spare decoder 194; and regular rows activated/deactivated by a regular row decoder 195, while the blocks BLK1 to BLK14 each include only regular rows activated/deactivated by the regular row decoder 195. With such a configuration adopted, the spare rows can be concentrated in the two blocks BLK0 and BLK15, thereby enabling the number of spare rows to decreases on a chip as a whole. When each of the plurality of blocks BLK0 to BLK15 is accessed, the plurality of blocks BLK0 to BLK15 are divided into two groups and access is performed to each of the two groups. That is, as shown in FIG. 24, the two groups are formed by division as a group Gr1 including the blocks BLK0, BLK2, BLK4, BLK6, BLK8, BLK10, BLK12 and BLK14 and a group Gr2 including BLK1, BLK3, BLK5, BLK7, BLK9, BLK11, BLK13 and BLK15. Further, spare memory cells substituted for a memory cell included in the group Gr1 are disposed in the block BLK0 and spare memory cells substituted for a memory cell included in the group Gr2 are disposed in the block BLK15. When a memory cell included in the group Gr1 is defective, a spare row 230 of the block BLK0 is activated, while when a memory cell included in the group Gr2 is defective, a spare row 231 of the block BLK15 is activated.
When a defective memory cell exists in the block BLK14 included in the group Gr1 and the defective memory cell is specified by an address, however, redundancy judgment is performed on whether or not the defective memory cell is a memory cell that can be replaced with a spare memory cell included in the block BLK0. In the two blocks BLK0 and BLK14, the bit line select signal BLI is activated to connect the bit line pair and the sense amplifier together and the bit line equalize signal BLEQ is activated to equalize the bit line pair to the precharge voltage till the redundancy judgment finishes. Thereafter, the bit line select signal BLI and the bit line equalize signal BLEQ are deactivated to make preparation for activation of a word line.
When a memory cell in the block BLK0 is used instead of a memory cell in the block BLK14 as a result of redundancy judgment, it is required that the bit line select signal BLI and the bit line equalize signal BLEQ are again activated in the block BLK14. Since the blocks BLK0 and BLK14 are spaced apart from each other, a signal for deactivating the block BLK14 is delayed due to propagation delay. As a result, a time period is extended in which the bit line select signal BLI and the bit line equalize signal BLEQ are inactive; therefore, a problem has arisen since a discharge amount for deactivating the bit line select signal BLI and the bit line equalize signal BLEQ increases as shown in FIG. 25. Particularly, since the bit line select signal BLI is driven by an internal high voltage generated by a built-in pump circuit on a chip, increase in power consumption caused by increase in discharge amount is a conspicuous problem. In company with this, a necessity arises for the pump circuit of a larger capacity, having led to a problem of a larger chip area.
On the other hand, as shown in FIG. 26A, a prior art semiconductor memory device 300 includes a memory cell array divided into 4 groups Gr0 to Gr3. The groups Gr0 to Gr3 each include spare rows 301 and regular rows 302. Column redundancy judgment on a memory cell included in the groups Gr0 and Gr1 is performed by one comparison circuit and column redundancy judgment on a memory cell included in the groups Gr2 and Gr3 is performed by another comparison circuit. In order to perform a burn-in test in which a high voltage is applied at a high temperature of the order of 120xc2x0 C. in the semiconductor memory device 300, the groups Gr0 and Gr2 are simultaneously activated and the groups Gr1 and Gr3 are simultaneously activated. Therefore, a column address for specifying a column 303 is inputted and comparison can be made of the column address with a column address programmed in a redundancy circuit.
The semiconductor memory device 300, however, includes spare rows 301 in each of the groups Gr0 to Gr3; therefore, a substitution capability to substitute a spare memory cell for a defective memory cell is low in the groups Gr0 to Gr3. Hence, a semiconductor memory device 400 as shown in FIG. 26B has been proposed. The semiconductor memory device 400 includes a memory cell divided into two groups Gr0 and Gr1. Each of the groups Gr0 and Gr1 includes spare rows 401 and regular rows 402. Furthermore, column redundancy judgment on memory cells included in the groups Gr0 and Gr1 is performed by one comparison circuit. With such a configuration, the groups Gr0 and Gr1 are simultaneously activated in a burn-in test; therefore, when a column address specifying a column 403 is inputted, the column address inputted cannot be compared with a column address programmed in a redundancy circuit. That is, since the inputted column address is in common with the groups Gr0 and Gr1, no judgment can be made on whether a column address of the group Gr0 or the group Gr1 coincides with a programmed column even if the inputted column address coincides with the programmed column address. As a result, a problem has arisen since no burn-in test can be performed on a semiconductor memory device having an increased substitution capability.
It is accordingly an object of the present invention to provide a semiconductor memory device with low power consumption.
It is another object of the present invention to provide a semiconductor memory device capable of simultaneously activating a plurality of groups to perform a burn-in test.
A semiconductor memory device according to the present invention is a semiconductor memory device having a plurality of regions and each of the plurality of regions includes: a plurality of memory cell regions each including a first block including substitution rows on which first memory cells are arranged in a row direction and regular rows on which second memory cells are arranged in a row direction, and a plurality of second blocks each including regular rows without any substitution row; a plurality of redundancy circuits provided correspondingly to the respective plurality of memory cell regions and each comparing a row address of a defective memory cell with an inputted row address to output a substitution row select signal indicating the presence or absence of selection of a substitution row on the basis of a result of the comparison; a block decoder receiving the substitution row select signal to generate a block select signal for selectively activating/deactivating a first block and a plurality of second blocks included in a memory cell region corresponding to a redundancy circuit outputting the substitution row select signal received on the basis of the substitution row select signal and output the block select signal that the block decoder has generated to the first block and the plurality of second block included in the corresponding memory cell region; and a plurality of bit line equalize circuits provided correspondingly to respective plural first and second blocks included in the plurality of memory cell regions and each generating a bit line equalize signal equalizing a bit line pair included in first and second blocks, wherein the first memory cells each are a memory cell substituted for a defective memory cell among a plurality of second memory cells included in the first block and the plurality of second blocks, a plurality of second blocks in one of a plurality of memory cell regions are continuously disposed, and each of the plurality of bit line equalize circuits activates a bit line equalize signal in response to deactivation of a block select signal.
A semiconductor memory device according to the present invention includes a plurality of regions. Each of the plurality of regions includes: a plurality of memory cell regions; a plurality of redundancy circuits; a block decoder; and a plurality of a bit line equalize circuits. The plurality of memory cell regions each includes a first block and a plurality of second blocks. The plurality of second blocks are continuously disposed. The block decoder outputs a block signal for selecting a plurality of blocks to the first block and the plurality of second block included in each of a plurality of memory cell regions. Each of a plurality of bit line equalize circuits activates a bit line equalize signal in response to deactivation of the block select signal. Thereby, a plurality of second blocks receive a block select signal with reduced propagation delay. Therefore, according to the present invention, a timing of activation of an inactive bit line equalize signal can be almost the same for each of a plurality of second blocks. As a result, a discharge amount when a bit line equalize signal is deactivated is reduced, thereby enabling realization of a semiconductor memory device with low power consumption.
It is preferable that each of the plurality of memory cell regions further includes: a third block disposed between the first block and the plurality of second blocks; a plurality of sense amplifiers each selectively amplifying read data from two adjacent blocks, wherein the third block is a first or second block constituting another memory cell region.
A first block and a second block including substitution rows are simultaneously activated in one memory cell region. Therefore, according to the present invention, first and second blocks are kept active till a comparison period between a row address of a defective memory cell and an inputted row address ends and after the comparison period ends, one of the two blocks that have been activated continues to be active, thereby enabling high speed operation of a semiconductor memory device to be realized.
It is preferable that each of the plurality of redundancy circuits of the semiconductor memory device further generates a substitution row activating signal for activating/deactivating a substitution row on the basis of a result of the comparison and each of the plurality of regions further includes: a plurality of substitution row decoders provided correspondingly to the respective plurality of memory cell regions and each activating/deactivating a substitution row in response to a substitution row activating signal.
A substitution row decoder performs activation of a substitution row in response to a substitution row activating signal from a redundancy circuit. Therefore, according to the present invention, a block including substitution rows can be activated at almost the same timing that a block including no substitution row can be activated according to a block select signal with reduced propagation delay and a substitution row included in the block can also be activated.
It is preferable that a block decoder outputs a first block select signal activating a first block and a second block select signal activating one of a plurality of second blocks to each of a plurality of memory cell regions till a comparison period ends in which a row address of a defective memory cell and an inputted row address are compared with each other and after the comparison period ends, outputs a third block select signal for activating one of a first block and a plurality of second blocks to each of a plurality of memory cell regions in response to a substitution row select signal.
During a period when it is judged whether or not a memory cell specified by an inputted address is a defective memory cell, a block including the memory cell specified by an inputted address and a block including a spare memory cell substituted for the memory cell specified by an inputted address if the memory cell specified by an inputted address is a defective memory cell are simultaneously activated, and after the judgment period finishes the block including the memory cell specified by an inputted address or the block including the spare memory cell continues to be kept active. Therefore, according to the present invention, a high speed semiconductor memory device can be realized.
It is preferable that the semiconductor memory device further includes: a control circuit generating an equalize control signal for controlling equalization of a bit line pair, wherein in refresh operations of a first and second memory cells, the control circuit generates an equalize control signal for deactivating a bit line equalize signal after a comparison operation performed by a redundancy circuit ends and each of a plurality of bit line equalize circuits activates/deactivates a bit line equalize signal in response to the equalize control signal.
In the semiconductor memory device, in a refresh operation of memory cells, all the blocks included in all of a plurality of memory cell regions are deactivated till a comparison period in which a row address of a defective memory cell is compared with an inputted row address ends, and after the comparison period ends, one block is activated and data is inputted/outputted to/from memory cells. Therefore, according to the present invention, power consumption is suppressed in the comparison period, and thereby a semiconductor memory device with low power consumption can be realized.
It is preferable that the control circuit of the semiconductor memory device further generates a word line control signal for activating a word line included in first and second blocks after deactivating a bit line equalize signal.
In a refresh period of memory cells, a word line included in an activated block is activated according to a row address after a comparison operation in a redundancy circuit ends. Hence, according to the present invention, power consumption of a semiconductor memory device can be surely suppressed in a refresh period of memory cells.
It is preferable that in a refresh operation of memory cells, the control circuit continues to generate an equalize control signal at a first logical level for an entire period of a comparison operation and generates an equalize control signal at a second logical level after the comparison operation ends; and each of a plurality of bit line equalize circuits generates a bit line equalize signal at the second logical level in response to the first logical level of the equalize control signal till the comparison operation ends, while generating a bit line equalize signal at the second logical level or at the first logical level in response to the second logical level of the equalize control signal and the first or second logical level of a block select signal after the comparison period ends.
The control circuit controls such that the circuit keeps blocks inactive till the comparison operation ends by switching logical levels of an equalize control signal while activating a selected block after the comparison operation ends. Hence, according to the present invention, a control circuit controlling so as to suppress power consumption in a refresh operation can be constituted of a logic circuit.
A semiconductor memory device according to the present invention is a semiconductor memory device including a plurality of regions and each of the plurality of regions includes: a plurality of memory cell regions each including a first block including substitution rows on which first memory cells are arranged in a row direction and regular rows on which second memory cells are arranged in the row direction, and a plurality of second blocks each including regular rows without any substitution row; a plurality of row redundancy circuits provided correspondingly to the respective plurality of memory cell regions and each comparing a row address of a defective memory cell with an inputted row address to output a substitution row activating signal activating/deactivating a substitution row and a substitution row select signal indicating the presence or absence of selection of a substitution row on the basis of a result of the comparison; a block decoder receiving the substitution row select signal to generate a block select signal from the substitution row select signal for selectively activating/deactivating a first block and a plurality of second blocks included in a memory cell region corresponding to a redundancy circuit outputting the substitution row select signal received and output the block select signal to a first block and a plurality of second block included in the corresponding memory cell region; a plurality of substitution row decoders provided correspondingly to a plurality of first blocks included in a plurality of memory cell regions to each activate/deactivate a substitution row on the basis of a block select signal and a substitution row activating signal; a plurality of row decoder provided correspondingly to a plurality of second blocks included in a plurality of memory cell regions to each activate/deactivate a regular row on the basis of a block select signal and a row address signal; a column redundancy circuit comparing a column address of a defective memory cell with an inputted column address to generate a substitution column activating signal for activating/deactivating a substitution column to which a memory cell substituted for the defective memory cell is connected on the basis of a result of the comparison; a substitution column decoder activating/deactivating a substitution column on the basis of the substitution column activating signal; and a column decoder activating/deactivating a regular column on the basis of a column address, wherein the first memory cells each are a memory cell substituted for a defective memory cell among a plurality of second memory cells included in a first block and a plurality of second blocks, the column redundancy circuit includes: a storage circuit storing a column address of a defective memory cell included in a first block and a plurality of second blocks in each of a plurality of memory cell regions and selectively outputting a stored column address according to a region address specifying one of the plurality of memory cell regions; and a comparison circuit comparing a column address outputted from the storage circuit with an inputted column address to output a substitution column activating signal; in a period of a burn-in test, the block decoder receives a degenerated region address to output a block select signal for simultaneously activating a plurality of blocks specified by the same block address included in a plurality of memory cell regions; and the storage circuit selectively outputs a column address stored therein corresponding to a memory cell region specified by a region address.
In a semiconductor memory device according to the present invention, in a period of a burn-in test, word lines of the same address included in a plurality of memory cell regions are simultaneously activated while bit lines included in each of the plurality of memory cell regions are activated independently of the others. Therefore, according to the present invention, a burn-in test can be performed simultaneously over a plurality of memory cell regions. As a result, the burn-in test can be performed in a short time.
It is preferable that the storage circuit of the redundancy circuit further outputs a correspondence signal showing whether or not an outputted column address is a column address corresponding to a memory cell region specified by a region address and the comparison circuit thereof outputs a substitution column activating signal when receiving a correspondence signal showing that a column address outputted from the storage circuit is a column address corresponding to a memory cell region specified by a region address.
When an inputted column address coincides with a column address of a defective memory cell and a correspondence signal showing the column address of a defective memory cell is effective is inputted, the comparison circuit outputs a substitution column activating signal. Therefore, according to the present invention, it is prevented that a spare memory cell is activated instead of a normal memory cell.
It is preferable that the semiconductor memory device further includes: a row address buffer latching an address signal to output a row address of n (n is a natural number) bits; and a degeneration circuit outputting a degenerated signal of k bits (k is a natural number satisfying 1xe2x89xa6k less than n) by degenerating a row address of k bits included in the row address of n bits, wherein the block decoder receives the degenerated signal and a block address of m (m is a natural number satisfying 1xe2x89xa6m less than nxe2x88x92k) bits, a row decoder receives a row address of nxe2x88x92kxe2x88x92m bits from a row address buffer and the storage circuit receives a row address of k bits from the row address buffer.
In a period of a burn-in test, the block decoder receives a degenerated row address of k bits and a non-degenerated row address of m bits to simultaneously activate a plurality of blocks specified by the row address of m bits included in a plurality of memory cell regions and a row decoder activates a word line included in a block activated by the non-degenerated nxe2x88x92mxe2x88x92k bits. Therefore, by degenerating k bits of a row address of n bits, a plurality of blocks of the same address included in a plurality of memory cell regions can be simultaneously activated.
It is preferable that the comparison circuit outputs a deactivated substitution column activating signal when receiving an activated first test mode signal and further outputs a substitution column activating signal activating a substitution column specified by a column address of the substitution column when receiving an activated second test mode signal.
In a burn-in test, the first test mode signal is activated to perform a test on a memory cell connected to a regular column and thereafter, the second test mode signal is activated to perform a test on a memory cell connected to a substitution column. Therefore, according to the present invention, all the memory cells can be tested in a burn-in test.
It is preferable that the comparison circuit includes: a coincidence detecting circuit detecting whether or not a column address outputted from a storage circuit coincides with an inputted column address to output a coincidence/non-coincidence signal on the basis of a result of the detection; a first test mode circuit outputting a deactivating signal for deactivating a substitution column activating signal when receiving a activated first test mode, and outputting a coincidence/non-coincidence signal from said coincidence detecting circuit when receiving a deactivated first test mode; and a second test mode circuit outputting an activated substitution column activating signal on the basis of a column address when receiving an activated second test mode signal, and outputting a substitution column activating signal on the basis of a deactivating signal from the first test mode circuit or a coincidence/non-coincidence signal when receiving a deactivated second test mode signal.
A substitution column activating signal is activated/deactivated according to a coincidence/non-coincidence signal when deactivated first and second test mode signals are inputted. The substitution column activating signal is deactivated when activated first test mode signal and a deactivated second test mode signal are inputted. A substitution column is activated according to an inputted column address when activated first and second test mode signals are inputted. Therefore, according to the present invention, various kinds of tests can also be performed using two test mode signals.
It is preferable that the coincidence detecting circuit is constituted of a first operational circuit performing an exclusive OR operation on a column address outputted from a storage circuit and an inputted column address, the first test mode circuit is constituted of a second operational circuit performing an AND operation on an output signal from the first operational circuit and an inverted signal of a first test mode, and the second test mode circuit is constituted of a third operational circuit performing an AND operation on a column address and a second test mode signal and a fourth operational circuit performing an OR operation on an output signal from the second operational circuit and an output signal from the third operational circuit. Therefore, according to the present invention, various kinds of test modes can be realized by the logic circuits.
It is preferable that a column redundancy circuit is constituted of a plurality of redundancy circuits provided correspondingly to respective plurality of substitution columns and a prescribed number of redundancy circuit among the plurality of redundancy circuits each include a storage circuit in which a column address of a defective memory cell is at least electrically written to store the written column address therein.
A column address of a defective memory cell is electrically written in some redundancy circuits among the plurality of redundancy circuits. Therefore, according to the present invention, a column address of a defective memory cell can be written even when the defective memory cell is detected in a test after a semiconductor memory device is packaged. As a result, a fraction defective can be reduced.
It is preferable that each of the plurality of row redundancy circuits include a plurality of redundancy circuits provided correspondingly to a plurality of substitution rows and each of a prescribed number of redundancy circuits among the plurality of redundancy circuits includes a storage circuit in which a row address of a defective memory cell is at least electrically written to store the written row address therein.
A row address of a defective memory cell is electrically written in some redundancy circuits among the plurality of redundancy circuits. Therefore, according to the present invention, a defective memory cell can be functionally saved even when the defective memory cell is detected in a test after a semiconductor memory device is packaged. As a result, a fraction defective can be reduced.
It is preferable that a storage circuit includes: a first fuse circuit constituted of a first fuse to be blown by supplying a current; and a second fuse circuit constituted of a second fuse blown by irradiation with laser light, wherein a column address is written in the first fuse circuit by blowing the first fuse and the second fuse becomes conductive in the second fuse circuit to output the same logical signal as that of a column address outputted from the first fuse circuit.
By supplying a current in the first fuse circuit, the fuse is blown to write a column address of a defective memory cell. Therefore, according to the present invention, a column address of a defective memory cell can be easily written by supplying a current.
It is preferable that a first fuse is constructed of a first conductor which is blown and a second conductor disposed so as to sandwich the first conductor at least vertically or horizontally.
When a current flows through the first and second conductors, a temperature of the first conductor rises higher than that of the second conductor. Therefore, according to the present invention, the first conductor can be easily blown even with a small current.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

Semiconductor memory device with low power consumption


A process for enhancing the. (a) normal healing processes involving a live mammalian body of PA1 (b) for enhancing the biocompatibility and adhesion of bone and/or prosthetic device involved in a non-dental surgical or nonsurgical repair procedure, to ossified and non-ossified tissue components with which they are in contact, where there is an injury to either soft or hard tissue or a non-biocompatible prosthesis is placed in the body, that involves placing at the injury or on the prosthesis. (i) injured non-dental-related soft tissue, and PA2 (ii) non-dental-related osseous material, and PA2 a) a primary coating that is a tenaciously-bonded hydrophilic water insoluble crosslinked resin coating, PA2 b) that optionally contains a measurable amount of a water/fluid leachable fluoride capable of (a) being leached from the coating in a metered amount, and (b) transporting a small amount of leached fluoride from the coating into the afflicted area ("the primary coating with fluoride").

Dentistry is the science concerned with the diagnosis, prevention, and treatment of diseases of the teeth, gums, and related structures of the mouth and includes the repair or replacement of defective teeth. Dental (i.e., relating to, or for the teeth) treatments involve those compositions, articles and processes encompassed within the field of dentistry. The terms "non-dental applications and treatments" and "non-dental-related", as used herein and in the claims hereof, address activities exclusive of activities that are part of the field of dentistry.
Geristore.TM. and Tenure.TM., sold by Den-Mat Corporation, Santa Maria, Calif., are promoted for certain uses in dentistry. U.S. Pat. Nos. 4,738,722, 5,334,625 and 5,151,453, incorporated herein by reference, describe Geristore.TM.. Geristore.TM. is a small particle composite that contains fluoride, is radiopaque and hydrophilic. It has low-cure shrinkage, low coefficient of thermal expansion and high strength. It aggressively bonds by chemical coupling to dentin, enamel, composites used in dentistry, porcelain and metal, such as stainless steel. It is a paste/paste formulation that is easy to mix. It is capable of rapid cure by exposure to room temperature and for more rapid cure, by exposure to light. In addition, though it contains a fluoride, which could be toxic when ingested in large dosages, it is biocompatible and safe to use within a human or other animal when applied topically.
Tenure.TM. is a solvent based crosslinkable acrylic resin, provided as a solution/solution formulation. Its composition is described in U.S. Pat. No. 4,964,911, patented Oct. 27, 1990, and more effectively disclosed in allowed copending application Ser. No. 965,102, filed Oct. 22, 1992, to issue as U.S. Pat. Re 34,937, the disclosure of which is incorporated by reference. It is not an ionomer and does not release fluoride ion. It is less hydrophilic than Geristore.TM.. It too is a crosslinkable resin. It contains a volatile solvent (typically acetone), which readily evaporates. After evaporation, a film of the resin rapidly cures in situ. Tenure.TM. bonds by chemical coupling to dentin, enamel, porcelain, metal and the composites typically used in dentistry. It has been recommended for use with Geristore.TM. in chemically bonding Geristore.TM. to dentin or enamel.
Galan, Journal Of Esthetic Dentistrv, Vol. 3, No. 6, (Nov./Dec. 1991), describes the general use of Geristore.TM. in the restoration of teeth and lesions both supra and subgingivally located.
M. Dragoo (unpublished) has used Geristore.TM. in subgingival restorations of teeth to treat subgingival root resorption, split roots, endo perforation, tooth fracture, external root resorption and root coverage over previously restored and/or eroded root surfaces. He found the Geristore.TM. aided in rebuilding biologic width, resulting in new tissue attachment, and minimized plaque induced gingivitis.
There is much art on the use of hydroxyethylmethacrylate ("HEMA") to make hygroscopic polymers such as a homopolymer of HEMA ("PHEMA"). Such HEMA based polymers typically form water swellable hydrogels. HEMA contains the sym. (or 1,2-) ethylene bis-methacrylate (ethylene glycol dimethacrylate) as a byproduct. This byproduct crosslinks the HEMA based polymers to allow formation of useful hydrogels. One such hydrogel form is used to make soft contact lens by cast molding HEMA containing small amounts of ethylene bis-methacrylate. One advantage of PHEMA based systems that allows use in physiological applications is the biocompatibility of the polymer. However, their use as described in the patent literature has been limited merely to transporting drugs and other materials to a bodily function based on their absorptive qualities or as an inert interface about a device to render that device biocompatible. See for example, U.S. Pat. No. 3,566,874, which describes the encapsulation of a catheter with a casting syrup of HEMA. The hydrogel form of the polymer of HEMA ("PHEMA") is renowned for its capacity to absorb moisture to generate a swollen film. Some patents describe PHEMA products into which other ingredients have been absorbed. In this respect, the PHEMA product, as such, is merely a reservoir for that ingredient. U.S. Pat. No. 3,566,874 describes the inclusion in a HEMA casting syrup of a germicide or an antibiotic. U.S. Pat. No. 4,303,066, makes a burn dressing by dispensing separate phases of a PHEMA and a high boiling liquid on a burn to serve as a dressing. As a consequence, the absorptive characteristic of PHEMA is being used only for the high boiling liquid which is provided supposedly for heat transfer purposes. U.S. Pat. No. 3,674,901 describes the coating of a HEMA based solvent solution to coat surgical suture threads. The patent includes antibiotics, antiseptics or bactericides absorbed into the cured resin. In this case, however, the resin is foamed first before the adsorption takes place. In U.S. Pat. No. 3,849,185, a HEMA coumarone-indene type resin casting material is mixed with materials such as heparin and used as a coating material. On the other hand, U.S. Pat. No. 3,868,447 describes a highly filled solvent-based HEMA paste to which biologically active ingredients can be added. The paste has been described for use in dental applications, such as a cover for dental fillings, or as a carrier for Novocain.TM. in dental surgery.
Though HEMA and PHEMA contain hydroxyl groups and hydroxyl groups are thought to aid in adhesion, the adhesion of such groups to a physiologically active surface is materially and adversely affected by the presence of water at the surface. Consequently, bonding of HEMA to a physiologically involved surface which contains moisture at its surface requires some ingredient in the resin that aids in bonding to such a surface.


A method and apparatus for an improved luer fitting connector, in one embodiment, has a luer fitting connector including a male or female luer fitting member and a locking member. The locking member may have at least one of a skeletal handle, a finlike handle, a cavity grip, and an undulating grip. The luer fitting connector also may include a male or female luer fitting member having a conical restraining surface and a locking member having a plateau shaped protrusion. A method of assembly of luer fitting connector members may include providing a male or female luer fitting member having a conical restraining surface and providing a locking member having a plateau shaped protrusion. The method also may include mounting the locking member upon the male or female luer fitting member from the rear.

Luer fitting or luer lock connections are utilized in fluid flow conduits having medical or surgical applications. Typically, a male member has a slightly tapered body and is connected in fluid communication with a female member, which has a similarly tapered bore for receiving the male member. A coupling device or locking member commonly has an internally threaded collar. The locking member may further be mounted upon the body of the male member.
One purpose of the locking member is to prevent fluid leakage between the male and female members. Another purpose of the locking member is to maintain the connection between the male and female members.
However, luer fitting connectors are conventionally very small in size. Hence, with conventional designs, it can be difficult for an operator to maintain manual control of the luer fitting connector assembly, as well as rotate the locking member about the male and female members by hand.
Additionally, conventional luer fitting connector assemblies are often assembled by mounting the locking member onto the male member from the rear. The male member may have a restraining mechanism for restricting the longitudinal movement of the locking member after it is mounted upon the male member. In some conventional designs, the locking member has a plateau shaped protrusion for engagement with the restraining mechanism. In such assemblies, the locking member may be mounted upon the male member by forcing the plateau shaped protrusion over the restraining mechanism.
However, the male member exerts compression forces on the locking member as the plateau shaped protrusion is slid over the restraining mechanism from the rear. The compression forces applied tend to shorten the radial height of the plateau shaped protrusion. Yet, the plateau shaped protrusion must have enough elasticity to sufficiently limit the permanent plastic deformation, if any, that it experiences as a result of the applied compression forces such that the locking member cannot subsequently inadvertently "jump" back over the restraining mechanism. Thus, conventional designs disclose plateau shaped protrusions that experience compression forces that may lead to plastic deformation and the inadvertent separation of the locking and male luer fitting members after the locking member and the male luer fitting member are coupled together.
The present invention alleviates one or more of the shortcomings described above.

Method and apparatus for an improved luer fitting connection


A carton has a removeable dispenser that forms a dispenser opening that allows articles to be removed from the carton. The dispenser also has access flaps that create access openings that provide access to articles in the carton.

Enclosed cartons with dispensing features have been used in the past. Many of these cartons include a dispenser defined by tear lines. The dispenser is removable from the carton to create an opening through which articles can be removed from the carton. In many instances, after the user engages and opens the dispenser, some of the articles, especially those disposed in a lower column or layer, are positioned substantially, or entirely, below the edge of the dispenser opening. In order to dispense the cans or articles that are substantially or entirely disposed below the dispenser opening, a user must insert their finger or other object into the carton in order to remove the can from the carton.

Carton with dispenser having access features


A pipe coupling (11) comprises a tubular casing (12) and a sealing gasket (13), which fit over the ends of the pipes to be coupled. The casing (12) is formed from a strip of rolled steel into a cylindrical shape, with a longitudinal gap (14). The free ends of the strip, which forms the casing, are bent outwardly to form radially projecting flange (15) along opposite edges of the longitudinal gap (14). The outer ends of the flanges (15) are bent back at right angles to form stiffening flanges (16) along the longitudinal outer edges of the flanges (15). A bridging member (18) fits inside the casing so as to span the longitudinal gap. Tensioning screw bolts (25) pass through reinforcing plate's (20) and the flange (15). A hexagonal nut (34) is threaded onto the end of each screw bolt. The nuts fit into the channel but are prevented from turning. The heads (35) of the bolts have a hexagonal recess to take an Allen key so that they can be tightened to clamp the coupling around the pipe ends.

1) Field of the Invention
The present invention relates to pipe couplings for connecting together pipes in a fluid-tight manner.
2) Description of Related Art
In our earlier patent specification GB-A-2249366 we describe a pipe coupling for connecting together the ends of two plain-ended pipes in a fluid-tight manner, comprising a tubular steel casing, a tubular rubber sealing sleeve and tensioning means in the form of screw bolts for tightening the casing around the sealing sleeve. The casing has circumferential flanges projecting inwardly from its axial end. Gripping devices in the form of incomplete frustoconical rings of steel sheet are located within the casing at opposite ends of the casing. The outer edges of the gripping rings engage in the angle between the axial wall of the casing and the flanges. The inner edges of the gripping rings are formed with teeth. When the coupling is placed around the ends of two pipes to be connected and the tensioning bolts are tightened, the casing is tightened around the sealing sleeve and the gripping rings, pressing the sealing sleeve against the outer surfaces of the pipe end to form fluid-tight seals and forcing the teeth on the gripping rings to bite into the surface of the pipes to grip the pipe.
The casing is made from a strip of rolled steel formed into a tubular shape with a longitudinal gap between the free ends of the strip. The free ends of the strip are folded back on themselves and welded to form loops along opposite edges of the longitudinal gap. Pins are inserted into the loops. The tensioning bolts pass through transverse holes in one of the pins and engage in tapped transverse holes in the other of the pins so as to interconnect the two free ends of the casing. Slots are cut in the loops in the region of the transverse holes to provide clearance for the bolts to pass through. When the screw bolts are turned, the transverse pins are drawn towards each other, thus tightening the casing around the pipe ends.
The coupling of GB-A-2249366 has been successful in many fields of applications. It has been found, however, that there can be problems in manufacturing such a pipe coupling for use with pipes of small sizes, say less than 38 mm in diameter. The tensioning arrangement is too bulky for pipe couplings of this size and the coupling is impractical in many small pipe applications on account of the size of the coupling in relation to the space available in the application, the weight of the coupling, and, especially, the cost of the coupling.
There is a need for a coupling having a tensioning arrangement of a size which is reasonable in proportion to the dimensions of the pipe. The design of the coupling should be such that it can be made lighter than the existing coupling and without pins or welded ends which would make the coupling prohibitively expensive to manufacture for most applications. At the same time, the coupling must meet all the performance requirements of resisting internal pressure in the pipeline (typically up to 100 bar), withstanding vibration, withstanding axial loads, and withstanding shock without leaking, as well as being adjustable to accommodate variations in the diameters of the pipes to be joined within manufacturing tolerances. The coupling should not deform under pressure. The coupling should be capable of repeated installation and dismantling without deformation and deterioration in performance.
The specification DE-A-3445807 proposes a coupling using a single screw bolt and nut which pass through and interconnect, flanges on a tubular casing to tighten the casing. When subjected to tightening, and hydrostatic and axial loads of the kind which would be required for the applications contemplated by the present invention, the casing will deform.

Pipe coupling comprising a divided sleeve