A dual channel showerhead comprising a first plurality of channels formed in the back surface of the showerhead and extending from a first end to a second end, a second plurality of channels formed through the thickness of the showerhead and extending from a first end to a second end, a first end plenum in fluid connection with the second plurality of channels at the first end and a second end plenum in fluid connection with the second plurality of channels at the second end. Processing chambers including the dual channel showerhead and a blocker ring separating the edge ring from the pumping ring are also discussed.

Semiconductor device formation is commonly conducted in substrate processing systems or platforms containing multiple chambers, which may also be referred to as cluster tools. In some instances, the purpose of a multi-chamber processing platform or cluster tool is to perform two or more processes on a substrate sequentially in a controlled environment. In other instances, however, a multiple chamber processing platform may only perform a single processing step on substrates. The additional chambers can be employed to maximize the rate at which substrates are processed. In the latter case, the process performed on substrates is typically a batch process, wherein a relatively large number of substrates, e.g. 25 or 50, are processed in a given chamber simultaneously. Batch processing is especially beneficial for processes that are too time-consuming to be performed on individual substrates in an economically viable manner, such as for atomic layer deposition (ALD) processes and some chemical vapor deposition (CVD) processes.
Temporal ALD processes are sensitive to the time taken to replace one precursor with another during the deposition process. Showerhead and process area internal volumes have to be minimized and conductances maximized. Current design approaches to address precursor replacement and purge/vacuum issues in the ALD chamber include cross-flow, coaxial injection/vacuuming and spiral showerhead structures. However, there is an ongoing need in the art for apparatus and methods to further reduce the amount of time between reactive gas exposures due to process chamber purging.

Temporal atomic layer deposition process chamber


An optoelectronic component is disclosed. In an embodiment an optoelectronic component includes a semiconductor chip configured to emit radiation and a conversion element including quantum dots, the conversion element configured to convert a wavelength of the radiation, wherein each quantum dot includes a wavelength-converting core and an inorganic encapsulation, wherein inorganic encapsulations form a matrix material of at least adjacent quantum dots, and wherein the adjacent quantum dots have a distance of at least 10 nm.

Optoelectronic components, such as light-emitting diodes, usually require a thick converter element for full conversion, in particular with a layer thickness of more than 100 μm.
In contrast, fully converting optoelectronic components for pixel applications require thin converter elements to reduce the so-called pixel-to-pixel crosstalk and thus improve the contrast.
The known converter elements are usually formed as foils, which are arranged on the radiation main side of the semiconductor chip of the optoelectronic component by means of an adhesive layer, for example, of silicone.
Alternatively, the converter elements can also comprise phosphors embedded in a polymer matrix, for example, of silicone, in which the semiconductor chip is embedded. The converter elements can be produced by dispensing, casting or spray coating phosphors embedded in silicone.
Both arrangements have the disadvantage that little heat flows from the converter element (stokes energy) through the matrix material, in particular polymers such as silicone, to the semiconductor chip heat sink and thus the application temperature and/or duration is limited.

Optoelectronic component and method of producing an optoelectronic component


Systems and techniques for converting an analog input signal to a digital code are described. A system includes a differential stage to produce a sign bit indicative of a sign of the analog input signal and to generate a first analog signal that is approximately equal to an absolute value of the analog input signal. The system also includes an analog-to-digital converter (ADC) to convert the first analog signal to a second digital code representing a magnitude of the analog input signal and a controller to combine the second digital code and the sign bit to produce a first digital code.

A bipolar analog-to-digital converter (ADC) converts an analog input signal to a digital output code that can represent both positive and negative values. Although there are different ways to represent a negative number as a digital code, most representations use the most significant bit (MSB) of the code to signify whether the represented value is positive or negative. The MSB is sometimes referred to as a "sign bit". Examples of binary representations of negative numbers include a one's complement representation and a two's complement representation.
The transfer function of an ADC is a plot of the code generated at the ADC output as function of the input signal value. Such a plot is not continuous but is a plot of 2N steps, where N the number of bits in the digital output. For an ideal ADC, a single straight line can be drawn through the points at each code-transition boundary, beginning at the origin of the plot.
FIG. 1 shows a plot 2 of an ideal transfer function 4 for a 3-bit ADC with reference points at code transition boundaries. The ADC in this example produces a total of eight steps that each represents a value of the analog input signal as a two's complement binary code. In this case, the MSB (i.e., the first bit of each code) signifies whether the code represents a negative or a positive value. For example, all of the digital codes having an MSB equal to "1" represent negative values, and all of the digital codes having an MSB equal to "0" represent either a positive value or zero. The transition occurs at one code width, which is equal to a least significant bit (LSB). The actual value of an LSB is equal to Vref/2(N−1), where Vref is the reference voltage that determines the full-scale range of the ADC (i.e., the range of analog input values that ADC can convert to digital values). The resolution of the ADC, which determines the best accuracy to which the ADC can represent an analog input value, is equal to the value of the LSB. In the example shown in FIG. 1, the resolution is Vref/4.


Embodiments of the invention are directed to systems, methods, and computer program products for providing a multi-channel cognitive resource platform configured for intelligent, proactive and responsive communication with a user, via a user device. The system is further configured to perform one or more user activities, in an integrated manner, within a single interface of the user device, without requiring the user to operate disparate applications. Furthermore, the system is configured to receive user input through multiple communication channels such as a textual communication channel and an audio communication channel. The system is further configured to switch between the various communication channels seamlessly, and in real-time.

Existing systems require a user to navigate multiple applications and perform numerous actions to perform electronic activities on an electronic device. Furthermore, execution of the electronic activities requires the user to be adept with various distinct functions and technology elements of a myriad applications. As such, conducting electronic activities on electronic devices is often extremely time consuming, cumbersome and unwieldy. There is a need for an intelligent, proactive and responsive system that facilitates execution of electronic activities in an integrated manner, and which is capable of adapting to the user's natural communication and its various modes.

Multi-channel cognitive resource platform


A method and system for providing call center emergency services to one or more occupants of a vehicle having a plurality of listening zones within a passenger compartment of the vehicle. The method involves detecting a potential emergency condition, sending an emergency notification to a call center, receiving a listening zone control signal identifying at least one of a plurality of listening zones in the vehicle, and supplying audio received from the identified listening zones(s) to the call center via a voice call between the vehicle and call center.

Vehicles commonly come equipped with user interfaces that provide not only manual inputs (e.g., pushbutton switches) and visual and audio output, but that increasingly use speech-based inputs from a driver or other occupant to provide vehicle services. These services may include those carried out exclusively at and by the vehicle, or those which utilize a telematics service provider via a wireless telematics capability of the vehicle or via a personal mobile device such as a cellular phone carried by the driver or other occupant.
Telematics service providers are able to provide vehicle occupants with emergency and other assistance via a call center operation that typically includes a live advisor who carries out voice conversations with the vehicle occupant(s). In the vehicle, occupant speech is picked up within the passenger compartment via a microphone system that may include one or more microphones configured to received audio from one or more listening zones within the vehicle.

Call center based zoned microphone control in a vehicle


In a highway expansion apparatus for a key telephone system and an operation method thereof, by connecting a MPB (main process board) of a master system with a system LMU (ink module unit) of an expansion system through a cable and generating a highway to be provided from the MPB to the expansion system, a highway of the key telephone system can be expanded.

1. Field of the Invention
The present invention relates to a telephone system and in particular to a key telephone system.
2. Background of the Related Art
In general, a key telephone system is a small telephone exchange system for relaying telephone communication between extensions or between an extension and an outside phone by connecting plural telephones with extension numbers in order to use limited telephone lines by a great number of people. The key telephone system consists of a main device, telephone sets, lines connecting the main device with the telephone sets and an additional unit for operating the system more efficiently.
However, in the related unit key telephone system, the system can be limited to a maximum number of voice time slots provided through one switching unit, and it is not possible to expand voice channels to exceed the limited maximum number. In addition, in the related art key telephone system, a request for capacity expansion of the system cannot be satisfied.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.

Highway expansion apparatus for key telephone system and operation method thereof


A method and apparatus for improving the performance of a memory wordline decoder is disclosed. A decoder latch is attached to an inverter which drives the wordline. Additionally, a voltage pump can supply operating voltage to the inverter to assist in overdriving the wordline. A voltage sink can also be coupled to the inverter which, in combination with the voltage pump, can be used to shift the output voltages used to turn the wordline on and off. A second inverter can also be added, and in such a case the transistors within the latch and the first inverter can be reduced in size, switching time, and power consumption.

To achieve high access speeds in memory arrays, including those of flash memory devices, addressed wordlines must be driven as fast as possible. Fast wordline decoder devices for long wordlines tend to require complex latch circuitry for properly driving the wordline. Such circuits draw considerable power. A less complex wordline decoder device which draws less power and occupies less die area is therefore desirable.

This patent is subject to a terminal disclaimer.

High speed wordline decoder for driving a long wordline


A quick release base system that includes a base platform and a removable base. The base platform includes a bottom platform surface and a top platform surface. The top platform surface is positioned above the bottom platform surface. The top platform surface includes platform prongs. The platform prongs are substantially perpendicular to the top platform surface and extend away from the top platform surface and away from the bottom platform surface. The removable base rests on top of the base platform, and the removable base includes an interior base surface. The interior base surface includes base prongs. The base prongs are substantially perpendicular to the interior base surface and extend away from the interior base, and the platform prongs interact with the base prongs to create a lateral restraining force between the base platform and the removable base.

1. Field of the Invention
The invention generally relates to equipment in baseball and softball. More specifically, the invention relates to bases that are used in the games of baseball and softball.
2. Discussion of Related Art
In the United States and Canada and in many East Asian, Latin American and Caribbean countries, the games of softball and baseball are very popular.
Familiarity with the basic concepts of the rules of baseball and softball are assumed, as one of ordinary skill in the art would know the rules intimately. However, the rules of baseball and softball provide for markers known as bases that are positioned at the four corners of a diamond, up to 90 feet in distance depending upon the age level of the players or whether baseball of softball is being played. Three of the bases are commonly referred to as bags, because they are short boxes that are placed on the surface of the ground and rise up one to three inches in height. The fourth base, known as home plate, is much thinner and rises above the ground less than ½ inch.
These bases are commonly held in position in a number of ways. For example, major league teams and other organized baseball leagues generally use hollow, square metal posts or anchors located in the ground at the proper base locations. Stanchions that are attached to the bottom of the bases are placed in the hollow posts/anchors. In this manner, the bases are firmly and fixedly, yet removably positioned for play. Runners naming to the bases do not have to fear that the bases will slide as the runner slides into or steps on the base. This method requires digging a hole into the ground, placing a concrete bed in the hole, setting the anchor/post in the concrete bed and repacking the dirt around the post/anchor. This can be accomplished on a dedicated baseball field.
A second common type of base uses spikes that are driven into the ground that are attached to straps. The straps are cinched tight to the base and the spikes that hold the base in position.
A third common category of common bases is called "throwdown bases." These bases typically are formed from a single piece or molded rubber or vinyl. These bases are generally thinner than, official bases.
Another type of base uses a magnet to secure a base having a bottom metal material. Dislodgement of the base exposes the magnet which can be poorly seen due to dirt and dust accumulating on it.
Other types of bases use either an oversized hole to receive an anchor for the base or can use protruding rubber tips which are inserted in openings formed in a substrate and trapped therein until a sufficient force is applied to the base. Such rubber tips are not able to be freely removed from the substrate.
Moreover, youth baseball leagues have recently mandated that a base is displaced from its position when a runner slides into it. Put another way, leagues are requiring a base that will move when a lateral load is applied. The difficulty is designing such a base that will not substantially move when the runner merely runs across the base, i.e. when the load applied is a combination of a lateral load and a vertical load.
Therefore, there is a need in the art for detachable/removable baseball and softball bases that will not substantially move when a runner runs across it and yet will detach when a runner slides in with sufficient force.

System and method for quick release base for baseball and softball


A communication system has a first communication terminal and a second communication terminal connected to a network. Communication can be performed by the first and second communication terminals in a plurality of modes. The first communication terminal has a detecting unit to detect calls that are refused by the second communication terminal and that are performed in a first mode when a second mode has been set. Based on the detection of the detecting unit, a first calling unit calls the second communication terminal in the second mode. Using the second mode, when the call from the first calling unit is accepted, a mode switching instruction unit instructs the second communication terminal to switch from the second mode to the first mode. Based on a response to an instruction from the mode switching instruction unit, a second calling unit calls the second communication terminal in the first mode. The second communication terminal includes a mode switching response unit. Upon receiving the instruction from the mode switching instruction unit, the mode switching response unit responds to the instruction using the second mode. After the response is returned, a mode switching unit switches the mode from the second mode to the first mode.

(1) Field of the Invention
The present invention generally relates to a communication system capable of changing a calling mode and a terminal used in the communication system, and more particularly to use of a terminal in a communication system constructed in a network, such as an ISDN, to which terminals can be connected in a plurality of modes, and in which a mode can be changed between terminals.
(2) Description of the Related Art
In a communication system constructed in an ISDN, each terminal can communicate with another terminal in any of a plurality of modes, such as an audio communication mode, a 64 kbps data communication mode and the like. In a communication system constructed in a network to which terminals can be in a plurality of modes, if a specific mode of a calling terminal is not set in a terminal that is being called, the calling terminal recognizes that the called terminal is in a busy state.
A user of the calling terminal which recognizes that the called terminal is in the busy state must repeatedly recall by changing the mode until the changed mode is the same as the mode set in the called terminal. As a result, it is often difficult and time consuming to connect the terminal to the network.

Communication system having a changeable calling mode and terminal used in the communication system


A paging method and apparatus for a mobile communication network to which at least two non-coordinated core networks are connected is disclosed, wherein a service state of a mobile station is checked, when a request for a paging message to the mobile station has been received from one of the non-coordinated core networks. Then, a multicall paging message is transmitted using an existing signalling link of the mobile station and/or mobile station location information known in a radio access network, when the mobile station is already connected to another one of the non-coordinated core networks. The checking is preferable performed by a radio network controller which is connected to the non-coordinated core networks. Thus, a paging request received form a non-coordinated core network can be supplied to a mobile station, although the paged mobile station is already connected to another non-coordinated core network.

A paging system is a one-way (wireline to mobile) digital transmission system. Message paging systems will grow with evolution of electronic-mail services, wherein the message communication hardly interrupts the person being called.
A mobile station (MS) of a mobile communication system has three states, i.e. idle, standby, and active. Data can be transmitted between the mobile station and the mobile communication network only when the mobile station is in the active state. In the active state, the cell location of the mobile station is known to the mobile communication network.
Looking at the MS-UTRAN level, an MS basically has only two service states (in the following referred to as UTRAN service states) seen from the higher layer perspective, namely idle and RRC connected. The RRC connected state has further substates that are not visible to the higher layers and/or core network entities. These substates are based on the current channel allocation situation and are called Dedicated Channel (DCH) Active state and Common Channel state. The MS is moved between these two states (and within the substates of these two states, explained below) based on the data activity level of the MS.
The DCH Active state is further divided into two substates based on the type of radio bearer to which a dedicated channel is currently allocated and are called User Data Active state and Control Only state.
The Common Channel state is further divided into two substates based on the accuracy at which an MS location is known in the UTRAN, which is also directly related to the type of downlink common channel which can be used to communicate to the MS. These substates are called RACH/FACH state and RACH/PCH state.
The RACH/PCH state is further divided into two substates based on the accuracy at which the MS location is known within this state. These states are called Single Cell PCH state and URA (UTRAN Registration Area) state.
In the idle state, the MS does not have a logical network context activated or any corresponding addresses allocated. In this state, the MS can only receive multi cast messages which can be received by any MS. Since the mobile communication network does not know the location of the MS, it is not possible to send messages to the MS from external networks.
If multiple non-coordinated core networks are connected to one radio access network (such as UTRAN) of the mobile communication network and one of the core networks has an active connection with an MS, while a "non-active" core network starts paging towards the MS, a special procedure is required to transfer the paging message to the mobile station, because the MS normally does not listen to a paging channel during the active state.
In a GSM-GPRS system, only class-A mobile stations (capable of simultaneously listening both GSM and GPRS control channels) can be paged, if a Gs interface between a Mobile Switching Center (MSC) and an SGSN (Serving GPRS Support Node) is missing. If the Gs interface exists and the MS is attached to the GPRS, it can be paged from the circuit-switched side (GSM) using GPRS channels. If a GPRS data channel is active, the circuit-switched paging can be routed via that data channel.
However, no solution has been proposed so far as to a paging control method to be performed if a circuit-switched call is active and a paging request arrives from a non-coordinated packet-switched network.
Also, for the UMTS system, where only one set of control channels in UTRAN are available even if two independent core network entities are connected to the same UTRAN, a novel method is required for the paging control.


Provided is an code rearranger and method for a virtual machine that uses a just-in-time-compiler (JITC) to manage a location of machine code stored in a code cache. The apparatus may rearrange consecutively-executable machine codes from among those stored in the code cache to be placed successively.

1. Field
The following description relates to a virtual machine that uses a just-in-time compiler (JITC) as a software execution environment.
2. Description of the Related Art
A virtual machine may be used to run an application in a device that is equipped with heterogeneous central processing units (CPUs) and memories.
Code that is written in a high-level language may be distributed, for example, as a script or as hardware-independent intermediate code. The code may be executed by the interpreters or the machine language translators of virtual machines that are installed in various devices.
Examples of a virtual machine include a JAVA® virtual machine, which is widely used in mobile phones, digital TVs, and the like. Other examples include JAVASCRIPT® which is code that may be transmitted via the web, a DALVIK® virtual machine, and the like.
Various applications may be run in various embedded devices such as mobile phones, digital TVs, servers, desktops, and the like, using virtual machines. Bytecode is generally distributed as execution code for a virtual machine to be run in diverse execution environments. The distributed bytecode may be executed by an interpreter. However, in executing bytecode, the interpreter is slower than when executing machine code. To prevent such a drawback and increase execution speed, a just-in-time compiler (JITC) may be utilized.
For example, the JITC may compile bytecode that is currently being executed into machine code, store the machine code in code cache of a virtual machine, and utilize the stored machine code while executing the compiled bytecode. The JITC may track a path from a certain position of bytecode in the course of running virtual machine, and generate machine code that corresponds to a predefined length of a bytecode trace.
The bytecode trace may be a segment of code of a predefined length of bytecode. The bytecode trace may prevent consumption of a large amount of time and/or the generation of an excessive amount of machine codes in the JITC.
In a tracking scheme, bytecode is executive in logically consecutive order, however, the order for a JITC to compile bytecode traces may not always follow the logical order for executing the bytecode.
Machine code generated by the JITC may be stored in a code cache of the virtual machine, and even when the bytecode is consecutive, the machine code may be stored in an inconsecutive manner if the machine code is generated at different times by the JITC.
Additionally, if the stored machine code has an increase in the number of jump instructions attached thereto, and if the length of each bytecode trace is short, the number of machine codes to be stored increases, and thus, the performance of the code cache may deteriorate.

Code rearranger and method for rearranging code for a virtual machine


A lightweight technique for sharing memory pages within a virtual machine (VM) is provided. This technique can be used on its own to implement intra-VM page sharing or it can be augmented with sharing across VMs. Memory pages whose content can be described by some succinct grammar, such as a regular expression or simple pattern, are identified for sharing within a VM. If the content of a page matches some simple pattern, it is proposed to share such a page, but only in the scope of the VM to which it belongs, i.e., intra-VM sharing. All other pages, i.e., those that are not simple patterns, can be candidates for sharing in the scope of all currently active VMs, i.e., inter-VM sharing. Either fully functional page sharing across VMs and/or page sharing in the context of each VM can be implemented.

A virtual machine (VM) is an abstraction, i.e., a "virtualization," of a physical computer system and provides an environment in which an operating system may execute with apparent control of a dedicated physical machine. Multiple virtual machines may execute on a common hardware machine and each virtual machine may operate with protection and isolation from other virtual machines executing on the same common hardware machine. Each virtual machine typically encapsulates a complete executing state for a corresponding operating system, including both user-level applications and kernel-mode operating system services.
In many computing environments, each hardware machine is typically underutilized when executing a corresponding server application. As a result of hardware underutilization averaged over many hardware machines, computing environments configured to dedicate a hardware machine to each server application are typically characterized as being very inefficient with respect to cost, power consumption, management, and, potentially, reliability.
Virtual machines are advantageously deployed to consolidate multiple software servers in a computing environment onto one or more shared hardware machines for execution. A hypervisor is a software layer that virtualizes hardware resources and presents a virtual hardware interface to one or more virtual machine instances that may reflect an underlying hardware machine architecture or an abstraction of an arbitrary machine architecture. The hypervisor may perform certain management functions with respect to an executing virtual machine.
Each virtual machine executing on a hardware machine includes a memory image of apparent physical memory. Because virtual machines tend to have working sets that are smaller than memory configured for the virtual machine, hardware machine memory may be efficiently overcommitted for many applications. For example, a hardware machine with four gigabytes of total machine memory may host a set of virtual machines that has a total of sixteen gigabytes of apparent configured physical memory. While approximately four gigabytes of machine memory are actually available at any one time, this four gigabytes of machine memory can be used by the virtual machines in the set in a multiplexed manner by demand-paging to a file residing in an attached mass storage system. The mass storage system conventionally comprises one or more magnetic hard disk drives, however, any form of mass storage system may be used. For example, in modern computer systems the mass storage system may comprise a solid-state drive (SSD) or an array of SSDs. Page sharing and ballooning, among various techniques, may be employed to reduce demand paging and enhance overall efficiency.
Page sharing is a memory reclamation technique widely used in virtual execution environments. This technique saves memory by eliminating duplicate pages—once such duplicates are identified for a given page's content, corresponding guest pages are mapped to the same shared machine page copy-on-write (COW) and old backing pages are released to the platform.
Ideally, duplicate contents should be identified and a corresponding page should be shared right at the moment a page's content is created, or is about to be created, in guest's memory. One known implementation of such a principle, for example, is when guest code responsible for creation of zero pages is identified by the hypervisor and its execution is skipped. The hypervisor then backs the guest physical memory page with the shared page of that content. Another known example is when an I/O operation reads page contents from a disk block that was already read to a different page. If this situation can be recognized then this read operation, and all subsequent reads from the same disk block, should be skipped and destination guest physical memory pages should be immediately backed with a shared machine memory page. These and other similar methods, however, cannot detect all sharing opportunities so that periodic searches for duplicates, known as transparent page sharing, typically takes place and covers both code and data pages' domains.
Memory content evolves over time and, therefore, so do sharing opportunities. An exhaustive periodic search for duplicates is not an option due to time constraints and, therefore, the scope of any search for duplicates is typically limited to a subset of memory pages. This subset might be obtained, for example, through random page sampling or sequential page scanning. Other selection criteria driven by page locality information, I/O, or execution activity, may also be applied. Another optimization approach typically used to speedup matching of identical pages applies a hash function to a page's content so that the hash values, and not the content, are compared most of the time.
In one known memory sharing approach, for each memory page to be examined, the following steps are typically taken. First, a hash of the page's contents is computed. Then, the result of hashing is looked up in a table that tracks all currently shared pages. If a page with an identical hash is found, a byte-by-byte comparison of the two pages' contents is performed, to assure that the contents do match, so that sharing can be initiated. If no match among already shared pages was found, the previously examined pages (hints) tracked by the same or a different hash table are tried next. As before, a table lookup is followed by a byte-by-byte comparison if a page with an identical hash was found.
Of these, the most expensive operations are hash computation and content comparison, although hash table lookup does not come for free and can produce noticeable overhead if any of the hash tables is improperly balanced.
Hash tables are typically maintained in a context visible to all VMs on the host. When virtualization software controls all the resources of the host itself, i.e., a "bare-metal model," the shared context is provided by the kernel. When virtualization software is running on a commodity operating system, i.e., a "hosted model," such a shared context is implemented in a special kernel module (a vmmon driver in products of VMware, Inc.) loaded in to the host OS and candidates for sharing are supplied there by a user level process. Being in a shared context, therefore, hash tables are typically protected by one or more global locks.
Global lock contentions and context switches, for example, from the user level process to the driver, add additional overhead to page sharing. Further, as the amount of time dedicated to a page sharing service is limited, a maximum rate at which pages may be examined is dictated by the per-page processing overhead. Thus, it is desirable to keep the cost of each operation as low as possible.
What is needed, therefore, is a mechanism for efficiently sharing memory pages in a virtualized system.

Sharing memory pages having regular expressions within a virtual machine


Systems and methods for providing a packaging instruction are disclosed. Sensor data of an item to be packaged is captured. The item is identified based on one or more detectable features. The item is determined to be associated with a plurality of item-specific characteristics that require different packaging materials. A plurality of user interface elements comprising the plurality of the item-specific characteristics is presented. A selection of one of the plurality of item-specific characteristics is received. An alternative packaging instruction associated with the received selection of the one of the plurality of item-specific characteristics is presented.

Packing systems and methods are critical to ensuring an item within a parcel arrives undamaged at its destination. Everything from the size of the parcel to the cushioning material itself will minimize any risk of the item being damaged as it is transported. Given that packaging items is a tedious and subjective process, it is a process that is prone to failure. For example, the item may be damaged during the shipment process at no fault of the carrier, but based on poor packaging procedures or using the wrong type of cushioning materials. Even more, packing the item according to certain guidelines could be critical to obtaining insurance coverage. For example, insurance coverage may require that the item be packed according to certain guidelines before it guarantees coverage of any claims.


A viscous electrophoresis separation medium is disclosed. The medium is formed by a matrix formed by a copolymer composed of hydrophilic polymer segments having selected, substantially uniform segment lengths, and a plurality of hydrophobic polymer segments carried on, and spaced from one another at regular repeating intervals, by the hydrophilic polymer segments. Also disclosed is an electrophoresis method which employs the separation medium, and novel copolymers used in forming the medium.

Gel electrophoresis is a powerful method of separating large biomolecules, such as proteins, deoxyribonucleic acids (DNA), and ribonucleic acids (RNA). In gel electrophoresis, a mixture of biomolecules is placed on a selected gel medium and the gel is subjected to an external electric field. The velocity (v) of migration of a biomolecule through the gel depends on the strength of the electric field (E), the net charge (z) on the molecule, and the frictional coefficient (f) of the medium: EQU v=Ez/f
The frictional coefficient depends on the mass and shape of the molecule and the viscosity of the medium.
Gels have become the preferred medium for conducting electrophoretic separations because they suppress the convective currents produced by small temperature gradients in less viscous media, and they act as molecular sieves which inhibit movement of large molecules, but permit smaller molecules to move readily through the pores of the gel. Polyacrylamide gels have generally been the medium of choice for performing separations because they are chemically inert and their pore sizes can be controlled by selection of a desired ratio of acrylamide and methylenebisacrylamide (cross-linking agent), and total monomer concentrations used in polymerization. The polyacrylamide gel is typically generated by free radical polymerization of the component monomers, using a free radical initiator, in the presence of the electrophoresis medium.
Electrophoretic separations of proteins are often performed in a cross-linked polyacrylamide gel under protein denaturing conditions. For example, proteins can be dissolved in a detergent solution, e.g., sodium dodecyl sulfate (SDS), and subjected to mercaptoethanol or dithiothreitol treatment to reduce any disulfide bonds. The SDS anions bind to the protein at a ratio of about one SDS molecule to two amino acid residues, thereby imparting a large net negative charge and bulk to the denatured protein. The charge and bulk of the protein-SDS complex are roughly proportional to the mass of the native protein. Displacements of a protein or peptide within a gel matrix can thereby be related to molecular size on a basis of the size and charge on the molecule. In the case of nucleic acids, which have roughly the same charge density, displacement in the gel matrix is more directly related, to molecular size.
Electrophoresed complexes are usually visualized by staining with a dye, such as Coomassie blue, or by autoradiography when the molecules are radioactively labelled. The displacement of a biomolecule in the gel is nearly linearly proportional to the logarithm of the mass of the molecule, with exceptions found for such species as glycosylated and membrane proteins. Proteins differing by as little as 2% in mass can often be distinguished by electrophoresis (see, generally, Stryer, L.).
One electrophoretic technique that permits rapid, high-resolution separation is capillary electrophoresis (CE) (Cohen, 1987, 1988, Compton, Kaspar) In one CE procedure, a capillary tube is filled with a fluid electrophoresis medium and the fluid medium is crosslinked or temperature-solidified within the tube to form a non-flowable, stabilized separation medium. A sample volume is drawn into or added to one end of the tube, and an electric field is applied across the tube to draw the sample through the medium. Typically, a bioseparation conducted by CE employs fused silica capillary tubes having inner diameters between about 50-200 microns, and ranging in length between about 10-100 cm or more.
The polymer concentration and/or degree of cross-linking of the separation medium may be varied to provide separation of species over a wide range of molecular weights and charges. For example, in separating nucleic acid fragments greater than about 1,000 bases, one preferred temperature-solidified material is agarose, where the concentration of the agarose may vary from about 0.3%, for separating fragments in the 5-60 kilobase size range, up to about 2%, for separating fragments in the 100-3,000 basepair range (Maniatis). Smaller size fragments, typically less than about 1,000 basepairs, are usually separated in cross-linked polyacrylamide. The concentration of acrylamide polymer can range from about 3.5%, for separating fragments in the 100-1,000 basepair range, up to about 20%, for achieving separation in the 10-100 basepair range. For separating proteins, crosslinked polyacrylamide at concentrations between about 3-20% are generally suitable. In general, the smaller the molecular species to be fractionated, the higher is the concentration of crosslinked polymer required.
The resolution obtainable in solidified electrophoresis media of the type described above has been limited, in the case of small molecular weight species, by difficulties in forming a homogeneous, uniform polymer matrix at high polymer concentration within an electrophoresis tube, and especially within a capillary tube. In one general method for forming a high-concentration solidified matrix in a tube, a high-concentration polymer solution, in a non-crosslinked, low-viscosity form, is introduced in fluid form into the tube. The fluid material is then crosslinked, for example, by exposure to light in the presence of persulfate and a cross-linking agent.
At high polymer concentrations, reaction heat gradients formed within the tube tend to produce uneven rates of reaction and heat turbulence which can lead to matrix inhomogeneities. Also, entrapped gas bubbles generated during the crosslinking reaction produce voids throughout the matrix. The non-uniformities in the matrix limit the degree of resolution that can be achieved, particularly among closely related, small molecular weight species. These problems may be overcome by polymerizing the gel material at elevated pressure; however, producing a controlled pressure within a capillary gel introduces difficult technical problems.
In the case of temperature-solidified gels, a polymer is introduced into an electrophoresis tube in a fluid form, then allowed to gel to a solid form by cooling within the gel. This approach, however, is generally unsuitable for fractionating low molecular weight species, such as small peptides and oligonucleotides, since the polymers, such as agar and agarose, that are known to have the necessary temperature-solidifying setting properties are not effective for fractionating low molecular weight species, even at high polymer concentrations.
A second limitation associated with crosslinked or temperature solidified matrices is the difficulty in removing crosslinked gel matrix from the gel support. In the case of a capillary-tube support, this may prevent recovery of separated material within the gel, and also may prevent reuse of the capillary tube.
Isoelectric focusing (IEF) is another separation method based on the migration of a molecular species in a pH gradient to its isoelectric point (pI). The pH gradient is established by subjecting an ampholyte solution containing a large number of different pI species to an electric field. Biomolecules added to the equilibrated ampholyte solution will migrate to their isoelectric points along the pH gradient. The components can then be isolated by eluting the gradient and capturing selected eluted fractions.
Although IEF methods are usually carried out in a low-viscosity fluid medium, it is occasionally advantageous to perform the IEF separation in a stabilized matrix. Crosslinked or temperature-stabilized gels of the type described above have been employed in IEF methods, but present some of the same limitations noted above for electrophoretic methods. In particular, the stabilized gels are generally not removable from capillary tubes, and isolating separated molecular species from the matrix may be inconvenient because exhaustive dialysis or electroelution are required.

Viscous electrophoresis polymer medium and method


A VCSEL with a near planar top surface on which the top electrode is deposited. A VCSEL according to the present invention includes a top electrode, a top mirror having a top surface, a light generation region, and a bottom mirror for reflecting light toward the top mirror. At least one of the mirrors includes a plurality of planar electrically conducting layers having different indices of refraction. In addition, at least one of the layers includes an oxidizable material. To expose this layer to an oxidizing agent (thereby converting the material to an electrical insulator), three or more holes are etched down from the top surface of the VCSEL to the layer containing the oxidizable material. The oxidizing agent is then introduced into the top of these holes. The partial oxidation of the layer converts the layer to one having a conducting region surrounded by an electrically insulating region, the conducting region being positioned under the top electrode.

Semiconductor laser diodes were originally fabricated in a manner that led to a diode structure that was parallel to the surface of the semiconductor wafer. In this structure, light is emitted from the edge of the structure such that the light is also emitted parallel to the surface of the semiconductor wafer. Unfortunately, this structure does not lend itself to low cost "mass" manufacturing or to the cost-effective fabrication of two-dimensional arrays of laser diodes.
A second class of laser diodes is fabricated such that the laser structure is perpendicular to the surface of the semiconductor wafer and the light is emitted perpendicular to the surface. These laser diodes are commonly known as Vertical Cavity Surface-Emitting Lasers (VCSELs). A VCSEL may be viewed as a laser having mirrors constructed from alternating layers of material having different indices of refraction. These lasers are better suited for the fabrication of arrays of lasers for displays, light sources, optical scanners, and optical fiber data links. Such lasers are currently being considered for use in CD-ROM drives, DVD heads, and laser printers.
To provide small diameter light beams while maintaining efficient conversion of electrical energy to light, the current flowing vertically in the VCSEL must be confined to a small area. Early designs utilized ion-implanted regions to contain the current flow; however, this approach is not satisfactory for very small confinement areas. In addition, implanted regions do not offer any index-guided optical confinement.
A method for containing the current flow and also for providing optical confinement is to convert a portion of one or more of the mirror layers in the upper mirror to an electrical insulator. These VCSELs utilize an oxidation process to convert one or more high aluminum content layers within the VCSEL structure to some form of aluminum oxide. The oxidation process proceeds along the layer from the outer edge of an etched mesa toward the center of the mesa. The process is stopped prior to converting the entire layer, thereby leaving a small unoxidized area in the center of the mesa, which defines the laser aperture.
One problem with these native-oxide VCSELs is the nonplanar geometry currently employed in fabricating such devices. To provide access to the layer being oxidized, the device is first etched to form a mesa-like structure with the edges of the various mirror layers exposed. The exposed edges are then subjected to the wet oxidation process.
If a number of lasers are to be constructed on a common substrate, this process leads to a device in which each laser is an isolated mesa on the substrate. The surface of the device has large steps which make the deposition of the various metallic conductors, such as those used for contacts, difficult. In addition, the need to provide trenches between the devices limits the density of lasers that can be fabricated in array structures. Even in the case of single devices, the raised mesa structures make it difficult to deposit metal for the connections to the electrode on top of the mesa.
Broadly, it is the object of the present invention to provide an improved VCSEL structure and method for fabricating the same.
It is a further object of the present invention to provide a VCSEL structure that provides a near planar top surface.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.

Near planar native-oxide VCSEL devices and arrays using converging oxide ringlets


The invention refers to a LED-based assembly (100) comprising: —an electrical device comprising circuit boards (110-1,110-2) arranged to drive and/or supply arrays of LEDs (111-1,111-2) electrically and mechanically connected thereto; —an optical device provided onto the electrical device and comprising optical boards (120) partly mounted onto the circuit boards (110-1,110-2).

Several electronic and optical architectures of such LED-based assemblies have been proposed and implemented in light products or systems over the course of the last few years. Some of them struggle with cost, manufacturability and maintenance.
The cost-control, when designing a light system, is indeed becoming crucial, while in the mean time the light system performance must be optimized.
In LED-based luminaires, it is preferred to have all LEDs connected onto a single printed circuit board ("PCB") for handling and releding reasons. PCB is fixed to the chassis and optical elements, or an optical board including optical elements, are also fixed to the chassis through the PCB to cover the LEDs.
The chassis (e.g. a heat sink) has usually a clean and good-finished interface with the PCB to insure a good thermal contact. For a large-sized PCB, these requirements involve extra-costs—e.g. foundry costs.
Furthermore, a high number of types of PCBs and optics needs to be provided to comply with the various designs and specifications of LED-based systems or luminaires. This diversity of PCBs and optics can be a serious handicap in an industrial environment as a factory can end up with a shortage of useful components inducing a longer delivery lead time for the product, and the unused components may stay in stock for some time which is undesirable in a Lean environment.

LED-based assembly with fixating optical boards


A liquid crystal display includes first and second opposing substrates having first and second opposing surfaces, respectively, at least one of the surfaces having a metal disposed thereon, the substrates bonded together with an adhesive in contact with the metal, the adhesive comprising a blend of: a pressure sensitive adhesive component comprising at least one polymer having acid or base functionality, a high Tg polymer having a weight average molecular weight greater than 100,000 and having an acid or base functionality, and a crosslinker, wherein the functionality of the pressure sensitive adhesive component and the functionality of the high Tg polymer form an acid-base interaction when mixed.

Devices employing liquid crystals have found use in a variety of electrooptical applications, in particular those which require compact, energy-efficient, voltage-controlled light valves, e.g., watch and calculator displays, as well as the flat-panel displays found in portable computers and compact televisions. Liquid crystal displays (LCDs) have a number of unique characteristics, including low voltage and low power of operation, which make them good candidates for use in non-emissive electrooptical display applications. Optical adhesives have been utilized in LCD applications. They are typically used in bonding processes during assembly of an original display as well as for after-market repair.

Optical adhesive for liquid crystal display


A housing for hot-pluggable network tap modules. The housing allows a user to maintain all network taps in any given system in one housing and location. This increases the ease of maintaining multiple network taps and allows the network tap modules to be powered by a power supply included with the housing. The housings can greatly simplify the process of managing multiple taps. Moreover, the housing are compatible with hot-pluggable network tap modules as well as legacy network tap modules that were developed in the past.

1. Related Applications
The present application claims priority to U.S. Provisional Patent Application Ser. No. 60/470,610, with a filing date of May 15, 2003 entitled "HOUSING FOR HOT PLUGGABLE NETWORK TAPS," and U.S. Provisional Patent Application Ser. No. 60/508,532, with a filing date of Oct. 2, 2003 entitled "HOUSING FOR HOT PLUGGABLE NETWORK TAPS," each of which is incorporated herein by reference in its entirety.
2. The Field of the Invention
The present invention relates to network taps for providing access to network data for analysis purposes. More specifically, the present invention relates to housings for receiving a set of pluggable network tap modules, including a shared power supply used by the network tap modules
3. The Relevant Technology
In recent years, it has become increasingly important to have the ability to monitor and analyze the data flow in communication channels between and within networks. Some of these reasons include monitoring the communication channel for certain types of data, identifying and diagnosing network problems, detecting interruptions in the communication channel, detecting degradation in the communication channel, and the like. Thus, network taps, which are systems for tapping into communication lines, have been developed. In general, a network tap is a device that is positioned in-line in a network communication line and enables network analyzers or other devices to have access to a copy of the data transmitted over the communication line. A network tap is typically installed by physically cutting or breaking a network cable and positioning the tap between the two ends of the network cable. Once the tap is installed, network analyzers or other devices can access the network data without having to manipulate the network cable or altering the topology of the network. Moreover, conventional network taps enable access to the network data without disrupting or modifying the network data or the topology of the network.
Systems using conductors composed of metallic materials such as copper or other low resistance metals have generally been relatively easy to monitor and evaluate without great disruption or intrusion into the communication channel since current flows throughout the entire conductor and portions of the conductor can be externally tapped with another conductor attached to the test equipment that bleeds off a negligible amount of test current.
Additionally, optical fibers that transmit light have also been used as a communication channel medium and have proven to be advantageous for the transmission of large amounts of information, both in digital and analog form. Optical fibers, unlike metallic conductors, propagate the information signal in a constrained directional path. Furthermore, the optical signal propagates primarily in a relatively narrow internal portion of the conductor, making non-intrusive external tapping of the fiber impractical. Therefore, in order to monitor data transmitted on an optical fiber, a splitter, also known as a coupler, must be placed in-line with the optical fiber to reflect a portion of the light from the main optical fiber to another optical fiber that can be coupled to a network analyzer or other test equipment.
Existing network taps typically are housed within a module including a faceplate through which various connections may be made. For example, the network tap module may include a set of in-line pass through connections to allow the tap to be positioned in line with the network (e.g. an "in" and "out" connection) in addition to one or more connections which allow a user to tap into the network for analysis purposes. Existing network tap modules also include a connector for receiving power, typically at the rear of the module.
Each network tap module allows the user to tap into the network at one specific location or on one selected cable or communication link between nodes in a network. Often, it is desirable to tap into the network at multiple communication links. To do this, a separate network tap must be inserted into each communication link to be accessed. Multiple taps also facilitate accessing and monitoring multiple channels that carry network data. Because each network tap module must be connected to a power supply, this can result in a system of network tap modules spread throughout a network, each module connected to its own power supply.
The several power supplies may represent a significant cost and, when multiple network tap modules are stored together, a separate power supply and the associated power cables for each tap module is inconvenient and intrusive. Furthermore, having individual network tap modules scattered throughout a network can be inefficient and confusing. In addition, each time a tap is inserted into a network, another potential link failure point is introduced into the network. Network link failures may result in loss of critical communication and data. Although network reliability is highly important, many network administrators have had to sacrifice reliability for the advantages gained from using conventional network taps. It would thus be an advantage to reduce the inefficiency and confusion of having the network tap modules scattered throughout the system. Furthermore it would be an advantage to reduce the number of power supplies required for the several network tap modules. It would also be useful to provide a network tap system that significantly reduces the likelihood of link failure at network taps.


On a semi-insulating substrate, an emitter layer (or a collector layer), a base layer, a compound semiconductor layer containing In and a collector layer (or an emitter layer) are provided. The collector layer (or the emitter layer) is patterned to form a collector region (or an emitter region). When the base surface is revealed by a reactive ion beam etching, the etching will be stopped at the compound semiconductor layer that contains In. Consequently, the nonuniformity in the base resistance that depends on the thickness of the base lead-out region can be reduced.

The present invention relates to heterojunction bipolar transistors and fabrication methods thereof.
The bipolar transistors have an excellent feature that their current drive performance is superior to that of the field effect transistors. Because of it, research and development of the bipolar transistors using not only silicon but also compound semiconductors such as gallium arsenide is actively engaged in recent years. In particular, the heterojunction bipolar transistors that use compound semiconductors (referred to as HBTs hereinafter) have such an advantage as enabling to hold the emitter injection efficiency at a high level even when the base is doped to a high concentration by making the gap of the forbidden band of the emitter to the greater than that of the base.
Next, an example of the collector-up type HBT will be described following the steps of its fabrication.
First, an n-Al.sub.0.25 Ga.sub.0.75 As layer (emitter layer), a p-GaAs layer (base layer) and a n-GaAs layer (collector layer) are sequentially formed by a molecular beam epitaxy method- (referred to as MBE method hereinafter) on a semi-insulating substrate consisting of GaAs. Next, after forming a collector electrode of a predetermined pattern having a silicon oxide film on its surface, and a collector region is formed by etching the n-GaAs layer using the collector electrode as a mask. Subsequently to the above process, a base electrode is formed according to a predetermined pattern on the exposed p-GaAs layer. Next, the p-GaAs layer outside the base electrode and the surface part of the underlying n-Al.sub.0.25 Ga.sub.0.75 As layer are removed, and an emitter electrode is formed on the exposed n-Al.sub.0.25 Ga.sub.0.75 As layer.
The thickness of the p-GaAs layer on which is formed the base electrode is determined by an etching process (the base surface revealing process) that forms the collector layer. In the base surface revealing process, a part of the surface of the p-GaAs layer is exposed by etching the overlying n-GaAs layer, but the contact resistance between the base layer and the base electrode becomes high if the etching of the n-GaAs layer is insufficient. Such an increase in the contact resistance can be avoided by etching the surface part of the p-GaAs layer. Since, however, the thickness of the p-GaAs layer underlying the base electrode (the base lead-out region) becomes smaller than that of the active base layer (the part in contact with the collector layer) as a result of such an operation, the base resistance will have to be increased. In practice, the thickness of the base lead-out region has to be made slightly smaller than that of the active base layer in order to avoid the increase in the contact resistance.
Consequently, the adequacy of the above-mentioned process strongly influences the high speed and the high frequency characteristics of the resulting transistor. In addition, the thickness of the base layer has a very small value of 70 to 100 nm so that the nonuniformity in the etching amount within the wafer becomes one of the causes of drastically reducing the uniformity of the characteristics of the elements. Heretofore, it has been very difficult to carry out the above-mentioned process for the entirely of the wafer under a sufficiently satisfactory controllability, and it has been inevitable to have a nonuniformity on the order of 20 nm for 2-inch wafers.
In the case of the emitter-up type HBTs, the base surface revealing process means to etch the AlGaAs layer. In this connection there is a report that it is possible to selectively remove the AlGaAs layer by a wet etching. Namely, according to P. M. Asbeck et al., "GaAlAs/GaAs Heterojunction Bipolar Transistors: Issues and Prospects for Application," IEEE Transactions on Electron Devices, Vol. 36, No. 10, p. 2032, October 1989, it is possible to carry out the surface revealing with a standard deviation of 3 to 4 nm for 2-inch wafers. However, the inventors were unable to confirm this with sufficient reliable reproducibility. In other words, the selective removal of the AlGaAs layer cannot be said to be a sufficiently matured technology. Moreover, from the sense of simplifying the fabrication process, the simultaneous use of a wet etching is not desirable. So far as the dry etching methods are concerned, there is not known a means for selectively removing the AlGaAs layer with respect to the GaAs layer, so that there exist the same problems as for the collector-up type HBTs.

Method of fabricating a heterojunction bipolar transistor


A process of preparing gold-coated magnetic nanoparticles is disclosed and includes forming a suspension of magnetic nanoparticles within a suitable liquid, adding an amount of a reducible gold compound and a reducing agent to the suspension, and, maintaining the suspension for time sufficient to form gold-coated magnetic nanoparticles.

In recent years, there has been an interest in using nanoparticles and magnetic nanoparticles for medicinal and biomolecular applications. U.S. Pat. No. 6,470,220 by Kraus, Jr. et al. described diagnosis and treatment of cancers using in vivo magnetic domains. This treatment approach employs a magnetic particle having a cancer-binding agent attached thereon. The cancer-binding agent should have binding specificity for the desired cancer cells. Such magnetic particles can be used as imaging agents in conjunction with magnetic resonance imaging (MRI), as a directing agent for therapeutics guided by external magnetic fields and for magnetotherapy techniques.
One prime candidate for the magnetic material is samarium cobalt. However, samarium cobalt has not previously been used as an agent within the body and has not previously been tested for biocompatibility. Thus, necessary governmental approvals would be required prior to the use of samarium cobalt.
Since samarium cobalt has such desirable magnetic properties for selected therapeutics and magnetotherapy techniques, a biocompatibly acceptable composition including a magnetic material such as samarium cobalt has been sought. After extensive and careful investigation, a composition has now been developed, in particular, a gold-coated magnetic particle composition.
It is an object of the present invention to provide a process of preparing a gold-coated nanoparticle composition, in particular a gold-coated magnetic nanoparticle composition for use in biotechnology applications.
It is another object of the present invention to provide a gold-coated nanoparticle composition, in particular a gold-coated magnetic nanoparticle composition for use in biotechnology applications.

Gold-coated nanoparticles for use in biotechnology applications


A composite stone which includes a first half-stone having a mating edge with a first length and a second half-stone having a mating edge with a second length which is approximately equal to the first length is provided. At least a first baguette and a second baguette are mounted between the first and second half-stones. Each of the at least first and second baguettes has a first mating edge and a second opposing mating edge which have a third length that is approximately equal to the first length. The first mating edge of the first baguette is generally aligned with the mating edge of the first half-stone. The second mating edge of the second baguette is generally aligned with mating edge of the second half-stone. The second mating edge of the first baguette faces the first mating edge of the second baguette.

The present invention relates to a novel arrangement of precious stones, and more particularly, to the arrangement and setting of four or more precious stones, such as diamonds, in a manner which provides the appearance of a single larger marquise, navette or other shaped stone.
Precious stones such as diamonds have varying commercial and esthetic value depending, among other factors, on their color, clarity, cut, and size. While color, clarity and cut are important factors in the marketability of a gem or setting, the size of a gem contributes greatly to the purchaser's perception of value and desirability. Ordinarily, in order to present a large viewable surface of a precious stone such as a diamond, it is necessary to employ a large stone. This can entail a considerable expense. Unfortunately, some natural gem stones are not readily available in sufficient quantity in the desired larger sizes to meet the market demand or, if available, are prohibitively expensive in the larger sizes. As a result, certain types of larger stones, such as emeralds, are now man made. However, this solution is not practical with diamonds. Additionally, consumers generally prefer natural gem stones over artificial ones, so the creation of man made stones, where possible, does not address this problem.
One known solution is to employ settings that hold two smaller stones together to provide the appearance of a single larger stone. A combination of smaller stones costs less than a single larger stone having the same total weight, and there is less loss of stone in the cutting process. This known technique has been attempted by the present inventor and others for producing so-called Marquise or Navette stones.
One known technique for constructing a composite marquise or navette stone has been to assemble two half-marquise stones, base-to-base, giving the appearance of a contiguous whole. The composite stone created by this method is, however, limited based on the geometry and proportions of the resulting assembled stone, as well as by the cost and availability of suitable stones for cutting larger half-marquise or other types of stones. It would therefore be desirable to create a composite stone of a larger size than that produced using two half-stones in order to satisfy the demands of the market.
Some prior attempts to assemble smaller stones into a larger contiguous whole have not been entirely successful in that the assembled stones often exhibit a dark band or zone in the region of the juncture between stones and/or include joints which are apparent. Additionally, dust and dirt particles become wedged between the stones when the joints are apparent. These disadvantages detract from the value and beauty of the assembled stones.
Prior attempts to eliminate these undesirable qualities have not been entirely successful. One reason for this lack of success is that the marquise-halves or escutcheons are generally elliptical stones, and the same basic cutting methods have been applied to them as have been used for the "brilliant" cutting of generally circular stones. This generally resulted in "dark zones" in the assembled stones because of less than optimal light reflection.


A bottle includes an outer vessel formed of a transparent or clear material and an inner vessel slightly smaller than the outer vessel and received therein to create a space therebetween. A cap is secured to the outer vessel and defines apertures therein. The outer vessel defines a closed upper end having apertures aligned with the cap apertures. A valve body providing check valves operable in opposite directions is coupled to a pair of straws which in turn are directed upwardly through the respective apertures and are joined at a common pump bulb. The pump bulb is formed of a resilient elastic material and cooperates with the check valves to displace liquid from the outer vessel to the inner vessel as the bulb is repeatedly squeezed and released. A doll cooperating with the bottle receives the pump bulb in a mouth opening and provides mouth motion to squeeze and release the pump bulb.

A variety of dolls have been provided by practitioners in the art which relate to simulated eating and drinking and which perform these simulations to varying degrees of realism. Drinking dolls in particular have enjoyed substantial development and attention by practitioners. As a result, drinking dolls have been provided in various designs and themes. However, all generally utilize a mouth aperture and, in some instances, moving lips together with a tube conducting liquid from the mouth aperture to an interior reservoir within the doll abdomen. Typically a baby bottle having a nipple suitable for insertion in a fitting attachment to the doll mouth aperture is provided. Often sound circuits are provided in which the doll responds to the administering of liquid by the user with contended sounds and/or cries in the absence of such. In most such drinking dolls, a liquid is ingested into the doll body and is collected within a reservoir. In some, this collected liquid is released through the lower torso to simulate wetting while in others the retained liquid must be emptied by the user. The retained liquid in such dolls often creates a messy situation due to the requirement that an emptying tube, valve, and port must be provided. In addition, the need to continuously empty the interior bladder detracts from the realism of the doll since this is an unnatural activity. Also such dolls very often utilize a very large volume internal bladder or reservoir which detracts from the realism of the doll as liquid churns within the reservoir interior.
U.S. Pat. No. 3,005,283 issued to Cohn sets forth a LIP MOVING MECHANISM FOR A DOLL OR THE LIKE having a resilient doll head and face joined to a doll torso. Within the doll head an internal aperture is formed and an apparatus is operative upon the mouth to cause it to open and close simulating lip movement. A tube leads from the doll mouth to a reservoir within the torso of the doll. A nipple and bottle is inserted into the mouth aperture and the lip movement adds realism to the activity.
U.S. Pat. No. 3,016,651 issued to Brudney sets forth a DOLL MOUTH having a doll head supporting a position actuated mouth valve which receives a feeding bottle. At one position of the doll, the mouth valve is closed while at an alternate position the mouth valve is open facilitating the ingestion of liquid.
U.S. Pat. No. 2,945,321 issued to Carter sets forth an IMITATIVE NURSING DOLL having a doll supporting a pivotable arm and a hand thereon for securing a nursing bottle. The hand and arm are pivotally supported to facilitate positioning the nipple of the nursing bottle within the doll's mouth.
U.S. Pat. No. 427,927 issued to Steiner sets forth a DOLL having a mouth aperture coupled to a passage extending through the doll head and exiting at the back of the neck. A tube is coupled through the passage and is secured to the straw of a liquid bottle. The remaining end of the tube exits downwardly and terminates in a reservoir supported beneath the seat of the doll.
Still other patents show various related structures. For example, U.S. Pat. No. 4,971,048 issued to Seekins sets forth a DUAL VALVE LIQUID TRANSFER TUBE FOR USE IN COMBINATION WITH A PROTECTIVE MASK while DES. U.S. Pat. No. 217,317 issued to Homorodean, Jr. et al sets forth a MULTIPLY SPIRALLED CURVED DRINKING STRAW. In addition, German Patent 405,500 sets forth a MULTIPLY FEATURED DOLL INCLUDING AN ASSOCIATED NURSING BOTTLE while French Patent 432,650 sets forth a DRINKING DOLL having an interior reservoir within the doll torso and a tube leading therefrom upwardly to a mouth aperture. The tube includes a vertical portion to confine liquid ingestion to the circumstances in which the doll is substantially horizontal.
While the foregoing described prior art devices have provided some improvement in the art, and have in some instances enjoyed commercial success, they remain subject to various limitations including the difficulty of retaining a large liquid mass within the doll. In addition, such prior art devices often fail to achieve sufficient realism or maximizing the enjoyment by young children. In further addition, the need for emptying internal liquid reservoirs in many of the prior art dolls further limits the attractiveness of the toy.


Methods of subsea communication in which a cathodic protection anode is used as a transmitting antenna. The signals are received at a second location by two electrodes which are spaced apart by different distances from the transmitting antenna.

1. Field of the Inventon
This invention relates to subsea communication.
2. Description of Related Art
There are a wide variety of different circumstances in which it is desirable to be able to communicate between bodies in a subsea environment. The term subsea is used in this application as this is conventional terminology, however, it should be appreciated that the term subsea encompasses any underwater situation.
A specific example of where subsea communication is important is in the operation of tetherless Autonomous Underwater Vehicles (AUVs) and tethered remotely operated vehicles (ROVs). Such vehicles need to be controlled and the data which they gather needs to be extracted. It is preferable if this control and extraction of data can be done on a regular basis (perhaps in real time) and without the need for a physical connection between the vehicle and, say, a surface vessel and without the need to bring the vehicle back to the surface vessel.
Various means of communication between AUV's and other locations have been investigated. One possibility is acoustic transmission but this suffers from difficulties because of noise generated by the fans which drive the AUV.


A method of manufacturing a semiconductor substrate is provided. The method includes a first step of forming a rugged portion in a GaN substrate, and a second step of forming a GaN thin film on the GaN substrate at a lateral growth rate fast enough to cover the GaN thin film vertically grown with the GaN thin film laterally grown, so that the rugged portion is covered with the GaN thin film.

1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor substrate, and more particularly, to a method of manufacturing a high grade GaN substrate.
2. Description of the Related Art
GaN is a material widely used for transistors, field emitters and optical devices as well as microelectronics devices. GaN is used for producing various kinds of compound semiconductor materials such as AlGaN, InGaN and AlInGaN.
A GaN layer is usually grown on a sapphire substrate or a silicon carbide (SiC) substrate. However, since the lattice constant of a sapphire substrate or silicon carbide substrate is different from that of a GaN layer, the GaN layer grown on the sapphire substrate or silicon carbide substrate contains many small crystal grains of a hexagonal system. The crystal grains have a high defect density and a warped and rotary distribution provoking a broad X-ray rocking curve. Here, the defective density of a GaN layer is about 108-10/cm2.
As the defect density of a GaN layer decreases, the applicability of the GaN layer increases. Accordingly, a variety of GaN layer manufacturing methods for lowering the defect density of a GaN layer have been proposed. FIGS. 1 through 4 show one of these methods step by step. FIGS. 5 and 6 show the steps of another method.
Referring to FIG. 1, a GaN layer 12 is grown on a sapphire substrate (or a silicon carbide substrate) 10. Here, the defect density of the GaN layer 12 is at least 108/cm2. Reference numeral 13 denotes a symbolized crystalline defect. As shown in FIG. 2, a silicon oxide mask layer 14 is formed in a predetermined pattern on the GaN layer 12. Subsequently, the growth of the GaN layer 12 is continued, as shown in FIG. 3. However, the GaN layer 16 does not vertically grow above the silicon oxide mask layer 14 but vertically grows on an exposed portion which is not covered with the silicon oxide mask layer 14. Thereafter, when the thickness of the vertically grown GaN layer 16 is significantly larger than that of the silicon oxide mask layer 14, the GaN layer 16 laterally grows on the silicon oxide mask layer 14. The GaN layer 16 continuously grows, and finally, the boundaries of the GaN layer 16, which laterally grows starting from both sides of the silicon oxide mask layer 14 and extends on the silicon oxide mask layer 14, meet, as shown in FIG. 4. With such a step, a second GaN layer 16 having a planarized surface is formed on the GaN layer 12 so that the entire surface of the silicon oxide mask layer 14 is covered with the second GaN layer 16. Here, due to the silicon oxide mask layer 14 involved in the growth of the second GaN layer 16, a tilt boundary Btilt is formed within the second GaN layer 16 directly upward from the boundary of the silicon oxide mask layer 14. In addition, a coalesced boundary Bc is formed at a portion where the two boundaries of the second GaN layer 16 growing from both sides of the silicon oxide mask layer 14 meet.
The more detailed description of the above GaN layer growth method is disclosed in U.S. Pat. No. 6,051,849 issued to Davis et al.
The second GaN layer 16 has the following characteristics. As shown in FIG. 4, the second GaN layer 16 has a defect density difference between a first portion 16a formed on the silicon oxide mask layer 14 and a second portion 16b formed between silicon oxide mask layers 14. In other words, the defect density of the first portion 16a is much lower than that of the GaN layer 12, but the defect density of the second portion 16b is almost the same as that of the GaN layer 12. It can be derived from this result that the potential of the GaN layer 12 does not propagate to form the second GaN layer 16 having a lower defect density than the GaN layer 12 when the GaN layer 12 laterally grows, while the potential of the GaN layer 12 propagates resulting in no improvement in a defect density when the GaN layer 12 vertically grows.
Another example of a conventional technique of growing a GaN layer will be described below with reference to FIGS. 5 and 6. Referring to FIG. 5, a GaN layer 12 is grown on a sapphire substrate (or a silicon carbide substrate) 10. A predetermined region of the GaN layer 12 is etched. A trench 18 having a predetermined depth is formed in the sapphire substrate 10 exposed by the etching process. Thereafter, as shown in FIG. 6, in a state in which the GaN layer 12 is formed on the entire surface of the sapphire substrate 10 except the trench 18, a third GaN layer 20 is grown on the sapphire substrate 10 and the GaN layer 12. Here, the third GaN layer 20 does not grow at the etched portion in the sapphire substrate 10, that is, at the trench 18 region, in either direction between vertical and horizontal directions while the third GaN layer 20 grows vertically and horizontally at the portion not etched in the sapphire substrate 10. During this process, the third GaN layer 20 is not formed in the trench 18 region, so the trench 18 remains as a void 22 after completion of the growth of the third GaN layer 20.
As described above, according to a conventional method of growing a GaN layer, a GaN layer is formed first on a sapphire substrate (or a silicon carbide substrate), and a mask layer is formed on the GaN layer or a trench is formed at a predetermined region of the sapphire substrate in order to prevent the potential of the GaN layer from propagating, thereby forming another GaN layer having a lower defect density. Such conventional methods of growing a GaN layer have the following problems.
First, in the case of the first conventional method shown in FIGS. 1 through 4, due to the surface tension difference between the second GaN layer 16 and the silicon oxide mask layer 14, the crystals of the second GaN layer 16 are tilted forming defects at the coalesced boundary. Moreover, during this process, grooves are formed on the surface of the second GaN layer 16.
Second, since a different sort of material such as a silicon oxide mask layer is introduced, a strain distribution in a growing GaN layer is non-uniform.
Third, since the heat conductivity of silicon oxide (SiO2) used to form a mask layer is lower than a GaN layer, the thermal reliability of a device may be degraded when the device is formed on the GaN layer formed on the mask layer.
Fourth, in the case where the void 22 is formed between the grown third GaN layer 20 and the sapphire substrate 10, as shown in FIG. 6, the resistance of a device formed on the third GaN layer 20 increases, which lowers the reliability of the device.
Fifth, the structure of a device may be vulnerable due to the void 22.
Sixth, in the case of the conventional method shown in FIGS. 5 and 6, it is necessary to etch the sapphire substrate 10 to form the trench 18. However, it is not easy to etch the sapphire substrate 10.
To solve the above-described problems, it is an object of the present invention to provide a method of manufacturing a high-grade semiconductor substrate without using a mask layer or by preventing crystalline defects from propagating to the surface of a grown semiconductor substrate even if using the mask layer.
To achieve the above object of the invention, there is provided a method of manufacturing a semiconductor substrate including a first step of forming a rugged portion having a predetermined depth in a first semiconductor substrate; and a second step of forming a second semiconductor substrate on the first semiconductor substrate at a lateral growth rate fast enough to cover the GaN thin film vertically grown with the GaN thin film laterally grown so that the rugged portion is covered with the second semiconductor substrate.
Here, the first step includes forming a trench in the first semiconductor substrate, and the second step further includes forming a mask on the first semiconductor substrate around the trench.
Alternatively, the first step includes the sub steps of forming a first rugged portion in the first semiconductor substrate, and transforming the first rugged portion into a second rugged portion.
The first semiconductor substrate is realized as a III-V compound semiconductor substrate, and preferably, as a GaN substrate.
The first rugged portion is formed to include protrusions, the surface of which is composed of a top and a slope bordered by the top, and a recess between the protrusions. The second rugged portion is formed to include a second protrusions having the shape of a pyramid with a sharp point, and a recess between the second protrusions.
According to the present invention, the defect density of a lower semiconductor substrate can be prevented from propagating to an upper semiconductor substrate, thereby obtaining the upper semiconductor substrate having a lower defect density than the lower semiconductor substrate. In addition, a low defect density area in the upper semiconductor substrate is much wider compared to prior art.

Method of manufacturing GaN semiconductor substrate


Methods, circuits, devices, and systems are provided, including a delay line for a delay-locked loop. One method includes providing a reference clock to a first delay unit in a delay line. The delay line includes a number of delay units coupled together. Even delay units, among the delay units, are coupled to an even clock line to generate a first intermediate clock. Odd delay units are coupled to an odd clock line to generate a second intermediate clock. The even and odd delay units are configured to in a manner intended to restrict an increase in drive to load ratio and to intrinsic delay as additional delay units are coupled to the number of delay units.

In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative to the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically are synchronized to external operations. For example, commands are placed on a command bus of the memory device in synchronism with the external clock signal, and the memory device latches these commands at the proper times to successfully capture the commands. To latch the applied commands, an internal clock signal is developed in response to the external clock signal, and is applied to latches contained in the memory device to thereby clock the commands into the latches. The internal clock signal and external clock are synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully capture the commands. In the example of FIG. 1, "external" is used to refer to signals and operations outside of the memory device, and "internal" to refer to signals and operations within the memory device. However, as the reader will appreciate, the principles described in the present disclosure are broadly applicable to aligning data output to a clock signal, external signals to input signals, etc. The present disclosure is directed to synchronous memory devices. However, as the reader will appreciate, the principles described herein are applicable to other types of synchronous integrated circuits.
Internal circuitry in the memory device that generates the internal clock signal introduces some time delay, causing the internal clock signal to be phase shifted relative to the external clock signal. As long as the phase-shift is small, timing within the memory device can be synchronized to the external timing. To increase the rate at which commands can be applied and at which data can be transferred to and from the memory device, the frequency of the external clock signal is increased, and in modern synchronous memories the frequency is in excess of 100 MHz. As the frequency of the external clock signal increases, however, the time delay introduced by the internal circuitry becomes more significant. This is true because as the frequency of the external clock signal increases, the period of the signal decreases and thus even small delays introduced by the internal circuitry correspond to significant phase shifts between the internal and external clock signals. As a result, the commands applied to the memory device may no longer be valid by the time the internal clock signal clocks the latches.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different approaches have been considered and utilized, including delay-locked loops (DLLs), phased-locked loops (PLLs), and synchronous mirror delays (SMDs), as will be appreciated by those skilled in the art. As used herein, the term synchronized includes signals that are coincident and signals that have a desired delay relative to one another.
A DLL is a feedback circuit that operates to feed back a phase difference-related signal to control a delay line, until the timing of a first clock signal, e.g., the system clock, is advanced or delayed such that its rising edge is coincident (or "locked") with the rising edge of a second clock signal, e.g., the memory internal clock.
FIG. 1 illustrates a block diagram of a DLL 100. The DLL 100 receives a reference clock (RefCLK) 112 as an input and generates an output clock (CLKOut) signal 114 at its output. The CLKOut signal 114 is in turn fed back as a feedback clock signal (ClkFB or FB Clock) 116. The reference clock 112 can be the external system clock serving the system processor(s) or a delayed, buffered version of it. The system clock 112 may be supplied to the DLL 110 via one or more clock buffers (not shown).
The delay line in the DLL 100 can include a coarse delay line 118 and a fine delay line 120. The RefCLK 112 may be supplied first to the course delay line 118 whose output is then fed into the fine delay line 120 to generate the ClkOut signal 114. The coarse delay line 118 may include a number of coarse delay stages (not shown) and may be designed to produce an output signal having phase variation from an input signal within a coarse delay stage, whereas the fine delay line 120 is designed to produce an output signal having a phase variation from the input signal which is smaller than the deviation provided by the coarse delay line 118. In other words, the coarse delay line 118 is designed to bring its output signal to a near phase lock condition, or phase delayed condition, whereas the fine delay line 120 is designed to perform "fine tuning" to achieve the signal locking condition. Thus, a dual delay line (coarse and fine) DLL or PLL can provide a wide lock range while at the same time still providing a tight lock within reasonable time parameters.
In operation, the clock output signal 114 is used to provide the internal clock (not shown) used, for example, by memory device (not shown) to perform data read/write operations on memory cells (not shown) and to transfer the data out of the memory device to the data requesting device, e.g., a processor. As can be seen from FIG. 1, the ClkOut signal 114 (and, hence FBClock 116) is generated using delay lines 118, 120, which introduce a specific delay into the input RefClk 112 to obtain the "lock" condition.
As noted the purpose of the DLL 110 is to align or lock the internal clock (not shown) used by, for example, a memory device to perform data read/write operations to the system's external clock (not shown). A delay monitor 122 monitors a delay time of the output clock 114 from the coarse and fine delay lines 118, 120 to DQ output and a delay time of clock input buffer. A phase detector (PD) 124 compares the relative timing of the edges of the system's external clock and the memory's internal clock by comparing the relative timing of their respective representative signals, e.g., the RefClk 112 which relates to the system clock, and the FBClock signal 116 which relates to the memory's internal clock, so as to establish the lock condition. The PD 124 may compare a phase difference between the RefClk 112 and the FBClock 116 (supplied via the delay monitor) and output appropriate shift signals SHL (shift left) signal 125 and SHR (shift right) signal 126 for adjusting the phase difference between the RefClk 112 and the FBClock 116. The delay monitor circuit 122 may function as a buffer or dummy delay circuit for the ClkOut signal 114 before the ClkOut signal 114 is fed into the phase detector 124 as the FBClock 116. The output of the delay monitor 122, i.e., the FBClock 116, may effectively represent the memory's internal clock, which may be provided to various circuit elements in a memory device through the clock driver and data output stages (not shown). Thus, the delay monitor 122 attempts to maintain the phase relationship between the RefClk 112 and the FBClock 116 as close as possible to the phase relationship that exists between the external system clock and the memory's internal clock.
The RefClk 112 and the FBClk 116 are fed as inputs into the phase detector 124 for phase comparison. The output of the PD 124, e.g., one of the SHL 125 and SHR 126 signals, controls the amount of delay imparted to the RefClk 112 by the delay lines 118, 120. The SHL125 and SHR 126 signals may determine whether the RefClk 112 should be shifted left (SHL) or shifted right (SHR) through the appropriate delay units in the delay lines 118, 120 so as to match the phases of the ReiCik 112 and the FBClock 116 to establish the lock condition. The SHL 125 and SHR 126 maybe supplied to the delay lines 118, 120 via shift register 128, which may control the delay time of the delay time of the delay lines 118, 120 according to the shift signals SHL and SHR from the phase detector 128. Based on the status of the SHL 125 and the SHR 126 signals input thereto, the shift register 128 may generate one or more delay adjustment signals 130 to carry out the left or right shift operations indicated by the phase detector 124. As is known in the art, a shift left operation in delay line results in adding a delay to the clock signal input thereto, whereas a shift right operation reduces the delay. The delay adjustment signals 130 essentially serve the same purpose as the SHL 125 or the SHR 126 signals, but their application to the coarse and fine delay lines 118, 120, respectively, is controlled by the shift register 128. The cumulative delay imparted to the RefClk 112 by the series-connected coarse and fine delay lines 118, 120, respectively, operates to adjust the time difference between the ClkOut signal 114 (as represented by FBClock 116) and the input RefClk 112 until they are aligned. The phase detector 124 generates the shift left (SHL) and shift right (SHR) signals depending on the detected phase difference or timing difference between the RefClk 112 and the FBClock 116, as is known in the art.
In the DLL 110 of FIG. 1, when the RefClk 112 is output from the coarse delay line 118 and input to the fine delay line 120, the switching at the boundary of coarse and fine delays may result in creation of jitters(s) or discontinuity in the final signal output from the fine delay line 120, i.e., the ClkOut signal 114. These clock perturbations may not be desirable, especially when an electronic device, e.g., a memory device is operated at significantly high clock frequencies, e.g., 800 MHz or higher. Furthermore, as reference clock frequencies increase, the DLL architecture in FIG. 1 may not be suitable to adequately control coarse shifting at such high frequencies, which may negatively affect the signal integrity of the ClkOut 114 and may also delay the establishment of a lock condition.
It is therefore desirable to devise a clock synchronization circuit that avoids output clock signal jitter at high frequencies and the also performs a smooth phase transition at the boundary of the coarse and fine delays. It is also desirable to have this synchronization circuit able to adequately control coarse shifting at higher clock frequencies without any limitations.