In a method of manufacturing a static memory device, a patterning process is performed to a lamination film composed of a first insulating layer, a first conductive layer, a second insulating layer and a second conductive layer with regions for load resistors. A lamination section of the first insulating layer and the first conductive layer are separated through the first and second patterning processes into first to fourth portions. The first and second portions respectively functioning as parts of the word line which are connected to each other and as the gates of the transfer MOS transistors, and the third and fourth portions respectively functioning as gates of the drive MOS transistors. The second conductive layer is separated through the second patterning process into fifth and sixth portions, and the fifth and sixth portions respectively functioning as parts of the power supply line which are connected to each other and as the load resistors connected to the parts of the power supply line. The fifth and sixth portions are laminated on a set of the first and third portions and a set of the second and fourth portions via the second insulating layer, respectively.

1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the semiconductor device. More particularly, the present invention relates to a resistance load type Static Random Access Memory (SRAM) in which a resistance pattern and a power supply line pattern are formed in a same layer, and a manufacturing method of the resistance load type SRAM.
2. Description of the Related Art
In recent years, in an SRAM, high integration has been carried out. As an SRAM suitable for the high integration, a resistance load type SRAM is conventionally known. A 1-bit memory cell of the resistance load type SRAM is composed of four N-type metal-oxide-semiconductor (MOS) transistors T1 to T4 and two load resistive elements R1 and R2 of high resistance, as in an equivalent circuit shown in FIG. 16.
As shown in FIG. 16, the drain of each of the driving MOS transistors T1 and T2 of a pair is connected to the gate of the other of the MOS transistors T1 and T2. Also, both of drains of the driving MOS transistors T1 and T2 as accumulation nodes N1 and N2 are connected to a power supply line Vcc through the load resistors R1 and R2, respectively. Also, both of the sources of the driving MOS transistors T1 and T2 are connected in common to a ground potential line Vss. The driving MOS transistors T1 and T2 and the load resistors R1 and R2 construct a flip-flop circuit and a small amount of current is supplied from a power supply. One of the source and drain regions of each of the data transfer MOS transistors T3 and T4 is connected to a corresponding one of the accumulation nodes N1 and N2 of the flip-flop circuit. Also, the other of the source and drain regions of each of the MOS transistors T3 and T4 is connected to a corresponding one of digit lines D1 and D2. Both of the gate electrodes of the MOS transistors T3 and T4 are connected to a word line W.
Next, a first structure example of a memory cell in the conventional resistance load type SRAM will be described with reference to FIGS. 1A, 1B, 2A and 2B.
FIG. 1A is a plan view illustrating a lower layer plane structure in the first structure example of the memory cell of the conventional resistance load type SRAM, and FIG. 1B is a plan view illustrating an upper layer plane structure of the conventional first structure example of the memory cell. Also, FIG. 2A is a cross sectional view of the first structure example of the memory cell along the 2A-2A' line shown in FIGS. 1A and 1B, and FIG. 2B is a cross sectional view of the first structure example of the memory cell along the 2B-2B' line shown in FIG. 1A and 1B.
As shown in FIGS. 1A, 1B, 2A and 2B, an element isolation region 2, a gate oxide film 3 and a gate polycide layer 4 are formed in the surface of a silicon substrate 1. The gate polycide layer 4 is formed as a lamination layer of a polysilicon layer and a silicide layer on the polysilicon layer. Source and drain diffusion layers are formed on the surface of the silicon substrate 1 on both sides of the gate polycide layer 4. These MOS transistors correspond to the MOS transistors T1 to T4 shown in FIG. 16, respectively. In this case, the gate polycide layer 4 as the gate electrodes of the MOS transistors T3 and T4 is also used as the word line W shown in FIG. 16.
An interlayer insulating film 5 is laminated on the MOS transistors T1 to T4, and a polysilicon layer 6 is formed and patterned on the interlayer insulating film 5 to form polysilicon patterns 6a and 6b. The polysilicon patterns 6a are doped with phosphorus ions to form low resistance sections, and act as power supply line patterns. Also, the polysilicon patterns 6b are left in a high resistance state. These high resistance sections correspond to the load resistors R1 and R2 shown in FIG. 16, respectively.
An interlayer insulating layer 7 is formed on the polysilicon layer 6, and a metal layer is formed on the interlayer insulating film 7, and then the metal layer is patterned to form ground line patterns 8.
Further, an interlayer insulating film 9 is formed on the interlayer insulating film 7 and the ground line patterns B. A metal layer is formed on the interlayer insulating film 9, and then the metal layer is patterned. These metal layers 10 correspond to the digit line D1 and D2 shown in FIG. 16, respectively.
In this case, the polysilicon layer 6b, the gate polycide layer 4 and the silicon substrate 1 are connected by a common contact 11. Also, the metal layer 8 as the ground line patterns and the silicon substrate 1 are connected by ground contacts 12. Further, the metal layers 10 as the digit lines D1 and D2 and the silicon substrate 1 are connected by digit contacts 13.
In the memory cell of the first structure example described above, there is a problem that a short-circuit is easily formed between the ground contact 12 and the polysilicon layer 6b or the gate polycide layer 4. The reason will be described below.
As shown in FIG. 2A, the ground contact 12 must be formed on the silicon substrate 1 between a gate polycide layer 4a and a gate polycide layer 4b such that the ground contact 12 and one of the gate polycide layers 4a and 4b do not form a short-circuit. For its purpose, when a hole for the ground contact 12 is formed, the position of the ground contact 12 must be adjusted in such a manner that it is not displaced with respect to the patterns of the gate polycide layers 4.
However, the ground contact 12 must be formed between the polysilicon layers 6a and 6b formed in the upper layer of the gate polycide layers 4. Therefore, the position of the ground contact 12 must be also adjusted in such a manner that it is not displaced with respect to the polysilicon layers 6a and 6b.
Generally, in the step that the layout of a memory cell is designed, the polysilicon layers 6b are designed to be formed on the positions straightly above the gate polycide layers 4a and 4b. Therefore, if the ground contact 12 is formed in such a manner that a short-circuit is not formed between the ground contact 12 and each of the gate polycide layers 4a and 4b, the short-circuit would not be formed between the ground contact 12 and each of the polysilicon layers 6b.
In actual, however, because a patterning process of the gate polycide layer 4 and a patterning process of the polysilicon layer 6 are separately performed in the manufacturing step, both of the gate polycide layers 4a and 4b and the polysilicon layers 6b are never completely coincident with each other. Thus, there is a slight position displacement between these two patterns.
For this reason, when the hole for the ground contact 12 is formed, if the position of the ground contact 12 is adjusted to be suitable for the gate polycide layers 4a and 4b, a short-circuit becomes easy to be formed between the ground contact 12 and the polysilicon layers 6b. On the other hand, when the position of the ground contact 12 is adjusted to be suitable for the polysilicon layers 6b, a short-circuit becomes easy to be formed between the ground contact 12 and the gate polycide layers 4a and 4b.
A second structure example of a memory cell formed to solve the above problem is disclosed in Japanese Laid Open Patent Disclosure (JP-A-Heisei 3-248558). Hereinafter, the second structure example of a memory cell of a conventional resistance load type SRAM mentioned in the above reference will be described with reference to FIGS. 3A, 3B, 4A and 4B.
FIG. 3A is a plan view illustrating the lower layer plane structure of a memory cell in the second structure example of a memory cell of conventional resistance load type SRAM, and FIG. 3B is a plan view illustrating the upper layer plane structure of the memory cell. Also, FIG. 4A is a cross sectional view in the second structure example of the memory cell along the 4A-4A' line in FIGS. 3A and 3B, and FIG. 4B is a cross sectional view in the second structure example of the memory cell along the 4B-4B' line in FIGS. 3A and 3B.
As shown in FIGS. 3A and 3B and FIGS. 4A and 4B, an element isolation region 22 is formed in the surface of a silicon substrate 21. Further, a gate lamination film composed of a gate oxide film 23, a gate polycide layer 24, a first silicon oxide film 25, a polysilicon layer 26, and a second silicon oxide film 27 is formed. Then, the gate lamination film is patterned to form gate lamination film patterns 28. Source and drain diffusion layers are formed on the surface of the silicon substrate 21 on both sides of each of the gate lamination film patterns 28. These correspond to the MOS transistors T1 to T4 shown in FIG. 16, respectively.
In this case, the gate polycide layers 24 as the gate electrode of the MOS transistors T3 and T4 are also used as the word line W shown in FIG. 16. The polysilicon layer 26 of the gate lamination film pattern 28 acts as a load resistor and corresponds to the load resistor R1 or R2 shown in FIG. 16.
Also, as shown in FIG. 4B, in a portion 28a of the gate lamination film pattern 28 which corresponds to the gate electrode of one of the driving MOS transistors T1 and T2 shown in FIG. 16, a portion of the gate oxide film pattern 23 and a portion of the first silicon oxide film pattern 25 are previously removed so as to electrically connect the gate polycide layer 24 as the gate electrode and the polysilicon layer 26 as the load resistor to the drain diffusion layer of the other driving MOS transistors.
An interlayer insulating film 29 is laminated on these MOS transistors T1 to T4, and power supply line patterns 30 and ground line patterns 31 are formed on the interlayer insulating film 29. The power supply line pattern 30 and the polysilicon layer 26 are connected by a power supply contact 32. Also, the ground line pattern 31 and the silicon substrate 21 are connected by a ground contact 33. Further, an interlayer insulating film 34 is formed on the interlayer insulating film 29, the power supply line patterns 30 and the ground line patterns 31. Then, a metal layer is formed on the interlayer insulating film 34 and is patterned. The patterns 35 correspond to the digit lines D1 and D2 shown in FIG. 16, respectively. In this case, the metal layers 35 as the digit lines D1 and D2 and the silicon substrate 21 are connected by digit contacts 36.
In the memory cell of the second structure example described above, the polysilicon layer 26 and the gate polycide layer 24 as the load resistors are laminated and are patterned at the same time to form the gate lamination film pattern 28. Therefore, if a position adjustment is performed with respect to the gate lamination film pattern 28 when a hole for the ground contact 33 is formed, the ground contact 33 can be formed in such a manner that a short-circuit is not formed to neither in the polysilicon layer 26 nor in the gate polycide layer 24 as the load resistor.
By the way, in the second structure example of the memory cell of the conventional resistance load type SRAM described above, the polysilicon layer 26 as the load resistor and the power supply line pattern 30 are connected by the power supply contact 32. A contact forming area 37 in which the power supply contact 32 is formed needs to be previously provided for the gate lamination film pattern 28 as the gate electrode of each of the driving MOS transistors T1 and T2 as shown in FIG. 3A. Therefore, there is a problem in increase of the area of the memory cell. In this manner, the SRAM can not be highly integrated.
Also, there is a case that the hole for the power supply contact 32 is formed to have a slight displacement in the adjustment, and the power supply contact 32 is formed out of the contact forming area 37. In this case, a portion of the power supply contact 32 is formed on the side of the gate lamination film pattern 28. Thus, because the gate polycide layer 24 and the power supply contact 32 are electrically connected by the power supply contact 32, there is a problem that the memory cell does not operate in a normal state.
In this manner, because the mask positioning margin in the manufacture process is small, there is a problem of low productivity.

Method of making SRAM having part of load resistance layer functions as power supply line


An image forming apparatus includes an image forming unit, a sheet receiving portion, an ejection roller, and a restriction member. The ejection roller is configured to rotate in a forward direction to eject a recording sheet fed from the image forming unit to the sheet receiving portion, and to rotate in a reverse direction to return the recording sheet to the image forming unit. The restriction member is configured to move between a restriction position where the restriction member protrudes farther in a sheet ejection direction than a peripheral surface of the ejection roller and a retracted position where the restriction member is retracted from the restriction position. The ejection roller is configured to move the restriction member to the restriction position by rotating in the forward direction, and to move the restriction member to the retracted position by rotating in the reverse direction.

Some known image forming apparatuses include an ejection roller configured to rotate in both forward and reverse directions. The ejection roller is configured to rotate in the forward direction to feed a recording sheet ejected from an image forming unit toward a sheet receiving proportion and configured to rotate in the reverse direction to return the recording sheet to the image forming unit.
One image forming apparatus including such an ejection roller is provided with a restriction member configured to, when the ejection roller rotates in the reverse direction, protrude from under the ejection roller toward the sheet receiving portion. In the image forming apparatus, when a recording sheet already ejected onto the sheet receiving portion is drawn and raised, due to static electricity, by a recording sheet to be fed to the ejection roller, the restriction member prevents the recording sheet raised from the sheet receiving portion from being drawn to the ejection roller by holding the raised recording sheet down to the sheet receiving portion.
Another image forming unit includes a restriction member pivotally attached to the main body and urged by a spring in a direction where the restriction member is retracted inside the main body relative to the ejection roller. The restriction member is configured to, when a recording sheet fed to the ejection roller contacts the ejection roller, pivot and protrude to the sheet receiving portion further than the ejection roller.
Still another image forming apparatus includes a restriction member engaged with a solenoid controlled by a controlling unit. When the ejection roller rotates in the reverse direction, the controlling unit operates the solenoid to cause the restriction member to protrude to the sheet receiving portion further than the ejection roller.


The adhesive sheet for manufacturing a semiconductor device is an adhesive sheet for manufacturing a semiconductor device used when a semiconductor element is adhered to an adherend and the semiconductor element is wire-bonded, and is a peelable adhesive sheet in which the 180 degree peeling adhesive strength against a silicon wafer is 5 (N/25 mm width) or less.

1. Field of the Invention
The present invention relates to an adhesive sheet for manufacturing a semiconductor device, a manufacturing method of a semiconductor device using the sheet, and a semiconductor device obtained by the method.
2. Description of the Related Art
In order to correspond to the demand of microminiaturization and realization of high functionality of a semiconductor device, the wiring width of a power line and the interval between signal lines arranged on the entire area of the major surface of a semiconductor chip (a semiconductor element) have been becoming narrow. Thereby, an increase of impedance and interference of signals between signal lines of different nodes occur, which become the cause of impeding the demonstration of sufficient performance in operation speed, degree of allowance in operation voltage, anti-electrostatic breakdown strength, and the like in the semiconductor chip. In order to solve these problems, a package structure is proposed in which the semiconductor element is layered (for example, refer to Japanese Patent Application Laid-Open (JP-A) Nos. 55-111151 and 2002-261233).
On the other hand, as a substance used when a semiconductor element is fixed onto a substrate or the like, an example using a thermosetting paste resin (for example, refer to JP-A No. 2002-179769) and an example using an adhesive sheet in which a thermoplastic resin and a thermosetting resin are combined (for example, refer to JP-A Nos. 2002-261233 and 2000-104040) are proposed.
In the conventional manufacturing method of a semiconductor device, an adhesive sheet or an adhesive is used at the time of adhesion of a semiconductor element and a substrate, a lead frame, or a semiconductor element. The adhesion is performed by compression bonding (die attaching) a semiconductor element and a substrate or the like, and then by curing an adhesive sheet or the like in a heating step. Further, wires are bonded to connect the semiconductor element and the substrate electrically, and then sealing with a sealing resin is performed by molding with the sealing resin and curing (for example, refer to JP-A Nos. 2002-261233 and 2000-104040).
When the above-described wire-bonding is performed, the semiconductor element on the substrate or the like moves due to ultrasonic vibration and heating. Because of this, conventionally, there has been a necessity to fix the semiconductor element so as not to move by heating and curing the thermosetting paste resin and the thermosetting adhesive sheet through a heating step before the wire bonding.
Furthermore, for the adhesive sheet consisted of a thermoplastic resin and the adhesive sheet in which a thermosetting resin and a thermoplastic resin are combined, a heating step is necessary after the die attaching and before the wire-bonding for the purpose of ensuring adhesive strength with an adhesion target and improving wettability.
However, in the case that air bubbles, foreign objects, or the like are mixed in when this adhesive sheet is adhered to a semiconductor element (a wafer) or a semiconductor chip made into an individual piece with a method such as a roller method or vacuum pasting, this adhesive sheet cannot be peeled off nor removed from the semiconductor element or the semiconductor chip made into an individual piece, and the semiconductor element and the like have been wasted. Because of this, production cost has been high and a decrease of the yield has been brought about.

Adhesive sheet for manufacturing semiconductor device, manufacturing method of semiconductor device using the sheet, and semiconductor device obtained by the method


A small jet propulsion watercraft 10 is provided with side wall portions 14a and 14b formed on both the left and right sides of a stepping platform 13, within which water lock devices 36 and 37 are disposed, respectively. The water lock devices 36 and 37 are connected with connecting pipes 38a and 38b located below the stepping platform 13. An exhaust pipe 40 is connected to the front end of the water lock device 37, with the exhaust pipe 40 initially extending forward, extending upward and then rearward, and passing above the water lock device 37 within the side wall portion 14b, and with its end further extending downward to a position below the stepping platform 13. The water lock devices 36 and 37 are connected with small-diameter pipes 39a and 39b at a portion lower than where the connecting pipes 38a and 38b are joined to the water lock devices 36 and 37.

1. Field of the Inventions
The inventions disclosed herein relate to a small jet propulsion watercraft on which an operator typically stands on a platform provided at a rear of the watercraft body (commonly known as "stand-up" type watercraft), and more particularly, to exhaust systems for such watercraft.
2. Description of the Related Art
Typically, stand-up type watercraft include a platform or "foot tray" provided at the rear of its hull for accommodating the operator. A jet pump is typically disposed below the foot tray. The jet pump is usually driven by a small internal combustion engine so as to draw in seawater from a bottom of the watercraft hull and to discharge the water from the stern of the hull, thereby providing thrust to propel the watercraft across a body of water. The engine on such a small jet propulsion watercraft is usually disposed such that its crankshaft extends longitudinally in the fore-to-aft direction of the body.
The engine usually has a plurality of cylinders, each having an intake port and an exhaust port. An intake system is connected to the intake port, and an exhaust system is connected to the exhaust port (see Japanese Patent Publication No. Hei 7-5219).
The exhaust system of this type of small jet propulsion watercraft typically has an exhaust pipe that is joined to the exhaust port of the engine and extends toward the front of the watercraft. An exhaust muffler is usually connected to the exhaust pipe, and a discharge pipe is typically connected to the exhaust muffler to discharge exhaust gas into the atmosphere. The exhaust pipe and the exhaust muffler are disposed inside of an engine chamber within the hull of the watercraft. In other small jet propulsion watercraft, an exhaust system is often includes a water lock device or other similar devices installed in a rear of the hull. In this case, too, most of the exhaust system is installed inside of the engine chamber or another chamber within the hull.


The present disclosure relates to a microorganism producing L-tryptophan in which the microorganism is modified such that a protein having an L-tryptophan-exporting activity comprising the amino acid sequence of SEQ ID NO: 1 is expressed, and a method for producing L-tryptophan using the microorganism.

L-Tryptophan, an essential amino acid, has been widely used as a raw material for feed additives, medicines (e.g., infusion solutions), health food materials, etc. At present, a direct fermentation method using a microorganism is mainly used for the production of L-tryptophan.
Previously, the microorganisms that had mainly been used in the production of L-tryptophan were selected strains exhibiting resistance to analogs through chemical or physical mutation. However, the rapid development of genetic recombination technology and identification of molecular-level regulatory mechanisms in the 1990s has enabled the use of recombinant strains using genetic engineering techniques.
Meanwhile, the expression of a gene capable of exporting a particular amino acid has contributed to an increase in productivity of the corresponding amino acid in microorganisms. The enhancement of the L-lysine-exporting gene (lysE) in a microorganism of the genus Corynebacterium has improved the productivity of lysine (WO 9723597A2). Additionally, the enhancement of the rhtC gene in E. coli has improved the resistance to L-threonine, and simultaneously, has also improved the productivity of L-homoserine, L-threonine, and L-leucine (EP1013765A1). EP1016710B1 discloses that the improvement of the productivity of L-glutamic acid, L-lysine, L-threonine, L-alanine, L-histidine, L-proline, L-arginine, L-valine, and L-isoleucine by enhancing yahN, yeaS, yfiK, and yggA genes, whose functions are not yet identified in E. coli.
However, no exporting protein showing specificity to L-tryptophan has yet been reported. Although the yddG gene of E. coli is known, it shows higher specificity to L-phenylalanine than to L-tryptophan (FEMS Microbiol Lett 275 (2007) 312 to 318). Additionally, in a microorganism of the genus Corynebacterium which is mainly used as a strain producing L-amino acid fermentation, no protein that can export L-tryptophan or an aromatic amino acid has been reported (J Ind Microbiol Biotechnol. 2015 May; 42(5): 787 to 97).
Under the circumstances, the inventors of the present disclosure have succeeded in expressing a novel tryptophan-exporting protein having specificity to L-tryptophan in an L-tryptophan-producing microorganism and have discovered that the amount of L-tryptophan production was significantly improved, thereby completing the present disclosure.

L-tryptophan exporter and method of producing L-tryptophan using the same


A cochlear implant electrode includes an implantable array carrier made of flexible material with electrode contacts distributed on its outer surface along a longitudinal axis. Electrode wires are embedded within the array carrier, each electrode wire having a terminal end electrically connected to a corresponding electrode contact for applying electrical stimulation signals carried by the electrode wires to adjacent neural tissue within the cochlea. Each electrode wire has an inner non-crystal conductive material surrounded by a flexible outer seal. The flexible material of the array carrier is configured to be reactive with the non-crystal conductive material of the electrode wires so that if a break occurs in the outer seal of an electrode wire that allows contact between the flexible material and the non-crystal conductive material, then a local leakage seal will form at the break that resists migration of the non-crystal conductive material to the outer surface of the array carrier.

A normal ear transmits sounds as shown in FIG. 1 through the outer ear 101 to the tympanic membrane 102 which moves the bones of the middle ear 103 that vibrate the oval window and round window openings of the cochlea 104. The cochlea 104 is a long narrow duct wound spirally about its axis for approximately two and a half turns. It includes an upper channel known as the scala vestibuli and a lower channel known as the scala tympani, which are connected by the cochlear duct. The cochlea 104 forms an upright spiraling cone with a center called the modiolar where the spiral ganglion cells of the acoustic nerve 113 reside. In response to received sounds transmitted by the middle ear 103, the fluid-filled cochlea 104 functions as a transducer to generate electric pulses which are transmitted to the cochlear nerve 113, and ultimately to the brain.
Hearing is impaired when there are problems in the ability to transduce external sounds into meaningful action potentials along the neural substrate of the cochlea 104. To improve impaired hearing, auditory prostheses have been developed. For example, when the impairment is related to operation of the middle ear 103, a conventional hearing aid may be used to provide acoustic-mechanical stimulation to the auditory system in the form of amplified sound. Or when the impairment is associated with the cochlea 104, a cochlear implant with an implanted electrode can electrically stimulate auditory nerve tissue with small currents delivered by multiple electrode contacts distributed along the electrode.
FIG. 1 also shows some components of a typical cochlear implant system where an external microphone provides an audio signal input to an external signal processor 111 in which various signal processing schemes can be implemented. The processed signal is then converted into a digital data format for transmission by external transmitter coil 107 into the implant 108. Besides receiving the processed audio information, the implant 108 also performs additional signal processing such as error correction, pulse formation, etc., and produces a stimulation pattern (based on the extracted audio information) that is sent through an electrode lead 109 to an implanted electrode array 110. Typically, this electrode array 110 includes multiple electrode contacts 112 on its surface that provide selective stimulation of the cochlea 104.
After an electrode array has been implanted, the body can react by forming fibrous tissue around the array. This adversely affects the impedance and charge transfer from the electrode contacts, and thus should be avoided or minimized One way to do that is to form a layer of hydrogel material over the electrode contacts. Such hydrogel material is biocompatible and electrically conductive so as to allow for the intended charge transfer from the electrode contact to the adjacent tissue. But the hydrogel material also prevents the direct contact of the metal material of the electrode contacts (e.g., platinum) with the cochlear tissue and thereby avoids formation of the undesirable fibrous tissues over the electrode contacts. See, for example, U.S. Pat. Nos. 5,786,439, 7,519,435, 7,519,435, 8,190,271; which are incorporated herein by reference.
The hydrogel materials swells when it contacts the perilymph fluid within the cochlea, absorbing more than its own dry weight. As this swelling occurs, polymer branches in the hydrogel matrix grow much larger, forcing the hydrogel material away from the electrode surface it lies against. The chemical bond that normally is used to connect the hydrogel material to the electrode array often is not strong enough to resist these swelling induced forces. When that happens, the hydrogel material separates from the electrode array and can undesirably wander away from the implanted array. One solution to this is described in the priority application, U.S. Provisional Patent Application 61/874,388, filed Sep. 6, 2013, which is incorporated herein by reference in its entirety.
Cochlear implants system exhibit high overall reliability. One cause of the rare failures in such systems is the occurrence of open circuits within the electrode array. See Carlson et al., Prevalence and Timing of Individual Cochlear Implant Electrode Failures, Otol Neurotol. 2010 Aug. 31 (6):893-8; which is incorporated herein by reference in its entirety. The main cause of open circuits within cochlear electrode arrays is externally applied force to the metal wires within the silicone array carrier. These forces can occur momentarily with a high amplitude due to an accident, or they may occur chronically at lower amplitude due to micro-movements induced by muscular activity. These forces applied to the metal structure of the electrode wires results in material fatigue and ultimately a mechanical failure, i.e. wire breakage.
To divert/distribute externally applied forces, the electrode wires can be wave-shaped so that induced force moves the entire flexible electrode array and only a fraction of the external force energy directly affects the metal structure of the electrode wire. See U.S. Pat. No. 8,112,161, which is incorporated herein by reference in its entirety. It also is known to achieving a certain stretch-ability by means of defined microstructures such as by thin-film technique, ribbons or grapheme. See, e.g., Someya, Takao (Editor), Stretchable Electronics, Wiley, 484 pages, December 2012, ISBN: 978-3-527-32978-6; which is incorporated herein by reference in its entirety. Some cochlear implant systems also implement multiple redundant electrode contacts and/or electrode wires within the electrode array to allow for the deactivation of an affected electrode(s) without a loss of clinical benefit of the cochlear implant. But if the loss of the clinical benefit is too large, then a revision surgery can be performed, to replace the defective part.
Sometimes, cochlear implant electrodes can contain drugs or chemicals. To avoid ototoxic reactions (i.e. damage to the inner ear due to unintended exposure of drugs or chemicals), the electrode wires are encased in a silicone array carrier and the electrode contacts are made of platinum. See, e.g., Stöver et al., Biomaterials in Cochlear Implants, GMS Curr Top Otorhinolaryngol Head Neck Surg. 2009; 8: Doc10; which is incorporated herein by reference in its entirety.
An alternative approach is taught in U.S. Patent Publication 20130006339 and U.S. Patent Publication 20090171336, which disclose metal wires comprising liquid metal instead of solid metal. But, these publications do not address problems that can arise when such liquid metal wires break.

Cochlear implant electrode with liquid metal alloy


The present invention provides methods for analyzing measurement errors in measured signals obtained in an experiment, e.g., measured intensity signals obtained in a microarray gene expression experiment. In particular, the invention provides a method for transforming measured signals into a domain in which the measurement errors in the transformed signals are normalized by errors as determined from an error model. The methods of the invention are particularly useful for analyzing measurement errors in signals in which at least portion of the error is dependent on the magnitudes of the signals. Such transformed signals permit analysis of data using traditional statistical methods, e.g., ANOVA and regression analysis. Magnitude-independent errors can also be used for comparing level of measurement errors in signals of different magnitudes.

DNA array technologies have made it possible to monitor the expression level of a large number of genetic transcripts at any one time (see, e.g., Schena et al., 1995, Science 270:467-470; Lockhart et al., 1996, Nature Biotechnology 14:1675-1680; Blanchard et al., 1996, Nature Biotechnology 14:1649; Ashby et al., U.S. Pat. No. 5,569,588, issued Oct. 29, 1996). Of the two main formats of DNA arrays, spotted cDNA arrays are prepared by depositing PCR products of cDNA fragments with sizes ranging from about 0.6 to 2.4 kb, from full length cDNAs, ESTs, etc., onto a suitable surface (see, e.g., DeRisi et al., 1996, Nature Genetics 14:457-460; Shalon et al., 1996, Genome Res. 6:689-645; Schena et al., 1995, Proc. Natl. Acad. Sci. U.S.A. 93:10539-11286; and Duggan et al., Nature Genetics Supplement 21:10-14). Alternatively, high-density oligonucleotide arrays containing thousands of oligonucleotides complementary to defined sequences, at defined locations on a surface are synthesized in situ on the surface by, for example, photolithographic techniques (see, e.g., Fodor et al., 1991, Science 251:767-773; Pease et al., 1994, Proc. Natl. Acad. Sci. U.S.A. 91:5022-5026; Lockhart et al., 1996, Nature Biotechnology 14:1675; McGall et al., 1996, Proc. Natl. Acad. Sci. U.S.A. 93:13555-13560; U.S. Pat. Nos. 5,578,832; 5,556,752; 5,510,270; and 6,040,138). Methods for generating arrays using inkjet technology for in situ oligonucleotide synthesis are also known in the art (see, e.g., Blanchard, International Patent Publication WO 98/41531, published Sep. 24, 1998, Blanchard et al., 1996, Biosensors and Bioelectronics 11:687-690; Blanchard, 1998, in Synthetic DNA Arrays in Genetic Engineering, Vol. 20, J. K. Setlow, Ed., Plenum Press, New York at pages 111-123). Efforts to further increase the information capacity of DNA arrays range from further reducing feature size on DNA arrays so as to further increase the number of probes in a given surface area to sensitivity- and specificity-based probe design and selection aimed at reducing the number of redundant probes needed for the detection of each target nucleic acid thereby increasing the number of target nucleic acids monitored without increasing probe density (see, e.g., Friend et al., U.S. patent application Ser. No. 09/364,751, filed on Jul. 30, 1999; and Friend et al., U.S. patent application Ser. No. 09/561,487, filed on Apr. 28, 2000).
By simultaneously monitoring tens of thousands of genes, DNA array technologies have allowed, inter alia, genome-wide analysis of mRNA expression in a cell or a cell type or any biological sample. Aided by sophisticated data management and analysis methodologies, the transcriptional state of a cell or cell type as well as changes of the transcriptional state in response to external perturbations, including but not limited to drug perturbations, can be characterized on the mRNA level (see, e.g., Stoughton et al., International Publication No. WO 00/39336, published Jul. 6, 2000; Friend et al., International Publication No. WO 00/24936, published May 4, 2000). Applications of such technologies include, for example, identification of genes which are up regulated or down regulated in various physiological states, particularly diseased states. Additional exemplary uses for DNA arrays include the analyses of members of signaling pathways, and the identification of targets for various drugs. See, e.g., Friend and Hartwell, International Publication No. WO 98/38329 (published Sep. 3, 1998); Stoughton, International Publication No. WO 99/66067 (published Dec. 23, 1999); Stoughton and Friend, International Publication No. WO 99/58708 (published Nov. 18, 1999); Friend and Stoughton, International Publication No. WO 99/59037 (published Nov. 18, 1999); Friend et al., U.S. patent application Ser. No. 09/334,328 (filed on Jun. 16, 1999).
The various characteristics of this analytic method make it particularly useful for directly comparing the abundance of mRNAs present in two cell types. For example, an array of cDNAs was hybridized with a green fluor-tagged representation of mRNAs extracted from a tumorigenic melanoma cell line (UACC-903) and a red fluor-tagged representation of mRNAs was extracted from a nontumorigenic derivative of the original cell line (UACC-903+6). Monochrome images of the fluorescent intensity observed for each of the fluors were then combined by placing each image in the appropriate color channel of a red-green-blue (RGB) image. In this composite image, one can see the differential expression of genes in the two cell lines. Intense red fluorescence at a spot indicates a high level of expression of that gene in the nontumorigenic cell line, with little expression of the same gene in the tumorigenic parent. Conversely, intense green fluorescence at a spot indicates high expression of that gene in the tumorigenic line, with little expression in the nontumorigenic daughter line. When both cell lines express a gene at similar levels, the observed array spot is yellow. Such a method is often termed "two-channel" measurement as compared to a method in which only one color labeling is measured.
Any quantitative measurement method, if affected by measurement errors, will have uncertainties in the measurement results. DNA microarray technology is not an exception. Differential expression ratios are typically derived from measured intensities in both single-channel and two-channel microarray technologies, so that it is essential to understand the intensity measurement errors. Measurement errors are often described by error models (see, e.g., Supplementary material to Roberts et al, 2000, Science, 287:873-880; and Rocke et al., 2001, J. Computational Biology 8:557-569). In a two-term error model, the first error source is a low-level additive noise of constant variance, which comes from the background of the array chip. This constant noise is independent from the hybridization levels of individual feature spots on a microarray. It may come from the combination of the scanner electronics noise and the chip surface fluorescence due to nonspecific binding. This constant additive noise is typically assumed normally distributed with a mean background. After background level subtraction, which is typically carried out during microarray data processing, the additive mean background becomes zero. The second error source is a multiplicative error that is the combined result of the speckle noise inherent in the coherent laser scanner and the fluorescent dye related noise. The multiplicative error is also called fractional error because its level is directly proportional to the measured intensity level. It is the dominant error source at high intensity levels. Sometimes an extra square-root term is also included to describe the effect of variation in number of available binding sites in a spot. This term is also called the Poisson term, because it is believed that the number of binding sites follows a Poisson distribution, and has a variance which is proportional to the average number of binding of sites.
Many microarray data processing and statistical analysis methods require the variance of the measurement error to be constant. In other words, the measurement variance should not be related to the measurement level over a measurement range. For example, in the commonly used analysis of variance (ANOVA) method, the variables under investigation must have a constant variance. In another example, many data regression and parametric or non-parametric modeling methods used in microarray data normalization and detrending to remove the intensity dependent non-linearity have the underlying assumptions that the data is not heteroskedastic (i.e., not having a changing variance). However, due to the multiplicative and Poisson terms, the measured microarray intensities do not meet the constant-variance requirement. To overcome thisproblem, measured intensities are often transformed to a new domain where the variance becomes a constant. All analysis and data processing are then carried out in the transformed domain. A logarithmic conversion is commonly used to transform multiplicative error to constant variance. But it does not work properly in low intensities where the original additive constant noise dominates. In a piecewise hybrid transformation method, a log transform is applied to high intensities and a linear transform is applied to low intensities. It has better error characteristics near the low intensity end than the simple logarithmic conversion. But the measurement variance of the hybrid-transformed intensity is still not close to a constant. The hybrid-transform can also significantly distort intensity distributions.
There is therefore a need for more efficient method that can be used to characterize measurement errors in measured signals. In particular, these is a need for methods that transform measured signals into a transformed domain which facilitate analysis of the signals and their errors. There is also a need for more efficient methods for analyzing measured signals as well as more efficient methods for processing measured signals, such as methods of obtaining difference of measured signals, methods of obtaining error-weighted averages, and methods of identifying and removing outliers.
Discussion or citation of a reference herein shall not be construed as an admission that such reference is prior art to the present invention.

Methods for analysis of measurement errors in measured signals


A method and service for handling incoming customer calls. The invention uses an Access Point Model (APM) that includes an inventory of access entry points for voice, text, and/or web communication from a customer; a process network that lists the names and roles of customer contacts within the enterprise; an APM diagram of optimized pathways to be taken by particular incoming customer calls; rules for the customer contacts to follow when handling the incoming customer calls; and a synchronization of the customer calls with back-end processes within the enterprise that are responsive to instructions from the customer contacts.

1. Technical Field
The present invention relates in general to the field of handling customer calls. In particular, the present invention relates to a method and service for directing a customer call to an appropriate attendant by streamlining integration of customer contact mechanisms and clearly defining the roles, responsibilities and relationships between internal organizations of the enterprise to which the customer call is directed.
2. Description of the Related Art
A major source of customer dissatisfaction with an enterprise is excessive phone transfers. That is, when a customer calls the enterprise's central number requesting advice, a specific product or service, or even a telephone number for a particular employee, her level of dissatisfaction increases 10-20% at each phone transfer. Thus, if a calling customer is transferred 3-4 times before reaching the needed person in the enterprise, the relationship between that customer and that needed person has already soured at the start of their telephone conversation.
The problem of knowing how to direct the customer's call is made more difficult if the enterprise has thousands of employees in the customer service/sales area, and the problem is exacerbated further if the employees are spread out across country borders. For example, an enterprise may have a central number in Europe, but the service/product needed may be in a particular country, such as Switzerland.
What is needed therefore is a method and system for efficiently directing a customer's call to an appropriate person who can provide the needed service, either within the enterprise or from a business partner of the enterprise.

Method for increasing ease of doing business through use of an access point model

International Business Machines Corporation


Novel nucleic acid molecules encoding proteins involved in the synthesis and assembly of O-antigen in P. aeruginosa; and novel proteins encoded by the nucleic acid molecules are described. Methods are disclosed for detecting P. aeruginosa in a sample by determining the presence of the proteins or a nucleic acid molecule encoding the proteins in the sample.

The opportunistic pathogen P. aeruginosa remains a problem in the nosicomial infection of immunocompromised individuals. P. aeruginosa infections are particularly a problem in burn patients, people receiving medical implants, and in individuals suffering from cystic fibrosis (Fick, R. B. Jr., 1993). The organism is intrinsically resistant to many antibiotics and capable of forming biofilms which are recalcitrant to treatment. Several virulence factors have been identified in the pathogenesis of P. aeruginosa infections, including proteins such as exotoxin A, proteases, and exopolysaccharides including alginate and lipopolysaccharide (LPS). The LPS of P. aeruginosa is typical of Gram-negative bacteria, composed of lipid A-core oligosaccharide-O antigen repeating units.
P. aeruginosa is capable of coexpressing two distinct forms of LPS, designated A-band and B-band LPS, respectively. A-band LPS is a shorter, common form expressed by the majority of P. aeruginosa serotypes, and has a trisaccharide repeating unit of .alpha.-D-rhamnose linked 1.fwdarw.3, 1.fwdarw.3, 1.fwdarw.2. B-band LPS is the serotype-specific, O-antigen-containing form, and is a heteropolymer composed of di- to pentasaccharide repeats containing a wide variety of acyl sugars, amino sugars, and uronic acids. Both the A- and B-band repeating units are attached to lipid A-core, but there appear to be differences between them regarding point of attachment to and composition of the outer core region (Rivera et al., 1992).
The gene clusters for biosynthesis of core oligosaccharides/O-antigens rfb have been cloned and characterized from several bacterial species, including some from non-enteric genera such as Bordetella (Allen and Maskell, 1996), Haemophilus (Jarosik and Hansen, 1994), Neisseria (Gotschlich, 1994), Vibrio (Stroeher et al., 1992; Amor and Mutharia, 1995; Comstock et al., 1996), and Xanthamonas (Kingsley et al., 1993).
rfb clusters appear to be composed of mosaics of biosynthetic genes acquired horizontally from different sources (Reeves, 1993). Biochemical characterization of O-antigens from various species has shown that conservation of structure does not necessarily mirror conservation at the genetic level. Strains with identical O-antigens can differ significantly in their rfb clusters, while unique O-antigens can be encoded by only slightly variant rfb genes in other strains (Whitfield and Valvano, 1993).
Lightfoot and Lam were the first to report the cloning of genes involved in the expression of A-band (Lightfoot and Lam, 1991) and B-band (Lightfoot and Lam, 1993) LPS of P. aeruginosa. A recombinant cosmid clone pFV3 complemented A-band LPS synthesis in an A-band-deficient mutant, rd7513. pFV3 also mediated A-band LPS synthesis in five of the six P. aeruginosa O serotypes which lack A-band LPS. Another cosmid clone, pFV100, complemented B-band LPS synthesis in mutant ge6, which lacks B-band LPS. Physical mapping of the genes involved in A-band and B-band LPS synthesis indicated that the two gene clusters are physically distinct and are separated by more than 1.9 Mbp on the P. aeruginosa PAO1 genome. A-band LPS genes mapped between 5.75 and 5.89 Mbp (10.5 to 13.3 min), and B-band LPS genes mapped at 1.9 Mbp (near 37 min) on the 5.9-Mbp chromosome.
The structure of the P. aeruginosa O5 O-antigen has been elucidated (Knirel et al., 1988). O5 has a trisaccharide repeating unit of 2-acetamido-3-acetamidino-2,3-dideoxy-D-mannuronic acid, 2,3-diacetamido-D-mannuronic acid, and N-acetyl-D-fucosamine (FIG. 30). Serotypes O2, O16, O18, and O20 of P. aeruginosa have similar O-antigens to serotype O5, varying only in one linkage or one epimer from O5 (Knirel et al., 1988) (FIG. 30). Immunochemical cross reactions have also been demonstrated among LPS of serotypes O2, O5 and O16 by the use of monoclonal antibodies (Lam et al., 1992). The rfbA (herein also referred to as "psbL" and "wbp1") from the O5 gene cluster has been characterized (Dasgupta and Lam, 1995). This O5 O-antigen biosynthetic gene has been shown to hybridize only with chromosomal DNA from the group of five serotypes with similar O-antigens, and not with the remaining fifteen serotypes.
There are currently three pathways proposed for biosynthesis and assembly of LPS, the Rfc-dependent and Rfcindependent pathways. Rfc is the O-antigen polymerase, and appears to be required for assembly of heteropolymeric O-antigens (Makela and Stocker, 1984). In contrast, homopolymeric O-antigens appear to be assembled without an O-antigen polymerase (Whitfield, 1995). Rfc-dependent (or Wzy) LPS synthesis has been shown to involve at least two other gene products which act in concert with Rfc; RfbX (or Wzx), the putative flippase which translocates individual O-antigen units across the cytoplasmic membrane where they are polymerized by Rfc (or Wzy), and Rol (or Wzz), the regulator of O-antigen chain length, which determines the preferred O-antigen chain length characteristic of the individual strain or serotype (Batchelor et al., 1993; Bastin et al., 1993; Morona et al., 1994b; Dodgson et al., 1996).

Proteins involved in the synthesis and assembly of O-antigen in Pseudomonas aeruginosa


The present disclosure provides for semiconductor device structures and methods for forming semiconductor device structures, wherein a field-inducing structure is provided lower than an active portion of a fin along a height dimension of that fin, the height dimension extending in parallel to a normal direction of a semiconductor substrate surface in which the fin is formed. The field-inducing structure hereby implements a permanent field effect below the active portion. The active portion of the fin is to be understood as a portion of the fin covered by a gate dielectric.

1. Field of the Invention
The present disclosure generally relates to a method for forming a semiconductor device structure and to a semiconductor device structure. Particularly, the present disclosure relates to forming bulk fins comprising a field inducing structure and to according semiconductor device structures.
2. Description of the Related Art
Transistors, such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors, represent the core building blocks for a vast majority of semiconductor integrated circuits. Generally, a FET includes source and drain regions between which a current flow is controlled by applying a bias to a gate electrode overlying a channel region between the source and drain regions. Conventional integrated circuits (ICs), such as high-performance microprocessors, for example, may include a great number of FETs, usually on the order of millions. For such ICs, decreasing transistor size and, therefore, increasing integration density has traditionally been a high priority in the semiconductor manufacturing industry. Nevertheless, transistor performance must be maintained with decreasing transistor size.
A FinFET is a type of transistor that addresses reducing the transistor size while maintaining transistor performance. In general, FinFETs represent three-dimensional transistors formed by thin fins extending upwardly from a semiconductor substrate. In a FinFET, the transistor channel is formed along the vertical sidewalls of the fin, which is also frequently referred to as a double gate transistor, or along the vertical sidewall surfaces and the upper horizontal surface of the fin, leading to a so-called tri-gate transistor. Double gate transistors and tri-gate transistors have a wide channel and, hence, high performance, which may be achieved without substantially increasing the area of the substrate surface required by the transistors because a transistor's performance, often measured by its transconductance, is proportional to the width of the transistor channel.
When considering bulk fins having a bulk substrate formed below an active fin, the doping of the bulk substrate needs to be self-aligned with regard to the active fin. In case the doping of the bulk substrate is not exactly adjusted, such as not sufficiently well aligned with regard to the active fin, the so-called sub-threshold leakage is not controllable because a leakage current (drift current at a gate-source bias) present in the sub-threshold region (or weak inversion region) depends crucially on the threshold voltage and further also depends on the dopant concentration within the channel region. Conventionally, the doping of the bulk substrate is realized by implanting dopants or out-diffusing dopants into the bulk substrate. However, those concepts result in a dopant profile that reaches into the active fin, which at current advanced technology nodes induces unacceptable variations from required dopant concentration profiles.
For SOI fins, i.e., fins in an active region that is formed in a semiconductor layer on an isolating material substrate (so-called silicon-on-isolator configuration or SOI configuration), an increased variability of the threshold voltage due to sub-threshold leakage is avoided. The reason is that a bottom oxide or BOX layer is present under the fins such that a possible leakage path into the substrate as present in bulk fins is cut off in SOI configurations. In general, the mainstream technology focuses on bulk FinFET technologies, partially relying on the SOI FinFET configurations exhibiting other intrinsic issues.
According to recent approaches, efforts have been made to increase the gate area. As the minimal gate length is mandatory in logic related device technologies, this proposal turned out to lack compatibility with logic devices and is, therefore, only realized in the context of SRAM devices. One reason is that the minimal gate length is mandatory to keep the gate delay low and to enable fast designs for logic devices.
Currently, FinFETs are considered to provide the appropriate technology for future nodes for overcoming important issues for strongly-scaled semiconductor circuit structures, such as short channel effects, and for realizing high density designs which are required in current complex semiconductor applications. In the framework of FinFET technologies, a strong scaling can be realized by the fins providing a fully depleted body together with a multi-gate controlling of the channel regions.
In general, a reliable and precise control of the threshold voltage, and in particular a reduced variability of the threshold voltage across FinFETs formed on a semiconductor wafer, may only be achieved by at least strongly reducing, if not suppressing, random dopant fluctuations migrating into fins. In bulk configurations, the body below an active fin requires to be controlled such that almost no bulk leakage appears, which results in a degraded performance of FinFETs. Conventionally, the bulk leakage is controlled by appropriately doping the bulk below the fins by high doping processes.
However, the accordingly-used high doping of the bulk below the fin unavoidably introduces a source for random dopant fluctuations in the active fin because the required ideal doping profile can only be approximated by a smooth function with a tail reaching into the active portion of each fin, such that the tail affects the doping within the active portions of the fins. To this end, the threshold voltage of the FinFETs under fabrication is negatively affected, i.e., its variability is degraded. Especially for SRAM devices, a tight variability strongly relates to the performance of SRAM devices and conventional highly integrated SRAM devices are, therefore, expected to fail in complying presently-demanded dense standards with regards to performance, operation, speed and the like.
Therefore, it is desirable to provide methods for at least reducing, if not suppressing, random dopant fluctuations in current advanced FinFET structures. In particular, it is desirable to provide processes which avoid a random distribution of dopants within active fins during the processing of the fins.

Semiconductor device with field-inducing structure


A mechanochemical process for producing fine WC/Co composite powder which is so small in WC grain size and in mean free path, and contains such a uniform distribution of WC and Co that its hard metal is superior in strength, compressive strength, TRS and wear resistance and considerably free of impurities. The method comprises the steps of drying an ammonium metatungstate--Co(NO.sub.3).sub.2 solution in a spray dry manner to give initial powder of porous spheroids or in a common manner to give a cake of initial powder, removing the salts and humidity from the initial powder by a thermal treatment, mixing and milling the desalted initial powder with carbon black, and subjecting the mixed powder to reduction/carburization in a reactor.

1. Field of the Invention
The present invention relates, in general, to a mechanochemical process for producing fine tungsten carbide (WC)/cobalt (Co) composite powders.
2. Description of the Prior Art
With superior mechanical properties including wear resistance, hot strength and elasticitic modulus WC/Co hard metals are the most widely used for tool materials or wear-resistant parts.
Such mechanical properties of the hard metal generally depend on its chemical composition, the grain size distribution of WC, its carbon content and micro structure, and the defects it contains, such as pore, free carbons and impurities. Of them the size of WC grain and the mean free path of WC and Co are the most important variables to determine the properties of the hard metal. For example, as the WC grains in the hard metal become smaller, hardness, compressive strength, transverse rupture strength (TRS) and wear resistances are improved. In addition, the smaller the mean free path of WC and Co is, the better the mechanical properties of the hard metal. Thus, in order to improve the properties of WC/Co hard metal, it is necessary to make the size of WC grain smaller and the mixture of Co and WC more homogeneous.
Conventionally, WC/Co composite powder is prepared by sufficiently mixing tungsten (W) with carbon black in a ball-mill, and performing a heat treatment for the mixture at 1,400.degree.-1,600.degree. C. in a carbon crucible under a hydrogen atmosphere to give WC, and mixing it with Co, serving as a binder with a ball-milling. However, the ball-milling may cause detrimental impurities to be contained in the resulting powder and the strongest pulverization possible may have a limited effect in making the powder fine. Moreover, it is virtually impossible to completely mix W with carbon or WC with Co owing to the difference in their specific gravities. It is also difficult to make fine WC grain with Co by ball milling. Further, since a temperature as high as 1,400.degree. C. is required for the carbonizing reaction, the conventional method has disadvantages in the production costs when considering the facility necessary for such high temperatures and the energy consumed.

Mechanochemical process for producing fine WC/CO composite powder

Korea Institute of Machinery & Materials


A patient interface device selection system that includes a database storing a plurality of sets of data. Each set of data in the plurality of sets of data is associated with a unique patient interface device or a component thereof. A patient data collection system, such as a measuring device, acquires a set of patient data that correspond to at least one characteristic of a patient. A processing system compares the acquired patient data with the plurality of sets of data, and determines the patient interface device or the component thereof that is suitable for use by such a patient based on a result of the comparison.

1. Field of the Invention
The present invention pertains to an automated system and method for selecting a patient interface device or a component of a patient interface device from a plurality of known patient interface devices or components for use by a patient based on at least one characteristic of the patient.
2. Description of the Related Art
There are many instances where it is necessary to communicate a flow of gas with an airway of a patient. For example, it is well known to deliver a supply of breathing gas to an airway of a patient to treat a medical disorder, such as sleep apnea syndrome, and, in particular, obstructive sleep apnea (OSA), congestive heart failure, or to ventilate a patient who has a compromised respiratory ability. It is also well known to monitor the condition of a patient by monitoring the gases inspired and/or expired by the patient. Typically, such monitoring involves evaluating the composition, flow rate and/or pressure of the gases over a period of time.
A patient interface device is used to communicate the flow of gas with the patient's airway. For present purposes, this includes any device that accomplishes this function, such as a nasal mask, nasal/oral mask, full face mask that covers the user's entire face, nasal cannula, etc. A typical patient interface device includes a mask, which provides a flexible seal covering the nose, mouth, or both, and a headgear that secures the mask to the user's head.
A requisite of such patient interface devices is that they provide an effective seal against the user's face to prevent leakage of the gas being supplied or received. It is often the case, in prior patient interface configurations, that a good mask-to-face seal is attained only with some discomfort to the user. This problem is most crucial because such patient interface devices are typically worn for an extended period of time, such as overnight while the patient is asleep. One concern in such a situation is that a user may avoid wearing an uncomfortable mask, defeating the purpose of the prescribed pressure support therapy. Thus, to ensure a comfortable fit providing an adequate seal, it is important that the patient interface device fit a patient's face properly to provide an effective seal and that it is comfortable to the patient.
A variety of different types or styles of patient interface devices are known. For example, the SIMPLICITY™ mask and the COMFORTSELECT™ mask, both of which are manufactured Respironics, Inc. of Murrysville, Pa., represent two different types, styles, or families of nasal masks. In addition, a variety of different sizes of masks, such as "small", "medium" and "large", or "adult" and "child", are available with each different mask style. For example, the SIMPLICITY mask is available in two sizes: medium and small; and the COMFORTSELECT mask is available in three sizes: small, medium, and small/wide. Of course there are other styles of masks having other sizes provided by this company and others.
In some patient interface devices, the mask is formed from two components, a mask frame and a cushion that attaches to the frame. The cushion provides the seal against the patient's skin. In these types of patient interface devices, it is known to provide one commonly sized mask frame that can accommodate different sizes and shapes of cushions, thereby effectively providing differently masks within a common mask family. Furthermore, accessories used with the mask, such as the headgear that attach the mask to the user, may have different styles and sizes.
Therefore, to properly fit a patient interface device on a user, the type or style of patient interface device that is best suited for that use must be determined. Then, the appropriate size for that style of patient interface device that best fits the patient must be determined. In addition, in some situations, the appropriate styles and size of accessories, such as headgear and exhalation port, must be determined.
In attempting to determine the proper style of patient interface device that is best suited to a particular patient, the conventional technique has been to have a patient physically try on different styles of masks and allow the patient to select the one they prefer. It can be expected that a style that the patient prefers, may not provide the optimal physical match between the structure of the patient interface device and the anatomical facial features of the patient. For example, a patient may select a style that is aesthetically pleasing over a patient interface device that is less visually appealing but a better fit. In addition, if the patient interface style does not suit the patient, the mask must be cleaned and disinfected prior to use on the next patient, or it should be disposed. Disposing of unused product is obviously wasteful and not profitable. Cleaning and/or disinfecting product is time consuming and may require special equipment or chemicals to properly clean the product.
It is also common for a caregiver to use their best guess or judgment as to which patient interface style will be best suited to the particular facial features of a patient. Of course, this technique relies heavily on the skill and knowledge of the caregiver in knowing the different styles of patient interface devices and the facial features that each style best matches.
Once a style of mask is selected, traditionally the manufacturer of the various types of respiratory masks supplies a sizing gage, also referred to as a template, associated with each type of mask for use in determining which size of that mask is best suited for each user. The sizing template is typically formed from a rigid material with a plurality of cutouts, each cutout corresponding to a different size of the mask. The user places the template on the part of the body to be measured, such as over the nose and/or mouth, to determine which size mask best fits their anatomical features. The user can test their anatomical features in each different size cutout to determine which cutout, and, hence, which size mask, best matches their features.
This template must be available to the provider each time a patient is sized. A disadvantage to this system is the provider must remember to take a sizing gage with them to a patient's residence, in the case of a homecare application, or to the patient's bedside, in the case of a hospital application. It should be apparent that one disadvantage is that this rigid gage may not always be available.
In another sizing technique, "eyeballing" is used. In this instance, the provider will guess the appropriate size product for the patient. It should be apparent that this method can easily result in the selection of the wrong product size. In another sizing procedure, the mask packaging is opened and the product is tried on the patient. As noted above, if the mask is not the correct size, the mask must be cleaned and disinfected prior to use on the next patient, or the mask may be disposed. Of course, disposing of unused product is obviously wasteful and not profitable, and cleaning and/or disinfecting is time consuming and may require special equipment or chemicals.

Patient interface device or component selecting system and method


The present disclosure provides a door latch assembly including (a) a locking pin movable from an extended position where the locking pin is positioned in an aperture of a driver, to a retracted position where the locking pin is configured to be removed from the aperture of the driver, (b) a solenoid including a solenoid plunger having a first end coupled to the locking pin and a second end coupled to a shaft, (c) a lever arm having a first end engaging the shaft, and (d) a switch including an actuator button in contact with the lever arm, wherein when the solenoid is actuated the solenoid plunger moves to retract the locking pin from the aperture and causes the shaft to displace the lever arm and the actuator button to activate the switch.

Many aircrafts provide a flight deck door that separates the flight deck, or cockpit, from the cabin of the aircraft. During flight, the flight deck door is typically locked for security reasons. However, during flight operations, a member of the flight crew may need to leave the flight deck temporarily, requiring the flight deck door to be opened. The traditional method of locking and unlocking the flight deck door is by activating a solenoid mounted inside of a hollow door post that runs from floor to ceiling. This solenoid is large as it was sized to provide unlocking during a rapid flight deck decompression event, as well as locking/unlocking in more traditional use cases of the flight deck door. As such, the hollow door post amplified a click made by the solenoid upon activation of the solenoid.
Several existing methods have been employed to reduce the noise of the solenoid when locking and unlocking the flight deck door. For example, dampening tape has been applied to the inside of the door post to reduce the reactivity of the door post, and rubber cushions and dampers have been used to slow down the action of moving parts in the flight deck door. While these solutions produced some reductions in the noise of the solenoid when locking and unlocking the flight deck door, none of these solutions addressed the root cause of the problem. Therefore, an aircraft door latch assembly that enables a flight deck door of an aircraft to be locked and unlocked with minimal sound may be desirable.


A method of detecting and eliminating errors in application data stored in a section of a memory of an electronic device. The method includes providing an application program containing an error checking algorithm in the electronic device, starting the application program to access the application data, and executing the error checking algorithm to check for errors in the application data. The application data is erased if the error checking algorithm detects an error in the application data.

1. Field of the Invention
The present invention relates to a method for detecting application data errors, and more specifically, to a method for detecting errors in application data of an electronic device and restoring the section of memory in which the application data is located to an initial status.
2. Description of the Prior Art
Whenever software is used to run electronic devices, it is highly likely that application data accessed by the software will become corrupted at some point. The user of the electronic device may inadvertently corrupt the application data while using the software. In addition, other hardware problems such as a memory access error may also corrupt application data.
Unfortunately, the traditional remedy for fixing the corrupted application data is to return the electronic device to the manufacturer. The manufacturer will then use a tool to reset all application data on the electronic device. However, even if only the application data for one application program was corrupted, the manufacturer must still reset the application data for all application programs. Besides the trouble of sending the electronic device back to the manufacturer and losing the application data, having corrupted data also reduces the user's confidence in the electronic device.

Method for detecting and eliminating errors in application data of an electronic device


A color generation and mixing system includes a color priority level input, an effects input, an incoming color input, and a mix level input. From the level input, a base color is determined which is interpolated with the effects input, resulting in a generated color. The generated color is output and mixed with the mixing color in an interpolator under control of the mixing levels.

1. Field of the Invention
The present invention relates to computer-based graphics systems and, in particular, discloses a colour generation and mixing system capable of operation at video data rates at real-time.
2. Description of the Related Art
U.S. patent Ser. No. 08/053,373, filed Apr. 28, 1993 entitled "A Real-Time Object Based Graphics System", claiming priority from Australian Patent Application No. PL 2147, filed Apr. 29, 1992. Lodged concurrently herewith and the disclosure of which is hereby incorporated by reference, discloses a system which provides for the rendering of object-based graphic images in real-time at video data rates.
An example of part of such a system is shown in FIG. 1 where part of a real-time object (RTO) based graphics systems 1 is shown which includes an RTO processor 2 and a colour look-up table (CLUT) 3. The RTO processor 2 and the CLUT 3 connect to various other components (not illustrated) of the system 1 which are seen in the above crossreferenced patent application. The RTO processor 2 is configured to be input with data describing object outlines, and is able to process the outlines of multiple objects for rendering in scan line and pixel dimensions. However, the RTO processor 2 does not attempt to generate colours, which are predefined by the object outlines. In this manner, the RTO processor 2 outputs colour levels of objects, which are synchronised with line and pixel dimensions, that can be externally mapped to any desired colour using the CLUT 3. As seen in FIG. 1, the RTO processor 2 outputs 8 bits of level and effects data which can be termed as level output data 4.
The 8-bit output 4 from the RTO processor 2 comprises 6 bits of LEVEL data and 2 bits of EFFECTS data and can be used to determine the colour at a current position provided by line and pixel dimensions which are synchronised with a display (not illustrated) such as a VDU or a printer. The output data 4 is input to the CLUT 3 wherein the level output data 4 acts as an address for the CLUT 3 which outputs 24-bit RGB data 5 to the display. It will be apparent to those skilled in the art that the CLUT 3 need not contain additive RGB data which is generally used in video devices but can store CMYK (cyan, magenta, yellow and black) data which is a subtractive colour space used in printers such as the CANON CLC 500 Colour Laser Copier. Alternatively, composite video comprising luminance (Y) and chrominance values (Cr and Cb) can also be used.
In the configuration of FIG. 1, the CLUT 3 is arranged to have four sets of 64 entries in which the two effects bits select the appropriate set, and the level bits select the appropriate entry in each set. For example, the first set of 64 entries can be standard colours and the remaining sets can be variations of these colours that can be used to illustrate shadow layers, or other visual effects.
FIGS. 2, 3 and 4 show three examples of an image output that can be created using the RTC system 1. The level data output 4 from the RTO processor 2 follows a simple rule in which:
EFFECTS equals the highest active priority level's effects bits (zero if no levels are active); and PA1 LEVEL equals the highest opaque active priority level (zero if no opaque levels are active). PA1 where no LEVELS are active, the output is LEVEL 0, EFFECTS 0; PA1 within the part of rectangle A that does not intersect with rectangle B, the highest active LEVEL is 10. The effects for LEVEL 10 is 0. The highest active opaque is also LEVEL 10 (as EFFECTS 0 is opaque). Therefore, the output for this section is LEVEL 10, EFFECTS 0; PA1 within the part of the rectangle B that does not intersect with rectangle A, the highest active LEVEL is 20. The effects for LEVEL 20 is 2. There are no active opaque LEVELS (as level 20 has EFFECTS 2 which is fall-through), so the output for this section if LEVEL 0, EFFECTS 2; PA1 Within the intersection of rectangles A and B, the highest active LEVEL is 20.
Thus, the priority level determines what will be shown for any given position. When a number of objects are all active at the same pixel location, the highest priority opaque object is displayed using the effects mode of the highest active priority, whether it is opaque or not.
Firstly, in considering the example of FIG. 2, rectangle A has a LEVEL of 10 and an EFFECTS of 0. Rectangle B has LEVEL 20 and EFFECTS 2. When the RTO processor 2 processes the object data to render the rectangles A and B, it implements an odd/even fill rule to fill the objects. That is, when it encounters an object edge at LEVEL N, the RTO processor 2 activates the fill for that level, and when it encounters the next edge, it deactivates the fill for that level. The output from the RTO processor 2 therefore depends on the highest active level's effects bits, and the highest active opaque level's level.
The RTO processor 2 is configured to implement transparency and when transparency is disabled, the effects modes 0, 1, 2 and 3 are all opaque. Accordingly, the highest active priority level will always be the highest active opaque level as all effects are opaque.
FIG. 3 illustrates the displayed image when transparency is disabled using inputs identical to those of FIG. 2. The net effect is that the objects drawn at higher levels (e.g. rectangle B) completely obscure objects drawn at lower levels (e.g. rectangle A).
When transparency is enabled in the RTTO processor 2, effects modes 0 and 1 are opaque, and effects modes 2 and 3 are fall-through. The output from the RTO processor 2 can then be seen in FIG. 4 and explained as follows:
The EFFECTS for level 20 is 2. The highest active opaque LEVEL is 10 (as LEVEL 20's EFFECTS 2 is fall-through, but LEVEL 10's EFFECTS 0 is opaque).
Therefore the output for this section is LEVEL 10, EFFECTS 2.
The net effect of the above, is that the objects drawn in fall-through effects modes cause a fall-through to the first opaque level below them. The output retains the effects mode of the fall-through level. Rectangle B is effectively a transparent rectangle, and the effects bits for it will be active, while it is the highest active level. At the intersection point, instead a level 10 effects 0, the effect is level 10 effects 2, which causes a look-up to a different colour, for example a darker version of level 10 effects 0, which would give a shadow effect.
The RTO system 1, FIG. 1, requires that the CLUT 3 is updated regularly so that the correct colour is stored in each entry. This is performed by connecting the CLUT 3 to a host processor which can alter the contents of the CLUT 3, for example on an image basis allowing any 256 colours in the palette of the CLUT 3.
By altering the contents of the CLUT 3 unlimited complexity for colour and effects can be provided merely by updating each entry using software. However, limits of update and calculation time in a real-time environment limit the visual effects that the system I is capable of producing.
Accordingly, it is an object of the present invention to substantially overcome, or ameliorate, the problems of updating the colour entries in the CLUT 3.

Canon Information Systems Research Australia Pty Limited


A device for releasably locking a parked vehicle at a loading dock during loading and unloading thereof. The device is provided with a carriage mounted for vertical adjustment relative to the front wall of the dock and adapted to be yieldably engaged by a depending safety bar of the parked vehicle. A hook-like member is mounted on the carriage for independent rectilinear movement between an operative mode wherein the vehicle safety bar is lockingly engaged thereby and an inoperative safety bar-release mode. A power-actuated unit is mounted on the carriage and is connected by a linkage assembly to the hook-like member and effects movement thereof between the operative and inoperative modes. The linkage assembly includes a pair of pivotally connected links one of which has an end portion pivotally connected to the hook-like member and the other has an end portion pivotally connected to a lower portion of the carriage. One of the links is pivotally connected to a movable portion of the unit and when the latter is moving in one relative direction causes the linkage assembly to move the hook-like member to the operative mode. When the unit portion is moved in a second relative direction, the linkage assembly moves the hook-like member to the inoperative mode. A control assembly is operatively connected to the power-actuated unit and is adapted to selectively actuate and deactuate the power-actuated unit.

1. Field of the Invention
The invention hereinafter disclosed relates to a safety device utilized at a loading dock to prevent accidental or unauthorized moving of a parked vehicle away from the dock while the vehicle is being loaded or unloaded.
2. Description of Related Art
Various locking devices, such as disclosed in Hahn, et al. U.S. Pat. No. 4,443,150, have heretofore been utilized to retain a parked vehicle against a loading dock while the vehicle is being loaded or unloaded. While the locking device disclosed in the aforenoted patent is effective in restraining such parked vehicle, it nevertheless is possessed of certain shortcomings such as: a) it relies upon a manual upward pull to effect a locking engagement between the device and a safety bar, commonly referred to as an ICC bar which is disposed at the rear end of the vehicle and depends from the underside thereof; b) the adjustment of the device to an operative locking mode and an inoperative release mode requires the manual manipulation of a tool to effect engagement with certain portions of the device which under certain circumstances may be a frustrating, awkward or time-consuming operation; furthermore, the tool may become lost or misplaced; c) the means for locking the device in an operative mode may be adversely affected by snow, ice and debris; d) signal lights indicating whether the hook member is in an operative or inoperative mode must be manually actuated and e) there is no audible signal if the ICC bar cannot be engaged by the hook member.
Other locking devices besides that disclosed in U.S. Pat. No. 4,443,150, may be susceptible to being damaged by the vehicle when backing into a parked position adjacent the loading dock or they may be of complex and costly design and highly susceptible to malfunction.


A fluid testing apparatus and associated method include a testing chamber, a filter storage device and a filter transfer mechanism. The testing chamber has a sample volume, a filtrate collection reservoir, an opening between the sample volume and the filtrate collection reservoir, and at least one port into the sample volume. The filter transfer mechanism positions at least one filter in the opening. The opening is closed and a sample fluid, introduced into the port, at least partially fills the sample volume. The sample volume is pressurized and a filtrate of the sample fluid flows from the sample volume, through the filter into the filtrate collection reservoir. The volume of filtrate passing into the filtrate collection reservoir is measured and the sample fluid from sample volume is discharged. The filtrate is discharged from the filtrate collection reservoir, and the filter transfer mechanism removes the filter.

The present disclosure, according to specific example embodiments, generally relates to improved methods for characterizing the performance of fluids. In particular, the present disclosure relates to a high temperature, high-pressure fluid filtration test apparatus, and associated methods of use.
In drilling wells for production of hydrocarbons from underground formations, drilling mud typically cycles through a well bore during drilling. In addition to driving a drill motor and cleaning a drilling bit, the drilling mud also provides a column of fluid that exerts pressure on the formation pierced by the well bore, which prevents or reduces fluid from a reservoir or formation from entering the well bore. In addition, drilling mud may infiltrate the formation in the region surrounding the well bore (the near well bore region).
A problem often encountered during subterranean treatments is the undesired loss or leak off of fluid into the formation. This undesired loss or leak off is commonly referred to as "fluid loss." Such treatments include, but are not limited to, drilling operations, cleanup operations, workover operations, completion operations, stimulation treatments (e.g., fracturing, acidizing), and sand control treatments (e.g., gravel packing). In fracturing treatments, fluid loss into the formation may result in a reduction in fluid efficiency, such that fracturing fluid cannot propagate the fracture as desired.
Fluid loss into the formation may result from a number of downhole conditions, such as high-formation permeability, overbalance pressures, perforated or open-hole intervals in the well bore, and large differential pressures associated with differential segregation in wells completed in a multilayer reservoir. In some instances, the fluid loss may be into a low-pressure portion of the formation due to overbalance pressures, for example, where a well is completed in a multilayer reservoir.
Traditional methods of characterizing the performance of fluids have involved a high pressure, high temperature filtration test. High Pressure, High Temperature (HPHT) filtration tests are used to measure filtration behavior of water or oil based drilling fluids at elevated temperatures, usually according to the specifications of the American Petroleum Institute (API). These tests are typically time intensive due to their setup requirements, testing protocol, and clean-up operations. As drilling rig time, space on offshore rigs, and personnel become more expensive, there exists a need for a method of testing fluids that requires less manpower and time.

Real-time filtration apparatus and associated methods


A videocassette package is disclosed which may be injection molded from plastic. The package includes sloped and vertical walls to assist in guiding the videocassette to be inserted into the proper position.

Videocassette packages are typically made from plastic or thermal formed material. The package usually contains an inner chamber for holding the videocassette, and outer label for identifying the videotape contained therein. The outer label is usually applied by first attaching a graphic wrap material to the package, and then placing a sheet of graphic material between the package and the graphic wrap.
One problem associated with prior art videocassette packages is that they are difficult to automatically load. Specifically, as a videocassette is placed into the videocassette package by an automatic loading means, it must be in exactly the right position to fall into the chamber created on the inside thereof for holding the videocassette. If the videocassette is loaded slightly off-center, it will not enter the package. Rather, the videocassette gets stuck hanging on the package, partially inserted. On an automatic assembly line, this becomes a significant problem and results in lost time and money.
An additional problem is that numerous manufacturing steps are required to form the package. For example, a thermal formed package may require the addition of numerous layers in order to form the outside of the videocassette package.
In view of the foregoing, there exists a need in the art for an improved videocassette package which is both easy to manufacture, and which may be loaded and unloaded efficiently and easily. More specifically, there exists a need in the art which will allow for the automatic loading and unloading of videocassette packages with videocassettes. Additionally, it is desirable to form the packages as quickly and inexpensively as possible.


An encoder includes a positional information generation unit configured to generate first positional information based on a detected signal which is output by a sensor unit, and an IIR filter unit configured to output second positional information obtained by performing filtering on the first positional information. In the IIR filter unit, a counter unit stores a predetermined high-order digit of the first positional information as a count value, and an input unit subtracts the count value from the first positional information to thereby generate input information. A computation unit generates an internal computation result based on delay information which is an internal computation result stored in a delay information storage unit, input information, and a predetermined filter coefficient, and generates output information on which filtering is performed. An output unit adds the count value and the output information to thereby generate second positional information. A changing unit changes a value of the delay information based on a unit of change of the input information when the value of the delay information falls outside of a predetermined range, and changes the count value.

There is known an encoder that includes a filter unit such as a low pass filter performing filtering on a detected signal (for example, an incremental signal), which is detected by a sensor unit, in order to reduce influence due to disturbance (noise) (for example, see Patent Document 1). The encoder detects positional information of a driven body based on the detected signal having been subjected to filtering by the filter unit.