In order to provide an actuator having great driving force and high impact resistance, an actuator of the present invention has a driving shaft 5 that can be vibrated in the shaft direction by a piezoelectric device 4 provided at its one end and a moving member 6 that is friction-engaged with the driving shaft 5 and moves on the driving shaft 5 due to the vibration of the driving shaft 5. The driving shaft 5 has two parallel shaft sliding faces 5a on its surface. The moving member 6 has two moving member sliding faces 7e, 8e that are in slide-contact with the shaft sliding faces 5a. The moving member 6 is friction-engaged with the driving shaft 5 such that the moving member sliding faces 7e, 8e clamp the shaft sliding faces 5a.

1. Field of the Invention
The present invention relates to an improved actuator. More particularly, the present invention relates to an actuator using a piezoelectric device. Further more particularly, the present invention relates to an actuator whose driving force and impact resistance are enhanced.
2. Description of the Related Art
Japanese Unexamined Patent Application No. 2002-95274 and Japanese Unexamined Patent Application No. 2004-15864 disclose an actuator that causes a moving member to be friction-engaged with a driving shaft that vibrates by a piezoelectric device and moves the moving member along the driving shaft by controlling the vibration waveform of the driving shaft. In the actuator of this type, the moving member is friction-engaged with the driving shaft such that a main body of the moving member engaged with the driving shaft and a spring clamp the driving shaft (via a holding member). Further, Japanese Unexamined Patent Application No. 10-80165 discloses an actuator that causes a driving shaft to be friction-engaged with a rotatable disk in the tangential direction in the vicinity of the disk, thereby being capable of controlling the rotation angle.
The conventional actuator described above gives acceleration, which exceeds the friction force by which the moving member is engaged with, to the driving shaft by the piezoelectric device for causing the moving member to slide relative to the driving shaft, wherein the driving force of the actuator is generated when the moving member is friction-engaged with the driving shaft and moved together therewith. Therefore, it is preferable that the spring is strengthened to increase the normal load to the friction face and the friction force by which the moving member is engaged with the driving shaft is increased. However, in the conventional actuator, the holding member pressed by the spring is in contact with the round surface of the driving shaft on the line in the shaft direction. Therefore, local concentration of the normal load may be generated due to a trivial factor such as a torsion between the driving shaft and the moving member or adherence of dust on the sliding face, so that there may be a case where great friction force is generated. The normal load is required to be set small to such a degree that the moving member can be slidably moved even in this case, thereby entailing a problem that the driving force cannot be set great.
Further, in a device having the actuator installed therein as disclosed in Japanese Unexamined Patent Application No. 2002-95274 and Japanese Unexamined Patent Application No. 2004-15864, acceleration of several thousand G is exerted on the moving member when it receives an impact due to, for example, a fall. The moving member may be fallen off over the spring or the spring may be damaged due to excessive force exerted thereon.


An apparatus and method for improving descriptor load time in a microprocessor are provided. The method and apparatus provide an instruction sequence which loads a selector, forwards a table index (TI) bit retrieved from the selector for use by the next instruction which loads the descriptor. Forwarding of the table index bit to a register file selects between a global descriptor table and a local descriptor table for loading the descriptor, without intervening instructions or clock cycles. The forwarded table index selectively addresses either the global descriptor table or the local descriptor table only when a descriptor load instruction is immediately preceded by a selector load instruction.

1. Field of the Invention
This invention relates in general to the field of memory segmentation, and more particularly to an improved method and apparatus for loading a segment register within a processing system.
2. Description of the Related Art
Memory management is a hardware mechanism which lets operating systems create simplified environments for running programs. For example, when several programs are running at the same time, they must each be given an independent address space. If they all had to share the same address space, each would have to perform difficult and time consuming checks to avoid interfering with the others.
Memory management consists of two methodologies called segmentation and paging. Segmentation is used to give each program several independent, protected address spaces. Paging is used to support an environment where large address spaces are simulated using a small amount of RAM and some disk storage. When several programs are running at the same time, either mechanism can be used to protect programs against interference from other programs. The following discussion will focus on segmentation.
Segmentation organizes memory into a collection of variable-size units, called segments. Within x86 processors, a two-part address is utilized: a segment part and an offset part. For a general background on segmentation in x86 processors, please see U.S. Pat. No. 4,442,484 issued to Childs, Jr. et al. The first part of the address, the segment part, defines a base address for a segment, and the offset defines a particular memory location which is offset from the base address.
To access data within a given memory segment, a program must first load a segment register with a special value that identifies that segment. This special value is called a selector. Programs then reference memory by specifying, either implicitly, explicitly, or by default, the segment register containing the selector for the segment part of the address. When a selector is referenced, it is used to determine the base address for the segment. The base address is then added to the offset to form the linear address for the memory location to be accessed.
More specifically, the selector is used to index into one of a number of descriptor tables which contain, descriptors. Descriptors define a base address for each segment, the largest offset that can be used with the segment (the limit), and various attributes of the segment such as whether the segment can be read from, written to, or executed as a program, the privilege level of the segment, etc. In an x86 environment, two descriptor tables are provided: 1) the Global Descriptor Table (GDT); and 2) the Local Descriptor Table (LDT). A third descriptor table (IDT) is provided for interrupt routines, but will be ignored for purposes of the present discussion. Each of the descriptor tables can contain up to 8,192 descriptors corresponding to 8,192 possible segments within memory. The descriptor tables are stored in memory.
The selector is a 16-bit value. Bits 3-15 of the selector, termed the descriptor index, define one of the 8,192 descriptors within one of the two descriptor tables. Bit 2, termed the table index (TI), selects which of the two tables, GDT or LDT, contains the descriptor of interest. Bits 0-1 contain the requested privilege level of the access.
As mentioned above, to access a particular memory segment, a program must first load a selector which identifies the segment into a segment register. Commensurate with the loading of the selector, the descriptor which defines the segment is loaded into a hidden or shadow register termed the descriptor register, which is associated with the segment register. Future references to the segment can then utilize the base address, limit, and attributes of the segment by retrieving the descriptor directly from the segment register, without requiring access to one of the two descriptor tables in memory.
When loading a segment register with a selector, and its associated descriptor, the selector is first loaded into a temporary register. The content of the TI bit is then extracted to determine which of the two descriptor tables, GDT or LDT, contains the descriptor to be loaded. Once the value of the TI bit is determined, the appropriate descriptor table is referenced to retrieve the descriptor for the memory segment. The descriptor is then stored in the shadow descriptor register, and the selector is written from the temporary register into the segment register. Thus, each time a segment register is loaded, at least three steps are required: 1) load the selector into a temporary register; 2) extract the TI bit to determine whether the descriptor is in the GDT or LDT; and 3) load the descriptor/selector into the segment register.
Hardware implementations of memory segmentation utilize a limited number of segment registers for storing selectors/descriptors. The segment registers allow programs to calculate memory locations for different segments, without having to reload the segment registers from memory. However, with over 16,000 possible memory segments, it is frequently necessary to overwrite previously used selector/descriptor information in the segment registers with new selector/descriptor information. And, each time access to a new memory segment is desired, program processing is delayed until the new selector/descriptor information can be loaded from memory into a segment register.
In the prior art, loading of a selector/descriptor into a segment register required at least three steps before access to the memory segment could be performed. As mentioned above, one of these steps includes determining which of the two descriptor tables contains the descriptor of interest, i.e., extracting the TI bit from the selector. One method which has been used performs a bit test on the selector to determine whether the TI bit selects the GDT or the LDT. A branch to one of two descriptor routines is then performed based on the outcome of the bit test. But, performing a bit test, and then a branch creates costly processing delays during program execution.
A second method used to determine whether the LDT or GDT is referenced by a selector is to extract the TI bit during the selector load, and feed the extracted bit back into the address operand of the following instruction. However, prior to multiplexing ("muxing") in the TI bit, the following instruction needs to be decoded to determine whether or not the TI bit should in fact be multiplexed into the register address. If a descriptor load instruction follows a selector load instruction, then mux it in. If a descriptor load instruction does not follow extracting the TI bit, then do not mux it in. However, the instruction decode to determine whether the following instruction was a descriptor load also required valuable processing time.
What is needed is a an apparatus and method which minimizes delays associated with the loading of a selector/descriptor into a segment register. More specifically, what is needed is a mechanism which eliminates the processing delay associated with determining which descriptor table contains the descriptor to be loaded into the segment register.

Apparatus and method for fast forwarding of table index (TI) bit for descriptor table selection


A microwave and millimeter wave circuit includes an amplifier having an amplification center frequency, input and output terminals, and a source-grounded transistor. First and second transmission lines are connected between the input terminal and a gate of the transistor, and are connected in series to each other. Third and fourth transmission lines are connected between a drain of the transistor and the output terminal, and are connected in series to each other. A first band elimination filter is connected to the input terminal, and has a first stopping frequency, and a second band elmination filter is connected to the output terminal, and has a second stopping frequency. A third band elimination filter is connected to a connecting point between the first and second transmission lines and has a third stopping frequency, and a fourth band elimination filter is connected to a connecting point between the third and fourth transmission lines and has a fourth stopping frequency. Each of the first to fourth stopping frequencies is lower than the amplification center frequency, and each of the third and fourth stopping frequencies is higher than the first and second stopping frequencies.

1. Field of the Invention
The present invention relates to a microwave and millimeter wave circuit including an amplifier and band elimination filters, and in particular, to a microwave and millimeter wave circuit for use in integrated circuits (referred to as ICs hereinafter) for microwaves, quasi-millimeter waves and millimeter waves at frequencies of about 800 MHz to about 300 GHz.
2. Description of the Prior Art
FIG. 13 is a circuit diagram of a microwave and millimeter wave amplifier circuit of a first prior art.
Referring to FIG. 13, in an amplifier circuit, a gate and a drain of a field effect transistor (referred to as an FET hereinafter) Q having a source grounded (referred to as a source-grounded FET hereinafter) are inserted between an input terminal 1 and an output terminal 2, and between two microstrip lines T11 and T12, each of which is a transmission line. In this amplifier circuit, a band elimination filter (referred to as a BEF hereinafter) FE comprising a series circuit of a microstrip line T13 of a transmission line functioning as an inductor, and a capacitor C11, and having a stopping frequency f.sub.c lower than a desired amplification center frequency f.sub.0 of the amplifier circuit is connected to the drain of the FET Q. This amplifier circuit has a gain frequency characteristic as shown by a gain G10 in FIG. 17. In this case, the amplifier circuit has had such a problem in that there is unnecessary gain, as shown by G11, at lower frequencies near the stopping frequency f.sub.c.
In order to solve this problem, as shown in FIG. 14 showing a second prior art, a directional coupler comprising two 1/4 wavelength microstrip lines T21 and T22 which are opposed to each other and electromagnetically coupled with each other is provided instead of the microstrip line T12, by which the improper gain G11 is eliminated as shown by a gain G12 of FIG. 17.
FIG. 15 is a circuit diagram of a microwave and millimeter wave amplifier circuit of a third prior art as disclosed in the Japanese Patent Laid-Open Publication No. 8-274552.
Referring to FIG. 15, reference numeral 1 denotes an input terminal, 2 denotes an output terminal, 3 and 4 denote bias applying terminals, reference character Q denotes an FET, T11 to T16 denote microstrip lines, which are transmission lines functioning as inductors, C11 and C12 denote capacitors, Rg denotes a resistor, and Ls1 and Ls2 denote high-frequency stopping inductors. A frequency characteristic of the microwave and millimeter wave amplifier circuit constructed as described above has an unnecessary gain arising at about 2 GHz or lower, as shown in FIG. 18, in a manner similar to that of the first prior art. Also, the stabilizing factor K of the circuit is lower than at frequencies of about 13 GHz to 27 GHz, so that the operation of the circuit is unstable.
Further, FIG. 16 is a circuit diagram of a microwave and millimeter wave amplifier circuit of a fourth prior art as disclosed in the U.S. Pat. No. 5,412,347.
Referring to FIG. 16, reference numeral 1 denotes an input terminal, 2 denotes an output terminal, 3 and 4 denote bias applying terminals, reference character Q denotes an FET, T11 to T17 denote microstrip lines, which are transmission lines functioning as inductors, C11 to C15 denote capacitors, and R11 denotes a resistor.
The microwave and millimeter wave amplifier circuit of the second prior art indeed has solved the problem of the first prior art. However, since the microwave and millimeter wave amplifier circuit comprises the directional coupler, the 1/4 wavelength line at 60 GHz, for example, has a length beyond 400 .mu.m. Therefore, the directional coupler is relatively large, and this results in the problem that the circuit including the amplifier circuit can not be miniaturized.
In order to solve the problem of the third prior art, the stabilizing factor K can be made to be equal to or more than one, for example, by adding a microstrip line functioning as a relatively long inductor to the source of the FET Q as shown in FIG. 19. However, there still exists an unnecessary gain. Inserting the inductor, which is a feedback circuit, causes the amplification gain of the amplifier circuit to lower from about 18 dB to about 6 dB with a decrement as much as about 12 dB. Besides, the fourth prior art also has a problem similar to that of the third prior art, so that a larger gain can not be obtained in wider band.

Microwave and millimeter wave circuit including amplifier and band elimination filters


The specification discloses a process for the manufacture of carbon disulfide from sulfur dioxide and carbon monoxide comprising two catalytic reactions. In the first reaction, sulfur dioxide and carbon monoxide are converted to carbonyl sulfide and carbon dioxide. In the second reaction, carbonyl sulfide is disproportionated to carbon disulfide and carbon dioxide. The second reaction is conducted in the presence of a solvent, which continuously removes the carbon disulfide product so as to drive the reaction to completion.

Carbon disulfide is a major industrial chemical, which has a long history of use in the chemical process industries. At one time large quantities of the chemical were used to manufacture viscose rayon, cellophane, and carbon tetrachloride. While these applications have declined, new markets, especially its use as a solvent, show considerable promise.
In the early years of its manufacture, carbon disulfide was produced from charcoal and sulfur at high temperatures in either an electric furnace or a retort. The method was both hazardous and environmentally unsound, but at the time no alternatives were available.
Beginning in the 1960's, a petrochemical process was introduced to manufacture carbon disulfide from natural gas (methane) and sulfur. A great improvement over the old process, this petrochemical technology soon gained dominance. Nevertheless, the petrochemical process was saddled with a major disadvantage: the need to recover sulfur from substantial quantities of byproduct hydrogen sulfide in a Claus unit.
Newer proposals continue to appear for the manufacture of carbon disulfide. One of the most interesting processes was disclosed in U.S. Pat. No. 4,122,156. This process makes carbon disulfide from boiler flue gas by catalytically reducing sulfur dioxide with carbon monoxide to carbonyl sulfide and then converting the carbonyl sulfide to carbon disulfide over an alumina catalyst.
Although this proposal to reduce sulfur dioxide to carbonyl sulfide has considerable merit, the conversion of carbonyl sulfide to carbon disulfide presents certain difficulties. The reaction of carbonyl sulfide to carbon disulfide and carbon dioxide is reversible and does not go to completion under normal conditions. Thus, expensive and inefficient procedures must be employed to get around this limitation.
An object of the present invention is to reduce or eliminate the disadvantages of the prior art in a way which meets the most demanding expectations for safety, environmental responsibility, and efficiency.
These and other objects, features and advantages of the invention will be apparent from the following description and the accompanying drawing.


A fixation device includes: a heating member; a fixation belt configured to be heated by the heating member and formed like an endless belt; a first fixation member configured to abut on an inner circumferential surface of the fixation belt; a second fixation member located upstream of the first fixation member in a paper conveyance direction and configured to abut on the inner circumferential surface of the fixation belt; a press member located between the first fixation member and the second fixation member and configured to abut on the fixation belt; a pressurization member configured to abut on an outer circumferential surface of the fixation belt, and press at least against the first fixation member and the press member via the fixation belt; a support frame configured to support the first fixation member; and a holding plate configured to support the press member.

1. Field of the Invention
The present disclosure relates to a fixation device used in an image formation apparatus such as a printer, a copier, a fax machine, a multifunction printer and the like, and an image formation apparatus including the fixation device.
2. Description of Related Art
In a conventional electrographic image formation apparatus, a charge roller uniformly charges a surface of a photosensitive drum, and thereafter an exposure unit such as a LED head exposes the surface of the photosensitive drum to light to form an electrostatic latent image according to image information. Toner in the form of a thin layer formed on a development roller is electrostatically attached to the electrostatic latent image to form a toner image. Then, a transfer roller transfers the toner image to a sheet on a conveyance belt for conveying sheets fed from a sheet feeder. After the toner image is transferred, a fixation device fixes the toner image to form an image on the sheet.
A fixation device disclosed in Japanese Patent Application Publication No. 2013-24895 is a fixation device with a belt heating scheme.

Fixation device and image formation apparatus


An imaging system that forms an image on a receiving medium including a fluid ejector that ejects fluid onto the receiving medium and a controller that controls the fluid ejector to eject the fluid to include a non-white and non-clear fluid or one of at least white and clear W fluid on each pixel on the receiving medium. A substantially single layer of fluid is ejected onto the receiving medium. A method for forming an image on a receiving medium includes ejecting a fluid onto the receiving medium, and controlling the ejection of the fluid to include a non-white and non-clear fluid or one of at least white and clear fluid for each pixel on the receiving medium.

When printing a image, solid or phase change inks that are solid at ambient temperatures and liquid at elevated operating temperatures are currently utilized in conventional printers. The printers eject fluid, e.g., liquid phase ink droplets from the print head, at an elevated operating temperature. The droplets solidify quickly upon contact with the surface of a receiving medium to form a predetermined pattern or image.
When forming an image on a medium, e.g., printing on a piece of paper by forming an image on a drum and transferring the image to paper. Printing is typically performed using Cyan, Magenta, Yellow, and Black ink (CMYK). where any combination of these four printer primary ink colors may be marked at any pixel location. The number of ink colors a printer uses is also referred to as the printer's number of color channels.
The quality of the image is generally limited by the drop size that the printer can produce. The drop size of the fluid and dot gain is usually a limiting factor determining the maximum practical addressability of a printer. With conventional CMYK printing systems, dots of secondary colors are usually printed with twice the ink of primary colors. Thus, because more ink is printed with secondary colors, more dot gain may occur when printing a secondary color than when printing a primary color. Furthermore, dot gain from the printed secondary colors spilling into adjacent unoccupied paper white areas may cause problems with the printed image.
One method of reducing dot gain ejects clear or white ink on unoccupied white areas next to printed non-white pixels. However, this method does not address problems associated with each marked pixel receiving a different amount of fluid which contributes to non-uniform dot gain. If the dot gain is significantly reduced, then much higher resolutions of an image may be possible in the final printed product.

Systems and methods that improve fluid color output by using clear or white fluid


A system and method for modifying the supply of fuel to injectors to attenuate combustion oscillations in a gas turbine engine. The gas turbine engine may comprise a combustor, a plurality of injectors and a manifold. The plurality of injectors may be operable to provide fuel to the combustor. The manifold may be configured to supply fuel to all of the plurality of injectors or to only a portion of the plurality of injectors in reaction to a determination of an existence of combustion oscillations.

Producers of gas turbine engines have made great strides in reducing regulated emissions such as NOx. However, these strides have led to various instabilities in combustion, such as combustor thermo-acoustic oscillations. This problem may be brought about by the coupling of the heat release and pressure waves, which produce a resonance with a characteristic frequency usually corresponding to one or more natural frequencies of the combustion chamber. This has been historically described by the well-known Rayleigh Mechanism. Such oscillations in the combustor may result in mechanical and thermal fatigue to combustor hardware which may lead to other operational problems that may have adverse affects on the engine.
Several attempts have been made to eliminate, diminish or prevent thermo-acoustic oscillations. One such attempt to attenuating oscillations was to decouple the heat release form the pressure wave by moving the fuel introduction point in the injector so that the residence time to the flame was different than that required to sustain resonant oscillations. This may be accomplished by moving the fuel spokes along the length of the injector main fuel and air flow path.
Another attempt to attenuate oscillations was to introduce airflow in a row of holes around the circumference of the injector barrel. The axial location of the row of holes along the barrel was determined so as to dilute the fuel to air ratio in an attempt to provide a non-sinusoidal variation in the energy input to the flame. However, problems with such attempts has been in the limited number of frequencies of oscillations that could be attenuated. Unfortunately, some engines exhibit more than one frequency of oscillation when they are at different power settings.
The system and method of the present disclosure is set forth to overcome at least one of the problems described above.

System and method for attenuating combustion oscillations in a gas turbine engine


Method and apparatus are disclosed for use in cementing a tubular member which is run into a borehole using a drill string. A landing collar is attached to the tubular member near the bottom of the tubular member, and the landing collar has an opening at least five inches in diameter. A liner wiper assembly is releasably suspended from the drill string. The liner wiper assembly comprises a lower liner wiper plug comprising float valves and an upper liner wiper plug. With the method and apparatus of the present invention, plugging problems are minimized.

1. Field of the Invention
The present invention relates to apparatus for use in cementing any tubular member that is run or landed with a string of drill pipe.
2. Description of the Prior Art
Prior art liner cementing equipment includes a flapper or a float valve at the bottom of the liner. The flapper is conventionally held open by a breakable plastic tab which is actuated (i.e., broken) by a drop ball when the cementing operation is to begin. Since the drop ball which is used to activate the float valve must be small enough to pass through the drill string, the maximum float valve opening size for a 13xe2x85x9cxe2x80x3 liner may be on the order of 2 to 3xe2x80x3 in diameter. As the liner is lowered into the well bore, the fluid in front of the liner must be displaced to flow through the bottom opening in the float valve as well as around the outside annulus defined by the well bore and the liner.
Two problems exist with respect to conventional cementing apparatus. First, the flow resistance of two above-identified flow paths may be high and thus cause a pressure buildup below the liner. This pressure buildup can: (a) cause damage to the formation; (b) result in loss of expensive drilling fluid; and (c) result in the liner sticking against the side of the borehole, which means that the liner does not go to the bottom of the hole. Second, the small opening through the float valve may, and often does, become plugged with cuttings and contaminants due to its small size and the highly contaminated environment in which it is used.
U.S. Pat. No. 5,960,881, which is incorporated herein by reference, discloses a downhole surge pressure reduction system to reduce the pressure buildup while running in liners. The system is typically located immediately above the top of the liner. Nonetheless, any plugging of the float valve at the lower end of the liner can, and very well may, render the surge pressure reduction system of the ""881 patent ineffective.
The method and apparatus according to the present invention overcomes the plugging problem which has heretofore existed.
In accordance with the present invention, a tubular member is provided that includes a landing collar which is attached at the bottom of the tubular member and which has an opening therethrough. This apparatus greatly reduces the likelihood of plugging the tubular member while running in and provides for lower flow resistance of fluid entering the tubular member during lowering in the hole.
An embodiment of the present invention also includes a lower liner wiper plug and an upper liner wiper plug. The upper liner wiper plug is releasably suspended from the drill string and the lower liner wiper plug is releasably suspended from the upper liner wiper plug. The lower liner wiper plug has at least one, and preferably two float valves. Both of these wiper plugs are thus near the top of the tubular member as the tubular member is run into the borehole.
Once the tubular member has been lowered to fall depth and the casing hanger has been set, the lower liner wiper plug is released from the upper liner wiper plug. Once released, the lower plug is pumped downhole by drilling fluid and thus displaces drilling mud from the bore of the tubular member through the large opening in the landing collar at the bottom of the tubular member. The lower liner wiper plug is locked into the landing collar, which results in float valves in the lower liner wiper plug being actuated. After cement has been pumped into the tubular member, the upper liner wiper plug is released from the drill string. As the upper liner wiper plug is pumped down, it forces the cement through the float valves, through the opening in the landing collar and into the annulus between the tubular member and the borehole.

Pumpdown valve plug assembly for liner cementing system


A process and articles for continuously making a tetrapolymer using two reactors connected in series with two unsaturated hydrocarbon streams, two injections of ethylene monomer, two injections of propylene monomer, and two injections of two different non-conjugated diene monomers with a Ziegler-Natta, a catalyst, a co-catalyst, and an optional promoter. The process allows for the creation of products and articles with high molecular weights while utilizing continuous flow reactors in series. The process allows for manufacture of anti-vibration articles made by tetrapolymers.

A need exists for a process to create a low damping high strength polymer with both high density impact absorbance and high heat resistance.
A need exists for a process to create a low damping high strength polymer for use as motor mounts.
A need exists for a process to create a low damping high strength polymer with a significant degree of long chain branching, a high degree of diene content, a unique molecular structure, and favorable elasticity characteristics.
The present embodiments meet these needs.

This patent is subject to a terminal disclaimer.

Process for continuously making high molecular weight tetrapolymer for use in anti-vibration applications


Composite polyamide reverse osmosis membranes are treated with an aqueous chlorinating agent at a concentration of 200 to 10,000 ppm for a time sufficient to improve flux, lower salt passage and increase the stability to base. In a preferred embodiment the membrane is treated with heated water at temperature of 40.degree. C. to 100.degree. C. before being exposed to the chlorine treatment.

The present invention relates to treatment of composite polyamide reverse osmosis membranes. More specifically, it relates to the treatment of polyamide membranes, used in the purification of salt water, to enhance the flux of water through the membrane and lower the salt passage. Additionally the treatment of the membranes in accordance with the present invention improves their resistance to base exposure.
The use of reverse osmosis membranes is based on the ability of such membranes to selectively allow passage of certain components of the mixture to be separated. In the purification of salt water, such as seawater, the water is contacted with one surface of the reverse osmosis membrane under pressure to cause effective permeation of water through the membrane while minimizing the passage of the salt in the feed solution.
The efficacy of a salt water reverse osmosis membrane, although primarily determined by the combination of high flux of the water and low salt passage, also depends on its ability to withstand chemical attack from impurities or additives contained in the water. Long term exposure to chlorine is well known to cause degradation of membranes and consequent failure of such membranes in the water purification processes in which they are employed. It is also well known that the effect of chlorine on the membrane depends on the chemical structure of the membrane. This is particularly true in polyamide membranes that contain a number of different sites where chlorine can react with the polymer. The degree to which polyamide membranes are attacked depends on the particular acids and amines employed in the formation of the polyamide.
Membranes used in water purification furthermore are run under a wide range acid and base conditions, i.e., pH, and subjected to periodic cleaning under even more severe conditions. Such cleaning is conducted at high pH in order to remove biological fouling and also to free the membrane of other colloidal and particulate materials. Long-term base stability is also a very desirable property. In many applications, such as in ultra-pure water systems, it is highly desirable to operate at as high a pH as possible since at such high pH permeation of other solutes in the water, such as dissolved boron and silica containing compounds or complexes and organic carbon containing compounds, is significantly lowered.
Polyamide membranes have been widely employed in reverse osmosis processes. U.S. Pat. No. 4,277,344 ('344), the teachings of which are hereby incorporated by reference, describes a variety of membranes having a polyamide discriminating layer on a porous support. These membranes are preferably prepared by interfacial polymerization of a difunctional aromatic amine, such as meta-phenylene diamine, and a trifunctional aromatic acyl halide, such as trimesoyl chloride and 1,3,5-cyclohexane tricarbonyl chloride, optionally also containing difunctional acyl halides. Such membranes are further illustrated in U.S. Pat. Nos. 4,520,044 and 4,606,943, the teachings of which are also hereby incorporated by reference.
The treatment of membranes to enhance their performance is disclosed in a number of patents. Thus the '344 mentioned above discloses the post-treatment of the polyamide membranes with a solution of a chlorine releasing agent, e.g., hypochlorite, at a pH of 8-9, as based on the concentration of the hypochlorite used, in order to improve the performance of the membrane. U.S. Pat. No. 5,051,178 discloses the treatment of certain polyamide composite thin film membranes based on polyamides obtained by condensation involving mixtures of amines and particularly triamines, with chlorine or a chlorine generating agent at a pH of 6-13, in order to improve salt rejection and water flux. U.S. Pat. No. 4,761,234 discloses the treatment of a polyamide thin film composite membrane employing triamino benzene as one monomer with an aqueous solution containing residual chlorine at a pH of 10.3 to improve the flux of the membrane at the cost of salt rejection.
The foregoing art has demonstrated that although the treatment of a membrane with an oxidizing agent and particularly an agent releasing chlorine can improve the flux of a polyamide membrane, it is generally at the cost of some other performance characteristic of the membrane. Nothing in the art indicates recognition of the significance of the pH or basicity of any chlorine treatment on the performance characteristics of composite polyamide membranes including the stability of the resulting membrane to base. It is therefore desirable to develop treatments of polyamide membranes that result in an improvement of both flux and salt rejection. It is a further object of this invention to provide reverse osmosis membranes that can be operated at very basic conditions without suffering an increase in salt passage. It is a further object of this invention to provide membranes exhibiting superior performance with respect to impurities in water other than salt.

Treatment of composite polyamide membranes to improve performance


A portable feed mill system consists of a housing containing a primary constituent tank, a first feed processor positioned to receive output from the primary constituent tank and a second feed processor. The second feed processor is positioned to receive the output from the first feed processor and an optional secondary feed constituent from either an integral or an external secondary feed constituent tank. Because the system is contained in a single housing, it may be remotely manufactured and transported to its final location at a cost far less than the cost of a conventional feed mill.

This invention relates to agricultural systems for processing measured quantities of feed constituents to form the desired finished product, and in particular to grinding and mixing, pelletizing and cooling, extruding and cooling, or cleaning and bagging measured quantities of feed constituents to form the desired finished feed product.
Many of today's feed mill systems are relatively large structures capable of yielding large quantities of feed from a number of feed constituents. These large-capacity feed mill systems usually include several large storage tanks, at least one feed processor, and a control system. An example of a feed mill system used to mix a number of feed constituents is shown in U.S. Pat. No. 3,822,056, in which the control system permits for the mixing of accurately measured quantities of macro-ingredients and micro-ingredients, both liquid and dry.
The use of a common feed processor for all feed constituents in a large-capacity feed mill provides a great deal of flexibility in the types of constituents than can be processed by the system, even though, in many instances, only a primary constituent, such as corn, needs to be processed by a particular feed processor. Therefore, the flexibility of the large-capacity feed mill system results in a configuration which requires power to transfer the constituents over long distances to the feed processor(s) and which covers a large geographic area. For example, separate feed constituents are normally stored in individual feed towers having inlets at the top of the towers and outlets at the bottom of the towers. To mix feed constituents, each constituent must be elevated and transferred to a separate common processor (such as a mixer) located in another tower. Thus, significant expense is incurred in constructing and maintaining separate towers to house the feed constituents and the mixer, and in providing and operating augers to elevate the contents of each feed tower and transfer them to the mixer.
As a result, feed mill systems are usually owned and operated only by large agricultural cooperatives or very large individual farm operators that use a large volume of feed. The expense of these systems is, in part, caused by the need to completely construct the mill at the site. Thus, the construction and maintenance costs of present feed mill systems, are prohibitively high for an individual farmer or a small agricultural cooperative that only needs moderate amounts of feed.


The invention relates to a device for the analysis of a liquid sample by way of light, comprising a transparent sample carrier, a movable upper mirror, which can be moved between a closed position, in which the mirror encloses a measurement space between itself and the sample carrier, and an open position, in which the sample carrier can be accessed so as to apply a sample, and a beam path, which guides incident measurement light between a light entrance into the measurement space and a light exit out of the measurement space from the sample carrier to the upper mirror reflecting the light. The beam path guides measurement light at an oblique angle of incidence through the sample carrier to the upper mirror.

The invention relates to a device for the photometric, in particular spectral photometric, analysis of a liquid sample having the characteristics described in the preamble of claim 1.
Such a device is known from DE 10 2004 023 178 B4. In the known device, a liquid sample is enclosed in a measurement space between a transparent sample carrier and an upper mirror located parallel thereto. Measurement light is radiated through the transparent sample carrier perpendicularly onto the upper mirror so as to analyze the sample. The upper mirror reflects the measurement light beam, so that the measurement light beam passes through the measurement space a total of two times between the light entrance and light exit.
A common method for analyzing liquid samples by way of light is the measurement of the sample absorption at one or more characteristic wavelengths. To this end, an absorption spectrum is generally measured, so as to detect analytes in a sample and determine the concentrations thereof. The level of absorption is the product of the optical path length of the measurement light through the sample, the analyte concentration and an extinction coefficient that is characteristic of the analyte in question at the respective light wavelength. For known extinction coefficients, it is thus possible to calculate a required analyte concentration based on the measured absorption values.
When liquid biological or biochemical samples are analyzed, for example for the quantitative determination of different nucleic acids, proteins or marker dyes, the problem arises that generally only small amounts of samples are available and therefore a quantitative analysis is made difficult.

Device for photometric analysis of a liquid sample and sample carrier therefor


Provided are: an engine-mounted controller capable of being suitably used in a vehicle that carries out an idle-stop operation while the vehicle is moving; and a vehicle. An engine-mounted controller of a vehicle determines whether or not an engine is in a completely stopped state when an idle-stop operation is canceled. If the controller determines that the engine is in a completely stopped state, a first control operation for suppressing the transmission of engine vibrations associated with engine idling is executed on the assumption that the engine is in a completely stopped state, and if the controller determines that the engine is not in a completely stopped state, the first control operation is prohibited when the engine restarts.

Japanese Laid-Open Patent Publication No. 2011-252553 (hereinafter referred to as "JP 2011-252553 A") has the object of providing an active vibration control supporting device, which is capable of appropriately suppressing and controlling transmission of vibration, so as to prevent rolling natural vibrations that are generated when the engine is started from being transmitted to a vehicle body (see paragraph[0006] and abstract). For accomplishing this object, an ACM_ECU 71 of JP 2011-252553 A acquires a crank angle from an engine AT_ECU before the engine is started, through a CAN communication line 207, in a motoring-time rolling natural vibration control unit 241 upon detecting a start of motoring. In addition, a vibration start timing, an input vibration load, a vibration frequency, and a vibration period of the rolling natural vibration, in conformity with the acquired crank angle before the engine is started, are calculated on the basis of rolling natural vibration characteristic data of a data unit 241a, to thereby generate a drive current waveform in a drive current computational unit 236. Then, based on the drive current waveform, drive control units 238A, 238B are used to control active control mounts MF, MR (see abstract). The aforementioned "crank angle before the engine is started" implies a crank angle at a time that the engine is stopped (see paragraph[0035]).


A mobile device and a method for providing a tethering service via a security mode and a list of preferred mobile devices are provided. The method includes determining, when the mobile device receives a connection request from a client mobile device, a number of client mobile devices that are currently connected to the mobile device, determining, when the number of connected client mobile devices is less than a preset maximum connection number, the number of created Basic Service Sets (BSSs), determining, when the number of BSSs is less than a preset maximum creation number, the identification-information regarding the client mobile device that requested connection, and providing a tethering service to the client mobile device according to the determined identification-information.

1. Field of the Invention
The present invention relates to Internet-enabled mobile devices that can provide Internet services and a method thereof. More particularly, the present invention relates to a tethering method for enabling an Internet-enabled mobile device to share the Internet services with other mobile devices, which cannot provide Internet services, by a tethering function.
2. Description of the Related Art
Tethering is a method that allows mobile devices, which cannot access a communication network, to share the Internet connection of an Internet-enabled mobile device that can access the communication network via 2nd Generation (2G) or 3rd Generation (3G) technology.
Tethering has been used to provide ad hoc service in a Wi-Fi network. That is, tethering allows nodes, which are distributed and can wirelessly communicate with each other without any access point, to provide Internet services via a network of a self-controlling structure.
However, ad hoc services do not provide a stable network connection so that data cannot be stably transferred. Ad hoc services are disadvantageous in that they limit the number of mobile devices that can be connected to the network and mobile devices connected to the network cannot enter an idle mode. In order to address these problems in ad hoc services, research has been conducted to develop mobile devices that can provide a tethering function using an Access Point.
However, a need still exists for a tethering method for enabling an Internet-enabled mobile device to share the Internet services with other mobile devices, which cannot provide Internet services, by a tethering function.

Tethering method and mobile device adapted thereto


Chipsets capable of preventing malfunction caused by feedback clock distortion are provided, in which a phase frequency detector generates a control voltage according to a first reference clock and a first feedback clock, a voltage-controlled oscillator generates an output clock according to the control voltage, a frequency divider performs a frequency-division on a second feedback clock to obtain the first feedback clock, and a frequency filter estimates swings and frequency of a third feedback clock from an external unit and selectively outputs one of the third feedback clock or the output clock to serve as the second clock.

1. Field of the Invention
The invention relates to a chipset, and more particularly, to a chipset capable of preventing malfunction caused by feedback clock distortion and a clock generation method thereof.
2. Description of the Related Art
FIG. 1 shows a conventional clock generation unit, in which a frequency phase detector (FPD) 10 generates a control voltage according to a reference clock SCLK and a clock divided by a frequency divider 14, and a voltage-controlled oscillator (VCO) 12 generates an output clock MCLK according to the control voltage. The frequency divider 14 receives and divides a feedback clock FBCLK from an external circuit, and then outputs the divided clock to the frequency phase detector 10, such that the clock generation unit 100 can adjust the output clock MCLK according to the feedback clock FBCLK. However, when the feedback clock FBCLK is distorted by the external circuit, the clock generation unit 100 improperly adjusts the output clock MCLK, such as improperly increasing the frequency of the output clock MCLK. The improper adjustment causes malfunctions to occur in the electronic elements coupled to the output clock MCLK.

Chipsets and clock generation methods thereof


A processor-implemented method, system, and/or computer program product deploys software images onto a computing system. A first computing machine is instantiated from a software image onto a computing system. The first computing machine has a first old access identifier, and is initially connected to a second computing machine in the computing system via a second old access identifier for the second computing machine. The second computing machine is reconfigured to have a new access identifier by: retrieving the new access identifier for said second computing machine, and associating the new access identifier with the second old access identifier; and redirecting each outbound communication, from the first old access identifier to the second old access identifier, to the new access identifier of the second computing machine.

The solution according to one or more embodiments of the present invention relates to the data processing field. More specifically, this solution relates to the deployment of software images.
Deployment of software images is a commonplace activity in modern computing systems (for example, virtual data centers); generally speaking, a software image is a snapshot of a software structure that is installed on a mass memory of a computing machine. For example, software images are widely used in virtual appliances. A virtual appliance is a software appliance (i.e., a software solution for performing a specific user task being encapsulated in a pre-built, self-contained package), which is designed to run in a virtualized environment. For this purpose, the package of the virtual appliance (for example, conforming to the Open Virtualization Format, or OVF) comprises the definition of one or more virtual machines, or VMs (i.e., emulations by software of physical machines) and the corresponding software images, each one with one or more application programs (for implementing the software solution) and a Just Enough Operating System, or JeOS (i.e., a limited operating system specifically tailored to support the application programs). Virtual appliances allow provisioning the corresponding software solutions in a very simple and fast way; this is especially useful in cloud computing environments (wherein multiple services are provided on demand).
Each software image is built by preparing a (reference) computing machine with the installation of the required operating system and application programs in a building environment. The computing machine is then configured for testing its correct operation in the building environment. Typically, this involves the assignment at the operating system level of an access identifier to the computing machine (for example, a hostname); moreover, especially in case of large virtual appliances with a multi-tier structure wherein multiple virtual machines cooperate for implementing the software solution (for example, conforming to the Service Oriented Architecture, or SOA), this also involves the connection at the application program level to the access identifiers of other computing machines (for addressing outbound communications thereto). The software image of the computing machine is then captured and stored into a shared repository, from which it may be copied and instantiated into any desired target environment.

Deployment of software images with run-time reconnection

International Business Machines Corporation


A system efficiently determines of the likely effectiveness of the cache memory for various cache memory sizes, based on a prediction of the likely cache miss rate, the prediction being based on operational statistics which are gathered during actual use of the cache memory over one or more time periods, and based on a variety of cache management methodologies. Based on the prediction, the operator or the system can facilitate increasing or decreasing the size of the cache memory, or maintaining the cache memory at its then-current size. The system determines the cache memory's read miss rate from statistics that are collected during use of the cache memory over an arbitrary time interval, including statistics concerning the file information retrieval activity and the extent of activity per unit time for system. Based on the statistics, equations, which are based on the respective cache memory management methodology, including the FIFO (first-in/first-out) methodology or the LRU (least-recently used) methodology, used in managing the cache memory, are solved to generate a prediction of the cache miss rate for a particular cache memory size, which may be larger or smaller than the current cache memory size, and for the particular cache memory management methodology. The system can repeat this a number of times over respective time intervals to determine corresponding predictions based on the cache memory utilization for respective sets of statistics determined during each time interval. Thereafter, the system or an operator can effect a change in the cache memory size based on the cache miss rate predictions.

Digital data processing systems include one or more processors for performing processing operations in connection with information stored in a memory. Typically, a memory in a modern digital data processing system consists of a hierarchy of storage elements, extending from large-capacity but relatively slow storage elements and various levels of lower-capacity and relatively fast storage devices. The large-capacity and relatively slow devices include such types of devices as disk or tape storage devices which store information on a magnetic medium; such devices are relatively inexpensive on a storage cost per unit of storage basis. Intermediate in the hierarchy, both in terms of speed and storage capacity are random-access memories, which are somewhat faster than the disk or tape devices, but which are also more expensive on a storage cost per unit of storage basis. At the fastest end of the hierarchy are cache memories, which are also the most expensive and thus generally the smallest.
Generally, during processing operations, a processor will enable information to be processed to be copied from the slower devices to the increasingly faster devices for faster retrieval. Generally, transfers between, for example, disk devices and random-access memories are in relatively large blocks, and transfers between the random-access memories and cache memories are in somewhat smaller "cache lines." In both cases, information is copies to the random-access memory and cache memory on an "as needed" basis, that is, when the processor determines that it needs particular information in its processing, it will enable blocks or cache lines which contain information to be copied to the respective next faster information storage level in the memory hierarchy. Certain prediction methodologies have been developed to attempt to predict the whether a processor will need information for processing before it (that is, the processor) actually needs the information, and to enable the information to be copied to the respective next faster information storage level. However, generally at some point in the processing operations, the processor will determine that information required for processing is not available in the faster information storage level, that is, a "read miss" will occur, and it (that is, the processor) will need to delay its processing operations until the information is available. Generally, the rate at which read misses will occur with storage element(s) at a particular level in the hierarchy will be related to the storage capacity of the storage element(s) at the particular level, as well as the pattern with which the processor accesses the information in the respective storage level. In any case, to enhance the processing efficiency of a digital data processing system, it is generally helpful to be able to assess the effect of changing the capacity of the memory element(s) at a particular level in the memory hierarchy on the rate of read misses at the particular level.

System and method for assessing the effectiveness of a cache memory or portion thereof using FIFO or LRU using cache utilization statistics


This storage system has a first disk array device for providing a first volume that stores data transmitted from a host system, a second disk array device for providing a second volume that is virtualized with the first disk array device, and a management terminal for managing the first disk array device; wherein the first disk array device includes a first management unit for managing volume information of the virtualized volume that was virtualized in the first disk array device by being mapped with the second volume; and a first transmission unit for transmitting, based on an external operation, the volume information of the virtualized volume managed with the first management unit to the management terminal; and wherein the management terminal includes a second management unit for managing the volume information of the virtualized volume transmitted from the first transmission unit.

The present invention relates to a storage system and management method thereof, and, for instance, is suitably employed in a storage system which virtualizes a volume of a certain disk array device with another disk array device.
Conventionally, a storage system which directly connects a disk array device to a host system and stores data in such disk array device was widely prevalent. Thus, in order for the host system to access data of a disk array device connected to another host system, the host system had to be connected, via such other host system, to the disk array device connected to the other host system.
Whereas, pursuant to the advancement of network technology in recent years and the exponential increase in the data volume to be handled by storage systems, the host system for inputting and outputting data and the storage system for storing data are being decentralized, and a storage system has been developed where a plurality of host systems are connected to disk array devices via a network, and the respective host systems share the data of the respective disk array devices.
As an example of such a storage system, there are, for example, a SAN (Storage Area Network) storage system that connects a host system and a disk array device via a SAN and provides block access service to the host system, and a NAS (Network Attached Storage) storage system that connects a host system and a disk array device via an IP network or the like and provides file access service to the host system.
Further, in recent years, proposed is a storage system having a first disk array device connected to a host system and a second disk array device connected to this first disk array device, wherein a plurality of disk array devices are integrated by mapping a logical volume of a second disk array device to a virtual volume of the first disk array device, and the first disk array device provides the logical volume of the second disk array device to the host system as though it is its own logical volume (e.g. refer to Japanese Patent Laid-Open Publication No. 2005-107645).

Storage system and management method thereof


A local shimming system for magnetic resonance imaging and the method thereof, wherein the shimming method comprises the following steps: collecting B0 field map information using two-dimensional gradient echo (301); calculating and evaluating the homogeneity of B0 (302); optimizing the current of each channel shim coil (303); determining whether the minimum standard deviation value of Δf is obtained (304); outputting an optimal current combination values and setting an optimum current value corresponding to each channel of the shim coil on the current control software (305); and testing and evaluating the homogeneity of B0 to achieve the shimming goal (306).

In a magnetic resonance imaging system, the magnet itself is generally capable of providing a relatively homogeneous static magnetic field B0 in a certain space. However, due to the difference in magnetic susceptibility of the tissue, local magnetic field changes are generated at the interface, causing image artifacts. Especially in single-shot spin Echo-planar imaging (EPI), geometric distortion, signal loss and image blur will occur. In general, increasing the number of shim coils can reduce the non-homogeneity of the magnetic field, thereby improving the quality of the image.
In general, shim coils mainly include two types: spherical harmonic function (SH) shim coils and multi-coil (MC) shim coils. The SH shim coil is generally used for the magnetic field non-homogeneity correction of the main magnet, while the SH shim coil of the commercial MRI system has the second order at most. In animal and human brain experiments, the magnetic field non-homogeneity at the junction of tissue and air is often as high as 5 orders, so the order of the SH shim coil needs to be increased to 5 orders to achieve a better shimming effect. However, increasing the order of the SH shim coils brings about practical problems, such as reduction of efficient space, poor efficiency of the coil. Moreover, an additional cooling system for shim coils and the need to increase the number of power amplifiers should be considered. Compared with the SH shim coil, the MC shim coil generates a relatively complex high-order magnetic field with a plurality of simple coil loops, obtaining a better shimming capability. Moreover, the inductance of the MC shim coil is relatively small, and is far away from the main magnet, without causing a large eddy current.
At present, in magnetic resonance imaging, the more is the number of the shimming multi-coil units, the higher is the order of the non-uniform magnetic field that can be compensated. However, the problem is that more power amplifiers are needed; moreover, in the shimming process, it is necessary to perform sensitivity field map collection for each channel coil unit, which takes long time.
For example, CN 201510629760 discloses a shim coil device that compensates for non-homogeneity of a main magnetic field in the process of performing medical magnetic resonance imaging of human chest. CN201210202891, CN201410414924 and CN201510173911 have also developed shimming systems for magnetic resonance imaging of human head and abdomen. The papers "Magnetic field modeling with a set of individual localized coils", Journal of Magnetic Resonance, 2010, 204(2): 281-289 by Juchem C et al., and "Multicoil shimming of the mouse brain[J]. Magnetic resonance in medicine", 2011, 66(3): 893-900 by Juchem C et al., describe a shim coil applied to magnetic resonance imaging in mouse brains, in which the number of channels is from 24 to 48, and the number of power amplifiers is also from 24 to 48, the cost is much higher and the system is more complicated.
In view of this, a local shimming system and a process capable of achieving a better shimming effect using a shim coil with a small number of channels should be developed.

Local shimming system for magnetic resonance imaging and method thereof

SHENZHEN INSTITUTES OF ADVANCED TECHNOLOGY


A method produces microalloyed tubular steel from a steel melt having a chemical composition of 0.04-0.05% C, 1.3-1.5% Mn, 0.035-0.05% Nb, 0.035-0.06% V, 0.2-0.4% Cr, 0.2-0.3% Si, >0.015% Al and <0.008% N in percent by weight, the remainder consisting of Fe and unavoidable impurities. The method includes roughening an uncut thin slab strand formed from the steel melt to form a rough strip, reheating the rough strip to produce a reheated rough strip, and finish-rolling the descaled rough strip in a first group of rolling stands and in a second group of the rolling stands.

Described below is a method for producing microalloyed tubular steel in a combined casting-rolling installation, and to the microalloyed tubular steel which can be produced by applying the method.
Microalloyed steels are those to which 0.01 to 0.1 percent by mass of niobium, vanadium or titanium (or even higher contents of the cited elements in combination) is alloyed in order to achieve high strength, e.g. by forming carbides and nitrides and grain refining. The alloying elements disperse partially during heating to deformation temperature. They are dispersed in the austenite and result in an increase in the recrystallization temperature. During the transformation of the shaped austenitic grain into ferrite and pearlite, bainite or even martensite, a refined transformation microstructure is formed according to the degree of deformation. In addition, carbides form in the case of carbon and nitrides form in the case of nitrogen during cooling. The grain refining achieved in this way increases the strength, essentially without reducing the toughness.
The yield point is a characteristic material value and denotes the maximal stress which a material will withstand before exhibiting any visible plastic deformation when subjected to a simple and zero-torque tensile load. If the yield point is exceeded, the material no longer returns to its original shape when the load is reduced, and an extension of the specimen remains. The yield point is generally determined during the tensile test and specified in the unit N/mm2=MPa.
Steel grades having a minimal yield point of at least 485 N/mm2 are required for the API 5L-X70 and API 5L-X80 standards (or higher) of the American Petroleum Institute (API). For example, steel according to the standard API 5L-X70 has a yield point of at least 485 N/mm2 and a tensile strength of at least 570 N/mm2.
This standard is used to designate steel products which can be used in the production of tubes by welding for the purpose of pipeline construction, and which must therefore have a specific strength but must also be highly ductile at low temperatures. The production of such steel products requires specific types of methods.
Existing manufacturing methods for such steels usually require the following conditions to be satisfied:
Only pure iron with low sulfur and phosphorous content is suitable for the steel composition, and the addition of microalloying elements such as niobium Nb, titanium Ti or vanadium V is required in order to achieve a fine grain.
Suitable temperature management is required in order to prevent segregation (dissociation) of the melt during the production of the slab. This occurs at the transition point of the melt into the solid state and results in different material properties within the slab. Suitable temperature management can also be used to prevent cracking in the second ductility minimum.
The rolling of the slab is effected by so-called thermomechanical rolling:
During roughing, a uniformly heated slab having a relatively coarse-grained microstructure arrives from a heating furnace at the roughing train (roughing mill). In order to achieve recrystallization, during which the relatively coarse-grained microstructure of the slab becomes increasingly fine-grained, the thickness of the steel must be reduced by at least 40%, normally in reversing operation. A fine austenitic grain is required before the rolled stock is shaped further in the finishing train.
During finish-rolling in the finishing train, final shaping takes place in a temperature range at which the material no longer recrystallizes: typically in the temperature range of 800-900° C. In this case, the steel band is stretched by a factor of at least 2.5 and usually more than 3 in order to achieve the desired material properties. Typical intake temperatures of the steel band into the finishing train are between 800° C. and 900° C. The exit temperature of the steel band emerging from the finishing train is typically in the region of 830° C.
Faster cooling of the steel band after it emerges from the finishing train results in the formation of particularly fine ferrite grains, even the development of acicular (needle-shaped) ferrite in some circumstances. This produces an extremely fine-grained transformation microstructure having high strength and very good toughness.
EP 1 978 121 A1 discloses a corresponding method for the production of highly weldable steel sheets having a yield point (yield stress) of at least 350 MPa and a tensile strength of at least 570 MPa, wherein the steel is thermomechanically rolled in the finishing train.
The production of API X70 tubular steel in a combined casting-rolling installation known as "CSP flex" is disclosed in the publication by C. Klein et al.: "Von CSP zu CSP flex—das neue Konzept für die Dünnbrammentechnologie, stahl and eisen 131(2011), No. 11". The proposed production method has the disadvantage that the steel melt must have a relatively high proportion of alloy, in particular niobium, in order to limit the grain growth of the cut thin slab strand in the heating furnace (usually a tunnel furnace). The production costs per ton of finished strip increase due to the high proportion of alloy.
The existing methods have the disadvantage that undesired grain growth can occur due to the long time the steel spends in the heating furnace ahead of the roughing train and/or the finishing train.

Method for producing microalloyed tubular steel in combined casting-rolling installation and microalloyed tubular steel


A non-volatile memory configuration scheme is disclosed for volatile-memory-based programmable circuits in a programmable integrated circuit that includes an FPGA fabric, a plurality of first configurable circuit elements external to the FPGA fabric, and a plurality of second configurable circuit elements external to the FPGA fabric. A plurality of distributed configuration non-volatile memory cells is disposed in the FPGA, each one of the distributed configuration non-volatile memory cells coupled to a different one of the plurality of first configurable circuit elements. A non-volatile memory array stores configuration information for the second configurable circuit elements. A plurality of register cells is disposed with the second configurable circuit elements and is coupleable to the non-volatile memory array, each one of the register cells coupled to a different one of the plurality of second configurable circuit elements.

The present invention relates to integrated circuit technology. More particularly, the present invention relates to programmable logic circuits, such as FPGAs, and particularly flash-based programmable logic circuits. The present invention addresses how to efficiently provide static control signals to circuit elements external to the FPGA fabric without compromising the bandwidth of the dynamic signal path.
An FPGA integrated circuit includes many circuit elements in addition to the FPGA fabric that require bits to control their functionality. A typical example is a general purpose I/O cell which typically has three dynamic signals (i.e., input, output, enable) that must be capable of being driven by a net from and to the FPGA.
Accompanying these signals are usually several control signals (which may number ten or more) that typically do not need connectivity to a net but need to be statically set. Such signals include those to configure the I/O standard being implemented (e.g. HSTL, PCI, etc.), and the enabling of delay elements in the input path. As the element gets more complex, the number of required static control signals can become much larger than the number of dynamic signals. An example of this is a SerDes with physical coding sub-layer (PCS) circuitry which may require static control signals for idle, align and stuff characters (16 bits each), SerDes drive, pre-emphasis and equalization control, and PCS data path selection.
As the number of signals necessary to configure circuit elements outside of the FPGA fabric increases, so does the number of signal lines needed to carry those signals. At some point, the bandwidth of the dynamic signal path is affected, since there is a physical limit to the number of conductors that can pass outside of the FPGA fabric. The present invention addresses how to efficiently provide those control signals to the circuit elements without compromising the bandwidth of the dynamic signal path.
Referring first to FIG. 1, a block diagram illustrates a prior-art arrangement for configuring circuit elements external to an FPGA array in an integrated circuit. Integrated circuit 10 includes an FPGA array 12 and also includes a group of external circuit elements 14. As is known in the art, the group of external circuit elements 14 may include circuit elements that need to be configured by static signals to control aspects of their operation. Representative ones of such configurable circuit elements are represented by small squares 16, 18, 20, 22, 24, 26, 28, and 30. Persons of ordinary skill in the art will appreciate that such configurable circuit elements can be as simple as an I/O or as complex as a PCS or a processor.
The configurable circuit elements 16, 18, 20, 22, 24, 26, 28, and 30 are controlled, respectively, by configuration bits 32, 34, 36, 38, 40, 42, 44, and 46, distributed throughout the FPGA array 12. Thus configuration bit 32 is shown coupled to external configurable circuit element 16, configuration bit 34 is shown coupled to external configurable circuit element 18, and so forth. The configuration bits may comprise non-volatile memory cells such as flash memory cells.
As will be apparent to persons of ordinary skill in the art examining FIG. 1, an individual conductor is needed to make each of the connections, thus requiring eight conductors running from the FPGA 12 to the external circuit elements 14 for making the eight connections in the illustrative example of FIG. 1.
In real-world integrated circuits that implement the above-described scheme, the number of connections between configuration bits in the FPGA array and the external circuit elements becomes exceedingly large as the size of the integrated circuit (i.e., gate count and number of I/O and other circuits external to the FPGA) increases. In addition, as the control requirements proliferate, there may not be enough physical room or architectural bandwidth to efficiently route one signal per control bit to the external element without compromising the effective bandwidth of the dynamic signals. At some point, the number of such conductors becomes unreasonably large and can become a critical design issue. The present invention presents a solution to this problem.
The configurable circuit elements 16, 18, 20, 22, 24, 26, 28, and 30 are controlled, respectively, by configuration bits 32, 34, 36, 38, 40, 42, 44, and 46, distributed throughout the FPGA fabric 12. Thus configuration bit 32 is shown coupled to external configurable circuit element 16, configuration bit 34 is shown coupled to external configurable circuit element 18, and so forth. The configuration bits may comprise non-volatile memory cells such as flash memory cells.
As will be apparent to persons of ordinary skill in the art examining FIG. 1, an individual conductor is needed to make each of the connections, thus requiring eight conductors running from the FPGA 12 to the external circuit elements 14 for making the eight connections in the illustrative example of FIG. 1.
In real-world integrated circuits that implement the above-described scheme, the number of connections between configuration bits in the FPGA fabric and the external circuit elements becomes exceedingly large as the size of the integrated circuit (i.e., gate count and number of I/O and other circuits external to the FPGA) increases. In addition, as the control requirements proliferate, there may not be enough physical room or architectural bandwidth to efficiently route one signal per control bit to the external element without compromising the effective bandwidth of the dynamic signals. At some point, the number of such conductors becomes unreasonably large and can become a critical design issue. The present invention presents a solution to this problem.

Non-volatile memory configuration scheme for volatile-memory-based programmable circuits in an FPGA


A fault severity check and source identification method for a frequency domain instrument accesses acquired reflection data for a transmission line under test. From the acquired data reflection surfaces are isolated as a function of distance. Each reflection surface is examined to produce a frequency response profile and a worst-case reflection response to determine fault severity. The frequency response profile may also be correlated in a pattern recognition algorithm with known reference source profiles to determine the source identification for the fault.

The present invention relates to transmission line testing, and more particularly to a method of determining the nature of a transmission discontinuity (fault) and its severity.
In transmission line testing it is very important to know not only the distance to a transmission discontinuity, but also the nature of the fault causing the discontinuity and its severity. For frequency domain based measurements, due to the frequency selective nature of most reflection responses, the distance-to-fault (DTF) result sometimes does not reflect the actual severity of the problem. For example a transmission line with a severe corrosion problem when stimulated with a step-function waveform shows a large reflection, as shown in FIG. 1b, but may only show a small reflection when stimulated with an impulse response or with swept tones of no low frequency components, as shown in FIG. 1a, which is hardly distinguishable from some non-harmful reflections. Where a test instrument uses a simple impulse-like signal source by stepping a sinusoid through a frequency range of interest, such as from 24 MHz up, it has the potential of missing the severity of built-up deterioration.
In an antenna system the most common problems are corrosion and watering. FIGS. 2a and 2b show the types of terminating impedances associated with each of these problems, with FIGS. 3a and 3b showing the frequency responses for the resultant reflections. Different terminating impedances have different frequency responses. When there are more than one reflection surface in the transmission line, the characteristic of the frequency response profile for the measured reflection is usually hard to categorize. FIGS. 4a and 4b show the frequency response and the reflection magnitude response of a system with both Type-I and Type-II impedances. As seen the spectral profile in FIG. 4a is neither the Type-I nor the Type-II profile shown in FIG. 3a or 3b.
What is desired is a method of determining not only the distance to a transmission discontinuity but also the nature of the fault causing the discontinuity and its severity, especially in situations where the characteristic of a frequency response profile for the measured reflection is difficult to categorize.

Fault severity check and source identification


A liquid receptacle has an inner vessel for holding a liquid, an insulated outer shell spaced from the Miler vessel, and a chamber defined between the inner vessel and the outer shell. A phase change material is disposed in the chamber for absorbing thermal energy from the liquid and then releasing the thermal energy back to the liquid to maintain the temperature of the liquid.

There have been a variety of attempts to provide liquid receptacles and containers designed to alter the temperature of liquids contained therein. For example, insulated mugs seek to prevent heat loss to the surrounding environment and therefore maintain a beverage's temperature. It is also known to provide a liquid receptacle with a phase change material in the wall of the receptacle. The phase change material regeneratively absorbs thermal energy from the liquid and then releases the thermal energy back to the liquid to maintain the temperature of the liquid. There remains a need for improvements in this field.

Thermal receptacle with phase change material


A data reader includes a memory board provided to a removable member and a reading member including a reading terminal. The memory board includes a positioning opening, a ground terminal provided to the positioning opening, and a contact terminal. The reading member includes an engagement projection that fits in the positioning opening and is disposed adjacent and parallel to the reading terminal. The engagement projection includes a uniform diameter portion, a tapered portion extending from the uniform diameter portion, and an apparatus-side ground terminal to contact the ground terminal of the memory board when the engagement projection fits in the positioning opening. The apparatus-side ground terminal includes a portion projecting laterally from the uniform diameter portion from an end of the uniform diameter portion toward a reading member base and an extended portion at the end of the uniform diameter portion, covered with the tapered portion.

1. Technical Field
Embodiments of the present invention generally relate to a data reader to read out data from a memory of a removable member installed in an image forming apparatus, such as a copier, a printer, a facsimile machine, a plotter, or a multifunction machine (so-called multifunction peripheral or MFP) having at least two of coping, printing, facsimile transmission, plotting, and scanning capabilities and further relate to an image forming apparatus incorporating the data reader.
2. Description of the Background Art
Generally, electrophotographic image forming apparatuses such as copiers, printers, facsimile machines, or multifunction machines (MFPs) include a latent image bearer such as a photoreceptor drum or a photosensitive belt, a developing device, and the like, and direct laser beams onto the surface of the latent image bearer, thereby forming electrostatic latent images according to image data. The electrostatic latent image is developed with toner by the developing device.
As toner in the developing device is thus consumed, the image forming apparatus is typically provided with a replaceable toner container (i.e., a toner cartridge) to supply toner therefrom to the developing device. Toner cartridges are provided with an identification chip (ID) board (hereinafter simply "ID chip"). For example, the ID chip is attached to an end face of the toner cartridge. The ID chip includes a memory to store data such as the amount of remaining toner, compatibility with a body of the image forming apparatus (hereinafter "apparatus body"), serial number, and the like.
Additionally, the image forming apparatus is provided with a data reader to electrically connect the ID chip to the apparatus body simultaneously when the toner cartridge to which the ID chip is attached is installed in a container mount in the apparatus body to enable the apparatus body to read out data from the ID chip.
For example, JP-2009-069417-A proposes a contact-type data reader including an engaging device to engage the apparatus body and the toner cartridge with each other while determining relative positions therebetween. The engaging device is provided with an electrode pin on the apparatus side (hereinafter also "apparatus-side electrode") and an electrode pin on the cartridge side (hereinafter also "chip-side electrode), which slide on and contact to each other, thereby enabling the apparatus body to read out data from the ID chip. Additionally, there are contactless data readers to read out data from the ID chip via an antenna such as those proposed in JP-2012-198499-A.
Contact-type data readers and contactless data readers have merits and demerits respectively. To reduce the size and cost of the image forming apparatus, contactless data readers without antennas may be advantageous.
Contact-type data readers of related arts are described below with reference to FIGS. 11A through 12C.
FIGS. 11A through 11C illustrate a contact-type data reader 211 provided to a toner container mount 201 of an image forming apparatus. A toner cartridge 202 is inserted into the toner container mount 201 in the longitudinal direction of the toner cartridge 202. A cap 203 is provided to an end of the toner cartridge 202 in the longitudinal direction thereof. The cap 203 is removably fitted in a receiving portion 204 of the toner container mount 201, and the positioning thereof is determined thereby.
When the cap 203 is fitted in the receiving portion 204 of the toner container mount 201, an ID chip 206 (a memory) on an end face 205 of the cap 203 faces a connector 208 held by a base frame 207 of the toner container mount 201. At that time, as shown in FIG. 11C, four electrode pins 209, which are like four bent pieces, of the connector 208 contact four electrodes 210, serving as metal terminals, of the ID chip 206. Then, the connector 208 serves as a reading member to read out data relating to the toner cartridge 202 stored in the ID chip 206.
FIGS. 12A through 12C illustrate a contact-type data reader 212, which is provided to the toner container mount 201 similarly to the data reader 211 shown in FIGS. 11A through 11C.
In this configuration, as shown in FIGS. 12A through 12C, a pair of projections 218 and three electrode pins 216 interposed therebetween are provided to a connector 213 on the side of the base frame 207. Each electrode pin 216 is columnar and arranged vertically. The electrode pins 216 each are constructed of a conductive material and have an identical external diameter.
By contrast, an ID chip 214 on an end face of the cap 203 of the toner cartridge 202 is shaped like a rectangular plate, and three through hole electrodes 217 are provided on a first side thereof. The through hole electrodes 217 are arranged in line. Inner circumferential rims of the through hole electrodes 217 are constructed of a conductive material and have an inner diameter slightly smaller than the outer diameter of each electrode pin 216.
When the toner cartridge 202 is attached to the receiving portion 204, the conductive electrode pins 216 of the connector 213 respectively fit in the conductive inner circumferential rims of the through hole electrodes 217 formed in the ID chip 214. Then, the image forming apparatus can read out data stored in the ID chip 214.

Data reader and image forming apparatus incorporating same


A measuring device includes a housing and a power source, a conductive detecting unit arranged in the housing and connected with the power source, a carrier facing the conductive detecting unit, connection terminals arranged on the carrier and connected with the power source, and a lifting mechanism configured to control the conductive detecting unit and the carrier to move relatively in the first direction. wherein the The carrying surface of the carrier is parallel to the main surface of the conductive detecting unit, and the first direction is a direction perpendicular to the carrying surface.

The present disclosure relates to the technical field of display, in particular to a measuring device and a measuring system of a display substrate.
Liquid crystal display (LCD) is widely used because of its light and thin body, low power consumption, no radiation and long service life.
Since the thickness of the liquid crystal layer has a great influence on the response speed, contrast and visual angle of the LCD, usually the person skilled in the art adjusts the thickness of the liquid crystal layer inside the LCD by arranging spacers between the two aligned substrates. The heights of the spacers have direct influence on the thickness of the liquid crystal layer. Therefore, the height is one of the important measurement parameters in the research and analysis of the spacers.
At present, the measuring method of spacer height is mainly optical method, which has the advantages of high measuring accuracy, but at the same time there are also some problems such as low measuring efficiency and complicated measuring equipment. Especially for high-resolution display products, the number of internal spacers is large, and the distribution of the overall spacer height represented by the measured height data of limited number of spacers obviously has error. As a result, it is difficult to obtain accurate analysis results when analyzing the correlation between LCD abnormalities and the height of spacers, which makes it more difficult and takes longer to analyze the causes of LCD defects.

Ordos Yuansheng Optoelectronics Co., Ltd.


An antitachycardia stimulation device that automatically adjusts its detection rate threshold as a function of a sensed physiological parameter indicative of cardiac rate. The implantable antitachycardia stimulation device includes heart rate detection circuitry and antitachycardia therapy circuitry for applying a specific antitachycardia therapy in the event that the detected heart rate falls within at least one tachycardia rate zone. The tachycardia rate zone is defined by a lower threshold limit, and may also be defined by an upper threshold limit if more than one rate zone is used. The lower threshold limit is automatically adjusted as a function of an independently sensed physiological parameter that predicts a normal or natural change in the heart rate. If more then one rate zone is used, other threshold limits may also be adjusted automatically as a separate function of the same sensed physiological parameter. In one embodiment of the invention, the implantable stimulation device comprises a rate-responsive pacemaker, and the sensed physiological parameter used to adjust the rate threshold limit(s) is also used to define a sensor indicated rate signal to control the pacing rate of the pacemaker.

Antitachycardia therapy devices, such a antitachycardia pacemakers or antitachycardia defibrillators-cardioverters, utilize heart rate detection circuitry to determine the onset of a cardiac arrhythmia. Such rate detection circuitry typically includes discrete rate zones for the classification of arrhythmias. The rate zones, which are typically set through one or more user programmable parameters, dictate what type of device response, i.e., what type of antitachycardia therapy, will be provided whenever the detected heart rate falls within a given rate zone. For example, a user may define a low rate ventricular tachycardia zone which is identified by a low rate limit, rate A (e.g., 135 bpm), and a high rate limit, rate B (e.g., 175 bpm). Any detected heart rate that falls within this zone would thus be identified as a low rate ventricular tachycardia, and such identification would trigger an appropriate therapy from the antitachycardia therapy device. Similarly, a high rate tachycardia classification zone, e.g., between 175 and 240 bpm, may be defined that borders the low rate tachycardia zone. Thus, any detected heart rate that falls within the high rate tachycardia zone would be identified as a high rate ventricular tachycardia, thereby triggering another type of therapy from the antitachycardia therapy device. Further, in some devices, a third zone may be added just above the high rate tachycardia zone. Hence, in this fashion, the user can set up a single large rate zone or as may smaller bordering rate zones as desired, with each rate zone providing a particular one of a variety of independent antitachycardia therapies that is automatically applied by the device in order to terminate a perceived arrhythmia. As needed, the detection and classification of arrhythmias may be further based on additional parameters, in addition to heart rate, such as the hemodynamics identified by a particular sensor, and/or other rate parameters, such as the onset, stability or duration of the detected heart rate.
Unfortunately, the selection of discrete rate zones may prove to be problematic when a patient has a normal sinus rate that enters into one of the tachycardia zones during exercise or during other periods of physiological stress. Although various discriminating parameters, such as the onset and stability of the detected rate or rhythm, may be used in an attempt to minimize the detection of a fast normal sinus rate as a tachycardia rate, the fast rhythm or rate may still be incorrectly classified as an arrhythmia, resulting in antitachycardia therapy being provided by the device. Such antitachycardia therapy could be inappropriate, and even dangerous, because it may actually induce an actual arrhythmia when provided incorrectly.
Hence, it is apparent that there is a critical need for rate detection circuitry in an antitachyardia pacemaker or defibrillator-cardioverter that minimizes the risk of incorrectly identifying and classifying a fast sinus rate (for which antitachycardia therapy is not needed nor desired) as an arrhythmia (for which antitachycardia therapy is needed and desired).

Automatic adjustment of detection rate threshold in an implantable antitachycardia therapy device