A translator circuit for a drive circuit of a power transistor connected to an electric load. The translator circuit includes a first current generator placed between a supply voltage reference and an input terminal of the drive circuit, a controlled switch placed between the input terminal and a ground reference, and a second current generator interposed between the controlled switch and the ground reference. The translator circuit further includes a circuit leg in the form of a current mirror connected in parallel with the second current generator. The translator circuit avoids phenomena of false switching.

As is well known, a number of applications in the electronic field require a regulation of a current in an electric load. In most cases, the electric load current is regulated by means of a power transistor which may be either of an integrated type or a discrete type. The power transistor, in turn, is driven by means of an integrated drive circuit, referred to as a high side driver.
A shift level or translator circuit is usually associated with high side driver circuits for converting a drive signal, being referred to a respective signal ground, to a drive signal which is referred to a signal ground of the integrated drive circuit. A good translator circuit allows signal propagation times to be minimized, and a propagation of a power on/off signal to be substantially symmetrized.
In certain applications, e.g. switching converters, it is especially important that the switching edges of the power transistor be quite small, so as not to impair the converter efficiency. In addition, false switchings of the power transistor may occur because the ground for the drive circuit is coincident with the source terminal of the power transistor, so that, with the potential at the source terminal varying rapidly, the drive signal should be able to move at the same rate.
The state of the art already offers an approach to meeting this requirement. For example, shown in FIG. 1 of the accompanying drawings is a drive circuit 10, according to the prior art, intended for a power transistor M1 of the NMOS type. The circuit 10 is supplied by a voltage Vs of 12 Volts, and provides an output U for driving the control terminal of the power transistor M1. The power transistor M1 is connected between a supply voltage reference Vcc and one end of an electric load 13. This end is coincident with a signal ground reference of the circuit 10 where a potential GND.sub.-- driver is presented.
A translator circuit 11 is associated with the circuit 10 and utilizes two current generators 14 and 15 generating currents I1 and I2, respectively. Specifically, the translator circuit 11 comprises a transistor A of the NMOS type which has its source terminal connected toward a signal ground, through the first generator 14 of the current I1. The drain terminal of the transistor A is connected to an input terminal IN of the drive circuit 10 and to the second generator 15 of the current I2. A signal DRIVE.sub.-- high is applied to this input terminal IN, while a control terminal G of the transistor A receives a signal DRIVE.sub.-- low.
The transistor A basically functions as a switch. With the switch in the open state, the current I1 is zero, and the signal DRIVE.sub.-- high takes a value which equals the combined values of the ground GND.sub.-- driver of the circuit 10 and the voltage Vs.
On the other hand, when the switch A in the closed state, the current I1 is larger than the current I2, and the potential DRIVE.sub.-- high at the input terminal IN matches that GND.sub.-- driver of the ground reference of the circuit 10. In this situation, the power transistor M1 is forced to the `on` state.
While being in many ways advantageous and essentially achieving its objective, this prior approach is still beset with a risk of false switchings. In fact, upon closing the switch A, the power-on information is transmitted to the power transistor M1, thereby causing it to conduct. The potential at the source terminal of the power transistor M1 rises toward the value of the supply voltage Vcc. This change takes place quite rapidly and results in the current I2 being increased, since the current generator 15 is implemented in the form of a current mirror structure 12, as shown in FIG. 2.
The current mirror 12 comprises a pair of transistors, Ma and Mb, of the PMOS type having their respective control terminals connected together. The transistor Ma is in diode configuration. The dimensional ratios between the transistors Ma and Mb are governed by a parameter k of proportionality, with the dimensions of Mb being k times those of Ma. The gate terminal of the transistor Ma has a first parasitic capacitance C1 toward the source terminal, and a second capacitance C2 toward ground. Accordingly, as the potential at the source terminals moves very rapidly, the gate-source voltage drop across the transistor Ma increases rapidly with respect to the steady-state value of a quantity given by the capacitive divider C1-C2.
Thus, when the power transistor M1 is turned on, the current I2 will be far above its steady-state value, and may even exceed the value of the current I1. Therefore, the node N is charged up to a potential Vcc+Vs, and the output from the circuit 10 forces the power transistor M1 to the `off` state, causing a false or undesired switching.
The problem might be circumvented by arranging for the gate-source capacitance C1 to be much higher than the gate-ground capacitance C2. However, this would entail integration of large-size capacitors in the semiconductor, and consequently, pose well-recognized problems in terms of circuit area occupation.
Alternatively, the current I1 could be rendered much larger than the current I2; but this method has a serious drawback in that it introduces asymmetry in the propagation times of the power on/off signals for the power transistor M1.
Other possible solutions are based on highly complicated and expensive circuit structures involving the use of memory elements.

Shift level circuit for a high side driver circuit


A process for determining an end member age of an illite component in an earth sample which contains a diagenetic illite component and a detrital illite component. As a first step, the sample is separated into a plurality of fractions so that the fractions will have different mean ages of illite. Next, the relative percentage of one of the illite components is determined for each fraction. The mean age of total illite in each fraction is determined using potassium-argon age analysis. The determined relative percentages are then correlated with the determined mean ages to generate a linear relationship. The end member age for each illite component can then be determined by using the linear relationship since zero percent of one of the illite components corresponds to the end member age of the other illite component.

In the exploration for oil and gas, it is often desirable to determine the age of clay minerals in sedimentary rocks. This information can be used as an aid to determine the genesis, history, and migration pattern of hydrocarbons, fluids, and minerals in sediments. Since sedimentary rocks often contain illite, considerable effort has been made by geologists to determine the date illite was formed in a rock sample.
Various dating techniques have been suggested. A widely used dating technique is known as the potassium(K)-argon(Ar) dating method. This dating technique is based on the principle that when a K-bearing mineral, such as illite, was formed it contained .sup.40 K, one of three isotopes of potassium. The .sup.40 K then underwent radioactive decay according to a constant decay rate to produce two daughter products, .sup.40 Ca and .sup.40 Ar. Because Ar is an inert element, it is very unlikely to be taken up into newly formed minerals. Therefore, most if not all argon in a mineral is a result of radioactive decay. The most abundant calcium isotope is .sup.40 Ca, and calcium is more abundant than potassium in the earth's crust. For these reasons, age dating is more reliable using the daughter argon isotope than the daughter calcium isotope even though 89% of all .sup.40 K decay produces .sup.40 Ca. The amount of .sup.40 Ar and .sup.40 K in a sample is determined directly with a mass spectrometer and by inference based on measurement of the total potassium content.
The K-Ar dating technique is relatively simple to use if at the time the earth sample was formed it was not contaminated with previously formed argon. Because argon is an inert gas, it escapes easily from molten rock and begins to accumulate only after the rock solidifies and minerals cool. For this reason the initial argon present in molten rock as it forms is generally not a problem in K-Ar dating. When molten magma was deposited on the earth's surface, any argon that was present in the magma would have been lost to the earth's atmosphere. The magma would have been so hot that the argon gas would have escaped. As the magma cooled it crystallized and trapped potassium ions in the crystalline lattice. The .sup.40 K began to decay to .sup.40 Ar and the gaseous .sup.40 Ar was trapped in the crystal lattice. The age of the sample can be easily determined by comparing the amount of potassium to the amount of argon.
The K-Ar dating technique is more difficult to use if the rock has undergone any chemical alteration or post-formational heating (above about 250.degree. C.). Such heating or chemical alteration may cause some or all of the accumulated argon to escape and thus partially or totally reset the K-Ar clock. Because sedimentary rocks have typically not undergone heating above 250.degree. C., application of K-Ar dating to sedimentary rocks does not suffer from this problem. However, when the K-Ar dating technique was first introduced in the 1950s, it was generally believed the technique was not practical for dating illite found in sedimentary rocks because such rocks contain a mixture of "old" and "new" illite.
As sediments undergo heating during burial, new illite is often formed in the rocks, especially in shales. This newly formed illite is called "diagenetic illite". Since illite is rich in potassium, K-Ar dating can be used to determine when the diagenetic illite was formed. However, the resulting age measured using K-Ar dating can be inaccurate because rocks in which the diagenetic illite forms often also contain old illite which is called "detrital illite". The detrital illite may have been carried there by wind, ocean currents, streams, or rivers millions or hundreds of millions of years before the diagenetic illite was formed.
Because the diagenetic illite formed in response largely to temperature, the amount of it and its age are important indicators of the sediment's thermal history. This information is useful in hydrocarbon exploration because it helps establish the time of maturation of the source rock for oil and gas. Knowing the age of the detrital illite can also help in determining the provenance of the sedimentary rock.
A major difficulty in using the K-Ar dating method on an illite sample that contains both diagenetic illite and detrital illite is determining the relative contribution of each illite component. Since diagenetic and detrital illites were formed at different times, K-Ar dating of the sample would give a mean age of all illite in the sample. Since detrital illite can contain much more argon than the more abundant diagenetic illite, the detrital illite may dominate the age value disproportionately.
Determining sedimentary (diagenetic) age using K-Ar dating is further complicated by the fact that different sized particles in the rock seldom have identical proportions of detrital illite and diagenetic illite. Coarser-sized fractions tend to have K-Ar age values greater than the age of the finer-sized fractions.
Efforts have been made to physically separate diagenetic illite from the detrital illite, but such efforts have not been entirely successful. Even the finer-sized fractions appear to contain mixtures of the two illite components. Therefore, the dates obtained using K-Ar dating are often not useful.
A need exists for an improved process for using the K-Ar dating method to determine the age of detrital illite and the age of diagenetic illite in an earth sample that contains both diagenetic illite and detrital illite.

Potassium-argon dating of illite components in an earth sample


A charge image recording medium (RM) comprising a lamination of an electrode (E) and at least one of a light-modulation material layer (PMLQ) and an insulating polymer film or dielectric layer (IL), wherein said light-modulation material layer (PMLQ) comprises a polymer-dispersed liquid crystals film comprising a liquid crystal dispersed in a polymer. The insulating polymer film (IL) may be provided thereon with a thin film (CL) of a fatty acid or a thin film (CL) of a metal salt of a fatty acid.. The light-modulation material layer (PMLQ) comprising a polymer-dispersed liquid crystals film comprising a liquid crystal dispersed in a polymer may also be provided thereon with a thin film (CL) of a fatty acid or a thin film (CL) of a metal salt of a fatty acid.

1. Field of the Invention
This invention relates to a charge image recording medium.
2. Description of the Prior Art
In recent years, a number of imaging devices based on a process using the latent image of electron-charge have been proposed that offer the hope of practical usefulness in image picking-up, image recording, image reproducing and image displaying. An example of such devices is disclosed in U.S. Pat. application Ser. No. 301,324 (filed on Jan. 24, 1989, a C.I.P. of U.S. Ser. No. 139,005), in which an optical image inputted is converted to a latent image of electron-charge, recorded on a recording medium and reproduced. The mechanisms for recording and reproducing, and an example of media proposed in this reference, are illustrated in FIGS. 8, 9 and 5, respectively.
A writing head WH or a reading head RH are necessary for operating the recording and reproducing of a charge image by the use of a charge image recording medium, as will be described later in detail with reference to FIGS. 8 and 9. Use of a light-modulation material at the part having the function of retaining a charge image in a charge image recording medium RM (i.e., a dielectric layer IL in the charge image recording medium RM illustrated in FIGS. 6 and 9) makes a reading head unnecessary at the time of reading. Hence, a recording medium comprising a lamination of an electrode and a layer (a light-modulation material layer) comprised of a light-modulation material is often used as the charge image recording medium RM.
However, since a recording medium may have a great variety of forms as exemplified by a tape, a disk, a sheet and a card, it has not been easy to construct the light-modulation material layer on the charge image recording medium that may have various forms. In particular, it has been difficult to construct the light-modulation material layer on a charge image recording medium having a large area or a charge image recording medium having the form of a tape.
The above difficulty also applies in the case when the light-modulation material used in constituting a light-modulation material layer comprises, for example, a liquid crystal or lithium niobate.
When the part at which a charge image is recorded is constituted of a dielectric layer IL, a charge image can be well recorded in a highly detailed state. In a conventional charge image recording medium RM, however, the charges of a charge image recorded thereon may gradually decrease with lapse of time and it has occurred even that the charge image can be retained only for several hours to several days or so. Thus, it has been sought to provide a charge image recording medium capable of storing a charge image for a long period of time.


A dye composition is provided and includes a non-aqueous dye and an ionic liquid. A dyeing method is provided and includes a process of applying the dye composition to an object, and a process of removing fluidity of the dye composition.

As a method of dyeing a substance with a non-aqueous dye, a dry dyeing method of precipitating a dye from a gaseous phase to a substance such as vacuum deposition, and a wet dyeing method of precipitating a dye from a liquid phase such as a dye solution and a pigment dispersion to a substance have been used. However, vacuum deposition requires a vacuum apparatus, further, the kinds of dyes that can be proof against a high temperature condition to evaporate dyes are limited in number, so that this method does not necessarily have a wide range of application. On the other hand, the drawback of the liquid phase method is that it is necessary to adopt a measure to reduce environmental load such as the equipments for recovering the vapor of solvent since a volatile organic solvent is used. Even when water is used as the medium, a dispersion process for a long time should be taken to finely disperse a non-aqueous dye in water, further, materials other than a dye such as various surfactants and latex polymers must be added as the auxiliary dispersants, so that this method also does not necessarily have a wide range of application.
On the other hand, a salt called an ionic liquid that is liquid at room temperature was reported by Wilkes et al. in 1992 (e.g., see Chemical Communications, p. 965 (1992)). Ionic liquids are incombustible, nonvolatile, can be used safely and repeatedly, and promising in the field of organic synthesis as an environmentally harmonic reactive solvent (e.g., see Ion-Sei Ekitai—Kaihatsu no Saizensen to Mirai-(Ionic Liquid—The Forefront and the Future of Development-), CMC Publishing Co., Ltd. (February, 2003)). In addition, since an ionic liquid has high ionic conductivity, the use in the field of electrochemistry has spread such that the use as the electrolyte of a secondary battery is discussed, and the use as the electrolyte of a dye sensitization solar battery is proposed (e.g., see JP-A-2001-167808 and JP-A-2002-75470).
However, it was not known to apply an ionic liquid to a coating material and a dyeing method.


A semiconductor device having asymmetrically-doped gate electrode and active region and a process of fabricating such a device is provided. According to one embodiment of the invention, a polysilicon layer is formed over the substrate. The polysilicon layer is then implanted with a first dopant to form a doped polysilicon layer. Portions of the doped polysilicon layer are then removed to form at least one gate electrode. Active regions of the substrate adjacent the gate electrode are implanted with a second dopant to form source/drain regions in the substrate. In this manner, the implant used to form the source/drain regions may be decoupled from the implant used to form the gate electrode. This, for example, allows for shallower source/drain regions to be formed without the formation of the depletion layer in the gate electrode.

Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applicability and numerous disciplines. One such silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor.
The principal elements of a typical MOS semiconductor device are illustrated in FIG. 1. The device generally includes a semiconductor substrate 101 on which a gate electrode 103 is disposed. The gate electrode 103 acts as a conductor. An input signal is typically applied to the gate electrode 103 via a gate terminal (not shown). Heavily doped source/drain structures 105 are formed in the semiconductor substrate 101 and are connected to source/drain terminals (not shown). The source/drain structures 105, illustrated in FIG. 1, are lightly-doped-drain (LDD) structures. Each LDD structure includes a lightly-doped, lower conductivity region 106 (hereinafter referred to as LDD region) near the channel region 107 and a heavily-doped, higher conductivity region 104 (hereinafter referred to as source/drain region) typically connected to the source/drain terminal. As illustrated in FIG. 1, the typical MOS transistor is symmetrical, which means that the source and drain are interchangeable. Whether a region acts as a source or drain depends on the respective applied voltages and the type of device being made (e.g., PMOS, NMOS, etc.). Thus, as used herein, the term source/drain structure refers generally to an active region used for the formation of a source or drain.
A channel region 107 is formed in the semiconductor substrate 101 beneath the gate electrode 103 and separates the source/drain structure 105. The channel is typically lightly doped with a dopant of a type opposite to that of the source/drain structure 105. The gate electrode 103 is generally separated from the semiconductor substrate 101 by an insulating layer 109, typically an oxide layer such as SiO.sub.2. The insulating layer 109 is provided to prevent current from flowing between the gate electrode 103 and the source/drain structure 105 or channel region 107.
In operation, an output voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode 103, a transverse electric field is set up in the channel region 107. By varying the transverse electric field, it is possible to modulate the conductance of the channel region 107 between the source region and the drain region. In this manner, an electric field controls the current flow through the channel region 107. This type of device is commonly referred to as a MOS field-effect-transistor (MOSFET).
One important step in the manufacture of MOS devices is the formation of the gate electrode and source/drain structures. These structures are typically formed by first depositing, usually through chemical vapor deposition (CVD), a layer of polysilicon over the entire substrate. The polysilicon layer is then patterned using a mask and etched, typically through a dry etch process, to form the gate electrode. An LDD implant is then performed to form the LDD regions 106. Spacers 108 are then formed on the gate electrode 103. Using the spacers for alignment, a source/drain implant is performed to form the source/drain regions 104 and to dope the gate electrode 103. The substrate 101 is then annealed to activate the dopants in the source/drain structures 105 as well as the dopant in the gate electrode 103.
Semiconductor devices, like the one described above, are used in large numbers to construct most modern electronic devices. In order to increase the capability of such electronic devices, it is necessary to integrate even larger numbers of such devices into a single silicon wafer. As the semiconductor devices are scaled down (i.e., made smaller) in order to form a larger number of devices on a given surface area, the structure of the devices and fabrication techniques used to make such devices must be altered. The depth of the source/drain region is an important dimension which must be scaled down as the device structure is made smaller. However, as the source/drain junction depth is reduced, complexities arise in the fabrication process.

Process of fabricating a semiconductor devise having asymmetrically-doped active region and gate electrode


A rack device with a height adjustable depending on the cargo carried and the size of the vehicle used. The rack device includes a pair of end portions each comprising a first bar and a second bar coupled to and extending upwardly away from the first bar. A third bar is coupled to and extends away from the second bar. A fourth bar is coupled to and extends upwardly away from the third bar. A fifth bar is removably coupled to and extends between the second bars of each of the end portions. A sixth bar is removably coupled to and extends between the first bar of each of the end portions.

1. Field of the Invention
The present invention relates to truck racks and more particularly pertains to a new rack device for adjusting the height of the rack depending on the cargo being carried and the size of the vehicle being used.
2. Description of the Prior Art
The use of truck racks is known in the prior art. More specifically, truck racks heretofore devised and utilized are known to consist basically of familiar, expected and obvious structural configurations, notwithstanding the myriad of designs encompassed by the crowded prior art which have been developed for the fulfillment of countless objectives and requirements.
Known prior art includes U.S. Pat. No. 4,405,170; U.S. Pat. No. 5,143,415; U.S. Pat. No. 5,806,905; U.S. Pat. No. 4,659,131; U.S. Pat. No. 4,138,046; and U.S. Pat. No. Des. 398,284.
While these devices fulfill their respective, particular objectives and requirements, the aforementioned patents do not disclose a new rack device. The inventive device includes a rack for a bed of a pickup truck. The pickup truck includes a front side, a back side and a pair of longitudinal sides. The rack comprises a pair of end portions. Each of the end portions is comprised of a first bar that includes a first end and a second end. The end portion also includes a second bar that is integrally coupled to and extending upwardly away from the second end of the first bar. There is a third bar that is integrally coupled to and extending away from the second bar. The third bar is orientated generally parallel to the first bar. There is also a fourth bar that is integrally coupled to and extending upwardly away from a free end of the third bar. The fourth bar is orientated generally parallel to the second bar. Additionally there is a fifth bar that is removably coupled to and extending between the second bars of each of the end portions. There is also a sixth bar that is removably coupled to and extending between the first bar of each of the end portions. The sixth bar includes a first end and a second end.
In these respects, the rack device according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of adjusting the height of the rack depending on the cargo being carried and the size of the vehicle being used.


There is provided bonding material having a Young's Modulus after hardening of not less than 20% of articles to be bonded, and an average linear coefficient of thermal expansion after hardening of not more than 70% of the articles to be bonded. This bonding material can suppress deformation of a honeycomb segment due to thermal stress to be generated by a bonding material layer and can suitably be used at the time of manufacturing exhaust gas trapping filters capable of reducing the generation of defects such as a crack, and above all, a diesel particulate filter (DPF) for trapping particulate matter (particulates) in exhaust gas from the diesel engine.

A honeycomb structure is built into an exhaust system of a diesel engine and the like to be used as a trapping filter for exhaust gas, for example, as a diesel particulate filter (DPF) to trap and remove particulate matter (particulates) contained in an exhaust gas from the diesel engine and the like.
Such a honeycomb structure has a structure in which a plurality of cells functioning as flow channels of fluid partitioned and formed by porous partition wall made of, for example, silicon carbide (SiC) are disposed in parallel with one another in the direction to the central axis. Further, ends of adjacent cells are alternately plugged (in a checkered pattern). That is, in one cell, one end is open, and the other end is plugged, and in another cell adjacent to this cell, one end is plugged, and the other end is open.
Because of such a structure, the exhaust gas allowed to flow into predetermined cells (inflow cells) from the end portions on one side is allowed to flow out through the adjacent cells (outflow cells) by allowing the exhaust gas to pass through the porous partition walls, and when passing the exhaust gas through the porous walls, the particulate matter (particulates) in the exhaust gas is trapped by the partition walls, so that the purification of the exhaust gas can be performed.
To continuously use such a honeycomb structure (filter) over a long period of time, a filter must be regenerated. That is, to remove an increase in pressure loss by the particulates accumulated with time inside the filter, the particulates accumulated inside the filer with time must be burnt and removed. At this regeneration time of the filter, there has been a problem that a large thermal stress is generated to cause a defect such as a crack and breakage. Complying with the request for improvement of thermal shock resistance against such a thermal stress, there has been proposed a honeycomb structure of a split structure allowed to have functions to disperse and relax the thermal stress by integrally bonding a plurality of honeycomb segments by a bonding material layer, thereby enabling it to improve the thermal shock resistance to some extent. The honeycomb structure of such a split structure is formed such that each has a shape to configure a part of the entire structure, and, at the same time, a plurality of honeycomb segments having a shape to configure the entire structure by being fitted in the direction perpendicular to the central axis are integrally bonded by the bonding material layer and are formed so as to become a predetermined shape such as a circle and the like in the entire cross-sectional shape cut along a plane perpendicular to the central axis, and after that, its outer peripheral surface is covered by a coating member.
However, in recent years, the filter has an increasing demand for a large size, and the thermal stress generated at the generation time is also increasing, and therefore, to inhibit the above described defect, the improvement of thermal shock resistance as a structure has comes to be strongly desired. Above all, the bonding material layer for integrally bonding a plurality of honeycomb segments is desired to realize a honeycomb structure excellent in thermal shock resistance by realizing an excellent stress relaxation function and bonding strength.
Addressing such a problem, a ceramic structure (honeycomb structure) has been disclosed (see Patent Document 1) in which, by adding inorganic fibers and organic binders to a sealing member (bonding material layer), generation of migration in the process of drying and hardening is suppressed, thereby controlling a development of the above described defect and aiming at the improvement in durability.
Further, there has been disclosed a honeycomb structure (use of a low Young's Modulus bonding material) satisfying either one of the conditions that the Young's Modulus of the bonding material layer between the honeycomb segments is made not more than 20% of the honeycomb segment material or that the material strength of the bonding material layer is made smaller than the material strength of the honeycomb segments (see Patent Document 2).
However, in the sealing member (bonding material layer) used for the ceramic structure (honeycomb structure) disclosed in the Patent Document 1, there has been a problem that securement of a bonding strength between the segment and bonding material layer boundary surface and securement of a stress relaxation function of the bonding material layer itself are hard to be compatible in the uniform system realized by the mutual inter-twisting of the component inorganic fibers and organic binders.
Further, though the low Young's Modulus of the bonding material forming the bonding material layer disclosed in Patent Document 2 is effective in that the thermal stress and thermal deformation generated between the honeycomb segments are relaxed, when the bonding material has high porosity due to the low Young' Modulus, there has been a problem that a bonding strength between the honeycomb segments becomes insufficient, and no sound honeycomb segment bonded body can be obtained.
Patent Document 1: JP-B-3121497
Patent Document 2: JP-A-2001-190916

This patent is subject to a terminal disclaimer.

Bonding material, process for producing the same, and honeycomb structure made with the same


In a system wherein one or more controllable camera(s) and one or more monitor(s) for displaying video information received from the camera(s) are connected to each other through a communication device, the states of all the cameras can be always understood at any monitor. Map management server software is provided to receive notification(s) of camera state information by all the cameras with the predetermined device, and to transmit the camera state information to all the monitors.

1. Field of the Invention
The present invention relates to a communication apparatus, a storage medium, a camera and a processing method.
2. Related Background Art
A video transmission system has been proposed in which, for example, plural video cameras and computers are located inside a building, and these video cameras and the computers are networked through communication lines, thereby realizing video transmission among plural desired points and interactive communication by video and audio.
In this video transmission system, a user of the computer at one point (local computer) can remote-control the video camera at a desired remote point and display the video taken by the remote-controlled video camera on the screen of the user's local computer.
Further, in a video transmission system capable of remote-controlling a remote video camera, especially, as the number of the video cameras to be remote-controlled increases, it is necessary for the user to easily understand where each video camera is located. Thus, a technique which superimposes a camera symbol representing the location of each video camera on an image representing a map has been proposed. Further, a technique which represents the direction of picture taking of the actual video camera by displaying the direction/orientation of the camera symbol has been proposed.
In the above system, there is a case where a video camera which is represented by a camera symbol superimposed on the map is operated and controlled by a user at a remote location. In this case, as long as the terminal which utilizes that map does not obtain a state update of the video camera concerned, a problem exists in that the state of the camera symbol does not correspond to the state of the actual video camera.

Communication apparatus, storage medium, camera and processing method


The present invention is a knob which attaches to the switch post of a push/pull switch. The knob selectively disengages from the switch post as the knob is inadvertently impacted, thereby isolating the push/pull switch from the impacting force. The knob moves independently of the switch post and contacts the housing supporting the switch. Consequently, the force of impact is directed to the housing through the body of the knob and very little force is directed to the switch.

Push/pull switches are electrical switches that operate by being pushed inwardly or pulled outwardly along a central axis. Such push/pull switches are commonly used to turn power on and off in a variety of devices such as radios, televisions, computer monitors and the like. Many such push/pull switches also have secondary control functions governed by the rotation of the switch knob around its central axis. For example, such a knob may be pulled outwardly to provide power to a television, pushed in to turn off the television, and rotated around its central axis to control a desired parameter such as the volume of the television.
Since push/pull switches must be pushed, pulled, turned and otherwise manipulated by an operator, such switches typically have large knobs. The large knobs promote the engagement of the switch by an operator's fingers, thereby making the switch easy to locate and operate. When push/pull switches are used on portable devices, the large size of the knob produces disadvantages. Portable devices experience many impacting forces as the device is carried or set into position for use. Since the knobs of push/pull switches are relatively large, many of the impact forces incurred act directly upon the knob of the switch. With many prior art switches, forces that impact the knob are directly transferred to the components of the switch. Consequently, the switches often break rendering the overall device inoperative until the switch can be replaced or repaired.
It is therefore an object of the present invention to provide a knob for a push/pull switch that does not transfer the forces of impact to the components of the switch, thereby increasing the overall reliability and resistance to shock of the device containing the switch.


A data storage system is provided for storing and retrieving data. The system includes: a conveyor system for carrying a plurality of data cartridges; and, a plurality of independently operable drive mechanisms, each one having a data cartridge transfer mechanism. The conveyor system is adapted to position a selected one of the data cartridges to the transfer mechanism of a selected one of the drive mechanisms. When so positioned, the transfer mechanism removes the data cartridge and inserts it into the drive mechanism for processing (i.e., data may be written onto the data cartridge or data may be read from the data cartridge). The data cartridge may then be withdrawn from the drive mechanism after processing and returned to the conveyor system. Because each one of the drive mechanisms is operable independently of the other drives and each drive has its own transfer mechanism, more than one data cartridge may be processed during the same time period, or during overlapping time periods.

This invention relates generally to data storage/data retrieval systems and more particularly to systems of such type which are adapted to store a plurality of magnetic data cartridges in a single housing, or data library, and access a selected one, or ones, of the data cartridges to store data on such one, or ones of such data cartridges and/or retrieve data previously stored on such one, or ones of the data cartridges.
As is known in the art, large amounts of data may be stored on data cartridges, such as tape cassettes, compact disc (CD) read only memories (ROMs), digital linear tape cartridges, and helical tape cartridges. Such data storage systems may be used, for example, as a system for backing up data used in a local area network of personal computers. The amount of data to be stored may require more than one standard data cartridge. A housing, or library to house a plurality of data cartridges has been suggested. Many of these systems, or libraries, however, take up considerable space because the mechanism used to retrieve one of the cartridges uses a two-dimensional orthognal configuration, such as described in U.S. Pat. No. 4,812,629 (O'Neil et al.), a cylindrical grid configuration, such as described in U.S. Pat. No. 5,143,193 (Geraci), or a circular confirmation, such as described in U.S. Pat. No. 4,287,541 (Tanahashi et al.).
Other configurations are shown in: U.S. Pat. No. 4,063,294 (Burkhart); U.S. Pat. No. 3,774,916 (Namba); U.S. Pat. No. 3,807,741 (Uemura); U.S. Pat. No. 4,361,858 (Chambers); and, U.S. Pat. No. 4,510,539 (Young).

Data storage and retrieval system having a data cartridge conveyor with independently operable drives each with an associated cartridge transfer mechanism


An airbed with an integral sleeve. After deflation of the airbed, the airbed is rolled or folded into a tight formation, and the sleeve is extended around the airbed for storage. The sleeve may be a flat fabric material that is attached to a seam of the airbed, for example by welding. The sleeve includes drawstrings or cords for tying and tightening the sleeve around the airbed. A handle may also be provided for carrying the stored airbed once the sleeve is in place.

An airbed is a large rectangular rubber or plastic (e.g., vinyl) bag that is filled with air so that it may be used as a bed. Airbeds are well known in the art and have proven themselves to be very useful. On the one hand, an inflatable airbed may be deflated and folded to store the airbed in a closet or basement. On the other hand, when guests arrive or when the owner of the airbed takes a trip to a place where there is no bed, the airbed may be inflated and may be used as a bed.
An air mat is similar in construction to an airbed, but is used as a float so that an individual may lie on the air mat in the water. Both products fall under the broad category of "inflatable" products. Other nonlimiting examples of inflatable products include rafts, inflatable furniture, inflatable pools, and inflatable boats.
One problem often encountered with inflatable products such as airbeds is that they are difficult to store. For example, often, an airbed is shipped in a box, and storing the airbed in the box is difficult, if not impossible. When the airbed is shipped, there is almost no air at all in the airbed, and it is efficiently folded so as to fit in the box. A user may find it difficult to remove all air from the airbed, and/or replicate the folding pattern used in shipping of the product. Thus, the user typically folds the airbed as tightly as possible and extends it partly into the box, with a portion hanging out. Even if the user can get the airbed back into the box, the box may become crushed, torn, broken, or otherwise damaged with use. If a box is not used, the user must store the airbed in a different manner, such as in a separate bag or using ties.


Provided are a dual-mode display device and a method of manufacturing the same. The device includes a lower substrate, an upper substrate facing the lower substrate, a thin-film transistor portion between the upper substrate and the lower substrate, a first anode on one side of the thin-film transistor portion, a first cathode between the first anode and the upper substrate, an organic light-emitting layer between the first cathode and the first anode, a second anode on the other side of the thin-film transistor portion, a second cathode between the second anode and the upper substrate, or the second anode and the lower substrate, and a optical switching layer between the second cathode and the second anode.

The inventive concept disclosed herein relates to a display device and a method of manufacturing the same, and more particularly, to a reflective and self-light emitting dual-mode display device and a method of manufacturing the same.
As modern society develops toward the information age, the importance of a flat panel display (FPD) industry is increasing. The FPD may display pictures by controlling the intensities of transmitted lights or self-emitted lights according to image control signals. The FPD may include a liquid crystal display (LCD) and an organic light-emitting display (OLED) as representative examples.
The LCD may be classified into a transmissive type LCD and a reflective type LCD. The transmissive type LCD may transmit and modulate a white light generated from a backlight to two polarizing plates and a liquid crystal layer. The white light may represent a color passing through a color filter layer. The transmissive type LCD is being widely used for mobile portable equipment, notebooks, computer monitors, TVs, etc., because it may be driven at low voltages. The transmissive type LCD may have low light efficiency because it uses only part of white lights that have been transmitted to the polarizing plate and the color filter layer. However, the backlight has a drawback of increasing the power consumption of the transmissive type LCD. Thus, research and development of the reflective type LCD without the backlight are being actively carried out. The reflective type LCD reflects external lights in a bright environment to represent images.
The OLED is taking center stage as a low-power self-light emitting optical display. The OLED includes a plurality of substrates facing each other, a plurality of electrodes between the substrates, and organic light-emitting materials between the electrodes. The substrates may include a flexible substrate such as a plastic substrate. Thus, the OLED may implement a stretchable display. The organic light-emitting material forms an exciton, a hole and electron pair that is supplied through the electrodes. The exciton is emitted as a light in the organic light-emitting material. Thus, the OLED represents images with self-light.
Recently, the reality is that a need for a dual-mode display device in which the OLED and the reflective type LCD are combined is increasing. The reason is that the dual-mode display device may adapt to external environments and realize ultra power saving.

Dual-mode display device and method of manufacturing same

ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE


A reception circuit includes: an AD converter that outputs digital data in accordance with an input signal; a correction circuit that corrects nonlinearity of the AD converter; and an equalization circuit that equalizes the corrected digital data, wherein the correction circuit includes: a conversion table used to convert digital data output from the AD converter; and a correction amount computation circuit that creates the conversion table from the output data of the AD converter and the output of the equalization circuit. The correction amount computation circuit creates the conversion table so that there is no dependence between the ADC output value of the AD converter and the estimation result by the equalization circuit for the ADC output value.

FIG. 1 is a diagram illustrating a schematic configuration of a high-speed signal transfer system. As illustrated in FIG. 1, the signal transfer system includes a transmission circuit 1, a transfer line 2 and a reception circuit 3. In the transmission circuit 1, low-speed parallel data is converted into serial data in a multiplexer (MUX) 11 and the serial data is output to the transfer line 2 by a driver 12 having an output impedance the same as the characteristic impedance of the transfer line 2. The serial data is input to the reception circuit 3 via the transfer line 2. An input reception waveform received by the reception circuit 3 is deteriorated by the characteristics of the transfer line 2. Specifically, the high-frequency component is lost and the waveform is dulled.
Data to be transmitted is two-value data of "0's" and "1's" (or "−1" and "+1") and when the degree of deterioration through the transfer line 2 is low, the input reception waveform for the serial data indicated by a string of "0's" and "1's" on the lower side is such that as illustrated in FIG. 2A. With this received signal waveform, it is possible to correctly reproduce the received data by setting a threshold level to a level indicated by the broken line and by determining the waveform with a comparator.
However, when the transfer line 2 is long or the frequency of the transmission data is very high, the degree of deterioration through the transfer line 2 is high and the input reception waveform for the serial data indicated by a string of "0's" and "1's" on the lower side is such that as illustrated in FIG. 2B. With such a received signal waveform, it is not possible to correctly reproduce received data by determining the waveform using only one comparator. In order to deal with this, the signal level is detected in accordance with a clock of the received data as illustrated in FIG. 2B and then the received data is reproduced correctly.
Because of this, as illustrated in FIG. 1, the reception circuit 3 samples the received signal (analog waveform) and digitizes the signal using an analog/digital converter (ADC) 31 arranged at the input part. An equalization circuit (EQ) 32 shapes the waveform (equalization processing) so as to compensate for the deterioration of waveform through the transfer line. The received data that is shaped is determined to be "0" or "1" and the determination result is converted from serial data into parallel data by a decision latch/demultiplexer (D/L DMUX) 33. A clock signal is necessary for sampling in the ADC 31 and processing in the equalization circuit 32. A clock recovery unit (CRU) 34 reproduces a data clock from the received data output from the equalization circuit 32. In the circuits to be explained below, the CRU 34 is also provided, however, an explanation is not given for the sake of simplification and it is not illustrated schematically.
FIGS. 3A and 3B are diagrams illustrating a configuration of an embodiment of the equalization circuit 32 called a decision feedback equalizer (DFE). FIG. 3A illustrates a conceptual diagram and FIG. 3B illustrates a specific circuit configuration. If a transfer function of the transfer line 2 is assumed to be H (z) as illustrated in FIG. 3A, adjustment is made so that the transfer function of a DFE 37 is 1−H (z). One sample received signal is H (z) and if the output 1−H (z) of the DFE 37 is added to a received signal H (z) by an adder 35, a signal without deterioration is output as a result and this output is determined by a comparator 36. Due to this, transmission data dn may be received correctly. Specifically, in order to sequentially correct the influence of the previous sample data, the sample data ahead by one sample is delayed by one sampling period and the sample data ahead by two samples is delayed by two sampling periods, and in this manner, the sample data is delayed sequentially up to that ahead by a certain number of samples and the delayed data is multiplied by a coefficient in accordance with the degree of influence and added to input data.
As illustrated in FIG. 3B, the equalization circuit 32 includes the DFE 37 having a plurality of multipliers hn0 to hnm, a plurality of the adders 35, the comparator 36, a switch 38 that switches between feedback of data having been subjected to equalization processing and feedback of training data, a comparator 39 that binarizes data to be fed back, a plurality of delay units 40 that generate data to be applied to hn1 to hnm after delaying the binarized feedback data, a subtracter 41 that calculates a difference between the data having been subjected to equalization processing and the binarized feedback data and generates an amount of error en, and a coefficient update part (e.c. LMS (Least-mean-square)) 42 that updates the coefficients of the multipliers hn0 to hnm so that the amount of error is small based on the amount of error en. The multiplier hn0 multiplies the data output from the ADC 31 by a certain coefficient and outputs the data and the multipliers hn1 to hnm multiply the previous sample data that is delayed by a certain coefficient and output the data, and the data is added by the adder 35.
H (z) is a z function and because of the limitations of hardware, normally, the terms beyond a certain finite term are truncated. As the coefficients of the multipliers hn0 to hnm, the values acquired by applying the LMS algorithm are set here; however, there may be a case where fixed values are set in advance. The coefficients of the multiplier represent the frequency characteristic of the transfer line. The amount of error, which is an input to the coefficient update part 42, is an error from an ideal waveform that remains even after the waveform shaping using the coefficients. The magnitude of the error represents the quality of the shaped waveform.
The equalization circuit is described in, for example, Japanese Laid-open Patent Publication No. 2000-224080, and therefore, no further explanation is provided.
There are various types for the ADC, however, an ADC that may be used generally in high-speed signal transfer as high as Giga bits/sec is limited to a flash type at present. In a flash type ADC, between a high-side reference potential and a low-side reference potential, a resistor string (ladder resistor) is provided and a divided potential, which is the reference potential divided, is generated at the connection node. Each of a plurality of comparators compares a voltage of an input signal (input voltage) with the divided potentials, respectively. When the input voltage is smaller than a certain divided potential, the output of the comparators located on the upper side of the comparator that makes a comparison with the divided potential is "0" and the comparators located on the lower side of the comparator, including the comparator, is "1", which is a so-called thermometer manner, and when the outputs of the plurality of comparators are encoded by an encoder, a digital output in the binary form in accordance with the level of the input voltage is obtained. For an N-bit ADC without an interpolation technique, (2N−1) comparators are required.
The input/output characteristics of an ADC are not linear but nonlinear because of variations in the size of its circuit constituent component or in threshold voltage Vth. FIG. 4 is a diagram explaining the nonlinearity of the ADC. When the ADC exhibits the characteristic illustrated by the stepwise solid line, the input/output characteristics are illustrated by the broken line, different from the input/output characteristics illustrated by the alternate long and short dash line.
In order for the equalization circuit to perform equalization processing to correctly receive data, it is necessary for the input/output characteristics of the ADC to include linearity.
One of the reasons for that the input/output characteristics of the ADC include nonlinearity is the offset of the input part. Because of this, the ADC circuit in the conventional example incorporates an offset voltage generation circuit and an offset cancel circuit configured by a switch that operates with a clock in order to alleviate the degree of nonlinearity.
Japanese Laid-open Patent Publication No. 2003-536342 describes a method of correcting nonlinearity by providing a conversion table used to convert an output of an ADC and creating the conversion table based on the already-known calibration signal to be input from a reference signal input terminal.

Reception circuit, method of creating AD converter conversion table of reception circuit, and signal transfer system


The interconnection system of the present invention comprises an interconnection film formed by chemical vapor deposition, wherein the interconnection film comprises an upper layer and a lower layer in which the concentrations of impurities are different. The method of producing an interconnection film comprising an upper layer and a lower layer by chemical vapor deposition using a single chamber, comprises: a lower layer forming step of depositing the lower layer in a recesses by evacuating the chamber and by injecting a reactant gas into the chamber; a cleaning step of subsequently reducing the partial pressure of impurities which are dissociated from the reactant gas; and an upper layer forming step of subsequently depositing an upper layer onto the lower layer by injecting a reactant gas into the chamber.

The present invention relates to an interconnection system formed by chemical vapor deposition (CVD) and a method for producing the same.
This application is based on Japanese Patent Application No. Hei 10-65781.
In the manufacturing of semiconductor circuits, an interconnection film is formed on a semiconductor substrate to connect active and passive elements.
The interconnection film is manufactured, in general, by a sputtering process in which particles are produced in a vacuum and are deposited onto the substrate, forming the thin film.
In recent years, as integration of circuits has progressed rapidly, aspect ratios of contact holes and through holes have increased, and the sputtering process is often unsatisfactory and ineffective to fill or plug the holes. There is a need to develop another process for manufacturing an interconnection film.
In addition to the sputtering process, chemical vapor deposition (CVD) has been found to be a convenient and effective process for forming interconnection films.
This process usually involves nucleating tungsten in holes (recesses) extending through an insulative layer, depositing a film to plug holes based on the tungsten nucleation, and depositing an upper layer onto the plugging film.
To performing the step of forming the upper layer onto the plugging film after plugging the holes in the insulative layer with tungsten film, a single-wafer type tungsten CVD device utilizes, in general, a single chamber.
The process for depositing the tungsten film using the single-wafer type tungsten CVD device involves introducing WF6 as a reactant gas to deposit the film plugging the holes, and subsequently introducing WF6 into the chamber to deposit the upper tungsten interconnection film onto the plugging film.
The present inventor has found, based on measurements of the warp of the semiconductor substrate using a stress measuring device, that stress occurs on the interconnections of the semiconductor substrate. The reflectance on the surface of the film measured by a reflectometer is low, and irregularities are detected on the surface of the film with the decreased reflectance by a SEM (scanning electron microscope).
After technically analyzing the above problem, the present inventor has reached the conclusion that when the semiconductor substrate warps due to the stress on the interconnections, the surface smoothness of the film which is to be a base for elements formed on the substrate is degraded, resulting in undesirable effects on the characteristics of the manufactured semiconductor device.
The reduction of the reflectance is caused by the irregularities on the surface of the upper interconnection film, which make the film thickness uneven, and in the following etching process residues or thinning may occur in the interconnection film, which may cause short-circuits.
The technical analysis by the present inventor shows that these problems are caused by fluorine which is dissociated from WF6 and contaminates the interconnection film.
The Japanese Patent Application, First Publication No. Hei 7-111253 discloses a technique for depositing a tungsten film onto an insulative layer, which involves stopping supply of a reactant gas between the first and second steps while cleaning the surface of the film by flowing only a carrier gas.
This technique, however, merely cleans the surface of the film and does not control the concentration of the impurities, and it is therefore impossible to prevent the stress on the interconnection film and the reduction of the reflectance due to the impurities in the film. The problems in the background process for forming the interconnection film using the CVD remain.
It is therefore an object of the present invention to provide an interconnection system and a method for producing the same, which can avoid contamination of impurities dissolved from a reactant gas into an interconnection film, and which can improve the performance of a manufactured semiconductor device.
In order to accomplish the above object, the interconnection system of the present invention comprises an interconnection film formed by chemical vapor deposition, wherein the interconnection film comprises an upper layer and a lower layer in which the concentrations of impurities are different.
The concentration of the impurities in the upper layer is less than the concentration of impurities in the lower layer. Preferably, the concentration of the impurities in the upper layer is in a range of {fraction (1/7)} to ⅕ of the concentration of the impurities in the lower layer. The impurities in the interconnection film are components dissociated from a reactant gas in a deposition process of the interconnection film. Increasing stress and reduced reflectance of said interconnection film are results of the impurities.
The interconnection film is formed by a two step process which involves depositing the lower layer and subsequently depositing the upper layer thereon. The lower layer fills a recess, and the upper layer is formed onto the lower layer.
The interconnection film is formed of tungsten using of WF6 a reactant gas. The tungsten interconnection film contains the impurities of fluorine dissociated from the WF6 gas. The concentration of the fluorine in the upper layer is in a range of {fraction (1/7)} to ⅕ of the concentration of the fluorine in the lower layer.
In another aspect of the present invention, a method for producing an interconnection film comprising an upper layer and a lower layer by chemical vapor deposition using a single chamber, comprises: a lower layer forming step of depositing the lower layer in a recess by evacuating the chamber and by injecting a reactant gas into the chamber; a cleaning step of subsequently reducing a partial pressure of impurities which are dissociated from the reactant gas; and an upper layer forming step of subsequently depositing an upper layer onto the lower layer by injecting a reactant gas into the chamber.
The cleaning step comprises reducing the concentration of the impurities in the upper layer. The upper layer and the lower layer are made of the same materials. The concentration of the impurities in the upper layer is in a range of {fraction (1/7)} to ⅕ of the concentration of the impurities in the lower layer.
In another aspect of the present invention, a method for producing an interconnection film comprising an upper layer and a lower layer by chemical vapor deposition using a single chamber, comprises: a lower layer forming step of depositing the lower layer in a recess, where tungsten is nucleated, by evacuating the chamber and by injecting a WF6 reactant gas into the chamber; a cleaning step of subsequently reducing a partial pressure of fluorine which is dissociated from the WF6 reactant gas and stays in the chamber; and an upper layer forming step of subsequently depositing an upper layer onto the lower layer by injecting a WF6 reactant gas into the chamber.
The cleaning step comprises reducing the concentration of the fluorine in the upper layer. The concentration of the fluorine in the upper layer is in a range of {fraction (1/7)} to ⅕ of the concentration of the fluorine in the lower layer. The ratio of the flows of the reactant gases in the lower layer forming step and in the upper layer forming step is in a range of approximately 1:0.25 to 1:0.5.
The cleaning step may include injecting only a replacement gas into the chamber. In the cleaning step, the replacement gas is an inert gas or a reducing gas, and the degree of vacuum in the chamber is in a range of 102 to 10xe2x88x922 Torr. The cleaning step may include evacuating the chamber. In the cleaning step, the degree of vacuum is in a range of 10xe2x88x921 to 10xe2x88x923 Torr. The cleaning step may include both evacuating the chamber and injecting a replacement gas into the chamber. In the cleaning step, the degree of vacuum in the chamber is in a range of 10xe2x88x922 to 10xe2x88x921 Torr.
According to the present invention, stress on the interconnection film and reduction of the reflectance can be prevented because the interconnection film is formed while the concentration of the impurities in the upper layer is reduced.
Further, the cleaning process is performed between the lower layer forming step and the upper layer forming step, and the steps are performed consecutively, enhancing process efficiency.

CVD METHOD FOR PRODUCING AN INTERCONNECTION FILM BY DEPOSITING A LOWER LAYER TO FILL A RECESS PERFORMING A CLEANING STEP TO REMOVE DISSOCIATED REACTANT GAS, AND CONSEQUENTLY DEPOSITING AN UPPER LAYER THAT HAS A SMALLER IMPURITY CONCENTRATION THAN THE LOWER LAYER


An image forming device includes a photoconductive body, an exposure unit configured with a plurality of light emitting elements aligned in a predetermined direction, the exposure unit being adopted to expose the photoconductive body to light emitted by the light emitting elements, a frame configured to support both sides of the exposure unit in the predetermined direction, the frame having a reference portion configured to position the exposure unit in the predetermined direction in contact with an end of the exposure unit in the predetermined direction, and a pressing member provided to one of the frame and the exposure unit, the pressing member being configured to press the end of the exposure unit against the reference portion.

1. Technical Field
The following description relates to one or more image forming devices configured to perform an exposure operation with an LED head having a plurality of LEDs.
2. Related Art
In general, an image forming device is configured to form a desired image on a sheet by exposing a charged photoconductive drum to light to form an electrostatic latent image on the photoconductive drum, supplying developer to the electrostatic latent image to form a developer image, and transferring the developer image onto the sheet. As such an image forming device, a device has been known that includes an LED head with a plurality of LEDs for exposing the photoconductive drum to light and a pair of main body frames adopted to support both ends in a longitudinal direction of the LED head (in which the LEDs are aligned) (see Japanese Patent Provisional Publication No. SHO61-95956).

Image forming device with exposure unit and pressing member


A circuit comprising a clock generator and a state machine. The clock generator may be configured to generate an output clock signal in response to (i) a first enable signal and (ii) a second enable signal. The state machine may be configured to generate the second enable signal in response to a first and a second control signal.

The present invention relates to memories generally and, more particularly, to circuits, architectures, and methods for generating a periodic signal in a memory.
First-In First-Out (FIFO) memories are used to provide a temporary buffer or storage between two communication devices running asynchronously. In FIFOs with bus matching capabilities, data can be written to and read from the FIFO in different data sizes and frequencies, depending on a particular bus mode of operation. For example, a 36-bit wide data word can be delivered in the form of a byte (i.e., x9), a word (i.e., x18) or a long word (x36) bus mode. Referring to FIG. 1a, a byte 10, a word 12 and a long word 14 are shown. The byte 10 is shown having bits from 0 to 8. The word 12 is shown having bits from 0 to 17. The long word 14 is shown having bits from 0 to 35.
Referring to FIG. 1b, a FIFO 16 is shown receiving a number of long words 14a-14n and presenting a number of bytes 10a-10n, a number of words 12a-12n and a long word 14i. The number of bytes 10a-10n, the number of words 12a-12n and the long word 14i are shown grouped so that a x36 FIFO is implemented. The FIFO 16 has an output 18 that presents status flags indicating the various parameters (i.e., fullness or emptiness) of the FIFO 16. The FIFO 16 also has an input 20 that receives a control signal BM and a second control signal SIZE that control the bus matching and bus sizing, respectively.
FIFOs often have write flag counters and read flag counters to keep track of the number of long words written to (i.e., loaded) and read from (i.e., unloaded) the FIFO. The flag counter must therefore be synchronized with the particular bus mode. In particular, the flag counter should only be incremented when an entire 36-bit operation is finished loading or unloading. The flag counter should increment (i) every cycle if the data packet is in long word form, (ii) every 2 cycles if the data packet is in word form and (iii) every 4 cycles if the data packet is in byte form.
One conventional approach to implementing the flag counter incrementer would be to use a divide-by-2 and a divide-by-4 flag counter, depending on the particular bus mode. However, such an implementation would have the disadvantage of having a slow operation time and/or consume a large amount of chip area. FIG. 2 shows a circuit 30 illustrating such an approach.
Another conventional approach to implementing the flag counter incrementer would be to use a state machine to re-generate a flag bus-matching clock. However, such an implementation would have the disadvantage of having a slow operation time. FIG. 3 shows a circuit 40 illustrating such an approach.
The present invention concerns a circuit comprising a clock generator and a state machine. The clock generator may be configured to generate an output clock signal in response to (i) a first enable signal and (ii) a second enable signal. The state machine may be configured to generate the second enable signal in response to a first and a second control signal.
The objects, features and advantages of the present invention include providing a flag counter incrementer that may adapt to a particular bus mode that may (i) have a fast operation time; (ii) consume a minimum amount of chip area; (iii) allow dynamic bus-matching re-configuration during operation without requiring a master reset of the FIFO; and/or (iv) transceive a data stream in the form of byte (e.g., 9 bit), word (e.g., 18 bit) or long word (e.g., 36 bit).

Circuits, architectures, and methods for generating a periodic signal in a memory


An upper slewing body includes a rear wall portion covering an engine room from a rear side, a bottom plate disposed so as to cover the engine room from a lower side and having an exhaust opening, and a pair of vertical plates standing upright on the bottom plate. A rear end portion of the vertical plate has proximate rear end surfaces disposed adjacent to the rear wall portion and a cutout portion formed by recessing the rear end surface of the vertical plate toward the front side with respect to the proximate rear end surfaces. A distal end portion of a tail pipe is introduced between the vertical plates and through the cutout portion from the outer position of the vertical plates and extends along the exhaust opening in a state where the distal end portion of the tail pipe faces the exhaust opening.

1. Technical Field of the Invention
The present invention relates working machines such as a hydraulic shovel, and among them, more particularly, to a working machine of a model in which gas is discharged through an exhaust opening formed in a floor wall portion that covers an engine room from a lower side.
2. Description of the Background Art
In general, in a working machine, an exhaust opening is formed in an upper wall portion or a rear wall portion that covers an engine room, and gas is discharged in a horizontal direction through the exhaust opening.
However, in this case, in a mini shovel or the like that has a driver's seat open to the surroundings, there is a problem in that since the driver's seat is disposed near an exhaust opening, the operator is likely to be influenced by the heat and the noise of exhaust gas.
Thus, in order to reduce the influence of the heat or the like of exhaust gas from reaching the driver's seat, a gas exhaust structure is proposed in which a distal end (tail pipe) of an exhaust pipe that blows exhaust gas is disposed inside an engine room and the exhaust gas is discharged through an exhaust opening formed in a floor wall portion disposed so as to cover the engine room from the lower side (for example, Japanese Patent Application Publication No. 2013-24078).
Specifically, a mini shovel of Japanese Patent Application Publication No. 2013-24078 includes a cylindrical duct extending in an up-down direction on a lateral side of an engine. This duct is configured to guide gas inside the engine room to the exhaust opening that is open on the lower side of the engine room. Further, a tail pipe is inserted in the duct.
Thus, the gas inside the engine room and the exhaust gas are mixed in the duct and the heat and the noise of the exhaust gas are reduced. After that, the mixture gas is discharged downward from the exhaust opening.
Although not described in Japanese Patent Application Publication No. 2013-24078, in a small working machine of a model such as a mini shovel, a number of members are densely disposed in the engine room. Due to this, there is practically no space margin inside the engine room.
In particular, since the space of the engine room on both sides of the engine is narrow, it is not easy to secure the space for disposing such a cylindrical duct as disclosed in Japanese Patent Application Publication No. 2013-24078.

KOBELCO CONSTRUCTION MACHINERY CO., LTD.


An alloy suitable for coating metal surfaces is provided in which the alloy provides a liquid melt which contains a fraction of dissolved oxide forming additives as deoxidizers. The alloyed combination of elements in the liquid melt resists compound formation thus preserving the chemical activity of the individual elements. In a coating application, the alloy may form a coating that can interact with and remove the oxide or residual oxide coating of the base metal to be coated, i.e., scrub the surface of the metal clean. This results in increased coating bond strength and the ability to bond effectively to normally difficult alloys such as stainless steel, refractory metals (W, Ti, Ta etc.), or aluminum alloys which form protective oxide layers.

All metals except for gold, form native oxide layers which act to passivate the metal surface. In some metals such as aluminum, the native oxide layer is adherent and prevents further corrosive attack of the oxidized surface. However, other materials such as iron form a native oxide layer which is nonadherent and spalls off leaving base metal susceptible to further oxidation, i.e., rusting. The tendency of metals to form native oxide layers is very strong due to the high thermodynamic stability of the resulting oxide which forms. When virgin metal surfaces are exposed to oxygen containing atmospheres, generally the native oxide layer grows to its full thickness in a short time and for very reactive metals such as aluminum, or chromium, either as a metal or when dissolved in stainless steel, the oxidation can occur in a few seconds. Even in experiments done at high vacuum such as 10−9 torr, virgin metal surfaces of these reactive metals will quickly form native oxide layers.
Unfortunately, the chemical bonding nature of metals is such that metallic materials typically do not bond well to ceramic materials, including metal oxides such an oxidized metal surface, which are formed including ionic bonds. This poor bonding is a function of the incompatible nature of the metallic bonds, which may be modeled as ion cores surrounded by a sea of shared free electrons, and ionic bonds which result from directional electron transfer from specific cation atoms to specific anion atoms.
The tendency of metals to form oxides on the surfaces thereof, and the incompatibility of metal to ceramic bonding presents serious obstacles in the field of metal coatings. For example, in thermal spraying of metal coatings, it is often very difficult to bond the metal coating to reactive metals or alloys such as stainless steel alloys, aluminum alloys, and refractory alloys such as tungsten, zirconium, and titanium. Even if the base reactive metal is degreased and subsequently grit blasted to expose virgin metal surface, the native oxide layer reforms at a very fast rate, before thermal deposition of coating can begin. To try to overcome this, often coupon preparation and subsequent spraying is done at high vacuum in a vacuum chamber. This adds considerable expense to the coating operation, and is only marginally effective for highly reactive metals.

Highly active liquid melts used to form coatings


A vehicle frame includes a pair of spaced frame rails and at least one cross member connecting the frame rails. A tower structure is on one of the spaced frame rails for supporting a floor of a load-carrying bed spaced above the frame rails.

The present disclosure relates to a vehicle frame and, more particularly, to a frame subcomponent for supporting a vehicle's load-carrying bed on frame rails the vehicle's frame. In one embodiment, the frame subcomponent is a unibody tower structure disposed on an adjacent frame rail supporting the vehicle's load carrying bed thereabove and will be described with particular reference thereto. However, it is to be appreciated that the frame subcomponent could relate to other similar environments and applications.
Frames on pickup trucks and like vehicles often include a pair of spaced frame rails extending along the length of the vehicle. Cross members are used to connect the spaced frame rails and, together with the frame rails, provide a rigid ladder-like frame upon which a cab structure and a load-carrying bed structure can be mounted. Typically, the frame consisting of the frame rails and cross members is subassembled independently of the cab structure and the load-carrying bed structure. Likewise, the cab and load carrying-bed structures are subassembled separately and independently of one another. Once these components are subassembled, the cab structure and the bed structure, which are sometimes together referred to as the vehicle body, are mounted to the frame.
Conventional bed structures are often open-box structures including a rectangular bed floor, sidewalls extending upward from three of four edges of the bed floor and an openable tailgate extending along the remaining edge of the bed floor. When mounted to a ladder-like vehicle frame, the tailgate is oriented at one end of the frame rails opposite the cab structure. The bed floor is typically positioned directly adjacent and mounted to the frame rails. Thus, the height of the frame rails is approximately the same as the height of the bed floor.
Various types of body mounts are usually used for secured the vehicle body to the frame. Often the body mounts include some resilient material for absorbing vibrations and loads that are otherwise transferred from the vehicle frame to the vehicle body. Though these types of body mounts often slightly space the vehicle body from the vehicle frame, the vehicle body can still be characterized as being directly adjacent and directly mounted to the frame rails of the vehicle frame. Thus, body mounts can slightly space a bed floor from the frame rails, but the floor is still closely adjacent and, via the body mounts, directly mounted to the frame rails. Moreover, the height of the frame rails and, particularly, tops of the frames rails is approximately the same as the height of the bed floor.


Acid-functional polymer is reacted with a transition metal compound at a temperature above the T.sub.g of the polymer to produce crosslinked polymer. The process produces a liquid polymer product that dries to a crosslinked film without the required presence of volatile ligands. Improved coating such as floor polishes are also disclosed.

It has been known in the art to add stable complex salts of transition metals such as zinc to emulsions and dispersions of acid containing polymers, (U.S. Pat. Nos. 3,308,078, 3,328,325, 3,467,610, 3,554,790, 4,150,005, and 4,517,330, ).
In practicing this chemistry, complex salts are formed from simple salt or oxides of transition metals with amines or other simple complexing ligands. (In the following formulae `M` indicates a transition metal, `L` indicates a ligand). ##STR1##
Since each of the above steps in the formation of the complex from the free (or hydrated) metal ion is reversible and runs to equilibrium, the process must be forced to completion (tetradentate ligand complex) by mass action, charging an excess of the ligand species. The complexing agent must be a simple ligand, to avoid the formation of very stable complex structures that will not donate metals to the acidic polymer.
The metal complex is formed before addition to the polymer to increase the ion complex surface area, decreasing the charge per unit area, so that the acid containing polymer is stable in the presence of the multivalent ion. The instability of acid containing polymers to multivalent ions is well known and, in fact, they be are commonly used to flocculate and precipitate polymers from waste streams (Fe++, Fe+++ and AI+++ salts are most commonly used). The reduced charge density of the complex multivalent salt provides only minimal disruption of the polar double layer thought to be responsible for polymer emulsion stability.
When the complex salt solution is added to the acidic emulsion polymer, the salt undergoes counterion exchange. Most commonly, the complex multivalent cations are prepared as carbonate, bicarbonate, or acetate salts. As this technology is generally understood, the only limitation of the anion of the salt is that it be a stronger base than the anion of the pendant polymeric acid. If weaker base anions, such as chloride, etc., are used as the salt, crosslinking apparently does not occur because the process of counterion exchange does not happen; the weaker base anions do not displace the anion of the polymeric acid. (In the following ##STR2## represents an acid functional group attached to a polymer). ##STR3##
The conjugate acid of the anion of the stable metal complex must be either volatile or unstable. For instance, acetic acid, the conjugate acid of acetate anion, is volatile, and carbonic acid, the conjugate acid of both bicarbonate and carbonate anions, is unstable (spontaneously decomposing to carbon dioxide and water). In practice, the evolution of volatile conjugate acid, or the volatile by-products of the decomposition of the unstable conjugate acid is a processing problem encountered duringthis crosslinking reaction.
The complex cation, in close association with polymer carboxylate anions provides latent crosslinking of the polymer (Maintenance Chemical Specialties, by Walter J. Hackett. Chemical Publishing Co., Inc. N.Y., 1972. pp9-13. ). This crosslinking has been referred to as latent because it occurs only after the volatile (amine) ligand is released from the metal during the polymer film formation stages. ##STR4##
The latent crosslinking may be due to the formation of insoluble metal-polymeric carboxylate salts, or the formation of polymeric carboxyl complexes with the metals. ##STR5##
Complexed transition metal salt latent crosslinking has thus enabled the art to produce polymers that will crosslink in a coating upon drying, without interfering with the film formation process. Since the final crosslinked polymer effectively has the pendant acid functionality tied up in insoluble acid-metal salts or complexes, metal crosslinked polymers have improved resistance to alkaline materials, such as detergents or cleaning solutions.
The addition of low levels (typically 1 to 3%) of ammonia or other amine to a cleaner solution is believed to effectively reverse the crosslinking process. The free metal-amine complex is re-formed, thus freeing the polymeric acid functionality which may then be attacked by simple alkaline materials. These amine-containing cleaner solutions are known as strippers, since they effectively allow for the removal of the previously crosslinked films.
One problem of this chemistry has been that application of multiple coats of compositions containing these metal salt complexes can sometimes prove difficult because the new wet coat of polymer composition contains a high concentration of the complexing amine liqand. This high concentration of free amine, and the amine ligand released from the complex, act as a stripper on the previously applied under-coat causing redispersion of the under-coat, drag in the application of the top coat, whitening and ghosting of the coating, and general disruption of the recoating process known as poor recoatability. These difficulties are particularly noted when coating formulations are applied rapidly, as is common practice in industrial applications.
Though transition metal salt latent crosslinking of acid-containing emulsion polymers has provided many improvements in dry film properties, the high ammonia content of transition metal complex formulations is disadvantageous in that it is mildly toxic and highly odoriferous. The volatile ligands lead to difficulties in handling, formulating, and use of the emulsion polymers produced by this technology.

Transition metal crosslinking of acid-containing polymers


An apparatus for use in kiosks or other computerized devices for filtering out selected key codes transmitted between an input device, such as a keyboard, and a host computer. The apparatus includes an input port to receive key codes transmitted from a keyboard en route to a host computer or workstation. A key code filter may be used to filter out or block selected key codes, sequences of key codes, and combinations of key codes, and to prevent unauthorized persons from accessing certain functions of the host computer. Key codes blocked or filtered out may be modified in accordance with each particular system. Once selected key codes are filtered out, an output port passes the remaining unblocked key codes to a host computer.

1. The Field of the Invention
This invention relates to digital computers, and more particularly, to unique apparatus and methods for blocking selected key codes, sequences of key codes, and combinations of key codes transmitted between a keyboard and a host computer.
2. The Relevant Art
Kiosks of various types and providing a wide variety of services, are currently increasing in popularity. Most kiosks operate using standard computer hardware and include some type of input device such as a keyboard. When designing a kiosk for use by the public, it is often desired to prevent customers from entering certain keys, key sequences, or key combinations from the keyboard. For example, if the input device is a standard keyboard, it may be desired to prevent a user from entering a key combination such as a "CTRL-ALT-DEL" sequence. This key sequence may enable a user of a kiosk to access shut down or reboot commands, or may allow undesired access to applications or data.
Currently, offending keys are blocked using either hardware or software. A typical hardware method is to design a keyboard that does not offer undesired keys to a user. This limits the choices available to a designer and may add expense by requiring a customized keyboard. One typical software solution is to alter drivers or system BIOS on a kiosk host computer so that undesired key codes are ignored. This solution can be impractical since a designer may then become responsible for writing and maintaining keyboard driver code for each operating system used.
Given the drawbacks of current solutions, apparatus and methods are needed to improve currently practice methods for blocking or filtering out selected key codes. Consequently, a need exists for improved apparatus and methods that block or filter out selected keys, sequences of keys, or combinations of keys that a user may input from a keyboard or other input device. What is further needed are such apparatus and methods that are easily installed with an existing keyboard and host computer without requiring modification of an operating system or installing additional applications on the host computer.
In particular, what is needed is an apparatus, physically independent from the host computer and keyboard, that may simply be inserted therebetween to monitor combinations and sequences of key presses, in addition to keys pressed alone, which would provide the desired key code filtration. Accordingly, it would also be an advance in the art to provide a filtration device that could be easily reprogrammed or updated to add, delete, or modify the set of selected keys codes to be blocked.

International Business Machines Corporation


A relay server presents, to an operator having made a login request, a list of connecting-target apparatuses to which the operator is able to connect. When, for example, a client terminal is selected from the list, the relay server stores, as address filter information of the relay server, an address of a communication apparatus operated by the operator, and transmits the address filter information to the client terminal. The relay server stores address filter information received from the client terminal. Then, a routing session for a VPN is established between the relay server and the client terminal, and routing of a packet is performed based on the address filter information.

1. Field of the Invention
The present invention relates to a relay server that enables communication to be performed between terminals connected to different LANs (Local Area Networks).
2. Description of the Related Art
Conventionally, a communication technology called a virtual private network (Virtual Private Network, VPN) has been known (for example, see Japanese Patent Application Laid-Open No. 2002-217938). The VPN is used for, for example, performing communication via Internet between terminals that are connected to LANs of a plurality of branch offices (stations) each located in each of a plurality of different regions. Use of the VPN enables another LAN located in a distant place to be used as if it is a directly-connected network.
In this type of system, generally, communication between apparatuses is performed by using IP addresses and identification information of the apparatuses. However, an operator may not always use the same apparatus when performing operations in this type of system. The operator may use a different apparatus when he/she is in a different place or on a business trip, for example. This means that an apparatus included in a VPN is changed, which usually requires the VPN setting to be changed. In a case where, for example, setting of a network is changed, the change should be reflected in the other apparatuses. This complicates a process. Particularly, in a case where a number of operators perform operations in a large-scale network, setting of an access control tends to be complicated.

Relay server and relay communication system


A vehicle light emitting device including a light emitting element, a primary reflector, and a secondary reflector. A reflecting surface of the primary reflector has a shape of a substantially dome-shaped body of revolution formed by rotating about the optical axis Ax an ellipse E which has a primary focal point F1 which is a point near the light emitting element and a secondary focal point F2 which is a point near the reflecting surface. The primary reflector includes a belt-shaped region, which straddles a ring-shaped locus of the secondary focal point F2 and is configured as a light translucent portion, whereby reflected light from the primary reflector is caused to temporarily converge on the secondary focal point F2 in each cross-section of the body of revolution including the optical axis Ax and is thereafter caused to be incident on the secondary reflector as a diffused light.

1. Field of the Invention
The present invention relates to a vehicle lighting device including a light emitting element, such as a light emitting diode, as a light source.
2. Description of Related Art
In recent years, lighting devices, which use as light sources light emitting elements, such as light emitting diodes, have been developed for use in vehicle lighting devices such as headlamps.
In relation to the development of these lighting devices, Japanese Patent Publication No. 2001-283616 describes a vehicle lighting device including a primary reflector which reflects light from a light emitting element disposed on an optical axis extending in a longitudinal direction of the lighting device in such a manner as to be directed towards the front of the lighting device towards the rear of the lighting device and a secondary reflector which reflects the light from the light emitting element that is reflected on the primary reflector towards the front of the lighting device. In the vehicle lighting device described in JP-A-2001-283616, the shape of a reflecting surface of the primary reflector is the shape of an ellipsoid of revolution, which takes a light emitting center of the light emitting element as a primary focal point and a point positioned forwards of the primary focal point on the optical axis as a secondary focal point.
While the utilization factor of bundles of rays of light from the light emitting element can be enhanced by adopting the vehicle lighting device described in the aforesaid JP-A-2001-283616, in the vehicle lighting device so described, there is a problem that light emitted from this vehicle lighting device cannot be accurately controlled since not only the light from the light emitting element that is reflected on the primary reflector, but also direct light from the light emitting element, are designed to be incident on the secondary reflector.
The invention was made in view of this situation, and an object thereof is to provide a vehicle lighting device including a light emitting element as a light source which can enhance the utilization factor of a bundle of rays of light from the light emitting element and also accurately control light emitted therefrom.


A method for actively detecting link failures on a high availability backplane architecture. The backplane system includes redundant node boards operatively communicating with redundant switch fabric boards. Uplink ports of the node boards are logically grouped into trunk ports at one end of the communication link with the switch fabric boards. A probe packet is sent, and a probing timer is set whenever either a specified number of bad packets are received, or an idle timer expires. If a response to the probe packet is received before the probe timer expires then the link is deemed valid, otherwise the link is presumed to have failed. Preferably, either the node boards or the switch fabric boards are configured to properly handle a probe pack, which preferably has identical source and destination addresses.

This invention is related to the field of networking devices, and more particularly to an Ethernet network device having backplane architecture for detecting a link failure and switching to a good port in response thereto.
Any business operating on a 24/7 basis strives cannot afford to suffer from outages for longer than just a couple of minutes or perhaps no more than half an hour. Unplanned outages can severely hamper data operations and, can be extremely expensive in terms of lost revenue and manpower expended to correct such situations. Two recent 1995 studies showed that average businesses lost between $80,000 and $350,000 per hour due to unplanned outages. With these dollar loses in mind, it becomes quickly obvious that setting up a redundant information technology structure comes at a cheaper price than the risk of even a short outage. This is especially true when considering the relatively low prices of computers running versus the cost of such downtime. Furthermore, administrators know exactly how expensive the additional equipment, software and operator education is, whereas the cost of unplanned outages can be very difficult to quantify beforehand.
The Ethernet network has been overwhelming deployed in Local Area Networks (LAN) because of its low cost, easy deployment and installation. After years of improvements on the Ethernet technology, today, the application of Ethernet has been extended from LAN to the both WAN/MAN. More recently, the Ethernet technology is also incorporated into the backplane of chassis-based systems due to the low cost, widely available sources, and embedded error detection capability.
In the chassis-based system, the backplane is required to provide the reliable and robust connections among link cards and modules. However, since the Ethernet network was originally developed in a LAN environment, the "availability" requirement for the LAN application is quite different from the one for the backplane application. For example, in a conventional LAN environment, the spanning tree protocol is used to provide a "failover" function by reconfiguring the active topology when the network detects a link or port failure. However, the convergence time is relative long. From the time of detection of the failure, it can take as long as twenty to fifty seconds to complete the change in topology and resume to normal operation. Even using a conventional "improvement" protocol, the fast spanning tree could take fifty msec (milliseconds) to resume normal operation after detecting the failure in a switch or a link.
According to the Institute of Electrical and Electronics Engineers 802.3 standard, link aggregation has been developed to increase bandwidth and availability by aggregating more than one link together to form a link aggregation group. The media access control layer (MAC) can treat the multiple links as a single logical link. When a link in the aggregating group fails, the traffic can be distributed (or rerouted) over the remanding operating links. However, link aggregation only provides failover among parallel connections, which parallel connections are shared with the same end nodes.
For the backplane application, the Ethernet network usually has very simple configuration, e.g., a star topology, meaning that from every card slot there connects a first bus to a first switch fabric and a second bus to a second switch fabric. If the first bus fails to work, the device switches automatically to use the second bus. However, the convergence time of twenty to fifty seconds in a spanning tree recovery is not acceptable in a backplane environment. Additionally, link aggregation, as indicated hereinabove, only provides failover among parallel connections that are shared by the same end nodes. That is, a backup link is not shared with the same ends of failure link. Thus, link aggregation may not find application to the Ethernet backplane environment.
Therefore, what is needed is a simple, rapid, and robust solution to achieve high availability for the Ethernet backplane environment with link failure detection and failover switching.

Apparatus for link failure detection on high availability Ethernet backplane