According to the present invention, a memory system comprises storing section having a plurality of memory elements each of which stores one of n-value storage states corresponding to data "0", "1", . . . , "n-1", and including a plurality of information memory elements for storing n-value information data and a plurality of check memory elements for storing check data, converting section for respectively converting the information data and the check data stored in the memory elements into binary codes having a plurality of bits each constituted by 0 or 1, the binary codes corresponding to the information data and the check data, and detecting/correcting section for detecting and correcting an error on the basis of the binary codes corresponding to the check data and the information data.

1. Field of the Invention
The present invention relates to a memory system and, more particularly, to a multi-value memory system using a nonvolatile semiconductor memory which is electrically erasable and programmable.
2. Description of the Related Art
In recent years, as a memory system, a semiconductor memory device using a semiconductor memory is popularly used. In the semiconductor memory device, degradation of reliability caused by various influences with a high degree of integration and a high integration density is posed as a problem.
For this reason, an error detection/correction is code for performing error detection/correction is often applied to a semiconductor memory device. In practice, this error detection/correction code must satisfy all the following conditions.
(1) An error frequency is lower than a permissible error frequency unique to a semiconductor memory device. PA1 (2) Coding and decoding can be performed at a high speed with a high-speed reading/writing operation. PA1 (3) In code structure, the redundancy of the code is minimum. PA1 (1) The information data storing means includes a second converting means for causing the check memory element to generate a binary code corresponding to data to be stored in one of the memory elements, and writing means for causing the memory elements to perform n-value storage on the basis of the binary code. PA1 (2) The converting means includes means for converting storage data of a memory element into a binary code having a plurality of bits each constituted by 0 or 1, and the detecting/correcting means includes means for detecting/correcting an error on the basis of information data and check data and outputting a data code represented by combinations of data of the plurality of memory elements on the basis of the binary code. PA1 (3) In the configuration of (2), the first memory system is characterized by further comprising means for generating a binary code corresponding to data to be stored in the memory element of the check memory element on the basis of the binary code converted from the data code and corresponding to data to be stored in the memory element of the information memory element to cause the memory elements to perform n-value storage on the basis of the binary code. PA1 (4) The converting means includes means for converting data such that, when a size of data in the memory element changes by one, a binary code of the data has a Hamming distance of 1, for that of the data whose size in the memory element is different by one. PA1 (5) The memory elements perform n-value storage using charge amounts stored in the memory elements and correspond to n data "0", "1", . . . , "n-1" in an order of magnitudes of the charge amounts. PA1 (6) The memory element is a nonvolatile memory cell obtained by stacking and forming a charge storage layer and a control gate on a semiconductor layer. PA1 (7) A storage state of the memory element is changed by one. PA1 (8) The storing means stores n-bit (2.sup.n <N.sup.M <2.sup.n+ 1) information having a relation n<2.sup.M using combinations of the M (M: an integer of not less than 2) and N-value (N: an integer of not less than 3) memory elements.
For the above practical viewpoints, an SEC-DED code for correcting a 1-bit error and detecting a 2-bit error has been popularly used at present.
In order to obtain higher reliability, a DEC code for correcting a 2-bit error is applied. In particular, a byte error detection/correction code for detecting/correcting errors in units of memory packages or units of multi-bit outputting/storing elements. In order to practically use a device for processing data in units of bytes, an SbEC-DbED code for not only correcting a single-byte error but also having high capability of detecting a 2-byte error is required.
As available means for high integration, a method of multi-value storage has been considered.
In an example of multi-value dynamic semiconductor memory, a memory cell performs a multi-value storage by having three or more dispersed charge distribution stored in the memory cell. In this case, since data stored in one memory cell will be destroyed by one soft error, error correction code (e.g., byte error correction code which treats one cell data as one byte) capable of correcting the above error is required.
On the other hand, in a case of a non-volatile semiconductor multi-value memory device which is electrically erasable and programmable, a memory cell having three or more disperse threshold voltage distribution is used. For example, a multi-value ROM (read only memory) of 3-bit which is constructed by two ternary memory cells is known (Jpn. Pat. Appln KOKOKU Publication No. 5-60199), a multi-value EEPROM can construct the same as the multi-value ROM. For example, 3-bit information can se stored for two memory cells by using eight values from nine values (i.e., 3.times.3=9), as cell group constructed by adjacent memory cells sharing their control gates is a fundamental element. In this case, the multi-value EEPROM differs from the multi-value dynamic semiconductor memory device and has not a problem of soft error. However, charge amount stored in a charge storage layer shifts to a threshold voltage of the memory cell whose charge amount is 0, whereby data error will be raised.
The structure and operation of a ternary NAND EEPROM which can be integrated at a high density will be briefly described below. FIG. 1 is a sectional view showing a NAND cell structure. A NAND cell has a p-type substrate 11, a floating gate 14, a control gate 16, an interlaminar insulating film 17, a bit line 18, and an n-type diffusion layer 19.
A plurality of memory cells are connected in series with each other such that adjacent memory cells commonly use a source and a drain, and the adjacent memory cells are connected to a bit line as one unit, thereby constituting the NAND cell. A memory cell array is integrally formed in a p-type well formed in a p-type substrate or an n-type substrate. The drain side of the NAND cell is connected to bit lines through selection gates, and, similarly, the source and drain sides of the NAND cell are connected to a source line through selection gates. The control gates of the memory cells are continuously arranged in a row direction to constitute word lines.
The operation of the ternary NAND EEPROM is as follows.
A data writing operation is performed from a memory cell located at a position farthest from the bit line. A high voltage Vpp (=about 20 V) is applied to the control gate of a selected memory cell, an intermediate voltage Vm (=about 10 V) is applied to the control gate and selection gate of a memory cell is closer to the bit line than the selected memory cell, and a voltage of 0 V, a low voltage Vdd (=about 2 V), or an intermediate voltage is applied to the bit line in accordance with data. When the voltage of 0 V or the low voltage Vdd (=about 2 V) is applied to the bit line, the potential of the bit line is transmitted to the drain of the selected memory cell, and electrons are injected from the drain into the floating gate. In this manner, the threshold voltage of the selected memory cell is positively shifted. However, a shift amount obtained when the low voltage Vdd is applied to the bit line is smaller than a shift amount obtained when the voltage of 0 V is applied to the bit line.
When an intermediate voltage is applied to the bit line, no electron injection occurs, and the threshold voltage does not change.
A data erasing operation is simultaneously performed for all the memory cells in the NAND cell. More specifically, all the control gates are set to be 0 V, and the bit and source lines are set in a floating state, thereby applying a high voltage Vpp (=about 20 V) to all the selection gates, a p-type well and an n-type substrate. In this manner, the electrons in the floating gates of all the memory cells are discharged into the p-type well, and the threshold voltage is negatively shifted.
A data reading operation is performed by two cycles. In the first cycle, the control gate of a selected memory cell is set to be 0 V, and the control and selection gates of the remaining memory cells are set to be a power supply voltage Vcc (=about 5 V). In this state, it is checked whether a current flows in the selected memory cell. In the second cycle, the control gate of the selected memory cell is set to be a low voltage Vdd (=about 2 V), and the control and selection gates of the remaining memory cells are set to be the power supply voltage Vcc (=about 5 V). In this state, it is checked whether a current flows in the selected memory cell. In this case, three threshold voltages Vt satisfy Vt <0 V, 0 V=<Vt<Vdd, and Vdd=<Vt<Vcc, respectively.
When i-th data obtained upon arrangement of the magnitudes of physical amounts (e.g., the threshold voltage of a memory cell of EEPROM) for determining multi-values in a descending order is defined as multi-value data "i", a case wherein read-out multi-value data is different from written multi-value data by only one in size is considered. At this time, read-out output data may be different from written input data by 2 or more bits. As a result, at least an SbEC code is required as an error correction/detection code using input/output data as information data. In addition, in order to obtain reliability almost equal to that of an SEC-DED code used in a binary storing element, an SbEC-DbED code is required. However, this SbEC-DbED code requires a complex decoding circuit.
When a burst error such as a column failure of stored data occurs, the net capability of correcting/detecting an error decreases. When such a burst error occurs, and stored data except for the stored data at an address at which the burst error occurs has an error, at least a 2-bit error correction code must be applied to correct these errors.
For example, in a electrically erasable and programmable nonvolatile semiconductor memory (EEPROM), a unique column failure may occur. This column failure occurs when current leaks from a bit line, or data in memory cells in a common column in a block are excessively written or excessively erased. When such a column failure occurs, and a memory cell except for the memory cell at the column address at which the column failure occurs has an error, these errors cannot be corrected by a single b-bit byte error correction code such as an SbEC code. In this case, for example, a double b-bit byte error correction code is required. However, this code requires a complex decoding circuit.
As described above, the conventional memory system has the following problems.
When i-th data obtained upon arrangement of the magnitudes of physical amounts for determining multi-values in a descending order is defined as multi-value data "i", and read-out multi-value data is different from written multi-value data by only one in size, read-out output data may be different from written input data by 2 or more bits. As a result, at least an SbEC code is required as an error correction/detection code using input/output data as information data. In addition, in order to obtain reliability almost equal to that of an SEC-DED code used in a binary storing element, an SbEC-DbED code is required. However, this SbEC-DbED code requires a complex decoding circuit.
In an EEPROM, a unique column failure may occur. When such a column failure occurs, and a memory cell except for the memory cell at the column address at which the column failure occurs has an error, these errors cannot be corrected by a single b-bit byte error correction code such as an SbEC code. In this case, for example, a double b-bit byte error correction code is required. However, this code requires a complex decoding circuit.


The present inventors have developed new radiolabeled Darapladib and analogs thereof which can be used for the specific detection of vulnerable atherosclerotic plaques by targeting lipoprotein-associated phospholipase A2 (Lp-PLA2) which is a biomarker of choice concerning inflammation and atherosclerosis progression. Thus, the present invention relates to radiolabeled Darapladib and analogs thereof and their use as imaging compounds.

Cardiovascular diseases, resulting from coronary and carotid complications, stand for one of the first cause of morbidity and mortality in the world. The concerned subjects show clinical signs when vulnerable atherosclerotic plaques become damaged or cracked. The vulnerable atherosclerotic plaque rupture initiates the formation of a thrombus which clogs vessels, resulting from myocardial ischemia, myocardial infarction or cerebral arteries embolization leading to transient ischemic attack (TIA) or ischemic stroke. Thus, atherosclerotic complications are responsible in western countries for about 50% of death. While progresses have been shown on treating atherosclerotic diseases, fatal events occurrence is still on the rise.
Atherosclerosis is characterized by an accumulation of lipids and leukocytes with the vascular wall of large arteries, leading to their occlusion and subsequent clinical events. Hydrolysis of oxidized phospholipids in low density lipoproteins (LDL) mediated by lipoprotein-associated phospholipase A2 (Lp-PLA2), predominantly produced by activated macrophages, plays an important role in atheroma plaque development by promoting the recruitment of leukocytes. Clinical studies have shown that plasma Lp-PLA2 levels were correlated with cardiovascular events. In situ, the expression of Lp-PLA2 was higher in carotid atherosclerotic plaques from symptomatic than asymptomatic patients.
As previously described, before rupture, vulnerable atherosclerotic plaques are characterized by a high number of inflammatory cells (leukocytes and phagocytic cells) and proteic biomarkers. Thus, by targeting biomarkers associated with vulnerable atherosclerotic plaques, it would be possible to precisely evaluate the inflammatory levels in atheromatous lesions.
Nuclear medicine, by its high sensibility, is able to provide solutions. Labels have been developed in scintigraphy to evaluate the recruitment of macrophages, the production of matrix metalloproteinase, apoptosis, and the increment of phagocytic cells metabolic activity. However, the identification of inflammatory lesions in coronary section remains difficult in particular due to the small size of the plaque, heart and respiratory movement and the absence of specific nuclear label.
Functional molecular imaging can enable diseases tracking at an early step of development or also during drug treatments. Positron Emission Tomography (PET) has become a powerful tool to elucidate disorders ranging from neurological to heart disease. Fluorine-18 is the most widely used radioisotope for PET diagnosis due to its suitable halftime (t1/2=109.8 min), high resolution imaging and low perdition of radioligand-target binding. In nuclear medicine, the "gold-standard" for PET diagnosis in many pathologies (cancer, cardiology, neurology etc.) is the Fluorodeoxyglucose or 18F-FDG. However, this PET label of reference, 18F-FDG is not suitable to detect vulnerable atherosclerotic plaques in coronary section due to the catch of 18F-FDG by the myocardium. Furthermore, 18F-FDG has a poor capture and does not specifically target the atherosclerotic plaques. 18F-FDG is thus a poor candidate for atherosclerosis diagnosis.
In view of the foregoing, there is a real need of candidates for early diagnosis of vulnerable atheroma plaques that are susceptible to break.
The present invention aims to the early detection of vulnerable atherosclerotic plaques and thus relates to new non-invasive imaging tools to assess plaque vulnerability and localization.
The present inventors have surprisingly found and developed new compounds which can be used for the specific detection of vulnerable atherosclerotic plaques by targeting lipoprotein-associated phospholipase A2 (Lp-PLA2) which is a biomarker of choice concerning inflammation and atherosclerosis progression. Lp-PLA2 is an enzyme produced by inflammatory cells involved in atherogenesis but is especially expressed in necrosis center of atherosclerotic lesions. This enzyme is thus highly present in the fibrous plaque before the complicated lesion phase. Lp-PLA2 rapidly degrades phospholipids present at the surface of oxidized LDL, thus leading to the production of inflammatory and cytotoxic products and consequently to vulnerable plaque rupture. Thus, by targeting the accumulation of inflammatory cells and/or lipoproteins (LDL and/or HDL), the present inventors have found that it was possible to detect diseases associated with Lp-PLA2.
During the last decade, scientists have tried to develop ligands to treat cardiovascular diseases. Darapladib, a new highly potent Lp-PLA2 inhibitor (IC50=0.25 nM)13, was discovered in the early 2000's but failed to reach critical endpoints in phase III clinical trials. The thiouracile ring bearing keto-enol tautomerism has three different alkylation sites that represent a challenge for large scale production.
The present inventors have hypothesized that Darapladib, a potent Lp-PLA2 inhibitor (IC50=0.25 nM), could be radiolabeled using 18F, 124I and 131I, and used as ligand rather than a drug, for PET imaging of vulnerable plaques. Thriving on the strong affinity of Darapladib towards Lp-PLA2 and the fluorine already present in the structure, the present inventors decided to use this affinity to target vulnerable atheroma plaques with [18F]-Darapladib, [123I]-Darapladib [124I]-Darapladib, [125I]-Darapladib, [131I]-Darapladib, and [211At]-Darapladib for PET imaging and SPECT (Single-photon emission computed tomography) imaging. They surprisingly found that the original structure of Darapladib could be preserved while having unchanged physico-chemical properties as well as in vivo behavior.
Since Lp-PLA2 inhibitors may be used to thwart the deleterious effect of this enzyme in different pathologies, the present inventors have synthesized their own series of inhibitors using the key structure of Darapladib.

Radiolabeled Darapladib and analogs thereof and their use as imaging compounds

INSERM (INSTITUT NATIONAL DE LA SANTE ET DE LA RECHERCHE MEDICALE)


A programmable interrupt controller for use in computer systems including one or more CPUs is provided. The programmable interrupt controller includes an interrupt request interface, a central interrupt controller, random access memory, and at least one processor interface. The central interrupt controller systematically selects interrupt requests from the interrupt request interface. Information associated with each interrupt request is stored in the random access memory. The central interrupt controller access the information in the random access memory and uses the information and the state of the currently selected interrupt request to determine a next state for the currently selected interrupt request. The information is passed on to the processor interface to determine when and if the interrupt request should issue to one of the CPUs.

1. Field of the Invention
The present invention relates to interrupts within a computer system, and more specifically to an interrupt controller for more efficient handling of interrupts in a computer system.
2. Description of the Related Art
A typical computer system contains at least one interrupt service provider, usually a central processing unit (CPU), and a number of input/output (I/O) devices peripheral to the CPU(s). These I/O devices commonly include hard disk drives, floppy disk drives, video adapters, parallel ports, serial ports, and other similar I/O type devices. An I/O device may need to alert the CPU(s) or request service when it completes a task or has a status change, such as finishing a data transfer, completing an operation, receiving data, or the occurrence of an error condition.
The typical mechanism for an I/O device to request service from the CPU(s) involves an interrupt request. An interrupt request is generally a hardware signal sent from the requesting device to a CPU notifying the CPU that the I/O device requires service. Other system devices such as timers, direct memory access (DMA) controllers, and other processors may generate interrupt request signals.
One advantage of using interrupts over other techniques, such as polling, is that the CPU is free to perform other operations between interrupts. When a CPU receives an interrupt request, it stops executing the current instruction routine, saves its state, and jumps to an interrupt service routine. The interrupt service routine includes instructions specific to the device requesting the interrupt so that the CPU can respond to the device condition or status change that instigated the interrupt request. When the interrupt service routine is completed, the CPU restores its state and returns to its location prior to the interrupt.
Referring to FIG. 1, a computer system 100 using interrupts is shown according to the prior art. The computer system 100 includes a CPU A 110a, and a main memory system 120 coupled to a host bus 180. The main memory system 120 typically includes a memory controller and system memory (not shown). A bus bridge 140 is coupled to the host bus 180 and an expansion bus 190 and typically includes a DMA controller (not shown). The expansion bus 190 typically conforms to a popular bus standard such as the Industry Standard Architecture (ISA), Extended Industry Standard Architecture (EISA), Microchannel Architecture (MCA), or Peripheral Component Interconnect (PCI). Alternatively, multiple expansion busses are included, such as a PCI bus further coupled to an ISA bus. Several I/O devices 150, 160, 170 are coupled to the expansion bus 190. The I/O devices 150, 160, 170 are typically devices such as a floppy disk drive, video adapter, parallel port, or other devices as are well known in the art.
The bus bridge 140 and the I/O devices 150, 160, 170 generate interrupt requests along interrupt request lines 142, 152, 162, 172, respectively, to notify the CPU A 110a that service is needed. The interrupt, requests along lines 142, 152, 162, 172 are collected by a programmable interrupt controller (PIC) 130. The programmable interrupt controller 130 is coupled to the host bus 180 and the expansion bus 190. Generally, when the programmable interrupt controller 130 receives one of the interrupt requests along lines 142, 152, 162, 172 it sends an interrupt signal on line 132 to the CPU A 110a. When the CPU A 110a receives the interrupt signal on line 132, it finishes its current operation and sends an interrupt acknowledge along line 112 to the programmable interrupt controller 130. When the programmable interrupt controller 130 receives the interrupt acknowledge it sends an interrupt vector to the CPU A 110a over the host bus 180. The interrupt vector indicates the location of the appropriate interrupt service routine to the CPU A 110a.
Generally speaking, in a typical system, a programmable interrupt controller receives the interrupt request signals from the various system devices and organizes the requests to be sent to the CPU(s). Normally, the programmable interrupt controller includes a mask register associated with each interrupt. The mask register is programmed to block a certain interrupt so that the CPU will not be interrupted by that particular interrupt. The programmable interrupt controller contains other registers associated with each interrupt for indicating information such as the interrupt status and interrupt vector for each interrupt.
The programmable interrupt controller also functions as an overall manager for interrupt requests. It receives the interrupt requests from each device, determines which requests are sent to the CPU(s) first, and handles new incoming interrupt requests. Some devices have more immediate need for service than other devices. Therefore, the programmable interrupt controller provides a priority system to be assigned to the interrupt requests. Generally, the programmable interrupt controller determines which one of the current interrupt requests has the highest priority and forwards that request to a CPU first. Occasionally, an interrupt request will be received by the programmable interrupt controller that has a higher priority than the interrupt request currently being serviced. One technique commonly employed to deal with this situation is interrupt nesting. In interrupt nesting, the programmable interrupt controller allows the incoming interrupt request to interrupt the servicing of an earlier interrupt request currently being .serviced if the incoming interrupt request is of higher priority than the earlier interrupt request currently being serviced. If the incoming interrupt request is not of higher priority, it is put in order with other pending interrupt requests, usually according to the source of the interrupt. However, this requires that the queue in each nesting buffer be of sufficient size to accommodate all of the potential interrupt sources. Accordingly, there is a need for an interrupt controller that will optimize the storage of pending interrupts.
In addition to resolving priority among devices needing to be serviced, the controller will also need to resolve a task priority to determine to which CPU in a multiple CPU system the interrupt should be sent Typically, the CPU or device servicing an interrupt is assigned a task priority according to the level of importance of the task being performed. When a new task is to be performed, it is customary to search for a device that has the lowest task priority, and assign the new task to that device (for an interrupt that does not have a destination previously specified). However, if more than one device shares the same task priority, there is a chance that one device will always end up performing the new task, while other devices a the same task priority level may never be assigned the task. Therefore, it would be desirable to introduce a scheme to ensure that no such uneven distribution of system load occurs.
It can easily be understood that a relatively large amount of time may pass before an interrupt request is serviced, especially if the interrupt request has a low priority. The amount of time between the assertion of an interrupt request and the actual servicing of the interrupt request is called the interrupt latency. A problem associated with large interrupt latencies is that the status of the requesting device may change during the latency period so that servicing is no longer required, and thus the CPU will unnecessarily execute the interrupt service routine. This unnecessary execution of interrupt service routines results in extra overhead because the CPU spends time trying to service a condition which no longer exists, and thus overall system throughput is degraded. Therefore, a technique is desired for preventing invalid interrupt requests from being sent to the CPU.
A typical programmable interrupt controller implementation includes storage registers associated with each interrupt which store the current state of the interrupt, such as pending or in-service. Also, storage registers are required to store information for each interrupt request, such as the vector information and the priority level. Interrupt request receiving circuitry in the programmable interrupt controller coordinates the interrupt request state and other information with processor interface circuitry in the programmable interrupt controller. For systems with a large number of interrupt request sources, the amount of circuitry required to implement the above storage registers is very large. If the system supports multiple CPUs, then the above storage registers may need to be repeated in the programmable interrupt controller for each CPU, further increasing the size of the circuitry. Also, a large amount of circuitry is required to coordinate, manage, and access the storage registers. For an integrated programmable interrupt controller, a large portion of the chip area is require to implement the storage registers and associated circuitry. Therefore, it is desirable to have a more efficient way of referencing and implementing the required storage information for each interrupt.
Additionally, a typical programmable interrupt controller includes control circuitry associated with each interrupt request input to track the changes in the state of the interrupt request. This control circuitry includes some storage elements that are used to store the current state, and some combinatorial logic to determine the outputs and the next state based on the current state and other inputs. Similar control circuitry is required for each interrupt request input. If the number of interrupt request inputs is large, the amount of circuitry required to implement all the control circuitry can become prohibitively large. Therefore, a more efficient way of implementing the interrupt request control circuitry is desired.

System and method for using random access memory in a programmable interrupt controller


An assembly includes a combustion engine and a housing to protect an engine, wherein the housing has a first wall and the first wall has a container.

Currently a stationary internal combustion engine is shipped in a container to a distant location. At the destination site the engine is removed from the container and is placed in a building, where the engine may be attached to a generator. The container will be removed from the site and can be used to transport other engines.
It is also known in the art to assemble a unit comprising an engine, a generator, and supporting devices like a cooler. The unit is placed in a container, so that the container may be used to transport the unit and to house the unit at the destination site.


The invention is based on an electric power tool having at least one drive unit and a gear unit, where the gear unit is a drive element for applying force to a piston unit. It is proposed that the drive element and the piston unit be arranged in an axially parallel manner. At least a region of the drive element overlaps axially with a longitudinal portion of the piston unit. The drive unit is arranged approximately centrally in an axial extension of the piston unit and the longitudinal axis of the drive unit is arranged transversely to the piston longitudinal axis.

1. Field of the Invention
The invention relates to an electric power tool.
2. Description of the Prior Art
Known electric power tools with an eccentric drive, in particular electric hammers, have a drive unit as well as a gear unit, and a rotary motion transmitted from the drive unit to a crankshaft via a drive shaft is converted into linear motions of a drive element, such as a connecting rod. In such electric hammers, a reciprocating barrel piston, connected to an eccentric element that is subjected to force by the connecting rod, is for instance used as the impact mechanism technology.
Typically, such electric power tools have a so-called "in-line" mode of construction, in which the eccentric element is disposed in-line axially before the drive unit. In this construction, the length of the connecting rod is included in the length of the device. This kind of construction can lead to a disadvantageous distribution of the weight of the device, because the device becomes top-heavy and can be manipulated only with difficulty.


This invention utilizes the fact that a maximum density difference of pixels in a window within a predetermined range including a pixel of interest is large for a character region, and is small for a photograph region. A maximum density difference of an image within the predetermined region is calculated. A quantization error of pixels around the pixel of interest is calculated, and a correction amount is then calculated by proportionally distributing the quantization error in accordance with a feature amount calculated by a feature amount calculator. The correction amount is added to an image signal of the pixel of interest to form a compensation image signal, and the compensation image signal is quantized.

1. Field of the Invention
The present invention relates to an image processing apparatus which can perform quantization processing of a document image including both a character portion and a photograph portion while maintaining high resolution of the character portion and a high gray scale characteristic of the photograph portion.
2. Description of the Prior Art
In general, in an image processing apparatus, such as a document image processing apparatus which can process not only code data but also image data, when image data are read by a reading means such as a scanner. The image data of, e.g., characters, graphs, and the like having a contrast are subjected to simple quantization using a fixed threshold value. Image data of, e.g., photographs having a gray scale are subjected to quantization by a pseudo gray scale means such as a dithering method. The reason why such processing operations are performed is as follows. That is, when read image data are uniformly subjected to simple quantization processing using a fixed threshold value, image quality is not degraded in a character/line region since the resolution is preserved. However, image quality is degraded in a photograph region since the gray scale characteristic cannot be preserved. On the other hand, when read image data are uniformly subjected to gray scale processing by, e.g., a systematic dithering method, image quality is not degraded in a photograph region since the gray scale characteristic can be preserved. However, an image with poor image quality is formed in a character/line region since the resolution is impaired.
As a means for solving such a problem, an "error diffusion method" as a quantization method which can satisfy a gray scale characteristic of a photograph image region, and has a better resolution of a character/line region than the systematic dithering method has been proposed. In this "error diffusion method", as described in the article entitled "An Adaptive Algorithm for Spatial Gray Scale" appearing in the journal "Proceeding of the S.I.D Vol. 17 2 Second Quarter 1976 p.p. 75-77", a product of a quantization error obtained when a pixel of interest is quantized by a given threshold value, and a predetermined weighting coefficient is diffused to non-quantized pixels in a predetermined region around the pixel of interest, and when the non-quantized pixels are quantized, quantization is performed while adding the diffused quantization error as a correction value.
In the "error diffusion method", since quantization processing is performed for a document image including both a character region and a photograph region by the same method, processing according to features of the respective regions cannot be performed. For this reason, when an input image places importance on the gray scale, quantization processing which can sufficiently satisfy the gray scale characteristic can be performed. However, in an image such as a character image which places importance on the resolution rather than the gray scale characteristic, the resolution of a character portion is impaired due to error compensation processing.

Image processing apparatus with improved dithering scheme


Systems and methods are provided for encoding and transmitting codewords. A message is encoded in two encoders. For at least one of the two encoders, the message is algebraically modified prior to being encoded. In a specific example, the message is algebraically modified prior to being encoded in each of two traditionally non-systematic encoders, with the result that the output is equivalent to that of a turbo encoder.

Radio signals suffer from high variability in signal quality due to effects such as propagation loss, fading and interference. Although radio link quality is robust in general for most types of applications ranging from delay sensitive voice to delay tolerant data, it is not uncommon for the radio link to experience outage, manifested by dropped calls or intolerable transmission error rates. Methods used to decrease outage probability and improve reliability with a single radio link are well known. These include forward error correction and HARQ (hybrid automatic repeat request).
It is common to find multiple RAT (radio access technology) transceivers in a wireless device; it is also common to find that at any given location, it is possible to access multiple RAT networks (due to overlapping coverage areas). For example, currently most wireless handset devices support both a GSM/GPRS (Global System for Mobile Communications/General packet radio service) and a UMTS (Universal Mobile Telecommunications System) interface. Often these devices attempt to maximize coverage by accessing the best available RAT. The carrier frequency used for GSM/GPRS operation is in the 900 MHz range while the carrier frequency used for UMTS operation is in the 1.9 GHz range. The two systems are thus substantially separated in carrier frequency and are unlikely to simultaneously suffer deep fades across the respective frequency bands of operation. In some cases, the wireless link (transmit, receive) endpoints (wireless device, base station) are collocated since the services are provided by the same operator, e.g., GSM/GPRS, UMTS. At any given location and time instant, it is possible that coverage is available for multiple RATs.

System and method of encoding and transmitting codewords


A receiver for use in a synchronous digital communication system wherein transmitted digital signal samples are modulated in accordance with a first constellation of modulated signal values. The receiver includes a phase locked loop for synchronizing digital sampling at the receiver with the received signal samples. The synchronism adjustment error is formed from a pseudo-error function which is a weighted combination of first and second errors, the first error being a function of the distance between received samples and the decisions made with respect thereto in the first constellation, the second error being a function of the distance between received samples and the decisions made with respect thereto in a second simplified constellation derived from the first constellation. A weighting is assigned to the second error which may, in one embodiment, be proportional to the first error.

1. Field of the Invention
The invention relates to a digital communications system comprising at least a transmitter and a receiver for transmitting a signal modulated on the basis of a first constellation, said receiver, which is intended to receive samples of said signal and make decisions with respect to said samples, further including a timing recovery device of the synchronous type which includes a phase-locked loop adjusted by means of an adjustment error.
The invention also relates to a receiver for digital modulations, intended to receive samples of a signal modulated on the basis of a first constellation and make decisions with respect to said samples, which includes a timing recovery device of the synchronous type which comprises a phase-locked loop adjusted by means of an adjustment error.
The invention finds highly significant applications in the field of synchronous communications. The clocks of the transmitter and receiver are in fact to be synchronized to optimize the sampling instants of the received signal.
2. Description of Related Art
Let us assume that a(nt) are the symbols transmitted by the transmitter at the rate T, x(nT+.tau.) is the signal sampled by the receiver with an offset of .tau., and h is the total transfer function of the transmission channel. The relation between transmitted symbols and received symbols can be expressed in the following manner: ##EQU1## In addition to the desired data a(nT)h(.tau.), there appears an intersymbol interference term which is a function of the offset .tau.. The error resulting therefrom in the received symbol will be used for correcting the offset .tau..
The article by Mueller and Muller entitled "Timing Recovery in Digital Synchronous Data Receivers", published in IEEE Transactions on Communications, Vol. 24, No. 5, May 1976, recommends to adjust the phase-locked loop by a function f derived from the channel response h and which symmetrizes the response at steady-state, that is to say, for .tau. verifying f(.tau.)=0. In practice, the channel response h is not available and thus an estimate of this function is used which itself is derived from samples received by the receiver. The estimate used is, for example, given by the following expression: EQU .epsilon..sub.n =Ree*.sub.n-1 (d.sub.n -d.sub.n-2)!
where
Re() indicates the real part of the complex number in brackets, PA1 d.sub.n is the decision made on the n.sup.th received sample x.sub.n, PA1 e.sub.n =x.sub.n -d.sub.n is the corresponding error for sample x.sub.n, PA1 and e.sub.n * is the conjugate of e.sub.n. PA1 said first error, when said first error is lower than a given threshold, PA1 and, if not, said second error. PA1 comparing means for comparing the coordinates of the received samples with the boundaries of said constellation, PA1 synchronization detection means, PA1 storage means for storing coordinates of said adjustment error, PA1 computing means for computing said adjustment error based upon the stored coordinates, PA1 check means for checking said storage means for storing a coordinate of said adjustment error only if the corresponding coordinate of the received sample is situated outside the boundaries of the first constellation, when said receiver is not synchronized.
This estimate in effect leads to symmetrizing the channel response at steady-state, since EQU Reh(T+.tau.)-h(-T+.tau.)!=0
This estimate .epsilon..sub.n is a function of the error e.sub.n-1 caused in sample x.sub.n-1. However, its use as an adjustment error of the phase-locked loop of the timing recovery device of the receiver for modulations in a large number of states yields insufficient results. In effect, whereas the distance between two points of the constellation used becomes smaller when the number of states of the constellation increases, the probability of having a false decision and thus a false error estimate becomes greater.
It is an object of the invention to overcome this disadvantage.

Digital communications receiver that includes a timing recovery device


A sole device with air cushion function includes a sole body having a receiving space and a sealing film, the sealing film sealing the receiving space, the sole body having a plurality of supporters formed at a top side thereof; and an air valve set assembled in the receiving space, the air valve set having a main valve, a sub valve and at least one air duct. Under this arrangement, the air flows into the sole body via the air valve set and a motion of a foot of a user.

1. Field of the Invention
The present invention relates to a sole device, and more particularly to a sole device with air cushion function.
2. Description of Related Art
Referring to FIGS. 1A-2B, a conventional sole device with air cushion function comprises a sole body, a plurality of first supporters A1 and a plurality of second supporters A2. Each first supporter A1 is extended from the sole body toward a foot of a user. A space with air is defined between the first supporters A1. Clearly, each first supporter A1 and each second supporter A2 are crossed with each other, so as to support the foot. However, the first supporters A1 or the second supporters A2 are usually made of hard rubber so as to stably support the foot; as a result, after long-term use, the supporters would be deformed or sunken. Therefore, the conventional sole device with air cushion function would make the user uncomfortable, after long-term use. In order to overcome said issue, another conventional sole device with air cushion function comes to the world.
Referring to FIGS. 3A-3B, another conventional sole device with air cushion function comprises a receiving space formed therein. The receiving space is stuffed with an EVA (Ethylene Vinyl Acetate) material so as to define an EVA layer A3. However, after long-term use, an elasticity of the EVA layer A3 would be decayed. In order to overcome said issue, another conventional sole device with air cushion function comes to the world.
Referring to FIGS. 4A-4B, another conventional sole device with air cushion function comprises a sole body having a plurality of supporting ribs A4. A buffer groove A5 is defined in each supporting rib A4, so as to provide a buffer for each supporting rib A4 when each supporting rib A4 is compressed. Referring to FIG. 4B, a cross-sectional area of the buffer groove A5 is hammer-shaped. However, an elasticity of each supporting rib A4 is still limited; in addition, because of the buffer groove A5 each supporting rib A4 is hollow, so that each supporting rib A4 is flabby. In order to overcome said issue, the other conventional sole device with air cushion function comes to the world.
The other conventional sole device with air cushion function comprises a sole body. The sole body is made of anti-friction material. A plurality of posts is defined at a front end of the sole body. A plurality of posts is defined at a rear end of the sole body. A hexagonal area is defined at a portion of the sole body which is corresponding to an inner side of the foot. The hexagonal area is made of anti-friction material or anti-skid material. An outer periphery is made of anti-friction material. Therefore, the whole sole body is anti-friction material and anti-skid. However, although the sole body is anti-friction material and anti-skid, the sole body would make the user uncomfortable; in addition, an elasticity of the sole body would be decayed.
Furthermore, referring to said conventional sole devices, the air is not flowable in the sole body, so that the user would be uncomfortable.
The present invention has arisen to mitigate and/or obviate the disadvantages of the conventional sole devices.


Provided is an electric device capable of suppressing vibration of a battery pack. Included are: a first housing 21 accommodating a load portion that consumes electric power; a second housing 22 having one end portion connected to the first housing 21 and another end portion to which a battery pack 9 is connectable; and an elastic member 40 interposed between the first housing and the second housing. The first housing includes a first restricting portion 42 positioned away from the elastic member, and the second housing includes a second restricting portion 44 positioned away from the elastic member and engageable with the first restricting portion. In a case where the second housing is urged to be separated from the first housing, the elastic member is deformed and the first restricting portion and the second restricting portion are engaged with each other to prevent separation.

An electric device driven by a battery pack as a power source is known in the art. There has been proposed a structure where an elastic member is attached to a main body of the electric device in contact with the battery pack in order to restrain vibration transmitted to the battery pack. The vibration occurs due to operation of an end bit attached to the electric device (see Patent Literature 1).


Within a system comprising a processor and a memory, a method that includes, via the processor, receiving a schema as an input. For each element in the schema, the method can include parsing the element from the schema, validating the parsed element, generating a parse tree node for the parsed element, and adding the parse tree node to a schema parse tree. The method further can include outputting the schema parse tree.

The embodiments disclosed within this specification relate to validation of a schema that itself is used to validate one or more document instances.
The use of XML messages to relay information, especially via Internet based protocols, is prevalent. Essentially, an XML message is an XML document communicated via a suitable communication medium. With the proliferation of XML, and the increased complexity Internet communications, XML messages also are becoming increasingly complex.
XML schema oftentimes are used to specify the content of XML documents. An XML schema is a description of a type of XML document, typically expressed in terms of constraints on the structure and content of documents of that type, above and beyond the basic syntactical constraints imposed by XML itself. In illustration, XML schema generally are expressed using some combination of grammatical rules governing the order of elements, Boolean predicates that the content must satisfy, data types governing the content of elements and attributes, etc.

This patent is subject to a terminal disclaimer.

Validation of schema and schema conformance verification

INTERNATIONAL BUSINESS MACHINES CORPORATION


According to one embodiment of the invention, a chemical mechanical polishing system includes a platen having a first surface adapted to couple a polishing pad thereto. The first surface includes a generally circular center portion and an annular portion surrounding the generally circular center portion. The generally circular center portion encloses an area and has an attachment surface area that is less than the area enclosed by the generally circular center portion. The attachment surface area is adapted to couple an inner portion of the polishing pad to the platen.

Chemical mechanical polishing ("CMP") is a semiconductor wafer planarizing and/or polishing procedure widely used in the fabrication of semiconductor wafers. As the name implies, there are two components to the process: chemical and mechanical polishing. Chemical polishing involves the introduction of chemicals that dissolve imperfections and impurities present upon the wafer. Mechanical polishing involves rotating the wafer upon an abrasive "polishing pad" in order to planarize the wafer. Generally, the wafers are mounted upside down on a wafer carrier and rotated above a polishing pad sitting on a platen. The platen is also rotated. Typically, a slurry containing both chemicals and abrasives is introduced upon the pad. The more defect-free the pad is, the less defects that are imparted to the wafer and the longer the pad lasts.
One problem that may occur during the course of many CMP cycles is delamination of the platen coatings around the edge of the platen. This may cause the pad to adhere poorly to the edge and allow the pad to peel up at the edges, which creates a hazard for the wafers.
Another problem is that replacing a pad is not as easy as it sounds since the forces imparted to the pad during the CMP process causes the pad to adhere to the platen with more strength than initially existed when the pad was adhesively coupled to the platen. This may lead to wasted time in removing the pad as well as exacerbating the delamination problem noted above.

Abstract: According to one embodiment of the invention, a chemical mechanical polishing system includes a platen having a first surface coupling a polishing pad thereto. The first surface includes a generally circular center portion and an annular portion surrounding the generally circular center portion. The generally circular center portion encloses an area and has an attachment surface area that is less than the area enclosed by the generally circular center portion. The attachment surface area is coupling an inner portion of the polishing pad to the platen.


In a driving power IC including a starter circuit comprising a main-switch (MS) transistor, a starter switch (SS) for starting the MS transistor and a start resistor (or a resistor element) SR, the start resistor is created on a field insulation film. In a periphery area of a chip for integrating the driving power IC, that is, on a semiconductor substrate""s surface beneath the field insulation film, field limiting rings (FLRS) are created, enclosing an active area in a multiplexed state. The resistor element is extended from a start edge on the inner side of a group of said field limiting rings to an end edge on the outer side of the group, having a zigzag shape. The electric potentials appearing at portions of the start resistor along a straight line connecting the start edge to the end edge and the electric potentials appearing at portions on the surface of the semiconductor substrate which correspond to the portions on the start resistor agree with each other, or the latter potentials are approximately close to the former potentials.

In general, the present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. More particularly, the present invention relates to an effective technique applied to a technology of putting a switching regulator used as a direct-current regulated power supply in an IC (Integrated Circuit).
A direct-current regulated power supply is used for driving electronic devices such as a personal computer and a hand phone or electronic circuits with a high degree of precision and in accordance with specifications. A switching direct-current regulated power supply also referred to as a switching regulator is known as one of direct-current regulated power supplies. A switching regulator once rectifies an alternating-current input voltage into a direct-current voltage and then converts the direct-current voltage back into an alternating-current voltage by using an on/off circuit comprising transistors before again rectifying the alternating-current voltage into a final direct-current output by using a rectification circuit. Control methods adopted by a switching regulator include a pulse-width control technique of controlling the width of pulses generated within a fixed period of time and a frequency control technique of varying the number of generated pulses in accordance with the magnitude of a load.
In the IEEE Transactions on Electron Devices, Vol. 44, No. 11, November 1997, pp 2002 to 2010, there is described a technology of putting a portion of a switching regulator in an integrated circuit. This reference discloses an SJT (Spiral Junction Termination) structure wherein, during a process of putting the switching regulator in an integrated circuit, a resistor element is formed into a spiral shape, and its center portion is connected to a high electric potential while its circumferential portion is connected to the ground electric potential. The resistor element having such a spiral shape is created in an active area.
In Japanese Patent Laid-open No. Hei 9(1997)-186315, on the other hand, there is disclosed an insulated gate bipolar transistor (IGBT) for use in an inverter for reducing a drop in strength to withstand a voltage. This reference discloses typical creation of an over-voltage-suppressing diode by providing an FLR (Field Limiting Ring) on the surface portion of a semiconductor substrate (drift layer) on the circumference (periphery area) of a semiconductor chip and creating the diode on the drift layer with an oxide film sandwiched between the drift layer and the diode. In this example, distribution of electric potentials is optimized to suppress a drop in strength to withstand a voltage by making the device dimensions of the FLR equal to 4/5 times the device dimensions of the over-voltage-suppressing diode.
Nowadays, the alternating-current voltage of the commercial power supply varies from country to country. For example, the alternating-current voltage in Japan is 100 V or 200 V while the voltage is 115 V in the US and 220 V to 240 V in Europe.
A switching regulator has a main switch and a starter circuit for activating the main switch. The starter circuit comprises a starter switch and a start resistor (a resistor element).
In a switching regulator connected to a direct-current power supply operating by rectification of a 240V alternating-current input, a transistor requires a maximum withstand voltage of about 700 V. In order to deliver the switching regulator as a product assuring this maximum withstand voltage, it is necessary to set a design value of the main switch and the starter switch at about 750 V.
A breakdown of any of transistors comprising the main and starter switches is caused by a high voltage applied to the transistor. It is desirable to devise such main and starter switches that an inevitable breakdown occurs on a portion other than the surface of a device with a large area. Concretely, it is desirable to avoid a breakdown of a start resistor element which has a small area and is prone to a breakdown occurring on the surface. However, it is inevitable to have a breakdown occur in a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a power MISFET (Metal Insulator Semiconductor Field Effect Transistor), which have a large area and are difficult to fall into a state of breakdown occurring on the surface. Thus, if the withstand voltage of a power MISFET is set in the range 750 V to 800 V, it will be desirable to set the withstand voltage of a start resistor at a value of at least 800 V.
Since there is no case in which a start resistor with such a withstand voltage of at least 800 V is included in an integrated circuit, however, it is necessary to launch new developments.
The inventor of the present invention studied the creation of a resistor into a spiral shape as is disclosed in the reference cited above. In an experiment conducted as part of the study, the inventor discovered a phenomenon in which, as the voltage applied to the resistor element increases, its resistance decreases, allowing a large current to flow. Further, since the resistor element is formed in an active region of a semiconductor substrate in which IC is formed, the IC chip increases in size and manufacturing cost increases. In dependence on the layout of the resistor element, a parasitic interaction with another device adjacent to the resistor element may probably occur.
In order to solve the problems described above, the inventor of the present invention has proposed a configuration wherein a resistor element having a zigzag shape is provided on a field insulation layer created on a periphery area of a semiconductor chip in a direction from the center of the semiconductor chip to the circumference thereof and has proposed a technology of preventing the field insulation layer from breaking down due to application of a high voltage. The zigzag portion is extended to cross each ring portions of a plurality of FLRs enclosing an active area of the semiconductor chip in a multiplexed state.
In such a resistor element having a zigzag shape, however, the following problems have been identified. FIGS. 26(a) to 26(c) are diagrams showing results of an analysis of an already proposed technology. To be more specific, FIG. 26(a) shows a model of a zigzag pattern of a resistor layer used as a start resistor SR. FIG. 26(b) shows a cross section of a portion including a resistor layer and FLRs of a driving power IC. FIG. 26(c) shows graphs representing the electric potential of a resistor layer and the electric potential of a semiconductor substrate surface including an FLR. It should be noted that, while 5 FLRs P1 to P5 are described in this analytical study, the number of FLRs is not limited to 5.
In other words, FIG. 26(b) is a diagram showing a cross section of a periphery portion of a semiconductor chip in which a driving power IC is created. The figure shows a semiconductor substrate 1 made of n+ silicon with an nxe2x88x92epitaxial layer 2 created on the main surface thereof.
In the semiconductor chip, a periphery area is located on the periphery of the semiconductor substrate""s active area in which devices such as transistors are created. On the main surface of the epitaxial layer 2 of this periphery area, a field insulation film 3 made of LOCOS (Local Oxidation of Silicon) is created. On the main surface of the semiconductor substrate of the periphery area, that is, on the main surface of the epitaxial layer 2, five field limiting rings (FLRs) 13 are created, enclosing the active area not shown in the figure. Made of a p diffusion layer, the five FLRs 13 are distinguished from each other by assigning reference notations P1 to P5 thereto respectively. It should be noted that a p diffusion layer P0 held at the electric potential GND of the ground is created on the inner side of the FLR P1.
In addition, on the edge of the semiconductor chip, a guard ring 14 is provided. To be more specific, the guard ring 14 is created on the surface of the epitaxial layer 2 under an insulation film 24, which is thinner than the field insulation film 3 and provided at a location separated away from the field insulation film 3. The guard ring 14 is created in a n+ diffusion area having a ring shape. The n+ diffusion area is formed by diffusing impurities into the main surface of the epitaxial layer 2 at a high concentration.
A resistor layer 20 made of a poly-silicon layer is formed on the field insulation film 3. The surface of the resistor layer 20 is covered by an interlayer insulation film 9. A contact hole 21 is formed by boring a location on the interlayer insulation film 9 above the p diffusion layer P0 and a contact hole 22 is formed by boring a periphery location on the interlayer insulation film 9. A contact hole 23 is formed at a location outside the edge of the field insulation film 3. The contact hole 23 is extended to a location outside the insulation film 24, which is thinner than the field insulation film 3 and provided at a location separated away from the field insulation film 3 as described above.
Conductor films 25 to 28 each having a ring shape are created along the periphery of the semiconductor chip on the interlayer insulation film 9. The conductor film 25 is created on the inner side of the periphery area, that is, on the active-area side of the periphery area. The conductor film 25 also fills up the contact hole 21, being electrically connected to the resistor layer 20. The conductor film 26 is created at a location adjacent to the conductor film 25 on the outer side of the conductor film 25 and is electrically connected to the p diffusion layer P0 held at the ground electric potential GND used as a reference electric potential. The conductor film 27 is created above the FLR 13 (P5) on the outermost circumference, being electrically connected to the FLR 13. The conductor film 28 also fills up the contact holes 22 and 23 and is electrically connected to the resistor layer 20 and the guard ring 14.
As an applied voltage is increased in the group of FLRs 13 described above, a depletion layer extends from an FLR 13 on an inner circumference to an FLR 13 on an outer circumference before an avalanche breakdown occurs, resulting in a punch-through structure and, eventually, a breakdown occurs at a pn junction of the FLR 13 on the outermost circumference. By providing a group of FLRs 13 as described above, the strength to withstand a voltage can be increased to a product of a punch-through voltage and the number of FLRs 13. Thus, the withstand voltage of the start resistance SR is equal to the sum of the withstand voltage of the portion comprising the FLRs 13 and a withstand voltage due to, among other factors, the thickness of the field insulation film 3. As a result, the start resistance SR has a total withstand voltage of at least 800 V.
A resistor-layer portion corresponding to the contact hole 21 is the start edge 31 of the resistor element serving as the start resistor SR and a resistor-layer portion corresponding to the contact hole 22 is the end edge 32 of the start resistor SR. A pattern of the resistor layer 20 serving as the resistance SR starting from the start edge 31 to ending at the end edge 32 displays a zigzag shape which has a fixed amplitude and changes the direction at fixed pitch intervals as shown in FIG. 26(a). In FIG. 26(b), however, the zigzag shape is not explicitly shown for the sake of simplicity.
By forming the resistor layer 20 into a zigzag pattern as described above, the length of the resistor layer 20 increases, resulting in a greater heat-dissipating area and a reduced electrical-field intensity. As a result, it is possible to avoid destruction caused by heat dissipated by the resistor element and destruction caused by an excessively strong electric field.
In addition, by forming the resistor layer 20 into a zigzag pattern, it is possible to provide a configuration wherein the resistance per unit length of the resistor layer 20 is increased over the resistance per unit length of a resistor having a shape like a straight line connecting the start edge 31 to the end edge 32.
When a high electric potential is applied to the start resistor SR, electric fields are generated in the start resistor SR and the FLRs 13. By providing the start resistor SR on the field insulation film 3 including an area for placing the FLRs 13 as described above, however, a difference between the electric field generated in the start resistor SR and the electric field generated in the FLRs 13 is reduced. Thus, the field insulation film 3 is relieved from an electric field applied thereto. As a result, destruction of the field insulation film 3 can be avoided.
In accordance with an analysis performed by the inventor and others, the electric potential of the start resistor SR does not exhibit the same variations as the electric potential of the semiconductor-substrate surface including the FLRs 13 as shown in FIG. 26(c). It has also been discovered that the difference between the potentials reaches a maximum value at the FLR 13 on the outermost circumference. This is because, even though the resistor layer 20 having a uniform thickness is formed into a uniform-width zigzag shape varying the direction at fixed pitch intervals from the start edge 31 to the end edge 32, the electric potential varies like a straight line as if the resistor layer 20 were replaced by a straight-line resistor connecting the start edge 31 to the end edge 32 as shown in FIG. 26(c). On the other hand, it has also been discovered that the potential on the surface of the semiconductor substrate, that is, the potential on the boundary surface between the field insulation film 3 and the semiconductor substrate 1 on the portions of the FLRs 13, changes like a staircase as shown in FIG. 26(c) and, in an area on the outer-circumference side of the FLR 13 on the outermost circumference, the potential changes like a curve.
In the portion of the FLR 13 on the outermost circumference, a strong electric field is generated. Electrons of electron-hole pairs generated in bulk are strongly attracted by a poly-silicon layer serving as the resistor layer 20 and many of the attracted electrons are trapped in the field insulation film 3. The electric charge inverts the surface of the nxe2x88x92epitaxial layer 2 between the FLRs 13 on the surface of the semiconductor substrate into a p type, causing a channel leak reducing the strength to withstand a voltage.
The inventor and others conducted a measurement experiment on a driving power IC. FIG. 28 is a diagram showing a measurement circuit of a driving power IC (power MOS chip) The driving power IC has a structure wherein a main switch MS, a starter switch SS and a start resistor SR are embedded monolithically on a silicon semiconductor substrate even though the driving power IC is not specially limited to such a structure. The main switch MS includes a main MOS (MAIN-MOS) comprising 2,270 cells and a current-sensing MOS (CS-MOS) comprising 2 cells for sensing a current. Four electrodes of the main switch MS are connected to a drain terminal DRAIN, a source terminal SOURCE, a gate terminal GATE and a current-sensing terminal CS respectively.
The starter switch SS is a start MOS (START-MOS) comprising 60 cells even though the starter switch SS is not specially limited to such a MOS. 3 electrodes of the starter switch SS are connected to the drain terminal cited above, a start-MOS gate terminal and a start-MOS source gate terminal respectively. The start-MOS gate terminal of the starter switch SS is connected to the common drain terminal by a series start resistor SR of typically 2 Mxcexa9.
With a voltage Vds applied between the common drain terminal of the driving power IC and the other terminals of the main switch MS and the starter switch SS, results of measuring a current Ids flowing from the other terminals of the main switch MS and the drain terminal are represented by a graph shown in FIG. 27.
FIG. 27 is a diagram showing a comparison of a graph representing data obtained at an initial time (at 0 hours) with a graph representing data obtained after an experiment, that is, after a time lapse of 48 hours, with the experiment conducted on a driving power IC in an environment at an ambient temperature of 150xc2x0 C. and a Vds value of 750 V. The graphs represent relations between the voltage (Vds) and the current (Ids) with the horizontal and vertical axes indicating values of the former and the latter respectively.
A discovery is obvious from the curves. That is, the curve representing data obtained at an initial time reveals occurrence of an avalanche breakdown at an applied voltage of about 800 V. On the other hand, the curve representing data obtained after the experiment reveals a phenomenon that, as the applied voltage exceeds a level of about 600 V, a channel-leak current flows, resulting in an increase in current and, at an applied voltage of about 800 V, an avalanche breakdown occurs.
Then, prior to a study of a structure for avoiding such an undesirable phenomenon, a simulation was conducted on an electric potential of the resistor element and an electric potential appearing on the surface of the semiconductor substrate to give the potential curves shown in FIG. 26(c).
The inventor invented the present invention in thinking of making the electric potentials appearing at portions of the start resistor (the resistor element) SR and the electric potentials appearing at portions on the surface of the semiconductor substrate which correspond to the portions on the start resistor (the resistor element) SR agree with each other, or making the latter potentials are approximately close to the former potentials.
It is thus an object of the present invention addressing the problems described above to provide a semiconductor device including an embedded resistor element having a high withstand voltage and a high resistance value and to provide a method of manufacturing the semiconductor device.
It is another object of the present invention to provide a semiconductor device provided with an embedded resistor element having a high withstand voltage and a high resistance value and used for a switching regulator and to provide a method of manufacturing the semiconductor device.
It is a further object of the present invention to provide a technology of allowing a resistor element having a high withstand voltage and a high resistance value to be manufactured without increasing the size of a semiconductor device including the resistor element.
The above and other objects as well as novel characteristics of the present invention will become more apparent from a careful study of this specification with reference to accompanying diagrams.
Outlines of representatives of the present invention disclosed in this specification are briefly described as follows.
1: A semiconductor device comprises:
a semiconductor substrate including an active area, in which a transistor is created, and a periphery area enclosing the active area and having a surface covered by a field insulation film;
a plurality of field limiting rings (FLRs) which are provided on the surface of the semiconductor substrate in the periphery area and enclose the active area in a multiplexed state;
a resistor element created on the field insulation film, being extended in a direction from an inner side of a group of said FLRs to an outer side of the group and connected between a first electrode having a low electric potential of the transistor and a second electrode having a high electric potential of the transistor where the first electrode is a start edge on the inner side of the group of said FLRs and the second electrode is an end edge on the outer side of the group of said FLRs;
an interlayer insulation film covering the resistor element; and
a field plate created on the interlayer insulating film at a location corresponding to the FLR on the outermost circumference and electrically connected to the FLR on the outermost circumference,
wherein, if the resistor element were replaced by a hypothetical equivalent resistor element having a shape of a straight segment connecting the start and end edges of the resistor element, a value of resistance per unit length in a portion of the segment would be different from a value of resistance per unit length in another portion of the segment.
Typically, electric potentials appearing at portions of the hypothetical equivalent resistor element having the shape of a straight segment connecting the start and end edges of the resistor element agree with or are approximately close to electric potentials appearing at portions of the surface of the semiconductor substrate, which correspond to the portions of the hypothetical equivalent resistor element. The sheet resistance of the resistor element is 10 kxcexa9/xe2x96xa1 or less.
An implementation of the semiconductor device described above has:
a first terminal to which a signal is supplied;
a second terminal to which a reference electric potential is supplied;
a control terminal;
a current-sensing terminal;
a starter-circuit control terminal for a starter circuit;
a second starter-circuit terminal to which a reference electric potential of the starter circuit is supplied;
a main-switch transistor serving as a main switch and comprising: a main-switch first electrode connected to the first terminal; a main-switch second electrode connected to the second terminal; a main-switch control electrode connected to the control terminal; and a current-sensing electrode connected to the current-sensing terminal and used for sensing a current output by the main-switch first electrode;
a starter-switch transistor serving as a starter switch and comprising: a starter-switch first electrode connected to the first terminal; a starter-switch second electrode connected to the second starter-circuit terminal; and a starter-switch control electrode connected to the control terminal; and
a start resistor connected in series between the first terminal and the starter-switch control electrode,
wherein the start resistor has the same configuration as the resistor element employed in the semiconductor device described above.
To put it concretely, the resistor element has a zigzag portion between the start and end edges of the resistor element and the zigzag portion has a zigzag pitch varying from location to location. The resistance values per unit length of the resistor segments on the inner and outer sides sandwiching the field limiting ring on the outermost circumference are different from each other.
The configuration of the resistor element has a variety of implementations as follows:
a: In addition to the zigzag portion, the resistor element has a wide zigzag portion with a large zigzag width and a narrow zigzag portion with a small zigzag width.
b: The resistor element has a zigzag portion and a straight portion along the hypothetical segment between the start and end edges of the resistor element.
c: The resistor element has a resistor-line width varying from location to location.
d: The resistor element is a resistor element having a shape like a straight line along the hypothetical segment and a line width at a specific location different from the rest.
e: The resistor element is made of a poly-silicon layer doped with impurities as an additive.
f: The resistor element is made of a metallic portion and a poly-silicon layer doped with impurities as an additive and connected to the metallic portion.
g: The resistor element has a sheet-resistance value varying from location to location.
h: The thickness of the field insulation film, on which the resistor element is created, is set in the range about 3 to 5 xcexcm to reduce the intensity of an electric field developed between a location on the resistor element and the corresponding location on the surface of the semiconductor substrate.
Such semiconductor devices are fabricated by adopting the following methods.
A method is adopted for manufacturing a semiconductor device comprising:
a transistor created in an active area of a main surface of a semiconductor substrate; and
a plurality of field limiting rings provided to enclose the active area in a multiplexed state.
The method comprises processes of:
creating the field limiting rings enclosing the active area of a main surface of the semiconductor substrate in a multiplexed state;
creating a field insulation film at a predetermined location and in a periphery area of the semiconductor substrate; and
creating a resistor layer on the field insulation film, being extended in a direction from a start edge on an inner side of a group of said field limiting rings to an end edge on an outer side of the group to be used for creating a resistor element connected to the transistor.
In the method described above, the resistor layer is created into such a pattern that, if the resistor element were replaced by a hypothetical equivalent resistor element having the shape of a straight segment connecting the start and end edges of the resistor element, a value of resistance per unit length in a portion of the segment is different from a value of resistance per unit length in another portion of the segment.
The resistor layer is created into such a pattern that electric potentials appearing at portions of the hypothetical equivalent resistor element having the shape of a straight segment connecting the start and end edges of the resistor element agree with or are approximately close to electric potentials appearing at portions of the surface of the semiconductor substrate, which correspond to the portions of the hypothetical equivalent resistor element.
Any of the following patterns can be created on the resistor layer by creation of a conductor layer, patterning and deposition using a mask: a zigzag pattern, a zigzag pattern with a zigzag pitch at a specific location different from the rest, a zigzag pattern with a zigzag width at a specific location different from the rest, a pattern combining any of the above patterns with a straight-line portion, any of the above patterns with a resistor-line width varying from location to location and a straight-line pattern with a resistor-line width varying from location to location.
The transistor is created as a field effect transistor and, in a process to form a gate electrode of the transistor from a poly-silicon layer, the resistor layer is created at the same time from the poly-silicon layer and, if necessary, the value of sheet resistance is adjusted by doping with impurities as an additive.
2: In configuration 1 described above, the resistance of the hypothetical equivalent segment resistor having the shape of a straight line connecting the start and end edges of the resistor element is set so that the resistance value per unit length varies along the segment like a staircase that electric potentials appearing at locations on the resistor element agree or are approximately close to electric potentials appearing at locations on the surface of the semiconductor substrate.
3: In configuration 1 or 2 described above, each of the field limiting rings is connected to the resistor element""s portion corresponding to the field limiting ring.
In the manufacture of such a semiconductor device, after creation of a field limiting film, a field insulation film, a resistor layer, and an interlayer insulation film covering the resistor layer, contact holes are formed by boring the interlayer insulation film and conductors are selectively created on the interlayer insulation film to electrically connect the field limiting rings to the resistor element""s portions corresponding to the respective field limiting rings through the contact holes.
In accordance with a first configuration 1 described above,
(a) Electric potentials appearing at locations on the hypothetical equivalent segment resistor having the shape of a straight line connecting the start and end edges of the resistor element agree or are approximately close to electric potentials appearing at locations on the surface of the semiconductor substrate which correspond to the respective locations on the hypothetical equivalent segment resistor. Thus, hole-electron pairs generated in bulk are not attracted by an electric field to a specific location even if a high voltage is applied to the resistor element serving as a start resistor. As a result, generated pairs of holes and electrons of the pairs recombine, neutralizing each other. Therefore, no channel is developed between the field limiting rings so that the withstand voltage is stabilized, preventing the strength to withstand a voltage from deteriorating.
(b) By setting the sheet resistance of the resistor layer on which the start resistor is created at 10 kxcexa9/xe2x96xa1 or smaller, it is possible to avoid an increase in temperature caused by a decrease in resistance. Thus, the amount of dissipated heat at a certain applied voltage can be stabilized. In addition, by forming the resistor layer into a zigzag shape, it is possible to increase the length of the resistor layer. With the length increased, the area dissipating heat is widened so that the heat dissipation efficiency is also raised. As a result, it is possible to avoid a destruction incident caused by fusion of the poly-silicon layer serving as the resistor layer due to dissipated heat.
(c) With schemes (a) and (b) described above, it is possible to provide a highly reliable semiconductor, that is, a driving power IC used in a switching regulator.
(d) Since the start resistor is created on the field insulation film on the periphery area instead of the active area, the size of the semiconductor chip can be made small and the cost of manufacturing the semiconductor device can also be reduced in comparison with a structure wherein the start resistor is created on the active area.
In accordance with configuration 2 described above, it is possible to prevent the strength to withstand a voltage from deteriorating and avoid a destruction incident caused by heat dissipated by the poly-silicon layer serving as the resistor layer as is the case with configuration 1.
In accordance with configuration 3 described above, the field limiting rings are electrically connected to the resistor element""s portions corresponding to the respective field limiting rings so that, at each of the connections, the electric potential of the field limiting ring is equal to the electric potential of the resistor element""s portion electrically connected to the field limiting ring. Thus, electric potentials appearing at locations on the segment resistor agree or are approximately close to electric potentials appearing at locations on the surface of the semiconductor substrate which correspond to the respective locations on the segment resistor as is the case with configuration 1. As a result, it is possible to avoid a destruction incident caused by heat dissipated by the poly-silicon layer serving as the resistor layer

Semiconductor device switching regulator used as a DC regulated power supply


A method of needling a web comprises the steps of continuously supplying the web to needles, reciprocating the needles to stitch the web supplied to the needles and to release the stitched web, moving the released stitched web step by step by subjecting the released stitched web to a weight load, and then continuously withdrawing the released stitched web. An apparatus for carrying out this method comprises a dancing roller arranged to exert the weight load between a stitch base and means for continuously withdrawing the stitched web.

1. Field of the Invention
This invention relates to a method for needling a web by means of needles repeatedly stitching into the web, where the web continuously supplied to the needles is moved on with respect to the needles step by step during the release by the needles between the needle impingements and is then withdrawn, and to a device for carrying out the method.
2. Description of the Prior Art
In known needling machines the feed of the web, which during the needling process is guided between a stitch base and a stripper, is effected by a continuously driven discharge roller. Despite this continuously driven discharge roller a stepwise conveyance of the web with respect to the needle area is obtained, because the web is retained with respect to the discharge roller by the impinging needles and is moved on only during its release by the needles between the succeeding needle impingements. The continuously driven discharge roller therefore necessarily involves a stretching of the web, where the withdrawal speed depends on the admissible degree of stretching of the web, on the stitching frequency of the needles and on the needle stroke, and thus on the period of the release of the web by the needles. Apart from the fact that these parameters limit the withdrawal speed, the needling result is impaired considerably by the tensile stress of the web increasing with the withdrawal speed during the needle impingement. In this connection it should also be considered that with increasing distribution density of the needles the tensile stress of the web is increased, because with increasing number of needles stitching into the web the bending elasticity of the individual needles can less and less be utilized for a resilient retainment of the web with respect to the discharge roller.


The effects of suppressing c-fos oncogene expression on drug or radiation resistant mammalian cells are described. A2780S human ovarian carcinoma cells with resistance to actinomycin D were isolated and the resultant A2780AD cells exhibited the MDR phenotype. A hammerhead ribozyme designed to cleave fos RNA cloned into the pMAMneo plasmid was transfected into A2780AD cells. Induction of the ribozyme resulted in decreased expression of c-fos, followed by that of mdr-1, c-jun, and p53. Reversal of the MDR phenotype by the anti-mdr ribozyme occurred one-fourth as rapidly as that induced by the anti-fos ribozyme. These studies demonstrate the primacy of the c-fos oncogene in maintaining the resistant phenotype in human cancer cells. Thus, down regulation of fos/jun will make resistant cancer cells more sensitive to conventional treatment, i.e., cancer chemotherapeutic agents and/or radiation.

Despite tremendous strides in understanding the molecular basis of cancer (1),.sup.1 treatment of human cancer is still limited by the toxicity of chemotherapeutic agents and the development of intrinsic or acquired resistance to these drugs. Cis-diamminedichloroplatinum (II) (cisplatin) is one of the most widely-used anticancer agents, active in the treatment of ovarian, testicular, head-and-neck, non-small cell lung and brain tumors, among others (2). However, the rapid development of resistance to cisplatin represents an important challenge to clinicians and laboratory investigators alike. Therefore, understanding the biochemical and molecular basis of cisplatin resistance may potentially result in the development of rational approaches to circumvent this problem. At the core of understanding cisplatin resistance lies the realization of both the similarities and differences between the mechanisms of cisplatin action and resistance and that of other chemotherapeutic agents. Cisplatin-resistant cells display a unique cross-resistance pattern to multiple agents, including anti-metabolites such as 5'-fluorouracil and methotrexate, DNA polymerase inhibitors such as azidothymidine (AZT), and topoisomerase inhibitors such as camptothecin and etoposide. This "atypical" multidrug resistance is both phenotypically and molecularly distinct from the "classical" multidrug resistance which may involve overexpression of the MDR-1 gene (3). FNT .sup.1 The bibliography precedes the claims.
A cursory review of the literature in cisplatin resistance quickly points to a potentially confusing array of mechanisms purported to be involved in this process, most of them seemingly disparate and unrelated. Recent advances in the workings of signal transduction in normal and cancer cells have led to a more cohesive picture of cellular pathways involved in the response to extracellular agents (e.g., growth factors, tumor promoters, viruses, and chemotherapeutic agents). This in turn has merged seemingly independent biochemical processes activated in response to various stimuli. An important molecular mechanism in cisplatin resistance concerns the c-fos proto-oncogene. The Fos protein dimerizes with the c-jun gene product to drive many important cell processes by transcriptional activation of AP-1-responsive genes (4). Numerous AP-1-responsive genes have been identified which participate in DNA synthesis and repair processes and which have been implicated in cisplatin resistance (5). These include metallothionein, DNA polymerase .beta., thymidylate synthase, topoisomerase II, and glutathione-S-transferase. Furthermore, the Fos/Jun heterodimers are thought to mediate the effects of H-ras activation following growth factor activation (6). And protein kinase C is a known participant in cellular signalling pathways leading to the activation of c-fos gene expression (4).

Modulation of drug and radiation resistant genes


In some embodiments an apparatus includes a higher order statistical signal processor to process a jittered digital signal, a diagonal line average unit to identify a distinct line in a signal output from the higher order statistical signal processor, and a peak detection unit to determine a peak value in response to an output of the diagonal line average unit and to provide a data rate signal as an output. Other embodiments are described and claimed.

High data-rate digital waves are widely used in digital data communications to send and receive data. A PCI (Peripheral Component Interconnect) Express bus system using high data-rate digital waves becomes a broadband interference source that decreases other communications such as wireless communication subsystems, for example. Radio communication performance in a computing platform can be degraded by high frequency noise sources such as, for example, PCI Express bus, clocks, and other wireless communication systems. A way of mitigating such interferences and degradations would be beneficial.

High speed digital waveform identification using higher order statistical signal processing