A lens-controlling device controls a first lens unit which moves for zooming and a second lens unit which moves for correcting the displacement of an image plane caused by zooming and for focusing. The lens-controlling device includes a memory which stores data for obtaining target-position information representing a target position to which the second lens unit is to be moved, the target position corresponding to a position to which the first lens unit is moved from a current position and a controller which generates the target-position information on the basis of the data and controls the movement of the second lens unit on the basis of position information of the first lens unit and the target-position information.

1. Field of the Invention
The present invention relates to an imaging apparatus which receives light.
2. Description of the Related Art
Cameras with built-in lenses are required to be smaller, and to record an image of an object at a position as close as possible to the camera. Accordingly, instead of mechanically moving a correcting lens and a variator lens in association with each other with a cam, a so-called inner-focus system is commonly used. In this system, the correcting lens is moved on the basis of lens cam data stored in a microcomputer in advance and representing trajectories of the correcting lens, and focusing is performed using the correcting lens.
FIG. 10 is a diagram showing the structure of a known inner-focus lens system. With reference to the figure, the system includes a fixed front lens 901, a zoom lens (also called a variator lens) 902 used for zooming (first lens unit), a diaphragm 903, a fixed lens 904, a focusing lens 905 (second lens unit) which serves as a correcting lens having a focus adjustment function and a function of correcting the displacement of an image plane caused by zooming (a so-called compensating function), and an imaging surface 906.
In the lens system shown in FIG. 10, the focusing lens 905 serves both the compensating function and the focus adjustment function. Therefore, even when the focal length is constant, the position of the focusing lens 905 for focusing on the imaging surface 906 varies depending the object distance. FIG. 11 is a graph obtained by plotting the position of the focusing lens 905 for focusing the object image on the imaging surface 906 versus focal length for different object distances. When zooming is performed, a trajectory corresponding to the object distance is selected from a plurality of trajectories shown in FIG. 11, and the focusing lens 905 is moved along the selected trajectory. Accordingly, the focused state is maintained during zooming.
In a lens system in which focusing is performed using a front lens, a focusing lens is provided separately from a zoom lens and the zoom lens and the focusing lens are mechanically connected to a cam ring. Accordingly, when the focal length is changed by manually rotating the cam ring, the lenses are reliably moved by the cam ring no matter how fast the cam ring is rotated. Since the zoom lens and the focusing lens move along an optical axis while sliding along cams formed on the cam ring, image blurring due to zooming does not occur as long as the focusing lens is at an in-focus position.
In comparison, in the above-described inner-focus lens system, information of the trajectories shown in FIG. 11 or information corresponding thereto (information representing the trajectories or functions taking lens position as a parameter) is stored in advance, and zooming is performed by moving the focusing lens along a trajectory selected from among the trajectories on the basis of the positions of the focusing lens and the zoom lens.
As is clear from FIG. 11, when the zoom lens is moved in the direction from telephoto to wide angle, the focused state can be maintained using the above-described trajectory tracing method since the trajectories converge toward the wide-angle end. However, when the zoom lens is moved in the direction from wide angle to telephoto, the trajectory to be traced by the focusing lens cannot be determined if the focusing lens is at a position where the trajectories converge, and therefore the focused state cannot be maintained by the above-described trajectory tracing method.
Accordingly, Japanese Patent No. 2795439 discloses a control method in which the focusing lens is repeatedly moved in a direction causing the image to go out of focus and then in a direction to adjust the focus on the basis of the information representing the focus state (in other words, the moving speed is varied) when the zoom lens is being moved for zooming. In addition, a method for increasing the accuracy of selecting the trajectory to be traced is also disclosed in Japanese Patent No. 2795439 (FIGS. 3 and 4). According to this method, the period of variation in a sharpness signal is varied by changing the amount of variation in a tracing speed depending on the object distance, the focal length, and the depth of field.
In the above-described control method for the zooming operation, focus detection is performed by a TV-AF method using a video signal from an imaging device. Therefore, processes are normally performed in synchronization with a vertical synchronizing signal.
On the other hand, as is clear from FIG. 11, when zooming is performed using the inner-focus lens system, the cam trajectories to be traced by the focusing lens are on substantially the same point at the wide-angle end for object distances in the range of several tens of centimeters to infinity. Therefore, when the TV-AF method is used, the cam trajectory to be traced cannot be selected accurately unless the zoom lens is moved to an area near the telephoto end.
In TV-AF, a signal detection period at which an AF evaluation value is obtained is equal to the period of the vertical synchronizing signal. Accordingly, as the zoom speed increases, the accuracy of determining the trajectory to be traced is degraded. Therefore, although actuators for focusing and zooming have recently been improved and made smaller, and inexpensive super-high-speed actuators have been developed, the potential of such actuators cannot be sufficiently exploited when the inner-focus lens system and the TV-AF method are used in combination, and hence, there is a limit to the zoom speed. Although high-speed zooming using super-high-speed actuators can be performed when the angle of view is adjusted in the standby mode, the zoom speed must be reduced in the recording mode in order to prevent image blurring.
In addition, when long-time exposure (recording), such as so-called slow shutter, is performed, the detection period of the AF evaluation value becomes equal to the exposure period, and the tracing accuracy is degraded even when the zoom speed is not high. Therefore, image blurring may occur when the trajectory is being determined and a long time is required for correcting the image blurring if zooming and panning are performed simultaneously. As a result, the imaging performance is degraded.
In addition, also when the contrast of the object is low or when the signal-to-noise (S/N) ratio is low due to low illumination, in the zooming operation, an accurate AF evaluation value cannot be accurately detected by the TV-AF method. Therefore, the trajectory-tracing performance is also degraded in these cases.


A thermal mass flow meter associated with an inclination sensor that detects an angle of inclination of at least one portion of a thermal mass flow sensor relative to at least one reference axis. Based upon the detected angle of inclination, the output signal of the mass flow meter that is indicative of the mass flow rate of fluid through the sensor may be compensated to account for any inaccuracies relating to the orientation in which the mass flow meter is installed. Inaccuracies for which compensation may be provided include thermal siphoning effects and fluid buoyancy effects. By compensating for such inaccuracies, the mass flow meter may be used in any orientation, and/or may be used in non-inertial (e.g., accelerating) environments. The flow meter may be used as a stand alone device, or incorporated in a thermal mass flow controller.

1. Field of the Invention
Aspects of the present invention are directed to the measurement and control of the rate of flow of a fluid, and more particularly to a thermal mass flow sensor that may be included in a thermal mass flow meter or a thermal mass flow controller, and that is associated with an inclination sensor.
2. Discussion of the Related Art
Thermal mass flow meters and thermal mass flow controllers are well known in the art. It is also well known in the art that the orientation of a thermal mass flow meter (or a thermal mass flow controller) may affect its performance. For example, due to a phenomenon termed the "recirculation effect," the accuracy of a thermal mass flow meter (or thermal mass flow controller) may vary considerably from one orientation to another. This recirculation effect is now briefly described with respect to a conventional thermal mass flow controller depicted in FIG. 1.
As illustrated in FIG. 1, thermal mass flow controller 100 includes a base 110 having a fluid inlet 120 and a fluid outlet 130, a thermal mass flow meter 140, a valve 150, and some associated control electronics 160. In the illustrated example, the thermal mass flow meter 140 includes a pressure dropping bypass 142 through which a majority of fluid flows, and a thermal flow sensor 146 through which a smaller portion of the fluid flows. The thermal flow sensor 146 includes a sensor inlet portion 146A, a sensor outlet portion 146B, and a sensor measuring portion 146C about which two resistive coils or windings 146D, 146E are disposed.
In operation, electrical current is provided to the two resistive windings 146D, 146E which are in thermal contact with the sensor measuring portion 146C. The heat generated by the resistive windings 146D, 146E is used to heat the fluid flowing therein to a temperature that is above the temperature of the fluid flowing through the bypass 142. As known to those skilled in the art, the rate of flow of fluid in the flow sensor 146, which is proportional to the rate of flow of fluid through the mass flow controller 100, may be determined in a number of different ways, such as, by a difference in the resistance of the resistive windings, by a difference in the amount of energy provided to each resistive winding to maintain each winding at a particular temperature or at a particular temperature above ambient temperature, etc. Examples of the ways in which the flow rate of a fluid in a thermal mass flow meter may be determined are described, for example, in commonly owned U.S. Pat. No. 6,845,659 B2, which is incorporated by reference herein.
When the valve 150 is in a closed position and the thermal mass flow controller 100 is disposed in the position shown in FIG. 1 with the sensor measuring portion 146C oriented horizontally (i.e., with the sensor measuring portion oriented parallel to the X axis shown in FIG. 1), the fluid in the sensor measuring portion is heated to a temperature above that of the fluid in the bypass 142. Because of this heating, the density of the fluid in the sensor measuring portion is less than the density of the fluid in the cooler bypass 142. Thus, in the orientation shown, and with the valve in a closed position, a density gradient will develop and be maintained by the force of gravity, with the heavier and more dense fluid in the bypass and with the lighter (more buoyant) and less dense fluid in the sensor measuring portion.
If, instead of being disposed in the orientation depicted in FIG. 1, the thermal mass flow controller 100 is instead disposed in a different orientation, for example, in the manner shown in FIG. 2 (i.e., with the sensor measuring portion 146C being oriented parallel to the Y axis), convective forces due to differences in temperature between the fluid in the sensor measuring portion and that in the bypass 142 and the force of gravity may give rise to a recirculation of fluid that can affect the accuracy by which flow rate is determined.
For example, with the valve 150 in a closed position and the thermal mass flow controller 100 disposed in the position shown in FIG. 2, the fluid in the sensor measuring portion 146C will again be heated to a temperature above that of the fluid in the bypass 142. As a result of this heating, the warmer and less dense fluid in the sensor measuring portion rises and flows out of the sensor outlet 146B where it contacts the bypass and cools, while the cooler fluid in the bypass is in turn pulled into the sensor inlet 146A and warmed by the resistive windings 146D, 146E. Due to a combination of convective forces and the force of gravity, a continuous circulation loop is created which will be detected as a flow of fluid by the control electronics associated with the mass flow controller, despite the fact that the valve is closed. It should be appreciated that depending upon the orientation of the mass flow controller, this false flow signal may be detected as a positive (e.g., increased) flow of fluid (for example, in the orientation shown in FIG. 2) or as a negative (e.g., decreased) flow of fluid. Further, although the effect of such recirculation is most noticeable when the valve 150 is in a closed position, it should be appreciated that this phenomenon will also affect the accuracy by which flow rate is determined when the valve is open, with its impact being more significant at lower flow rates and with more dense fluids.
A number of different mass flow meters and/or mass flow controller designs have attempted to mitigate the effects of recirculation, such as, for example, those described in commonly owned U.S. Pat. Nos. 5,279,154 and 6,044,701. Although the devices disclosed in the afore-mentioned U.S. patents do reduce the effects of recirculation, that reduction is generally dependent upon installing and using the mass flow meter and/or mass flow controller in the specific orientation in which it was designed to be used.

Mass flow meter or controller with inclination sensor


A power control system and method controls a power generator to vary the duty cycle of a power output provided to a delivery instrument for delivering that power to a site in a patient for ablation. The peak power can be raised and the duty cycle lowered to result in deeper lesions. However, the effective power is controlled so that it does not exceed a predetermined level. A power output having a higher peak power for producing deeper lesions can be obtained by using a lower duty cycle having a longer "off" period in order to deliver more power to the ablation site without overheating the delivery instrument. The maximum peak power that may be selected is determined in accordance with the structural limitations of the delivery instrument. The temperature of the delivery instrument is monitored, and the duty cycle is lowered when the temperature exceeds a predetermined maximum limit. After the instrument has cooled sufficiently, the duty cycle is then increased to its previous level.

The invention generally relates to power control, and more particularly, to controlling the energy delivered to a patient for more effective energy transfer.
The heart beat in a healthy human is controlled by the sinoatrial node ("S-A node") located in the wall of the right atrium. The S-A node generates electrical signal potentials that are transmitted through pathways of conductive heart tissue in the atrium to the atrioventricular node ("A-V node") which in turn transmits the electrical signals throughout the ventricle by means of the His and Purkinje conductive tissues. Improper growth of or damage to the conductive tissue in the heart can interfere with the passage of regular electrical signals from the S-A and A-V nodes. Electrical signal irregularities resulting from such interference can disturb the normal rhythm of the heart and cause an abnormal rhythmic condition referred to as cardiac arrhythmia.
Electrophysiological ablation is a procedure often successful in terminating cardiac arrhythmia. This procedure involves applying sufficient energy to the interfering tissue to ablate that tissue thus removing the irregular signal pathway. However, before the ablation procedure can be carried out, the interfering tissue must first be located.
One location technique involves an electrophysiological mapping procedure whereby the electrical signals emanating from the conductive endocardial tissues are systematically monitored and a map is created of those signals. By analyzing that map, the interfering electrical pathway can be identified. A conventional method for mapping the electrical signals from conductive heart tissue is to percutaneously introduce an electrophysiology ("EP") catheter having mapping electrodes mounted on its distal extremity. The catheter is maneuvered to place those electrodes in contact with or in close proximity to the endocardium of the patient's heart. By monitoring the electrical signals at the endocardium, aberrant conductive tissue sites responsible for the arrhythmia can be pinpointed.
Once the origination point for the arrhythmia has been located in the tissue, the physician may use an ablation procedure to destroy the tissue causing the arrhythmia in an attempt to remove the electrical signal irregularities and restore normal heart beat or at least an improved heart beat. Successful ablation of the conductive tissue at the arrhythmia initiation site usually terminates the arrhythmia or at least moderates the heart rhythm to acceptable levels.
The distal end of an EP catheter may include mapping electrodes as well as an ablation device for performing the ablation procedure. One type of ablation device includes an ablation electrode that emits radio frequency ("RF") energy to heat the target tissue to a temperature high enough to cause ablation of that tissue. Another type of ablation devices comprises an ultrasonic device, such as a piezoelectric device.
As the ablation procedure progresses, heat is generated and the surrounding blood is exposed to this heat. At approximately 100.degree. C., charring and boiling of the blood take place. Coagulation may also occur. Charring is particularly troublesome at the surface of the ablation device because emboli may form on the surface of the device to an extent that the catheter must be removed and cleaned before the procedure can continue. Furthermore, charring and coagulation can cause a substantial increase in the impedance and a corresponding decrease in the power delivery to the tissue. Too great a rise in impedance can result in sparking and thrombus formation within the heart, both of which are undesirable.
Because part of the ablation transducer is in contact with the blood in the heart, blood boiling, emboli development, and clotting can result if the surface temperature of the transducer exceeds 90-100.degree. C. If this occurs, the ablation procedure must be stopped regardless of whether the entire ablation procedure has been completed. The catheter must then be removed from the patient, the attached necrotic tissue removed, and the catheter reinserted into the patient. Such cleaning processes require extra time and unduly prolong the ablation procedure. To avoid such undesirable circumstances, a temperature sensor may be incorporated at the distal end of the catheter to monitor and maintain a selected temperature during ablation. The ablation process can then be controlled so that the temperature is not allowed to increase above a predetermined level.
In many cases, the target tissue extends relatively deeply in the endocardium. To successfully ablate that tissue, deeper lesions are necessary. However, merely increasing the power applied to the ablation device does not necessarily result in a lesion of greater depth. Power at too high a level can damage the delivery instrument, or cause charring and boiling of the surrounding blood and tissues, thereby necessitating termination of the application of energy and prematurely shortening the ablation procedure before the lesion can be developed to the desired depth.
Hence, those skilled in the art have recognized the need to improve the delivery of energy to the patient. Improved delivery of ablation energy is needed to produce deeper lesions in the heart tissue while at the same time, controlling the temperature developed at the site. The present invention fulfills these needs and others.

System for controlling the energy delivered to a patient for ablation


A method and device is shown for converting a conventional printer cartridge into a self-contained re-inking cartridge. A conventional printer cartridge is modified by providing an access hole in its top panel and a re-inking insert is positioned within the access hole. The re-inking insert includes a slit formation allowing passage of the ribbon therethrough. The insert further includes a source of ink and a roller assembly for delivering ink in metered fashion to the ribbon. Thus, under the present invention a wide variety of conventional printer cartridges may be converted, for example by a value-added intermediate manufacturer, into self-inking cartridges having a life span determined by the durability of the ribbon, rather than the ribbon length and ink saturation thereof.

This invention relates generally to printer ribbon cartridges used for impact computer printers, e.g., daisy wheel or dot matrix printers, and generally to a re-inking device for ribbon cartridges.
Printer ribbon cartridges are typically provided as a disposable product including a given length of pre-inked ribbon. The length of the ribbon defines the useable life of such printer cartridges. Often the usable life is a short life resulting in frequent user dissatisfaction caused by the inability to print long documents without the fading of printed characters, or caused by the necessity of frequent cartridge replacement. It is estimated that up to 26 million impact printers are now in the hands of personal, business, government and military users in the United States alone, with up to 2 million such printers sold annually. Given the vast number of such printers in use, it may be appreciated that ribbon cartridges may be improved by providing a longer cartridge life.
Typical ribbon cartridges include a nylon ribbon, 4 to 5 mils (thousands of an inch) thick, pre-inked at manufacture to a given standard saturation level, typically between 17 and 25 percent. The ribbons are arranged as an endless loop, typically between 5 and 160 feet in length. In basic operation, the ribbon is moved past an exposed portion of the cartridge for impact by the printer head on one side and contact with paper on the other side to form a printed character upon the paper. The cartridge typically includes a mechanical input driven by the printer in order to circulate the ribbon through the cartridge. A good portion of the ribbon is collected within a pocket of the cartridge in generally serpentine configuration. As the cartridge operates, the ribbon is pushed into and drawn from the pocket. Such ribbon cartridges produce good density print when new, but gradually fade during their life span. Such cartridge life spans average 150 pages in the smaller cartridges and up to 300 pages in the larger cartridges. For very long documents, e.g., a doctoral dissertation, an inventory printout, or a book manuscript, printing with a single cartridge can result in significant fading of the printed characters. This fading of characters is apparent by flipping through the pages of the document. Such presentation is undesirable in most instances, especially in formal presentations.
Many attempts have been made to solve such fading problems and associated limited cartridge life problems. Most notable is the separate or external re-inking device which requires ribbon cartridge removal from the printer and mounting of the cartridge upon the separate re-inking device. The re-inking device turns the ribbon through the cartridge and applies a reasonably uniform distribution of ink upon the cartridge. Thus, the external re-inking device includes some mechanical coupling to the printer cartridge in order to draw the ribbon through the cartridge and access the exposed portion in a manner similar to that conducted by the printer, but for the purpose of ink delivery to the cartridge. As may be appreciated, re-inking a cartridge by use of such a separate re-inking device necessarily requires that the ribbon cartridge be taken out of use during re-inking and that sufficient time be allotted to dismount the cartridge from the printer, mount the cartridge to the re-inking device, monitor the re-inking operation, and then re-mount the ribbon cartridge upon the printer for further use. Also, in mounting the cartridge upon the re-inking device the user must thread the ribbon through the re-inking components of the device and must often wear gloves to keep the ink free of their hands.
In other approaches to the problem of limited ribbon cartridge life and ink supply, a re-inking device has been provided as in integral part of the printer cartridge. This has been done b employing a square or rectangular felt or open celled foam rubber pad with a short wick to draw the ink, by capillary action, from the pad onto a roller or gear of the cartridge, which in turn transfers ink onto the passing ribbon. The pad arrangement, however, must be inked to near saturation before the capillary action takes place, and the particulant in the ink causes the cells of the rubber or the passageways of the felt to partially clog. Thus, capillary action alone is insufficient to do the job of delivering ink to the ribbon, and this pad arrangement does not provide any force to feed ink toward the ribbon. Thus, when inked heavily enough to operate properly, such pad arrangement frequently results in ink gravitating toward the passive or active drive gear holes of the cartridge panels and ink undesirably leaks from the cartridge.
U.S. Pat. No. 2,743,470 issued to R. G. Horowitz shows for a typewriter ribbon a cylindric inking pad fed by replenishing ink from a screw-off cap on the top of the device. Such a device, wherein the ribbon enters and leaves this cylinder through two slits and passes against this inked pad, creates the problem of imparting excessive ink against the ribbon if the device is left inside the typewriter, or if the ribbon is stopped while remaining in contact with the pad. It appears that the Horowitz device was designed to be held in place by the operator while the ribbon is manually wound from the feed-spool onto the take-up spool. U.S. Pat. No. 2,441,973 illustrates a device similar to the Horowitz device, with the same deficiencies.
U.S. Pat. No. 3,951,253 shows a self-contained re-inking device designed to attach to a typewriter ribbon spool and to ink the two separate bands on a two color typewriter ribbon. The disclosure of U.S. Pat. No. 3,951,253 shows no provision for preventing excess ink delivery to the ribbon when the ribbon is not in motion. This design would produce what is known as "hot spotting" where the ribbon is overly inked in certain portions and produces non-uniform printing density.
As may be appreciated, a limited life for ribbon cartridges provides an active market for ribbon cartridge manufacturers, but is a source of frustration for users of printer cartridges. More particularly, because the nylon ribbon of most ribbon cartridges is durable enough to withstand 4 or 5 times more printing impact than the supply of ink provided in the ribbon, the ribbon cartridges lack but one component to greatly extend their useful life. It is desirable therefore, that such pre-existing ribbon cartridges be provided with a mechanism for re-inking the ribbon in order to extend the useable life of the cartridge and maintain uniform print density, but not require significant activity on the part of the user in re-inking the cartridge.

Self-contained re-inking insert and ribbon cartridge device


A system and method are disclosed for providing a low voltage bandgap reference circuit that provides a substantially constant output voltage over a range of values of temperature. For example, the bandgap reference circuit could be capable of providing output voltages that are as low as one hundred millivolts. Also, no special start-up circuitry may be required to initiate the operation of the bandgap reference circuit. The bandgap reference circuit could further require fewer transistors and fewer resistors than prior art bandgap reference circuits.

A bandgap reference circuit is commonly used to provide a reference voltage in electronic circuits. A reference voltage must provide the same voltage every time the electronic circuit is powered up. In addition, the reference voltage must remain constant and independent of variations in temperature, fabrication process, and supply voltage.
A bandgap reference circuit relies on the predictable variation with temperature of the bandgap energy of an underlying semiconductor material (usually silicon). The energy bandgap of silicon is on the order of one and two tenths volt (1.2 V). Some types of prior art bandgap reference circuits use the bandgap energy of silicon in bipolar junction transistors to compensate for temperature effects.
As the design dimensions of electronic circuit elements decrease, the magnitude of the power supply voltages have also decreased. Lower power supply voltages reduce the total power requirements of an electronic circuit. This is especially important in electronic circuits that operate on battery power. Electronic circuits that use lower supply voltages also require bandgap reference circuits that provide lower reference voltages.
Therefore, there is a need in the art for a bandgap reference circuit that is capable of providing a low reference voltage. Specifically, there is a need in the art for an improved low voltage bandgap reference circuit that can provide a reference voltage having a magnitude less than one and two tenths volts (1.2 V).
Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms "include" and "comprise," as well as derivatives thereof, mean inclusion without limitation; the term "or," is inclusive, meaning and/or; the phrases "associated with" and "associated therewith," as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.
Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as to future uses, of such defined words and phrases.

System and method for providing a low voltage bandgap reference circuit


A compatible special effect signal can be produced without using an encoder or a special signal processor. Each of EDTV signals is divided into a main screen signal and a compensation screen signal. Compensation screen modification circuits modify the special position and size of the compensation screen signals such that the compensation screen signals match with the main screen signals in spacial position and size. The modified signals and the main screen signals are multiplexed in a frequency domain. The multiplexed signals are gated in response to a wipe signal and the gated signals are mixed with each other. The mixed signal is separated into the main screen signal and the compensation screen signal in the frequency domain. A compensation screen signal restorer circuit converts the frequency separated compensation screen signal into the original compensation signal which is mixed with the main screen signal to generate the wiped wide screen EDTV signal.

The present invention relates to a video switcher apparatus proper for a video display apparatus of displaying wide screen EDTV signals on a screen.
A screen configuration ratio (aspect ratio) of a current type television signal is 4:3 as shown in FIG. 9A. The Extended Definition TV (EDTV) system is in the spotlight recently as a television system which is able to reproduce a detailed image or a high definition image. A non-interlace scanning method having 525 horizontal scanning lines is applied to the EDTV system.
A wide screen type EDTV will next enter the spotlight as a next age of the EDTV system. This type employs non-interlace scanning having 525 horizontal raster lines similar to the current EDTV system. The screen aspect ratio will be 16:9 in a manner similar to a high definition television (HDTV) system.
It is difficult to accomplish a compatibility between a current type television signal and the wide screen type EDTV signal because their aspect ratios are different from one another. However, a so-called letter box system is proposed for the wide screen type EDTV signal as one method to accomplish compatibility.
According to the letter box system, if an image of 16:9 aspect ratio is reproduced on a screen of 4:3 aspect ratio, upper and lower screen areas become non-image areas as shown in FIG. 9C. In this drawing, slant line areas represent the non-image areas.
It is assumed that a main screen SM represents a common screen area to both the screens having different aspect ratios and a main screen signal (represented by SM) is displayed on the main screen area SM. In this instance, it is desired for the wide screen type EDTV signal that a relatively low frequency component of the wide screen type EDTV signal be assigned to the main screen signal SM and horizontal and vertical high frequency components (for the high resolution display) be assigned to a compensation screen signal SC. Then, the compensation screen signal forms non-image areas 1 and 2 as shown in FIG. 9C.
The compensation screen signal is used only for the EDTV receiver. The high definition image is reproduced by both the compensation screen signal and the main screen signal. The main screen signal can be used as the television signal by a conventional receiver. The upper and lower non-image areas 1 and 2 are accomplished by applying the wide screen type EDTV signal to the conventional receiver. If the compensation screen signal is inserted into the upper and lower non-image areas 1 and 2, the wide screen type EDTV video signal would be reproduced by the conventional receiver. It should be noted that the compensation screen signal is unnecessary for the conventional receiver because it is not used to produce an image. Thus, compatibility can be established between the wide type EDTV signal and the current TV signal.
Thus, the wide screen type EDTV signal may be converted into a format such that the main screen signal SM is positioned at the center portion of the raster and the compensation screen signal SC is positioned at the upper and lower non-image areas. Then, the converted signal may be transmitted.
The compensation screen signal includes high frequency components or the like along the horizontal and vertical directions, and these components act as a high frequency compensation signal. In this instance, for example, the horizontal compensation screen signal SCH is inserted into the upper non-image area 1 and the vertical compensation screen signal SCV is inserted into the lower non-image area 2.
Each of the compensation signals may be separated and inserted into the upper and lower non-image areas. As shown in FIG. 10, each of the non-image areas 1 and 2 may be separated by two horizontally. Moreover, the horizontal compensation screen signal SCH and the vertical compensation screen signal SCV may be separated and inserted into the non-image areas.
When the compensation screen signal is inserted, it is compressed horizontally or vertically and then inserted. Since a horizontal line number of the non-image areas to which the compensation screen signal is inserted is about one third of the horizontal line number of the main screen area, one horizontal line of the compensation screen signal corresponds to three horizontal lines of the main image signal. If the compensation screen signal is not compressed, the more non-image area is required.
The transmitted wide screen type EDTV signal can be displayed on the conventional receiver by processing the signal as discussed hereinbefore. On the other hand, the wide CRT type special receiver can display the wide screen type EDTV signal in the high definition mode by using the compensation screen signal.
If many video cameras outputting the wide screen type EDTV signals are used in a broadcasting station, it is necessary to switch the outputs from the many video cameras. The output switching operation is done for switching the video cameras as well as accomplishing special effects, such as a wipe operation.
Examples of the special effects are shown in FIGS. 11a, 11, 11b and 11c. A horizontal wipe image (FIG. 11b) or a vertical wipe image (FIG. 11c) is obtained by using an image of a camera A (FIG. 11a) and an image of a camera B (FIG. 11a').
A video switcher apparatus shown in FIG. 12 may be proposed to be used in this instance. This drawing is a block diagram of a two-channel video switcher apparatus for switching two cameras wherein, for example, a terminal 11 receives the wide screen EDTV signal "a" of FIG. 11a and a terminal 12 receives the wide screen EDTV signal "a". Reference numbers 13 and 14 represent gate circuits each of which executes a complement gate process in response to a wipe signal (key signal) applied to a terminal 15. A mixer 6 mixes the wiped wide screen EDTV signals with each other and applies the wiped EDTV signal "b" or "c" shown in FIG. 11b or 11c to a terminal 17.
In order to make the switching operation proper, the input signals "a" and "a'" should match with the wipe signal in spacial position.
As discussed hereinbefore, the wide screen EDTV signal is formed by inserting the compensation screen signal SC and the main screen signal SM into the raster in which the spacial position relationship therebetween is modified. Since the main screen signal SM and the compensation screen signal SC are wiped simultaneously, the screen is divided into, for example, the left half screen and the right half screen when the horizontal wipe is accomplished.
There is no special problem in the main screen. However, the high frequency components in the main screen signal SM of the left half L of the screen shown in FIG. 11b cannot be compensated only by the compensation screen signal SC in the left half L. Similarly, the high frequency components in the main screen signal SM of the right half R cannot be compensated only by the compensation screen signal SC in the right half.
The reason is that the compensation screen signal can be inserted such that the high frequency components of the main screen signal can be compensated if the compensation screen signal inserted into all the non-image screen portions 1 and 2 is used. If a compression process is accomplished, the high frequency compensation signal is unstable and this signal cannot be employed effectively.
There is a problem in the vertical wipe operation. As shown in FIG. 11c, the compensation screen signal in the upper screen U consists only of the horizontal high frequency components in the main screen of the upper screen U after the wipe operation is finished. After the wipe operation, the compensation screen signal in the lower screen L consists only of the vertical high frequency component in the main screen of the lower screen L. Thus, the resultant signal is completely different from the ideal signal.
These problems occur when the screen insertion position of the compensation screen signal has no relation to that of the main screen signal.
In order to resolve these problems, EDTV decoders could be provided at the input terminal of the video switcher apparatus, the number of the EDTV decoders should be the same as that of the inputs, the main screen signal and the compensation screen signal should be mixed to produce a single EDTV signal, and then the video signal switching process should be done. In other words, the high resolution wide screen would be restored once.
The above discussed construction needs many decoders at the input side of the video switcher apparatus and is very expensive. In the broadcasting station, since video switcher apparatuses are apt to be connected in cascade, the discussed construction is not practical.
The decoded EDTV signal is generally of the line sequence type because of the high quality image of the EDTV signal. Thus, the video switcher apparatus receiving the decoded signal should be the line sequence type. As a result, it is impossible to use the current type apparatus and the cost performance of the discussed apparatus is not acceptable.
What is desired is a video switcher apparatus that resolves the above discussed problems and can avoid an improper video switching operation without using a decoder or the like.

Video switcher apparatus for wide screen EDTV signals


A radio having two signal processing paths, one including a digital signal processor that consumes a relatively large amount of power and one including a signal processor that consumes a relatively small amount of power. The low power processor operates to monitor for broadcast signals of interest. Upon detecting such a signal, the low power processor enables the digital signal processor to facilitate proper signal processing.

Radios generally function to receive broadcast signals. Usually, the user of a radio will not be interested in all of the signals that are broadcast on a communication resource (such as a particular frequency or a particular TDM time slot). Since many broadcast signals of interest include an identifying signal or other identifying indicia, many radios include a signal processor that examines the received broadcast signal to determine the presence of the identifying signal. If present, the radio can be further enabled to render the broadcast signal audible, visible, or otherwise as appropriate for that particular broadcast signal.
For example, some radios remain squelched unless a carrier can be sensed on a particular monitored communication resource. Other broadcast signals include special identifying signals, such as tone signals or subaudible digital signals, that the radio can recognize and respond to. Yet other signals of interest can be prefaced with a specific identifying preamble, such as an ID for the intended radio.
In order to expand the capabilities and flexibility of radios, digitizers and digital signal processors (DSPs) have been used. These processors typically receive digitized received signals. Further processing of the signal, equivalent to IF and discriminator processing, then occurs in the DSP in a digital manner. The resultant signal can then be converted into analog form and processed further as appropriate. For example, the resultant signal may be rendered audible in the case of a voice transmission.
DSPs, however, consume a significant amount of power when operating. This becomes a particular problem when seeking to use a DSP in a portable radio with limited power resources. DSP power consumption becomes of particular concern when the DSP operates both in the presence and absence of a broadcast signal of interest. Typically, the DSP must operate even in the absence of a broadcast signal of interest because the DSP itself aids in detecting the presence of a broadcast signal of interest. Unless the broadcast signals of interest occur at known times, the DSP must remain active in order to detect the signal when it occurs.

DSP based radio with diminished power requirements


A photothermographic material of the present invention comprises: a support; a photosensitive silver halide; a non-photosensitive organic silver salt; a heat developer; a binder; and a fluorine compound containing a specific structure.

In recent years, reduction of amount of waste processing solutions is strongly desired in the medical field from the standpoint of environmental protection and space savings. Techniques relating to photosensitive heat-developable photographic materials for use in medical diagnosis and photomechanical processes are required which enable efficient exposure by a laser image setter or laser imager and formation of a clear black image having high resolution and sharpness. The photosensitive heat-developable photographic material can provide users with a simple and non-polluting heat development processing system that eliminates the use of solution-type processing chemicals.
Although the same is required also in the field of general image-forming materials, the image for medical diagnosis in particular must be finely drawn and therefore, high image quality with excellent sharpness and graininess is needed. Moreover, in view of diagnostic convenience, an image of cold black tone is preferred. At present, various hard copy systems using a pigment or a dye are commercially available as a general image-forming system, such as ink jet printer and electrophotography, however, these are not a satisfactory output system for the medical-use image.
On the other hand, thermal image forming systems using an organic silver salt are described, for example, in U.S. Pat. Nos. 3,152,904 and 3,457,075, B. Shely, Thermally Processed Silver Systems, and Sturge, V. Walworth and A. Shepp (compilers), Imaging Processes and Materials, 8th ed., page 2, Neblette (1996). In particular, heat-developable photosensitive materials generally have a photosensitive layer comprising a binder matrix having dispersed therein a catalytic amount of a photocatalyst (for example, silver halide), a reducing agent, a reducible silver salt (for example, organic silver salt) and if desired, a color toner for controlling the silver tone. The heat-developable photosensitive material after image exposure is heated at a high temperature (for example, 80° C. or more) to bring about an oxidation-reduction reaction between the silver halide or reducible silver salt (acting as an oxidizing agent) and the reducing agent and thereby form a black silver image. The oxidation-reduction reaction is accelerated by the catalytic action of a silver halide latent image generated upon exposure. Therefore, the black silver image is formed in the exposed area. This is disclosed in many publications including U.S. Pat. No. 2,910,377 and JP-B-43-4924 (the term "JP-B" as used herein means an "examined Japanese patent publication"). As a medical image forming system using a heat-developable photosensitive material, "FM-DP L" (Fuji Medical Dry Imager) is put on the market.
For the production of a thermal image forming system using an organic silver salt, a method of producing the system by coating a solvent, and a method of producing the system by coating and drying a coating solution containing, as a main binder, an aqueous dispersion of fine polymer particles are known. The latter method needs only a simple production equipment and is suited for mass production, because a step for collecting a solvent is unnecessary.
In either the coating method using a solvent or the aqueous coating method using mainly water as the solvent, the coating of a heat-developable photosensitive material is difficult as compared with conventional photosensitive materials using gelatin as a main binder. In particular, high-speed coating causes generation of streaks or unevenness. In order to improve the productivity and profitability, improvement is demanded in the coatability.
Furthermore, use of an aqueous latex as a binder has a problem in that on touching with a hand wetted with sweat or oil, a fingerprint attaches and this causes discoloration in aging.

This patent is subject to a terminal disclaimer.


There is provided a solid-state image sensing device that can prevent the occurrence of vertical line noise with a simple circuit. A timing adjustment circuit generates a first clock supplied to a ramp generator and a second clock supplied to a counter so that a phase difference between the first clock and the second clock is within a predetermined range and differs according to lines in an image sensor.

The present invention relates to a solid-state image sensing device, and for example to a solid-state image sensing device having column ADCs (Analog to Digital Converters).
Many of solid-state image sensing devices for camera equipment or the like use CMOS sensors as image sensors and use simple integral ADC circuits for cost reduction. Further, even camera equipment or the like is required from the market to have a simple video shooting function. To increase the frame rate during video shooting without greatly increasing the overall cost, it is necessary to decrease the output bit precision of ADC to a level that does not greatly affect the image quality.
However, in such a CMOS sensor, for example, vertical line noise which does not appear in 12-bit output for photographs may appear in 10-bit output for video. This is known to be caused by quantization noise specific to a column ADC system having an ADC for each column of the image sensor. The following patent documents take the following measures against this problem.
In Japanese Unexamined Patent Publication No. 2008-60872 (Patent Document 1), a noise signal N2dim indicating random noise in two-dimensional space without temporal variation is added to a pixel signal So. A column ADC circuit (25) separately converts a reset level Srst and a signal level Ssig of the pixel signal having the noise signal N2dim added thereto into digital data independently, and takes the difference. By separately converting the two into digital data, with the noise signal N2dim added, the same noise effect appears on the AD conversion results of the two, thus canceling column-correlated noise. Although a quantization error associated with difference processing in a digital domain occurs, the quantization error can have no column correlation, and also the added noise signal N2dim can be removed. As for a specific way to generate the noise signal N2dim, a reset release interval TRelease is set to be shorter than a typical interval. That is, part of reset noise occurring during a reset operation by a reset transistor (36) as a pixel reset unit in a unit pixel (3) remains in the unit pixel as noise that is not removed by an offset removal operation by an operating point reset unit (offset removal unit) (330) in a voltage comparison unit (252).
In Japanese Unexamined Patent Publication No. 2011-50046 (Patent Document 2), a random offset of not more than +/−0.5LSB is added for each line to an offset of a DAC for generating a reference RAMP wave during ADC sampling, thereby reducing vertical streak noise. The offset addition is performed by current addition by an analog circuit.


A method and apparatus controlling a light power, the apparatus including a light power controller, which controls a quantity of light and disposed inside the main controller disposed outside the laser scanning unit, and a light generator, which generates light and disposed inside the laser scanning unit.

1. Field of the Invention
The present invention relates to a printing device, such as a printer, a scanner or a multifunctional device, and more particularly, to a method and apparatus controlling a light power of a laser diode (LD) which is an element for a laser scanning unit (LSU) in a printing device.
2. Description of the Related Art
A conventional laser scanning unit (LSU) includes optical elements, such as a laser diode (LD) emitting laser light, an auto power controller (APC) maintaining a light power of the laser diode (LD) at a constant level, a collimator lens making the emitted laser light as parallel light or convergent light with respect to an optical axis, a polygon mirror scanning laser light that has passed the collimator lens at uniform speed in a horizontal direction, a cylinder lens forming an image of the laser light on the surface of the polygon mirror as a linear shape in the horizontal direction, an F-theta lens polarizing light having a predetermined refractive index with respect to the optical axis and reflected on the polygon mirror at uniform speed in a scanning direction, correcting aberration, and focusing on a scanned surface, an image-formation reflective mirror reflecting the laser light that has passed the F-theta lens and forming an image on the surface of a photosensitive drum of a printing device, a synchronous signal detection light sensor receiving the laser light and making horizontal synchronization, and a synchronous signal detection reflective mirror reflecting the laser light on the synchronous signal detection reflective mirror. The optical elements are installed in a housing and sealed. This prevents the optical elements from being contaminated from a foreign substance, such as dust or dispersion toner. In particular, the light power controller maintaining the light power of the LD at the constant level is disposed on a circuit board. The light power controller includes a laser diode driver, a field effect transistor (FET), a laser diode (LD), a light receiving unit, a variable resistor, and a threshold voltage generator.
The operation of the light power controller will now be described. If an ON signal for emitting light from the LD is input into the light power controller, the FET is conductive by the laser diode driver. If the FET is conductive, a current is applied to the LD, the LD emits light, and the light receiving unit receives light and generates a monitor current. The monitor current and the variable resistor detect a voltage, and the detected voltage is input into the threshold voltage generator. If the input voltage is higher than a threshold voltage, the threshold voltage generator generates a high H signal. If the input voltage is lower than the threshold voltage, the threshold generator generates a low L signal. The FET is turned on or off in response to the high H signal or the low L signal so that light of the LD is controlled. The quantity of light of the LD increases or decreases a value of the variable resistor so that the amount of current supplied to the LD increases or decreases. As such, a desired quantity of light can be fixed. In the conventional art, the light power controller is disposed inside the LSU and controlled by a main controller disposed outside the LSU.
However, the light power controller in a conventional analog manner adjusts the value of the variable resistor measuring the monitor current to output a desired quantity of light, thereby fixing the quantity of light emitted from the LD. Thus, even when the intensity of light should vary according to the speed of a printer, the quantity of light cannot be controlled freely. In addition, since the quantity of light is adjusted using the threshold voltage, the range of adjustment is limited. Since the light power controller is disposed inside the LSU, malfunction may occur in the light power controller due to heat caused by light emitted from the LD or vibration. In particular, due to heat, resistance of the fixed variable resistor may vary. In addition, the variable resistor should be fixed according to the quantity of light when manufacturing.

Method and apparatus for controlling light power


Systems and methods are discussed to localize facial landmarks using a test facial image and a set of training images. The landmarks can be localized on a test facial image using training facial images. A plurality of candidate landmark locations on the test facial image can be determined. A subset of the training facial images with facial features similar to the facial features in the test facial image can be identified. A plurality of shape constraints can be determined for each test facial image in the subset of test facial images. These shape constraints graphically relate to one landmark location from a linear combination of the other landmark locations in the test facial image. Shape constraints can be determined for every landmark within each test facial image. A candidate landmark can be chosen from the plurality of candidate landmarks using the shape constraints.

Localizing facial landmarks can be an important component in many computer vision applications such as face recognition, facial expression recognition, face reconstruction, and re-targeting. Many approaches have been proposed with varying degree of success on benchmark datasets composed by mostly frontal images in controlled setting. However, accurate localization of facial landmarks in real-world, cluttered images is still a challenge due to a number of factors. FIGS. 1A-1E show examples of facial images that create facial recognition challenges. FIG. 1A shows an example of a facial image in a non-ideal pose. The face is looking down relative to the camera. FIG. 1B shows an example of a facial image with unusual expression. FIG. 1C shows an example facial image with illumination varying across the face. The left side of the face is well illuminated and the right side of the face is in shadow. FIG. 1D shows an example of a facial image with a portion of the face occluded. In this image the left eye is occluded by a hat. FIG. 1E shows an example of a low quality image. In this example, the face is out of focus. Each of these examples, among others, pose challenges to facial recognition techniques.

Facial landmark localization by exemplar-based graph matching


A fluxing composition for soldering metals together, contains a carrier solvent, an oxide removing agent, and a nitrogen liberating compound. The oxide removing agent sublimes at or below the temperature at which the metals are soldered together. The nitrogen liberating compound sublimes or decomposes at below the temperature at which the metals are soldered together in order to provide a blanket of inert gas over the metals being soldered. The oxide removing agent is 2-amino-isophthalic acid, 5-amino-isophthalic acid, isophthalic acid, ammonium fluoborate, or ammonium salicylate. The compound that liberates nitrogen upon heating is 1,2-benz-3,4-anthraquinone, 1,2-benz-9,10-anthraquinone, 5,6-chrysoquinone, 6,12-chrysoquinone, 2,3-benzanthraquinone, 2-amino-isophthalic acid, 5-amino-isophthalic acid, or 5-isoquinoline carboxylonitrile. Electronic components are soldered to a circuit board by applying the fluxing composition to the circuit board. The fluxing composition, the component and the circuit board are heated to a temperature sufficient to cause the activator to react with metal oxides on either the component or the circuit board and to sublime, and also to a temperature to cause the nitrogen containing compound to decompose or sublime.

Solder flux formulations typically consist of a fluxing component or agent dispersed or dissolved in an aqueous or organic solvent. These fluxes are generally applied to surfaces or locations required to be soldered together. The application of the flux is performed in any number of ways, such as coating, dispensing, dipping, spraying, or otherwise selectively or globally depositing the flux on the surfaces to be soldered together. In the electronics industry, for example, electronic components are soldered to printed circuit boards. A solderable material, typically a tin-lead alloy, is applied either to the component, the circuit board, or both, along with the flux, and the assembly is heated and the flux activates the surfaces of the metals. When the solder melts, it alloys with both the electronic component and the printed circuit board, to form an electrical and mechanical joint between the component and the circuit board.
For most uses in the electronics industry, it is desirable to use a flux composition which is non-corrosive and non-conducting. For this reason, rosin based flux compositions are widely used in the commercially available fluxes made specifically for manufacturing surface mounted electronic assemblies. If more reactive fluxing compositions are used, they typically leave residues which are corrosive and/or conductive. However, higher reactivity is, in some ways, desirable, in that it aids in removing oxides which may form on the metal surfaces to be soldered, thereby providing a strong solder bond. However, the use of such fluxes also has a number of disadvantages. Because the residues from rosin based fluxes tend to be sticky, they interfere with automatic testing of the circuit, and unsightly, attract dirt and moisture from the environment, they prevent effective encapsulation or conformal coating of the circuitry, and are hygroscopic.
Because of these disadvantages, flux residues are typically removed in a post-solder cleaning operation. A common procedure is to use an aqueous or organic solvent to remove the flux residues. Water is preferred because it does not leave an objectionable residue. However, water is typically an ineffective agent since many of the residues, such as the rosin, are only slightly soluble in water. Organic solvents are more effective but are less desirable because they are expensive to purchase initially, and are also expensive and difficult to dispose of. One class of organic solvents that has historically obtained widespread use is the chlorofluorocarbons (CFCs) because they are inert and volatilize after cleaning. CFCs have recently come under strong attack because of their tendency to deplete the ozone layer. With severe restrictions placed on the manufacture and use of CFCs, it is clear that this method of cleaning will be totally unsuitable in the near future.
For these and other reasons, the prior fluxing compositions are not preferred, and it would be advantageous to discover a new fluxing composition that would avoid one or more of these disadvantages.


A system and method in accordance with the invention allows the emulation of a DMA transfer between a device such as a CD-ROM which is incapable of a bus-mastering mode of operation (e.g., a DMA transfer) and a memory. Following receipt of an interrupt request, a system in accordance with the invention generates an I/O access cycle to the device, retrieves data and stores the data in a buffer. Following data retrieval, the system transfers the data to host memory. Once data is transferred to host memory, an interrupt is generated to the host processor. Thus, host processor resources are not required to perform a data transfer with devices unable to become bus-masters.

1. Field of the Invention
The invention relates to data transfers by system bus devices, and particularly to transfers by devices incapable of a bus master mode of operation.
2. Background Art
The IBM PC AT computer architecture has become industry standard architecture for personal computers, and is typically built around a CPU such as an 80286, 80386, 80486, or 80586 (Pentium.RTM.) microprocessor manufactured by Intel Corporation. The CPU is coupled to a host (local) bus, capable of performing memory accesses and data transfers at high rates of speed (i.e., on the order of 10-66 MHz). The host bus generally includes 16, 32, or 64 data lines, a plurality of address lines, and various control lines. For present purposes the following signals on the host bus are important:
______________________________________ Signal Name Signal Description ______________________________________ HD63:0! Host Bus Data Lines. HA31:3! Host Bus Address Lines. BE7:0!# Byte enables 7 through 0: Selects the active byte lanes on HD63:0!. INTR Interrupt Request: INTR is driven to signal the processor that an interrupt request is pending and needs to be serviced. M/IO# Memory/Input-Output: M/IO#, defines processor bus cycles along with D/C#, and W/R#. D/C# Data/Control: D/C# defines processor bus cycles along with M/I0# and W/R#. W/R# Write/Read: W/R# defines processor bus cycles along with M/I0# and D/C#. ADS# Address Strobe: The processor asserts ADS# to indicate that a new bus cycle is beginning BRDY# Burst Ready: BRDY# indicates that the system has responded in one of three ways: 1) Valid data has been placed on the processor data bus in a response to a read, 2) Processor write data has been accepted by the system, or 3) the system has responded to a special cycle. STPCLK# Stop Clock: this signal is connected to the STPCLK# input of the processor. It causes the processor to get into the STPGNT# state. ______________________________________
The typical IBM PC AT-compatible computer also includes a system bus, sometimes referred to as an I/O bus. Such a system bus is used to interface communications between a host CPU and a peripheral device, or communications between peripheral devices and host memory. The system bus is coupled to the host bus via certain interface circuitry. The system bus includes generally 8, 16, or 32 data lines, a plurality of address lines, as well as control lines.
One of the most commonly used system buses is the industry standard architecture (ISA) bus. The ISA bus was adopted by several computer industry groups in the 1980's to create a standard to permit the development of compatible add-on cards in a reasonable and consistent fashion. The ISA bus operates at approximately 8 Mhz and includes 8 or 16 data lines, distinct address lines, as well as distinct control and command lines.
The various signals on the ISA bus are well specified and known in the industry. General information on the ISA bus can be found in Solari, "AT Bus Design" (San Diego, Annabooks, 1990), incorporated by reference herein. For present purposes, the following ISA signals are important:
______________________________________ Signal Name Signal Description ______________________________________ SA23:0! 24 address lines. BALE Bus address latch enable line. BALE is an active high signal asserted to indicate when the SA address, AEN and SBHE# lines are valid. BALE remains asserted throughout ISA master and DMA cycles. SBHE# System byte high enable. When SBHE# is active, it indicates that a byte is being transferred on the upper byte (SD15:8!) of the data bus. AEN Address enable line. AEN is asserted during DMA cycles to prevent I/O slaves from misinterpreting DMA cycles as valid I/O cycles. When active, AEN informs I/O resources on the ISA bus that a DMA transfer is occurring. SD15:0! 16 data lines. MEMR# Read request lines to a memory resource on the ISA bus. MEMW# Write request lines to a memory resource on the ISA bus. IOR# Read request line to an I/O resource on the ISA bus. Also called IORC# or IORD#. IOW# Write request line to an I/O resource on the ISA bus. Also called IOWC# or IOWR#. M16# Memory chip select 16. Asserted by an addressed memory resource on the ISA bus if the resource can support a 16-bit memory access cycle. Also called MEMSC16#. I016# I/O chip select 16. Asserted by an addressed I/O resource on the ISA bus if the resource can support a 16-bit I/O access cycle. Also called IOCS16#. NOWS# Synchronous Ready line. Also sometimes called 0WS#, SRDY# or ENDXFR#. Activated by an addressed memory resource to indicate that it can support a shorter-than-normal access cycle. IOCHRDY I/O channel ready line. If this line is deactivated by an addressed I/O resource, the cycle will not end until it is reactivated. Also sometimes called CHRDY. INTRQ(15, Interrupt request lines. 14,12:9,7:3) DMARQ(7:5,3:0) DMA Request lines from I/O resource on ISA bus. DACK(7:5,3:0) DMA Acknowledge lines. BCLK ISA bus clock signal. XD7:0! XD bus lines. ISA status signals. ______________________________________
Recently, efforts have been made to develop other bus protocols for PC AT-compatible computers with the goals of reducing the size of PC AT-compatible computers as well as continued industry standardization. These efforts have included the development of the PCI bus, which has been developed to establish a new industry standard for bus architectures, particularly those interfacing with high bandwidth functions. The PCI bus is described in detail in "PCI Local Bus Specification", Revision 2.1 (Portland, Oreg., PCI Special Interest Group, 1995), incorporated by reference herein. For present purposes, the following PCI signals are important:
______________________________________ Signal Name Signal Description ______________________________________ AD31:0! PCI Address and Data: AD31:0! are bidirectional address and data lines for the PCI bus. FRAME# Cycle Frame: FRAME# is driven the current bus master to indicate the beginning and duration of an access. FRAME# is asserted to indicate that a bus transaction is beginning. While FRAME# is asserted, data transfers continue. When FRAME# is deasserted, the transaction is in the final data phase or has completed. IRDY# Initiator Ready: IRDY# indicates the initiating agent's (the bus master's) ability to complete the current data phase of the transaction. IRDY# is used in conjunction with TRDY#. A data phase is completed on each clock that both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates that valid data is present on AD31:0!. During a read, it indicates the master is prepared to accept data. TRDY# Target Ready: TRDY# indicates the target agent's (selected device's) ability to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is asserted. During a read, TRDY# indicates that valid data is present on Ad31:0!. during a write, it indicates the TRDY# is proper. DEVSEL# Device Select: When actively driven, DEVSEL# indicates the driving device has decoded its address as the target of the current access. STOP# Stop: STOP# indicates that the current target is requesting a master to stop the current transaction. PCICLK Master PCI clock. CLKRUN# Clock Run: CLKRUN# is an I/O sustained tristate signal used by the central resource (the host) to request permission to stop or slow the PCICLK. ______________________________________
Despite PCI bus development, because the PCI bus was designed primarily to support high-end peripherals (i.e., supporting speeds of up to 66 Mhz for 64-bit data), it is not as economical to manufacture low-end peripherals for the PCI-bus as it is for the older, slower ISA-bus. Thus both PCI-type devices and ISA-type devices are commonly produced and computer systems must be developed which have the interfaces to support both PCI-type and ISA-type devices.
Specific devices coupled to the system bus are often peripheral storage units such as disk drives and CD-ROM drives. Many of these devices are IDE (integrated device electronics) devices meaning that they have a built-in controller which allows them to directly interface with the system bus, often an ISA bus. To allow compatibility with various IDE devices and to develop industry standardization and systems, the AT Attachment-3 Interface Specification (ATA-3) has been developed by various industry groups. ATA-3 is described in detail in "Information Technology--AT Attachment-3 Interface (ATA-3), Revision 5 (released for comment and review by ASC X3T10 Technical Committee, October 1995), incorporated by reference herein. For present purposes, the following IDE signals (as defined by ATA-3) are important:
______________________________________ Signal Name Description ______________________________________ DA2:0! IDE address lines: asserted by host to access device. DD15:0! IDE data: bidirectional data lines DRD# Read request line to IDE resource DWR# Write request line to IDE resource. INTRQ Interrupt request. Asserted by IDE device when data is ready for transfer. DMARQ DMA request. Asserted by IDE device when IDE device is ready for a DMA transfer. DMACK# DMA acknowledge. DCS1#, DCS3# Chip select signals for selecting control block registers in IDE device. DCHRDY Channel ready: negated during an access cycle when device is not ready to respond to a data transfer request. ______________________________________
Generally, when a host system (which may include a processor, a memory, and interface circuitry) requires data from an IDE drive, the host will first write command parameters (e.g., sector count, sector number, head, etc.) and other command codes to device registers notifying the device of a request for data. When data is available for transfer to or from the device, the device asserts an interrupt (INTRQ) to the host system. Upon receipt of an interrupt, the host processor initiates an access cycle to transfer data to or from the device. Such mode of data transfer is often referred to as a "programmed I/O" (or "PIO") data transfer because of use made of programmable registers. Other methods of I/O transfer without using programmable registers are also known in the art. Thus, as referred to hereinafter, a "PIO" mode of data transfer is any I/O cycle requiring host processor resources throughout the access cycle. Generally the host processor remains actively involved in the PIO access cycle until it is completed, e.g., by waiting to receive data and then transferring the data to memory. More detailed information regarding PIO data transfers can be found in ATA-3.
Because of the high demand for host processor resources during an access cycle, many IDE drives are also "bus masters", meaning that the device itself can initiate and control a data transfer cycle on the system bus with little to no host processor participation. Often such "bus master" control occurs through DMA (direct memory access) cycles, which allow a device to transfer data to or read data from the host memory directly without host processor involvement.
Generally for a DMA transfer, when a host system requires data from a bus mastering IDE device, the host will first write command parameters and other command codes to IDE device registers, thereby notifying the device of a request for a data transfer, in a manner similar to that done for IDE devices using a PIO mode of transfer. However, rather than asserting an interrupt to the host processor, the bus-mastering IDE device will assert a DMA request signal (DMARQ), which is not transferred to the host processor. Rather the DMARQ signal is received by the interface circuitry and indicates that the IDE device is attempting to assert ownership of the bus. Upon receipt of a DMA acknowledge (DMACK) signal from the interface circuitry, indicating that the bus is available for ownership by the device, the IDE device transfers data to host memory via a DMA data transfer cycle. No host processor resources are utilized during a DMA data transfer. More detailed information regarding DMA data transfers to and from IDE devices can be found in ATA-3.
Some devices, however, particularly CD-ROM drives, do not have bus-mastering capability. These devices have no option but to transfer data to and from the host via a PIO data transfer, consuming valuable host processor resources. Unfortunately, CD-ROM devices use more host processor bandwidth in a data transfer than any other type of system I/O device currently available. Thus a data transfer involving a CD-ROM drive will consume considerable CPU resources, causing slower system performance.
As applications on CD-ROM and other high-bandwidth devices increase, such performance compromises are becoming more and more unacceptable. While some CD-ROM drives are beginning to be designed with bus mastering capability, the vast majority lack this ability. Thus, a device for improving the performance of computer systems during a data transfer involving a non-bus-mastering device is needed.

System and method for bus master emulation


Aspects of the disclosure relate to quantification of attack surfaces in an enterprise computing system. A computing platform may receive indications of usage of a plurality of controls associated with an enterprise computing system. The computing platform may determine, based on a mapping between the plurality of controls and a plurality of attack vectors, one or more controls of the plurality of controls that are mapped to an attack vector. The computing platform may determine respective compliance scores of the one or more controls, and determine, based on the respective compliance scores, a vulnerability score associated with the attack vector. The computing platform may transmit an indication of the determined vulnerability score associated with the attack vector.

Enterprise organizations may be susceptible to attacks intended to gain unauthorized access for malicious purposes (e.g., financial gain, disruption, espionage, etc.). Malicious attacks may use one or more attack vectors (e.g., compromised passwords, phishing attacks, viruses, trojans, adwares, malwares, ransomwares, etc.) for targeting specific hardware and/or software components in an asset (e.g., application, device, and/or system) of an enterprise organization. An attack surface may be a set of vulnerabilities that may be used for unauthorized access to one or more assets. Determination of attack surfaces may enable an enterprise organization to identify assets that may vulnerable to attacks, and ensure timely and targeted remediation measures are taken to bolster cyber defense. This may enable the organization to minimize impact to enterprise services and prevent cyber security threats. Enterprise organizations may use one or more security control systems/protocols to protect against malicious attacks. In light of potentially large numbers of attack vectors and security controls used to mitigate the attack vectors, it may be challenging to determine an overall measure of vulnerability to the enterprise organization and/or identify which particular assets are vulnerable. Further, different assets may be vulnerable to different attack vectors and may be associated with different security controls making quantitative determination of vulnerabilities for each asset challenging.

Detecting and quantifying vulnerabilities in a network system


An improved video draw poker game is disclosed that deals a player an initial five card draw poker hand plus an additional match hand of cards. After the player has held and replaced cards to obtain a final hand of cards from which draw poker winnings are determined in a conventional manner, the final hand of cards is compared to the match hand of cards to determine additional winnings based on face value and suit matches between cards in the draw hand and in the match hand. The match concept is also disclosed as used with a game played on a video slot machine.

Electronic wagering games, such as video poker and video slot machines, are more successful, wherever they are played, when players are provided with a sense of participation and control, the opportunity to make decisions, reasonable odds of winning, and what the players perceive is an improved chance to beat the odds that are normally in favor of a casino.
Poker, in its many variations, is well known and is played using a standard deck of playing cards, and no standard poker hand contains more than five cards. In poker, various combinations of five cards from a standard fifty-two card deck have significance based on both the numerical or face value of the cards and their suits. The basic object of poker is for a player to achieve a five card hand having a higher poker rank than the hands held by the player's opponents. Even when wild cards are used, they only substitute for cards in the defined combinations and do not create new or broader combinations of winning poker hands, although they improve the odds of having a winning hand.
Poker is played in a number of variations including draw poker and stud poker. Probably the most common and popular poker variation is draw poker in which the player has the opportunity to substitute one or more of the cards they are initially dealt in an effort to improve the value of their hand.
The introduction of computerized, video poker games permits players to see the representation of dealt card hands on a video screen, and the players usually play against a standard payout table retained in a computer memory. For one example, conventional video draw poker is a single player game in which a player does not play against a dealer or other players, but rather tries to achieve the highest possible ranking poker hand. A payout schedule is used to determine the amount of winnings awarded to the player for achieving specified winning combinations of cards. After an initial deal of five cards, the player is allowed to discard unwanted cards and draw replacement cards. The number of winning card combinations possible in a five card draw poker game means that, even at the lower payout value levels, a player has a relatively low probability of having a winning hand, even though lower ranked winning hands of cards are the ones which occur most frequently.
The conventional poker hand rankings that are used in video draw poker, from the highest to lowest, are: royal flush, straight flush, four of a kind, full house, flush, straight, three of a kind, two pair and a pair of jacks or better. Any hand having less than a pair of jacks or better is a losing hand. There is a wide difference in the winnings between a royal flush and a pair of jacks or better.
Over time gaming casino patrons become bored with standard versions of video poker games, as well as other video games found on slot machines, and the casinos are continually looking for new variations of video poker and other video games to continually create renewed interest and attract more players to play the games.
It would therefore be advantageous to have new video poker games and games on video slot machines which are similar to conventional games in their playing strategy but which provide for greater player interaction with the game and which would appear to provide greater opportunities for winning. Such new games would stimulate renewed interest of experienced players, and the interest of casual players, who will both find the new games exciting.

Method for playing video games with improved player interest


A method of manufacturing a hermetically sealed electrical connection is provided. The method includes providing an electrically conductive wire, surrounding the electrically conductive wire with a metal layer, providing an insulating layer between the metal layer and the electrically conductive wire, and applying a magnetically-induced compressive force to the metal layer such that the metal layer is compressed against the insulating layer and the insulating layer is compressed against the electrically conductive wire to form a hermetic seal between the metal layer and the conductive wire while maintaining the insulating layer therebetween.

Housings for electronic components typically enclose electrical circuitry to protect it from damage. However, electrical circuitry often requires more than one conductive path between the inside and the outside of the housing (e.g., one conductive path for providing power to the circuitry and one conductive path for grounding the circuitry). Thus, electrical wires may be passed through apertures in the housing. Because the apertures also allow potentially damaging substances (e.g., liquids, debris, etc.) to enter the housing, the housing and/or the circuitry is often sealed.
Sealing may be accomplished in several ways. For example, an organic material may be used to seal the housing and/or the circuitry, forming a seal between the wires and the housing. Organic materials insulate the conductive paths through the housing while sealing the housing to help protect the electronics from foreign matter that may cause damage to the electronics.
Some housings are attempted to be sealed by press-fitting two inorganic materials together to both seal and insulate the conductive paths. Sometimes, an adhesive is included between the inorganic materials. Other attempts to seal include the use of brazing. Typical methods of brazing include joining two metals by heating and melting a thin layer of brazing material between them. The brazing material cools and acts like a glue to hold the two metals together.

Hermetically sealed electrical connection assembly


A CMOS logic circuit consists of a domino gate serving as a logic gate 1 not disposed on a critical path and operating on a lower supply voltage (VDDL) and another domino gate serving as a logic gate 2 operating on a higher supply voltage (VDDH). An output of the logic gate 1 is an input to the logic gate 2. No level converter is arranged between the logic gates 1 and 2, and therefore, the power dissipation of the CMOS logic circuit is small. The CMOS logic circuit is designed according to a method that satisfies timing requirements and maximizes the number of logic gates that operate on the lower supply voltage (VDDL).

1. Field of the Invention
The present invention relates to a logic circuit of low power dissipation adopted for a large-scale integrated circuit, to a computer system employing the logic circuit, and to a method of designing the logic circuit.
2. Description of the Prior Art
CMOS logic circuits play an important role in integrated circuits because they basically pass no DC current. The power requirement of CMOS logic circuits, although once thought comparatively low, is rapidly becoming a major concern in design of personal information systems and large computer. The power dissipation P.sub.d of a CMOS logic circuit is a dynamic loss, or the power dissipation P.sub.d is mainly caused when charging and discharging load, and is proportional to a square of a high level source voltage V.sub.DD supplied to the circuit as follows: ##EQU1## where C is the effective capacitance per gate. The CMOS logic circuits usually operate between a high level source voltage and a low level source voltage such as a ground (GND) voltage. As is apparent in the expression (1), the power dissipation P.sub.d effectively decreases if the high level source voltage V.sub.DD is scaled down. Lowering of the high level source voltage V.sub.DD, however, has drawbacks such as decreasing the drift velocity of electrons in transistors and decreasing a drain current of the transistors. By such drawbacks, the lowering of the high level source voltage V.sub.DD increases a gate delay time and deteriorates the performance of the logic circuit.
Now, a logic circuit having CMOS gates operating with different supply voltages is reviewed as an example of the art for minimization of the power dissipation. FIG. 1A shows a CMOS logic circuit consisting of first and second CMOS inverters according to a prior art. The first CMOS inverter operates on a lower supply voltage VDDL and the second CMOS inverter on a higher supply voltage VDDH. The first and second inverters are directly connected to each other, and if a node N1 between the first and second inverters is at the lower supply voltage VDDL and if VDDL<VDDH-.vertline.Vthpl.vertline., a p-channel MOS transistor MP1 of the second inverter is not completely turned off to thereby generate a short-circuit current (or DC current) through the second inverter. In this specification, "Vthp" represents the threshold voltage of a pMOS, "Vthn" the threshold voltage of an nMOS, "pMOS" a p-channel MOS transistor, and "nMOS" an n-channel MOS transistor.
Since the pMOS MP1 is incompletely turned off, the short-circuit current flows from a power supply of the higher supply voltage VDDH toward a ground through the second inverter. If the first inverter operates on the higher supply voltage VDDH and the second inverter on the lower supply voltage VDDL contrary to the case of FIG. 1A, no short-circuit current will flow through the second inverter. This is because an input voltage to the second inverter is the higher supply voltage VDDH to completely turn off the pMOS MP1 of the second inverter.
FIG. 1B shows a level converter interposed between gates operating on different supply voltages in a CMOS logic circuit, to prevent the short-circuit current and reduce power dissipation. Although the level converter blocks the short-circuit current, it consumes relatively large dynamic power when it carries out a switching operation. If the CMOS logic circuit must have many level converters, the power dissipation thereof will increase.
FIG. 2A shows a CMOS logic circuit according to the prior art. The expression (1) tells that lowering the high level source voltage V.sub.DD is effective to reduce the power dissipation of a CMOS logic circuit. It is impossible, however, to drop the high level source voltage of every gate in the CMOS circuit because it will make some gates involved in critical paths unable to secure timing requirements. If the timing requirements are not secured, the total operation speed of the circuit will drop. In FIG. 2A, some gates that are not involved in critical paths are selected and set to operate on a lower supply voltage VDDL. To achieve this, the level converter of FIG. 1B must be interposed between a gate operating on the lower supply voltage VDDL and a gate operating on a higher supply voltage VDDH, to prevent a short-circuit current, in practice.
From this point, FIG. 2B shows the modified CMOS logic circuit of FIG. 2A provided with the level converters. In the circuit, some gates operate on the higher supply voltage VDDH and the others on the lower supply voltage VDDL. The number of the level converters used for these gates is large to dissipate large power, and therefore, the circuit of FIG. 2B is undesirable in terms of power dissipation.
Techniques about level converters and arts for reducing power consumption and power dissipation are disclosed in Japanese Unexamined Patent Publication (JUPP) Nos. 4-168805, 4-227318, and 2-198099. The JUPP 4-168805 discloses a dynamic level shifter that passes no short-circuit current. The level shifter carries out a sampling operation according to a clock signal and employs a cross-linked dynamic sense circuit, to reduce power dissipation and secure a high-speed operation. The JUPP 4-227318 discloses a BiCMOS buffer circuit by which an ECL level signal (lower voltage level such as from -0.9 to -1.7 Volts) is converted into a CMOS level signal (higher voltage level signal such as from 0 to 5 Volts) as quickly as possible. The JUPP 2-198099 discloses a vertical ROM (dynamic ROM) incorporating a power source clamp made of a differential amplifier and an FET. A lowered voltage (3V) by the power source clamp is used to precharge a memory array and as a source voltage for a level converter disposed after the memory array. The output of the level converter is transmitted to an external circuit operating with a higher voltage (5V). This technique improves a read speed without increasing a circuit scale or power consumption.
As mentioned above, a CMOS logic circuit may be preferred to have mixed gates operating on a lower supply voltage VDDL and gates operating on a higher supply voltage VDDH. However, any gate operating on VDDH and connected after the gate operating on VDDL generates a short-circuit current. To prevent the short-circuit current, the level converter must be arranged between them. The level converter dissipates relatively large power. If the circuit must have many level converters, the power dissipation thereof will increase to nullify the effort of decreasing power dissipation by using the two supply voltages VDDL and VDDH. As a result, the prior arts hardly reduce the power dissipation of CMOS logic circuits.

Logic circuit and method of designing the same


Embodiments of the invention describe to methods of diagnosing, classifying, and/or identifying a patient's risk of developing graft versus host disease, including severe or lethal graft versus host disease, after receiving hematopoietic cellular transplantation, a transfusion or a transplantation, but before the onset of clinical symptoms.

Embodiments of the invention relate generally to methods of diagnosing, classifying, and/or identifying a patient's risk of developing graft versus host disease, such as severe or lethal graft versus host disease, after receiving hematopoietic cellular transplantation or transfusion or transplantation including lymphocytes, but before the onset of clinical symptoms. In some embodiments, the patient's GVHD is resistant to steroids. In some embodiments, the patient can be tested at multiple time points after receiving HCT to monitor development of GVHD or TA GVHD, such as for example and not limitation, patients who are determined to be at low risk for developing GVHD or TA GVHD at an early time point.
Hematopoietic cellular transplantation (HCT) is an important treatment for high risk hematologic malignancies (e.g., leukemia, lymphoma, multiple myeloma, acute leukemia, acute myeloid leukemia, dysplastic condition, acute lymphocytic leukemia (ALL)) whose curative potential depends on the graft-versus-leukemia (GVL) effect. Graft-versus-host disease (GVHD), the major cause of non-relapse mortality (NRM) post-HCT, is closely associated with GVL.1-4 Pre-transplant clinical risk factors for GVHD include the degree of human leukocyte antigen (HLA) match between donor and recipient, recipient age, donor type, and conditioning regimen intensity.5,6,37 Some centers use one or more of these risk factors to guide GVHD prophylaxis, such as the use of anti-thymocyte globulin when the donor is not an HLA-identical sibling,7 but such approaches are globally immunosuppressive and carry their own risks, in particular of opportunistic infections.8-9
HCT is also used to treat non-malignant genetic disorders of the blood or immune system (e.g., severe combined immunodeficiency, hemophagocytic lymphohistiocytosis (HLH), hemoglobin disorders such as thalassemia, sickle cell anemia) in which a less severe GVHD effect is beneficial.
Acute GVHD affects 40-60% of patients and targets the skin, liver, and gastrointestinal (GI) tract.6,10 The median onset of acute GVHD is approximately one month after transplant.11,12 Recently, a signature of three plasma biomarkers (TNFR1, ST2, and REG3α) at the onset of clinical symptoms has been shown to predict non-relapse mortality and response to treatment.11 However, it would be beneficial for treatment options to identify a biomarker signature early after HCT could predict non-relapse mortality and GVHD before the development of overt clinical disease.
Acute GVHD is measured by dysfunction in the three organ systems: the skin, liver and gastrointestinal (GI) tract (Cutler et al., Manifestation and Treatment of Acute Graft-Versus-Host-Disease, Appelbaum et al., eds., Thomas' Hematopoietic Cell Transplantation, 4th edn. Oxford: Blackwell Publishing Ltd; 2009. p. 1287-303; Mowat et al., Intestinal Graft-vs.-Host Disease, Ferrara et al., eds., Graft-vs-Host Disease, 3rd edn. New York: Marcel Dekker; 2004. p. 279-327; Ferrara et al., Lancet 373: 1550-61, 2009). Acute GVHD of the GI tract affects up to 60% of patients receiving allogeneic HCT (Martin et al., Biol. Blood Marrow Transpl. 10: 320-7, 2004; MacMillan et al., Biol. Blood Marrow Transpl. 8: 387-94, 2002). This dysfunction manifests with nausea, vomiting, anorexia, secretory diarrhea and, in more severe cases, abdominal pain and/or hemorrhage. Thus, the etiology of diarrhea following HCT presents a common diagnostic dilemma.
Acute GVHD typically occurs between two and eight weeks after transplant, but may occur later, and is often clinically indistinguishable from other causes of GI dysfunction such as conditioning regimen toxicity, infection or medication. Endoscopic biopsy is often used to confirm, the diagnosis, but histologic severity on biopsy has not consistently correlated with clinical outcome. Clinical stage two or greater (more than one liter of diarrhea per day) is associated with reduced survival, but daily stool volume can vary considerably. Lower GI GVHD responds poorly to treatment compared to other target organs, and treatment with high-dose systemic steroid therapy carries significant risks, especially infectious complications in profoundly immunosuppressed patients. Thus, determining risk of developing GVHD and monitoring GVHD throughout treatment is important in patients with GVHD that is resistant to steroid therapies.
Transfusion-associated GVHD (TA GVHD) can occur in immunocompromised recipients (e.g., patients with inborn immunodeficiency, acquired immunodeficiency, or other malignancy), as well as non-immunocompromised recipients, when the recipient's (host's) immune system is unable to or does not recognize the donor lymphocytes (graft) as foreign, but the donor lymphocytes recognize the recipient's cells as foreign and mount an immunological attack against the recipient. TA GVHD can result from transfer of lymphocytes from the donor to the recipient, including directed blood transfusion, small bowel transplantation, and liver transplantation. The clinical symptoms of TA GVHD are the same as GVHD.
Responses to primary therapy, high dose systemic corticosteroids, have not improved and survival for patients with treatment resistant GVHD remains particularly poor.38 The clinical response after four weeks of treatment is a validated surrogate for long term survival39, but physicians usually cannot wait one month before deciding whether to modify therapy, particularly for patients who do not achieve or maintain a convincing clinical response. In clinical practice, the period of one week of treatment is commonly used to determine escalation or de-escalation of immunosuppressive therapy but this early response correlates poorly with long-term outcomes40. Patient who do not respond early to systemic steroids have a generally poor prognosis but results are inconsistent among transplant centers and biomarkers that accurately predict long term outcomes in this highly immunosuppressed population are urgently needed.
What is needed, therefore, is a method of identifying, classifying or diagnosing a patient's risk for developing (i) GVHD soon after receiving HCT or (ii) TA GHVD after a transfusion or transplantation, but before clinical symptoms of GVHD or TA GVHD develop, as well as determining the patient's risk level for developing GVHD or TA GVHD, including severe or lethal GVHD or TA GHVD, and subsequently treating the patient appropriately. In some embodiments, the patient's GVHD is resistant to steroid therapies. In some embodiments, the patient is tested at multiple time points after receiving HCT to monitor development of GVHD or TA GVHD, such as for example and not limitation, patients who are determined to be at low risk for developing GVHD or TA GVHD at an early time point. It is to such a method that embodiments of the present invention are directed.

Method of predicting graft versus host disease