A semiconductor device, a method related to the semiconductor device, and a printed circuit board are disclosed. The semiconductor device includes a chip, a package including a plurality of power voltage terminals and a plurality of ground voltage terminals, wherein the chip is disposed in the package. The semiconductor device further includes an impedance circuit connected between a DC component power voltage terminal and a ground voltage, wherein the DC component power voltage terminal is one of the plurality of power voltage terminals, and an AC component interrupter connected between the DC component power voltage terminal and a power voltage. Both the AC component and a DC component of the power voltage are applied to each of the power voltage terminals except the DC component second power voltage terminal, and the ground voltage is applied to each of the ground voltage terminals.

1. Field of the Invention
Embodiments of the invention relate to a semiconductor device, a method related to the semiconductor device, and a printed circuit board. In particular, embodiments of the invention relate to a semiconductor device including an impedance circuit and an AC component interrupter, a method related to the semiconductor device, and a printed circuit board comprising an impedance circuit.
This application claims priority to Korean Patent Application No. 10-2006-0043068, filed May 12, 2006, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Semiconductor devices are used in high-speed and high-performance systems. Thus, a semiconductor device used in such a system needs a greater operating speed and a greater number of signal input and/or output terminals. In a semiconductor device, noise proportional to "N×dl/dt" (wherein "dl/dt" is a signal variation speed and "N" is the number of varying signals) is generated and induced over a power voltage or a ground voltage. This so-called "power voltage noise" may alter the perceived frequency of data/control signals or cause circuit malfunctions. Power voltage noise is proportional to the impedance of a terminal connecting element(s) internal to a semiconductor device and external element(s). Thus, power voltage noise may be generally reduced by reducing the apparent impedance of a connection terminal. One approach to reducing the impedance of any one connection terminal reduction suggests increasing the number of connection terminals provided by the semiconductor device.
FIG. 1 is a schematic diagram illustrating a conventional semiconductor device. The semiconductor device of FIG. 1 includes a chip 1 and a package 2.
Referring to FIG. 1, terminals 10-1 are power voltage terminals of chip 1, terminals 10-2 are ground voltage terminals of chip 1, terminals 20-1 are power voltage terminals of package 2, and terminals 20-2 are ground voltage terminals of package 2. Each terminal referred to herein may be a pad. In addition, VCCL is a power voltage line of chip 1, and GNDL is a ground voltage line of chip 1. When package 2 is a ball grid array (BGA) package, terminals 20-1 and 20-2 are balls, and when package 2 is a thin small outline package (TSOP), terminals 20-1 and 20-2 are pins. The power voltage line VCCL connects power voltage terminals 10-1 inside chip 1, and ground voltage line GNDL connects ground voltage terminals 10-2 inside chip 1.
FIG. 2 is an equivalent circuit diagram illustrating the semiconductor device of FIG. 1. In FIG. 2, "Rpkg" and "Lpkg" respectively represent a package resistance and a package inductance present in series between power voltage terminal 20-1 of package 2 and power voltage terminal 10-1 of chip 1. In addition, "Cdie" indicates a static capacitance present between power voltage line VCCL and ground voltage line GNDL, "I" indicates an electrical current that flows from power voltage line VCCL in chip 1 to ground voltage line GNDL, and "Vn" indicates power voltage noise.
A parallel resonant impedance Zp of the circuit illustrated in FIG. 2 is defined by Equation 1:
      Z                          P    =                    V                                                  n            I        =                  1                              jω                                                                          C                                                                          d                                                                          i                                                                          e                    +                      1                                          R                                                                                p                                                                                k                                                                                g                            +                              jω                                                                                L                                                                                p                                                                                k                                                                                g                                                        .
A resonant frequency obtained using Equation 1 is
      1          2            π                              C                                                              d                                                              i                                                              e                                                              L                                                              p                                                              k                                                              g                      .Power voltage noise Vn increases as electrical current I increases, and power voltage noise Vn has a maximum level at the resonant frequency. The resonant frequency is inversely proportional to inductance Lpkg, so when inductance Lpkg decreases, power voltage noise Vn decreases as well.
Accordingly, as one or more of the signal variation speed and the number of varying signals increases, electrical current I increases. Thus, power voltage noise Vn induced by the power voltage or the ground voltage also increases. In addition, when inductance Lpkg of package 2 increases, power voltage noise Vn increases.
However, because it is difficult to reduce the number of varying signals, power voltage noise Vn is reduced by increasing the number of power voltage terminals 20-1 and ground voltage terminals 20-2, which reduces the impedance of the terminals and thereby reduces inductance Lpkg of package 2.
However, while it is possible to increase the number of power voltage terminals 20-1 and ground voltage terminals 20-2 to reduce inductance Lpkg of package 2, increasing the number of power voltage terminals 20-1 and ground voltage terminals 20-2 has the disadvantage of increasing the size of package 2. That is, there is a limit to the amount that power voltage noise can be reduced by increasing the number of power voltage terminals 20-1 and ground voltage terminals 20-2. In addition, even though inductance Lpkg of package 2 can be reduced by increasing the number of terminals 20-1 and 20-2, increasing the number of terminals 20-1 and 20-2 shifts the resonant frequency to a frequency that is greater than an operable frequency of the semiconductor device and does not necessarily reduce the impedance at the resonant frequency. Thus, in the semiconductor device of FIG. 1, the power voltage noise which occurs at the resonant frequency may not be reduced.
FIG. 3 is a schematic diagram illustrating a conventional semiconductor device having a configuration intended to reduce power voltage noise. The semiconductor device of FIG. 3 is substantially the same as the semiconductor device of FIG. 1 except that the semiconductor device of FIG. 3 includes an impedance circuit 3 disposed between a power voltage terminal 20-1′ of power voltage terminals 20-1 of package 2 and ground voltage GND.
Referring to FIG. 3, impedance circuit 3 is disposed outside of package 2; however, impedance circuit 3 may be disposed inside package 2 and may be disposed inside chip 1. When impedance circuit 3 is disposed outside of package 2, impedance circuit 3 may be mounted on package 2.
FIG. 4 is an equivalent circuit diagram illustrating the semiconductor device illustrated in FIG. 3. In FIGS. 2 and 4, like reference symbols indicate like elements or values. In FIG. 4, "Rpkg1" and "Lpkg1" respectively denote a first package resistance and a first package inductance present in series between a power voltage terminal 20-1 of package 2 and a power voltage terminal 10-1 of chip 1. In addition, "Rpkg2" and "Lpkg2" respectively denote a second package resistance and a second package inductance present in series between power voltage terminal 20-1′ of package 2 and power voltage terminal 10-1 of chip 1.
In FIGS. 3 and 4, impedance circuit 3 may include a capacitor; a capacitor and a resistor connected to one another in series; or a capacitor, an inductor, and a resistor connected to one another in series. In other words, compared to the semiconductor device of FIG. 1, the semiconductor device of FIG. 3 additionally includes a serial resonant circuit between a power voltage terminal 20-1′ of power voltage terminals 20-1 and ground voltage terminal 20-2.
A parallel resonant impedance Zp of the circuit illustrated in FIG. 4 is defined by Equation 1 by replacing Rpkg, Lpkg with Rpkg1, Lpkg1, respectively, and a serial resonant impedance Zs of that circuit is defined by Equation 2:
      Z                          s    =                    V                                                  n            I        =                  R                                                  t            +                        j                                (                                          ω                                                                                L                                                                                t                            -                              1                                  ω                                                                                C                                                                                t                                                      )                          .
It is assumed in Equation 2 that impedance circuit 3 includes a capacitor, an inductor, and a resistor, wherein, in Equation 2, the capacitance of the capacitor, the inductance of the inductor, and the resistance of the resistor are represented by C, L, and R, respectively. Also in Equation 2, Rt denotes Rpkg2+R, Ct denotes C×Cdie/C+Cdie, and Lt denotes Lpkg2+L. A serial resonant frequency obtained by Equation 2 is
      1          2            π                              C                                                              t                                                              L                                                              t                      .Power voltage noise Vn increases as electrical current I increases, and power voltage noise Vn has a minimum level at the serial resonant frequency. Also, because the serial resonant frequency is inversely proportional to inductance Lt, power voltage noise Vn decreases as inductance Lt decreases.
Thus, the semiconductor device of FIG. 3 reduces power voltage noise Vn by making the resonant frequency of the serial resonant circuit and the resonant frequency of the parallel resonant circuit the same and offsetting a maximum value of power voltage noise Vn obtained by resonance of the parallel resonant circuit with a minimum value of power voltage noise Vn obtained by resonance of the serial resonant circuit. That is, the semiconductor device of FIG. 3 can reduce power voltage noise Vn by reducing the impedance at the resonant frequency.
Alternatively, though it is not shown, impedance circuit 3 may be disposed between a terminal 20-2′ of ground voltage terminals 20-2 and power voltage Vcc. In another alternative, an impedance circuit may be disposed between a terminal 20-1′ of power voltage terminals 20-1 of package 2 and ground voltage GND and another impedance circuit may be disposed between a terminal 20-2′ of ground voltage terminals 20-2 and power voltage Vcc.
Semiconductor devices analogous to the one illustrated in FIG. 3 are disclosed, for example, in U.S. Pat. No. 5,926,061.
Although the semiconductor device of FIG. 3 can be arranged such that it can reduce the AC component power voltage noise and such that impedance circuit 3 can reduce the impedance at the resonant frequency, the semiconductor device of FIG. 3 has the disadvantage of having a relatively large number of terminals receiving the power voltage or the ground voltage. Thus, the semiconductor device of FIG. 3 will suffer from a relatively large drop in the power voltage and/or ground voltage, so DC component power voltage noise will increase.
FIG. 5 is a schematic diagram illustrating a conventional printed circuit board (PCB). The PCB of FIG. 5 includes a substrate 30 having a plurality of layers, a semiconductor device 32, and decoupling capacitors 34-1 to 34-4. Substrate 30 includes signal line layers 30-1 and 30-4, a power voltage layer 30-2, and a ground voltage layer 30-3. In FIG. 5, the dots ("·") each represent a connection to power voltage layer 30-2, and the "×"s each represent a connection to ground voltage layer 30-3.
FIG. 6 is an equivalent circuit illustrating the PCB of FIG. 5. In FIG. 6, "Cp" denotes a capacitance that exists in the PCB; Ll denotes an inductance between power voltage terminal 40-1 of substrate 30 and power voltage layer 30-2 of substrate 30; "Cd", "Ld", and "Rd" represent a capacitance, an inductance, and a resistance, respectively, of decoupling capacitors 34-1 to 34-4, which are represented by element 34 in FIG. 6; and "Vpn" represents the power voltage noise between power voltage line PVCCL and ground voltage line PGNDL of substrate 30. "Rpkg", "Lpkg", "Cdie", and "I" represent the same values in FIG. 6 as in FIG. 2.
A parallel resonant impedance Za of the circuit of FIG. 6 is defined by Equation 3:
      Z                          a    =                    V                                                  p                                                  n            I        =                  1                              jω                                                                          C                                                                          p                    +                      1                                          R                                                                                d                            +                              j                                                  (                                                            ω                                                                                L                                                                                d                                        -                                          1                                              ω                                                                                C                                                                                d                                                                              )                                                                        +              jω                                                  L                                                  1.
A resonant frequency obtained through Equation 3 is
      1          2            π                              C                                                              d                                                              L                                                              d                      .Power voltage noise Vpn increases as electrical current I increases, and power voltage noise Vpn has a maximum level at the resonant frequency. Also, since the resonant frequency is inversely proportional to inductance Ld, power voltage noise Vpn decreases as inductance Ld decreases.
Thus, in order to reduce the power voltage noise induced in the conventional PCB, the decoupling capacitors are added to thereby reduce inductance Ld. When "Ci", "Li", and "Ri" respectively represent a capacitance, an inductance, and a resistance of each of the decoupling capacitors, and N decoupling capacitors having the same capacitance, inductance, and resistance are connected to one another in parallel, the total capacitance, inductance, and resistance of the N decoupling capacitors are N×Ci, Li/N, and Ri/N, respectively. However, while power voltage noise can be reduced by reducing the inductance by adding decoupling capacitors to the PCB, adding the decoupling capacitors shifts the resonant frequency of the PCB to a frequency that is greater than an operable frequency of the semiconductor device mounted on the PCB, so the power voltage noise at the resonant frequency of the PCB of FIG. 5 cannot be reduced.

Semiconductor device, related method, and printed circuit board


A nutritional formulation containing an effective amount of Lacto-N-neoTetraose to simulate the growth and/or metabolic activity of Bifidobacterium is provided. A process of inhibiting bacterial infections including the step of feeding the nutritional composition to a subject is also provided.

Before birth, a fetus exists in a practically germ-free state, as the fetus is protected by the defense mechanisms of its mother. During parturition, the neonate is exposed to an abundance of bacteria from the mother's vaginal and skin flora as well as from the surrounding environment. Several weeks after its birth, the intestinal microflora of the neonate becomes established. The composition of this microflora is relatively simple and is believed to be influenced by the variety of bacteria the baby comes in contact with as well as the baby's diet.
In the first few months of life, an infant's diet consists mainly of human breast milk and/or formula. Human breast milk is well-known to contain more than 100 different oligosaccharides, some of which are genetically determined. Unfortunately, the structural similarities of many of the carbohydrates have made it difficult to isolate, identify and quantify these oligosaccharides.
Many beneficial functions have been attributed to human milk and its oligosaccharides. In fact, several studies have found that the stool of breast-fed infants differs from that of formula-fed infants. More specifically, studies have shown that stool from breast-fed infants has a lower pH, a higher proportion of bacteria of the genus Bifidobacterium, and a lower proportion of less desirable putrefactive-type bacteria than the stools from formula-fed infants. Studies have found that the low pH of human breast milk (5.0) inhibits the growth of Bacteroides spp., Clostridium, spp. and Escherichia coli (E. coli). (Beerens, H., et al., Amer. J. Clin. Nut. 33:2434-2439 (November 1980, this reference, as well as all other publications and patents disclosed herein, are incorporated by reference). Therefore, the breast-fed infant possesses a natural defense against Bacteroides, Clostridium, and E. coli, which gives the infant a resistance to gastroenteritis. Id. Furthermore, the introduction of cow's milk or formula into the diet of an exclusively breast-fed infant usually results in a substantial increase in the number of these bacteria. Petschow, B. W., et al., J. Clin. Microbio., 28:287-292 (1990).
Human breast milk is believed to contain certain factors which promote the development of a favorable intestinal bacterial flora, specifically, Bifidobacterium, which discourage the proliferation of pathogenic microbes. The growth of Bifidobacterium in the intestine of a baby is believed to be promoted by the physicochemical properties of human milk, particularly its high lactose content, which is a substrate for Bifidobacterium, its low protein content, and its low buffering capacity. Unfortunately, infant formula is believed to have a high buffering capacity which is not favorable for the growth of Bifidobacterium. Therefore, a need exists for a nutritional product for use in infants that promotes the growth and proliferation of favorable intestinal microflora such as for example, Bifidobacterium while inhibiting the growth of for example, Bacteroides, Clostridium, and E. coli.

Nutritional formulations containing Lacto-N-neoTetraose


A first and second boat member are provided, with the first member including a spring actuated torpedo directed through the hull of the first toy member arranged to engage and impact a target plate of a second boat member. Upon impact of the target plate, simulation smoke and the ejection of a stacked housing column of plates is projected from the second boat member. Impact of the target plate effects the rotation of a cam plate to impact the housing plates.

1. Field of the Invention
The field of invention relates to toy apparatus, and more particularly pertains to a new and improved naval battle toy apparatus wherein the same is arranged to simulate a submarine and ship warfare scenario.
2. Description of the Prior Art
Toy ship apparatus is indicated in the U.S. Pat. Nos. 3,419,997; 3,451,159; and 3,395,665.
The instant invention attempts to overcome deficiencies of the prior art by employing a plurality of ship members arranged to act in concert to simulate a naval battle and in this respect, the present invention substantially fulfills this need.


A resistive random access memory and a method for fabricating the same are provided. The method includes forming a bottom electrode on a substrate; forming a metal oxide layer on the bottom electrode; forming an oxygen atom gettering layer on the metal oxide layer; forming a first top electrode sub-layer on the oxygen atom gettering layer; forming a second top electrode sub-layer on the first top electrode sub-layer, wherein the first top electrode sub-layer and the second top electrode sub-layer comprise a top electrode; and subjecting the metal oxide layer and the oxygen atom gettering layer to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, resulting in a plurality of oxygen vacancies within the metal oxide layer.

1. Field of the Invention
The invention relates to a memory element, and more particularly to a resistive random access memory element.
2. Description of the Related Art
For IC (integrated circuit) designers, the ideal semiconductor memory includes random accessibility, non-volatile characteristics, increased capacity, increased speed, reduced power consumption, and unlimited reading and writing functions. Resistive random access memory (RRAM) technology has been gradually recognized as having exhibited the aforementioned semiconductor memory advantages.
Please refer to FIG. 1, a conventional single-pole operation resistive random access memory 10 with a single oxide layer is shown. The resistive random access memory 10 includes a Pt bottom electrode 14, a dielectric layer 16 of nickel oxide, and a Pt top electrode 18 sequentially formed on a substrate 12. The structure of the conventional resistive random access memory 10 can be represented as below: Pt/NiO/Pt. The conventional resistive random access memory 10, however, exhibits extremely unstable operating voltage (in particular SET voltage) after repeated and continuous conversion of resistance, resulting in loss of endurance.
U.S. Pat. Publication No. 20070215977 discloses a resistive random access memory 20 with two adjacent oxide layers, as shown in FIG. 2. The resistive random access memory 20 includes a lower electrode 22, a first oxide layer 23, a second oxide layer 24 doped with transition metals (serving as current control layer), and an upper electrode 25 sequentially formed on a substrate 21. In comparison with the conventional single-pole operation resistive random access memory 10, the resistive random access memory 20 has lower on-current. Even so, the resistive random access memory 20 does not improve upon endurance.
Therefore, it is necessary to develop a resistive random access memory with superior endurance and reduced on-current.

Resistive random access memory and method for fabricating the same

Industrial Technology Research Institute


A film-type resistor having a high power rating and a relatively low manufacturing cost. The structural strength of the resistor is derived primarily from a molded body that covers both a film-coated substrate and a heatsink. The heatsink, to which the substrate is bonded in high thermal-conductivity relationship, has an exposed flat bottom surface of relatively large area.

There has for several years been manufactured, by the assignee of applicants, a power resistor having a relatively thick copper base that serves not only as the heatsink but as the structural-support component of the resistor. A portion of this heatsink-base is apertured for mounting by a bolt to the underlying chassis. The remaining portion is indented in comparison to the first-mentioned portion, and has a ceramic substrate bonded thereto. A resistive film is provided on the side of the substrate remote from the heatsink. The film is connected to termination leads by metallization traces and solder. The substrate and the lead ends, and only part of the heatsink-base, are encapsulated in silicone molding compound, in such manner that the bottom surface of the heatsink-base----and the entire heatsink-base in the region of the bolt aperture----are exposed. The bottom heatsink surface is in flatwise contact with the chassis.
It has now been discovered that a power resistor having a vastly higher power rating than that of the resistor described above can be manufactured at less cost, and with strength adequate for the great majority of applications, although not as much strength as that of the above-indicated resistor incorporating relatively thick metal.
The power rating of the present resistor is at least double that of the earlier one referred to in the preceding paragraphs, yet the overall area of the present resistor (bottom surface) is less than 14% higher than that of the earlier one. The cost per watt of power rating of the present resistor is about one-half that of the earlier resistor referred to in the preceding paragraphs, in that there is less copper and less difficulty of assembly.

Film-type resistor assembly with full encapsulation except at the bottom surface


The present invention provides an apparatus and method for directional drilling and a method and apparatus for placing pipe in a directionally drilled bore. The present invention provides a launch tube which is placed into unstable soil. The tube is fitted with a unique cutting shoe which forces soil both into and out of the tube to prevent the tube from becoming obstructed. Preferably, the launch tube extends to bedrock or stable soil. Once the launch tube is placed a directional drill is moved through the tube and into the bedrock so that the bore may be directionally drilled in the bedrock. Once the bore is established a pipe, or a plurality of pipes, may be placed into the tube using known techniques.

Drilling a hole in soil is generally accomplished with a drill bit. Drill bits may also be configured to directionally drill holes within soil. The drill bit digs the soil and then the soil is conveyed up and out of the bore. It is difficult to drill in unstable soil. Many difficulties are raised by drilling in unstable soil. One of the difficulties is that the unstable soil tends to impede the drill bit. Also, it is difficult to convey the unstable soil out the hole as it is being drilled. Further complicating matters is that after the hole is drilled in unstable soil it has a tendency to collapse.
Unstable soils, such as gravel, are often found adjacent to rivers or streams. Thus, directionally drilling is not typically an option available when it is desired to place a bore underneath a river or stream.
In the prior art, pipe was placed in soil by first digging a trench and placing the pipe within the trench. This technique worked well for both stable and unstable soils. However, digging a trench and placing a pipe within it has many disadvantages, not the least of which is that the technique is extremely costly and time consuming.
Digging a trench is a known technique of the prior art to place pipe underneath rivers or streams. To dig a trench under a river or stream, the river or stream must be dammed up to permit backhoes to access the area for digging. If the river or stream is very deep or wide, it may have to be partially dammed so that trenches may be dug on opposite sides of the river. Further, environmental regulations restrict work on placing a pipe underneath a waterway to narrow windows of time. For example, environmental regulations often forbid work when fish are spawning, or during fishing season. Also, the location of the pipeline may be restricted as not to disturb environmentally fragile spawning grounds. All of the difficulties associated with placing pipe underneath a river extend the time it takes to place pipe under such circumstances to a year or more.
Pipes may be placed in stable or unstable soils without digging a trench by ramming the pipe into the soil and then clearing the soil from the pipe with, for example, compressed air. This is generally known as "trenchless" pipe placement. However, such "trenchless" placement of pipes may only be accomplished in a straight line. Thus, problems exist when the pipe which is to be placed is not intended to move in a straight line. Line, for example if it is desired to place a pipe underneath a river or within a metropolitan area.
There are many different types of pipe rammers. Pipe rammers typically ram pipes directly into soil. An example of a pipe ramming machine is described in U.S. Pat. No. 5,289,887 entitled "Method of Operating an Earth Boring Machine." This machine operates by directly ramming pipe into soil with pneumatic power and clearing soil from the pipe.
When ramming pipe the prior art provides that a cutting shoe may be positioned on the outside of the tube. The cutting shoe is slip fit to the outside of the pipe and held to the pipe by deformation of the shoe. The shoe and pipe combination is designed such that the soil is forced into the lumen of the tube as it is rammed. The soil is then removed from the lumen of the tube and the pipe is put in use.
A need exists to improve the placement of pipe in difficult areas. A need also exists to permit direction drilling in unstable soils.

Methods and apparatus for directionally drilling a bore and placing pipe


Integrated circuits include a silicon substrate having multiple conductive metallization lines placed thereon and vertically spaced apart from each other by polyimide insulating layers wherein a moisture resistant barrier layer is completely interposed between the polyimide layers and each metallization line. The moisture resistant barrier retards corrosion of the metallization lines by reaction products formed by the release of water from the polyimide layer by reducing the amount of water which can penetrate to the metallization lines.

1. Field of the Invention
The present invention is directed to integrated circuits containing multiple conductive metallization lines that are spaced apart from each other by polyimide insulating layers.
2. State of the Art
Integrated circuit fabrication requires the formation and patterning of conductive metallization lines, typically aluminum or aluminum silicon, to define inter-connections between various circuit elements formed in/on the device substrate. For products having a high density of such circuit elements, such as very large scale integration (VLSI) devices, it is normally necessary to form multiple metallization lines which are vertically spaced apart and separated by intermediate insulating layers. Specifically, it is well known that if individual metallization lines cross (contact) each other, then the crossing lines will short out. Accordingly, insulating layers are employed to vertically separate such individual lines thereby preventing their contact.
The insulating layers in the above-described integrated circuits are usually formed from silicon dioxide, although polyimide insulating layers offers a number of advantages over silicon dioxide layers. For example, one problem encountered in the formation of multiple metallization lines vertically spaced apart from each other is the propagation of surface irregularities. Specifically, the patterning of each metallization line results in an uneven surface whose contours are imparted to the overlying silicon dioxide insulating layer. Since integrated circuit fabrication requires substantial planarity of the insulating layer prior to addition of the next metallization line(s), additional steps are required to planarize the surface of the silicon dioxide insulating layer prior to formation of the next metallization line(s).
It is well known, however, that an advantage of polyimide insulating layers over silicon dioxide insulating layers is that the polyimide layers smooth over the irregularities of the underlying metallization lines, providing a superior surface for applying additional metallization lines. Additionally, the polyimide insulating layers are also free from discontinuities, such as small holes, which are frequently found in silicon dioxide insulating layers. Accordingly, the use of polyimides as insulating materials between metallization lines has been suggested.
Notwithstanding the above-noted benefits of polyimides insulating layers in integrated circuits, the commercial use of such layers has been significantly deterred by the fact that during fabrication and use, polyimides can release water. The released water can react with one or more of the components found in the integrated circuit (e.g., PO.sub.2 or chlorine) and generate species (e.g., acids such as H.sub.2 PO.sub.4 and HCl) that can corrode the metallization lines (i.e., corrodible species). Corrosion of the metallization lines by water released from the polyimide insulating layers leads to integrated circuits with substantially reduced useful lifetimes as compared to similar integrated circuits employing silicon dioxide in the insulating layers.

Methods of moisture protection in semiconductor devices utilizing polyimides for inter-metal dielectric


The present invention relates to a process for preparing powders of niobium suboxides or niobium, wherein the process comprising: mixing the niobium oxides as raw material with reducing agent, conducting a reaction at a temperature in the range of 600˜1300° C. in an atmosphere of vacuum or inert gas or hydrogen gas, leaching the reaction product to remove the residual reducing agent and the oxides of the reducing agent and other impurities, heat treating at a temperature of the range of 1000˜1600° C. in an atmosphere of vacuum or inert gas, and screening to obtain the powders of niobium suboxide or niobium of capacitor grade. According to the present invention, the niobium oxides were directly reduced into capacitor grade niobium suboxides or niobium with reducing agents which can be easily removed by mineral acids, wherein the speed of the reaction can be controlled and the reaction can directly reduce the niobium oxides into capacitor grade niobium suboxides or niobium powder. According to the present invention, the process is simple with high yield and high productivity. The products obtained have good flowability, low impurities, uniform distribution of oxygen, and have good electrical properties.

Niobium suboxide is a kind of ceramic material. Due to its metal conductivity, the Nb2O5 dielectric oxide film can be formed on the surface thereof, so electrolytic capacitor can be manufactured thereof.
The agglomerated niobium suboxides powders for manufacturing electrolytic capacitor shall have low content of impurities, large specific surface area, large pore size and good flowability.
There are some available techniques which can be utilized for preparing the powder of niobium suboxides and niobium as mentioned above. But some disadvantages are presented in different aspects.
Chinese patent application CN 1587066A discloses a process for preparing niobium suboxide powders by heat treating the mixture of niobium oxide and capacitor grade niobium powder, in which process the niobium suboxides were prepared through the oxidization of capacitor grade niobium powder by niobium oxide. The problem of this process is that capacitor grade niobium powders have to be prepared in advance. Moreover, after niobium oxide oxidizes capacitor grade niobium powder, some oxygen is lost, the residue is not suitable for manufacturing capacitor. As a result, the period of the process is long. In addition, since the requirements on the capacitor grade niobium powder as starting material are rigorous, this process is not suitable for the industrial scale production.
WO 00/15555 discloses a process, which includes reducing the niobium pentoxide in the presence of hydrogen gas by using the flake, particulates or powder of tantalum or niobium for sufficient time and at a sufficient temperature, which permits the transfer of oxygen atoms from the pentoxides to the reducing agent to reduce niobium pentoxide. This process has some problems as follows: tantalum or niobium in the shape of flake or particulate is used for reducing agent, thus the surface area is low and the contacting area with the oxides is low. As a result, the reaction dos not proceed uniformly, which leads to the distribution of oxygen in the product not uniform, degrading the properties of the product. Since the reducing agent of tantalum or niobium is not soluble in acid, the residue of tantalum or niobium can not be removed.

Process for preparing powder of niobium suboxides or niobium

Ningxia Orient Tantalum Industry Co., Ltd.


A seat belt webbing guide includes a main body having a slot through which seat belt webbing passes and a through hole through which a mounting bolt passes. The webbing guide includes at least one rib that is formed as a single unit with the main body along a circumferential surface of the through hole. The at least one rib extends inwardly in a radial direction of the through hole to a central axis of the through hole. At least a portion of the at least one rib is protruded from a surface of the main body toward a head of the mounting bolt.

In general, a seat belt for protecting a passenger is installed in a vehicle, and the seat belt includes seat belt webbing extending from a fixing portion mounted at a lower side portion of a vehicle seat, passing through a webbing guide, and being wound by a retractor with a predetermined force.
A tongue of the seat belt is mounted at one end of the seat belt webbing extending between the fixing portion and the webbing guide, and multiple sections of the seat belt webbing extending between the webbing guide and the retractor are slidably inserted in a vertical direction into a guide holder mounted at an inner side of the vehicle.
Also, a buckle to be coupled to the tongue is connected to the fixing portion mounted in the lower side portion of the seat.


A method of embedding watermark data in a two-color image includes assessing the suitability of each of several candidate pixels to embed a bit of watermark data. Candidate pixels for which one pixel directly above, directly below, and immediately to the left and right of the candidate pixel have different colors, are identified. In one embodiment, only a single candidate pixel in each 2×2 block is identified. Suitability of each candidate pixel may be determined based on a relationship of coefficients computed from a binary wavelet or binary lifting transform formed from the image. Data is embedded by inverting suitable pixels. A recipient of the image may assess which blocks contain watermark data, by assessing the suitability of each 2×2 block in the image to embed data and extract data without further information about the data's location.

The proliferation of digital media such as digital images, audio, video, and text images (documents) has generated significant interest in copyright protection, image annotation, and authentication. Watermarking (also referred to as data hiding) has been identified as a promising mechanism for copyright protection, annotation, and authentication. Watermarking promises the ability to embed inalterable watermark data directly in a digital file. At a later time, the data may be extracted to identify the origin of the digital file and verify its authenticity.
Typically, watermarking an image is achieved by changing a portion of the visible image. For example, single pixels within an image may be modified in order to transport data. Embedding watermark data in binary images, however, has presented significant challenges as arbitrarily changing pixels in such images is easily noticed.
Nevertheless, numerous data-hiding methods for embedding watermark data in binary documents have been proposed. For example, Min Wu, Edward Tang and Bede Liu, "Data Hiding in Digital Binary Image", IEEE International Conference on Multimedia and Expo., 2000, pp. 393-396 proposes dividing an image into blocks, and locating the most suitable pixel within each block to embed watermark data. A list, based on the block size (for example, based on 3×3 blocks), is used to rank the pixels in blocks in order of appropriateness for inverting or "flipping" the pixel. Such ranking, however, is quite subjective and may lead to mixed results depending on the image as a whole. Therefore, pixels in the image are randomly rearranged ("shuffled") to handle uneven distribution of inverted pixels in the image. The shuffled image is divided into blocks and one bit is embedded in each block in the shuffled image by inverting the "flippable" pixels which is determined by the list. Moreover, for small blocks (e.g., 8×8 pixels), it is difficult to find a suitable shuffle key to ensure that every block in the shuffled domain has at least one "flippable" pixel. As a consequence, the final result is often not pleasing, as less than ideal pixels may be flipped in some blocks, salt-and-pepper noise, or erosion will be created in this case. On the other hand, for large block sizes (e.g.16×16) only one bit is embedded in each block and the number of "flippable" pixels available to transport the hidden data is low.
Watermarking or data hiding on binary images can be classified into several categories, e.g., fragile or semi-fragile and robustness watermarks. Based on the domain used for watermarking or data hiding, it can be categorized into spatial domain techniques and transform domain techniques.
U.S. patent application Ser. No. 10/958,033, for example, discloses a method of searching for bits within a two color image that may be inverted without perceptibly affecting the nature of the image. The method proceeds by searching for specific patterns in the image. As the method operates directly on the image without transforming the image, the technique is said to operate in image space.
Image space techniques can be generally classified into several classes: text line, word or character shifting, boundary modifications, fixed block partitioning, modification of character features, modification of run-length patterns and modification of halftone images as seen in M. Chen, E. K. Wong, N. Memon and S. Adams, "Recent Development in Document Image Watermarking and Data Hiding", Proc. SPIE Conf. 4518: Multimedia Systems and Applications IV, pp. 166-176, August 2001. An early work on data hiding for binary images which enforces the ratio of black vs. white pixels in a block to be larger or smaller than one is proposed in J. Zhao and E. Koch, "Embedding Robust Labels into Images for Copyright Protection", Proc. of the Int. Congress on Intellectual Property Rights for Specialized Information, Knowledge and New Technologies, pp. 1-10, Vienna, August 1995. A group of continuous or distributed blocks are modified by switching white pixels to black and vice versa until such thresholds are reached. Modifications of the pixels are done either on the boundary of pixels, e.g., for common text documents, or distributed throughout the whole block, e.g., for dithered images. The technique is not secure enough to be directly applied for authentication and the capacity is limited by enforcing a certain percentage of black pixels.
Several pattern-based methods are discussed in for example Min Wu, E. Tang and B. Liu, "Data Hiding in Digital Binary Image", IEEE International Conf. on Multimedia and Expo., 2000, pp. 393-396; Min Wu, and Bede Liu, "Data Hiding in Binary Images for Authentication and Annotation", IEEE Transactions on Multimedia, Vol. 6, No. 4, pp. 528-538, August 2004; H. Yang and Alex C. Kot, "Data hiding for Bi-level Documents Using Smoothing Techniques", Proceedings of the 2004 International Symposium on Circuits and Systems (ISCAS'04), Vol. 5, pp. 692-695, May 2004; and H. Yang and Alex C. Kot, "Date Hiding for Text Document Image Authentication by Connectivity-Preserving", Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, Vol. 2, pp. 505-508, Mar. 18-23, 2005, Philadelphia, Pa., USA. These methods mainly look for the patterns in 3×3 or 5×5 neighborhood.
A fixed block partition method proposed by Tseng et al. (in H.-K. Pan, Y.-Y. Chen and Y.-C. Tseng, "A Secure Data Hiding Scheme for Two-Color Images," Proceedings of the Fifth Symposium on Computers and Communications, pp. 750-755, Jul. 3-6, 2000.) uses a secret key and a weight matrix to protect the hidden data. Given an image with block size of m×n, the scheme can hide as many as └log2(mn+1)┘ bits of data. However, the visual effects of the scheme are poor because of the randomness in choosing the locations for flipping. The watermarked document appears to be noisy.
Other embedding techniques require an image to be transformed from image space into some other space. An early investigation of combined spatial and frequency domain approach is proposed by Y. Liu, J. Mant, E. Wong and S. H. Low, "Marking and Detection of Text Documents Using Transform-domain Techniques"; Proc. of SPIE, vol. 3657, Electronic Imaging (EI'99) Conf. on Security and Watermarking of Multimedia Contents, pp. 317-328, San Jose, Calif., 1999, in which the watermark embedding is done in spatial domain by using the line or word shifting method whereas the watermark detection is done in frequency domain by using Cox et al.'s method. The idea is based on the observation that the watermarking effect on text document images in frequency domain is more obtrusive than pictorial image. It always creates a "dirty" background. "Cleaning" the background by thresholding light grays to white renders the watermark less obtrusive but also sharply reduces the detector response.
A further investigation of watermarking on binary images based discrete cosine transform DC components is proposed in H. Lu, X. Shi, Shi, Y. Q., Kot A. C. and L. Chen, "Watermark embedding in DC Components of DCT for binary images", The 2002 IEEE Workshop on Multimedia Signal Processing, pp. 300-303, 9-11, Dec. 2002. A preprocessing step of blurring and a post-processing step of biased binarization are required in order to embed the watermark successfully into the binary image. However, the experimental results show that the watermarked image has poor quality due to the pre-blurring and post-binarization process.
All of these techniques present their own benefits and disadvantages. As such, there is a need for other techniques of embedding data in two color images.

Software and method for embedding data in two color images


A 3-D stackable semiconductor package includes a first component and a second component. The semiconductor package is formed by stacking the back of the first component and the back of the second component together. The metal pads on the surfaces of the first component and the second component are redistributed to the edge of the first and the second components by a redistribution layer. A plurality of electric conduction posts is formed at the edge of the first and the second component to transmit electric signals between them. The semiconductor package transmits electric signals to the PCB by the electric conductive bumps.

1. Field of Invention
The invention relates to a 3-D stackable semiconductor package, and more particularly to a 3-D stackable semiconductor package combining two components back to back.
2. Related Art
Although the electronic packaging is often seen to be a minor technology of manufacturing semiconductors, it determines the size and the cost of the electronic products, and therefore its importance should not be underestimated.
Electronic packaging includes single chip packaging (SCP) and multi-chip packaging (MCP). MCP includes a multi-chip module (MCM). The MCP, also called 3-D stackable packaging, has became the mainstream of electronic packaging, for it satisfies the demands for small, cheap, and multi-functional electronic products, and therefore lowers the cost and simplifies the process of the MCP.
U.S. Pat. No. 6,359,340 discloses a multi-chip module having a stacked chip arrangement. It stacks chips on a substrate and electrically connects to each chip by wire bonding technology. Although the developed wire bonding lowers the cost, it increases the size of the module.
U.S. Pat. No. 6,611,052 discloses a wafer level stackable semiconductor package. It stacks each chip on a substrate with electric conductive bumps disposed on the surface of the chips to form electric connection. Since this semiconductor package can perform electric tests only after stacking all chips, the whole package is useless if any single chip is disabled.


The present disclosure provides a mobile terminal and a method for implementing a browser of the mobile terminal. The method comprises: the mobile terminal establishes a remote browser connection with a computing entity; and the mobile terminal remotely calls a browser engine to parse webpage data and render an image for data to be parsed through a distributed program interface of the browser engine provided by the computing entity, and receives frame dataflow from the computing entity. Through the present disclosure, the mobile terminal establishes a remote browser connection with the computing entity to share the browser engine of the computing entity based on distributed implementation as a component to the mobile terminal; the browser engine of the computing entity is remotely called to work to actually acquire the parsing capability of the CPU and other hardware resources of the computing entity; and the frame dataflow returned from the computing entity is received and presented. The mobile terminal not only acquires a relatively high computing capability but also has small power consumption; extra expense of the user is avoided and additional client software is not needed, and thereby improving the usability.

After the entry into Third Generation (3G) mobile communication era, the function of mobile terminal is richer and richer, especially the browser is becoming a common function for mobile terminal users. However, the mobile terminal is inferior to a computer in computing processing capability, and data parsing and image rendition speed, which results in the problems of unsmooth refreshing of webpage and the like when a user browses a webpage through the browser in the mobile terminal.
Therefore, an Advanced RISC Machine (ARM) processor and a mobile application processor with higher performance are applied in the mobile terminal to certainly improve the processing performance of the mobile terminal and further improve the effect of browsing web pages through the browser in the mobile terminal. However, the power consumption is also increased along with the improvement of the processing performance of the mobile terminal; meanwhile, the popularization of the high-performance processor will take some time due to its price factor, thus, the current situations of a significant market share of middle and low end mobile terminals and poor computing capacity of function mobile terminals are still not solved effectively.
Another method is to obtain a powerful computing and storage capability provided by distributed processing through a data centre by cloud computing, specifically the mobile terminal accessing 3G network or Internet. However, this method needs to occupy the bandwidth of a communication network and the user charge expense is relatively high; and meanwhile, the radio frequency part of the mobile terminal needs much power to maintain network connection.

Mobile terminal and method for implementing browser thereof


A check fixture for electrical connectors, including a pin nest made of a rigid plastic such as Delrin, having parallel slots and bores contiguous with said slots formed therein to receive one piece contact pins in precise arrangements and orientations to fit a connector to be checked. The contact pins are spring biased into the bores with blade portions extending outwardly from the slots. Wires are soldered into the butt ends of the contact pins and run to a conventional indicator. The pin nest is held within an outer body having a keyed opening to accept the connector in the proper orientation to be checked.

Electrical connectors are checked for electrical continuity through the use of a check fixture which places the terminal openings in an end surface of the connector in alignment with a set of contact pins, called "POGO" pins, which are held in a pin nest. The geometric arrangement of pins in the nest matches the geometric arrangement of terminal openings in the end surface of the connector. A typical check fixture is provided with a lever which can be rotated to urge the connector toward the contact pin nest or vice versa such that the contact pins make electrical contact with internal terminals in the connector. If all of the terminals are properly in place and properly wired, electrical continuity is established through the connector and contact pins to an indicator which passes or fails the connector according to the results of the test. A fixture of this type is described in U.S. Pat. No. 5,649,043 issued Dec. 2, 1997 to Yazaki Corporation of Tokyo, Japan, the disclosure of which is incorporated herein by reference.
It is difficult and expensive to manufacture the prior art pin nests and to arrange the "POGO" pins as contact members in the pin nests so as to properly align with the arrangement of terminal openings in the connector under test. The POGO pins, in addition to being expensive components in and of themselves, create additional electrical contact interfaces in the check fixture which add to electrical losses and can result in false indications of missing terminals.


A console device for controlling a door operator for a motor operated door includes a housing; a transmitter unit, a door operator control circuit, a user accessible door operator switch operable to control a door, an LED driven menu operably connected to the control circuit, an alphanumeric keypad and user input push buttons. The LED driven menu provides visual programming feedback to the user. The LED driven menu may provide feedback such as a home state or ready indicator, a door selector, user code or PIN assignment designators and a programming error indicator.

The present invention relates to the general field of garage door or other barrier entry operators, and more particularly, to an external wall mountable, menu driven, console device for such operators.
In the art of garage door operators and the like, it is conventional practice to provide a wall mountable, menu driven, console device to control a door operator from the exterior of a building or a residential dwelling. Console devices known in the art are of various sophistication and user friendliness. Some console devices may be hardwired to the door operator. Other console devices may provide a wireless user interface to the door operator. Still other console devices may allow for a key-like entry system to gain access. Yet other console devices provide access to operation of the garage door after performing a keypad type entry.
It is conventional practice for some console devices to grant access only after entering a user identification or authorization code such as a Personal Identification Number (PIN). Console devices in the art allow a user to program a PIN of their own choosing.
Some conventional console devices provide programming feedback by a blinking light emitting diode (LED). Blinking LEDs fail to convey the nature of an error or confirm an entry while programming. Thus, blinking LEDs in conventional console devices make programming a user determined PIN tedious and difficult.
Because console devices with blinking LEDs offer limited feedback and thus have limited programming capabilities, they also have limited functional capabilities. For example, such console devices lack certain functional capabilities such as the ability to easily program and control more than one door, program more than one unique PIN or to create a separate temporary PIN. Limiting the functional capabilities of a console device limits the usefulness and efficiency of a given console device.
In the art of garage door openers and the like, certain console devices could include liquid crystal displays (or LCDs) to convey console device information to the user. Although these displays may provide the user with some programming feedback, LCDs are costly to manufacture when compared to LEDs, require expensive backlighting, fail to operate in most outdoor environments and do not hold up well in traditional surface mount manufacturing.
Accordingly, improvements in door operator console devices are desired, particularly in menu-driven programmable keyless wall console devices. There is a need for low cost, efficient and easy to use console devices with desirable features. With an easily programmable console device, users will have the ability to, for example, control and operate more than one door, efficiently program more than one PIN number for each door and easily create temporary PINs.

Menu driven wall console with LED indicators for garage door operator


A method of controlling the idle speed of an internal combustion engine of a vehicle from a first idle speed to a second idle speed that is higher than the first idle speed in response to a driver originating indication that is independent of the acceleration control of the vehicle. The higher second idle speed is set to achieve a desired level of vehicle creep. When the driver originating indication indicates that vehicle motion is no longer desired, the engine idle speed is returned to the first lower idle speed. The change between the first lower idle speed and the second higher idle speed can be accomplished in a stepping or ramping fashion. In addition, the first and second idle speeds are adjusted in response to changes in engine operating parameters such as engine coolant temperature, changes in engine load, and vehicle speed. Tilt indication means are used to determine the inclination of the vehicle and adjust the idle speed of the vehicle to achieve the desired vehicle creep when the vehicle is on an incline.

A desirable feature of vehicles having an automatic transmission containing a fluid torque converter between the engine and the driving wheels is "creep" this being a motion, normally experienced on flat ground, either forward or backward, of the vehicle when the brake thereof is released, the vehicle is "in gear", and the engine speed is at idle. Such vehicle creep is considered a desirable feature in a vehicle as it allows the driver to achieve a slow, steady movement of the vehicle by merely releasing the brake and without having to depress the accelerator or throttle of the vehicle. Thus, by operation of the brake alone, the driver can selectively achieve a slow forward or rearward motion of the vehicle or maintain the vehicle stationary when it is in gear. This nature of operation of a vehicle is convenient and desirable in various traffic conditions and particularly in congested, slow moving traffic wherein the ability to achieve small movements of the vehicle without the need for the driver to move their foot away from the brake or to actuate the accelerator pedal is very desirable. It also provides the vehicle with a positive feel during maneuvering in traffic and when parking and prevents vehicle roll back to a certain degree during hill starts.
Vehicle creep is generated by the torque transmitted through the torque converter when the engine is idling in, for example, "drive". The main criteria used to select a torque converter for an engine having an automatic transmission is the engine torque characteristic. If the engine has relatively high low-speed torque, the torque converter will have a low stall speed therefore providing a "stiff" coupling. However, if the engine torque is generated at a higher speed, the torque converter will have a higher stall speed providing a "loose" coupling. This ensures that the engine speed is kept close to the speed that gives the highest torque during the commencement of movement of the vehicle and during general driving so as to achieve the best vehicle performance. Therefore, the level of creep is governed by the torque converter "stiffness" and the engine idle speed.
A number of criteria affect the selected engine idle speed for a vehicle and engine combination. These include body vibration due to any resonances caused by engine vibrations, combustion stability at low engine speeds, the accommodation of loads such as power steering, air conditioning and neutral drive transitions, and the amount of vehicle creep desired.
In a vehicle having an automatic transmission, when the vehicle is stationary and in "drive", the engine is loaded by the torque converter as it tries to rotate the input side of the torque converter with the output side of the torque converter being held stationary. Therefore, the higher the engine idle speed, the higher the loading on the engine, and the more energy, and therefore fuel, that is wasted primarily in the form of heat into the gearbox oil. Therefore, idle speed on an automatic vehicle has a significant effect on fuel economy. However, where a low idle speed is used in order to limit fuel consumption and exhaust emissions, that idle speed may be too low to achieve creep, or a desired level of creep.
In addition to not providing the desired level of creep, such a low idle speed may lead to undesirable shudders or jolts in the vehicle drive train if the driver depresses the accelerator harshly to rapidly increase engine speed from this low idle speed. This is due to the fact that at such low idle speeds, there is very little or no load appearing in the vehicle drive train including the torque converter. Accordingly, under hard acceleration, the unloaded engine is able to rapidly gain momentum until the speed thereof approaches the stall speed of the torque converter, at which point the engine suddenly takes up the torque converter load and subsequently transfers a shock through the drive train. This may be further accentuated as the drive train may become unloaded to the point that there no longer exists a pre-load between the various drive train components. In such a case, clearances may need to be taken up during the initial increase in idle speed which may lead to a noticeable physical shudder and audible impact.
In the case of vehicles having manual transmissions, it is also desirable to set the engine idle speed as low as possible. This however presents the problem that engagement of the clutch by the driver may stall the engine if the engine idling speed is too low.

Idle speed control for internal combustion engines

Orbital Engine Company (Australia) PTY Limited


An N-channel transistor protection circuit and method are disclosed that prevent gated diode breakdown in N-channel transistors that have a high voltage on their drain. The disclosed N-channel protection circuit may be switched in a high voltage mode between a high voltage level and a lower rail voltage. A high voltage conversion circuit prevents gated diode breakdown in N-channel transistors by dividing the high voltage across two N-channel transistors, MXU0 and MXU1, such that no transistor exceeds the breakdown voltage, Vbreakdown. An intermediate voltage drives the top N-channel transistor, MXU0. The top N-channel transistor, MXU0, is gated with a voltage level that is at least one N-channel threshold, Vtn, below the high voltage level, Vep, using the intermediate voltage level, nprot. The drain voltage of MXU0 will be at least one N-channel threshold, Vtn, lower than the input voltage level, nprot, and the drain voltage Vd of the bottom N-channel transistor, MXU1, is limited to less than the breakdown voltage, Vbreakdown.

Many semiconductor circuits require the switching of high voltages. For example, non-volatile memory devices require voltages to erase and program the memory device that are significantly higher than the voltages needed for other device functions, such as reading data from the memory or communicating with other semiconductor circuits. Thus, semiconductor circuits often employ a voltage conversion circuit to provide the high voltage levels required by the non-volatile memory and other associated devices.
FIG. 1 illustrates a conventional high voltage conversion circuit 100. As shown in FIG. 1, the high voltage conversion circuit 100 receives a logical input signal (0 volts to VDD), input, and a voltage level, Vep, e.g., on the order of 3 to 12 volts. The logical input signal, input, may be set to a low logic value, for example, to pass the voltage level, Vep, to the output and to a high logic value to pass 0 volts to the output. Thus, the output of the high voltage conversion circuit 100 switches between 0 volts and the applied voltage level. Vep, depending on the value of the applied logical input signal. The feedback transistor MP4 gates the P-channel output transistor MP7 with the applied voltage level, Vep. In this manner, the transistor MP7 is turned off when the output is low. The N-channel output driver MXU1 is gated with a high voltage level, Vdd, to pass 0 volts to the output.
Gated diode breakdown is a well-known condition that can occur in a metal oxide semiconductor (MOS) transistor, such as the transistor MXU1 in FIG. 1, under certain conditions. FIG. 2 is a cross sectional view of the transistor MXU1 of FIG. 1. The gated diode breakdown condition occurs in the junction 210 between the N+drain and the P-substrate, when a high voltage is applied to the drain of the transistor MXU1 and the gate and substrate of the transistor MXU1 are grounded. The transistor MXU1 is off in this state, but the high voltage applied to the drain can cause the reverse biased diode from the drain to the P-substrate to break down (right under the gate where the field is the highest), causing an avalanche of current and impairing circuit operation.
The actual drain voltage at which gated diode breakdown will occur, referred to herein as Vbreakdown, depends on the transistor fabrication process. In one particular process, a drain voltage on the order of 10 volts has been observed to cause a gated diode breakdown. Thus, to avoid gated diode breakdown, the voltage applied to the drain must remain below the breakdown voltage, Vbreakdown, if the gate voltage is grounded. As previously indicated, however, in many semiconductor circuits, voltages greater than the breakdown voltage are needed. For example, the erase and program operations for non-volatile memories on a secure integrated circuit require voltage levels of 10 and 12 volts, respectively, on the high voltage power supply, Vep.
FIG. 3 illustrates a known technique for avoiding gated diode breakdown, for example, in high voltage conversion circuits, when the breakdown voltage, Vbreakdown, is less than the required high voltage level, Vep. The modified high voltage conversion circuit 300 includes a logical input signal, input, that operates in the same manner as the logical input signal, input, of FIG. 1 whereby a low logic value, for example, passes the voltage level, Vep, to the output and a high logic value passes 0 volts to the output. As shown in FIG. 3, the modified high voltage conversion circuit 300 places an additional P-channel transistor MP5 and MP8 in series with the existing P-channel transistors MP4 and MP7, respectively. In this manner, when the gate voltage applied to the existing transistors MP4 and MP7 is the high voltage level, Vep, another P-channel transistor MP5 or MP8, respectively, is placed in series so that the drain voltage on transistors MP4 and MP7 will not be pulled to ground. Rather, the drain to bulk voltage on transistors MP4 and MP7 will be pulled to a value below the breakdown voltage, Vbreakdown, i.e., approximately Vep minus (Vdd plus Vtp), where Vtp, is one P-channel threshold, since the transistor bulk has a voltage level of Vep for a P-channel transistor.
Similarly, the N-channel transistor MXU1 is protected from gated diode breakdown by placing an additional N-channel transistor MXU0 in series with the existing transistor MXU1. Transistor MXU0 is gated by Vdd, thus preventing the high voltage on the output from reaching the drain of MXU1 and limiting the drain voltage on transistor MXU1 to a value below the breakdown voltage, Vbreakdown. It is noted that Vdd on the gate of MXU0 also eliminates the gated-diode condition on MXU0 because the transistor is on with a channel formed under the gate.
While the modified high voltage conversion circuit 300 effectively prevents gated diode breakdown in the N-channel transistor, the modified high voltage conversion circuit 300 is only capable of switching between an output voltage of 0 volts and the high voltage level of 10 or 12 volts. For some applications, however, it is necessary, to switch between an output voltage of Vdd and the high voltage level of 10 or 12 volts, which is not possible with the cascaded transistor implementation shown in FIG. 3.
A need therefore exists for an N-channel protection circuit that prevents gated diode breakdown in N-channel transistors that have a high voltage on their drain, and provides greater flexibility on the output voltages that may be obtained. A further need exists for an improved N-channel protection circuit that prevents gated diode breakdown in N-channel transistors by dividing the high voltage such that no transistor has a drain voltage that exceeds the breakdown voltage, Vbreakdown.

Method and apparatus for avoiding gated diode breakdown in transistor circuits


The present disclosure relates to a class of mammalian heat shock factor (HSF) inhibitors, to pharmaceutical compositions comprising these inhibitors as well as to methods for using the inhibitors. The inhibitors inhibit stress-induced expression from heat shock gene promoters. Furthermore, the inhibitors are cytotoxic to a variety of human cancer cells types.

Heat shock genes were discovered more than 50 years ago as genes whose activity is increased in cells exposed to elevated temperature (often about 5° C. above normal). Ritossa, F. (1962) Cellular and Molecular Life Sciences 18: 571-573. Protein products of these genes, heat shock proteins (HSP), were identified some ten years later. Because their functions were unknown at the time, HSPs were classified according to their subunit molecular weights (in kDa) and have been referred to as HSP90, HSP70, HSP60, etc. Further investigation of heat-inducible genes and proteins revealed that the group also included genes encoding proteins with previously known functions such as heme oxidase, ubiquitin, FKBP52, MDR1, LDH-A, etc. It also was found that there existed homologous genes encoding proteins (HSC) highly related to HSPs, the activity of which genes did not increase in response to heat. As more was learned about the functions of HSPs, the latter finding began to make sense: many HSPs act as molecular chaperones and play important roles in normal protein homeostasis (proteostasis) and trafficking. Hence, an unheated cell maintains substantial levels of HSCs and HSPs. When it is heated, it activates, or enhances the activity of, inducible heat shock genes (hsp genes) resulting in elevated levels of HSPs. The latter reaction is referred to as the heat shock protein response. Because not only heat treatment but also exposure to a wide range of noxious chemicals activates inducible hsp genes, the terms "stress protein genes", "stress proteins" and "stress protein response" are used frequently in lieu of "heat shock protein genes", "heat shock proteins" and "heat shock protein response".
Exposure of cells to above-normal temperatures (heat stress) or chemical stress leads to a degradation of protein quality control and can result in activation of apoptotic mechanisms. Elevated levels of HSPs resulting from forced over-expression or a mild stress exposure (stress pre-conditioning) inhibit apoptotic mechanisms and counteract degradation of protein quality control. Stress pre-conditioning has been shown to produce a transient tolerance that permits cells to weather severe stress conditions that would normally be lethal. Over-expression of HSPs was found to produce "therapeutic" effects in various disease models, e.g., in models of ischemia of the heart or the brain, or neurodegenerative conditions such as Parkinson's and polyglutamine diseases. It is noted that Alzheimer's, Parkinson's and all ataxias are considered to be diseases of protein folding. It is therefore not surprising that provision of extra HSPs, i.e., of extra chaperoning capacity, can be an effective means for attenuating or preventing these diseases. Akerfelt, M., Morimoto, R. I. and Sistonen, L. (2010) Nat. Rev. Mol. Cell Biol. 11: 545-555; Parsell, D. A. and Lindquist, S. 1993. Annu. Rev. Genet. 27: 437-496.
Expression of genes is mediated by so-called promoters, which are gene-associated sequence regions capable of interacting with transcription factors and components of the transcription machinery. Stress induction of hsp genes is conferred by so-called HSE sequences present within the promoters of these genes (hsp promoters). HSEs are binding sites for heat shock factors (also referred to as heat shock transcription factors) (HSF), in particular HSF1. HSF1 is a ubiquitously expressed transcription factor that is normally present in an inactive form but is reversibly activated when a cell experiences a heat or chemical stress. Vertebrate cells typically also express one or more other HSF, e.g., HSF2, HSF3 (avian) or HSF4. Akerfelt, M., Morimoto, R. I. and Sistonen, L. (2010) Nat. Rev. Mol. Cell Biol. 11: 545-555; Voellmy, R., and Boellmann, F. (2007) Adv. Exp. Med. Biol. 594: 89-99.
HSFs, including HSF1, are not essential for the normal life of a mammalian cell or even a mammalian organism, although mice lacking HSF1, HSF2 or HSF4 show important phenotypes. Jin, X. et al. (2011) Meth. Mol. Biol. 787: 1-20. Mammalian cells or organisms not expressing HSF1 are incapable of induced HSP expression as well as have an elevated sensitivity to stress. McMillan, D. R. et al. (1998) J. Biol. Chem. 273: 7523-7528; Xiao, X. et al. (1999) EMBO J. 18: 5943-5952; Christians, E. S. and Benjamin, I. J. (2006) Handb. Exp. Pharmacol. 172: 139-152.
Work carried out over the last ten plus years qualified HSF1 as a new and promising target for cancer therapy. HSF1 was shown to be critically important for effective tumorigenesis in several different animal tumor models. HSF1 was also found to play an essential role in the maintenance (viability) of a variety of different human tumor cell lines, including breast (of different p53 status, HER2 over-expression, estrogen sensitivity and metastatic potential), cervical, prostate, nerve sheath and kidney cancer lines and melanoma. Dai, C. et al. (2007) Cell 130: 1005-1018; Khaleque, M. et al. (2005) Oncogene 24: 6564-6573; Meng, L. et al. (2010) Oncogene 29: 5204-13; Nakamura, Y. et al. (2010) J. Dermatol. Sci. 60: 187-192; Solimini, N. et al. (2007) Cell 130: 986-988; Whitesell, L. and Lindquist, S. (2009). Expert Opin. Ther. Targets 13: 469-478; Zhao, Y. et al. (2009) Oncogene 28: 3689-3701. More recently, HSF1 was shown to regulate a transcriptional program specific to highly malignant cells, which program differs from that triggered by heat stress. Mendillo, M. L. et al. (2012) Cell 150: 549-562.
To the extent that this is known to date, HSF1 activity is controlled by interactions with a number of other proteins and the activities of modifying enzymes (protein kinases, etc.). Of the known proteins or enzymes affecting HSF1 activity, none is specific to HSF1. Targeting any one of the latter proteins or enzymes with an intention to also inhibit HSF1 activity is expected to have pleiotropic effects that are likely manifested in excessive general toxicity of inhibitor compounds. Hence, the most desirable anti-cancer agents that act by inhibiting HSF1 activity would be compounds that directly and specifically interact with the transcription factor. Whitesell, L. and Lindquist, S. (2009); Voellmy, R. (2006) Handb. Exp. Pharmacol. 172: 43-68. The present disclosure relates to the discovery of HSF inhibitors and their uses, e.g., as anti-cancer agents.

Inhibitors of heat shock factors and uses thereof


Cutting elements include a diamond-bonded body attached with a substrate. The substrate has a coercivity of greater than about 200 Oe, and has a magnetic saturation of from about 73 to 90. The diamond-bonded body has a compressive stress at the surface of greater than about 0.9 GPa after heat treatment, and greater than about 1.2 GPa prior to heat treatment.

Cutting elements, such as those used with bits for drilling earth formations, known in the art include a diamond surface layer or diamond table disposed on a carbide substrate. The diamond table is used to provide properties of improved wear and abrasion resistance, relative to the underlying substrate, and the substrate is used to provide an attachment structure to facilitate attachment of the cutting element to an end-use machine tool, e.g., a drill bit or the like.
Such known cutting elements have a diamond layer or diamond table formed from polycrystalline diamond (PCD) and make use of a carbide substrate such as WC—Co. While the diamond layer operates to provide improved wear and abrasion resistance to the cutter, e.g., when compared to cutting elements having a wear surface formed from tungsten carbide, the diamond layer in such known cutting elements is susceptible to breaking and/or fracturing as a result of being placed into downhole drilling conditions and being subjected to the impact forces imposed on the diamond layer as a result of such use. The breaking/fracturing and/or crack formation in the diamond layer of such cutting elements is not desired as such operates to limit or reduce the effective service life of the cutting elements.
Attempts to improve the service life of such cutting elements have focused on issues involving the delamination or breakage of the diamond body from the substrate, and have included reducing the residual compressive stress at the diamond layer-substrate interface, e.g., by heat treating the cutting elements. While such efforts may be useful in reducing or minimizing instances of breakage or delamination of the diamond body from the substrate, such performance gains are provided at the expense of compromising the wear resistance and resistance to breakage, fracture and/or crack initiation at the surface of the diamond table caused by impact forces encountered during use, which as noted above also may operate to limit the effective service life of the cutting element.

Cutting elements with impact resistant diamond body


An inhalation device for transpulmonary administration comprises: a chamber (16) for containing a pharmaceutical composition which is pulverized into fine particles by an air-generated impact for dispersal in air; an air inlet flow path (2) for introducing to the chamber (16) outside air to apply the air-generated impact to the pharmaceutical composition and for injecting the outside air toward the pharmaceutical composition; an inhalation flow path (1) for inhaling the pulverized pharmaceutical composition; a housing (9) for accommodating the chamber (16), the air inlet flow path (2), and the inhalation flow path (1); a mouthpiece (10) provided at one end of the housing (9), the mouthpiece (9) being provided with a mouth-side flow path (11) which communicates with the inhalation flow path (1), and an auxiliary flow path (12).

Such inhalation devices are provided with a chamber for containing a pharmaceutical composition, and are configured in such a way that outside air is introduced to the chamber by the inhalation-induced pressure of a user (patient) to apply an air-generated impact to the pharmaceutical composition, thus pulverizing the pharmaceutical composition into fine particles so that the user (patient) can inhale the pulverized pharmaceutical composition into the lungs from the mouth-side flow path (disclosed in Japanese Unexamined Patent Application No. 1999-221280, for example).
Such an inhalation device disadvantageously places a burden on users (patients) who have reduced pulmonary capacity or children (patients) when generating the air impact with his/her inhalation-induced pressure.
This burden on the user can be reduced by providing an auxiliary flow path which directly reaches the mouth-side flow path of the mouthpiece, not via the chamber, so that he/she can inhale outside air which is not used for applying air impact to the pharmaceutical composition (hereinafter, referred to as auxiliary air). This auxiliary air also serves to efficiently deliver the generated fine particles to the lungs.
However, because fine particles easily coalesce/agglomerate, they tend to form coalesced or agglomerated masses due to disturbances in the air flow within the mouth-side flow path of the mouthpiece that are caused when the auxiliary air is mixed with air containing the pulverized pharmaceutical composition. Thus, some of the pulverized pharmaceutical composition does not reach the user's (patient's) lungs and adheres to his/her throat.
The pulverized pharmaceutical composition is partially dispersed in the form of agglomerated masses of fine particles when the air-generated impact applied to the pharmaceutical composition is insufficient.
In view of the above-described problems, the present invention provides an inhalation device for transpulmonary administration which can prevent agglomerated masses of fine particles of the pharmaceutical composition from entering the user's (patient's) mouth.

Inhalation device for transpulmonary administration


Various embodiments include a leak detection system for a turbine compartment. In some embodiments, the leak detection system includes: a tracer fluid system fluidly connected with the turbine compartment, the tracer fluid system configured to provide an optically detectable fluid to a fluid supply of the turbine compartment; an optical detection system operably connected to the turbine compartment, the optical detection system configured to detect the presence of the optically detectable fluid in at least one location of the turbine compartment; and a control system operably connected to the tracer fluid system and the optical detection system, the control system configured to obtain data about the presence of the optically detectable fluid in the at least one location, and provide an indicator indicating a potential leak location based upon the data about the presence of the optically detectable fluid in the at least one location.

Gas turbine (GT) systems, in particular, heavy-duty gas turbine (HDGT) systems, are utilized in various locations, in part because these HDGTs can run on a variety of fuel types. For example, HDGTs can operate using fuels such as heavy oils, naphtha, diesel fuel (e.g., distillate), flare gas, synthesis gas (or, syngas), landfill gas and/or natural gas. Due to the availability of particular forms of fuel (or lack thereof), some HDGTs are designed to operate on multiple fuel types, for example, both natural gas and distillate.
Detecting fuel leaks in HDGT systems allows for safe and efficient operation of those systems. Detecting fuel leaks can be particularly helpful where an HDGT system is adapted to operate using multiple fuel types. Conventional fuel leak detection systems for HDGTs are ineffective in properly identifying leaks.


A fault-tolerant computer system employs multiple identical CPUs executing the same instruction stream, each with their own independent memory. The multiple CPUs are loosely synchronized, as by counting events such as operating cycles and stalling any CPU ahead of others. Data output references via separate busses are voted at separate ports of each of the CPUs by voting circuits which detect when all CPUs have made the same reference, and only then pass on identical references to external I/O busses. The ports may include FIFO buffers to allow output references from the asynchronous CPUs to be handled as the CPUs load the FIFOs at different times. Input data to the CPUs from the I/O busses is not voted, but is buffered to allow the CPUs to accept it at their own clock rate.

This invention relates to computer systems, and more particularly to a fault-tolerant system using multiple CPUs.
Highly reliable digital processing is achieved in various computer architectures employing redundancy. For example, TMR (triple modular redundancy) systems may employ three CPUs executing the same instruction stream, along with three separate main memory units and separate I/O devices which duplicate functions, so if one of each type of element fails, the system continues to operate. Another fault-tolerant type of system is shown in U.S. Pat. No. 4,228,496, issued to Katzman et al, for "Multiprocessor System", assigned to Tandem Computers Incorporated. Various methods have been used for synchronizing the units in redundant systems; for example, in said prior application Ser. No. 118,503, filed Nov. 9, 1987, by R. W. Horst, for "Method and Apparatus for Synchronizing a Plurality of Processors", also assigned to Tandem Computers Incorporated, a method of "loose" synchronizing is disclosed, in contrast to other systems which have employed a lock-step synchronization using a single clock, as shown in U.S. Pat. No. 4,453,215 for "Central Processing Apparatus for Fault-Tolerant Computing", assigned to Stratus Computer, Inc. A technique called "synchronization voting" is disclosed by Davies & Wakerly in "Synchronization and Matching in Redundant Systems", IEEE Transactions on Computers June 1978, pp. 531-539. A method for interrupt synchronization in redundant fault-tolerant systems is disclosed by Yondea et al in Proceeding of 15th Annual Symposium on Fault-Tolerant Computing, June 1985, pp. 246-251, "Implementation of Interrupt Handler for Loosely Synchronized TMR Systems".
As high-performance microprocessor devices have become available, using higher clock speeds and providing greater capabilities, such as the Intel 80386 and Motorola 68030 chips operating at 25-MHz clock rates, and as other elements of computer systems such as memory, disk drives, and the like have correspondingly become less expensive and of greater capability, the performance and cost of high-reliability processors has been required to follow the same trends. In addition, standardization on a few operating systems in the computer industry in general has vastly increased the availability of applications software, so a similar demand is made on the field of high-reliability systems; i.e., a standard operating system must be available.
It is therefore the principal object of this invention to provide an improved high-reliability computer system, particularly of the fault-tolerant type. Another object is to provide an improved redundant, fault-tolerant type of computing system, and one in which high performance and reduced cost are both possible. A further object is to provide a high-reliability computer system in which the performance, measured in reliability as well as speed and software compatibility, is improved but yet at a cost comparable to other alternatives of lower performance.

Multiple-processor computer system with asynchronous execution of identical code streams


The present disclosure discloses a method for preparing an anode material for lithium ion battery of a SiC nanoparticle encapsulated by nitrogen-doped graphene. The method includes: in an ammonia atmosphere, heating a SiC nanoparticle for a predetermined time, and cooling to obtain the SiC nanoparticle encapsulated by nitrogen-doped graphene.

Currently, the commercial lithium ion batteries generally use graphite as an anode material, and use lithium nickel manganese cobalt oxide (NMC) as a cathode material. Among them, the graphite anode has a theoretical mass specific capacity of 370 mAh·g−1 (without lithiation), a crystal density of 2.266 g·cm−3, and a volume specific capacity of 841 mAh·cm−3 (without lithiation) or 719 mAh·cm−3 (with lithiation). Therefore, when matched with commercial cathode materials, graphite may account for 55-60% of the total battery volume. In addition, the graphite anode has the problem of lithium dendrites at high rates, which severely restricts the application of lithium ion batteries with a graphite anode. At present, the commonly used means to improve the transport efficiency of ions in electrode materials is to shorten the transport distance of ions by adjusting the morphology and the particle size. However, since the charge and discharge processes involve the transfer of multiple electrons and multiple ions, the adjustment of the morphology and particle size cannot fundamentally change the slow kinetic process of the electrode material itself, which can lead to a significant reduction in the rate capability and cycle life of lithium ion batteries.
In summary, it is important to design a cost-effective anode material for lithium ion battery that has good structural stability and could achieve rapid electron transfer and ion transfer.

Method for preparing anode material for lithium ion battery of SiC nanoparticle encapsulated by nitrogen-doped graphene


Systems and methods for requesting, tracking and reporting modifications to a record are the subject of the present disclosure. In one embodiment, the record is associated with a customer-relationship management or CRM system. According to varying embodiments, the system and method may be implemented through the use of one or more modules and may permit one of several actions to be taken with respect to a record.

Typical CRM systems contain a variety of information displayed in a variety of different manners. However, the information is not easily visualized in a format that is efficient or convenient for a user to navigate, manage and act upon. In addition, the present limitations on these systems make it difficult, if not impossible, for a user to flag a record that requires further action and assign another user with the task of modifying that record, or reporting to one or more users that action has been taken on a record. Further, current CRM systems contain limitations with respect to tracking modifications once made by another user, or multiple users, over time. Thus, CRM systems presently suffer from a number of shortcomings with respect to managing information and/or modifying information contained within a data repository and accessible by multiple users.
It is with respect to the above issues and other problems presently faced by those of skill in the pertinent art that the embodiments presented herein were contemplated.


A signal strength for a received signal such as a radio signal transmitted over a communication network is determined. The signal strength measurement is compensated for non-linear characteristics of the receiver. The compensation is provided by taking two signal strength readings with the receiver set at two different, known, gain levels. The difference between the expected change in the signal strength and the change actually measured by the receiver is used to generate a compensated signal strength measurement A table of compensation factors is generated for each signal strength which is also utilized in generating the compensated signal strength measurement. The compensated signal strength measurement reading is transmitted to the communication network for use in mobile assisted handover.

Communication networks typically include at least one sender and one receiver. In either a wired or wireless network, a signal transmitted between the sender and receiver must be of sufficient magnitude (or strength) to allow the information contained within the signal to be discriminated from the noise which is generally present in the communication network. This may be a greater problem with a wireless network, which typically is more susceptible to noise from various interference sources.
An example of a wireless network is a radio network such as a cellular network commonly utilized for voice and/or data communications between a fixed base station covering a geographic region and mobile devices such as cellular terminals (or phones) present in the covered region. A cellular phone typically includes a radio receiver including an antenna for receiving signals and an amplifier/detector for generating a measure of the strength of received signals or noise. A signal strength measure, commonly known as Radio Signal Strength Indication (RSSI), may be expressed as a logarithmic measure of received signal strength and may be converted to a digital form by an analog to digital converter.
It is known in the prior art that radio signal strength measurements can be useful in determining which base station should serve a cellular phone during a call. In the U.S. AMPS system, the mobile phone would typically use such signal strength measurements to determine the strongest base station to which it should listen for calls during standby (idle) mode. Also in the U.S. AMPS system, base stations belonging to the cellular network typically listen to the signal strengths received from mobile phones that are actively transmitting during calls, and the network uses its measurements to determine an optimum base station for handling a call in progress. When a call in progress is switched from one base station to another, it is commonly known as "handover" or "handoff." Handoffs enable calls to be maintained even though the mobile phone may be changing location.
Cellular phones using a Time Division Multiple Access method conforming to either the European cellular standard known as GSM or any of the American TDMA standards, for example, those known respectively as D-AMPS, IS54, IS136 or PCS1900, may use spare time between transmit and receive timeslots to change frequency and monitor the signal strengths of other base stations. Several measurements of signal strength may be averaged for the same base station. The mobile phone makes measurements of the signal strengths received from surrounding base stations even during the progress of a call. Mobile Assisted Handover (MAHO) may be implemented using these measurements. The averages are typically reported to the currently serving base station, which determines if a handoff should be made to another, base station. The mobile typically reports MAHO RSSI measurements to the network station using a low-bitrate, inband signaling channel called the Slow Associated Control Channel or SACCH. The network uses SACCH measurements to determine the optimum base station to handle a call in progress, preferably the base station that the mobile phone is receiving most strongly.
In order for MAHO to operate effectively, it is preferred that the RSSI measurements that are reported to the network using the SACCH are reasonably accurate over a wide range of signal strengths that may be encountered from base stations. It is known in the prior art to employ logarithmic IF amplifiers with progressive saturation and progressive detectors in order to produce an RSSI signal approximately proportional to the logarithm of the received signal strength. See for example U.S. Pat. Nos. 5,048,059 entitled "Logpolar Signal Processing" and 5,070,303 entitled "Logarithmic Amplifier/Detector Delay Compensation" which are incorporated by referenced herein in their entirety.
Inaccuracy in RSSI measurements may occur when the RSSI value is not exactly proportional to (linearly related to) the received signal strength. Inaccuracy of RSSI measurements may also occur when measuring strong signals that partially saturate amplifing stages prior to the RSSI detectors; a 10 dB increase in received signal level may not then be passed through to the RSSI detectors due to the preceding amplifiers being unable to deliver a 10 dB increase in output signal. The RSSI detectors typically then register a lower increase in signal strength than is actually received. These inaccuracies may vary between mobile phones or change with temperature or other conditions that vary in operation. Therefore, there is a need for an improved means to account for such inaccuracies.

Received signal strength determination methods and systems