A flexible manufacturing system which includes a stack yard, a machine tool and a stacker crane. In the stack yard, a pallet group, formed by stacking a number of pellets, is stored. The pallet group is transferred to a machine tool cell by the stacker crane. Each pallet has a memory, and data of the pallet itself and the member loaded on the pallet are memorized by the pallet. There are various kinds of members such as work-piece, tool and chuck jaw. These members are stored on exclusive pallets made for each kind of the member. Of the members, each tool and chuck jaw has its own memory and memorizes its own data. The data of all the memory can be read and written; therefore, the position of the pallet, tool and chuck jaw can be controlled at all times.

1. Field of the Invention
This invention relates to a flexible manufacturing system for automatically manufacturing many kinds of processed works, and which is provided with a complex machine tool.
2. Description of the Prior Art
There is known an FMS (flexible manufacturing system) which is provided with a complex machine tool and a device for transferring loading members such as works or working tools (cutting tools, chucking jaw, etc.).
The specification of U.S. Pat. No. 4,369,563 (Molins) discloses a machine tool plant which possesses plural NC (numerical control) machine tools, stores with plural storage means, a transferring device for transferring works between store and machine tool group, and a central program controlling means for controlling the movement of the works and the processing operation.
In this system of the specification of U.S. patent, works, tool magazines and three kinds of members (jig, template, work order sheet) are stored separately, and when necessary, transferred to the specified machine tool by the transfer means. The pallet (carrier) for carrying work has an identifying sign, and also has a means for feeding back to the central program control means.
The gazette of Japanese Patent Laid-Open Showa 63-102857 discloses a manufacturing system comprised of a loading station for receiving work, jig and tool, and data, a memory for memorizing data of the loading station, a transferring means for transferring memory and work, jig, tool as a unit, an automatic machine tool placed at a distance from the loading station, and a data reading device located near the machine tool for transferring data of the memory to the control unit of the machine tool.
Also the above-mentioned Japanese Patent Laid-Open Gazette discloses a cell system provided with a storage for storing working tools, works and data.
In the machine tool plant specified in the U.S. patent specification, the data is controlled by the central program control means, and the matching of the member, such as the working tool and the data, depends on the accuracy of the operation of the operator. Therefore, when the operator makes the loading error of the working tool and the like, the system cannot find that error so it becomes the cause of trouble. Also, the means for putting the supplied working tool to the machine tool has to be done manually by the operator.
Moreover, the prior art system is delicate and thus prone to failure. For example, when data is damaged by incidents such as a power failure, it takes time for the system to be restored. Therefore it is not suitable for continuous automatic manufacturing for many hours.
The manufacturing system stated in the above-mentioned Japanese Patent Laid-Open Gazette could handle the member and the data as a unit, but because the members itself does not possess the data, the match between the member and the data depend on the operation of the operator. Therefore, it is necessary for the operator to carry out loading with accuracy based on the data give, and the detection and prevention of the loading error is impossible.
The working tool itself does not posses the data. Therefore, for example, when a breakage of the tool and the like has occurred, that tool cannot be identified, so it cannot be exchanged automatically.
Therefore, it is not suitable for continuous automatic manufacturing for many hours.


A watch case for a digital or analog watch assembly. The watch case includes a body, a time display element, an electronic speaker unit for generating musical or other acoustical sounds, and an aperture formed in the body which communicates with the speaker. Significantly, the aperture is sized so that the quality sound (e.g., music and voices) emitted therethrough from said speaker unit is clearer and more understandable than has been available heretofore.

This invention relates to a new type of watch construction, and more particularly to a watch design in which the case thereof includes within its usual dimensions a sound chamber and an electronic speaker for generating musical sounds.
Prior art wristwatches broadly describe use of "sound" in a wristwatch. However, the acoustical quality of such sound-producing devices is severely limited by the type of sound-generating devices and the size of the enclosure. For example, many of the so-called "speaker" watches to date are just achieving synthesized (simulated) speech. Typical among these are U.S. Pat. Nos. 5,440,526 and 5,197,044 which describe an integrated circuit with clock functions and the like, which not only actuates an animation feature, whereby the mouth of the character moves, but also synthesizes speech and drives the speaker. In this design, a very large and quite cumbersome case with the embodiment of the character mounted thereon is utilized, as compactness and generating quality music was never the goal, and certainly was not achieved in the prior art arrangements.
The prior art also includes analog watch designs also using piezoelectric buzzers to generate sound through a vibrating or perforated case back, thus marring the attractive and fashionable cases such analog watches strive to attain, as well as producing sounds not suitable for musical watches.
For digital watches, speakers have been used in the past to announce time when a button was pressed. However, since the level of enunciation and intonation was not very high in the first place, the positioning of the speaker in the watch case was not found to be critical, and little attention was paid to this feature.
Accordingly, it is desirable to provide a wristwatch assembly, whether analog or digital, which includes a watch case having incorporated therein an electronic speaker unit for generating sophisticated acoustical and musical sounds.


A method, computer program product, and computer system are provided. A message storage area of an adjunct processor (AP) crypto adapter is filled with a plurality of command request messages sufficient to maximize utilization and performance of the AP crypto adapter. In response to detecting an error during execution of one of the plurality of command request messages, generating an AP crypto adapter command reply message. The AP crypto adapter command reply message includes the error. In response to the error being a non-recoverable failure, determining a state of the command request message, wherein the state of the command request message comprises an in-process state or a request-pending state. The AP crypto adapter command reply message is formatted, wherein the formatted AP crypto adapter command reply message is stored in a message queue in the AP crypto adapter pending completion of machine failure recovery. The AP crypto adapter is recovered.

The present invention relates to computer systems, and more specifically to managing machine failure having an adjunct processor (AP) crypto adapter in the configuration.
Each channel attached AP crypto adapter, can be configured to operate in one of three different supported modes. Each mode has its own AP message structure and format.
When a non-recoverable failure occurs in the AP crypto adapter which prohibits completion of the requested command, the hardware architecture requires that the command requestors are notified of the AP crypto adapter failure. The AP crypto adapter is restarted to recover from the failure.
However, both operations of notifying the command requestors and restarting the AP crypto adapter cannot be done concurrently. Notifying the owners of the requested commands that the AP crypto adapter failed means restarting the failed AP crypto adapter is delayed until the owners of the requested commands dequeue the enqueued but not yet dequeued messages.
It would be advantageous to preserve the AP crypto adapter failure and report it to the owners of those requested commands after the failed crypto adapter is restarted to recover from the failure state.

International Business Machines Corporation


An improved lightbulb ceiling fixture having a canister transversely affixed to a location of a canister frame, comprising two pairs of slidable bar hangers retained on respective opposite sides of the canister frame by retaining mechanisms located on each side of the frame. Each pair of slidable bar hangers comprises an inner sliding bar hanger slidably inserted into an outer sliding bar hanger so that the overall length of the bar hanger can be readily adjusted. A bar hanger stop means such as a wing screw with an interior ratchet mechanism enables the exact overall length of the two bar hangers to be fixed at any desired joint lengthwise distance. A rotatable press fit mounting bracket with rotatable adjustment means is rotatably affixed to one exterior end of one of the sliding bar hangers, thus. The improvement facilitate speed of installation and safety for the worker installing the fixture.

1. Field of the Invention
The present invention is related to an apparatus by which a ceiling fixture is mounted and attached to beams and joists in a ceiling so that the ceiling fixture is attached in a manner which enables the lightbulb retained within the ceiling fixture to illuminate the room in which the ceiling fixture is attached.
2. Description of the Prior Art
In general, lightbulb ceiling fixtures are known in the prior art. A conventional ceiling fixture comprises a lightbulb canister transversely affixed to a rectangular canister frame, wherein a pair of flat bar hangers having a fixed length are permanently affixed to the respective opposite sides of the canister frame. One disadvantage of prior art bar hangers is that they have a fixed length which must be cut to size to accommodate given distances between ceiling beams into which the bar hangers are mounted. In addition, the mounting brackets are conventionally fixed and this increases the difficulty in attaching the ceiling fixture to the ceiling beams. Typically, a workman is standing on a tall ladder and must balance himself while trying to accurately hang the ceiling fixture.
A significant problem in the prior art is that is that a workman must balance himself on a tall ladder while holding the recessed ceiling fixture in one hand and trying to nail the mounting brackets to a wall with his other hand holding a hammer. This is both a time consuming process and is also hazardous as the workman can easily fall off the ladder and injure himself.
There is a significant need for an improved apparatus to more safely and efficiently attach a ceiling fixture to the support beams in a ceiling.

Ceiling fixture having tiltable foot hanger bars with press fit mounting brackets and slidable and adjustable hanger bars with press fit rotatable end mounting brackets


A female electrical contact including at least one axial elongate flexible spring offset from the axis (A) of the contact and elastically deformable in a transverse direction. The flexible spring (6) comprises a tail (5) engaged in a support (2, 4); a contact portion (7); an intermediate portion (8) located between the tail portion (5) and the front contact portion (7), and having longitudinal curvature of large radius without any folding so as to enable it to bend elastically in a transverse direction; and a portion (10) having a reduced moment of inertia located between the intermediate portion and the front contact portion, thereby making the spring suitable for distributing bending stresses over the entire length of the intermediate portion and facilitating progressive and continuous elastic bending thereof the three portions (5, 7, 8) and having predetermined transverse curvature imparting desired stiffness thereto; an abutment surface (2a) being located at the rear of the spring to keep its deformation within its elastic limits.

Various "split-tube" contacts of the above-specified type are known in which the tube structure makes it difficult to control the insertion/extraction force, in particular because of excessive tolerance ranges. It is therefore necessary to sort contacts so as to eliminate those which are out-of-range.
In addition, presently manufactured flexible spring contacts do not provide a sufficient safety margin. This drawback is a direct result of the structure and the method of manufacture used for the flexible springs currently in use. The contact end of a spring is obtained by folding a metal part that was initially rectilinear in the longitudinal direction. When the contact end is subjected to radial resilient forces during insertion/extraction operations, it pivots relative to the fixing portion via a fold that acts as a hinge. As a result, stresses are concentrated and the metal is subjected to considerable stress at the fold, which means that its safety factor is insufficient for certain applications, such as space applications.
Furthermore, in a flexible spring contact organized in that way, only the contact end is displaceable and it alone determines the force bearing against the pin of the male contact with which it is required to co-operate (the bearing force being determined in particular by its length and its slope), thereby determining the insertion/extraction force. The remainder of the spring is not involved in determining said force, and as a result, when considered overall, the spring is too rigid for it to be possible to obtain an insertion/extra ction force that is as small as could be desired for making it easy to operate connectors having a large or a very large number of contacts.

Flexible spring electrical contact for an electrical connector


An embedded multilayer printed circuit includes a first ground plane (105, 1205, 1405) of a multilayer printed circuit board and an embedded layer. The embedded layer includes a co-planar capacitor (110, 1210, 1410), a distributed inductor (125, 1215, 1415), and a capacitive plate (135, 1220, 1420) circuit. The capacitive plate is a plate of a vertical capacitor (270, 1305, 1505). The embedded layer further includes a node (111, 1225, 1425) of the embedded multilayer printed circuit that is formed by a connection of a first terminal of the co-planar capacitor and a first terminal of the first distributed inductor, and in some embodiments, the first capacitive plate is also connected to the node. A second terminal of one of the co-planar capacitor and the distributed inductor is connected to the first ground plane.

A significant portion of the design effort for transceivers operating above 1 GHz is in the design of frequency filtering circuits, subcircuits, and filters. Low temperature co-fired cermics (LTCCs) have been used to implement these circuits due to desirable dielectric characteristics of LTCC, and vertical (between layer) capacitors have typically been used to achieve needed capacitances. However, LTCC is more expensive than organic multilayer printed circuit boards.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.


A mammal undergoing an energy-based therapy is treated by administering at least one vasoconstrictive agent to the mammal prior to or during the procedure. The at least one vasoconstrictive agent is added in amounts sufficient to reduce or prevent vasodilation. This treatment method increases or promotes the size of the coagulation zone created after energy-based therapy.

Technical Field
The present disclosure relates to application of vasoconstrictive agents for use during the energy-based tissue therapies or procedures and, more specifically, to a treatment regimen that prevents or alleviates symptoms associated with vasodilation.
Background of the Related Art
Energy-based tissue therapies such as ablation techniques are used clinically and in the operating room for therapeutic and surgical purposes. Such techniques eliminate tissue using energy sources such as laser, microwave, radiofrequency, high-intensity focused ultrasound, cryotherapy (such as freezing below −20 C), conductive heating, and the like. Although energy-based therapies such as tissue ablation therapies and procedures have been successful in treating patients, these therapies and procedures are problematic in that they can lead to elevated concentrations of the purine nucleoside adenosine in treated areas. Adenosine can be problematic and counterproductive to the energy-based therapy and/or overall treatment. For example, adenosine can promote metastasis disease, angiogenesis, tumor cell proliferation, vasodilation, cardiac depression, low blood pressure, and other detrimental symptoms such as metastatic bloom. Moreover, adenosine can inhibit cell-mediated anti-tumor immune response. Vasodilation may be problematic during an energy-based therapy in that, among other things, it may reduce the size of the coagulation zone formed during an energy-based procedure.

This patent is subject to a terminal disclaimer.

Method of using vasoconstrictive agents during energy-based tissue therapy


A method for dynamic caching of data in a disk based operating system whereby physical memory is dynamically shared between the cache management system and the operating system. The operating system is monitored to determine the availability of free physical memory in the computer system and its location therein. A portion of free physical memory may be borrowed from the memory management component of the operating system and allocated to the cache management system for the purpose of increasing the cache memory size. The borrowed physical memory is returned to the memory management software component when needed by the operating system.

Typically, a cache is a special purpose high speed buffer interposed between a processor and a larger but slower speed data memory or data storage device. If data is stored in the cache, then it can be accessed (termed a "hit") in a shorter amount of time by the central processing unit (CPU) than if it were stored in the larger but slower data storage device. If data is not in the cache memory when referenced (termed a "miss"), then access must be made to the slower speed memory or storage device. When this occurs, the cache management software selects that portion of the cache memory containing stale data that has not been requested in a relatively long period of time and replaces it with the data just accessed from the slower data storage device.
Sophisticated cache memory schemes typically select and store data in the cache in anticipation of future use by the CPU to minimize the number of slow accesses to the slower data storage devices. As a result of the combination of the cache memory's speed, size and caching scheme, over 85% of the data requests may be performed with zero wait times. A typical cache memory has its own memory controller. When the CPU sends out a request for data, the cache memory controller intercepts it and checks the cache memory to see if the information is there so that it can be immediately accessed (a "hit"). If the information is not there (a "miss"), the cache memory controller reads the data from the slower system memory. The information is then copied into cache memory as it is sent to the processor so that all subsequent requests for that information can be read from cache memory, with zero wait times.
The advantage of caching arises from the tendency of applications to make repeated references to the same data. This clustering of data is commonly termed "locality of referencing". Performance measures include the ratio of the number of hits or misses to the total number of input/output (I/O) references. These are denominated the "hit ratio" or "miss ratio", respectively. In the past (the 1970's), hit and miss ratios were only determined from reference tables, which limited their utility to static tuning of storage devices.
In microcomputers, caches are used in two places. First, CPU chips contain separate data and instruction caches within them that lies between the CPU itself and the dynamic memory external to the chip. This creates an apparent speed up of the physical memory. Second, caching schemes are used between the microcomputer and its external mass storage devices, especially disk drives. This creates an apparent speed up of the external mass storage device. These cache schemes are referred to as "disk caches".
For example, there are many types of disk caching schemes implemented for the real mode Disk Operating System (DOS) environment. In addition, such a cache is implemented in the protected mode environment of Windows.RTM. 3.11, using memory under the control of Windows.RTM., and consists of several components, including separate cache logic and I/O logic. The memory manager component of the Microsoft Window.RTM. operating system, version 3.1x, is incorporated into the Virtual Machine Manager (VMM) virtual device. The VMM virtual device is responsible for managing the physical memory resources (i.e., RAM) of the computer system, which comprises all available physical memory at the time the Windows.RTM. program is started. Some of this physical memory can be devoted to implementing a cache system.
The cache logic component of the Windows.RTM. 3.11 operating system is VCache. VCache provides general storage and retrieval caching services to virtual device software components. A fixed proportion of the microcomputer physical memory is allocated by VCache from the VMM for caching during the duration of a Windows.RTM. session. A primary VCache client is the File Allocation Table (FAT) file system virtual device introduced with Windows.RTM. 3.11. VCache services are also available to other system or third party virtual device components.
Since the effectiveness of a caching scheme is directly related to the amount of memory it has been assigned, it is beneficial to devote as much physical memory for caching as possible. However, it is not effective to increase the cache memory size at the expense of committed virtual memory devoted to the operating system and user applications, because doing so can cause a substantial increase in virtual memory paging to the swap file that resides on disk. When virtual memory paging occurs, there is more disk access activity and therefore the system slows down.
The performance penalty incurred by a dramatic increase in paging outweighs the slight gains realized by the extra cache memory. Therefore, a fixed size cache, such as implemented by VCache, requires the user to weigh the penalties against the benefits to determine a fixed size of the disk cache before starting the operating system. This cache size will remain fixed during the entire session. Therefore, it is an object of the invention to allow the cache size to be dynamically determined while the operating system is running so that the cache management software component can automatically maintain as large a cache as possible without incurring the increased paging penalty.

Method for providing dynamic cache management in a computer system


A HEMT type device which has pillars with vertical walls perpendicular to a substrate. The pillars are of an insulating semiconductor material such as GaN. Disposed on the side surfaces of the pillars is a barrier layer of a semiconductor material such as AlGaN having a bandgap greater than that of the insulating material of the pillars. Electron flow is confined to a narrow channel at the interface of the two materials. Suitable source, drain and gate contacts are included for HEMT operation.

1. Field of the Invention
The invention in general relates to high power microwave devices.
2. Description of Related Art
In the field of microwave electronics a need exists for a high power, high frequency transistor. A widely used transistor for this purpose is the GaN (gallium nitride) based HEMT (high electron mobility transistor). The HEMT is a transistor which has a heterojunction formed between two semiconductor materials of different bandgaps. Current in such a device is confined to a very narrow channel at the junction, such current being known as a 2DEG (two dimensional electron gas).
Although the GaN based HEMT has many advantages over a GaAs (gallium arsenide) based HEMT it has several problems, one of which is the requirement for a prohibitively high substrate expense. That is, due to the thermal conductivity requirements of high power applications, SiC (silicon carbide) is used as the substrate for the layers comprising the HEMT.
A typical HEMT is structurally similar to a conventional, generally planar, field effect transistor and a particular insulating SiC substrate must be used. Such substrate can be an order of magnitude higher in cost than the widely used n+ SiC.
Accordingly, it would be desirable to have a HEMT type device which may be fabricated on an n+ SiC substrate thereby benefiting not only from the reduced substrate cost, but a higher device yield, due to the superior quality of n+ SiC substrates. It is a primary object of the present invention to provide such device.


A process for the pyrolysis of 1,2-dichloroethane (EDC) in a pyrolysis furnace (1) involves feeding liquid EDC into a convection heat transfer tube (2) for preheating, channeling an intermediate flow of preheated EDC into a radiation heat transfer tube (3) for further heating, thereby pyrolyzing a part of EDC into vinyl chloride monomer, and discharging a decomposition gas flow from the pyrolysis furnace. Potential heat is recovered from the decomposition gas by using a double tube type heat exchanger (10) consisting of outer and inner tubes, that is, by channeling the intermediate flow through the outer tube (11), channeling the decomposition gas through the inner tube (15) for heat exchange between the intermediate flow and the decomposition gas, and feeding the heat acquired intermediate flow into the radiation heat transfer tube (3).

1. Field of the Invention
This invention generally relates to a process for the pyrolysis of 1,2-dichloroethane to form vinyl chloride monomer in a pyrolysis furnace. More particularly, it relates to a method and means for recovering heat from such a pyrolytic process by adding a heat exchanger to the furnace.
2. Prior Art
As is well known in the art, vinyl chloride monomer (to be abbreviated as VCM, hereinafter) is generally produced by pyrolyzing 1,2-dichoroethane (to be abbreviated as EDC, hereinafter) in a pyrolysis furnace. The pyrolysis furnace includes a convection heat transfer conduit extending in an upper convection heat transfer region, a radiation heat transfer conduit extending in a lower radiation heat transfer region, and means for heating the radiation heat transfer conduit. Liquid EDC is fed into the convection heat transfer conduit where EDC is preheated for vaporization, and then channeled into the radiation heat transfer conduit where the gaseous EDC is pyrolyzed to generate VCM and hydrogen chloride.
In this process, for the purpose of suppressing formation of by-product impurities and formation of carbon due to excessive decomposition, pyrolysis reaction is controlled to such an extent that about 50 to 60% of the EDC feed is decomposed. Then the decomposition gas exiting from the pyrolysis furnace mainly contains VCM, hydrogen chloride, and EDC. The gas available at the pyrolysis furnace outlet (to be referred to as decomposition gas, hereinafter) is generally at a temperature of about 450 to 550.degree. C.
Various attempts were made in the prior art to recover the potential heat that the hot decomposition gas possesses for effective utilization of heat. For example, Japanese Patent Application Kokai (JP-A) No. 129233/1980 discloses a method for recovering potential heat from decomposition gas in an industrially acceptable manner. This method uses a heat exchanger for recovering heat from the decomposition gas and utilizes the recovered heat for heating EDC feed. When the high temperature the decomposition gas possesses is utilized for preheating and evaporating (or vaporizing) EDC, the fuel consumed in the pyrolysis furnace can be saved about 20 to 25%. This heat recovery method is quite advantageous from economic and environmental aspects.
The method of JP-A 129233/1980 for recovering potential heat in decomposition gas by means of a heat exchanger and utilizing the recovered heat for heating EDC feed is described in detail. After EDC is fed into a convection heat transfer region of the pyrolysis furnace for preheating EDC, the EDC is taken out of the furnace and fed to a heat exchanger which also receives the decomposition gas that has been heated hot, whereby heat is recovered from the decomposition gas. EDC is heated with the recovered heat for partial evaporation or vaporization. Thereafter, gaseous EDC is separated from the partially evaporated or vaporized EDC. The gaseous EDC is fed back to a radiation heat transfer region of the pyrolysis furnace. The heat exchanger used in this method is a single tube type heat exchanger having an inner tube extended in a jacket in a serpentine manner. Decomposition gas flows through the inner tube while liquid EDC is contained in the jacket. Since liquid EDC remains in the jacket of the single tube type heat exchanger, the amount of gaseous EDC taken out of the jacket is not always coincident with the amount of liquid EDC fed thereto. When the gaseous EDC is fed to the pyrolysis furnace, its flow rate must be controlled. Also the surface of liquid EDC in the jacket must be controlled. A new control loop is thus required. Undesirably, the control system becomes complex and the instrumentation cost is increased.
The method of JP-A 129233/1980 has another problem that since liquid EDC is evaporated or vaporized in the jacket of the heat exchanger, carbonaceous scale or carbon scale is likely to deposit on the inner wall of the jacket in contact with EDC. Undesirably the carbonaceous scale deposited on the inner wall reduces heat transfer. It is thus necessary to remove the carbonaceous deposit from the inner wall.

Method and means for recovering heat in the pyrolysis of 1,2-dichloroethane

Kashima Vinyl Chloride Monomer Co., Ltd.


Decoding blocks, memories, and methods for decoding pre-decoded address information are disclosed. One such decoding block includes a first latch and voltage shift circuit configured to receive first pre-decoded address information at first voltage levels and further configured to latch the first pre-decoded address information and shift the voltage levels of the same to second voltage levels. An address decoder includes a second latch and voltage shift circuit configured to receive second pre-decoded address information at the first voltage levels and latch and shift the voltage levels of the same to the second voltage levels. The address decoder is further configured to select control gates of the memory cells of the memory based at least in part on the first and second pre-decoded address information.

Data in electronic circuits may be stored in memory, for example, semiconductor memory. Examples of memory include volatile memory, which is limited to storing data while power is provided to the memory, and non-volatile memory, which can store data even when power is no longer provided to the memory.
Non-volatile memory typically have memory operations, for example, read, write, and erase. Data is retrieved from the memory by "reading" the data while data is stored to the memory by "writing" the data. Memory addresses are provided to the memory and decoded by internal, address decoders included m the memory to identify the particular memory to be read or written. Erase operations are used to clear data from memory, given that data may be stored indefinitely until "erased." Non-volatile memories may be structured to have erase operations occur at various levels of memory. For example, the memory area in which data is stored may be segmented into sections of memory and data for an entire section of memory may be erased during erase operations. Additionally, in some memories the sections of memory may be further segmented into memory sub-sections so that data, am be erased at level of memory sub-sections rather, mast entire sections of memory. The design of the memory area may be influenced by whether per section or per sub-section erase operations may be performed.
Non-volatile memories have become more popular as mobile and compact electronic devices, for example, mobile phones, digital cameras, portable computers, and other such devices, require storage of information even after the electronic device is switched off. Generally, it is desirable to design non-volatile memories to have compact circuitry, which can be advantageously used to design memories of greater capacity for a given space, or to make the memory smaller to allow for an electronic device including memory to have a smaller form factor. It is also generally desirable to design the memory circuitry to be efficient and use less power so that less battery power may be used daring operation.
Therefore, alternative memory circuit designs that may provide greater circuit density, smaller size, and/or lower power consumption is desirable.
Certain details are set forth below to provide a sufficient understanding of embodiments of the invention. However, it will be clear to one skilled in the art that embodiments of the invention may be practiced without these particular details. Moreover, the particular embodiments of the present invention described herein are provided by way of example and should not be used to limit the scope of the invention to these particular embodiments. In other instances, well-known circuits, control, signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the invention.
FIG. 1 illustrates a decoding block 100 according to an embodiment of the invention. The decoding block 100 may be included in a non-volatile memory, for example, a NOR Flash memory. The decoding block 100 may be associated with a partition of memory, for example, a bank or block of memory, having a cell array 10 that may be logically divided into sectors of memory 20. The sectors of memory 20 may be further divided into memory sub-sectors 30. An address pre-decoder circuit 50 configured to receive address information <R . . . 0> from an address bus pre-decodes the address information into pre-decoded address information, for example, sector information LS and page-row information including LX, LY, P, PDS and POP. Each of the LS, LX, LY, P, PD, and PDF information includes a combination of bits (i.e., binary digits).
The decoding block 100 includes a latch and voltage shift circuit 114 configured to receive the LX, LY, P, PD, and PDP information from the address pre-decoder circuit 50. The latch and voltage shift circuit 114 is configured to latch the information provided from the address pre-decoder 50 and shift the voltage levels of the LX, LY, P, PD, and PDP information to provide LX_H, LY_H, P_H, PD_H, and PDP_H information having different voltage levels. For example, the LX, LY, P, PD, and PDP information may have relatively low voltage levels (e.g., between the range of 0 and 4 volts). In some embodiments, the latch and voltage shift circuit 114 is further receives the LS information and is configured to latch the information and shift the voltage levels of the LS information to provide LS_H information having a different voltage.
The latch and voltage shift circuit 114 may provide LX_H, LY_H, P_H, PD_H, and PDP_H information that may have relatively high voltage levels (e.g., between the range of −10 and +10 volts). The latch and voltage shift circuit 114 may include an array of latch and shift circuits for latching and shitting the voltage levels of the pre-decoded address information. The latch and shift circuit 114 is provided a logic level voltage VX_PART and a logic level voltage VNEG_PART that provides the voltage levels for the logic levels of the voltage shifted pre-decoded address information. For example, the VX_PART logic level voltage may be used for pre-decoded address information having a "1" logic level provided by the latch and shift circuit 114 and the VNEG_PART logic level voltage may be used for pre-decoded address information having a "0" logic level.
The LS, LX_H, LY_H, P_H, PD_H, and PDP_H information are provided over a pre-decoded address bus 120 to an address decoder 140. Although not shown in FIG. 1, in embodiments where LS_H is provided by the latch and voltage shift circuit 114, the LS_H information may be provided over the address bus 120. The address decoder includes page-sector decoders 130(0)-130(S), each of which is coupled to control gates of the memory cells (e.g., by way of word lines coupled to the control gates of the memory cells) of a respective memory sector 20(0)-20(S). A memory array 10 includes memory cells having control gates, and may be divided into memory sectors 20. The control gates of the memory cells may be coupled to word lines. The memory sectors 20 may be divided into sub-sectors 30, for example, pages of memory. The page-sector decoders 130(0)-130(N) may be used to select the different sub-sectors for operation, such as an erase operation where all of the memory ceils of a sub-sector are erased while the memory cells of the other sub-sectors of a memory sector continue to store data. The individual sub-sectors 30 may be selected for other memory operations as well. In operation, the address decoding block 100 decodes the address information provided to the address pre-decoder circuit 50 to select memory cell(s) (e.g., a row or rows of memory cells) corresponding to the address information. As previously mentioned, the sub-sectors may be selected by the page-section decoders 130(0)-130(N) for various memory operations as well.
In some embodiments, the decoding block 100 may provide a benefit of reducing the number of voltage shift circuits needed for proper operation of a memory, as well as providing a delineation between relatively low-voltage circuitry and relatively high-voltage circuitry. Additionally, the sectors of memory 30 of the array 10 may be formed without sector-to-sector p-well separation.
FIG. 2 illustrates a latch and voltage shift circuit 200 according to an embodiment of the invention. The latch and voltage shift circuit 200 may be used for the latch and voltage shift circuit 114 of the embodiment of FIG. 1. The latch and voltage shift circuit 200 is configured to latch the logic levels of an input signal provided to an input A and shift the voltages of "0" and "1" logic levels to different voltages, for example, VN and VP voltages, respectively. The voltage shift circuit 200 outputs from an output AH a "0" logic level having the VN voltage and a "1" logic level having the VP voltage. An output AH_N provides the complementary logic level of the AH output. The VN and VP voltages may be, for example, supply voltages that may change according to an operation of the memory, as will, be explained in more detail below. In some embodiments, the latch and voltage shift circuit 200 includes circuitry configured to handle relatively high positive voltages for the VP voltage and relatively high negative voltages for the VN voltage. For example, the dimensions of the transistors, oxide thicknesses, transistor characteristics, among other things, may be selected to accommodate operation with relatively high voltages.
The latch and voltage shift circuit 200 includes first and second stages 210, 220, The first stage 210 is configured to shift the voltages of "0" and "1" logic levels of the input signal provided to the A input to a reference potential and VP. An example of a reference potential is ground, however, other reference potentials may be used as well. The second stage 220 is configured to shift the ground and VP voltages of the first stage 210 to VN and VP voltages for "0" and logic levels output at AH and AH_N. The voltages of the logic levels for the input signal at the A input may be relatively low voltages and the latch and voltage shift circuit 200 is used to shift the "0" and "1" logic levels to relatively high voltages. That is, the voltage shift circuit 200 shifts a relatively low voltage input signal to a relatively high voltage output signal. In some embodiments, the voltages may vary in the range of −10 and +10 volts, which may be used, for example, daring programming or erasing memory. It will be appreciated, however, the voltage applied to the circuitry should be within the acceptable range of operation, for example, a maximum value VP-VN of 12 volts.
The first stage 210 includes complementary-FET (i.e., field effect transistors) inverters 212 and 214, and further includes inverter 216. The inverters 212, 214 have respective output nodes 213, 215 and are coupled between a VP voltage node 230 and ground 234. The gates of the NFETs (n-channel FETs) are coupled to receive the input signal from the A input and a complement of the input signal provided by the inverter 216. The gates of the PFETs (p-channel FETs) are coupled to the output nodes 213, 215 of the other inverter. In operation, the first stage 210 latches an input signal by coupling art output node 213 to the VP voltage node 230 in response to a "0" logic level input signal and couples the output node 213 to ground 234 responsive to a "1" logic level input signal.
The second stage 220 is coupled to the output nodes 213 and 215. The second stage 220 includes a latch 226 formed, for example, from cross-coupled complementary FET inverters. The latch 226 is coupled between the VP voltage node 230 and a VN voltage node 240. Transistors 222 and 224 are coupled between the VP voltage node 230 and input/output nodes 252 and 254, respectively. The transistor 222 is coupled to the output node 215 and the transistor 224 is coupled to the output node 213. In operation, the latch and voltage shift circuit 200 may be operated in two phases, that is, for example, a data load phase and a data latch phase, as will be described in more detail below.
In the data load operation, responsive to the output node 215 being coupled to ground the transistor 222 is more conductive than transistor 228. As a result, the input/output node 252 is pulled to a higher voltage than the input/output node 254. The latch 226 latches the logic levels by coupling the node 252 to the VP voltage node 230 and coupling the node 254 to the VN voltage node 240 through the transistors of the complementary FET inverters. Operation is similar in the case where the output node 213 is coupled to ground instead of the output node 215.
Data loading is inhibited when the VP voltage is lower than the absolute value of a negative VN voltage, which results in the conductivity of transistors 222 and 224 unable to overcome the conductivity of transistors 227 and 228. This leads to a data latch condition, which may be achieved by grounding the VP voltage during the data latch phase. That is, the latch 226 latches the output of the first stage 210 responsive to the VP voltage being insufficient to overcome the drive of the VN voltage. In summary, a "0" logic level input signal at the A input results in a "0" logic level at the AH output (i.e., input/output node 254) having a VN voltage and a "1" logic level having a VP voltage at the AH_N output (i.e., input/output node 252). A "1" logic level at the A input signal results in "1" at the AH output having a VP voltage and a "0" logic level having a VN voltage at the AH_N output.
FIG. 3 illustrates a page-sector row selector 300 according to an embodiment of the invention. The row selector 300 may be included in a page-sector decoder, for example, page-sector decoders 130 of FIG. 1. The row selector 300 may be used to select the rows of memory based at least in part on pre-decoded address information for memory operations, Additionally, the row selector 300 may also be used to select a sub-sector 30 of memory based at least in part on the pre-decoded address information for memory operations.
Decode logic 310 and 320 are configured to receive pre-decoded address information from the pre-decoded address bus 120. For example, as shown in the embodiment of FIG. 3, the decode logic 310 receives the PD_H, and PDP_H pre-decoded address information and the decode logic 320 receives the LX_H and LY_H pre-decoded address information from, the pre-decoded address bus 120. As previously discussed, the LX_H, LY_H, PD_H, and PDP_H pre-decoded address information are at voltage levels set by a latch and voltage shift circuit, for example, latch and voltage shift circuit 114 of FIG. 1.
The LS pre-decoded address information, as also previously discussed, may be provided to the tow selector 300 at a relatively low voltage over the pre-decoded address has 120. A latch, and voltage shift circuit 302 is configured to shift the LS pre-decoded address information to different voltage levels to provide LS_H pre-decoded address information for use in the row selector 300. Logic-latch and voltage shift circuit 304 is configured to provide LS_S_H pre-decoded address information based at least in part on the LS pre-decoded address information and having voltage levels set by the logic-latch and voltage shift circuit 304 for use in the row selector 300. The latch and shift voltage shift circuit 302 and the logic-latch and voltage shift circuit 304 are used to provide the LS_H and LS_S_H pre-decoded address information locally, that is, at the level of the page-sector row selector. In contrast other pre-decoded address information, for example, LX_H, LY_H, PD_H and PDP_H having the voltage shifted voltage levels are provided to the row selector 300. The LS_H pre-decoded address information, is provided to the decode logic 320 and the LS_S_H pre-decoded address information is provided to the decode logic 310. In some embodiments, however, LS_H is not generated locally and may be provided to the tow selector 300 by the pre-decoded address bus 120.
The decode logic 310 include logic circuits 312<0>-312<M>. Only logic circuits 312<0> and 312<1> are illustrated in FIG. 3, but those ordinarily skilled in the art will appreciate that the decode logic 312 may include greater or fewer logic circuits 312. The logic circuits 312 provide decode selection, signals DECS_S<0>-DECS_S<M> having a logic level based at least in part on the combination of bits received by the respective logic circuits 312. In some embodiments, the logic circuits 312 may be configured to provide NAND logic operations. For example, the logic circuit 312<0> of FIG. 3 provides a logic "0" DECS_S<0> decode selection signal responsive to LS_S_H-<0>, PD_H<0>, and PDP_H<0> pre-decoded address information ail having a "1" logic level. The logic circuit 312<0> provides a logic "1" DECS_S<0> decode selection signal for all other combinations of logic levels of the LS_S_H<0>, PD_H<0>, and PDP_H<0> pre-decoded address information.
The decode logic 320 include logic circuits 322<0>-322<M> Only logic circuits 322<0> and 322<1> are illustrated in FIG. 3, but those ordinarily skilled in the art will appreciate that the decode logic 320 may include greater or fewer logic circuits 322. The logic circuits 322 provide decode selection signals SP<0>-SP<M> having a logic level based at least in part on the combination of bits received by the respective logic circuit 322, in some embodiments, the logic circuits 322 may be configured to provide AND logic operations. For example, the logic circuit 322<0> of FIG. 3 provides a logic "1" SP<0> decode selection signal responsive to LS_H<0>, LX_H<0>, and LY_H<0> pre-decoded address information all having a "1" logic level. The logic circuit 322<0> provides a logic "0" SP<0> decode selection signal for all other combinations of logic levels of the LS_H<0>, LX_H<0>, and LY_H<0> pre-decoded address information.
As will be described in more detail below, logic circuits 312 and 322 are coupled to supply voltages VXS and DECS_SECT. The VXS voltage is output by die logic circuits 312, 322 for a "1" logic level and the DECS_SECT voltage is output for a "0" logic level. The VXS voltage is provided through a voltage selection switch 330 configured to switch the VXS voltage between various voltages and the DECS_SECT voltage is provided through a voltage selection switch 340 configured to switch the DECS_SECT voltage between various voltages. For example, as illustrated in FIG. 3, the VXS voltage may be switched between a read voltage VXR, a program voltage VXP, and a reference potential, for example, ground. The DECS_SECT voltage may be switched between ground and a negative voltage VNEG, In some embodiments, the VXR voltage may be approximately 5 Volts, the VXP voltage may be approximately 10 Volts and the VNEG voltage may be approximately −10 Volts. The VXR, VXP, and VNEG voltages may vary based on operation of the memory as well, that is, for example, the VXP voltage may vary over the range of 1 to 10 Volts and the VNEG voltage may change over the range of −3 to −10 Volts. Other voltage magnitudes may be used for VXR, VXP, and VNEG as well.
The DECS_S<0>-DECS_S<M> and SP<0>-SP<M> decode selection signals are provided to multiplexer 350. The multiplexer 350 includes switches 358 that are coupled to the decode selection signals provided by the decode logic 310, 320. The switches 358 are further coupled to word lines WL (corresponding to rows of memory; the word lines coupled to control gates of memory cells) of the memory sector 20. The switches 358 are configured to couple the respective WL to the SP or DECS_S decode selection signal responsive to a respective switch control signal. As illustrated in FIG. 3, a set of switches 358 are coupled to respective SP and DECS_S decode selection signals to select rows of memory corresponding to a sub-sector 30 of memory. For example, switches 358<0> receive the decode selection signals SP<0> and DECS_S<0> and switches 358<1> receive the decode selection signals SP<1> and DECS_S<1>. Multiplexer control logic 354 provides switch control signals to control the switches 358. Logic circuits 360 included in the multiplexer control logic 354 provide switch control signals GPN<0>-GPN<S> to control switches 358 responsive to pre-decoded address information. LS_H and P_H. In some embodiments, the logic circuits 360 may be configured to provide AND logic operations. The logic circuit 360 are coupled to supply voltages VXS and DECS_SECT to output the VXS voltage for a "1" logic level and output the DECS_SECT voltage for a "0" logic level.
The combination of logic levels of the LS_H and P_H information determines which switches 358 are controlled to couple the respective word, line WL to the SP decode selection signal and which are controlled to couple the respective word line WL to the DECS_S decode selection signal. For example, the switches 358<0> and 358<1> coupled to logic circuit 360<0> are controlled to couple the word lines WL to SP<0> and SP<1>, all respectively, responsive to the LS_H<0> and P_H<0> pre-decoded address information both having a "1" logic level. In this condition, the logic circuit 360<0> provides a "1" logic level GPN<0> signal. Note, however, that the logic levels of the decode selection signals SP<0> and SP<1> may be different due to the combination of logic levels of the pre-decoded address information LX_H and LY_H. For example, the SP<0> signal may be at a "1" logic level while the SP<1> signal may be at a "0" logic level. As a result, although the switch 358<1> coupled to the logic circuit 360<0> couples the respective word line to SP<1>, the word line remains deselected.
Operation of the page-sector row selector 300 will be described for an erase operation according to an embodiment of the invention, for a selected sub-sector of memory. In operation, the page-sector row selector 300 receives the sector information LS and page-row information LX, LY, P, PD, and PDP from the address pre-decoder circuit 50. The voltage levels of the page-row information may be shifted to the voltage levels that will be used by the page-sector row selector 300 during the erase operation by the latch and voltage shift circuit 114 (FIG. 1), for example, and provided over the pre-decoded address bus 120.
The latch and voltage shift circuit 114 is also illustrated in FIG. 4 as providing the page-row information LX_H, LY_H, P_H, PD_H, and PDP_H with the shifted voltage levels. The sector information LS, as previously discussed, may be provided to the page-sector row selector 300 having voltage levels that are different than those used by the page-sector row selector 300 during the erase operation. A local latch and voltage shift circuit, for example, latch and voltage shift circuit 302 of FIG. 3, shifts the voltage levels to provide voltage shifted LS_H information having the voltage levels to be used in the page-sector row selectors 300. A local logic-latch and voltage shift circuit, for example, logic-latch and voltage shift circuit 300, 304 provides voltage shifted LS_S_H information having the voltage levels used in the page-sector row selectors 300. In some embodiments, as also previously discussed, LS_H information is provided to the page-sector row selector 300 rather than being provided locally by the latch and voltage shift circuit 302.
As further shown in FIG. 4, the logic levels for the page-row information for selecting a sub-sector of memory cells of an erase operation are LX and LY (and LX_H and LY_H) are at a logic "1." As will be described in more detail below, the memory sector 20 having the sub-sector to be erased is selected based on the LS information, and the particular sub-sector to be erased is selected by the PD and PDF information. The P information may be used to select the individual word fines WL (or all WLs of a selected sub-sector of memory) to be erased. For unselected memory sectors 20 the LS (and LS_H) information is at a "0" logic level whereas for memory sector 20 having the selected sub-sectors of memory the LS (and LS_H) information is at a "1" logic level. As illustrated in FIG. 4, the voltage levels for the voltage shifted page-row information LX_H, LY_H, P_H, and PDP_H are set by VNEG_PART and VX_PART, for example, a logic "0" has a VNEG_PART voltage and a logic "1" has a VX_PART voltage. The voltage levels of the voltage shifted sector information LS_H is also set by VNEG_PART and VX_PART. In carrying out an erase operation the VNEG_PART voltage is HVNEG (e.g., a relatively high negative voltage) and the VX_PART voltage is at a reference potential, ground GND. That is, a logic "0" is VNEG
For the unselected memory sectors 20, both LS_H and LS_S_H are at logic level "0" with reference to the logic circuits 312 and 322 of the decode logic 310, 320 (FIG. 3), the decode selection signals DECS_S are at a logic "1" and SP are at a logic "0" Moreover, the switches 358 are controlled by the multiplexer control logic 354 to couple the respective word lines WL of the unselected memory sectors to DECS_S. As previously discussed, the output voltage levels of the logic circuits 312, 322 is set to VXS for a logic "1" and set to DECS_SECT for a logic "0." During an erase operation, the VXS voltage is VXP and the DECS_SECT voltage is GND. As a result, the word lines WL of the unselected memory sectors 20 are coupled to VXP (i.e., WL coupled to DECS_S, which is at logic "1" represented by a VXS voltage of VXP).
For the memory sector 20 having the sub-sector of memory to be erased, the LX_H and LY_H page-row information are at logic level "1," LS_H is also at logic level "1," and PD_H, PDP_H and P_H may be either at logic levels "0" or "1" depending on which of the sub-sectors are selected for the erase operation. For example, for the sub-sectors that are not selected to be erased, at least one of PD_H or PDP_H is a logic level "0." As a result, for the unselected sub-sectors the decode selection signals DECS_S are at logic level "1" and SP are at logic level "1." The voltage levels for the "1" and "0" logic levels are set by VXS and DECS_SECT voltages, respectively. During an erase operation, the VXS voltage is GND and the DECS_SECT voltage is HVNEG for the memory sector having the sub-sector to be erased. Thus, for the unselected sub-sectors in the same memory sector 20 as the sub-sector to be erased both decodes selections signals DECS_S and SP are at GND. As previously discussed, the switches 358 are controlled by the switch control signals GPN provided by the multiplexer control logic 354. The logic levels of the GPN signals are controlled in part by the P page-row information (recall that LS_H is at logic level "1" for the entire memory sector having the selected sub-sector to be erased). However, given that both decode selection signals DECS_S and SP are at GND, the P information for the unselected sub-sectors of memory may be inconsequential.
For the selected sub-sector of memory to be erased, the PD_H and PDP_H information are at logic level "1" (along with LX_H and LY_H at logic level "1" and LS_H at logic level "1"). As a result, the decode selection signals DECS_S are at logic level "0" and SP are at logic level "1." As previously described, the voltage levels for the "1" and "0" logic levels are set by VXS and DECS_SECT voltages, respectively, for the memory sector having the selected sub-sector of memory to be erased. As further previously described, during the erase operation, the VXS voltage is GND and the DECS_SECT voltage is HVNEG for the memory sector having the sub-sector to be erased. The P information, may be used to select word lines WL of the selected sub-sector to be erased. For example, a particular word line or word lines are selected by the corresponding P information, having a "1" logic level. For the word lines WL that are not programmed in the selected sub-sector the P information has a "1" logic level. That is, the switches 358 that are coupled to the logic circuits 360 that receive P information having a "0" logic level couple the respective WL to DECS_S (i.e., HVNEG) for erasing. In contrast, the remaining switches 358 are controlled by the logic circuits 360 receiving P information having a logic level "0" to couple the respective WL to SP (i.e., GND). Note that although the switches 358 of the sub-sectors that are not selected to be erased may couple the respective WLs to either SP or DECS_S based on the P information, as previously discussed the SP and DECS_S voltages for those unselected sub-sectors are both at VXS (i.e., GND).
As illustrated by the previous example, the page-sector row selector 300 provides negative voltage selection of the WLs or particular WLs belonging to one (or more) sub-sectors of memory. Additionally, the unselected WLs of the unselected sub-sectors of the same memory sector are coupled to GND and the WLs of the unselected memory sectors are coupled to a high positive voltage VXP. The erase operation also does not exceed the voltage operating limit of the transistors. For example, as described to the previous example operation no transistor gate is connected simultaneously to both VXP and VNEG.
In general terms, the selected and unselected sectors of memory are configured during erase operations by managing the voltage supply connections. The erase selection "pattern" for selecting a WL or WLs to be erased is propagated to the selected sub-sector of memory using the appropriate voltage levels for the erase operation. The word line selection pattern applied to the sector of memory having memory to be erased addresses a specific subset of word lines to be erased. The WLs associated with the SP and DECS_S pair is used to provide the first and second logic level voltages for a selected memory sub-sector. As also illustrated by the previous example, the sub-sector-erase-pattern is carried by the PD_H and PDP_H busses while the individual WL erase pattern is set adding a "reverse" pattern on the P_H bus.
Managing voltage levels and logic voltage levels as previously described allow propagation of the erase-selection pattern for a selected memory sub-sector using a sector selection information (i.e., LS) having the "canonical" logic "1" for the selected sector of memory and "0" for the non-selected sectors of memory. Additionally, the busses for the pre-decoded address information are shifted to the same voltage level and logic voltage levels as used in the selected sector of memory.
A possible switching sequence to access the erase phase may be possible during "non stressing" auxiliary phases, where the VXF and VNEG voltages are set to relatively "mild" V+ & V− values, and the decoding gates can still work as a logic, for example, VXS=VXP and DECS_SECT=VNEG in all the sectors of memory. The non-erase signal (ER/) is put to a "0" logic level and the pre-decoded buses set to the erase configuration, as previously described. As a result the WL selection pattern is propagated in the selected sector of memory while in the non-selected sectors of memory the LS_S and LS pre-decoded address information having a "0" logic level creates a "bulk 0" on the SP and GPN lines and a "bulk 1" on the DECS_S lines. The related WLs are therefore set to a "bulk 1," which may be held during the erase phase by the SP and GPN paths. During the erase phase (when the voltage level are set as shown in FIG. 4), the SP, GPN and DECS_S lines may reverse their configuration, that is, apply "bulk 1" on the SP and GPN lines and "bulk 0" on the DECS_S lines.
Although the operation of the page-sector row selector 300 was described with reference to a page memory, the page-sector row selector 300 may be used with a non-page memory as well. Those ordinarily skilled in the art will have sufficient understanding based on the description provided herein to make modifications as necessary for use with non-page memories.
FIG. 5A illustrates a latch and voltage shirt circuit 500 according to an embodiment of the invention. The latch and voltage shift circuit 500 may be used for the voltage shift circuit 302 of the embodiment of the page-sector row selector 300 of FIG. 3. In operation, the latch, and voltage shift circuit 500 provides pre-decoded information LS_H having voltage levels set by a VX_PART voltage and a VNEG_PART voltage (e.g., a "1" logic level has the VX_PART voltage and a "0" logic level has the VNEG_PART voltage) responsive to the pre-decoded information LS. The VX_PART and VNEG_PART voltages may be system supply voltages generally provided to the circuitry of the system for operation. As previously discussed, the LS pre-decoded information may have relatively low voltage levels and the LS_H pre-decoded information may have relatively high voltage levels for use in the page-sector row selector 300, for example. In some embodiments, the latch and voltage shift circuit 200 of FIG. 2 may be used as the latch and voltage shift circuit 500.
FIG. 5B illustrates logic-latch and voltage shift circuit 510 according to an embodiment of the invention. The logic-latch and voltage shift circuit 510 may be used for the logic-latch and voltage shift circuit 304 of the embodiment of the page-sector row selector 300 of FIG. 3. The logic-latch and voltage shift circuit 510 includes logic 514 and a latch and voltage shift circuit 512. The logic 514 may be an OR logic gate, as illustrated in FIG. 5B. The logic 514 provides pre-decoded information LS_S based on the logic levels of the LS pre-decoded information and an erase enable signal ER. In the embodiment illustrated in FIG. 5B, the ER signal is an active low signal, designated as ER/, which when active enables erase operations for the page-sector row selector 300, for example, while forcing LS_S_H to be "1" during all operations other than erase. This, together with a "bulk 1" forcing of PD and PDP lines, may provide for the DECS_S to be forced to "0" in the non-erase operation. The latch and voltage shift circuit 512 provides pre-decoded information LS_S_H responsive to the LS_S information. The LS_S_H information has voltage levels set by a VX_PART voltage and a VNEG_PART voltage (e.g., a "1" logic level has the VX_PART voltage and a "0" logic level has the VNEG_PART voltage). The LS_S_H pre-decoded information may have relatively high voltage levels for use in the page-sector row selector 300, for example.
FIG. 5C illustrates logic circuit 520 according to an embodiment of the invention. The logic circuit 520 may be used for the logic circuits 312 of the embodiment of the page-sector row selector 300 of FIG. 3. The logic circuit 520 includes logic 522 and a driver 524. The pre-decoded information LS_S_H, PDP_H, and PD_H are provided to the logic 522, which is configured to provide an output based on the logic levels of the LS_S_H, PDP_H, and PD_H information. The output has voltage levels set by a VX_PART voltage and a DECS_SECT voltage (e.g., a logic "1" has a VX_PART voltage level and a logic "0" has a DECS_SECT voltage). The logic 522 is illustrated as a NAND gate for the embodiment of FIG. 5C, but other logic functions may be used as needed. The VX_PART voltage, as previously discussed, may be a system supply voltage generally provided to the circuitry of the system for operation. The DECS_SECT voltage may be a local supply voltage provided to the circuitry of a page-sector row selector, for example, for operation. The output of the logic 522 is provided to the driver 524, which provides decode selection signals DECS_S and its logical complement DECS_N. The voltages of the DECS_S and DECS_N decode selection, signals are set by voltages VXS and DECS_SECT. The VXS voltage may be a local supply voltage provided to the circuitry of a page-sector row selector, as the DECS_SECT voltage.
FIG. 5D illustrates a logic circuit 530 according to an embodiment of the invention. The logic circuit 530 may be used for the logic circuits 322 of the embodiment of the page-sector row selector 300 of FIG. 3. The logic circuit 530 includes logic 532 and an inverter 534. The pre-decoded information LS_H, LX_H, and LY_H are provided to the logic 532, which is configured to provide an output based on the logic levels of the LS_H, LX_H, and LY_H information. The output has voltage levels set by a VX_PART voltage and a DECS_SECT voltage (e.g., a logic "1" has a VX_PART voltage level and a logic "0" has a DECS_SECT voltage). The logic 532 is illustrated as a NAND gate for the embodiment of FIG. 5D, but other logic functions may be used as needed. The output of the logic 532 is provided to the inverter 534, which provides decode selection signals SP. The SP decode selection signal has a logic level that is the complement of the output from the logic 532. The voltages of the SP decode selection signal is set by voltages VXS and DECS_SECT.
FIG. 5E illustrates a logic circuit 540 according to an embodiment of the invention. The logic circuit 540 may be used for the logic circuits 360 of the embodiment of the page-sector row selector 300 of FIG. 3. The logic circuit 540 includes logic 542 and a driver 544. The pre-decoded information LS_H and P_H are provided to the logic 542, which is configured to provide an output based on the logic levels of the LS_H and P_H information. The output has voltage levels set by a VX_PART voltage and a DECS_SECT voltage (e.g., a logic "1" has a VX_PART voltage level and a logic "0" has a DECS_SECT voltage). The logic 542 is illustrated as a NAND gate for the embodiment of FIG. 5E, but other logic functions may be used as needed. The output of the logic 542 is provided to the driver 524, which provides switch control signals CP and its logical complement GPN. The voltages of the GP and GPN switch control signals are set by voltages VXS and DECS_SECT.
FIG. 5F illustrates a word line selection circuit 550 according to an embodiment of the invention. The word line selection circuit 550 may be used for the word line selection circuits 358 of the embodiment of the page-sector row selector 300 of FIG. 3. The word line selection circuit 550 includes complementary-FET inverter 552 and transistors 554 and 556 coupled to a respective word line WL. The word line WL is coupled to the voltage of the SP decode selection signal responsive to the PFET of the inverter 552 or the transistors 554 or 556 being activated to be conductive. As known, the PFET and transistor 556 are conductive responsive to the voltages of the GP switch control signal or the DECS_N decode selection signal being at logic level "0" (while the SP line is at logic level "1"). The transistor 554 is conductive responsive to the voltage of the GPN switch control signal being at logic level "1" (while the DECS_S logic level is at "0"). As previously discussed, the VXS and DECS_SECT voltages, which set the voltage of the GP, GPN, and SP signals may change according to the operation performed, for example, read memory, program memory, or erase memory.
FIGS. 5A-5F illustrate embodiments of circuitry that may be used to provide the voltages during an erase operation as described with reference to FIG. 4. As a result, the circuitry may provide during an erase operation (1) propagation of the sub-sector or signal WL selection pattern in the selected sector of memory and (2) force an "all 1" pattern to the WLs in the unselected sectors of memory (forcing to "1" the LS and GPN lines).
A flash memory 600 that includes the decoding block according to an embodiment of the invention is shown in FIG. 6. The flash memory 600 includes an array 630 of flash memory. The memory may be arranged m sectors of memory 620(0)-620(S) that are independently accessible for memory operations. The sectors of memory 620(0)-620(S) may be arranged in memory sub-sectors (not shown). Most command signals, the address signals and the write data signals are applied to the memory 600 as sets of sequential input/output ("I/O") signals transmitted through an I/O bus 634. Similarly, read data signals are output from the flash memory 600 through the I/O bus 634. The I/O bus is connected to an I/O control unit 640 that routes the signals between the I/O bus 634 and an internal data bus 642, an internal address bus 644, and an internal command bus 646. The flash memory 600 also includes a control logic unit 650 that receives a number of control signals either externally or through the command bus 646 to control the operation of the memory 600.
The address bus 644 applies row address signals to a row decoder 660 and column address signals to a global column decoder 664 and local column decoders (not shown). A portion of the column address signals are provided to the global column decoder 664 and another portion are provided to the local column decoders. The row decoder 660, column decoder 664 and local column decoders may be used to select sectors of memory, memory sub-sectors, or memory cells tor memory operations. The row decoder 660 may be sectorized, as shown in FIG. 1, and a portion of the row address (e.g., sector information LS) may be used to access a sector of memory. A further portion of the row address may be used to access a sub-sector and the remaining portion used to select individual rows (i.e., word lines) of memory. Global and local column addresses may be used to access individual memory cells in the selected row, with the local column decoder activated in the selected sector. The row decoder 660 includes a decoding block 635 according to an embodiment of the invention to decode pre-decoded address information for performing memory operations, for example, erase, program, and read, on memory corresponding to the pre-decoded address information. The column decoder 664 enables write data signals to be applied to bit lines for columns corresponding to the column address signals and allow read data signals to be coupled from bit lines for columns corresponding to the column address signals.
In response to the memory commands decoded by the control logic unit 650, the flash memory in the array 630 are erased, programmed, or read. The memory array 630 is programmed on a row-by-row or page-by-page basis. After the row address signals have been applied to the address bus 644, the I/O control unit 640 routes write data signals to a cache register 670. The write data signals are stored in the cache register 670 in successive sets each having a size corresponding to the width of the I/O bus 634. The cache register 670 sequentially stores the sets of write data signals for an entire row or page of flash memory ceils in the array 630. All of the stored write data signals are then used to program a row or page of memory cells in the array 630 selected by the row address coupled through the address bus 644. In a similar manner, during a read operation, data signals from a row or page of memory cells selected by the row address coupled through the address bus 644 are stored in a data register 680. Sets of data signals corresponding in size to the width of the I/O bus 634 are then sequentially transferred through the I/O control unit 640 from the data register 680 to the I/O bus 634.
From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.

Row address decoding block for non-volatile memories and methods for decoding pre-decoded address information


A close-range microwave imaging method includes: implementing Fourier transform in a pre-set rotation axis direction on an echo signal reflected from a target object and acquired by rotating an array antenna around the pre-set rotation axis to obtain a first echo signal, wherein the first echo signal is represented in polar coordinates; multiplying the first echo signal by a pre-set reference function to obtain a second echo signal; converting the second echo signal into rectangular coordinates by a pre-set algorithm to obtain a third echo signal; and implementing three-dimensional Fourier transform on the third echo signal to obtain three-dimensional image data of the target object. By means of the method, three-dimensional image data of a target object can be obtained fast, fast imaging of the target object can be realized, the data processing amount is small, the imaging precision is high and the method is easy to implement.

The close-range microwave imaging technology adopts an array antenna rotating around a specific rotation axis to form a curved scan surface and carries out scan imaging on objects by actively transmitting electromagnetic microwaves which can penetrate through the surfaces of the objects to detect metallic or non-metallic prohibited articles hidden in the objects. Because the close-range microwave imaging technology has the characteristics of small radiation dosage, non-ionizing radiation, and the like, it has been widely applied to safety inspection systems to perform human safety inspection tasks.
However, due to the curved scanning path, large data processing amount, and high requirements for imaging precision, the close-range microwave imaging technology is difficult to implement and has not been widely used yet.

Close-range microwave imaging method and system

CHINA COMMUNICATION TECHNOLOGY CO., LTD.

SHENZHEN VICTOOTH TERAHERTZ TECHNOLOGY CO., LTD


In a method of crystallizing a semiconductor film by introducing a metallic element that promotes crystallization, a gettering thereafter is effectively performed. A material film having a high tensile stress, typically a silicon nitride film, is formed in contact with the semiconductor film or heated after the formation thereof, thereby the metallic element in a crystalline semiconductor film is gettered to the material film having a high tensile stress. Thus, the metallic Interstitial silicon density element is removed or reduced to thereby form a gettered region.

1. Field of the Invention
The present invention relates to a method of manufacturing a crystalline semiconductor film formed on a substrate, and more particularly to a semiconductor device having a circuit constructed of a thin film transistor (hereinafter referred to as TFT) that uses the crystalline semiconductor film as an active layer and a method of manufacturing the same. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and to electronic equipment having such an electro-optical device mounted thereon as a part.
It is to be noted that a semiconductor device as stated herein throughout the present specification denotes a general device which functions by utilizing semiconductor characteristics, and that electro-optical devices, semiconductor circuits, and electronic equipments are all semiconductor devices.
2. Description of the Related Art
In a method of manufacturing a semiconductor device employing a semiconductor substrate such as a silicon wafer, impurities such as heavy metallic elements are introduced into the substrate through a process contamination whereby the semiconductor device deteriorates and results in a reduction in yield. Therefore, an ultra-clean-technology has been proposed as a technique to remove these impurities from the source and its utility as an impurity remover has been proven. On the other hand, in a semiconductor process technique, a gettering technique for eliminating and capturing the impurities from an active region of the device is relatively inexpensive, and hence has procured sound achievements in the improvement of yield.
Conventional gettering techniques are roughly and conveniently divided into three methods: (1) Extrinsic Gettering: EG method, (2) Intrinsic Gettering: IG method, and (3) Chemical Gettering: CG method.
The extrinsic gettering (EG) method is a gettering technique for supplying a gettering sink to the back surface of the wafer by way of the extrinsic means. Therefore, the EG method is also called a backside gettering. The gettering sink in the EG method is imparted to the back surface of the wafer by the extrinsic means (a mechanical damage typified by a sand blasting which uses the polishing powder of SiO2 or the like, a high concentration diffusion of phosphorus, CVD growth of an Si3N4 film or a polysilicon film, etc.).
A distorted region, a stress region, a defect region, or a chemically active region formed on the back surface of the wafer operates as the gettering sink, which is due to the above-mentioned extrinsic means, to capture the impurities that have diffused to a distance which corresponds to a thickness from the front surface of the wafer. Thus, the gettering sink must be provided in the back surface of the wafer before the initial oxidation process. One of the drawbacks of the EG method is that the process employing the EG method itself may introduce new impurities into the front surface of the wafer. However, the EG method, which inflicts mechanical damages to the back surface of the wafer, is widely and generally used in the manufacturing of devices for reasons of its simplicity and low cost.
The intrinsic gettering (IG) method is a gettering technique which utilizes a bulk defect that is induced in the silicon wafer by heat treatment. That is, the IG method is also called an internal gettering because it employs a sink in the wafer.
Further, the chemical gettering (CG) method is a gettering technique which forms metal chlorides susceptible to evaporation by performing heat treatment under an atmosphere containing chloric gas to thereby remove contaminants from the front surface of the wafer. Dissimilar from the above EG method and IG method, the CG method does not supply a gettering sink. Note that the frequency of use of the CG method, compared with that of the EG method or the IG method, is not much.
Many have acknowledged that characteristics of semiconductor devices are enhanced by employing the above-mentioned gettering techniques, and hence the EG method which is suitable as a mass production technique is being actively adopted and developments for a more superior gettering techniques and simpler and easier methods have been examined as well. Although the IG effect was discovered and there was an academic rise in the interest in the gettering techniques, and even a model of a gettering phenomenon was proposed, industrial applications preceded all these. The mechanism of a gettering in which physical constants and chemical constants such as an individual saturation, a diffusion coefficient, a level of solid solution, and a segregation coefficient of the impurities formed of heavy metal elements in the silicon crystal are taken into consideration has been made clear only recently.
A technique for structuring a thin film transistor (TFT) using a semiconductor thin film (having a thickness on the order of about several to several hundred nm) formed on a substrate having an insulating surface has been attracting much attention in recent years. Thin film transistors are widely applied to electronic devices such as an IC or an electro-optical device, and in particular, development of the TFT as a switching element of an image display device is proceeding rapidly.
Conventionally, an amorphous silicon film was used in the formation of the TFT. However, attempts have been made in manufacturing the TFT by utilizing a crystalline silicon film (also referred to as a polycrystal silicon film or a polysilicon film) in order to attain a higher performance.
A technique as one of the techniques for obtaining the crystalline silicon film on a glass substrate is disclosed in Japanese Patent Application Laid-open No. Hei 8-78329. The technique disclosed in this application is one in which a metallic element for promoting crystallization to the amorphous silicon film is selectively doped, and then heat treatment is carried out to thereby form the crystalline silicon film spreading from a doped region as the starting point.
This technique is a technique in which the metallic element (such as Ni) for promoting crystallization to the amorphous silicon film is selectively doped, and then heat treatment is conducted to thereby form the crystalline silicon film spreading from the doped region as the starting point. Further, due to an action of the metallic element in this technique, a lowering of the crystallization temperature of the amorphous silicon film by approximately between 50 to 100° C. of is possible compared with the case where the metallic element to promote crystallization is not used. Thus, the time necessary for performing crystallization in this technique can also be reduced to between one fifth and one tenth compared with the case where the metallic element to promote crystallization is not used.
Despite having excellent merits in lowering the temperature and shortening the time of the crystallization process, in this technique, the metallic element (such as Ni) used in promoting crystallization forms deep levels in the silicon film to trap carriers, and hence there is concern that this will exert a bad influence on the reliability and electric characteristic of the TFT. Therefore, similar to the method of manufacturing the semiconductor device employing the above-mentioned semiconductor substrate, after crystallizing the silicon film, it is preferable that either gettering is performed to swiftly remove the metallic element or the metallic element is reduced to a level where the electric characteristic of the TFT is not influenced.
As one of the gettering methods of the metallic element (Ni), a gettering process was conceived. That is, in this gettering process, after the metallic element is doped into the amorphous silicon film formed on an insulating surface, phosphorus (P) is doped into a portion of the crystalline silicon film which was formed by performing heat treatment. Then, Ni is gettered from a region serving as the active layer of the TFT by performing heat treatment.
However, because a dosage of 2×1015 (atoms/cm3) of phosphorus is doped into the amorphous silicon film in the above gettering process, there is an extremely high possibility of bringing about a new problem in that a chemical contamination is generated inside the clean room. In addition, a phosphorus contamination in the furnace, which occurs when a substrate doped with phosphorus is placed in a furnace, also becomes a problem. In practice, a considerably high concentration of phosphorus has been detected not only in the vicinity of the doping device but also in other areas in the clean room. Phosphorus is deemed as one of the major causes of making the controlling of a threshold value of the TFT difficult.

Method of manufacturing a semiconductor device that includes forming a material with a high tensile stress in contact with a semiconductor film to getter impurities from the semiconductor film

Semiconductor Energy Laboratory Co., Ltd.


A piston valve assembly for a shock absorber is disclosed. In a high-frequency mode, a damping force control is achieved through an open passage that is always opened. In a low-frequency mode, a guide assembly moves downward due to an increase in a pressure of a first pressure chamber by a fluid moved through an inlet hole of the first pressure chamber. At this time, the guide assembly blocks the open passage and the damping force control is achieved through only a rebound passage. Consequently, it is possible to solve a fluid bottle neck through a passage formation. A disk is installed on the inlet hole to prevent a continuous increase in the pressure of the first pressure chamber, thereby effectively preventing the reduction of the damping force.

1. Field of the Invention
The present invention relates to a piston valve assembly for a shock absorber, which is capable of improving a ride comfort by providing a damping force sensitive to both a pressure and a frequency, and more particularly, to a piston valve assembly for a shock absorber, in which an inlet hole is formed in an upper end of a first pressure chamber and a disk is installed on the inlet hole, such that the inlet hole is closed so as to prevent a pressure of the first pressure chamber from being continuously increased.
2. Description of the Related Art
Generally, suspension systems are installed in vehicles so as to improve a ride comfort by absorbing and damping a vibration or shock which is transferred from a road surface to an axle during driving. As one of such suspension systems, a shock absorber is used.
The shock absorber operates with a vibration of a vehicle according to a condition of a road surface. At this time, a damping force generated by the shock absorber is changed according to an operating speed of the shock absorber, that is, a high or low operating speed of the shock absorber.
A ride comfort and a driving stability of a vehicle may be controlled according to how to adjust a damping force characteristic generated by the shock absorber. Therefore, in designing the vehicle, it is very important to adjust the damping force characteristic of the shock absorber.
In this regard, an existing frequency-sensitive shock absorber or an existing pressure-sensitive shock absorber has a valve structure that realizes similar operational effects in terms of functions. However, parts for pressure sensitivity and parts for frequency sensitivity must be separately provided. Consequently, an increase in the number of parts and a rise in production cost are inevitable.
In particular, since such a problem causes an additional problem that the total length of the piston valve assembly is increased, there are many limitations to applying the conventional piston valve assembly to small- and medium-sized vehicles.

Piston valve assembly for shock absorber


A method for resin coating electrical windings enclosed within a housing of an electric motor and defining a central cylindrical cavity, the method including preparing a core having an elastic wall that encloses an inner chamber having an opening provided with a selective shut-off means, as well as a lower disc-like portion and an upper cylindrical portion that protrudes from a surface of the lower portion, coupling the core and an electric motor stator, in such a way that the upper portion occupies the cavity of the stator, and the lower portion is positioned within a housing of the motor below the electric windings, inflating the inner chamber through the opening, in such a way that the lower portion comes into contact with an inner surface of the housing and the upper portion comes into contact with the windings, which define a central cavity of the stator, pouring a resin so that it coats the windings when they are not in contact with the core; deflating through the opening the inner chamber, and separating the core from the stator, whose windings are coated with resin.

This method is typically conducted in an oven, after pouring liquid, two-component resin on the windings where it cures, forming a solid layer of coating. It is therefore critical to ensure that the resin only comes in contact with the parts of the windings that are to be actually embedded. Otherwise, the functionality of the motor will be compromised, unless long and complex resin removal methods are subsequently carried out on parts on which resin has been improperly poured and which are intended to house the rotor.
Therefore, according to a known technique, prior to pouring the resin, a core of a material having a thermal expansion coefficient higher than that of the stator material is inserted within the central cavity, for example a core made of Teflon or similar plastic material. The pre-heating that takes place in the oven therefore determines differential expansions that bring the core in contact with the parts of the stator's windings facing it, making sure the latter can then come into contact with the resin. The resin can then be poured and left to cure in the oven, forming a coating layer only where desired. Finally, as a result of the cooling and the consequent shrinkage of the core, the latter can be separated from the stator.
However, the time required for the cooling process to occur spontaneously is rather long and thus economically incompatible with an industrial working cycle. Consequently, it is necessary to conduct a forced cooling process with the risk that it will produce fissures, cracks, etc. in the resin coating.
Moreover, the separation operation requires applying a significant mechanical force, which can cause scratches and abrasions to form on the core's outer surface. Therefore, after a few working cycles, the core has an outer surface so damaged as to be useless and in need of replacement.

Process for over-moulding an outer stator


A sanitary bathroom organizer is an apparatus that stores and houses bathroom cleaning tools and bathroom cleaning supplies in an organized and hygienic manner. The apparatus includes a reservoir, at least one slot, a toilet paper roll mount. The reservoir contains disinfectant solution and houses bathroom cleaning tools. The at least one slot allows bathroom cleaning tools to enter the reservoir. The toilet paper roll mount connects a roll of toilet paper with the apparatus. The reservoir includes a base plate, a lateral wall, and a lid. The base plate is positioned adjacent the lateral wall. The lateral wall is perimetrically connected with the base plate, effectively containing disinfectant solution. The lid is removably coupled with the lid, allowing the interior environment of the reservoir to be accessible. The at least one slot traverses through the lid in order for bathroom cleaning supplies to be housed within the reservoir.

In present times, individuals are always looking for ways to compartmentalize toiletry tools/supplies in a sanitary way. In conventional systems, users would often rely on dedicated toilet tool holders, and/or separate storage compartments. These conventional systems oftentimes lead to improper sanitary storage of toiletry tools, and/or inconveniences of dragging along multiple toiletry tools. Additionally, conventional systems often lack the means providing a self-contained system for liquid disinfectant, which often leads to unintentional biohazard spillage of said contents, creating an unsanitary environment for bacterial growth on the site of the spillage.
The present invention aims to improve on these conventional systems by providing a practical and economical way to maintain a safe and healthy storage environment for toiletry tools that are arguably are subjected to some of the worst usages known to our society. The present invention was created to eliminate the biohazard mess often associated with biohazard spillages in conventional systems. The present invention is an improved sanitary storage system that not only prevents biohazard leakage, but also stores and dispenses toiletry media, and other types of loose articles.


A method is disclosed for removing water soluble salts from a metal substrate in a wet blast system in which a bicarbonate abrasive is blasted in a pressurized water stream against the surface of the metal substrate to prepare the surface for the application of a coating. The method includes the steps as indicated in FIG. 3 in which a high pressure wet blast pressurized water and sodium bicarbonate abrasive is first applied by a nozzle (14) against the surface of the metal substrate with the water soluble salts being removed or neutralized. Iron salts are present where the metal substrate is of a ferrous material such as iron or steel. Next, pressurized water without abrasive is applied by the nozzle (14) against the surface of the metal substrate for washing the surface clean and removing the neutralized water soluble salts. The water for the wet blast system is of a very high purity characterized by a conductivity of between 0.5 and ten (10) micromohs/cm. To confirm the removal of the salts to an amount less than one (1) ppm, a ferricyanide testing is performed on the surface of the metal substrate. An apparatus for carrying out the method is shown in FIG. 2.

Various coatings are applied to metal substrates. It is highly desirable that the metal substrate be effectively cleaned of contaminants prior to the application of the coating so that the useful coating life may be prolonged. Contaminants include liquid halogens, sulfur compounds, and occasionally nitrogen compounds. Such surface contaminants include water soluble salts, such as chlorides, sulfates and nitrates. On steel substrates such salts are iron salts (ferrous and ferric salts.)
The presence of water soluble salts on substrates has long been recognized as a major factor in reducing coating life. The detrimental effect of these contaminants on coating performance has been discussed in coatings related literature for almost 30 years. Water soluble salts on a substrate initiate coating disbondment (and substrate corrosion) through an osmotic blistering process which is described below.
In the event of a media blasted steel substrate, ferrous chloride is formed whenever steel or iron soluble chloride in moisture are in contact. This reaction, in itself, is a strong corrodant of steel surfaces. Upon exposure to air, ferrous chloride oxidizes to ferric chloride, a hygroscopic salt with a natural affinity for moisture in the air. Trace amounts of either ferric or ferrous chloride remaining on the substrate accumulate moisture from the air resulting in the formation of a concentrated iron chloride solution on the surface of the steel substrate. Iron ions, chloride ions and water comprise an electrolytic solution that drives an electrochemical corrosion reaction. Coatings applied over such a substrate fail in a short period of time due to the concentrated iron chloride solution on the substrate drawing water through the coating by osmosis and creating a blistering or disbondment of the coating. Rates of coating failure due to osmotic blistering are dependent on the thickness and porosity of the coating.
Contamination of substrates from soluble salts has been identified as the source of coating failure and has been thoroughly documented. Practical cost effective solutions to the problem have eluded routineers in the coating science field. Complicating the search for cost effective solutions is the lack of standards defining acceptable levels of soluble salt contaminations or concentrations on substrates. The level of cleanliness required varies significantly with the service environment and the characteristics of the coating selected. However, independent of these variables, "the cleaner the substrate, the greater the resistance to coating disbondment".
Until recently, blast cleaning specifications have not addressed removal of non-visible surface contaminants. Conventional grit blasting techniques were not designed to remove ionic contamination. Dry abrasive blasting can not efficiently remove localized sources of corrosion initiation sites (commonly referred to as corrosion cells) because an operator may not be able to see such contaminants and direct a dry grit blast against such corrosion initiation sites. Efforts to develop methods for removal of these non-visible contaminants from substrates have been generally unsuccessful although several techniques have been tried with partial success, such as, for example, (1) dry blasting followed by water rinsing (several cycles), (2) hard grit wet abrasive blasting, (3) high pressure washing, and (4) acid washing followed by water rinsing.

Method for removal of surface contaminants from metal substrates