A computer system having a multi-module memory system. Accesses to the memory modules for reading or writing are undertaken in parallel. The memory system is addressed by input addresses. The memory system includes a map unit for transforming the input addresses to output addresses in a pseudo-random manner so as to tend to distribute memory accesses uniformly among the memory modules whereby contention resulting from multiple concurrent attempts to access the same memory module is reduced. The map unit performs addresses transforms that are repeatable so that the same input address maps to the same output address and that are one-to-one such that each input address maps to one and only one output address.

The present invention relates to computers, and more particularly, to high-speed, parallel-processing computers employing horizontal architectures and multi-module memory systems.
Horizontal processors have been proposed for a number of years. See for example, "SOME SCHEDULING TECHNIQUES AND AN EASILY SCHEDULABLE HORIZONTAL ARCHITECTURE FOR HIGH PERFORMANCE SCIENTIFIC COMPUTING" by B. R. Rau and C. D. Glaeser, IEEE Proceedings of the 14th Annual Microprogramming Workshop, Oct. 1981, pp 183-198 Advanced Processor Technology Group ESL, Inc., San Jose, Calif., and "EFFICIENT CODE GENERATION FOR HORIZONTAL ARCHITECTURES:COMPILER TECHNIQUES AND ARCHITECTURAL SUPPORT" BY B. Ramakrishna Rau, Christopher D. Glaeser and Raymond L. Picard, IEEE 9th Annual Symposium on Computer Architecture 1982, pp. 131-139.
Horizontal architectures have been developed to perform high speed scientific computations at a relatively modest cost. As a consequence of their simplicity, horizontal architectures are inexpensive when considering the potential performance obtainable. This potential performance is realized when the multiple resources of a horizontal processor are scheduled effectively. An example of one horizontal computer is described in the above cross-referenced application and the applications referenced therein.
In computer systems, the processing units execute programs which require accesses to the memory system. Some of the accesses to the memory system are read (fetch) operations in which information from an address location in the memory system is accessed and returned to the processing unit for use in further execution of the program. In statically scheduled computer systems, the return of the accessed information in response to a request from the processing unit is in a predetermined order and at a predetermined time. Generally, information is returned to the processing unit from the memory system in the same order that the processing unit makes a request for the information.
It is often necessary or desirable in computer systems for one or more ports (from one or more processing units, I/O devices or other system units) to simultaneously initiate accesses (by generating memory addresses) to a shared memory system for fetching and storing information. The amount of time required to return requested information from a memory system to the processing unit after a request for the information by the processing unit is the actual latency time of the memory. The memory latency time affects the overall efficiency in which the processing unit can complete the execution of programs. In general, it is desirable to have the actual memory latency as short as possible so that the processing unit is not required to wait for the memory system in order to continue processing.
In order to increase system speed, memory systems have been constructed using interleaved memory modules. The use of multiple memory modules increases the bandwidth of the memory system by directing successive memory requests to different ones of the memory modules. Since a request directed to one module can be processing at the same time that a request is processing at another module, the rate at which the memory system can return requested information is greater than the rate of any individual module. For this reason, the memory system has a higher bandwidth as a result of using multiple memory modules operating in parallel.
As speed requirements of computers have increased, memory systems employing greater numbers of parallel memory modules have been developed. However, merely increasing the number of memory modules does not guarantee higher memory speed or a higher number of memory accesses during a period of time. The number and speed of total memory accesses is limited by the conflicts that occur in accessing the individual memory modules.
Memory modules are usually constructed so that requests to access a memory module, in response to a sequence of input addresses, can only be accommodated one address at a time in sequential order. Multiple requests to a single memory module must have a conflict resolution mechanism that orders the requests. Theoretically, the number of memory modules can be increased in order to reduce such conflicts but, in conventional systems, the total achievable rate of accesses to a memory system does not increase in proportion to an increase in the number of memory modules forming the system.
In a conventional multi-module memory system, part of the input address, Ai, to the memory system defines the particular one of the memory modules in which the physical address is actually located. Let M be the number of memory modules, where M=2.sup.m and m is an integer. Typically, m contiguous bits of a given input address Ai specify which one of the M memory modules includes the physical address Ai. In one example where m equals 6 and M equals 64, sixty-four memory modules exist and six of the input address bits, for example Ai(7, 2), uniquely define one of the 64 memory modules.
When an input sequence, Ai($), of input addresses Ai, where $ is the index from 0 to $max of Ai, is presented to a memory system, it is desirable that the physical addresses in the memory modules be uniformly distributed and not clustered. If the distribution in response to that input sequence tends to be random, then generally the distribution will be uniform among the memory modules. Such a distribution is called pseudo random. When the distribution tends to be random, the probability that a memory module will be busy when an input address makes a request to that module is lower than when not random. If the memory module is not busy when a request is made, then of course the memory system operates more quickly since time is not lost in waiting for the memory module to become not busy. Therefore, in general, memory systems suffer a loss in speed from memory access conflicts when a higher frequency of accesses results for some of the memory modules relative to the frequency of accesses for other of the memory modules.
A pseudo random distribution of accesses among memory modules is important for both short address sequences and for long address sequences. For example with 64 memory modules and for a short sequence with S from 0 to 63, representing 64 different input addresses Ai in the input sequence Ai(S), it is desirable that the physical addresses (that is, the physical module actually having the address location) be distributed one each in each of 64 different memory modules. Similarly, for a long sequence (With $ much larger than 64), it is desirable that each of the 64 memory modules tends to have an equal number of physical addresses in response to the input addresses irrespective of the nature of the input sequence of addresses.
While it is desirable to access all memory modules uniformly with equal frequency, certain types of programs generate input address sequences that address memory modules in a manner that tends to cause non-uniform accessing among the memory modules. Such non-uniform memory accessing frequently arises in performing matrix computations. For example, a two-dimensional matrix might have its matrix values stored with column values in a single memory module. With such storage, row matrix values and forward-diagonal and reverse-diagonal matrix values can be accessed from different memory modules. However, When the column matrix values are accessed serially out of the single memory module the accessing rate is materially reduced because of the module access conflicts which arise.
In order for an interleaved memory system to be effective and have accesses uniformly distributed among the memory modules, the organization of addresses in the memory modules must be appropriately determined.
The typical organization of an interleaved memory system uses m contiguous bits of the input address to define the memory module. Such an organization has every M-th word assigned to a given memory module, where M is the number of memory modules. Usually, M is a power of 2. Less frequently, M is some other number such as a prime. Such a prime number memory system is described, for example, in U.S. Pat. No. 4,051,551 to Lawrie et al. With such organizations, however, input address sequences Ai(S) are found, in actual practice, that map non-uniformly and more frequently to the same module and therefore, the full benefits expected from interleaving are not achieved.
Another memory system organization uses m non-contiguous bits from the input address (where M=2.sup.m) and assigns all words with the same addresses in those m bits to the same memory module. This non-contiguous address bit organization is not susceptible to as long-term a concentration of references to one module as the previous m contiguous bit approach. However, when m is much less than the number of address bits (which is almost always the case), there is still a susceptibility to a short-term concentration of references to a module.
In one example of a memory system where m=6 and the number of bits in the word address is 29, the number of contiguous address bits which do not enter into the determination of the selected memory module cannot be guaranteed to be less than 4. A contiguous set of not more than 4 bits is achieved if the 6 bits that are used are evenly distributed throughout the 29 address bits. Even with such a distribution, however, there can be at least 16 consecutive references to the same memory module when the appropriate stride exists in the input address sequence. This short-term (up to 16 in the example described) non-uniform concentration of references to the same memory module is as detrimental to performance (assuming realistic queueing buffer capacities) as is a long-term non-uniform concentration.
Methods for avoiding non-uniform accesses among memory modules have been proposed which use address transforms. In connection with address transforms, the terms "real address" and "input address" are used to refer to the address presented to the memory system prior to an address transform and the terms "physical address" and "output address" are used to refer to the address after transform.
In connection with an address transform, each input address, Ai, is transformed by a transform, H, to form an output address, Ao. In this specification, the number of bits, I, for an input address is designated in parentheses, Ai(I-1, I-2, . . . , 0). For example, with 29 addresses bits (I=29) the designation is Ai(28, . . . , 0), and similarly, the number of bits in a transform output address is indicated for the same 29 bit example as Ao(28, . . . , 0).
In general, the expression for the transform of a single input address Ai to a single output address Ao is given as follows: EQU Ai[H]=Ao Eq.(A)
A number of bits, usually m consecutive bits, of the output address Ao defines the particular one of the memory modules in which the output address is physically located. Usually 2.sup.m memory modules are defined. In one example where 64 memory modules exist, the output address bits Ao(7, . . . , 2) uniquely defines one of the 64 memory modules. The transform of the input address Ai to form the output address Ao frequently uses g of the I input address bits in determining the output address module bits Ao(7, . . . , 2). The number g of input address bits is usually greater than m of output address bits. In one example, the memory modules are addressed on a word basis and the low-order b address bits Ai(1,0) and Ao(1,0) define the byte address within a word.
A sequence of input addresses, each input address of the form Ai, is designated as Ai{S} and, with a transform, H, a sequence of output addresses Ao{S} is formed where each output address of the form Ao all given as follows: EQU [Ai{$ }][H]=Ao{$ } Eq.(B)
where,
Ai=input address PA1 Ai{$}=sequence of $max input addresses indexed from 0 to ($max-1) PA1 H=address transform PA1 Ao=output address of a memory module PA1 Ao{$}=sequence of output addresses indexed from 0 to ($max-1) PA1 An equal number of input addresses are mapped into each memory module. PA1 The mapping is onto, that is, some input address will map into any given output address. PA1 The concentration in any particular memory module of output addresses in response to any sequence of input addresses is not greater than would be the oase with a truly random output address sequence irrespective of the nature of the input address sequence. The distribution of output addresses in memory modules tends to be uniform among the memory modules for both short and long sequences of input addresses. PA1 The mapping is effective over the entire range of interleaving for which the memory system is designed including 2-way, 4-way, 8-way, 16-way or other interleaving.
In Eq.(B) the sequence Ai{S} of input addresses Ai presented to a memory system is indexed from 0 to (Smax-1) and the sequence Ao{$} of output addresses Ao similarly is indexed from 0 to (Smax-1). For a 29-bit example, the designation is Ai(28, . . . ,0){$} and Ao(28, . . . ,0){S}.
When sequences of input addresses Ai(S) are transformed to sequences of output address Ao($), it is desirable that the distribution of the output addresses into physical memory modules tends to be random, that is, pseudo-random. For example, for the sequence $ indexed from 0 to 63, representing 64 different input addresses in the input sequence Ai($), it is desirable that the output addresses be distributed one each in each of the 64 memory modules. Similarly, as Smax grows much larger than 64, it is desirable that each of the 64 memory modules tends to have an equal number of output addresses Ao resulting from the input addresses Ai irrespective of the nature of the input sequence Ai(S) of input addresses.
In general, the function of an address transform is to assign the location of physical addresses in storage to memory modules so that no non-artificial sequence of input addresses exhibits statistically more frequent long-term or short-term accesses to individual memory modules.
Also for an effective transform, the rate of accesses to memory modules will increase in proportion to an increase in the number of memory modules with substantial independence of any non-artificial memory referencing pattern established by the input sequence of memory input addresses.
One example of an address transform is described in U.S. Pat. No. 4,484,262 to Sullivan et al. In that patent, a truly random address transform was described which did not disclose a mechanism that insured the repeatability or one-to-one mapping properties that are required for practical systems.
Transform repeatability insures that the same input (real) address always maps to the same output (physical) address. This property is useful in a computer system so that different requests to the memory system are assured of accessing the same memory location. In a practical computer system, it is desirable that the transform mapping not be truly random, but rather be deterministic and therefore can be described as pseudo-random.
Transform one-to-one mapping insures that no more than one input (real) address maps to the same output (physical) address. This property is useful in a computer system to insure that information which is needed in the system is uniquely defined and not confused with or destroyed by other information. However, there may be output (physical) addresses with no corresponding input (real) addresses in some computer systems.
In accordance with the above background, it is an objective of the present invention to provide an improved computer system which provides address transforms that avoid consecutive references to the same memory module for many different types of input address sequences so that a uniform distribution of accesses occurs among memory modules.

Apparatus for transforming addresses to provide pseudo-random access to memory modules


A beam irradiation apparatus includes: an actuator which scans a target region with a laser beam; a photodetector which receives a servo beam and outputs a signal according to a beam reception position; an optical unit which makes the servo beam displaced on the photodetector in association with driving of the actuator; and a position signal generation circuit that generates a signal according to the reception position of the servo beam based on an output signal from the photodetector. The position signal generation circuit has a signal removal circuit that removes a disturbance signal generated when the laser beam is incident on the photodetector, from an output signal of the photodetector.

1. Field of the Invention
The present invention relates to a beam irradiation apparatus for irradiating a target region with a laser beam and, particularly, to a beam irradiation apparatus mounted on a so-called laser radar, for detecting the presence or absence of an obstacle in a target region and a distance to an obstacle based on reflection light of a laser beam emitted to a target region.
2. Description of the Related Art
In recent years, a laser radar is mounted on a family car or the like in order to enhance safety during driving. The laser radar emits a laser beam to the front in the driving direction and detects the presence or absence of an obstacle in a target region and distance to an obstacle. Generally, the laser radar scans a target region with a laser beam and, based on the presence or absence of reflection light in each of scanned positions, detects the presence or absence of an obstacle in each of the scanned positions. Further, based on required time from a laser beam emission timing in each scan position to a reflection light reception timing, the distance to the obstacle from the laser radar in the scan position is detected.
To enhance detection precision of a laser radar, a target region has to be properly scanned with a laser beam, and each scan position of a laser beam has to be properly detected. As a laser beam scanning mechanism, a scan mechanism using a polygon mirror and a lens-driving-type scan mechanism for two-dimensionally driving a lens for scan are known.
On the other hand, as a method different from the scan mechanisms, a mirror-turning-type scan mechanism can be proposed. In the scan mechanism, a mirror is supported so as to be driven about two axes. The mirror is turned about each of the drive shafts as an axis by an electromagnetic drive force between a coil and a magnet. A laser beam is obliquely incident on the mirror. By two-dimensionally driving the mirror about each of the drive shafts as an axis, a target region is scanned in the horizontal and vertical directions with reflection light of the laser beam by the mirror.
In the scan mechanisms, scan positions of the laser beam can be detected by, for example, disposing a light source which emits a servo beam in addition to a light source which emits the laser beam and receiving the servo beam by a photodetector such as a PSD (Position Sensing Device) or the like. In this case, a configuration of making the servo beam displaced on the photodetector so as to trace a scan of the laser beam is disposed.
For example, the scan mechanism of the mirror rotating type can employ a configuration of disposing a servo mirror which rotates with a mirror to reflect the laser beam to the target region and making a servo beam incident on the servo mirror. Alternatively, a configuration of disposing a transparent member having a flat plate shape in place of the servo mirror, and making a servo beam incident on the transparent member can be used. In the case where the servo mirror is used, a servo beam reflected by the servo mirror is received by a PSD or the like. In the case where the transparent member is used, a servo beam passed through the transparent member is received by a PSD or the like. When the mirror rotates at the time of a scan with a laser beam, the servo mirror or the transparent member rotates in association with the rotation of the mirror, and the servo beam is displaced on the PSD. Based on an output signal from the PSD, the scan position of the laser beam on the target region can be obtained.
In the beam irradiation apparatus having the above-described configuration, a laser beam is emitted as a pulse beam to the target region at a predetermined timing. In this case, the power of the laser beam emitted toward the target region is remarkably higher than that of a servo beam incident on the PSD (by about 100,000 times). Consequently, when the laser beam is incident on the PSD as ambient light, an output signal from the PSD largely changes, and a problem such that an error is included in the position detection signal occurs. Normally, the wavelength of a servo beam is set so as to be different from that of a laser beam. As described above, the power of the laser beam is remarkably higher than that of the servo beam. Due to this, it is extremely difficult to completely block the PSD from the laser beam with a filter or the like. Even if a filter or the like is used, the laser beam exerts some influence on a position detection signal as ambient light, and a problem such that the precision of the position detection signal deteriorates occurs.


Retroreflective appliques comprising a monolayer of retroreflective elements partially embedded in and protruding from the front surface of a binder layer and an optional layer of adhesive on the rear surface of the binder layer for securing the applique to a garment, wherein the binder layer comprises an electron-beam cured polymer selected from the group consisting of chlorosulfonated polyethylenes, ethylene copolymers comprising at least about 70 weight percent of polyethylene, and EPDM polymers.

In order to improve safety of pedestrians, joggers, workers on roadways, etc., retroreflective markings have been attached to clothing. In one common embodiment, retroreflective appliques comprising a monolayer of retroreflective elements, e.g., transparent microspheres with hemispheric reflectors, partially embedded in a layer of binder material, with adhesive backings are bonded to articles of clothing.
Typically, the binder materials in such appliques comprise thermally or chemically cured compositions, e.g., phenolic cured resins, isocyanate cured polymers with active hydrogens such as two part urethanes, and aminoplast- or amine-cured hydroxy functional polymers. A problem with such appliques is that their retroreflective performance tends to diminish unacceptably when the garment to which they are bonded is washed. After a few washings, the retroreflective brightness of the applique may be reduced to a small fraction, e.g., 5 percent or less, of its original brightness. This decrease is due to loss of retroreflective elements from the surface of the applique and/or degradation of the retroreflective elements, e.g., corrosion of aluminum hemispheric reflectors, during washing.
The problem is particularly troublesome when the clothing is subjected to industrial laundering, where the conditions of laundering are often more severe than conventional home laundering. For instance, in an industrial laundry, the laundering conditions may include wash temperatures of 40.degree. to 90.degree. C. (105.degree. to 190.degree. F.) and pH of 10 to 12.5, whereas in contrast, typical conditions for home laundering may include temperatures of 4.degree. to 60.degree. C. (40.degree. to 140.degree. F.) and pH of less than 11. Also, home laundering equipment typically subjects the articles being cleaned to less rigorous handling and stress than does industrial laundry equipment.

Launderable retroreflective applique with binder layer comprising electron-beam cured polymer

Minnesota Mining and Manufacturing Company


Methods and systems for adjusting reference signal reporting based on path loss and fading and cell edge conditions experienced by wireless devices in 5G EN-DC networks. As the path loss increases, a period between reference signal reports (or a frequency of reference signal reports) can be increased. This ensures continued quality of service for the wireless devices. Reference signals can include SRS, DMRS, PTRS, etc.

As wireless networks evolve and grow, there are ongoing challenges in communicating data across different types of networks. For example, a wireless network may include one or more access nodes, such as base stations, for providing wireless voice and data service to wireless devices in various coverage areas of the one or more access nodes. As wireless technology continues to improve, different iterations of radio access technologies (RATs) may be deployed within a single wireless network. Such heterogeneous wireless networks can include newer 5G and millimeter Wave (mmWave) networks, as well as older legacy networks. In some cases, deployment of 5G new radio (NR) access nodes alongside or co-located with 4G long-term evolution (LTE) access nodes utilizes dual connectivity technology (e.g. EN-DC), wherein control information is transmitted using the 4G RAT and data is transmitted using the 5G RAT. There are various potential deployments of EN-DC, such as one-to-one (where a 4G eNodeB is collocated with a 5G gNodeB at the same cell site or radio access network), or distributed or one-to-many (where a 4G eNodeB at a first radio access network is coupled via X2 links to many different 5G gNodeBs, each within their own radio access network or cell site). Each radio access network (RAN) or cell site can further include a cell site router, which provides connectivity to other network elements, such as an intermediate or core network. The connection between the cell site router and other network elements closer to the core network may be referred to as a mobile backhaul.
Further, as wireless device technology improves, different wireless devices are configured to use different types of applications (such as voice over IP, streaming, gaming, etc.), and each different application may optimally function with a different channel size or bandwidth. While channel bandwidths in 4G are static, 5G can deploy various bandwidths, most of which are higher than 4G bandwidths. Further, wireless networks may be configured to utilize multiple-input-multiple-output (MIMO), in which multiple data streams can be directed towards one or more eligible wireless devices via various combinations of antennae and transceivers based on the orthogonality of transmission, thereby maximizing resources. MIMO can include single-user MIMO (SU-MIMO), multi-user MIMO (MU-MIMO), and massive MIMO (mMIMO), which extends MU-MIMO to antenna arrays coupled to base stations, the antenna arrays comprising large numbers of controllable antenna elements that enable directing several MU-MIMO streams to various groups or "pairings" of wireless devices. Beamforming is another transmission mode that is used to provide better coverage to wireless devices in specific locations within a coverage area of a cell or access node. A beamforming downlink transmission mode uses multiple antennae to direct or "steer" signals from the antennae towards a particular wireless device located at, for instance, a cell edge. Both beamforming and MU-MIMO require the use of multiple antennae, with any performance gains being proportional to a number of antennae deployed by a specific cell or access node. Further, both beamforming and MIMO have been identified as some of the promising air interface technologies to address the capacity requirement required demanded by 5G networks.
Beamforming, MIMO, and other transmissions modes are enabled by using reference signals. For example, wireless devices can transmit uplink reference signals that are analyzed by an access node to determine how to best serve these wireless devices via different transmission modes. While using uplink signals enabled better communication between wireless devices and access nodes, excessive uplink signaling can cause noise or interference in uplink channels and affect quality of service.
Overview
Exemplary embodiments described herein include methods, systems, and processing nodes for adjusting reference signal reporting based on uplink channel conditions such as path loss or fading and cell edge conditions. An exemplary method for adjusting reference signal reporting in dual-connectivity wireless networks based on channel conditions includes obtaining channel conditions for a communication channel between a wireless device and an access node and, based on the channel conditions, adjusting a reference signal reporting parameter for the wireless device.
Thus, an exemplary method for adjusting reference signal reporting can include determining that a path loss of a wireless device exceeds a threshold and increasing a reference signal reporting frequency for the wireless device.
Further, an exemplary method for adjusting reference signal reporting can include determining that a fading parameter of a wireless device exceeds a threshold and increasing a reference signal reporting frequency for the wireless device.
These operations can be performing for one or more wireless devices individually, or for all wireless devices within a sector. An exemplary method for adjusting reference signal reporting can include monitoring channel conditions of a communication channel between a wireless device and an access node, and responsive to changes in the channel conditions, adjusting one or more reference signal reporting parameters for the wireless device.
Further, an exemplary method for adjusting reference signal reporting can include monitoring channel conditions of a communication channel between one or more wireless devices within a sector and an access node, and responsive to changes in the channel conditions, adjusting one or more reference signal reporting parameters for all the wireless devices within the sector.
The exemplary embodiments described herein may be performed by a processing node within a system, such as a telecommunication system. For example, an exemplary system for adjusting reference signal reporting in dual-connectivity networks based on channel conditions can include an access node that is capable of simultaneously receiving uplink data via at least two different radio access technologies, and processing node communicatively coupled to the access node. The processing node can be configured to perform operations including any of the operations described herein in any combination.
For example, an exemplary processing node can be configured to perform operations including monitoring channel conditions for a communication channel between one or more wireless devices and an access node, and responsive to changes in the channel conditions, adjusting one or more reference signal reporting parameters for the one or more wireless devices. The channel conditions can include one or more of a path loss or a fading parameter, and the reference signal parameters can include one or more of a reporting frequency or a timing offset. The operations further include determining an increase in the path loss or the fading parameter and increasing the reporting frequency or adjusting the timing offset.

Adjusting reference signal reporting based on uplink channel conditions


A method of manufacturing a dartboard by grass stem includes the steps of rolling grass stems and removing insect eggs, binding the grass stems into a bundle and then cutting the bundle into grass stem cakes, compressing the grass stem cakes into a target body of the dartboard, fixing a backplane of the target body coated with an adhesive, an insect repellent, and a preservative, and flattening a target surface before performing a printing process and a baking process, so as to prevent the dartboard from being damaged by insects and mildews.

Shooting darts is a general leisure activity as well as a professional competition, and the equipments for the sport of darts are nothing more than darts and a dartboard. The darts may be divided into darts with a steel dart head and darts with a plastic dart head according to the nature of the leisure activity and the professional competition, and the dartboard may be divided into a dartboard made of wood, linen, paper and special fiber.
In general, the dartboards used in an official competition are linen dartboards, and most of them are made of sisals with the properties of high durability and strength. However, the sisals are not accessible easily and mainly imported from other countries, and thus incurring a higher cost.
Although some of the dartboards are made of grass stems, the grass stems contain insect eggs. If the grass stems are not processed properly before using them to manufacture the dartboards, the insect eggs hidden in the dartboards will be hatched and the internal structure of the dartboard will be damaged by insects or mildews.

Method of manufacturing dartboard by grass stem


An electrical connector (100) for mating with a corresponding plug (200) includes a dielectric housing (1) defining two contact areas (15) along an up to down direction. An outer shield (3) encloses the dielectric housing. A plurality of contacts (2) are retained in the contact areas. An inner shield (4) are mounted between two contact areas and comprises a pair of spring arms (42) extending into the contact area to lock with the plug and a resilient strip (43) extending into the contact areas to abutting against an outer side of the plug.

1. Field of the Invention
The present invention relates to electrical connectors, and more particularly to electrical connectors with improved grounding structure.
2. Description of Related Art
Electrical connectors are widely used in various peripherals for electrically connecting with each other. With a miniature development of the electrical device, the electrical connector is tended to be designed with a miniature structure for reducing occupied area. Usually, electrical connectors are stacked with each other for obtaining the purpose. Such electrical connector usually includes an insulative housing, a plurality of contacts retained in the insulative housing and an outer shield enclosing the insulative housing. The insulative housing comprises two or more mating sections stacked with each other along an up to down direction for mating with a corresponding plug. A partition plate extends forwardly from the insulative housing and is located between two mating sections. The electrical connector also includes an inner shield enclosing the partition plate. The inner shield includes two pairs of spring arms extending into two mating sections respectively.
The outer shield is stamped from a unitary one-piece metal sheet to have a generally rectangular configuration with four peripheral walls including a pair of top wall and bottom wall, and a pair of side walls. Each of the top wall, bottom wall and side walls has a pair of spring arms extending into the mating sections. Usually, the corresponding plug includes an insulative housing with a number of mating contacts retained thereon, and a metal shield enclosing the insulative housing. The metal shield defines a plurality of openings locking with the spring arms of the inner shield, the upper and lower walls of the outer shield. In addition, the spring arms of the side walls abut against the metal shield of the plug for grounding.
However, the outer shield is made of ordinary, low cost material, such as iron, for reducing the cost of the electrical connector usually. But the ordinary, low cost material has badly mechanical property that could not ensure desirably flexibility of the spring arms, and would adversely affect the contact between the spring arms and the plug after longtime mating cycles. The grounding performance tends to be worse at the same time. If the outer shield is made of material with excellent mechanical property, the cost of the electrical connector will be increased.
Hence, an electrical connector with improved grounding performance and low cost is needed to solve the problem above.

Electrical connector with improved grounding structure


Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. A liner-forming material is deposited overlying the barrier layer to form a liner. A conductive metal is deposited overlying the liner.

Integrated circuits (ICs) typically include a plurality of semiconductor devices and interconnect wiring. Networks of metal interconnect wiring are often used to connect the semiconductor devices from the semiconductor portion of the substrate. Multiple levels of metal interconnect wiring form a plurality of metallization layers above the semiconductor portion of the substrate and are connected together to form a back-end-of-the-line ("BEOL") interconnect structure. Within such a structure, metal lines run parallel to the substrate in the metallization layers and conductive vias run perpendicular to the substrate between the metallization layers to interconnect the metal lines.
High performance of contemporary ICs may be achieved using a highly conductive metal, such as copper (Cu), as the interconnect metal of the BEOL interconnect structure, which also employs a low dielectric constant material or dielectric material as an interlevel dielectric (ILD) layer or layers to insulate the interconnect wires from each other. To help prevent migration of the interconnect metal into the ILD layer, a barrier-forming material, such as tantalum nitride (TaN), is deposited onto the dielectric material to form a barrier layer. A metal liner material, such as tantalum (Ta) or the like, is deposited overlying the barrier layer to form a metal liner layer to help hold the highly conductive interconnect metal to the barrier layer and the underlying dielectric material. Then, a conductive metal seed layer, such as a layer of copper (Cu) or copper alloy, is formed on the metal liner layer and the highly conductive metal (e.g., Cu) is deposited over the conductive metal seed layer to form a metal interconnect wire. Unfortunately, many conventional approaches for forming the barrier layers for such interconnect structures can (1) damage the underlying dielectric material of the ILD layer, (2) produce non-conformal barrier layers that are too thin or discontinuous particularly along vertical walls or too thick particularly around corners of the ILD layer, and/or (3) form relatively low density barrier layers that have undesirably high resistivity and/or are susceptible to damage by impurities, such as oxygen (O), carbon (C), or the like, that are produced during subsequent deposition of the liner.
Accordingly, it is desirable to provide methods for fabricating integrated circuits including forming barrier layers that are more robust such as for back-end-of-the-line interconnect structures. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.

Methods for fabricating integrated circuits including barrier layers for interconnect structures


In one of the many embodiments of the present inventions, a system is provided which includes at least one server to execute at least one session where the at least one session includes data associated with a user. The system also includes at least one stateless client coupled to the at least one server where the at least one stateless client obtains the at least one session from the at least one server.

1. Field of the Invention
This invention relates to the field of computer systems.
Portions of the disclosure of this patent document contain material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office file or records, but otherwise reserves all copyright rights whatsoever. Sun, Sun Microsystems, the Sun logo, Java, JavaBeans, HotJava and all Java-based trademarks and logos are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries.
2. Background Art
There is a desire to provide access to computer networks via simple computing devices. Currently the most effective way to access computer networks such as the internet is via personal computer (PC). Various manufacturers have attempted to provide a simplified computing device for network access, such as so called "network computers". Network computers and other such devices are referred to here as "information appliances". Another type of information appliance is the so called "web phone". The web phone is an attempt to provide a telephone for both voice and data transactions. In most incarnations, the webphone includes some form of voice transmitter and receiver, a numeric keypad, and an extended or dual purpose keypad for data entry, and a multi-line display.
Current information appliances implemented in the form of a so called web phone typically fit into one of two categories. One category is a low cost design with a very limited and fixed set of capabilities. Another category is a high cost design requiring large amounts of RAM, ROM, and CPU speed to achieve acceptable performance.
Problems with the low cost designs include a limited feature set and the inability to be dynamically updated or to download executable content from resources such as the internet. Problems with high cost design include the high cost (approximating that of a desktop PC) while lacking the performance of PCs. Also, when the devices have persistent data, that data must be explicitly synchronized if more than one device is used in a location, such as a home.
Another problem with prior art information appliances is the lack of effective scalability. Per unit cost is the same regardless of the number of units in the system.

Low cost, stateless, full-featured information appliance


An improved spent catalyst regenerator which contains sub-troughs branching off from the main trough, distribution troughs which extend outward from the sides of the main trough and the sub-troughs, and downflow tubes extending downward from the bottom of the main trough and sub-troughs.

The theory behind spent catalyst distributors has been known for many years. Generally, once catalyst has been used in a cracking process, it is referred to as being "spent" catalyst. The spent catalyst is covered with coke, which covers the active sites on the catalyst thereby substantially reducing the activity of the catalyst. It is possible, however, to remove the coke from the catalyst through the use of a regenerator. The spent catalyst is fed into the regenerator and the deposited coke is burned away, leaving only the catalyst. The hot re-activated catalyst is then removed from the regenerator to be reused in the cracking process. It is a known problem in the art that if the spent catalyst is not distributed into the regenerator in a uniform manner, the catalyst is not regenerated as cleanly, after-burning and the associated temperature increase in the dilute phase of the regenerator is present, and NOx is generated in undesirable amounts. Several past patents have attempted to resolve the deficiencies of the prior art distribution problems with varying degrees of success.
For example, U.S. Pat. No. 4,150,090 to Murphy et al. teaches an apparatus that is used in the regeneration of cracking catalyst. Arms which carry spent catalyst are connected to a center shaft and extend outward from the shaft but do not touch the outer walls of the regenerator. This patent thus discloses a shape that is very similar to the spokes on a wheel, when viewed from above. However, this design causes the spent catalyst to be distributed in the regenerator in a very uneven manner.
U.S. Pat. No. 5,635,140 to Miller et al. discloses a design for a spent catalyst distributor for a fluid catalytic cracking unit regenerator. In this design, the spent catalyst is aerated in the spent catalyst distributor by air and combustion or exhaust gases. The aeration facilitates the flow of the spent catalyst through the trough arms of the spent catalyst distributor. As in the Murphy patent, arms that carry spent catalyst are connected to a center shaft and extend outward from the shaft. This patent thus discloses a shape that is very similar to the spokes on a wheel, when viewed from above. However, this design also causes the spent catalyst to be distributed in the regenerator in a very uneven manner.
U.S. Pat. No. 6,809,054 to Myers et al. is directed towards a distributor arrangement for introducing spent fluid catalytic cracking catalyst more uniformly across the dense bed of a regenerator to provided more even contact with regeneration gas in order to avoid hot spots and zones of incomplete combustion. This invention also contemplates the possible use of aeration to fluidize the header to further assist catalyst flow. A spent catalyst-carrying arm extends out from the wall of the regenerator and extends towards, but doesn't touch, the opposite wall. This patent also teaches that small arms can extend from the main arm at angles of 90° or 60°. However, this design, while not in the shape of a spoked wheel, also causes the catalyst to be distributed in the regenerator in a very uneven manner.
Accordingly, it would represent an advancement in the art of regenerating spent catalyst in cracking units if there were a design that would allow the distribution of spent catalyst onto the catalyst bed in a very even manner that would improve the efficiency of the regeneration of catalyst.

Bathtub-type spent catalyst distributor for effective counter-current regeneration in fluid catalytic cracking units

Stone & Webster Process Technology, Inc.


A method for forming metal lines of a semiconductor device, which is capable of eliminating a problem in the planarization caused by the chemical vapor deposition method, namely, the formation of a thin film having a rough surface, an increase in the impurity concentration and an influence on an under layer. The method includes the steps of depositing an anti-diffusion metal layer over a structure formed with a metal contact, depositing a metal layer such as a copper film or aluminum film over the anti-diffusion metal layer in accordance with a physical vapor deposition method, annealing the resulting structure in a chamber maintained at a high temperature and high vacuum without losing the vacuum, thereby planarizing the structure. The method further includes forming an anti-reflection film over the metal layer, patterning the anti-reflection film, the metal layer and the first anti-diffusion film, thereby forming an anti-reflection film pattern, a metal layer pattern, and a first anti-diffusion film pattern that form a line; and forming a second anti-diffusion film on an exposed surface of the anti-reflection film pattern, the metal and the first anti-diffusion film pattern.

1. Field of the Invention
The present invention relates to a method for forming metal lines of a semiconductor device, and more particularly to a method for forming metal lines of a highly integrated semiconductor device.
2. Description of the Prior Art
Generally, previously known copper line polarization methods utilize the chemical vapor deposition method. Since there is no precursor concretely defined for these methods, a number of research efforts are being made in association with the methods.
A thin film deposited according to the chemical vapor deposition method typically has a rough surface. As a result, It is impossible to directly form lines on such a thin film.
Accordingly, the line formation can be carried out after the rough thin film is processed by a polishing process, for example, a chemical mechanical polishing (CMP) process.
Furthermore, where lines of a semiconductor device are comprised of a copper thin film, a degradation in the reliability occurs because the copper thin film contains several percentages of impurity gas. In this case, a deposition device having a complex configuration should also be used.

Method for forming metal lines of semiconductor devices

Hyundai Electronics Industries Co., Ltd.


A seismic source for crosshole testing comprises a hammer rod supported by axial bearings in the ends of a cylindrical housing. Fasteners attach a down-blow hammer to the hammer rod inside the housing. A helical spring inside the housing biases the hammer rod in a downward direction. A hammer cable, attached to the upper end of the hammer rod, raises the hammer rod against gravity and spring pressure until an up-blow hammer attached to the hammer rod below the cylindrical housing strikes the bottom end cap which serves as an anvil. Relaxation of the hammer cable tension results in the down-blow hammer striking the anvil. The device provides compression waves and highly repeatable and selectable-phase shear waves. The device is simple, light and operable by a single person.

The present invention relates to crosshole seismic testing and data gathering and, more specifically, seismic sources for insertion in boreholes.
Crosshole seismic testing has been commonplace for a considerable time; first in the petroleum industry, and later used in a broader spectrum of geological engineering areas. Crosshole testing incorporates placement of a seismic source in one borehole, and a seismic receiver or geophone in another borehole. Analysis of the seismic data received by the geophone provides valuable information on soil types, soil compaction, deposits, faults, and other information useful in geological information.
Useful data and data analysis requires repeatable seismic sources and an ability to distinguish between shear and compression waves generated by the sources. Compression waves are characterized by wave front oscillation in the direction of wave propagation, while shear waves oscillate transversely to the direction of wave propagation. Earlier seismic sources, such as explosive or spark sources, produce primarily compression waves. An example of such a device is disclosed in U.S. Pat. No. 5,305,287 by the applicant. The shear waves are relatively weak and the phase relationship of successive events is random, limiting the usefulness of cumulative or "stacking" methods of data accumulation.
Other seismic sources utilize oscillating masses to provide shear or compression waves. One such device is disclosed in U.S. Pat. No. 5,137,109. These devices require complex hydraulic, electromagnetic, or pneumatic arrangements and require special equipment to transport and power the devices.
There is a substantial need for a simple, lightweight seismic source which provides accurate, repeatable compression and shear waves for seismic analysis.

Reversible polarity borehole seismic device for P and enhanced S-wave crosshole testing


In some embodiments, the invention includes a method of editing a video stream. The method includes storing segment frame icons representing segments of the video stream, the segment frame icons having a layout. The method further includes displaying at least some of the segment frame icons and responding to signals from a user input device by changing the layout of the segment frame icons. In some embodiments, the segment frame icons are arranged in a two-dimensional grid. The segment frame icons may include an image derived from a representative frames of the segments. Changing the layout may involve one or more of the following: re-arranging an order of the segment frame icons in the layout, deleting at least one of the segment frame icons, and adding at least one segment frame icon from another video stream. The segment frame icons may be shot frame icons representing shots of the video stream. The segment frame icons may be subshot frame icons representing subshots of shots of the video stream. Other embodiments are described and claimed.

1. Technical Field of the Invention
The present invention relates to systems and methods for editing video streams. Segments (e.g., shots or subshots) of the video streams are represented by icons which include an image derived from one of the frames of the corresponding segment.
2. Background Art
Video recording has become extremely popular. Traditionally, video tape has been used to record video streams. A video stream is a sequence of frames. In many cases, a VCR (video cassette recorder) is used to playback the video tape. More recently, computers, such as personal computers, have been used to edit video signals. Video editing software is commercially available. For example, the Adobe Premiere™ editor sold by Adobe Systems Incorporated allows a user to edit frames of a video stream by deleting, adding, and re-arranging the order of frames. Some of the frames of the video to be edited (called source clips) are displayed serially in a row in a window on a computer display. The user selects at least some of the source clips for inclusion in an edited footage section, which is displayed below the source clips in the window. The edited video section is initially empty and added to from one or more sources.
The term "shot" is used in the present disclosure. As used herein, the term shot means a portion of a video stream representing an event or a related continuous sequence of actions. The shot may end even though the camera does not stop capturing video signals. Shots often have a particular theme. For example, in a video stream of a child's birthday party, playing a game may be one shot, singing "Happy Birthday" may be another shot, and opening presents may be still another shot, whether or not the camera stops recording between shots. Various techniques have been developed to detect the beginning and ending of shots. For example, techniques for shot detection are described in B. Yeo et al. "Rapid Scene Analysis on Compressed Video," IEEE Transactions on Circuits and Systems For Video Technology, Vol. 5, No. 6, December 1995.
In the Adobe Premiere™ editor, not every frame of the video stream to be edited is visually displayed in the window. Rather, according to the user's designation, for example, only one frame is selected by the editor to be displayed for every N frames in the video stream or only one frame is selected for a particular time interval (e.g., one frame a second). The editor does not make a selection of which frames are to be displayed based on shots that may be included in the video stream.

Systems and methods for editing video streams using a grid-based representation


For the inspection of materials and the detection and characterization of hidden objects, features, or flaws sensors and sensor arrays are used to image form two-dimensional images suitable for characterizing the hidden features. Magnetic field or eddy current based inductive and giant magnetoresistive sensors may be used on magnetizable and conducting materials, while capacitive sensors can be used for dielectric materials. Enhanced drive windings and electrode structures permit nulling or cancellation of local fields in the vicinity of the sense elements to increase sensor sensitivity. The addition of calibration windings, which are not energized during measurements, allows absolute impedance and material property measurements with nulled sensors. Sensors, sensor arrays, and support fixtures are described which permit relative motion between the drive and sense elements. This facilitates the volumetric reconstruction of hidden features and objects.

The technical field of this invention is that of nondestructive materials characterization. This includes inspection of materials for hidden objects and characterization of surface, near-surface, and bulk material condition for flat and curved parts or components using magnetic field based or eddy-current sensors. A specific inspection application is the need for detection of hidden damage in complex and thick structures. This specifically includes detection of deeply buried cracks under fasteners, but also related applications that require imaging of complex constructs, such as hidden corrosion-fatigue (e.g., fatigue cracks initiating from buried corrosion damage), or hidden corrosion in difficult to inspect locations such as the F-15 wing or C-130 longeron. Another application is the detection and identification of hidden objects such as unexploded ordnance, where false indications from harmless clutter need to be suppressed in order for site remediation efforts to be effective.
The capability of existing technologies to discriminate between harmful unexploded ordnance (UXO) and harmless clutter continues to limit the efficacy of UXO remediation. These remediation sites include live ammunition testing ranges, mine fields, and areas of past military actions. Inductive sensors with a single sensing coil are commonly used for detection. These single coil methods often detect all relevant metal objects but generally cannot discriminate between UXO and harmless clutter. Also, research into model based methods, using such single coil sensors, to discriminate between UXO and clutter have shown limited success when variations in the orientation, material types, and damage are considered, even in the absence of clutter. False indications continue to far outnumber verified detections so that site reclamation is typically a slow and costly process.
According to the United Nations, there are over 100 million land mines currently deployed in more than 60 countries. The mines themselves range from large anti-tank mines to small anti-personnel mines and from all metal construction to primarily plastic or even wood. Triggering mechanisms range from direct pressure, to trip wires, to magnetic sensors and fiber optics. In addition, millions of bomblets have been deployed as Cluster Bomb Units (CBUs) during wars and military actions. A significant number of these failed to explode and continue to threaten the populations indigenous to the original combat zones. Being largely constructed of metal, unexploded bomblets are readily detectable with existing hand-held metal detectors. However, current metal detectors have no way of discriminating an intact bomblet, which may be buried at depths up to 1 m (39 in.), from a bomblet fragment or other pieces of shrapnel or metallic debris that is near the surface.
The US Army currently has a deployed mine detector called the AN/PSS-12. This is an inductive type detector that utilizes the creation of eddy currents in a metallic object to alter the impedance of the search coil. This detector has served the Army well, but to be reliably detected the object or mine must be directly beneath the search head and must contain some metal. Other methods such as ground penetrating radar, infrared, acoustic, thermal, and x-ray, have been investigated to solve the problem of detecting low-metal and no-metal mines.

High resolution inductive sensor arrays for UXO


Described herein is a pinned photodiode pixel architecture having a p-type substrate that is independently biased with respect to a pixel area to provide an avalanche region between an n-type region and a p-type region formed on the substrate. Such a pinned photodiode pixel can be used in imaging sensors that are used in low light level conditions.

When capturing low light intensity signals, it may be particularly important to register the light level with the lowest noise possible. Known advanced complementary metal oxide semiconductor (CMOS) image sensors (CIS) make general use of pixels with a so-called four-transistor pinned photodiode (4T-PPD) architecture. In such an architecture, the transistors are used to read out a pinned photodiode (PPD), and some of the transistors can be shared between different pixels. A PPD may help to eliminate or limit several noise sources, for example, PPD reset noise and dark current shot noise, by avoiding interaction of signal electrons with the silicon surface. As such, a PPD may help to significantly to improve signal to noise ratio (SNR). As a result, the remaining dominant noise source shifts to the rest of the readout chain, for example, source follower, column thermal noise, etc.
The design of a PPD generally includes careful optimization of doping concentrations to ensure auto-reset to a predefined pinning voltage at the point that all charges are removed from the diode and thus the diode is said to be empty. Typically, this pinning voltage lies in the range of between around 1.0V and 1.5V, with a circuit voltage, VDD, typically around 3.3V.
SNR can be further improved in two different ways, namely, by further reducing the readout chain noise, and by amplifying the signal itself whilst introducing no or minimal additional noise. Amplification of the signal may be performed as early as possible as all noise sources at intermediate stages are also amplified.
Further, a p-n junction, when reverse biased by a sufficiently large voltage, can break down due to avalanche generation, that is, impact ionization of carriers in the space-charge region. The breakdown happens when the avalanche generation via a positive feedback goes out of control. However, the same avalanche principle can also be utilized as an amplification process when biased just below the breakdown voltage. Generally, the breakdown voltage of a silicon photodiode can be engineered by choosing the appropriate doping concentrations of the p and n side of the junction. By increasing the photodiode doping concentration, the electric field inside the junction also increases and the breakdown voltage, together with the depletion region width, decreases. However, it has been found that, at breakdown voltages below 6V as described by A. I. Biber in 2000 in his thesis entitled "Avalanche Photodiode Image Sensing in Standard Silicon BiCMOS Technology", the breakdown is primarily caused by tunnelling, rather than impact ionization. In the case where the breakdown is caused by tunnelling, there is no signal amplification.
Unfortunately, the reverse bias voltages that are used tend to be beyond what a typical CIS process are designed for, and the operating voltage range of the photodiode is normally limited by the gate oxide thickness of a CMOS transistor in a chosen technology. Whilst it is possible to increase the pinning voltage in a 4T-PPD architecture so that an avalanche photodiode can be implemented, this tends not to be practical due to changes required in the associated circuitry.
Previous attempts to utilize in-pixel avalanche photodiodes, as described by A. I. Biber mentioned above, and in 2008 by Y. S. Kim et al. in an article entitled "Design and characterization of CMOS avalanche photodiode with charge sensitive preamplifier" and by L. Pancheri et al. in an article entitled "G.F.D Low-Noise Avalanche Photodiode in Standard 0.25 μm CMOS Technology", required the use of more complex circuitry leading to poor fill factors.
In US-A-2011/0303822, US-A-2012/0292483 and in an article entitled "A charge-multiplication CMOS image sensor suitable for low-light-level imaging" by R. Shimizu et al., 2009, electron-multiplication is described to achieve avalanche amplification. However, electron-multiplication requires a high voltage capability resulting in CMOS process modification. In addition, a worse fill factor is obtained as more gates need to be employed in each pixel.

Pinned photodiode (PPD) pixel architecture with separate avalanche region

Katholieke Universiteit Leuven, KU Leuven R&D


A multiphase clock generator includes a current mirror, a voltage controller, a pseudo-resistor circuit and a first delaying circuit. The current mirror includes a receiving terminal, a first mirroring terminal and a second mirroring terminal. The voltage controller is connected with the receiving terminal of the current mirror. A feedback terminal of the voltage controller is connected with the first mirroring terminal of the current mirror. A first terminal of the pseudo-resistor circuit is connected with the first mirroring terminal of the current mirror. A second terminal of the pseudo-resistor circuit is connected with a ground terminal. The first delaying circuit is connected with the second terminal of the pseudo-resistor circuit. An input terminal of the first delaying circuit receives a first input clock signal. An output terminal of the first delaying circuit generates a first delayed clock signal.

As known, all electronic chips are operated according to clock signals. For example, an AI chip comprises a neural network system. The neural network system is defined by plural neurons and plural neuron connection weights collaboratively. Moreover, the neural network system can be used for executing various detection and recognition behaviors. Generally, the neuron connection weights of the neural network system are recorded in an analog non-volatile memory. That is, the analog non-volatile memory is suitably applied to the AI chip. Moreover, the computing speed of the AI chip is determined according to the frequency of a clock signal. A frequency synthesizer is able to generate plural clock signals with various frequencies.
The conventional frequency synthesizer comprises a close-loop phase lock loop (PLL) circuit or a combination of a delay lock loop (DLL) circuit and a combinational logic circuit.
FIG. 1A is a schematic circuit diagram illustrating a conventional frequency synthesizer with a phase lock loop circuit. FIG. 1B is a schematic waveform diagram illustrating associated signals for the conventional frequency synthesizer as shown in FIG. 1A. The frequency synthesizer 100 comprises a phase lock loop circuit and a combinational logic circuit 190. The phase lock loop circuit is a multiphase clock generator. The phase lock loop circuit comprises a phase frequency detector (PFD) 110, a charge pump 120, a loop filter 130, a voltage controlled oscillator (VCO) 140 and a frequency divider 150.
The phase frequency detector 110 receives a reference signal CKr and a divided clock signal CKd, and generates a control signal Sctr1 to the charge pump 120.
The charge pump 120 comprises a charging path and a discharging path. According to the control signal Sctr1, the charging path or the discharging path generates a driving current Ic to the loop filter 130.
The loop filter 130 comprises an RC circuit. According to the driving current Ic from the charge pump 120, a charge/discharge control operation is performed on the RC circuit. Consequently, the loop filter 130 generates a tuned voltage Vtune to the voltage controlled oscillator 140.
The voltage controlled oscillator 140 receives the tuned voltage Vtune and generates plural tuned clock signals CKt_1˜CKt_n with the same frequency. When the tuned voltage Vtune is changed, the frequency of the tuned clock signals CKt_1˜CKt_n is correspondingly changed. For example, if n=4, the voltage controlled oscillator 140 generates four tuned clock signals CKt_1˜CKt_4. Moreover, the phase difference between every two adjacent ones of the four tuned clock signals CKt_1˜CKt_4 is 90 degrees.
The frequency divider 150 receives a tuned clock signal CKt_n and performs a frequency division on the tuned clock signal CKt_n. Consequently, the divided clock signal CKd is generated to the phase frequency detector 110. For example, if the frequency of the reference signal CKr is Fref, the tuned frequency Ft of the tuned clock signals CKt_1˜CKt_n is N times the frequency Fref. That is, Ft=N×Fref, wherein N is an integer.
After the combinatorial logic circuit 190 receives the tuned clock signals CKt_1˜CKt_n and performs a logic operation on the tuned clock signals CKt_1˜CKt_n, an output clock signal CKout is generated. The combinatorial logic circuit 190 comprises plural logic circuits. The plural logic circuits generate the output clock signal CKout according to the tuned clock signals CKt_1˜CKt_n. The output frequency of the output clock signal CKout is a specified multiple of the tuned frequency Ft.
For example, the voltage controlled oscillator 140 generates four tuned clock signals CKt_1˜CKt_4. Consequently, as shown in FIG. 1B, the phase difference between every two adjacent ones of the four tuned clock signals CKt_1˜CKt_4 is 90 degrees. For example, the combinatorial logic circuit 190 is an XOR gate. After the tuned clock signals CKt_1 and CKt_2 are inputted into the combinatorial logic circuit 190, the output clock signal CKout is generated. The output frequency Fout of the output clock signal CKout is two times the tuned frequency Ft.
It is noted that the circuitry structure of the combinatorial logic circuit is not restricted. That is, various logic gates may be combined as the combinatorial logic circuit to generate plural clock signals with various frequencies.
FIG. 2 is a schematic circuit diagram illustrating a conventional frequency synthesizer with a delay lock loop circuit. The frequency synthesizer 200 comprises a delay lock loop circuit and a combinational logic circuit 290. The delay lock loop circuit is a multiphase clock generator. The delay lock loop circuit comprises a phase detector (PD) 210, a charge pump 220, a loop filter 230 and a voltage controlled delay line circuit (VCDL) 240.
The phase frequency detector 210 receives a reference signal CKr and a tuned clock signal CKt_n, and generates a control signal Sctr1 to the charge pump 220.
According to the control signal Sctr1, the charge pump 220 generates a driving current Ic to the loop filter 230. According to the driving current Ic, the loop filter 230 generates a tuned voltage Vtune to the voltage controlled delay line circuit 240.
The voltage controlled delay line circuit 240 receives the reference signal CKr and the tuned voltage Vtune, and generates plural tuned clock signals CKt_1˜CKt_n with the same frequency. When the tuned voltage Vtune is changed, the frequency of the tuned clock signals CKt_1˜CKt_n is correspondingly changed. For example, if n=4, the voltage controlled delay line circuit 240 generates four tuned clock signals CKt_1˜CKt_4. Moreover, the phase difference between every two adjacent ones of the four tuned clock signals CKt_1˜CKt_4 is 90 degrees.
After the combinatorial logic circuit 290 receives the tuned clock signals CKt_1˜CKt_n and performs a logic operation on the tuned clock signals CKt_1˜CKt_n, an output clock signal CKout is generated. The combinatorial logic circuit 190 comprises plural logic circuits. The plural logic circuits generate the output clock signal CKout according to the tuned clock signals CKt_1˜CKt_n. The output frequency of the output clock signal CKout is a specified multiple of the tuned frequency Ft.

Multiphase clock generator and associated frequency synthesizer


An e-fuse circuit, a method of programming the e-fuse circuit, and a design structure of the e-fuse circuit. The method includes in changing the threshold voltage of one selected field effect transistor of two field effect transistors connected to different storage nodes of the circuit so as to predispose the circuit place the storage nodes in predetermined and opposite states.

Current electronic fuse (e-fuse) circuits require large areas of chip real estate for the fuses themselves as well as the e-fuse program circuits and read fuse state circuits. As post manufacture programmable modes are increasing, the e-fuse area is likely to increase as well. Further, current e-fuse technology is not only area-inefficient, but requires an additional voltage source capable of driving currents that are high enough to "blow" the fuse which adds additional expense. Therefore, there is a need for an area efficient e-fuse that does not require a separate fuse-blow power supply to program the e-fuse.

International Business Machines Corporation


A method for managing routing tables and data packet forwarding is disclosed. The method comprises obtaining, at a networking device, a first outgoing label associated with one or more output port identifiers of the networking device. The first outgoing label identifies a first destination node. The one or more output port identifiers identify one or more of a plurality of output ports. The method further comprises determining whether or not the one or more output port identifiers are also associated with a second outgoing label. The second outgoing label identifies a second destination node different from the first destination node. The method further comprises merging, into a next hop table allocated in a non-transitory memory, the first outgoing label with the second outgoing label in response to determining that the one or more output port identifiers are also associated with the second outgoing label.

Networking devices often use routing tables in order to facilitate traffic forwarding. In the control plane, certain current systems store label tables identifying next hop nodes using identifiers for nodes to which traffic can be directed. In certain systems, each label table includes next hop addressing information corresponding to a separate destination node. The labels or versions thereof in turn are used by next hop tables.
In accordance with common practice the various features illustrated in the drawings may not be drawn to scale. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. In addition, some of the drawings may not depict all of the components of a given system, method or device. Finally, like reference numerals may be used to denote like features throughout the specification and figures.


A personal multimedia communication system and network for emergency services personnel includes a plurality of personal communication systems linked together and to a base station in a network. Each personal communication system includes a PDA device mounted on a PASS control console, a video camera mounted on the PDA device, a GPS unit, a microphone, and other electronic devices. The various electronic devices are all communicatively connected to the PDA device. Data from the various devices may be collected in the PDA device and wirelessly transmitted to any other node or device in the network, including other personal communication devices. Each personal communication device may serve as a repeater, thus providing a wireless communications link between a device located out of range of the base station.

1. Field of the Present Invention
The present invention relates to communication systems for firefighters, and, in particular, to handheld devices carried by firefighters and other emergency services personnel for collecting, displaying, wirelessly transmitting, and wirelessly receiving multimedia data in hazardous environments.
2. Background
Traditionally, the equipment carried into fires and other hazardous environments by firefighters and other emergency services personnel (generally referred to herein as "firefighters") has been primarily mechanical, with the most important piece of equipment being a self-contained breathing apparatus ("SCBA") for providing the wearer with breathable air. Conventional SCBA's generally include a facepiece, one or more pressurized cylinder or tank, and a hose. The facepiece, which covers the wearer's nose, mouth and eyes and includes a lens for external viewing, is supplied with air from the tanks via the hose. The tanks are secured to the wearer's body by a harness or backpack. One or more gauges are typically supplied to tell the user how much air remains in the tank.
More recently, firefighters have begun carrying a variety of auxiliary equipment on their backpacks or their headgear. Of this additional equipment, one of the most important items is a personal alarm safety system ("PASS") device. This device typically includes a motion sensor for monitoring whether the wearer has become motionless, thus indicating a potential injury or other debilitating condition for the wearer which may be signaled with audible or visual alarms or alert signals. The PASS device may also be integrated with a pressure gauge, thus serving multiple functions. The pressure gauge portion of the PASS device may be separated from the motion sensor portion to permit the user to look at the gauge when desired while positioning the motion sensor on the backpack. However, most PASS devices or systems are incapable of alerting personnel other than the wearer using any method other than the audible or visible alert signals generated by the PASS devices themselves, which has been a serious shortcoming of such devices.
This problem was partially solved with the development of an advanced PASS device which was capable of transmitting data from the PASS device back to a central location. The Scott Emergency Management System ("SEMS"), manufactured by Scott Health & Safety of Monroe, N.C., uses transmitting PASS devices, each carried by an individual firefighter, to transmit PASS data back to a central base station. However, the SEMS devices use a point-to-point protocol, wherein data received from the PASS device may only be transmitted as full duplex radio data directly to a dedicated base station. This technology limits the range of the Scott SEMS device. This limitation can be overcome by deploying repeaters to allow greater effective transmission distances from individual transmitting PASS devices. Unfortunately, using repeaters to relay the information has shortcomings in firefighting environments. First, time must be taken to place the repeaters in key locations in and around the burning building or other firefighting environment in order to have the ability to have at least one repeater within range of every firefighter and the base station. In addition, the repeaters are not mobile, and each will remain in a single location until it is physically moved to another one, which is also time consuming. Further, in a building fire it is not always possible to retrieve the repeater if dropped inside the building due to changes in the building environment. Thus, a more flexible and effective transmitting PASS system is needed.
In addition, there has been an increased emphasis in recent years on the development of other electronic devices to be carried by firefighters. These include heads up displays ("HUDs") for displaying tank pressure or other information to a user directly in his line of sight; video cameras, and particularly thermal imaging cameras, for capturing visual data or for use in seeing through dense smoke, recognizing areas of thermal stress, and the like; GPS devices for giving a firefighter information about his location, and many other devices. In addition, additional onboard sensors have been developed or are being developed for monitoring biometric conditions of the firefighter, environmental conditions, additional equipment information, and many other conditions and data. Still further, firefighters continue to carry audio communications devices such as radios and the like to facilitate communications between firefighters or to a command center located outside the immediate area of danger.
Unfortunately, until now there has been no effort to consolidate all of this information in a single location, or to communicate multiple different types of data from one firefighter to another or from one firefighter to a command center using a single device. This means that there is no central location or device carried by a firefighter on which he may view or otherwise receive multiple different types of data, thereby avoiding the problem of having to check or consult different devices to receive different types of data. Moreover, it has been impossible to correlate data of one type with data of another type without going through a tedious manual process, if such a correlation is possible at all. For example, it is difficult if not impossible with current systems and devices to correlate GPS data captured over time by a firefighter's GPS device with video data captured by a thermal imaging camera carried by the same firefighter. Likewise, it has been difficult or impossible to correlate audio signals, video signals or data, positional data, biometric data, environmental data, SCBA status information and other data using either the firefighter's current equipment or at the command center using data transmitted from the firefighter thereto.
Thus, a convenient, robust, handheld solution to all of these problems is needed in order to improve the effectiveness of firefighters and other emergency services personnel.

This patent is subject to a terminal disclaimer.

Personal multimedia communication system and network for emergency services personnel


A power unit has a power case which includes a crankcase portion integrally formed with a transmission case portion. The crankcase portion forms a crankcase in which the crankshaft of a 4-cycle internal combustion engine is received. The transmission case portion forms a transmission case in which a wet type multiple disc friction clutch for transmitting the torque of the crankshaft is received. A partition wall makes the crankcase independent of the transmission case, and thus separates the lubrication system of the internal combustion engine from the lubrication system of the friction clutch. The lubrication structure of the present invention can improve the durability of the friction clutch and make the friction clutch compact, and secure good connection performance of the friction clutch by separating the lubrication system of an internal combustion engine from the lubrication system of friction clutch.

1. Field of the Invention
The present invention relates to the lubrication structure of a power unit mounted on, for example, a vehicle. The power unit has a power case in which a crankcase is integrally formed with a transmission case. A crankshaft of a 4-cycle internal combustion engine is received in the crankcase. A wet type friction clutch is received in the transmission case.
2. Description of the Background Art
A conventional lubrication structure of this kind of power unit, for example, is shown in the lubrication structure disclosed in Japanese Patent Unexamined Publication No. 6-288214. In the conventional structure, a clutch case having a multiple disc friction clutch therein communicates with a transmission case having an output shaft and a transmission shaft therein which is provided with various kinds of gears. The communication is via a communication hole and an oil pan to keep the oil level in the transmission case and that of the clutch case at the nearly same level. Also, a magnet case in which a flywheel magnet is received communicates with a crankshaft case in which a crankshaft is received via the communication hole to keep the oil level in the crankshaft case and the oil level in the magnet case at the nearly same level.
The oil stored at the bottom portion of the crankshaft case is sucked, pressurized and discharged into the transmission case by a suction oil mechanism. The oil sucked from a suction port made in the transmission case is pressurized by the oil pump mechanism for lubrication, is cleaned by a oil filter, then is sent to the crankshaft, crankpin and lubricating portions in the crankcase, and then is returned to the crankcase after lubrication.
In the conventional lubrication structure, the oil stored in the transmission case, the clutch case and the oil pan is used for lubricating the lubricating portions in the crankshaft and the crankcase of the internal combustion engine, and is sucked by the suction oil pump mechanism and is returned to the transmission case. Thus, the lubrication system of the internal combustion engine and the lubrication system of the transmission shaft and the multiple disc friction clutch have a shared portion and use the same lubricating oil. Therefore, the oil lubricating the internal combustion engine is used for the lubrication system of the transmission shaft and the clutch.
However, the oil lubricating the internal combustion engine receives combustion heat and increases in temperature, and its viscosity is decreased by the increased oil temperature. Accordingly, this reduces the cooling capacity of the oil for cooling the multiple disc clutch, and thus reducing the durability of the multiple disc clutch. Therefore, in order to secure a clutch capacity, that is, a friction force necessary for good clutch connection, it is necessary to enlarge the diameter of a friction disc or to increase the number of the friction discs, which presents a problem of enlarging the clutch and thus the power unit.
Further, in the case where an additive is added to the lubricating oil in order to reduce the friction of the sliding portions of the crankshaft and a piston, the same lubricating oil is also used for the multiple disc friction clutch, and hence it produces a slip on the multiple disc friction clutch, resulting in a reduction of the connection performance thereof.
It is therefore an object of the present invention to provide a lubrication structure of a power unit which can improve the durability of the friction clutch and make the friction clutch compact and secure good connection performance of the friction clutch by separating the lubrication system of a 4-cycle internal combustion engine from the lubrication system of a wet type friction clutch.
The present invention is a lubrication structure of a power unit having a power case in which a crankcase portion for forming a crankcase, in which the crankshaft of a 4-cycle internal combustion engine is received, is integrally formed with a transmission case portion for forming a transmission case, in which a wet type friction clutch for transmitting the torque of the crankshaft is received. The crankcase and the transmission case are formed in independent cases, and the lubrication system of the internal combustion engine is separated from the lubrication system of the friction clutch.
The crankcase is made independent of the transmission case, and the flow of the lubricating oil is stopped between both cases in the integrally formed power case. In this way, the lubrication system of the internal combustion engine is separated from the lubrication system of the friction clutch. Accordingly, the lubricating oil for the internal combustion engine for lubricating the lubricating portions of the internal combustion engine, such as lubricating portions in the crankcase and others, is not mixed with the lubricating oil for the transmission mechanism supplied for the wet type friction clutch. Accordingly, since the friction clutch is not supplied with the lubricating oil for the internal combustion engine whose temperature is raised to a comparatively high temperature by the combustion heat, or which includes an additive for reducing the friction, the friction clutch is effectively cooled by the lubricating oil for the transmission mechanism, which is not heated by the combustion heat and has a comparatively low temperature, and is prevented from slipping owing to the lubricating oil for the internal combustion engine, whose viscosity is reduced by the high temperatures or which includes the additive described above, to secure a large friction force.
As a result, the following effects are made. Since the friction clutch is not supplied with the lubricating oil for the internal combustion engine whose temperature is raised to a comparatively high temperature by the combustion heat, the cooling ability of the lubricating oil is improved, and hence the durability of the friction clutch is also improved. Also, since the friction clutch is not supplied with the lubricating oil for the internal combustion engine whose temperature is raised to a high temperature to reduce its viscosity or which contains the additive for reducing the friction, it is possible to easily secure a necessary friction force and hence to realize a set clutch capacity by a compact friction clutch, and further to prevent the friction clutch from slipping and hence to obtain the friction clutch having a good connection performance. In this manner, since the friction clutch can be made compact, the power unit can also be made compact.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.


The present invention discloses a preventive or ameliorant of hypertension or medical symptoms caused by it and a food or beverage that prevents or ameliorates hypertension or medical symptoms caused by it that contain for its active ingredient dioxabicyclo3.3.0!octane derivative represented by the formula (2). ##STR1## wherein, R.sup.1, R.sup.2, R.sup.3, R.sup.4, R.sup.5 and R.sup.6 are respectively and independently a hydrogen atom or an alkyl group having 1 to 3 carbon atoms, or R.sup.1 and R.sup.2 and/or R.sup.4 and R.sup.5 collectively represent a methylene group or ethylene group, and n, m and L represent 0 or 1.

1. Field of Invention
The present invention relates to a preventive or alleviative agent for hypertension or medical symptoms caused thereby comprising as its active ingredient a dioxabicyclo3.3.0!octane derivative, a food or beverage having the effect of preventing or alleviating hypertension or medical symptoms caused thereby comprising a dioxabicyclo3.3.0!octane derivative or an extract comprising said derivative as its active ingredient, and a process for production thereof.
2. Related Art
Although the condition in which blood pressure remains continuously high is referred to as hypertension, there are considerable differences of opinion in the art with respect to what degree of high blood pressure constitutes hypertension. The World Health Organization (WHO) has made the following criteria based on epidemiological considerations. Namely, the normal range of blood pressure is set at 140/90 mmHg or less, and blood pressure of 160/95 mmHg and above is considered to constitute high blood pressure. However, in addition to a certain degree of correction required according to age and sex, in the clinical setting, there are many practitioners who consider blood pressure in excess of 150/90 mmHg to constitute high blood pressure.
Although there are various diseases that bring about hypertension, these can be broadly classified into essential hypertension, for which the cause is unknown, and secondary hypertension, for which there is a definite cause. Examples of diseases that cause secondary hypertension include kidney diseases such as glomerulonephritis and pyelonephritis, renal artery arctation, endocrine diseases such as primary aldosteronism, Cushing's syndrome (both of which are adrenocortical tumors) and melanocytoma (an adrenomedullary tumor), aortic arctation, certain types of central nervous system diseases and others. On the other hand, essential hypertension is responsible for the largest portion of hypertension cases, accounting for roughly 80% of all hypertension cases. The cause remains unknown at present, and although genetic factors have clearly been shown to be involved, details of the genetic mode are unknown.
Essential hypertension frequently occurs between the ages of 35 and 40. In the beginning, blood pressure is labile, and with the exception of the rise in blood pressure, hypertension does not exhibit any other extraordinary subjective or objective symptoms. With the passage of time, high blood pressure becomes continuous, eventually leading to left ventricular hypertrophy, arteriosclerosis and arteriolosclerosis, and causing ischemic diseases of the brain, heart and kidney. As the patient enters adulthood and old age, hypertension eventually causes death due to cerebral hemorrhage, cerebral thrombosis, congestive heart failure, myocardial infarction or uremia. Thus, hypertension is a disease that has a detrimental effect on various vascular diseases, and in particular, vascular disorders of the heart and brain. The extent to which hypertension can be prevented and treated is therefore an important issue for modern medicine.
At present, although it is possible to lower blood pressure even in the most serious cases of hypertension due to the remarkable progress that has been made in the area of depressors, conversely numerous problems remain to be solved with respect to adverse side effects of these drugs. Since treatment of hypertension requires drug therapy over an extended period of time (usually the life of the patient), there is a need for a drug that has minimal adverse side effects while offering even greater efficacy. In addition, since the particular depressor that is suitable for an individual may vary even for the same type of hypertension, various types of different depressors are necessary. Moreover, there is also a need for a mild depressor that is essentially free of adverse side effects in cases of hypertension that are not that serious.
On the basis of these viewpoints, research has recently been conducted on a plant extract to be used in pharmaceutical applications that has blood pressure lowering effects. Differing from conventional depressors such as calcium antagonists and .beta.-blockers, this plant extract preparation has hardly any adverse side effects, and is considered to occupy an important position in applications to self-medication. Particularly in the society of today with its extremely high levels of stress, there are many persons suffering from symptoms of stress, which can be considered to be a precursor of hypertension. A natural pharmaceutical preparation that is extremely safe and offers excellent efficacy is needed by these people.

Method for preventing or alleviating cerebral apoplexy


A wiper for an automobile rear-view mirror includes a wiper transmission device disposed at the rear side of a mirror base, a connecting rod and a wiper. The wiper transmission device has a transmission motor provided with a drive gear engaged with a driven gear coupled with a worm that is engaged with a worm gear. The worm gear is connected with a driven worm by a support shaft, and the driven worm is engaged with a driven worm gear secured on a rotating shaft, which has its outer end inserted out of the rearview mirror and fixed with a connecting rod having a wiper fixed thereon. When the wiper transmission device is started, the wiper can sway upward and downward for wiping water drops off the surface of the rear-view mirror to keep it clear, enabling a driver to clearly watch the traffic conditions and drive safely.

1. Field of the Invention
This invention relates to a wiper for an automobile rear-view mirror, particularly to one able to wipe out water drops on the surface of a rear-view mirror of an automobile to enable a driver to clearly watch the traffic conditions reflected in the rear-view mirror and drive with safety.
2. Description of the Prior Art
As commonly known, it is of great importance for a driver to watch the moving conditions of the automobiles coming from behind through the left and the right rear-view mirror before making a turn, overtaking a car, changing lanes or parking. However, the rear-view mirrors of an automobile are respectively positioned at its opposite outer sides; therefore, in raining days, rain water will remain on the surfaces of the rear-view mirrors and make the rear-view mirrors fail to reflect images clearly. As a result, the driver of an automobile cannot clearly watch the moving conditions of the automobiles coming from behind, thus rendering a driver unable to drive with safety.

Wiper for an automobile rear-view mirror