A superscalar microprocessor is provided having a load/store unit which receives a pair of pointers identifying the oldest outstanding instructions which are not in condition for retirement. The load/store unit compares these pointers with the reorder buffer tags of load instructions that miss the data cache and store instructions. A match must be found before the associated instruction accesses the data cache and the main memory system. The pointer-compare mechanism provides an ordering mechanism for load instructions that miss the data cache and store instructions.

1. Field of the Invention
This invention relates to the field of superscalar microprocessors and, more particularly, to branch misprediction recovery and load/store retirement.
2. Description of the Relevant Art
Superscalar microprocessors achieve high performance by executing multiple instructions simultaneously using the shortest possible clock cycle. As used herein, the term "clock cycle" refers to the interval of time that a superscalar microprocessor requires to complete the various tasks employed within its pipeline (for example, the processing of instructions). Two features important to high performing superscalar microprocessors are branch prediction and out-of-order execution.
Branch prediction is the process of speculatively selecting the direction that a branch instruction will select before the branch instruction is executed. Microprocessors execute instructions sequentially: when a first instruction is executed, the second instruction to be executed is the instruction stored in memory adjacent to the first instruction. Branch instructions, however may cause the next instruction to be executed to be either the next sequential instruction, or alternatively an instruction which resides in another memory location that is specified by the branch instruction. The memory location specified by the branch instruction is typically referred to as the "target" of the branch. Which of the instructions is selected for execution typically depends on a condition that the branch instruction tests. An exemplary tested condition is the value stored in a register, wherein the branch target is selected if the register contains zero and the next sequential instruction is selected if the register does not contain zero. It is noted that some branch instructions do not test a condition. Unconditional branches always select the target path, and typically no instructions are specifically encoded into the next sequential memory locations.
Branches occur relatively frequently in computer programs. In order to continue executing large numbers of instructions simultaneously, superscalar microprocessors predict which direction (or which "path") each branch instruction will select: next sequential or target. The microprocessor then speculatively executes instructions residing on the predicted path. If the superscalar microprocessor "mispredicts" the path that a branch instruction selects, the speculatively executed results are discarded and the correct path is fetched and executed. Various branch prediction mechanisms are well-known.
Because branch instruction mispredictions occur, a misprediction recovery mechanism is necessary. A misprediction recovery mechanism is a mechanism which causes the corrected fetch address to be fetched from the cache and the associated instructions to be dispatched to the instruction processing pipelines. The corrected fetch address is the address generated by the branch instruction for locating the next instruction to be executed. The misprediction recovery mechanism is required to complete in relatively few clock cycles, so that correct instructions are executed soon after the misprediction is determined. Typically, the clock cycles between the clock cycle in which the misprediction is discovered and the clock cycle in which the corrected instructions begin execution are idle cycles. Overall performance of the superscalar microprocessor is degraded by the number of idle cycles it must endure.
Superscalar microprocessors are evolving such that they execute larger and larger numbers of instructions simultaneously. However, branch instructions continue to occur in programs with the same frequency. Therefore, superscalar microprocessors are implementing branch prediction schemes in which multiple branch predictions may be outstanding in a given clock cycle (i.e. multiple branch paths have been predicted, but have not been validated by the execution of the associated branch). With the possibility of multiple branch instructions executing in a given clock cycle, and therefore multiple mispredictions being detected, the misprediction recovery mechanism becomes more complex. However, the importance of the misprediction recovery mechanism completing in relatively few clock cycles is not diminished. A misprediction recovery mechanism which requires relatively few clock cycles to complete and that can correctly resolve multiple branch mispredictions is desired.
Along with branch prediction, another feature intended to improve the performance of superscalar microprocessors is out-of-order execution. Out-of-order execution is the process of executing a particular instruction in a clock cycle that is before a clock cycle in which instructions which are before the particular instruction in program order are executed. An instruction which does not depend on the results generated by the instructions before it in program order need not delay its execution until the instructions before it execute. Because the instruction must be executed at some time, performance is advantageously increased by executing the instruction in a pipeline stage that would otherwise be idle in a clock cycle.
Unfortunately, certain instructions cannot be executed out-of-order. Programs assume that instructions are executed in-order, and therefore out-of-order execution must be employed in a manner which is transparent to programs. Exemplary instructions that cannot be executed out-of-order are load instructions that miss the data cache and store instructions. Store instructions modify memory, as opposed to other instructions which modify registers. If the store instruction is allowed to modify the data cache out-of-order and is then cancelled due to a previous branch misprediction or an interrupt, then the data cache would contain corrupted data. Therefore, the store instruction must not be allowed to modify the data cache or main memory until previous instructions have executed, so that the store instruction is not going to be cancelled. Load instructions that miss the data cache cannot be executed out-of-order either, as will be discussed below.
Data caches are implemented either on the same silicon substrate as a superscalar microprocessor, or are coupled nearby. The data cache is a high speed memory which is configured to store copies of a main system memory (when employed in a computer system). When a load or store instruction accesses the data cache, the access is found to be either a "hit" or a "miss". If an access is a hit, then the associated data is currently stored in the data cache. If the access is a miss, the associated data is in main memory. Load instructions are allowed to execute out-of-order when reading the data cache. However, when load instructions miss the data cache they are required to execute in order. Otherwise, a load miss may begin a transfer from main memory and then be cancelled. The external bus bandwidth used by the access would then be wasted. Furthermore, the data being transferred may cause a line to be removed from the cache. If that removed line is later needed, it will have to be transferred in from main memory and more external bus bandwidth would be wasted. Therefore, load instructions that are data cache misses should not execute out of order. A mechanism is needed to correctly order load instructions that are data cache misses and store instructions.

Load/store unit with multiple oldest outstanding instruction pointers for completing store and load/store miss instructions


The color image forming apparatus includes a CPU configured to correct a result of detecting a toner patch by a density sensor based on a result of detecting a first white reference plate by the density sensor, and to control a density or chromaticity of a toner image based on a result of detecting the toner patch by the density sensor corrected by the CPU. The CPU is configured to further correct the result of detecting the first white reference plate by the density sensor based on a result of detecting, by the density sensor, a second white reference plate for correcting the first white reference plate. With this configuration, a correction of a sensor output is performed with high accuracy, and detection accuracy of the density or the chromaticity by the sensor is enhanced.

1. Field of the Invention
The present invention relates to an image forming apparatus that controls an image processing unit by using information obtained by a color discrimination method of an electrophotographic or inkjet color image forming apparatus, such as a color printer and a color copy machine.
2. Description of the Related Art
In recent years, higher image quality of an output image has been demanded for an electrophotographic or inkjet color image forming apparatus such as a color printer and a color copy machine. Particularly, in the case of the electrophotographic color image forming apparatus, a constant gradation-density characteristic needs to be maintained all the time, because the color balance may be disrupted due to a variation in the density of an image caused by a change of the environment or a variation in each part of the apparatus due to a long time usage. To this end, a density sensor or a chromaticity sensor (hereinafter referred to as "color sensor") for detecting a density of a monochrome toner image or a color of a full color image on a transfer material after transferring and fixing toner images is installed in the color image forming apparatus. A color toner patch (hereinafter referred to as "patch") for controlling the density or the chromaticity is formed on the transfer material, and the density or the chromaticity detected by the color sensor is fed back to a process condition, such as an exposure amount, a process setting, or a look-up table (LUT). With this configuration, the density or the chromaticity of the final output image formed on the transfer material is controlled. For example, a gamma characteristic control is performed based on the measured density, or a correction of a color matching table or a color separation table is performed based on the measured chromaticity. The same goes for an inkjet printer.
In order to detect the density or the chromaticity of the patch with the color sensor, a white reference plate or the like for correcting a sensor output is required for the following reasons. The first reason is that a fluctuation of spectroscopic characteristics of a light emitting element and a light receiving element constituting the sensor needs to be corrected. The second reason is that, even when the same patch is used for the detection, different outputs may be produced due to a temporal change of a light emitting unit or a light receiving unit constituting the sensor or a change of the ambient temperature. The third reason is that, because a large number of transfer materials pass near the sensor at the time of normal printing, paper dust, toner, or ink may be scattered and deposited or adhered to a surface of the sensor, causing a degradation of the sensor output. In addition, in order to detect the absolute density or the absolute chromaticity of the patch by using the color sensor, there is required a white reference plate or the like for correcting the sensor output, which has a known absolute value of the density or the chromaticity.
For example, in Japanese Patent Application Laid-Open No. 2003-149903, a process of measuring the density or the chromaticity illustrated in FIG. 9 is executed by using a filter-type color sensor. Firstly, in Steps S1001 and S1002, a process of adjusting the color sensor is executed based on an absolute reference such as the white reference plate. Specifically, in Step S1001, an RGB output measured value Dref(i) (i=r, g, and b, the same applies hereinafter) of the absolute reference is detected by the color sensor. In Step S1002, a correction coefficient Oref(i)/Dref(i) is obtained from the RGB output measured value Dref(i) of the detected absolute reference and an RGB output theoretical value Oref(i) stored in advance. In Steps S1003 and S1004, a process of measuring the absolute density or the absolute chromaticity by the adjusted color sensor is executed. Specifically, in Step S1003, an RGB output measured value D(i) of a patch is detected by the color sensor. In Step S1004, the RGB output measured value D(i) of the detected patch is converted into an RGB output value O(i) corrected by using the absolute reference. The RGB output value O(i) is obtained by uniformly multiplying the RGB output measured value D(i) of the detected patch by the correction coefficient Oref(i)/Dref(i) as represented by Equation (1).O(i)=D(i)×Oref(i)/Dref(i)(i=r,g, and b)  Equation (1)
Similarly, in a measurement of the density and the chromaticity by a spectrophotometric color sensor, a process of adjusting the color sensor by using the absolute reference and a process of measuring spectroscopic reflectivity by using the adjusted color sensor are executed. It is assumed that a spectroscopic output measured value of the absolute reference is represented by Dref(m), a spectroscopic output theoretical value is represented by Oref(m), a spectroscopic output measured value of a patch is represented by D(m), and a spectroscopic output value of the patch corrected by using the absolute reference is represented by O(m), provided that, m represents a wavelength in the visible light wavelength band. For example, m indicates an arbitrary wavelength in a wavelength range from 380 nm to 730 nm. As represented by Equation (2), the obtained spectroscopic output measured value D(m) of the patch is converted into the spectroscopic output value O(m) corrected by using the absolute reference. The spectroscopic output value O(m) is obtained by uniformly multiplying the obtained spectroscopic output measured value D(m) of the patch by a correction coefficient Oref(m)/Dref(m).O(m)=D(m)×Oref(m)/Dref(m)(m=380,390, . . . , 730)  Equation (2)
In the following, the reference plate, which is the absolute reference, is described as white. However, the reference plate is not limited to white, but may be any color so long as the absolute value of the density or the chromaticity is known.
However, the white reference plate that is generally and commonly used as the absolute reference for correcting the output of the color sensor may be discolored compared to the initial white reference plate due to yellowing generated after a long time irradiation with light from the color sensor, for example. Further, in the same manner as the color sensor, the white reference plate may become unusable as the absolute reference due to the scattering of paper dust, toner, or ink. If the correction of the color sensor output is performed in a state in which the white reference plate is stained and discolored, the color sensor ends up with outputting a value that is different from the actual density or chromaticity of the patch. If a control of the density or chromaticity is performed by using the result, the color balance cannot be obtained, and as a result, a desired gradation-density characteristic cannot be obtained. Not only that, the gradation-density characteristic is likely to disrupt the color balance.


In an image projector for enlarging and projecting an image on a screen, a condition of a discharge lamp is judged so as to alarm that the discharge lamp has been damaged or life of the discharge lamp reaches to a late stage to a user. A driving circuit of the image projector comprises: a driving signal generator generating a driving signal applied to the discharge lamp, and executing feedback control so as to make power consumption of the discharge lamp substantially constant; a lamp condition judger judging that the discharge lamp has been damaged, the discharge lamp has been normally lighted or not lighted or life of the discharge lamp reaches to a late stage corresponding to a value of voltage or current of the driving signal; and an alarm output unit outputting an alarm corresponding to the result of judgment of the lamp condition judger.

1. Field of the Invention
The present invention relates to lighting control of a lamp of an image projector.
2. Description of the Related Art
An image projector, which reproduces an image with using an image data outputted from an external apparatus such as a personal computer or a video camera and projects the image on a screen by a projection lens, is conventionally known.
Since the image projector enlarges the image on the screen disposed at a long distance, it uses a high intensity discharge lamp as a light source for displaying the image brightly. In the discharge lamp, it is known that a load between terminals of the lamp where the discharge occurs (hereinafter abbreviated as load of the lamp) varies after starting the lighting of the lamp, so that a driving voltage necessary for lighting the lamp (hereinafter abbreviated as lamp voltage) varies correspondingly. Specifically, the lamp voltage is relatively low just after the start of the lighting, and the lamp voltage gradually increases to be stable. Furthermore, the lamp voltage of the discharge lamp entirely becomes higher when life of the discharge lamp reaches to a late stage.
If the driving voltage applied to the discharge lamp is set to be constant regardless of such the behaviors of the discharge lamp, the luminance of the discharge lamp becomes lower corresponding to the increase of the load of the lamp. Thus, it is necessary to execute a feedback control of the driving voltage by a driving circuit of the image projector in a manner so that the luminance of the discharge lamp is maintained substantially constant. In other words, it is necessary that the power consumption of the discharge lamp is maintained substantially constant.
On the other hand, when the driving voltage of the discharge lamp is made too high due to the feedback control, the discharge lamp involves a risk of bursting. Thus, a safety circuit is conventionally provided in the driving circuit of the discharge lamp in a manner so that the safety circuit senses a value of the driving voltage of the discharge lamp, and outputs an alarm or extinguishes the discharge lamp when the value of the driving voltage becomes equal to or larger than a predetermined reference value.
Conventionally, various technologies are proposed for estimating the life of the discharge lamp and announcing a time for replacing the discharge lamp or occurrence of burning out of the discharge lamp.
In a lighting apparatus of a discharge lamp shown in Publication Gazette of Japanese Patent application 5-36481, the above-mentioned behaviors that the lamp voltage is lower just after the start of the lighting, and the lamp voltage gradually increases to be stable, and the lamp voltage of the discharge lamp entirely becomes higher when the life of the discharge lamp reaches to a late stage is utilized for announcing that the discharge lamp should be replaced. The lighting apparatus senses the lamp voltage after passing a predetermined term from the start of the lighting of the discharge lamp, counts a number of the cases that the lamp voltage becomes equal to or higher than a predetermined reference voltage, and displays a message to replace the discharge lamp when the number becomes larger than a predetermined reference number.
In another lighting apparatus shown in Publication Gazette of Japanese Patent application 2000-48989, the safety circuit is activated after passing a predetermined term from the start of the lighting of the discharge lamp in order to prevent malfunction of the safety circuit due to the increase of the lamp voltage in a short term when the life of the discharge lamp reaches to a late stage.
A current, however, flows in the discharge lamp, even when the discharge lamp has not been lighted due to the driving voltage is lower. The conventional driving circuit of the image projector senses the driving voltage applied to the discharge lamp and only judges whether it is in critical condition or not by comparing a value of the driving voltage with the predetermined reference value corresponding to an upper limit of the permissible driving voltage. Thus, it is impossible to judge whether the discharge lamp has been actually lighted or not.
Furthermore, when the feedback control is executed under the condition that the driving voltage is lower, the current flowing in the driving circuit becomes larger. Thus, there is a possibility that the critical condition such as over heat occurs due to the over current.
Still furthermore, when it is attempt to relight the discharge lamp just after the discharge lamp has been extinguished (it is called "hot-start"), the temperature of the discharge lamp has become too high so that the load of the lamp has been too large. Thus, it is necessary to make the driving voltage much higher so as to relight the discharge lamp. Thus, the discharge lamp could be damaged. With respect to such the problem of the hot-start, the same goes for the above-mentioned conventional lighting apparatuses.


A screw device for orthodontic treatment comprises a screw-body part, a platform part integrally formed with the screw-body part, and a head part. The head part is detachable from and exposed outside the screw-body part and is operatable to hook a spring (or rubber band) for orthodontic treatment. Since the head part is detachable, various types of head parts can be chosen to attach on the same platform part and screw-body part for performing different orthodontic treatments. Cost to manufacture the screw device is lower, and flexibility and convenience to use the screw device are higher. The external threads of the screw-body part are slightly loosened and tapered at a portion away from the platform part and relatively concentrated at another portion near to the platform part.

As shown in FIG. 1, in a conventional orthodontic treatment process, after part of the maxilla (or mandible) 10 is cut off or a tooth 12 is pulled out (usually not the incisor), the tooth 12 or the maxilla (or mandible) 10 is pulled and dragged by an orthodontic archwire 13 after the operation for helping the maxilla (or mandible) 10 to heal over or correcting the position of the tooth 12. In order to maintain the position of the orthodontic archwire 13 relative to the tooth 12, it is usually to apply several orthodontic brackets 14 adhered onto the tooth 12, and each orthodontic bracket 14 is arranged with slot 141 for providing an accommodation for the orthodontic archwire 13. The width and the depth of the slot 141 must be slightly larger than the diameter of the orthodontic archwire 13 such that, not only may the orthodontic archwire 13 be appropriately glided along the extensive direction of the slot 141, but also may the orthodontic archwire 13 be kept from being dropped out of the slot 141.
As known in the prior arts, in order to provide a pulling-and-dragging force to the orthodontic archwire 13, a screw 20 is screwed on a maxilla (or mandible) 10 at the adjacency of a molar 121, then a spring 15 or rubber band is further connected between the screw 20 and the end of the orthodontic archwire 13 for providing an appropriate pulling-and-dragging force. Since the end of this kind of spring 15 used specially for orthodontic treatment in current market is all arranged with a hook ring 151 so, for the connection between the spring 15 and the end of the orthodontic archwire 13, the end of the orthodontic archwire 13 just may be bent into a hook structure 131, then it can be easy to fit the hook ring 151 of the spring 15 into the hook structure 131 of the end of the orthodontic archwire 13, such that both connection is completed. Relatively, the connection between the spring 15 and the screw 20 is more difficult relatively.
As shown in FIG. 2 and FIG. 3, since the screw 20 currently applied for orthodontic treatment is all belonged to the common screw 20 as shown in FIG. 2 and FIG. 3, so the materials used for the screw 20, orthodontic bracket 14, and orthodontic archwire 13 are usually pure titanium alloy or stainless steel, those which are harmless to the human body. The screw 20 is commonly comprised of two parts: the head part 21 and the screw-body part 22. A general screw head groove 211 is then arranged on the head part 21 for providing a securing operation for a screwdriver (not shown in the figure). Usually, the dimension of the head part 21 is the widest part along the entire screw 20. Further, the diameter of the head part 21 is usually larger than the inner diameter of the hook ring 151 of the end of the spring 15, such that it is impossible for the spring to be hooked and hanged on the screw 20 directly. Therefore, for the current prior arts, an additional ligature wire 16 is used for tying the end of the spring 15 onto the screw-body part of the screw 20. However, such kind of method has caused several shortcomings as follows:
(1) It is difficult to operate. Since the head part 21 of the screw 20 is larger than the hook ring 151 of the spring 15, so it is impossible for the spring to be hooked and hanged on the screw 20 but, if the diameter of the head part 21 of this prior screw 20 is designed to be smaller than the hook ring 151 of the spring 15, then it will be much more easier for the spring 15 to be dropped off from the screw 20 to cause further inconvenience. Therefore, the prior arts that still use additional ligature wire 16 for tying the spring 15 and the screw 20 not only cause inconvenient in operation, but also cause difficulties for a less-experienced doctor to approach such kind of operation.
(2) It is easy for the spring 15 and the ligature wire 16 to impinge the gingiva 11. Since the ligature wire 16 is tied on the screw-body part 22 of the screw 20, so the ligature wire 16 and the spring 15 will be sometimes abutted against the gingiva 11 and irritate it. Not only will the user feel uncomfortable, but also may it sometimes hurt the gingiva 11 or reduce the healing-over speed of the wounds after operation.
(3) It is easy loosening for the screw 20. Since the screw-body part 22 of the screw 20 has a partial length that must be left in advance for tying the ligature wire 16 so, when the screw 20 is being driven tightly, it is impossible to screw the screw-body part 22 of the screw 20 completely into the maxilla (or mandible) 10 to make its head part 21 abutted smoothly against the maxilla (or mandible) 10. Contrarily, the head part 21 of the screw 20 must be kept an appropriate distance with the maxilla (or mandible) 10 for proceeding the operation of tying the ligature wire 16. In such way, the pulling-and-dragging force between the spring 15 and the ligature wire 16 will create a torque to the head part 21 of the screw 20, so it is easy to cause the screw 20 to loosen or even to drop off and break off.
(4) The gingiva 11 will be ugly after being healed over. Since the tissue of the gingiva 11 will be sometimes abutted against the screw 20 to grow during the healing procedure and there is a lack of appropriate guidance and restriction, so the surface of the gingiva 11 is uneven and ugly after being healing over.
(5) It only has a single function. This kind of prior screw 20 only can be applied in tying the ligature wire 16 for connecting the spring 15, neither does it have any other function, nor is it possible for providing an accommodation for the orthodontic archwire 13.
U.S. Pat. No. 4,988,292 discloses an abutment for orthodontic anchorage to a dental implant fixture. It comprises an endosseous implant fixture which is fixed in the lower jaw at the site of a missing molar for supporting an abutment for orthodontic anchorage. The abutment and the fixture are connected by a bolt in a detachable manner. However, the abutment of U.S. Pat. No. 4,988,292 does not provide the function of spring hooking. Even if someone tries to hook the spring on the abutment, the spring will be prone to impinge the gingival as previously illustrated. In addition, the fixture is prone to loose since it has identical outer threads and identical outer diameter throughout the entire fixture.
U.S. Pat. No. 5,836,768 discloses a fastening device for fixing orthodontic apparatuses on a dental implant. It comprises an implant which is fixed in the jaw bone, an anchoring screw screwed within an axially arranged threaded bore in the implant, and an occlusal screw located inside the threaded bore and engaged with the anchoring screw. None part of the occlusal screw nor anchoring screw is exposed outside the implant, such that they cannot be used for spring hooking. Even if the spring can be tied (not hook) on a bracket of U.S. Pat. No. 5,836,768, the spring will be prone to impinge the gingival. In addition, the implant is prone to loose since it has identical outer threads and identical outer diameter.
U.S. Pat. No. 5,921,774 discloses a supporting body for use in orthodontic appliance. It comprises a supporting body to be fixed in the jaw bone, an abutment formed with an arm at a side surface thereof, and a male screw for screwing and fixing the abutment onto the top of the supporting body. Since the screw is an independent element and is screwed from a top side of the abutment, therefore the arm can only be form at the side surface of the abutment, and thus the application and flexibility thereof are limited. In addition, the device disclosed by U.S. Pat. No. 5,921,774 comprises at least three elements (e.g., supporting body, abutment and male screw). Not only the cost to manufacture is higher, but also is more complex to use. Moreover, the supporting body is prone to loose since it has identical outer threads (or no threads at all) and identical outer diameter throughout the entire supporting body.
Other prior art, such like U.S. Pat. No. 6,241,516, U.S. Pat. No. 5,071,345, and US Pub. No. 2002/0127510. None of them has been disclosed a screw device which comprises a screw-body part, a platform part and a head part which is detachable from and exposed outside the platform part (or screw-body part) and is operatable to hook the spring for orthodontic treatment.
As known from above description, the prior arts that are used for orthodontic treatment currently still have many shortcomings to be further improved urgently.


A semiconductor device includes a glass substrate having a main surface, a polysilicon film formed on the main surface, having a channel region formed and having a source region and a drain region formed on opposing sides of the channel region, a gate insulating film provided so as to be in contact with the polysilicon film and containing oxygen, and a gate electrode provided in a position facing the channel region with the gate insulating film being interposed. The polysilicon film has a thickness larger than 50 nm and not larger than 150 nm. The polysilicon film contains hydrogen in a proportion not smaller than 0.5 atomic percent and not larger than 10 atomic percent. With such a structure, a semiconductor device attaining a large drain current and having a desired electric characteristic is provided.

1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly to a thin film transistor (TFT) used, for example, in a display device.
2. Description of the Background Art
For example, Japanese Patent Laying-Open No. 2001-345448 discloses a conventional thin film transistor and a manufacturing method thereof The thin film transistor disclosed in this publication includes an alkali-free glass substrate, a silicon nitride film formed on the glass substrate, a polycrystalline silicon film formed on the silicon nitride film and having a channel region and a source/drain region formed in the film, a gate electrode formed with a silicon oxide film (a gate insulating film) provided on the polycrystalline silicon film being interposed, and an insulating layer implemented by an silicon oxide layer formed so as to cover the gate electrode. The insulating layer has a contact hole reaching the source/drain region formed, and a metal serving as a source/drain electrode fills the contact hole.
The polycrystalline silicon film included in the thin film transistor is formed in the steps of initially forming an amorphous silicon film on the glass substrate and thereafter polycrystallizing the amorphous silicon film by instantaneous heating using excimer laser. The polycrystalline silicon film thus obtained has a thickness of 50 nm.
An operation of the thin film transistor will now be described. When the thin film transistor is of an n-type, for example, a drain current flows between the drain region and the source region by applying a positive voltage (5V, for example) to each of the gate electrode and the drain electrode and by connecting the source electrode to the ground.
Meanwhile, Japanese Patent Laying-Open No. 2000-260731 discloses a laser heat treatment method aiming to form a polycrystalline silicon film having excellent crystallinity, in order to implement a thin film transistor attaining high mobility.
In the thin film transistor disclosed in Japanese Patent Laying-Open No. 2001-345448, the polycrystalline silicon film having the channel region and the source/drain region provided is as thin as 50 nm. Accordingly, the region through which the drain current flows at the time of operation of the thin film transistor is limited within the small-thickness film. Therefore, in the n-type thin film transistor having a gate width of 10 μm, for example, an ON current (the drain current that flows when a voltage of 5V is applied to each of the gate electrode and the drain electrode) of 0.1 mA is merely obtained, which is unsatisfactorily low.
In addition, when the polycrystalline silicon film has a small thickness, a contact hole may be formed in such a manner as to penetrate the polycrystalline silicon film in forming the contact hole in the insulating layer. Here, the source/drain electrode and the polycrystalline silicon film come in contact with each other solely along side surfaces of respective electrodes. Moreover, when the polycrystalline silicon film has a small thickness, a concentration of an impurity in the film cannot be set to a high value if destruction of crystals of the polycrystalline silicon film should be avoided at the time of ion injection. For these reasons, the thin film transistor disclosed in Japanese Patent Laying-Open No. 2001-345448 is disadvantageous in that a contact resistance between the source/drain electrode and the polycrystalline silicon film is increased.
On the other hand, when the polycrystalline silicon film with a large thickness is formed, dangling bonds in the film are increased, although the above-described problem is solved. This will cause another disadvantage of a poorer transistor characteristic. In addition, when the gate insulating film is formed to cover the polycrystalline silicon film, performance in covering the polycrystalline silicon film with the gate insulating film is deteriorated. A desired transistor characteristic cannot be obtained either.


The optical module comprises a device mounted with a photoelectric element and a receptacle to optically connect this device and an optical fiber is provided. The receptacle comprises a device holder at its one end, allows the device holder to be fitted to the top end side of the device, and fixed and held through the interposition of the ultraviolet curing resin. The device holder comprises a window area relatively large in an amount of ultraviolet transmission dispersedly arranged on the entire periphery of the fitted portion with the device.

(1) Field of the Invention
The present invention relates to a technique for connecting an optical element and an optical waveguide, and in particular, to an optical module having a light receiving device and an instrument loaded with an optical fiber.
(2) Description of Related Art
The optical module comprises a light emitting device having a light emitting element or the light receiving device having a light receiving element, and a receptacle loaded with an optical fiber end portion. The light receiving device and the receptacle are fixed with an optical axis aligned. The fixation, for example, is performed by fixing the receptacle and the light receiving device with a holder made of metal by YAG welding and the like (see JP-A-2004-94033).
To prevent a temperature stress by the welding, the holder made of metal and the holder made of metal of the receptacle are required to use the same SUS material, and therefore, the holders are limited regarding the material to be used. Further, the fused material by the YAG welding infiltrates into a gap between both holders, thereby to generate the displacement of an optical position. Hence, to stabilize a weld penetration at the welding period, it is necessary to design the shape, and the method thereof is disclosed in JP-A-2004-94033. However, in the welding fixation method as disclosed in JP-A-2004-94033, there is a limitation regarding the shape/material, and this makes a state that the degree of freedom for design is narrowed.
On the other hand, a method of adhering the light receiving device and the receptacle with an ultraviolet curing resin in place of the YAG welding, is disclosed in JP-A-2002-90587. This method resolves the restriction, and can be configured at a low cost.

Optical module having improved access to ultraviolet curing light


A next line prediction mechanism for predicting a next instruction index to an instruction cache of a computer pipeline, has a latency equal to the cycle time of the instruction cache to maximize the instruction bandwidth out of the instruction cache. The instruction cache outputs a block of instructions with each fetch initiated by a next instruction index provided by the line prediction mechanism. The instructions of the block are processed in parallel for instruction decode and branch prediction to maintain a high rate of instruction flow through the pipeline.

The processing of a single instruction by a computer system is performed in a number of different stages, such as instruction cache fetch, instruction decode and instruction execution. Many modern computer systems utilize an instruction pipeline to increase the speed of processing of an instruction. In a pipelined computer design, the various stages of instruction processing are arranged in series so that each one of the stages can process an instruction independently of the other stages during each cycle of pipeline operation and transmit its processing results to a next succeeding stage in the series for processing in a subsequent cycle. Of course, each stage receives as an input the output of a preceding stage of the series.
In this manner, a computer system does not have to wait for an instruction to be completely processed before fetching and processing a next instruction. For example, if the instruction pipeline comprises three stages, a first instruction that has been processed in previous cycles by each of the first and second stages will be processed in a current cycle by the third stage. During the same cycle, the second stage can process a second instruction that has already been processed by the first stage, and the first stage can process a third instruction, and so on. Pipelining of instructions is a much more efficient method of processing instructions in comparison with waiting for a single instruction to be completely processed before beginning the processing of a second instruction.
In a normal flow of a computer program, it is easy to know which instruction is to enter the pipeline next. In most instances, it is the next sequentially numbered instruction in the program that is to be processed so that, for example, instruction 101 will enter the pipeline in the cycle after instruction 100. An exception to this normal flow of control within a computer program is a branch instruction that instructs the computer system to fetch a next instruction that is out of the normal sequence of the numbered instructions.
For example, instruction 101 may be a conditional branch instruction that instructs the computer system to process instruction 200 if a certain condition is satisfied and to process instruction 102 if the condition is not satisfied. Accordingly, the next instruction to enter the pipeline will not be known until instruction 101 is processed by the execution stage of the pipeline to determine the status of the condition for selection of the next instruction. This results in a "bubble" in the pipeline behind the branch instruction since additional instructions cannot be entered into the pipeline during subsequent cycles until the branch instruction has flowed to the execution stage, which is typically at the end of the pipeline, and the next instruction, 200 or 102, that is to enter the pipeline becomes known.
To minimize bubbles, the prior art has provided branch prediction mechanisms to predict, early in the pipeline, as, for example, at the instruction decode stage, whether a branch will be taken and to fetch the predicted instruction from the instruction cache. Typically, the execution stage includes a device, such as a comparator, to compare each instruction input to the execution stage to the instruction that should be executed. Thus, if the branch prediction mechanism mispredicts the branch, the execution stage comparison will detect the wrong instruction at its input and issue a signal to the branch prediction mechanism to fetch the proper instruction. The pipeline is then backed up to the branch instruction, for processing with the proper branched to instruction following the branch instruction into the pipeline.
As should be understood, the speed up in the operation of the pipeline accomplished by the use of the branch prediction mechanism will be a function of the accuracy of the branch predictions made by the mechanism. However, despite the elimination of the relatively large bubbles for all correct conditional branch predictions, there is a certain amount of latency introduced into the pipeline by the branch prediction mechanism. More specifically, an index to the instruction cache for a next cycle of operation of the computer system pipeline is not available for input to the address input of the instruction cache until the branch prediction mechanism processes a current instruction to determine whether the current instruction is a branch instruction and thereafter to predict whether the branch is to be taken. This can take several cycles of pipeline operation for instruction cache fetch, instruction decode, and branch prediction, before an index for the next instruction is available for input to the address input of the instruction cache to continue pipeline operation.
The reduction in instruction cache bandwidth caused by the latency of the branch prediction mechanism can slow down the speed of operation of the execution stage. In other words, the pipeline might still not be able to deliver instructions to the execution stage as fast as the execution stage is able to process instructions since a small bubble will be introduced into the pipeline after each instruction fetch due to the latency of the branch prediction mechanism. The instruction cache itself can also introduce a latency into the pipeline since an advantageous size for the instruction cache may result in the need for several cycles of pipeline operation just to fetch an instruction.
Ideally, the pipeline should operate to deliver instructions to the execution stage at a rate that enables the execution stage to operate at its maximum speed. The total latency introduced into the pipeline by the instruction cache fetch and branch prediction has become a serious problem as the speed of instruction execution that can be achieved in an execution stage has increased. The execution stage will sit idle during each cycle that an instruction is not available for execution, resulting in a waste of computer resources. For example, if the total latency of instruction cache fetch and branch prediction is six nsec. and the execution stage can execute an instruction in two nsec., the execution stage will sit idle for four nsec. between the delivery of successive instructions.
In an attempt to minimize the branch prediction latency, a next instruction prediction approach has been suggested by the prior art as a partial solution. This is to simply assume a flow through to the next in number instruction for each fetch and to fetch that instruction prior to completion of processing by the branch prediction mechanism so that a next instruction is available for input to the pipeline as soon as possible. In some prior art devices, this is implemented by fetching two instructions at a time.
In other words, the prior art approach always assumes that no branch is taken. The branch prediction mechanism would then do a comparison similar to the comparison done by the execution stage, to determine whether the instruction fetched from the instruction cache in each cycle is the instruction that was predicted by the branch prediction mechanism. Again, the pipeline would be backed up to the branch instruction if the next instruction prediction was incorrect. With this approach, the effect of the latency introduced by the branch prediction mechanism can be overcome, at least for each flow through after a branch instruction. While this scheme keeps the pipeline full for all sequential instructions, no advantage is derived at the instruction fetch stage due to the operation of the branch prediction mechanism further downstream at the instruction decode stage.
Accordingly, the prior art has also suggested building a look-up table, typically an extension to each instruction cache entry indicating whether that instruction is a branch instruction and, if so, what the branch prediction mechanism predicted the last time the instruction was processed through the pipeline. The look-up information can, for example, comprise a pointer to the next instruction.
For each branch instruction, the pointer points either to a flow through instruction, when the branch prediction mechanism last predicted that the branch was not taken or to the branched to instruction, when the branch prediction mechanism last predicted that the branch was taken. For non-branch instructions, the pointer simply points to the next in number instruction (flow through). The look up table is filled by using the branch prediction mechanism output as write data to the look up table.
In this approach, however, the look-up table comprises an extension of the instruction cache. Thus, there is no speed advantage in the look up operation and this scheme does not entirely eliminate the latency introduced into the pipeline by the instruction cache fetch and the branch prediction mechanism. In addition, classical branch prediction in the computer art is typically limited to branch taken and flow through predictions for a conditional branch. Thus, the look up table would not contain information for other types of branches such as a subroutine return instruction. Moreover, the necessity of having an entry in the look-up table corresponding to each instruction in the instruction cache uses an inordinate amount of real estate on the chip or chips used to implement the pipeline.
Accordingly, there is a need for improvement in a scheme for predicting a next instruction index for the instruction cache, prior to completion of branch prediction processing of a previous instruction, so as to obtain an increase in instruction bandwidth sufficient to accommodate the speed of execution of the execution stage.

Next line prediction apparatus for a pipelined computed system


The present invention discloses compounds with a carboxyl acid group and an amide group which also containing the tertiary amino groups. The carboxyl acid group having a partial negative charge can attract the tertiary amino group with each other to form a quaternary ammonium salt structure, so that the compounds are easy to dissolve in water. Moreover, these compounds having a mushroom tyrosinase-inhibition effect and have the potential to use in the cosmetics for skin whitening.

1. Field of the Invention
The present invention is generally related to a compound with a carboxyl acid group and an amide group, and more particularly to a water-soluble compound with a carboxyl acid group and an amide group.
2. Description of the Prior Art
Recently, compounds with carboxyl acid group(s) having skin whitening effect are often applied in cosmetic products. For example, azelaic acid is a common cosmetic raw material and has anti-acne and whitening effect. However, it has poor solubility to cosmetic base materials and this affects skin penetration and thereby results in formulation difficulties.
In order to develop better cosmetic materials, the skin whitening effect and the solubility to cosmetic base materials should be considered simultaneously. Thus, many compounds with carboxyl acid group(s) are synthesized successively. However, their water solubility is still not satisfied while generally commercial whitening products are aqueous solutions. For example, it is not easy to use non-salt solid compound with carboxyl acid group(s) together with an aqueous solution. Therefore, non-salt solid materials have limited application fields and lack of convenience.
In order to resolve such a problem, solid salts become very important in development. For example, the patent WO2006/010590A1 disclosed a compound with carboxyl acid salts, comprising a structure of alpha-amino acid and non-toxic cation, where its water solubility is from ion dissociation. That is, while in use, solid raw materials should dissolve in solvent and then be blended with other cosmetic raw materials. Thus, solid raw materials can not be blended with other materials directly to thereby result in inconvenience.
At present, compounds with carboxyl acid group(s) are still under development since their water solubility is still not satisfied. In view of the above description, a novel water-soluble compound with carboxyl acid group(s) is urgently needed.

Compound with carboxyl acid group and amide group and application thereof


The present invention relates to a method for efficiently performing hierarchical design rules checks (DRC) and layout versus schematic comparison (LVS) on layout areas of an integrated circuit where cells overlap or where a cell and local geometry overlap. With the present invention, a hierarchical tree describes the integrated circuit's layout data including cells having parent-child relationships and including local geometry. The present invention performs efficient layout verification by performing LVS and DRC checking on the new portions of an integrated circuit design and layout areas containing overlapping cells. When instances of cells overlap, the present invention determines the overlap area using predefined data structures that divide each cell into an array of spatial bins. Each bin of a parent is examined to determine if two or more cell instances reside therein or if a cell instance and local geometry reside therein. Once overlap is detected, the areas of the layout data corresponding to the overlap areas are selectively flattened prior to proceeding to DRC and LVS processing. During selective flattening of the overlap areas, the hierarchical tree is traversed from the top cell down through intermediate nodes to the leaf nodes. Each time geometry data is located during the traversal, it is pushes directly to the top cell without being stored in intermediate locations. This provides an effective mechanism for selective flattening.

1. Field of the Invention
The present invention relates to layout verification for an integrated circuit device. More particularly, the present invention relates to a method for improving the process of design rule and layout versus schematic verification for integrated circuit devices.
2. Prior Art
In the design of an integrated circuit, a designer develops a high level language (e.g., VHDL) design and converts this into a netlist using circuit synthesis or logic capture computer implemented programs. The netlist represents logic elements and their interconnections that perform the desired circuit functions outlined in the high level circuit design. Using the netlist, a circuit layout is developed that translates the electrical symbols and connections into primitive geometric patterns ("primitives or geometry") from which transistors or other logic elements are formed and which are to be etched onto the semiconductor device.
The various primitives specify various geometric objects such as boxes, polygons, vias and wires. Cells are defined as either a geometric primitive, such as a single polygon, or as a combination of a plurality of primitives arranged to create a device, such as a transistor or a number of transistors. Since cells are respectively used in the design of an integrated device, it is convenient to identify each cell with a symbolic name that is easily manipulated on a computer. Each instance of this symbolic descriptor used in a circuit is then assembled into a sequence and format suitable for eventual output to a mask-making device or a direct-write-to-silicon semiconductor processing equipment. The sequential stream of symbolic descriptors are typically stored in a data storage device of a computer system and manipulated by computer-based processes to determine where each cell is to be placed on the integrated circuit and the interconnection between the cells. The sequential stream of symbolic descriptors is often called "layout data." One such format for storing and transferring this layout data is the GDSII format (graphic design stream). Layout data can be stored in hierarchical formats where parent cells can incorporate multiple child cells by referencing those cells.
It will be appreciated by one skilled in the art that as cells are assembled in a hierarchical manner by computer-based processes to build subsystems, and as subsystems are interconnected in a hierarchical manner to implement desired circuit functions, it is common for one or more layout design rules to be violated. Design rules specify permissible geometric patterns, minimum resolution, spacing between cells and other constraints of the integrated circuit manufacturing process that need be followed for proper operation of the devices and interconnections formed by the process. Although design rule violations may not necessarily result in a non-functional integrated circuit, production yields may be negatively impacted with a corresponding increase in the cost of manufacture or other circuit problems can result.
Design rule checking procedures (DRCs) and layout versus schematic (LVS) checking are executed on the layout data to determine if any violations exist on an integrated circuit layout design. It is desirable to arrive at a layout design that contains no design rule violations in before the design is committed to silicon or other semiconductor material. The LVS procedures compare the layout data to the actual logic elements of an integrated circuit design's netlist to determine if the layout data actually performs the proper logic functions as specified in the netlist. Violations occur where this mapping is faulty. It is desirable to arrive at a layout design that contains no LVS violations in before the design is committed to silicon or other semiconductor material.
Design rules may be checked either manually or by interpreting the symbolic stream with computer programs once the layout of an integrated circuit is available In the past, DRC and LVS verification required the entire hierarchical representation, often referred to as the hierarchical tree, of the integrated circuit be processed entirely for each layout verification. The data can be processed using a flatten process or a hierarchical process. Under the flatten process, the design is completely flattened into the top level cell so as to remove all hierarchical structure. The flat representation is created by moving the geometry of leaf cells, e.g., those cells at the lowest level of the hierarchical tree, and the geometry of all intermediate cells, upward through the hierarchical structure until all layout data and interconnect information resides at the top level. The flat representation is then run through DRC and LVS checking. Each time an integrated circuit design is modified, it needs to be entirely flattened and entirely re-run through DRC and LVS checking procedures.
Using a hierarchical approach, the process is not entirely flattened but processed according to the hierarchical tree. However, even under this approach, each time an integrated circuit design is modified, it needs to be re-run through DRC and LVS checking procedures. However, performing DRC and LVS checking on a densely populated circuit (as performed by flat DRC programs) is memory and input/output (I/O) intensive and relatively inefficient in terms of computer processing time since each instance of a cell must be checked for conformity with the layout verification rules. In fact, layout verification programs can often take many hours tc perform on high density integrated circuits. It would be advantageous to provide a layout verification system that can operate only on a portion of the design.
One problem with DRC and LVS checkers arises when the processes encounter juxtaposed cells. Overlap of adjacent cells can introduce layout errors not present in either cell prior to the overlap or can remove apparent errors that exist in the absence of the overlap. Early prior art methodologies prohibited overlap as a means to prevent unanticipated parasitic devices from being created by the overlap of cells. But merely prohibiting overlap of cells is not acceptable since circuit design requires that cells overlap to create, for example, full width conductors, inputs and outputs to the cell or to reduce the size of routing resources.
One improved hierarchical method for checking for design rules violations created by overlap areas is disclosed in Exploiting Structure in Integrated Circuit Design Analysis by Martin E, Newell and Daniel T. Fitzpatrick, 1982 Conference on Advanced Research in VLSI, M.I.T., Jan. 26, 1982, p. 84. The disclosed method employs a disjoint transformation to exploit the hierarchical nature of the typical integrated circuit design. The disjoint transformation removes overlapping cell instances by generating new cells from the overlapping area of these cells. The new cells are generated by recursively employing "split" and "gather" procedures. However, this method is inefficient since new must be cells created and design rule checks performed on each of the new cells. Further, the time to perform the disjoint transformation depends in large part on the degree of overlap present in the circuit and is not necessarily correlated with the number of transistors comprising the design.
Recognizing that greater efficiency could be achieved, later design rule checking methods check each cell in its environmental context by first identifying all elements that interact with the cell. On such method is disclosed in The Halo Algorithm--An Algorithm for Hierarchical Design of Rule Checking of VLSI Circuits, Nils Hedenstierna and Kjell O. Jeppson, IEEE Transaction On Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 2, February 1993. This reference discloses a hierarchical checking algorithm where each cell is checked in context of the environment in which the cell is used. One primarily purpose of this algorithm is to solve the problem of where to report a design rule violation (i.e., whether to include violations with the cell description as stored in the database structure or as part of all chip level instances of that cell).
This algorithm first generates a hierarchical tree to describe chip-level instances of cells hierarchically. The tree consists of all paths from the chip level instance to the most primitive cells, often referred to as instances of leaf cells. After generating the hierarchical tree, an inverse layout tree is derived for each leaf cell. The inverse layout tree is derived by treating the leaf cell as the root and taking all paths from the leaf cell to the chip-level. If the circuit design is regular, the inverse layout tree may be simplified to minimize memory requirements and will process faster. However, since multiple inverse trees must be derived, processing time and memory are increased. Further, it is not desirable to build and store inverse layout trees each time the circuit is modified. Inverse hierarchical trees do not represent the natural order in which hierarchical database information is stored in a layout file. Further still, it is not desirable to expend time or system resources in building large intermediate data structures.
Further, the above-described DRC and LVS checking processes are lengthy to perform and must be performed each time the design of the circuit is modified, even if the modification is relatively minor or isolated. Clearly, the prior art processes are inefficient particularly when DRC and LVS processes must be re-run on moderately or only slightly modified layout database information.
Accordingly, it is desirable to provide a method for verifying circuit layout of an integrated circuit, (e.g., performing design rule checks and/or LVS checks) while reducing demand on computer resources and time to complete the verification. The present invention offers the above by allowing layout verification only on a portion of the layout data. Further, it is desirable that the method provide an efficient means for detecting and checking overlapping geometric features to eliminate circuit errors. It is also desirable to perform efficient methods for flattening the layout data in those overlapping areas. The present invention provides the above advantages and other not specifically recited above but clear within the discussions of the present invention presented herein.

Selective flattening in layout areas in computer implemented integrated circuit design


A method of fabricating a belt of capsules comprising: providing a first strip of material, forming a matrix of receptacles in the first strip, depositing a quantity of at least one material in each receptacle, attaching a second strip of material over the first strip to close the receptacles and form a matrix of capsules, and cutting the matrix of capsules into rows to thereby form a plurality of belts of capsules.

It is known to drop incendiaries from aircraft such as helicopters and light fixed wing aircraft for the purposes of forestry management. One known incendiary is in the form of a small sphere having a diameter of approximately 32 mm made from plastics material filled with a quantity of potassium permanganate. The sphere is injection moulded from extruded plastic. The sphere is made initially as two hemispheres one of each is filled with the potassium permanganate. The other half of the sphere is subsequently attached to the first hemisphere. The spheres are subsequently placed in a hopper which feeds them sequentially to a chute where they are injected with a small volume of glycol. This initiates as exothermic reaction generating a flame.
The present inventor developed an alternate form of incendiary described in U.S. Pat. No. 6,877,433 in which the incendiary comprises a plurality of containers coupled together to form a belt which is fed through a dispensing machine. The present invention was motivated by a desire to provide an alternate method of manufacturing the incendiary capsules. However during the course of developing the alternate method it became apparent that the method is generic to the extent that it can be applied to the manufacture of capsule belts per se irrespective of the contents of the capsules which can be varied for the application at hand.


A pipe cutting device for cutting tubing and other cylindrical objects comprises a frame with a handle portion at one end thereof and an upper jaw portion at another end thereof. A cutting roller is rotatably supported in the upper jaw portion. A slide carriage is slidingly mounted on the frame and a power-driven roller is rotatably supported in the slide carriage. The slide carriage with the power-driven roller forms a lower jaw disposed opposite from the upper jaw, and the upper and lower jaws define a cutting space for receiving tubing or other cylindrical objects to be cut. The slide carriage is slid in a direction towards the upper jaw for narrowing the cutting space during a cutting operation. A power motor drives the power-driven roller.

1. Field of the Invention
The invention relates to tube cutting tools, and in particular to pipe cutting devices as generally used in the plumbing art.
2. Description of the Related Art
Tubing cutters of this general kind comprise a clamp with a U-type open end into which the tubing is inserted. One or two rollers support the tubing and bias the same against an oppositely disposed cutting roller. As the device is rotated about the longitudinal axis of the pipe, the cutting roller cuts into the material and thus severs the tubing.
U.S. Pat. No. 5,206,996 to McDaniel describes a tubing cutter with a single cutting roller and two biasing and guide rollers. The tubing is automatically retained within the triangular configuration formed by the two guide rollers and the cutting roller. The biasing force, with which the cutting roller is effectively forced into the tubing material, is provided by a spring.
U.S. Pat. No. 4,305,205 to Girala discloses a self-clamping cutting tool which, in one embodiment, is a power-driven pipe cutter. A cutting head is driven about the pipe axis by means of a power mechanism with a motor and a one-way ratchet mechanism. The device is quite complicated and thus expensive.
None of the prior art hand-held tubing and pipe cutters, except for Girala's, are fully automatic and completely power driven, i.e. they all require a certain amount of manual power application during the cutting operation.


A method for combined computed tomography (CT) imaging and positron emission tomography (PET) imaging uses respiration-gated CT imaging in which the optimal criteria for CT scan gating are determined after the PET scan has been performed. After acquisition of first CT scan image data and PET scan image data with strain gauge levels being recorded, optimal gating criteria are calculated based on the strain gauge levels, and a second CT scan is then performed with triggering in accordance with the optimal gating criteria.

Computed tomography (CT) scanning (i.e., using an external X-ray source) and positron emission tomography (PET) scanning (i.e., using an infused radiopharmaceutical as a source of gamma ray emissions) are well known methods for diagnostic medical imaging. CT scanning employs multiple X-ray images taken in multiple directions to generate a 3-dimensional image or multiple tomographic image "slices." PET scanning employs a gamma-emitting radiopharmaceutical ingested by a patient or injected into a patient. Multiple gamma ray images are taken in multiple directions to generate a 3-dimensional PET image or multiple slices. CT and PET scanning provide different information. For example, CT scanning generally has higher resolution and is superior for providing structural data such as the structure of bones, organs, etc. PET scanning generally has lower resolution but provides more useful information regarding the functional condition of body tissues and systems such as the cardiovascular system. PET is superior for indicating the presence of soft tissue tumors or decreased blood flow to certain organs or areas of the body, for example. The complementary strengths of CT and PET scanning can be provided simultaneously by performing both methods in a single apparatus and imaging session. However, combining CT and PET scanning presents technical challenges because CT and PET require different scan times and have different sensitivities to patient motion.
PET scanning requires a relatively long duration data acquisition period on the order of about 30 minutes for a typical clinically sufficient image. Typically, a large number of PET data acquisitions are acquired at many different angles during this period. Consequently, patient movement is a problem in PET scanning. Excessive motion of a patient can result in scan failure. Thoracic cage movement caused by breathing is a significant problem in PET scanning.
By comparison, CT scanning is relatively fast and can typically be performed during one breath-hold by a patient.
Fusion of CT and PET images often is inaccurate because of inevitable patient movement and breathing. Associated problems include several types of CT artifacts, errors in the association between anatomy and PET uptake, motion blur in PET, and quantitative errors PET errors such as miscalculation of the standard uptake value due to underestimation or overestimation of attenuation.
Part of the solution to these problems is to provide gating of PET and CT scanning based on measurement of certain triggering parameters associated with respiratory motion. In particular, it is known in the art to use a strain gauge to measure the tension in a strap placed around the abdomen or chest of a patient. Signals from the strain gauge are used to develop information that can be used to gate or trigger the operation of imaging apparatus.
The accuracy of such approaches is limited by the fact that patient breathing patterns change over the time period involved in performing the diagnostic scan. This problem is illustrated in the strain gauge traces of FIG. 1. The traces show that deep, irregular breathing at one point in time can be followed by a more regular, shallower breathing pattern ten minutes later. In FIG. 1, the horizontal axis represents time, with a one minute interval between the left and right sides of each plot. The vertical axis represents the signal from the strain gauge, with smaller values corresponding to a more relaxed chest and larger values corresponding to a more expanded chest. Thus, trigger signals based on respiratory cycle alone do not solve the misregistration problem.
Accordingly, there is a need in the art for improved methods for combined CT and PET scanning. It would be particularly beneficial to provide a method for combined CT and PET scanning that can correct for inaccuracies caused by patient motion such as motion caused by respiration.

Registration of computed tomography (CT) and positron emission tomography (PET) image scans with automatic patient motion correction


A golf club head includes a body and at least one light cover. The body includes a striking face for striking golf balls and a crown. At least one recessed portion is defined in the crown and includes a bonding face. The bonding face includes a plurality of regularly arranged holes spaced by a plurality of resilient ribs. The light cover is securely mounted to the recessed portion. The light cover and the holes reduce a weight of the crown of the golf club head and improve a rearward resilient deforming capacity of the striking face. Further, the resilient ribs assure strength of the recessed portion.

1. Field of the Invention
The present invention relates to a golf club head. In particular, the present invention relates to a golf club head with improved striking effect.
2. Description of Related Art
Japanese Patent Publication No. 2003-111874 discloses a golf club head comprising a body with an opening defined in a crown portion thereof. Two carbon fiber plates are respectively bonded to inner and outer sides of the opening. The carbon fiber plates have a specific gravity of about 1.8 g/cm3 and the body has a specific gravity of about 4.5 g/cm3. By means of using the carbon fiber plates to replace a portion of the crown of the body, the center of gravity of the body is shifted downward and rearward for increasing the inertia moment and for improving the striking effect. Due to provision of the opening in the crown of the body, rearward flexibility (or resilient deforming capacity) of the striking face of the body is improved.
U.S. Pat. No. 6,623,378 discloses a golf club head including an opening in a crown portion of the body, with the opening extending toward a toe and a heel of the body. A carbon fiber plate is mounted to the opening to replace metal material in the crown, toe, and heel of the body. Thus, the center of gravity of the golf club head can be adjusted in a wider range while providing the striking face of the body with a greater rearward flexibility.
Although the resilient deforming capacity of the striking face of each of the above-mentioned golf club heads can be increased, the opening in the crown is without support, resulting in a weak structure in the crown. When the striking face is subjected to a relatively large striking momentum and thus has a relatively large rearward deformation, the carbon fiber plate is compressed and thus breaks. Further, even though the striking face is not subjected to a relatively large striking momentum, repeated deformation of the crown of the body adversely affects the bonding strength and bonding reliability between the opening and the striking plate after a long-term use of the golf club head.

Golf club head with improved striking effect


In one example in accordance with the present disclosure, a system for handling memory errors includes a memory module having volatile components and non-volatile components. The system includes a BIOS chip having BIOS code and a BIOS non-volatile (NV) memory. The BIOS NV memory stores error data associated with the memory module that was stored prior to a power-on or reset of the system. The system includes a processor to execute the BIOS code to, after the power-on or reset of the system end before an operating system is loaded; (1) read, from the BIOS NV memory, the error data; and (2) determine, based on the error data, whether to take a corrective action with respect to the memory module.

Non-volatile (NV) DIMMs (dual in-line memory modules) are a technology that includes both volatile memory components (e.g., DRAM devices) and non-volatile memory components (e.g., Nand Flash). These NV DIMMs possess characteristics of both volatile memory devices and nonvolatile memory devices. Data in volatile memory components of an NV DIMM is copied to the non-volatile components in various situations when power is lost to the memory module. Thus, overall, the data contained in these NV DIMMs is persistent and will be preserved following a power loss, power cycles and system resets.

Handling memory errors in memory modules that include volatile and non-volatile components

Hewlett Packard Enterprise Development LP


A backlight unit according to various embodiments of the disclosure may include a light source, a light guide plate configured to guide light emitted from the light source and disposed to face in a first direction, and an optical film disposed over the light guide plate. The optical film may include a first prism sheet including first prism structures arranged side by side to each other along a second direction perpendicular to the first direction, and a second prism sheet disposed over the first prism sheet and including second prism structures arranged side by side to each other along a third direction forming an acute angle with the second direction.

In general, a liquid crystal display (LCD) may include a backlight unit configured to evenly emit light across the entire screen of an electronic device. the backlight unit may include a light source, a light guide plate, a diffusion sheet, and an optical film. Light emitted from the light source may be transferred to the upper portion through the light guide plate, and the light transferred to the upper portion may be diffused through the diffusion sheet and then transferred to the liquid crystal panel through the optical film provided on the upper portion. In some cases, the backlight unit may further include an additional diffusion sheet on the upper portion of the optical film. A conventional optical film may have multiple diffusion and light-collecting sheets laminated such that the point light source of the light source is changed to a surface light surface.
Recently developed display panels tend to become thinner, and backlights thus need to be manufactured flat. There has been ongoing development for removing the diffusion sheet, which has a relatively large thickness, from the backlight unit. However, if the diffusion sheet is removed simply to reduce the thickness of the backlight unit, resulting irregular luminance may pose a problem of reliability, and insufficient diffusion may pose a problem of narrow field of views. Accordingly, there is a need to develop a structure capable of sufficiently compensating for the luminance and the field of view while guaranteeing a flat backlight unit.

Optical film and backlight unit including the same


The reading head having the capability of processing two different data cards of the inductive type and chip-cards provided with contact pads on their surface. The raising and lowering of connection pins which contacting the pads is achieved by linking the pin supporting plate to rocking C-shaped driving arms having bifurcated free upper ends slidingly coupled to pivots which are attached to the plate. The lower limbs of the arms extend parallel to the lower face of the upper part of the reading head, the limbs having bosses facing the lower face, the gap between the bosses and the face being roughly equal to the thickness of an inductive card. The greater thickness of a chip-card presses down the bosses bringing about a clockwise rotation of the C-shaped arms around a fixed shaft resulting in a lowering of the connection pins which touch the contact pads on the card surface.

The present invention refers to devices capable of statically processing, indifferently, elements bearing data by means of inductive cells of the type described in patent document PI (BR) 7804885 and PI (BR) 9201380, as well as chip-cards using contacts. More specifically, the present invention concerns the modifications introduced into the lifting and lowering mechanism of the eletric contact pins of the static reading head which engage the contact pads provided on the surface of the chip-cards, simplifying said mechanism and making it easier to withdraw the card after its use.
A reading head capable of carrying out the processing of two types of cards is shown in FIG. 1 of the present application having been already described in patent document PI (BR) 9404627-1. In this known reading head, the fitting-in of cards having different thicknesses is achieved by means of a lifting and lowering mechanism of the magnetic plate 142. Said mechanism comprises frames 84, 85, tabs 93, 94, directional retainer 86 and stop rod 88. The vertical movement of block 161 to which contact pins 162 are attached is provided by the above mentioned elements associated with brackets 150 and 152 which move simultaneously with frames 84 and 85. Said pins provide the electrical connection with contact pads on the chip-card surface (not shown).
The reading head shown in FIG. 1 exhibits, however, some disadvantages, such as a relatively high cost resulting from the complexity of the lifting device. Moreover, the fact that said lifting and lowering motions are provided by the combined action of mutually sliding mechanical parts brings about an accelerated wear of the contacting surfaces, thus impairing the operation of the device in the long run. Furthermore, the lifting of the magnetic plate and contact pin supporting block 161 occur simultaneously by employing the user's card pulling effort, so as to overcome the combined resistance of the springs which provide the lowering of said elements and the friction of the sliding surfaces. This demands a substantial effort from the user; pulling strength values higher than 5 N have been measured in field tests.
Additionally, the known device does not discriminate between (thicker) chip-cards and (thinner) inductive cards which results in the lowering of contact pins 162 every lime any card is inserted into the reading head, hasteninig the mechanical wear of the parts associated with said movement.
Considering the foregoing, the present invention aims to reduce the complexity of the reading device, without sacrificing its performance.
A further aim is to decrease the mechanical wear by means which discriminate between the thinner inductive cards and the thicker chip-cards so as to have the contact pins moving only when chip-cards are inserted into the reading head.


A device having an air bearing surface and a method of forming the device are disclosed. The device can include a writer portion including a surface at the air bearing surface of the device, a magnetic adhesion layer disposed proximate at least a portion of the surface of the writer portion, and an overcoat disposed proximate at least a portion of the magnetic adhesion layer such that the magnetic adhesion layer is between the at least a portion of the surface of the writer portion and the overcoat.

Disc drive systems can be used for storage of digital information that can be recorded on concentric tracks of a magnetic disc medium. Several discs are rotatably mounted on a spindle, and the information, which can be stored in the form of magnetic transitions within the discs using a writer, is accessed using a reader. The reader and/or writer is carried by a slider that is located on an actuator arm that moves radially over the surface of the disc. The slider and transducer can be collectively referred to as a magnetic head.
The discs can be rotated at high speeds during operation. As the discs are spun, the slider and the reader and/or writer glide above the surface of the disc on a small cushion of air. Upon reaching a predetermined high rotational speed, the head floats in air at a predetermined distance from the surface of the disc where it is maintained during reading and recording operations. To maximize this high areal recording density, the flying height (i.e., the distance between the head and the surface of the disc as the head floats above the surface) can be minimized.
One or both of the air bearing surfaces of the head and the disc can be coated with a diamond like carbon (DLC) protective overcoat and/or a lubricant layer. The function of the DLC overcoat is to protect underlying metals and alloys from wear and corrosion during the manufacturing process and throughout the lifetime of the disc drive system. As applied to the head, the DLC overcoat can include a DLC overcoat and an adhesion layer. DLC overcoat thickness for the head can range from about 10 to 20 angstroms, while typical values of DLC overcoats for magnetic media can be in excess of 20 Angstroms. DLC overcoat thicknesses is one of the biggest contributors to head media separation (HMS) distance. The HMS distance is measured from the magnetic surface of the head to the magnetic surface of the media. The HMS distance in turn affects the data reading and writing efficiency of the transducer.

Magnetic adhesion layer and method of forming same


This is a method of manufacture of a shallow trench isolation semiconductor device with STI trenches where an active area mask is provided for exposure of an active area during manufacture of the device comprises several following steps. The STI trenches are filled by coating the device with a blanket coating of silicon oxide. Coat the device with negative resist. Next, expose the negative resist layer with the active area mask for the device providing windows through the negative photoresist layer with an level of exposure energy provided to broaden the dimensions of exposure substantially laterally of the active area mask. Then, etch back the silicon oxide layer to a thin layer below the windows through the negative photoresist layer. Strip the resist. Finally, perform chemical mechanical planarization to remove excess silicon oxide from the surface.

1. Field of the Invention
This invention relates to the process of manufacture of semiconductor devices which employ Shallow Trench Isolation (STI) and more particularly to use of negative photoresist and CMP for shallow trench isolation.
2. Description of Related Art
U.S. Pat. No. 5,350,486 of Huang for a "Semiconductor Planarization Process" shows a method of planarization using a photoresist (PR) layer to etch oxide from an oxide layer located over active areas. The method includes the steps of selectively etching portions of a glass structure that overlies portions of the oxide layer that have higher elevations than other portions of the oxide layer, and then etching the glass layer overall. The etching step includes forming a photoresist layer over the glass layer. A positive or negative photoresist layer is formed by exposing selected areas of the photoresist layer in areas over those portions of the oxide layer that have higher elevations than other portions of the oxide layer. As a result, the exposed areas of the photoresist layer are removed to form a set of windows therethrough thereby converting the photoresist layer into a photoresist layer. Then the glass layer is etched where it is exposed through those through the windows in photoresist layer. The master mask used in patterning the photoresist layer can be the same mask, or its negative, that is used in forming the metallization layer over which the oxide and glass layers have been formed. If the negative of the master mask is used then a positive photoresist layer is used. If the same master mask is used, then a reverse tone photoresist layer is used.
U.S. Pat. No. 5,691,215 of Dai et al. for "Method for Fabricating a Sub-Half Micron Device with Insulator Filled Shallow Trenches Planarized Via Use of Negative Photoresist and De-Focus Exposure" shows a process featuring smoothing the topography that exists after the insulator filling of narrow and shallow trenches, by creating photoresist plugs, only in the depressed topography regions. This is accomplished using a negative photoresist layer, a de-focus exposure, and the identical mask used to create the shallow trench pattern in a positive photoresist layer. A RIE (Reactive Ion Etching) procedure, with a 1:1 etching selectivity, is used to complete the planarization process. However, this patent does not show the invention's next CMP step.
U.S. Pat. No. 5,641,704 of Paoli et al. for "Method of Isolating Active Areas of a Semiconductor Substrate by Shallow Trenches and Narrow Trenches" teaches an isolation planarization using a negative mask before an etch back and CMP. However, Paloi teaches CMP but does not teach the Negative photoresist (PR) of the invention. See col. 5, lines 41-44.
U.S. Pat. No. 5,494,857 of Cooperman et al. for "Chemical Mechanical Planarization in Semiconductor Substrates" teaches an isolation planarization using a negative mask before an etch back and Chemical Mechanical Planarization (CMP).

Manufacture of a shallow trench isolation device by exposing negative photoresist to increased exposure energy and chemical mechanical planarization

Vanguard International Semiconductor Corporation


A method and system for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks, or with other two-mask lithographic processes employing a trim mask. The method and system comprises locating regions in a finished semiconductor design that do not contain as-designed shapes. The method and system generates dummy fill shapes in the regions at a predetermined final density and sizes the generated dummy shapes so that their local density is increased to a predetermined value. The method and system further creates corresponding trim shapes that act to expose an oversized portion of the dummy shape, effectively trimming each dummy shape back to the predetermined final density. The method and system can be implemented on a computer program product comprising a computer useable medium including a computer readable program.

Phase shift mask technology allows for much smaller features to be resolved for a given illumination wavelength than conventional Chrome-On-Glass or Attenuated Phase Shift methods. Typically small features are resolved by exposing the spaces on either side through alternating 0-degree and 180-degree phase-shifted openings on a phase mask. The ends of these fine features are normally trimmed by exposure through a second block mask, since it is 0-degree and 180-degree shapes are not normally allowed to touch one another. Large features that could be easily resolved without resorting to alternating phase shift methods are normally rendered by the block mask alone.
For polysilicon gate applications, these large features normally include large decoupling capacitors and dummy fill shapes, among others. Within macros containing a large number of critical gates, the local density of 0-degree and 180-degree shapes (openings in an otherwise opaque mask) is normally about 40-65%, while the density of block shapes (opaque regions in an otherwise clear mask) is normally 70-90%. In other regions of a design, such as otherwise-empty areas containing only dummy fill shapes, the local density of 0-degree and 180-degree shapes is nearly zero, and the density of block shapes is typically 25%. In peripheral areas containing mostly large decoupling capacitors, the 0-degree and 180-degree local density is nearly zero, and the density of block shapes is about 60-75%.
On technology development testsites, there are often companion chiplets surrounding a central product or product-like chip. For these companion chiplets, the local density of 0-degree and 180-degree shapes is very often also nearly zero, and the local density of block shapes, mostly dummy fill, is approximately 25%. As a result, the local density of 0-degree and 180-degree phase shapes varies widely across the phase shift reticle, particularly on large length scales (1 mm or larger). Similarly, the local density of block shapes varies widely across the block reticle, particularly on large length scales. Variations in the local density of shapes are known to have an adverse effect on the dimensional control of features on those masks, and these non-uniformities have been demonstrated to exhibit a strong adverse effect on the manufacturing mask bias for both phase and block reticles. Similar manufacturing difficulties arising from non-uniform density of shapes can adversely affect masks used in other two-mask lithographic processes incorporating an auxiliary trim mask, used for example to create closely-space line ends in an SRAM or other memory array.
Known solutions include a two-pass methodology for mask manufacture, wherein oversized features are trimmed in a second pass through the mask writer. This approach increases the cost and turnaround-time for the masks, has the potential to increase the defect density on those masks, and is inherently a one-way process only. That is, features that were rendered too large can be trimmed, but features that were originally rendered too small cannot be readily adjusted.

Structure and method for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks

International Business Machines Corporation


The invention is directed to a method of highly purifying a polypeptide or other biological compounds from a contaminant by crystallization comprising contacting a mixture containing uncrystallized polypeptides and a contaminant with an exogenous nucleating agent, crystallizing the polypeptides, thereby forming at least one crystal of the polypeptide attached to the nucleating agent, the attached crystal being of a high purity, and at least one polypeptide crystal unattached to the nucleating agent, the unattached crystal being of a lower purity than the attached crystal, and separating the crystal attached to the nucleating agent from the crystal unattached to the nucleating agent. Also, the invention is directed to a method of purifying a polypeptide in a high purity and in a high yield from a contaminant by crystallization comprising contacting a mixture containing uncrystallized polypeptides and a contaminant with an exogenous nucleating agent that has a close lattice match to the polypeptide, crystallizing the polypeptides, thereby forming at least one crystal of the polypeptide attached to the nucleating agent, the attached crystal being of a high purity and produced in a high yield, and at least one crystal unattached to the nucleating agent, the unattached crystal being of a lower purity than the attached crystal, and separating the crystal attached to the nucleating agent from the crystal unattached to the nucleating agent. The invention is also directed to compositions comprising highly purified polypeptide or biological compound crystals and compositions of highly purified polypeptides or biological compounds.

1. Field of the Invention
This invention relates generally to a method of purifying biological compounds or molecules, such as polypeptides, by crystallization. More particularly, the compounds can be purified to a significantly higher degree of purity than previously available techniques. In another embodiment, the present invention relates to crystallizing biological compounds on nucleating agents with a close lattice match to the crystalline lattice of the biological compound to selectively obtain biological compound crystals of high purity in a high yield.
2. Background Art
Crystallization of biological compounds, such as polypeptides, is important, both as one of the final separation or purification steps in bioprocessing and for growing crystals for basic scientific studies, such as structural analysis by X-ray diffraction. For example, improvements in protein purity are important to achieve more therapeutically acceptable proteins for drug use and for facilitating or even permitting the study of proteins by, for example, X-ray diffraction for rational drug design. Traditional methods for crystallizing proteins (herein after referred to as polypeptides), such as by spontaneous crystallization wherein no nucleation agent is used, have resulted in high failure rates and high heterogeneity of any resulting crystals. The present invention provides techniques for obtaining biological compound crystals in higher purity than previously attained, or in a combination of a high purity in a high yield never before attainable, based on their attachment to an exogenous nucleating agent.
This invention, therefore, represents a new method of growing biological compound crystals, such as polypeptide crystals, of high purity, and solves a need in the art for producing crystals of high purity, and in one embodiment, in a high purity and in a high yield.

Crystallization and purification of polypeptides


An exemplary system may allow new devices to be added. In one embodiment, upon receiving information associated with a device event, the system generates a first rule for a device based on the information and a system state. The system determines determine an updated system state based on the first rule. The system determines whether a second rule is required for the updated system state. Upon determining that the second rule is required for the updated system state, the system generates the second rule.

Most modern computing systems allow users to add one or more devices. The devices added can be physical hardware devices, such as storage media, or virtual devices, such as virtual storage media for a virtual machine. However, the rules for adding devices can be very strict.
When a device is connected to the computing system, an interrupt is injected into the computing system and the computing system can determine a type of the device. The computing system can determine whether one or more general rules exist on the computing system for that type of device. The general rule can include information about one or more actions for the computing system to perform when a device of the corresponding type is added. If a general rule for the type of device exists on the computing system, the device can be successfully added to the system and the general rule for the type of device can be applied to the device. If a general rule for the type of device does not exist on the computing system or if the type of device is unknown, the device may not be added to the system and an error message can be generated. For example, if storage disk A is added to a computing system, a determination is made of whether a rule for storage disks exists on the computing system. If a general rule for storage disks exists on the computing system, storage disk A is added to the computing system and the general rule for storage disks is applied. If a general rule for storage disks does not exist on the computing system, storage disk A is not added to the computing system.

Manipulating rules for adding new devices


A system is described for determining the active copresence of users during interactions. The system may include a processor, a memory, and an interface. The memory may store a degree of active copresence. The interface may communicate with a user. The processor may identify a primary interaction of the user. The processor may determine whether the user engages in a secondary interaction while the user is engaged in the primary interaction. The processor may determine the degree of active copresence of the user during the primary interaction based on a quality score of the primary interaction and a quality score of the secondary interaction. The degree of active copresence may represent the level of engagement of the user during the primary interaction. The processor may provide the degree of active copresence to the user via the interface.

The advancement of mobile devices, such as mobile phones, has allowed users to be accessible to non-present individuals from virtually anywhere at anytime. For example, a user of a mobile phone may be accessible to non-present individuals via emails, phone calls, text messages, instant messages, twitters, or generally any form of network communication. The pervasiveness of mobile communications with non-present individuals may be interfering with a user's interactions with present individuals.

System for determining active copresence of users during interactions