Machine learning on user equipment candidate locations provides more accurate location estimation in timing-based location estimation. For instance, timing signals from a user equipment are collected, and adjusted using calibration data, previously known for pairs of fixed-located cells. The adjusted timing data are processed into a location candidate dataset. The location candidate data set is iteratively processed using machine learning technology to eliminate candidate locations until an estimated location is determinable. The location estimation via the described technology is significantly more accurate than other timing-based methods.

In wireless communications networks, some mobile devices (user equipments) are equipped with Global Positioning Systems (GPS) or other, generally software-based location determination mechanisms. However, many mobile devices do not have such location determination mechanisms. Other times, mobile devices do not have the power or capability for accurate GPS signal reception, such as when a clear view of satellites is not available, which can occur indoors, in "urban canyons" and in other such situations.
As a result, location determination of a mobile device often relies on timing-based location methods. When a mobile device (user equipment) is asked for a timing-based location result by a network device, the network device relies on the timing data that the user equipment returns and the base stations' (cellular radio) locations from which the user equipment receives timing signals. This process takes the timing data and normally returns a location (latitude, longitude and possibly an altitude) and an accuracy uncertainty. This uncertainty translates into an accuracy level that represents the radius of uncertainty of the locate.
One example of a timing based location method is (Observed Time Difference Of Arrival), which uses Relative Signal Time Differences (RSTDs) reported by mobile devices. A recent study showed that the standard accuracy from the OTDOA method had a median value averaging sixty meters. This accuracy is not sufficient for many commercial scenarios (e.g. advertising/geo-fencing) or internal (e.g., small cell placement) use scenarios.

Refining and selecting timing data to increase accuracy of timing-based location for user equipment


The invention provides recombinant ethanologenic bacteria, methods of making the bacteria and methods of producing ethanol using the bacteria.

Lignocellulosic biomass represents a renewable source of carbohydrate for biological conversion into fuels and chemicals and, as such, presents an attractive alternative to petroleum-based technology (Arntzen and Dale, 1999). It is recognized, however, that to reach its full potential, commodity production of ethanol from biomass will require high rates and efficiencies, simple processes, and inexpensive media (Ingram et al. 1998; Zhang & Greasham 1999).
Bacteria such as Escherichia coli have the native ability to metabolize all sugar constituents contained in lignocellulose.
To realize fully the potential of recombinant ethanologenic bacterial strains to serve as a source of ethanol, there is a need for new and improved strains of such bacteria that can efficiently produce ethanol.

Recombinant ethanologenic bacteria comprising a urease gene


A universal computer for a vehicle, comprising a microprocessor for the processing of control programs, a storage unit, for the data thus calculated and an interface which permits a connection of the computer to a databus in the vehicle. The computer comprises control programs for controlling device provided in the vehicle, whereby the control commands are transmitted to the device to be controlled via device interfaces. The computer also comprises reconfigurable hardware, which permits a retroactive reconfiguration of peripheral components or an interface in the assembled state of the computer. A transmission of an algorithm for reconfiguration of the hardware is provided to the storage unit on the vehicle, so that a process for reconfiguration of the hardware associated with the peripheral components or the interface may be carried out.

This application claims the priority of German patent document 101 39 610.4, filed 11 Aug. 2001 (PCT International Application No. PCT/EP02/06251), filed Jun. 7, 2002 the disclosure of which is expressly incorporated by reference herein.
The invention relates to a universal computer for vehicle, having a microprocessor for processing control programs, a storage means for the data which is calculated in the process, and an interface which permits the computer to be connected to a vehicle data bus. The computer has control programs for controlling vehicle devices and device interfaces that transmit control instructions to the devices that are to be controlled.
German patent document DE 197 48 536 C2 discloses a computer for a vehicle, which is provided with a microprocessor, various storage means and an interface which permits connection to a CAN bus. Such control devices ordinarily also have interfaces via which various devices, such as a mobile telephone or a navigation device, can be coupled.
A disadvantage of the conventional control devices is that the computers remain installed in the vehicle during its entire service life, so that the hardware of the computers is predefined. Subsequent exchange of the hardware in a vehicle which is in use cannot be carried out in contemporary network systems (with up to 60 computers in a vehicle), due to the high degree of expenditure on configuration. As a result, hitherto all that has been considered is to exchange various software modules during the service life of the vehicle so that the software is adapted to changing in conditions.
It is then necessary also to configure parts of the hardware in a way which can be flexibly adapted. In particular in the telecommunications market (for example in the case of mobile telephones), the design of the housings and interfaces are changed frequently. Thus, it is virtually impossible to subsequently connect a relatively modern mobile telephone to a control device in the vehicle.
German patent document DE 197 50 662 A1 discloses a processor unit for a data processing protected electronic control system in a motor vehicle, in which the computer is a scaleable arithmetic unit (i.e., a piece of hardware which is designed to meet the power requirements with different processor power); and depending on the demands, it can be replaced with a faster or slower microprocessor. If a relatively high processor power is called for, the microprocessor can then be replaced by a more powerful one, it being possible to plug the scaleable processor into the same processor connector. However, the hardware is replaced in its entirety, which is possible if the control devices are opened, the hardware exchanged and the software programs correspondingly input.
Reconfigurable hardware in the form of field programmable gate arrays (FPGA) are disclosed, for example, in U.S. Pat. Nos. 5,457,410 and 6,014,509, and in International Patent Document WO 95/28769. These FPGAs have memory cells such as flip flops which can also change their function after manufacture. The memory cells are freely configurable with one another, electrically conductive connections being newly wired so that diverse logical circuits can be established. By means of such FPGAs it is possible to simulate logic circuits and in particular to construct electrical filters, or they can be used simply as storage means.
An article in Elektronik [Electronics] July 1998, page 38, entitled "Mit programmierbarer Logik verheiratet [Wedded to programmable logic]" discloses that an FPGA field is provided as reprogrammable hardware in order to perform complex computing tasks.
European Patent Document EP 801 351 A2 discloses a microprocessor with interface modules which have FPGAs. The use of FPGAs makes it possible to reconfigure these interface modules to adapt to different components.
One object of the present invention is to provide a universal computer for a vehicle, which is suitable for use with a data bus and other control devices, can be adjusted within the vehicle without changing the hardware, to new interface requirements or subsequently interchangeable devices, and at the same time provides a specific storage region of the algorithm for configuring the hardware.
This and other objects and advantages are achieved by the computer according to the invention, which has transmission means that transmit an algorithm for reconfiguring the hardware to the storage means in the vehicle so that the hardware which relates to the peripheral components or the interface can be reconfigured. A storage control means is provided which automatically transmits the algorithm for reconfiguring the hardware to the storage means in the vehicle, and a memory is provided in which a plurality of data pages for configuring the hardware are stored. Only one of these data pages is classified as valid as in the present device configuration, and the storage control means retrieves the applicable data pages in accordance with the configuration.
According to the present invention, the computer is installed in the vehicle in the form of a control device when the vehicle is manufactured. Together with other control devices, it forms a network within the vehicle. The various control devices can communicate with one another via the data bus, and control programs are provided for actuating, via device interfaces, devices which can be coupled to the network.
According to the invention reconfigurable hardware is used, which can be reconfigured by downloading an algorithm, even years after the vehicle has been delivered to the customer. The algorithm may be a hardware description language which describes the configuration of the respective hardware. Such reconfigurable hardware is used in particular in all interfaces and peripheral components which are frequently affected by hardware changes. "Peripheral components" is understood to mean interrupt controllers, logic modules and circuits as well as filters and output stage actuation circuits, which control devices which are connected. In addition, these include interface drivers, addressing components, devices for actuating data buses or logic units for controlling storage. The microcomputer itself can also be simulated by an FPGA module.
For example, a central vehicle display is arranged in the interior of the vehicle and can be actuated by means of a control device. Various telematics devices (for example a mobile telephone, a navigation system or various audio or video devices) are connected to the vehicle network via a device interface. If an additional device is then connected to the network or a control device or a relatively old device is replaced with a device according to a new standard, on the one hand the necessary driver software is transmitted from the outside to a storage means in the computer using a transmission means. However, on the other hand, the wiring between the device interface and the computer can also be changed by the reconfigurable hardware using an algorithm for reconfiguring the hardware so that it is unnecessary to exchange the entire device interface, as is customary, but rather the hardware can be reconfigured. Furthermore, various digital filters and logic circuits can be reconfigured or newly connected by virtue of the fact that an algorithm for reconfiguring a service center is transmitted to the storage means of the computer.
In this way, a plurality of configuration algorithms for the FPGA can be stored in a storage area of the computer, and the FPGA module is configured by the storage control means by means of a memory access. The storage control means can then access the currently applicable data page at the same memory address, and configures the FPGA hardware correspondingly. In a memory addressing area in the memory, the currently applicable data page is respectively superimposed on the other pages which could be used as an alternative for configuring the hardware, but are not currently required owing to the existing device circuitry.
The advantage of this new universal computer architecture is that specific hardware elements can be reconfigured so that standard logic elements and their wiring can be changed or subsequently rewired. In this way, in future, hardware will no longer need to be exchanged if new devices are retrofitted in the vehicle; rather the hardware can be correspondingly adapted by means of an algorithm for reconfiguring the hardware. In this way, it is not necessary to provide new hardware whenever a device is changed, because it can be adapted by means of the reconfigurable hardware when new devices are used. On the other hand, it is also possible to adapt the long-life computer architecture which is present in the vehicle to new conditions by reconfiguring its functionality.
The reconfigurable hardware preferably has freely connectable memory cells with reconfigurable electrical connections which can be subsequently newly connected in accordance with the algorithm for reconfiguring the hardware in the installed state of the vehicle. The reconfigurable hardware may be a FPGA that is either ROM-based (in which case information is retained when the power fails and the hardware can be changed by means of ultraviolet light or electronic processes) or RAM-based (whose information is lost when the power fails). Such FPGAs can be appropriately reprogrammed by means of an algorithm, for example a set of instructions for programming digital logic functions. FPGAs can also be used as state machines. Here, the signals assume various, permanently predefined states such as are also implemented today in means of transportation in the form of state machines.
In one preferred embodiment of the invention, the microprocessor of the computer has standard cell blocks (SCB), and is constructed from various predefined logic blocks, so that logic components from various electronic manufacturers can be combined in one microprocessor and implemented in the form of what is referred to as a user specific module (ASIC). The invention then combines advantages of a standard cell block microprocessor core with reprogrammable hardware, and it is possible to transmit the software and algorithms for reconfiguring the hardware to a storage means of the computer over a wire-free interface. Using the information which is transmitted from a service center over the wire-free interface, it is then possible to reconfigure the universal computer in terms of hardware in accordance with the algorithms and thus adapt it to new external devices or further hardware requirements.
In another embodiment of the invention, a storage control means is provided which, without affecting the processor time of the microprocessor, transmits the algorithm for reconfiguring the hardware to the storage means in the means of transportation automatically. If necessary, when triggered by a service center or the microprocessor, the storage control means can request transmission of the algorithms for the reconfiguration of the hardware and then store the result data in what is referred to as a flash memory, for example. The wire-free interface via which the data can be transmitted to the computer may be implemented, for example, in a GSM Standard or according to the Bluetooth Standard. The storage control means according to the present invention thus relieves the loading on the computer which is occupied with control programs when it is operating, and transmits the algorithms for reconfiguring the hardware into a flash memory independently of the microprocessor. A flash memory is suitable for long-term storage of data which can be transmitted from a service center to the means of transportation. By transmitting the reconfiguration algorithms over a wireless interface and reading in the data as well as algorithms into the flash memory, a highly flexible and effective computer architecture is produced which permits later reconfiguration of the hardware.
As the microcomputer is preferably composed of standard cell blocks, the hardware structures can be modularized and also easily transferred to reconfigurable hardware (FPGA). Such standard cell blocks are then eliminated from the microcomputer hardware and programmed in the form of FPGAs by means of the reconfiguring algorithms. The standard cell blocks can, however, also be provided within the microprocessor which can then be wired in a variable fashion to a device interface via the reconfigurable hardware. On the other hand, the reconfigurable hardware can also be arranged as a peripheral device next to the microprocessor and can carry out the wiring and the processing of the electrical signals.
The storage control means can be responsible not only for the control of data transmission but also for data protection. All the data which is transmitted to the computer via the interfaces (for example the device interfaces or the interface for transmitting the algorithm for reconfiguration) can, for this purpose, run via the storage control means. The storage control means then checks a specific enabling number or private and public keys according to an encryption method, and the data (i.e., the algorithm for reconfiguring the hardware) cannot be transmitted to the computer until there is a positive check. If an algorithm is to be transmitted from an external service center or from a device which is coupled to the device interface to the computer, first a request for the transmission of the reconfiguration data may be necessary.
In addition, after the microprocessor has been powered up, an enable signal to the storage control means may be necessary in order to signal that the system is ready for an external data transmission, and the storage control means can independently carry out the transmission of an algorithm to the flash memory or to an overlay memory. It is possible to provide a state in which an external transmission of hardware algorithms is completely prohibited.
If, for example, hardware configuration data are stored in a specific memory area of a memory, it is possible to provide that all such data can be retrieved at the same address, with only one of the memory pages (representing the present hardware configuration for a device which is connected) being active. The other data pages may provide algorithms in the form of a hardware configuration language if another device is to be connected. Then, only one of the previously inactive memory pages is activated, as a result of which the hardware configuration for the new device is automatically set. The reconfigurable module is automatically rewired by the hardware description language with respect to the connections between the individual memory cells, and wired differently with respect to the memory cells. As a result, for example, the interface is configured with a new pin to pin connection.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.


A drive force transmission device has an outer clutch plate and an inner clutch plate, which are rotatable relative to each other about a common rotational axis. The inner and outer clutch plates become frictionally engaged with each other with lubricant oil provided in between. The outer and inner clutch plates each have a sliding surface. The sliding surfaces face each other. A diamond-like carbon film is formed on the sliding surface of the outer clutch plate. Fine grooves are formed in the sliding surface of the inner clutch plate. The proportion of the sliding area to the sliding surface of the inner clutch plate at the initial stage of use is 55 to 90%.

The present invention relates to a drive force transmission device that transmits drive force through frictional engagement between drive force transmitting members that are coaxially arranged in a manner rotatable relative to each other.
To improve performance, a drive force transmission device may typically include a plurality of fine grooves formed in a sliding surface of a drive force transmitting member. For example, as described in Japanese Laid-Open Patent Publication No. 2005-36863, a plurality of fine grooves are formed in a sliding surface of one of a drive clutch plate and a driven clutch plate, which form a drive force transmitting member of a drive force transmission device. The grooves extend in parallel with one another in the circumferential direction of the sliding surface. The grooves maintain an appropriate thickness of an oil film formed between the opposing sliding surfaces of the drive and driven clutch plates. In this manner, the sliding surfaces exhibit μ-v characteristics of high friction and positive gradient, which indicates that the friction coefficient μ increases as the sliding speed v increases. Accordingly, the drive force transmission device reliably obtains desired drive force transmission characteristics with improved anti-judder properties.
The sliding surfaces of the drive force transmission device must maintain the desired drive force transmission characteristics even after a certain period of use, or an assumed length of life of the drive force transmission device. Specifically, regardless of wear of the sliding surfaces caused by long-term use, the shape of each of the fine grooves must be maintained in an appropriate state, or an oil film formed between the sliding surfaces must be maintained in a desired state. It is thus ideal that such fine grooves are formed to have rectangular cross-sectional shapes. However, since the fine grooves of such shapes are difficult to form, typical fine grooves have substantially triangular cross-sectional shapes. In other words, the width of each fine groove decreases from the opening end of the groove toward the bottom. If the fine grooves are formed through cutting as in the case of the aforementioned document, the triangular cross-sectional shape of each fine groove becomes more acute. Thus, as the sliding surfaces become worn due to the long-term use, the width of each groove becomes gradually smaller, changing the drive force transmission characteristics. To avoid this problem, each fine groove is formed initially with an increased width at an opening end and an increased depth, in such a manner that a sufficient groove width is maintained regardless of the wear of the sliding surfaces. Therefore, in a typical drive force transmission device, the sliding area (corresponding to the portions other than those corresponding to the grooves) of the sliding surface in which the fine grooves are formed is approximately 50% or smaller of the total area of the sliding surface at the initial stage of use.
However, if each fine groove has an increased width at the opening end, the sliding area of the sliding surface becomes excessively small particularly at the initial stage of use, thus increasing surface pressure. This causes a significant decrease of the width of each fine groove when the sliding surface becomes worn. The drive force transmission characteristics thus greatly change after a long time of use, compared to the initial stage of use.


In order to properly allocates a limited number of sockets to applications (202, 202, . . . ) in a computer system so as to improve the system network performance, an application management module (300) memorizes the total number of sockets which OS (100) can supply to the applications (202, 202, . . . ), and a target number of sockets for each application. When an application (202) wants to obtain a socket, the application management module (300) recalculates the target number of sockets which can be allocated to the application (202), using a predetermined scheduling algorithm (312), based on the number of sockets presently unallocated and the priority revel of the application (202), and notifies the recalculated target number to the application (202). The application (202) judges from the notified target number whether a socket can be obtained or not, and based on the judgment determines whether or not to actually obtain a socket from the OS (100).

1. Technical Field
The present invention relates to a technology of managing the number of socket descriptors (referred to as "sockets" in this specification) allocated to each of one or more network applications operating in a computer system.
2. Related Art
A socket interface is used for programming a general network application, and the application uses a socket descriptor (or socket) generated by the socket interface to identify a communication destination for communication.
In a computer system which has a relatively large amount of built-in memory, such as a personal computer, the network application can use sockets without considering the upper-limit number of sockets. In contrast, a computer system built in an apparatus such as a printer has a small amount of built-in memory, and only a small number of sockets corresponding to the amount of the memory can be used. Therefore, it is usual that the number of sockets which can be used are allocated in advance to each network application, and a program is created with the allocated sockets.
In the latter case (the computer system built in an apparatus such as a printer), since a certain number of sockets need to be allocated even to rarely used applications, the number of sockets to be allocated to an application for a main function (for example, a print function in the printer) which is most frequently used in the apparatus is reduced, thus reducing the number of client connections which can be established at the same time. A simple solution to such a problem of reduction in the network performance of a product is to increase the amount of built-in memory, which naturally causes an increase in cost.
As for socket allocation, JP-A-2000-148426 discloses a technology in which sockets to be used by an application that monitors a printer are reserved in advance in order to avoid a situation where communication cannot be performed because of socket shortage, and the reserved sockets are used in response to a request of the application. With this technology, the application can be always operated normally. However, since sockets that are not being used are also always reserved, the socket resources are not efficiently used in the entire product.

Socket management device and socket management method


A roaming gateway for support of advanced voice services while roaming in wireless communications systems. The roaming gateway supports push-to-talk (P2T) calls, or other advanced voice services, when P2T subscribers roam from their home network (i.e., a network operated by their service provider where the subscriber's profile resides) into a foreign network (i.e., a network operated by another service provider). The roaming gateway is a specialized version of a real-time exchange that is located in the home network and is connected to mobile switching centers in foreign networks, so that the mobile switching centers in the foreign networks need not be programmed for the advanced voice services.

1. Field of the Invention
This invention relates in general to wireless communications systems, and more specifically, to a roaming gateway for support of advanced voice services while roaming in wireless communications systems.
2. Description of Related Art
Group-based voice services, such as two-way half-duplex voice calls within a group, also known as "Push-to-Talk," "Press-to-Talk," PTT or P2T, have enormous revenue earnings potential for wireless networks, such as cellular networks and personal communications systems (PCS) networks. Corporate subscribers primarily use such services for coordinating field people or fleet users from a central location.
Currently, there are three major approaches employed in providing group-based voice services such as P2T in wireless networks. One approach requires the installation of a dedicated private network, parallel to the wireless network, to support the group-based voice services. NEXTEL uses such a system, based on a solution developed by MOTOROLA known as IDEN. However, a dedicated private network is costly to install and maintain and is employed by a few public wireless carriers. Also, the IDEN system is non-standard, and hence cannot be used in standard wireless communications networks, such as those based on CDMA and GSM.
Another approach is based on Voice over IP (VoIP) technologies. While this approach promises compliance with newer and emerging standards, such as GPRS (General Packet Radio Service), UMTS (Universal Mobile Telecommunications System), etc., it does not provide a solution for carriers employing wireless networks based on existing standards, such as GSM (Global System for Mobile Communications), CDMA (Code Division Multiple Access), etc. However, even for the newer standards, solutions based on VoIP have serious drawbacks, including slower call setup, significant overhead, increased susceptibility to packet losses, low bit rate voice coders (vocoders), and significant modifications to the mobile handset. There is a need, instead, for solutions that require only minimal upgrades to the handset.
Still another approach is that defined in the co-pending and commonly-assigned patent applications cross-referenced above and incorporated by reference herein. In this approach, group-based voice services are provided by a real-time exchange or dispatch gateway that interfaces to the wireless network to provide the group-based voice services therein, wherein both the real-time exchange and mobile handsets that use the group-based voice services communicate with each other using call setup and in-band signaling within the wireless network.
Notwithstanding these innovations, there is a need in the art for a roaming gateway for support of advanced voice services while roaming in wireless communications systems. The present invention aims to satisfy this need.

Roaming gateway for support of advanced voice services while roaming in wireless communications systems


A slide housing having a plurality of rows of side wall ports directed into the side walls of the housing is arranged to receive a slide block within the housing, wherein the slide block includes through-extending bores arranged for alignment with the side wall bores, with a helical wind tube mounted to the side walls, with the wind tube having individual coils, and each coil including a coil exit port, and the coil exit ports are mounted to the side wall ports, with the slide arranged to effect intercommunication between a selected number of the individual coils to effect pitched change in use of the instrument. The slide block includes a slide conduit received within an instrument bell conduit in pneumatic communication with the instrument bell.

1. Field of the Invention
The field of invention relates to the use of brass instrument slide arrangements and particularly pertains to a new and improved musical brass instrument slide apparatus wherein the same is arranged to effect pitch change in brass instruments employing a slide mounted within a housing arranged to effect selective pneumatic communication of individual coils of a helical wind tube mounted in communication with a housing.
2. Description of the Prior Art
Wind instruments, and particularly brass instruments, use various slide arrangements such as exemplified in the U.S. Pat. Nos. 4,860,629; 4,831,911; 3,903,779; 3,631,755; and 3,937,116.
The instant invention attempts to overcome deficiencies of the prior art by providing for ease of pitch change in use of a brass instrument by having a helically wound coil permitting selective cooperation between an individual or plurality of the coils to effect pitch change in directing pneumatic communication between a mouth piece tube and a bell conduit of the instrument.

Musical brass instrument slide apparatus


A high permittivity gate dielectric is used in an NROM memory cell. The gate dielectric has a dielectric constant greater than silicon dioxide and is comprised of an atomic layer deposited and/or evaporated nanolaminate structure. The NROM memory cell has a substrate with doped source/drain regions. The high-k gate dielectric is formed above the substrate between a pair of the source/drain regions. A polysilicon control gate is formed on top of the gate dielectric. The gate dielectric can have an oxide-high-k dielectric-oxide composite structure, an oxide-nitride-high-k dielectric composite structure, or a high-k dielectric-high-k dielectric-high-k dielectric composite structure.

Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory. One type of flash memory is a nitride read only memory (NROM). NROM has some of the characteristics of flash memory but does not require the special fabrication processes of flash memory. NROM integrated circuits can be implemented using a standard CMOS process.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
The performance of flash memory transistors needs to increase as the performance of computer systems increases. To accomplish a performance increase, the transistors can be reduced in size. This has the effect of increased speed with decreased power requirements.
However, a problem with decreased flash memory size is that flash memory cell technologies have some scaling limitations. For example, stress induced leakage typically requires a tunnel oxide above 60 Å. This thickness results in a scaling limit on the gate length. Additionally, this gate oxide thickness limits the read current and may require large gate widths.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a more scalable, higher performance flash memory transistor.

NROM flash memory with a high-permittivity gate dielectric


A semiconductor integrated circuit device using precharge circuits free from the influence of a phase difference skew is provided. Each of the precharge circuits is controlled by a clock signal such that an arbitrary node in the circuit is precharged during a low level period or a high level period of the clock signal and the precharge circuit is operative during a high level period or a low level period of the clock signal. A first precharge circuit and a second precharge circuit having the same operational functions are arranged in parallel, and controlled by their respective clock signals to perform complementary operations, wherein the second precharge circuit is in an active period when the first precharge circuit is in a precharge period, and the second precharge circuit is in a precharge period when the first precharge circuit is in an active period.

The present invention relates generally to semiconductor integrated circuit devices, and more particularly to semiconductor integrated circuit having precharge circuits suitable for use in high speed applications.
Conventional semiconductor integrated circuits generally use a precharge circuit for performing high speed operations. The precharge circuit is controlled, based on a clock signal, to alternately have a precharge period and an active period. A latch circuit is typically arranged previous to a precharge circuit for latching an input signal. Generally, a level trigger type latch circuit is used for that purpose, where a through period for passing an input signal therethrough and a hold period for holding an input signal are alternately controlled by a clock signal.
For example, a latch circuit is controlled to have a through period for passing an input signal therethrough when a clock signal .phi.1 for controlling the latch circuit is at high level and to enter a hold period for holding data latched therein at the time the clock signal .phi.1 changes to a low level. Also, a precharge circuit is controlled, for example, to have a precharge period when a clock signal .phi.2 for controlling the precharge circuit is at low level and to have an active period for operating in response to an input signal supplied thereto at the time the clock signal .phi.2 changes to a high level.
The clock signal .phi.1 and the clock signal .phi.2 have the same period and opposite phases to each other such that the latch circuit and the precharge circuit operate in synchronism. In other words, the latch circuit is in a through period when the clock signal .phi.1 is at high level, while the precharge circuit is in a precharge period since the clock signal .phi.2 is in opposite phase, i.e., at low level. When the clock signal .phi.1 changes to low level to cause the latch circuit to enter a hold period to hold an input signal, the clock signal .phi.2 is in opposite phase, i.e., at high level, causing the precharge circuit to enter an active period, in which the precharge circuit operates based on the signal held in the latch circuit.
Since the clock signal .phi.1 used to control the latch circuit and the clock signal .phi.2 used to control the precharge circuit have the same period and opposite phases to each other, these circuits suffer from a dead time due to a phase difference skew. How a phase difference skew occurs is explained below in detail.
The clock signal .phi.1 and the clock signal .phi.2 should have the same period and opposite phases to each other, so that, essentially, when the clock signal .phi.1 changes from high level to low level, the clock signal .phi.2 must change from low level to high level at the same timing. Conversely, when the clock signal .phi.1 changes from low level to high level, the clock signal .phi.2 must change from high level to low level at the same timing. However, since the clock signal .phi.1 and the clock signal .phi.2 are different clock signals, they are typically generated and distributed by different circuits. Therefore, variations in the processes and devices used for generating these clocks may cause a deviation in timing between a rising edge of the clock signal .phi.1 and a falling edge of the clock signal .phi.2, i.e., a phase difference skew.
When a rising edge of the clock signal .phi.2 is delayed from the timing of a falling edge of the clock signal .phi.1 to arise a phase difference skew, the operation of the precharge circuit is delayed due to the delayed rising edge of the clock signal .phi.2, although the latch circuit has performed a latch operation in response to the falling edge of the clock signal .phi.1, thus arising a dead time corresponding to the delay of the clock signal .phi.2.
Conversely, when the clock signal .phi.2 goes high earlier than a falling edge of the clock signal .phi.1 to arise a phase difference skew, the clock signal .phi.2 goes high even during a through period of the latch circuit, in which the latch circuit is not yet performing a latch operation, to cause the precharge circuit to operate in response to the rising clock signal .phi.2. Thus, the precharge circuit cannot perform a correct operation, and a dead time arises corresponding to the time by which the clock signal .phi.2 has risen earlier than the falling edge of the clock signal .phi.1.
Further, since the phase difference skew possibly occurs when the clock signal .phi.2 goes high at the timing of a falling edge of the clock signal .phi.1 and when the clock signal .phi.1 goes high at the timing of a falling edge of the clock signal .phi.2, the phase difference skew can occur twice in one cycle of the clock signal .phi.1, thus resulting in a longer dead time.
With the ever increasing miniaturization of semiconductor integrated circuits, discrete circuits can operate at higher speeds. However, as a total load capacity and a total wiring length associated with clock signals are increased due to higher integration of semiconductor integrated circuits, it is more difficult to reduce the clock skew, particularly, the phase difference skew as compared with discrete circuits.
When a precharge circuit is employed, for example, in each of a plurality of logical circuits which are connected in series for performing high speed logical operations within one machine cycle, the logical operations must be performed so as to avoid a dead time due to the above-mentioned phase difference skew, and a latch circuit must be operated to store data indicating the results of the logical operations before the next dead time occurs. For these requirements, the number of stages of the serially connected logical circuits must be reduced to perform a less number of logical operations within one machine cycle. Thus, although the precharge circuit is employed for the purpose of high speed operations, the high speed operations are limited by the influence of the dead time due to the phase difference skew.


The present disclosure provides polarization mode dispersion compensation (PMDC) and polarization de-multiplexing systems and methods for polarization multiplexed (PolMux) optical transmission systems. The PMDC detects an error signal before a polarization splitter in PolMux systems for controlling polarization controllers (PC) and/or DGDs in the PMDC for return-to-zero (RZ) differential m-phase shift keying (DmPSK) signals. For bit-aligned PolMux systems, the error signal could be the level of clock frequency at one, two, or more times of the baud rate at one polarization. For bit-interleaved PolMux systems, the error signal could be the level of clock frequency at two times of the baud rate at one polarization. The PMDC can operate in PolMux systems with any arbitrary time offset between the two polarizations. The polarization de-multiplexer utilizes error detection at both output arms of a polarization splitter to mitigate PDL impact on any PolMux type of signal.

The rapid advance of transmission capacity of optical fiber communication systems demands techniques to improve optical spectral efficiency. For example, advanced optical modulation formats have been proposed to increase spectral efficiency and transmission distance. Exemplary formats include return-to-zero (RZ) differential binary phase shift keying (DBPSK), differential quadrature phase shift keying (DQPSK), differential 8 phase shift keying (D8PSK), and the like (generically referred to as DmPSK). RZ refers to the fact that the optical intensity returns to zero within each bit slot. Generally, duty cycles for RZ signals include 33%, 50% and 67% of the symbol period. DBPSK encodes information on the binary phase change between adjacent bits: a 1-bit is encoded onto a π phase change, whereas a 0-bit is represented by the absence of a phase change. The difference of an optical pulse train between DBPSK and the traditional on-off keying (OOK) is that DBPSK has an optical pulse in every bit while OOK has an optical pulse in 1-bits only. DBPSK has an advantage of 3 dB receiver sensitivity improvement over the OOK modulation format. DQPSK is a multi-level modulation formation that doubles the spectral efficiency at a symbol rate of half of the aggregate bit rate. It also has an optical pulse in every bit, which is coded by one of four phase shifts {0, π/2, π, −π/2}.
Polarization-multiplexing (PolMux) can further double the capacity of a wavelength channel and the spectral efficiency by transmitting two optical signals at orthogonal polarizations on the same wavelength. A polarization de-multiplexer is needed to track and split the two orthogonal polarizations in front of an optical receiver. If the bits of the two polarizations are synchronized or aligned with each other, it is called a bit-aligned PolMux system. On the other hand, if the bits of the two polarizations are offset by a half bit, it is called a bit-interleaved PolMux system. Also, the bits of the two polarizations can be offset by an arbitrary amount. PolMux-RZ-DBPSK or PolMux-RZ-DQPSK are very promising techniques for advanced optical fiber communication systems.
The birefringence of optical fiber supports two polarization modes, each having different propagation velocities, giving rise to polarization mode dispersion (PMD). Disadvantageously, PMD provides limiting effect for high speed optical communication systems, i.e. 10 Gbit/s and beyond. In a first order approximation, the PMD of fiber can be described by the parameters of differential group delay (DGD) and principal states of polarization (PSPs). An input optical pulse whose state of polarization (SOP) is aligned with one of the fiber's two input PSPs will come out of the fiber without distortion. An input pulse aligned with neither input PSP will emerge as two orthogonally polarized pulses, separated in time by the fiber's DGD. Both the DGD and the PSPs of the optical fiber vary randomly with time due to environmental factors and the like. Although polarization-multiplexing is considered promising for increasing the transmission capacity, it suffers from decreased PMD tolerance in comparison to non-polarization-multiplexing transmission. Accordingly, PMD compensation is a critical issue for PolMux systems.
Conventionally, many optical PMD compensators (PMDCs) have been proposed to overcome PMD limitations. A single stage PMDC usually includes a polarization controller (PC) and a fixed or variable time delay. Two or more stages of a polarization controller and time delay can be cascaded to build a multi-stage PMDC. A control loop is set up to extract error signals in front of a receiver and the error signals control the polarization controller and/or time delay automatically. In polarization multiplexed systems, both the PMDC and the polarization de-multiplexer need to be controlled automatically. They may use the same error signal or different error signals based on system design.
An optical PMDC can work in one of two different operating modes: cancellation mode and PSP mode. The PMD of a fiber system can be described as a vector quantity, with the DGD as the magnitude and the fast axis of the PSP as the direction. The principle of a cancellation mode PMDC is to adjust the PMD vector of the PMDC to be of an opposite direction of the PMD vector of the fiber system so the magnitude of the combined PMDC vector is minimized. If the DGD of the PMDC is variable, the PMD of fiber system can be perfectly cancelled in the first order approximation. The principle of the PSP mode is to adjust the direction of the PMD vector of the PMDC to align the direction of combined PMD vector to the same or opposite direction as that of the signal input SOP. In this way, the signal is injected to the one of the PSPs of the fiber system and the PMDC, and comes out of the PMDC without distortion.
Most conventional optical PMDCs cannot differentiate between these two modes and may work in either of them (H. Sunnerud, et al., "A comparison between different PMD compensation techniques", OSA/IEEE JLT, vol. 20, no. 3, pp. 368-378, 2002). They have the problem of dynamic limitation (E. Ciaramella, "Theoretical evidence of dynamical limitations in practical single-stage PMD compensators", IEEE PTL, vol. 16, no. 8, pp. 1843-1845, 2004). Dynamic evolution of the signal input SOP and the fiber PSP could require a switch between these two modes, producing significant performance degradation during the switch. The fundamental reason for this problem is that both modes can compensate for the PMD, and the error signals generated in front of the receiver cannot differentiate between these two modes. To solve this problem, the PMDC has to be locked in the cancellation mode. So the error signal used for PMDC control has to be sensitive to the total DGD change and insensitive to the PSP change of the combined PMD vector of fiber system and PMDC.
H. Y. Pua et al. propose polarization scrambling at a transmitter to lock the PMDC at the cancellation mode (H. Y, Pua et al., "An adaptive first-order polarization-model dispersion compensation system aided by polarization scrambling: theory and demonstration", OSA/IEEE JLT, vol. 18, no. 6, pp. 832-841, 2000). However, this technique produces timing jitter and partial eye closure when some residual DGD remains. It is also not applicable to polarization multiplexed systems because fast polarization scrambling prevents polarization multiplexed systems from polarization tracking and de-multiplexing in front of the receiver.
E. Ciaramella et al propose low-depth polarization dithering to stabilize the PMDC at the cancellation mode in order to decrease the penalty of timing jitter and eye closure (E. Ciaramella and E. Matarazzo, "Stabilizing PMD compensators by means of polarization dithering", IEEE PTL, vol. 19, no. 23, pp. 1892-1894, 2007). However, polarization dithering produces crosstalk between the two orthogonal polarizations when they are de-multiplexed.
Polarization multiplexed systems include signals at two orthogonal polarizations. When PMD exists in a fiber system, the arrival time and relative delay of the two polarizations will depend on the DGD level and the angle difference between the SOPs of the signals and PSPs of the system. The information extracted between the two orthogonal polarizations may be used as error signals to control PMDC.
D. Sandel et al. propose the detection of arrival time of optical pulses at a polarization for control of the PMDC, and the detection of interference between two polarizations for control of the polarization de-multiplexer in polarization multiplexed signals (D. Sandel, et al., "Standard and polarization multiplex transmission with PMD compensation", IEEE PTL, vol. 14, no. 8, pp. 1181-1183, 2002). Both error signals are detected from the signal at one polarization after a polarization splitter. This technique was used for OOK systems, but not for DBPSK, DQPSK, or DmPSK systems. It also needs complex electrical circuits to detect the arrival time of optical pulses accurately.
Hemonth Rao proposed the detection of RF power at the frequency of baud rate before the polarization splitter for the control of both the PMDC and the polarization de-multiplexer in bit-interleaved polarization multiplexed signals (Hemonth Rao, "A novel multi-stage automatic PMD compensator for polarization-multiplexed signals", OFC, OThU1, 2008). It uses a polarization maintaining tap and a component with half-symbol period DGD to generate the demanded clock frequency. The detected error signal is used to control the polarization controllers for both the PMDC and the polarization de-multiplexer. However, these techniques are not optimal. The control objective is to minimize the DGD value and align the SOPs of the signals with that of the polarization splitter. The polarization state change caused by the polarization controller of the polarization de-multiplexer will change the SOPs of signals only. However, any polarization state change caused by the polarization controller of the PMDC will change both the DGD value and the SOPs of signals. The PMDC may be locked at a state with a bad DGD value and an optimal SOP state, because any optimize of DGD value will cause a penalty from a sub-optimal SOP state. If the penalty from the sub-optimal SOP state is higher than the gain from the better DGD value, the PMDC will not be moved to new state. Actually, the PMDC should move to the new state because the penalty caused by sub-optimal SOP state can be compensated by the state change of the polarization controller of the polarization de-multiplexer. Because two or more polarization controllers are controlled by a single error signal, some compromises may be needed in the control algorithm. This is probably the reason why the reported control speed is very low. Another issue of the PMDC in Rao is that it works for bit-interleaved polarization multiplexed signals only.
Additionally, PolMux systems require a polarization de-multiplexer in addition to PMDC. An automatic polarization de-multiplexer usually includes a polarization controller (also referred to as a polarization tracker, polarization stabilizer, etc.), a polarization splitter, an error detection circuit, and a control circuit. The polarization controller is used to align the state of polarization (SOP) of the input signals to the polarization splitter. The polarization splitter splits the input signals into two output arms: one at horizontal linear polarization and the other at vertical linear polarization. If the SOP of the input signals are aligned to horizontal and vertical linear polarizations, the polarization multiplexed input signals are perfectly de-multiplexed. If not, each output arm includes both signals, in which one is the desired signal at the desired polarization while the other is the crosstalk from the other polarization. The error detection circuit is located at the one output arm of the polarization splitter. It detects an error signal that reflects the amount of crosstalk in the output arms of the polarization splitter. The control circuit reads the error signal and controls the polarization controller to minimize the crosstalk.
In optical systems, the loss and gain of some optical components may vary as the signal SOP changes. These are referred to as polarization dependent loss (PDL) and polarization dependent gain (PDG). Because gain is the negative of loss, the term PDL can be used to represent both polarization dependent loss and polarization dependent gain with an appropriate sign (+/−). The polarization dependence of the transmission properties of optical components has many sources. Some of the common effects are fiber bending, angled optical interfaces, oblique reflection, and optical amplification.
PDL has a severe impact on PolMux systems. PDL can cause a power difference between the signals at the two orthogonal polarizations, and destroy the orthogonal relationship of the two signals. The two signals then are no longer at two perfect orthogonal polarizations. Because the two output arms of the polarization splitter are always at orthogonal polarizations, the two polarization-multiplexed signals can no longer be de-multiplexed perfectly. Because conventional polarization de-multiplexers only have error detection circuits at one output arm of the polarization splitter, they have no idea of the existence and level of PDL in the system. They can only always try to align the SOP of one signal, signal H, to one arm of the polarization splitter, say arm H, and assume that the SOP of the other signal, say signal V, is automatically aligned to the other arm of the polarization splitter, say arm V, as well. Due to the PDL impact, however, the SOP of signal V is no longer perfectly orthogonal to the SOP of signal H. So the SOP of signal V is not perfectly aligned to the arm V of the polarization splitter. In this case, the power of signal V is split into both arms of the polarization splitter, with P cos2α in arm V and P sin2α in arm H, where P is the power of signal V and α is the angle between its SOP and the vertical linear polarization. The power of P sin2α in the arm H will be a crosstalk and cause penalty to the signal H at that polarization.

Polarization mode dispersion compensation and polarization demultiplexing systems and methods for optical transmission systems


A circuit arrangement, integrated circuit device, apparatus, program product, and method utilize an array of functionally interchangeable dynamic logic cells to implement an application specific logic function in an integrated circuit design. Each functionally interchangeable dynamic logic cell is comprised of a dynamic logic circuit configured to generate an output as a function of a plurality of inputs, and an output latch that is configured to latch the output generated by the logic circuit. The array of functionally interchangeable dynamic logic cells are used to implement an application specific logic function within a specific logic design by routing a plurality of conductors between inputs and outputs of at least a subset of the functionally interchangeable dynamic logic cells.

Electronic integrated circuits, or "chips" have become significantly more complex as circuit fabrication technologies have improved. It is not uncommon for integrated circuits to incorporate hundreds of millions of transistors, with a comparable number of interconnects, or signal paths, integrated together onto a single piece of silicon substrate no larger than the size of a coin. In addition, often the same functionality that once required multiple chips can now be integrated onto the same chip, a concept often referred to as "system-on-chip" technology.
The design of integrated circuits has likewise become more difficult as complexity has increased. Whereas early chips were often designed gate by gate, more advanced integrated circuits incorporating millions of gates represent too much of an undertaking for early design methodologies. Likewise, another important aspect of integrated circuit design is that of testing and verifying an integrated circuit design, both from the standpoint of verifying that a design will logically operate as intended, and of ensuring that a design will comply with the physical limitations that are inherent in any integrated circuit, i.e., to ensure that all timing and delay constraints are met.
As a result, a variety of software design applications, or tools, have been developed to assist designers with designing and testing integrated circuits.
Generally when utilizing these tools, the overall design process is represented by two stages. The first stage is referred to as logic design, where the desired functional operation of an integrated circuit is initially defined and tested. The second stage is referred to as physical design, where the logic design created during the logic design stage is processed to select actual circuit components to implement the functions defined in the logic design, and to lay out the components on an integrated circuit and route interconnects therebetween. The interconnections between circuit elements are often referred to as nets, and the nets are generally routed after placement of circuit components at specific locations on an integrated circuit.
Often, automated design tools rely on standardized circuit components, referred to as logic cells, which are self-contained, reusable and pre-tested circuit designs that represent specific higher level functions. Logic cells simplify a number of design steps. For example, logic design is simplified given that the logic synthesis tool is able to construct a circuit from fewer, more complex functions. Furthermore, both physical design and verification are often simplified because the logic cells function more or less like a "black box", whereas all of the individual gates and interconnects in a logic cell have already been placed relative to one another and tested beforehand.
In addition, some logic cells may be configured to provide different logical responses depending upon how they are interconnected with other circuit components. For example, a logic cell might be utilized to provide a generalized function such as A AND B AND C AND D AND E, where A-E are different inputs. Should one particular design only need to implement the function A AND B AND C, the D and E inputs could simply be connected to a logic 1 value to effectively remove those inputs from the function. Likewise, where only a function such as A AND B be needed in a different design, the C, D and E inputs could be connected to a logic 1 value, resulting in the same logic cell having a different logical response than in the first example.
Conventional logic design using logic cells, however, suffers from a number of drawbacks. Often the logic cells differ in size and shape, which can lead to inefficient space utilization when placed in a design. Furthermore, routing of the interconnects and clock signals is often haphazard and irregular, in many instances creating timing problems such as skew and jitter that require excessive testing and redesign.
In addition, conventional design methodologies and tools have typically been limited to use with logic cells implemented using static logic. More recently, however, dynamic logic has come into favor in circuit designs due to faster speed, lower power consumption, and reduced gate count. With dynamic logic, a clock signal is used to precondition a circuit of gates to a steady state during a precharge phase of the clock, then during an evaluate phase of the clock, a boolean function of the inputs of the circuit is evaluated and output by the circuit.
Logic synthesis tools have conventionally been unable to effectively utilize dynamic logic due in part to tighter stricter timing constraints associated with dynamic logic. In many cases, automated routing of the clock and interconnect signals is simply too irregular to meet the strict timing requirements of dynamic circuits.
Yet another drawback of conventional design methodologies arises when changes in the logic design a required at later stages of the development cycle. Oftentimes, dummy cells may be incorporated into a design to account for the possibility that the logic functions to be implemented in a circuit will be changed at a later point in the design process. If such dummy cells are never utilized, however, the space allocated to the dummy cell is effectively wasted, thus increasing the size and overall cost of the design.
Therefore, a significant need continues to exist for a circuit design methodology that supports the use of dynamic logic in a circuit design, as well as reduces the irregularities and inefficiencies associated with conventional methodologies and tools.

Integrated circuit design utilizing array of functionally interchangeable dynamic logic cells

International Business Machines Corporation


Systems and methods are disclosed for managing a multimedia conference call. According to certain embodiments, a server establishes a multimedia conference call between a plurality of multimedia conference devices. The multimedia conference call includes the communication of multimedia conference contents via one or more of the plurality of multimedia conference devices. The server also records at least a portion of the multimedia conference contents; and detects one or more interrupting events. The interrupting events occur during the multimedia conference call. The server further provides substitute contents to the other multimedia conference devices of the plurality of multimedia conference devices. The substitute contents are generated based on a recorded portion of the multimedia conference call associated with a time to the interrupting events.

A video conferencing system allows two or more conference participants to conduct conferences by two-way or multi-way video and audio transmissions using conference devices capable of performing multimedia communications. A video conferencing system uses digital compression technologies to compress the video and audio streams in real time and transmit the compressed video and audio streams through a network, such as an integrated services digital network (ISDN) network or an Internet protocol (IP) network. A video conferencing system allows concurrent transmitting and receiving of video and audio streams by any conference device connected to the conference.

Systems and methods for managing multimedia conference calls


A set of likelihood values associated with a set of characteristics associated with the set of goodware entities is determined. The set of characteristics is stored in association with the set of likelihood values as a model. A set of relative information gain values associated with the characteristics of the set of characteristics is generated. One or more characteristics are removed from the model responsive to the relative information gain values associated with the one or more characteristics to produce a revised model.

1. Field of the Invention
This invention pertains in general to computer security and in particular to the development of signatures to accurately identify malware.
2. Description of the Related Art
There is a wide variety of malicious software (malware) that can attack modern computers. Malware threats include computer viruses, worms, Trojan horse programs, spyware, adware, crimeware, and phishing websites. Modern malware is often designed to provide financial gain to the attacker. For example, malware can surreptitiously capture important information such as logins, passwords, bank account identifiers, and credit card numbers. Similarly, the malware can provide hidden interfaces that allow the attacker to access and control the compromised computer.
Security computer systems and software for counteracting malware typically operate by seeking to identify malware signatures. Malware signatures contain data describing characteristics of known malware and are used to determine whether an entity such as a computer file or a software application contains malware. Typically, a set of malware signatures is generated by a provider of security software and is deployed to security software on a user's computer. This set of malware signatures is then used by the security software to scan the user's computer for malware.
During malware signature generation, malware signatures are typically validated against entities that are known to not contain malware, herein referred to as "goodware", in order to ensure that the malware signatures do not generate false positive identifications of malware. In other words, the malware signatures are validated to ensure they do not falsely identify goodware as malware. Typically, a malware signature is first generated by a security administrator then compared to a dataset of goodware in order to determine whether the malware signature generates false positive identifications of malware. Due to the large size of the dataset of all known goodware and the large number of potential malware signatures, comparing malware signatures to a dataset of goodware may be very computationally expensive.
An alternate method of generating malware signatures involves determining the rate at which characteristics occur in the dataset of all goodware. Using this method, malware signatures containing characteristics which have a low rate of occurrence or no occurrence in a dataset of goodware may be generated. However, due to the large set of all possible goodware and the large set of all possible characteristics, it is not tractable to identify and store a rate of occurrence for all characteristics.
Accordingly, there is a need in the art for methods of developing malware signatures with reduced false positive malware detections.

Modeling goodware characteristics to reduce false positive malware signatures


An exemplary slide rail assembly includes a first rail having a pair of stop members, a second rail, a first release member and a second release member slidably attached to the second rail, a fixing board attached to the second rail, a pair of actuating members slidably attached to the fixing board, and a clip. The clip includes a pair of arms respectively abutting against the actuating members. The actuating members engage with the stop members to latch the second rail in the first rail in two opposite directions. One actuating member is driven by the first release member to disengage from one stop member so that the second rail is released along one direction. The other actuating member is driven by the second release member to disengage from the other stop member so that the second rail is released along the other direction.

1. Field of the Invention
The present invention relates to a slide rail assembly.
2. Description of Related Art
Slide rails are used in a variety of applications, including business furniture, kitchen drawers, electronic racks, and copiers. One type of slide rail is a telescopic slide rail. Telescopic slide rails often comprise two, three, four or more telescoping members. The shape of a slide rail, and the individual members, are determined by design needs. The slides can be frictional, with lubricated members rubbing against each other, or a slide assembly may include roller or ball bearings for easier movement. The members in such assemblies tend to be C-shaped in nature.
A conventional three-section slide rail assembly for a drawer includes a first slide rail (e.g. outer slide rail), a second slide rail (e.g. middle slide rail), and a third slide rail (e.g. inner slide rail). A ball rail is sandwiched between any two of the first slide rail, the second slide rail, and the third slide rail to provide a smooth sliding movement. Moreover, the third slide rail and the second slide rail mount a retaining member and a stop member respectively to prevent the slide rails extending too far. The retaining member is attached to an inner surface of the third slide rail, and provided with an inclined wall. The stop member is mounted to a front end of the second slide rail, and provided with a protrusion. To prevent users from drawing the third slide rail out too far from the second slide rail, the protrusion of the stop member engages with the inclined wall of the retaining member.
Users can draw out a keyboard or a component, which is attached to the third slide rail. Although the engagement of the stop member with the inclined wall avoids the release of the third slide rail from the second slide rail by accident, it cannot prevent the third slide rail retracting into the second slide rail too far by careless force of users. Therefore, it is inconvenient to users for operating the slide rail assembly in use.
Consequently, it is required a slide rail assembly which can latch the two rails in two-directions and selectively release the two rails in different directions.

Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd.


Apparatus for aerating a pool of liquid has a hollow, rotatable drive shaft journaled for rotation about an axis and coupled at one end to a driving motor. A propeller is mounted at the other end of the drive shaft. The propeller has a plurality of hollow blades in communication with an internal aerating fluid passage in the drive shaft. A plurality of air inlets is provided in the drive shaft and at least one outlet port is provided in each blade at the zone of highest negative pressure resulting from rotation of the blade in the liquid. The drive shaft automatically is movable from a dry-docked position in which the shaft is out of the liquid to an operating position in which the propeller blades are immersed in the liquid. A seal is provided between the propeller and the shaft journal to protect the latter against exposure to the liquid. The shaft is continuously pressurized between the journal and the seal to prevent liquid from passing through the seal should the seal become worn.

Aeration of waste water is known and involves introducing air into the water and mixing the air and water to promote biological consumption of algae and other pollutants present in the water.
Various mechanical aeration devices have been proposed utilizing a submerged propeller coupled to a draft tube. Rotation of the propeller agitates the water and creates a differential pressure which draws air through the draft tube for discharge into the water. To treat water effectively and efficiently with such mechanical devices, it is desirable to introduce into the water as much air as possible per unit of time and as a dispersion of very small bubbles. It also is desirable to produce as much thrust as possible from the propeller to force the air bubbles deeply into the water for optimizing retention time of the air bubbles in the water. Preferably this is accomplished with minimum consumption of energy.
Known mechanical aerator devices have included hollow hub-type aerators such as those disclosed in U.S. Pat. Nos. 4,280,911; 4,308,221; 4,954,295; and 4,741,870. Each of these devices includes rotatable propeller blades for generating low pressure in the vicinity of the propeller hub causing air to be drawn through a draft tube and out of the hub for discharge into the water. Such devices require rotation of the propeller at high velocity in order to generate sufficiently low pressure to draw air through the tube. Rotating the propeller at high speeds results in high energy consumption and produces a rather coarse dispersion of air bubbles in the water which negatively affects aeration efficiency.
Other aeration devices have been proposed utilizing propellers having perforated hollow blades communicating with atmosphere through a draft tube. Like the hollow hub aeration devices described above the hollow blade devices conduct the air or other fluid to the liquid under the influence of suction generated by the rotation of the propeller in the liquid. Since the blades rotate at a relatively higher circumferential velocity than the hub, increased aeration can be produced by providing outlet ports in the blade rather than in the hub. Examples of known hollow blade aerating devices appear in U.S. Pat. Nos. 4,200,597; 4,371,480; and 5,013,490.
In the operation of aerator devices of the kinds described above, positive air pressure at the air outlets produced as a result of rotation of the propeller prevents the backing of liquid into the draft tube through the outlets. When the propeller is not rotating, however, water can enter the draft tube via the air outlets. Such a result is particularly objectionable when treating waste water of a sewage treatment facility since, over time, algae and other bacterial matter accumulate in the draft tube and block the air passages.
Waste water also may be so corrosive as to damage bearings and seals within the draft tube. In order to avoid such problems, it presently is necessary manually to dry dock or remove the aerator from the water so that the air outlets are above the surface of the water.
Some manufacturers of aeration devices have replaced conventional antifriction bearings with water bearings as a means for extending the bearing life of the aerator. Wet bearings, however, also are prone to attack by waste water and require replacement after a short period of time. In contrast, ball or roller bearings will last considerably longer than wet bearings if they are adequately protected from exposure to the waste water. The Gross patent referred to above discloses a conventional antifriction bearing journaling the drive shaft, but such bearing is located above the surface of the waste water to prevent its exposure to the water. This construction results in several feet of the drive shaft extending beyond the bearing, thereby requiring support from a cantilever sleeve and additional wet bearings, resulting in additional complexity and cost in the manufacture of such devices.


Provided is a thin film solar cell module including series-connected unit cells, wherein a thin film silicon photoelectric conversion unit and a compound semiconductor-containing photoelectric conversion unit are electrically connected in each unit cell. Each unit cell includes at least a transparent electrode, an amorphous silicon-containing photoelectric conversion unit, an intermediate transparent electrode layer, a photoelectric conversion unit, a compound semiconductor-based photoelectric conversion unit, and a metal electrode in this order from the light incident side. In each of the unit cells, the photoelectric conversion unit and the compound semiconductor-based photoelectric conversion unit are connected in series to form a series-connected component. The series-connected component is connected to a first photoelectric conversion unit in parallel via the transparent electrode and the intermediate transparent electrode layer.

For realization of both reduced cost and enhanced efficiency of a photoelectric conversion device, a thin film solar cell has attracted attention and been vigorously developed in recent years, since it needs fewer raw materials during production. At present, a crystalline silicon thin film solar cell on top of a conventional amorphous silicon thin film solar cell has been developed, and a stacked thin film solar cell called a hybrid solar cell obtained by stacking these cells has been put into practice. Further, studies on a compound semiconductor-based solar cell using compound semiconductor are proceeding, and a product with a higher efficiency than the thin film silicon-based solar cell has been put into practice.
The thin film silicon-based solar cell has advantages in that it is producible by a technique facilitating larger area production, such as CVD, and it has highly excellent volume cost due to raw materials being abundant. Further, although the compound semiconductor-based solar cell is inferior in volume cost to thin film silicon solar cell, it can absorb light by direct transition of electrons, thereby enhancing the efficiency with relative ease.
As for a material for the thin film silicon-based solar cell, amorphous silicon has a band gap of 1.85 to 1.7 eV. Meanwhile, crystalline silicon as a mixed phase of the amorphous silicon and crystal silicon normally has a band gap of 1.4 to 1.2 eV, depending upon a crystalline volume fraction. These thin silicon films can be alloyed with an element such as hydrogen, carbon, oxide, nitrogen or germanium, to adjust a band gap. Further, they can be doped with a material having a different valence electron number from those of silicon, such as boron or phosphorus, to obtain P-type silicon or N-type silicon.
It is to be noted that in this specification, a term "crystalline" includes polycrystalline and microcrystalline, and further includes a material partially including amorphous. Further, a term "silicon-based" includes, other than a simple silicon substance, silicon alloyed with the element such as hydrogen, carbon, oxide, nitrogen or germanium.
In the thin film silicon-based solar cell, normally, a photoelectric conversion unit is formed by a PIN structure where a substantially intrinsic I-type layer is sandwiched between a P-type layer and an N-type layer. With the I-type layer being a light-absorbing layer, a wavelength and a photovoltaic power of photoelectrically convertible light are decided according to a band gap of a material constituting the I-type layer. When energy not smaller than the band gap is absorbed, redundant energy becomes heat or light, and thus cannot be converted into electric power.
Further, it is very unlikely that energy not larger than the band gap would be absorbed. Even in the case of the energy not larger than the band gap being absorbed, electrons are not excited to a conduction band, and thus, also in this case, energy becomes heat or light, and cannot be converted into electric power. Therefore, stacking a plurality of photoelectric conversion units with different band gaps and efficiently converting light energy corresponding to the band gaps into electric power in the respective photoelectric conversion units, which is so-called multi-junction, is essential for improving the efficiency of the thin film solar cell in the future.
A compound semiconductor-based photoelectric conversion unit is an example of one expected to be stacked with the thin film silicon-based photoelectric conversion unit to form multi-junction. Although there are a variety of kinds of compound semiconductor, they are classified into three: a compound made up of a III-group element and a V-group element; a compound made up of a II-group element and a IV-group element; and further, a chalcopyrite-based compound of the I-III-VI2 group as modification of the II-VI group, or the like. Among them, CuInSe2 (hereinafter referred to as CIS) and CuInTe (hereinafter referred to as CIT), as solar cells using the chalcopyrite-based compound, have large absorption coefficients and show sufficient light absorption even with a film thickness being not larger than 1 μm.
The chalcopyrite-based compound has a band gap smaller than 1.0 eV, and excited electrons transit on the bottom of a low conductive band, whereby energy of a visible light component of solar light cannot be efficiently converted into electric power, and the compound as a simple substance is not suitable for the solar cell. For this reason, when it is used in a solar cell, a composition of chalcopyrite-based compound is changed to Cu(In, Ga)Se2 or CuIn(S, Se)2 so as to widen the band gap of the compound semiconductor. However, there is a limit on widening the band gap, and even when the composition is changed, the compound semiconductor-based photoelectric conversion unit used as a single unit cannot be suitable for the solar cell. Therefore, in order to obtain a solar cell with high practicability, a multi-junction of the compound semiconductor-based photoelectric conversion unit with other unit(s) is important.
Patent Document 1 provides a method for producing a high-efficiency solar cell in which an epitaxial growth of III-V group compound semiconductor onto a single crystal Si substrate is performed. However, forming a GaAs-based photoelectric conversion unit requires a large amount of As, and its adverse effect upon the environment is concerned. Further, since the compound semiconductor layer is required to be deposited onto the Si single crystal plane for the epitaxial growth, it is not realistic as a method for producing a large area module.
In a general chalcopyrite-based compound semiconductor-based solar cell, zinc oxide/CdS are used as a window layer on an N-type layer side. Therefore, in the chalcopyrite-based compound semiconductor-based solar cell, allowing light to be incident from the N-type layer side is one of conditions for improving the efficiency. Meanwhile, conditions for improving the efficiency of the solar cell having an amorphous silicon-based photoelectric conversion unit may include that: light is allowed to be incident from the P-type layer side of the amorphous silicon-based photoelectric conversion unit; a rate of a current of the amorphous silicon-based photoelectric conversion unit is not limited even when a multi-junction is formed; and characteristic deterioration due to photodegradation of the amorphous silicon-based photoelectric conversion unit is small.
It is expected that stacking a low-cost thin film silicon-based photoelectric conversion unit and a chalcopyrite-based compound semiconductor photoelectric conversion unit as a narrow band gap material with high sensitivity on the long wavelength side to form a multi-junction as described above can enhance the efficiency of the thin film photoelectric conversion device. However, advantages thereof cannot be sufficiently utilized when a multi-junction is formed by simply stacking them, since it is preferable to allow light to be incident from the P-type layer side on the amorphous silicon-based photoelectric conversion unit, and from the N-type layer side on the chalcopyrite-based compound semiconductor photoelectric conversion unit. Further, it is difficult to match current densities of these two photoelectric conversion units to prevent rate-limiting of the current of the amorphous silicon-based photoelectric conversion unit. There has thus been no example to date in which the amorphous silicon-based photoelectric conversion unit and the chalcopyrite-based compound semiconductor photoelectric conversion unit are stacked in a multi-junction and modularized manner.


A metal alloy workpiece is heated convectively in a first step by heat conduction, heat radiation or further non-inductive heat transfer to a temperature lying just below the solidus temperature of the alloy and is heated inductively in a subsequent second step to the final temperature lying between solidus and liquidus temperature. The process is particularly suitable for producing workpieces having thixotropic properties intended for further processing, in particular for further processing bolts or bars in die-casting, forging, rolling and pressing plants.

The invention relates to a process for heating a solid metal alloy workpiece to a final temperature lying between solidus and liquidus temperature of the alloy, in particular for producing a part solid-part liquid, thixotropic state for the workpiece.
When producing metal alloy phases having thixotropic properties, it is known to set the temperature of an alloy melt to a value between solidus and liquidus temperature and to vigorously stir the alloy paste thus produced to convert the dendrites forming in the solidification process to form essentially globular cast grains. This process and the possibilities for using the metal alloy phase having thixotropic properties thus produced are described in detail, for example in U.S. Pat. No. 3,948,650 and U.S. Pat. No. 3,959,651.
These part solid-part liquid metal alloy phases are generally initially cooled below the solidus temperature of the alloy, generally to room temperature, and heated only shortly before further processing thereof to the required processing temperature, at which the thixotropic properties appear.
Coarsening of the cast grains is undesirable both in the production of the metal alloy phase having thixotropic properties and in the later repeated heating of the workpieces to the further processing temperature.
It is generally known to use oil, gas or resistanceheated furnaces with or without circulation of air, or even induction furnaces, to heat metal materials.

Process for heating a metal alloy workpiece


Hair cleaning agents and methods for improving the care properties of hair are provided. An exemplary hair cleaning agent contains anionic surfactant and a specific oil mixture. The oil mixture may include (i) at least one mono- and/or diester of glycerol and a saturated or unsaturated, branched or unbranched carboxylic acid having 18 to 30 carbon atoms, (ii) at least one vegetable oil, (iii) at least one cationic guar polymer, and (iv) at least one amidoamine of a selected formula.

Human hair and the scalp can be cleansed and freed of sebum, styling residue and other contaminants with the help of cosmetic cleaning agents (hair shampoos).
Due to the (mostly anionic) surfactants usually contained in cosmetic hair cleaning agents, hair cleaning is always associated with the removal of lipids and proteins from the hair or scalp, in which damage to the hair structure and/or dehydration of the scalp can occur, in particular with frequent cleaning.
Damage to the hair structure or the hair fibers, in particular split ends and/or hair breakage, can also be promoted by environmental influences (such as intense sunlight), mechanical stress (such as combing under hair dryer) and by chemical influences (such as dyeing, deforming or straightening the hair).
In order to prevent and/or reduce hair damage, different care substances such as cationic care polymers, mineral or vegetable oils and/or silicones have been added to hair shampoos in the past. This already resulted in significantly improved care properties such as combability and hair feel from the first application.
However, disadvantages also appear with regular use over a long period of time. Thus, the regular deposition of higher amounts of oil from care shampoos on the hair ensures the aforementioned conditioning benefits, but at the same time—in particular after regular application to fine and/or damaged hair—a certain over-conditioning can be observed, whereby the hair looks greasy and weighted. Overall, the hair thus has an unkempt, unattractive appearance.
A further disadvantage is that higher amounts of oil in shampoos must be stabilized with effort by the incorporation of excipients, such as special thickening polymers and/or alkoxylated nonionic emulsifiers and usually lead to milky-turbid formulations.
Due to the increasing number of incompatibilities, the consumer desires less complex cosmetic agents which have a high proportion of active substances and excipients of natural origin which are readily degradable.
For the consumer, this is synonymous with transparent formulations.
The partial or total abandonment of oils in shampoos in favor of other care substances such as cationic care substances leads to unwanted flying of the hair and does not provide a solution to the aforementioned problem.
The present application was therefore based on the object of providing a hair care agent having high care performance, which ensures an optimal balance between mild and thorough cleaning, long-lasting and sustainable care and good compatibility. In order to avoid the over-conditioning effects described, ideally the use of larger amounts of oil, in particular the use of silicones or mineral oils, should be therefore dispensed with.
Another goal was to provide transparent hair care shampoos.


A system for containing a stack of face masks and dispensing individual face masks from the stack. The system includes a container and a stack of folded face masks. The container has a bottom panel forming a cut-line that defining a flap that is transitionable to an open state to generate an opening in the bottom panel. The stack is disposed within the container, and each face mask includes an elastic sheet forming a central portion and opposing first and second lateral end portions. Each face mask is folded such that a section of the first lateral end portion extends from a first fold line along the central portion. In a dispensing mode, the first lateral end portion of a bottommost folded face mask naturally drops through the opening due to gravity.

Protective face masks are useful in a number of fields. In the health care field, a face mask may be useful for protecting both the patient and the health care provider from airborne pathogens or for preventing the transfer of pathogens that reside in bodily fluids or other liquids. Wearing protective face masks may also be useful in many industrial settings.
Many protective face masks are constructed to have a front panel that covers the nose and mouth of a user and a securing device (e.g., manual tie straps) that can attach this front panel securely to the head of the user. Often, the front panel and the tie straps are created separately in separate processes and then attached to one another (e.g., using adhesives, staples or other mechanical fasteners). The attachment point between the front panel and the tie strap of a face mask may be broken, for example, by pulling on the tie strap.
Face masks are sometimes provided or packaged in a dispenser. For example, a nested stack of face masks may be provided in a carton or container from which the tie strap may be grasped. The user may grasp the tie strap and pull down, thereby causing the face mask onto which it is attached to be removed from the carton. Subsequently, a new face mask to be dispensed will fall into the place of the previously dispensed face mask, and the tie straps of the next-to-be-dispensed face mask will protrude from the carton. These types of dispensing arrangements suffer from the disadvantage of commonly dispensing more than one face mask when a user pulls on the elastic band or tie straps. Also, such an arrangement may fail to have the next-to-be-dispensed face mask being positioned in the dispensing position upon the removal of a preceding face mask. In this instance, the user must reach into the carton in order to grasp the face mask to be removed. This could cause the face mask to be damaged upon being grasped and pulled by the user. And, as mentioned above, pulling on the tie strap is a common way to break the face mask.
The dispenser packaging format employed with so-called single piece face masks may also be problematic. With this type of face mask, the front panel is formed integrally with side panels that otherwise provide openings that are used to attached the face mask to the wearer. The front panel and the side panels may be die cut from a web of material and may be formed at the same time. Some of these masks are stretchable to achieve a better fit on the face of the wearer. Due to the relatively planar and foldable nature of the single piece face mask, some packaging and dispensing techniques entail forming a stack of face masks in which adjacent ones of the face masks within the stack are interfolded with one another, and packaging the stack in a carton. As an outermost face mask is pulled through an opening in the carton, the next-to-be-dispensed face mask is partially pulled through the opening due to the interfolded relationship and is readily available for subsequent dispensing. While highly viable, this approach may entail a more complex manufacturing methodology in order to form the stack of interfolded face masks. Further, with these and other packaging configurations, the next-to-be-dispensed face mask may not consistently protrude from the carton, leading to possible user confusion.
Because of the problems associated with dispensing face masks, improved design and dispensing of face masks may be desirable.

Conformable face mask packaging and dispensing systems


In an embodiment of the present invention, a firearm recoil suppressor comprises a boot for receiving the butt-stock, at least one means for suppressing the recoil, a base, and a base fixture device. In one embodiment, the suppressing means comprises at least one hydraulic shock absorber, such as a piston and cylinder, or other shock absorber known to those with skill in the art.

A common problem when using a firearm is the recoil, or kick, experienced by a user. Recoil is the backward kick or force produced by a firearm upon discharge. During use, a user will place the butt-stock, also known as the butt of the gun, firmly against their shoulder to fire the weapon. Many rifles and shotguns have such a strong recoil, that a user's arm will become sore and may even experience bruising. Because of this recoil effect, the ability to fire multiple rounds accurately may be reduced, as well as the user's desire. Other users may even abstain from firing some weapons because of the recoil experienced. The present invention seeks to solve these problems.


The substrate of a liquid crystal display has a non-square rectangular shape and is bent such that the longer edges of the rectangular shape are nonlinear while the shorter edges are linear. Liquid crystal containerizing micro-cavities of the display are organized to be elongated in the extending direction of the nonlinear longer edges of the substrate while gate lines and liquid crystal injection holes forming areas are formed extending in the extending direction of the linear shorter edges of the substrate. Concentration of mechanical stresses may be reduced due to this configuration.

(a) Technical Field
The present disclosure of invention relates to a liquid crystal display (LCD) having a bent screen and more specifically to one in which the liquid crystals are encapsulated in micro-cavities.
(b) Description of Related Technology
A liquid crystal display (LCD) is one of the flat panel displays that are currently most widely used. LCD's typically include two panels where at least one of them has electric field generating electrodes disposed thereon, such as pixel electrodes and a common electrode, where a liquid crystal layer is disposed therebetween.
The LCD is configured to produce electric fields extending through the liquid crystal layer by applying corresponding voltages across the electric field generating electrodes. The produced electric fields determine corresponding alignments of local liquid crystal molecules of the liquid crystal layer. A displayed image is then formed by using the oriented liquid crystals for controlling polarization of incident light.
One technique for implementing a LCD display involves forming a plurality of micro-cavities for a respective one or more pixels and filling the micro-cavities with liquid crystal such that liquid crystal material is containerized in the areas where the micro-cavities are present. When the micro-cavities technology is used, the typical two-panel configuration for the LCD is no longer needed and it is possible to reduce a weight, a thickness, and the like, of the LCD by forming constituent elements on only a single substrate.
One class of LCD's uses a flexible substrate whereby the LCD is rendered bendable. In this instance, excessive stress may become concentrated on structural points at which the micro-cavities are formed.
It is to be understood that this background of the technology section is intended to provide useful background for understanding the here disclosed technology and as such, the technology background section may include ideas, concepts or recognitions that were not part of what was known or appreciated by those skilled in the pertinent art prior to corresponding invention dates of subject matter disclosed herein.


Apparatus for pretreating fuel for combustion in a combustor comprising a fuel line leading from a fuel supply to the combustor, said line including at least one fuel pretreatment apparatus which contains one or more of at least one ceramic piece and at least one ferromagnetic plate. The apparatus of claim 1, wherein said fuel line includes a substantially cylindrical shaped enlarged fuel pretreatment apparatus, which contains a plurality of partitions disposed therein at predetermined axial intervals each of said partitions having one or more flow through opening formed therein, whereby a undulating fuel passage is formed in said tube.

In recent years, the requirements for the reduction of harmful components of combustion engine exhausts have been tightened to avoid harm to the environment. Some of the worst offending combustors are internal combustion engines of diesel trucks and other oil-fueled vehicles, and of boilers. Therefore, conventionally, such automobile engines were fitted, for example to have the exhaust pressure of the engine force air into the engine to increase the combustion efficiency. This improves the horsepower performance of the engine and also lowers fuel consumption, and decreases the harmful matter in the exhaust gas. The use of a turbocharger, however, is still not sufficient to decrease the harmful exhaust compositions. Other suggestions to reduce harmful exhaust include the use of chemical additives to the fuel oil, placing a magnet into a fuel tank, but these measures also did not lead to acceptable results.