Techniques for determining the eagerness of a call processing unit within a multiple processor call processing system to accept a new call or call upgrade, as well as call admission control and other call event processing, as well as systemwide load balancing through query of such eagerness are disclosed. Fuzzy logic and associated analysis is used to determine this eagerness. Eagerness for a particular call processing unit is determined in part with reference to the actual load of a call as well as an estimated load approximated using a probabilistic distribution function, such as a Gaussian distribution.

In light of recent tightening of the credit markets and general drop-off in demand, telecommunications carriers are increasingly pressured to maximize return on their existing infrastructure and/or make wise choices when purchasing and deploying new telecommunications gear. Due in part to their cost and potential performance bottlenecks, especially when stretched beyond nominal loads, call processing systems within the carrier's network have drawn heightened scrutiny.
Traditional time-domain switched, voice-oriented communications typically included a single call processing unit tightly coupled to and servicing a given switch fabric or a dedicated portion thereof. Smaller, enterprise class telecom solutions such as a digital key system or private branch exchange included one call processing unit, whereas carrier grade central office solutions involved a dedicated call processing unit servicing a dedicated portion of the central office switching fabric. TDM switching techniques assured an actual or virtual connection be established and maintained for the duration of a call, at the expense of resource efficiency and dynamism.
With the advent of packet voice and softswitch solutions, the call processing system has been decoupled from the actual or virtual switching fabric, and a number of multi call processor designs have been developed, since each call processing unit is now capable of handling almost any call originating from or terminating to the larger system.
A representative multiple processor call processing system 2500 is shown in FIG. 25. In this system, plural individual call processing units or PMCis, including PMC1 2515 and PMC2 2520 and PMCK 2525; collectively handle a number of call processing activities and call events. The managing call processing unit, or PMC-M 2510, performs other call processing activities and events. Typically, in known multiple call processing system architectures, the PMCis 2515, 2520 and 2525 handle the bulk of the "individual call" oriented activities and tasks based on the subset of system calls they are assigned to handle, whereas the PMC-M 2510 is primarily responsible for coordinating operation of the PMCis as needed for e.g. system-wide call admission control and load balancing. As such, communication of coordination information (not shown) such as control, status, query and reporting messages occurs between these PCMis 2515,2520, 2525 and the PMC-M 2510 on a periodic and/or event-driven basis.
A well-known goal that multiple processor call processing systems (such as the system 2500 shown in FIG. 25) attempt to achieve with respect to call admission control (CAC) and load balancing is to maintain the QoS commitment for the existing calls (failing to introduce delays or packet loss in packet voice environments) while maximizing call capacity, and ultimately maximize efficient use of the call processing system. In particular, the goal is to provide an optimally efficient call handling situation in which all individual call processing units in a multiple processor call processing system are evenly and homogeneously (with respect to call type) loaded. Thus, ideally, call admission control and new call blocking will thus only occur where all these call processing units are already fully or nominally loaded.
To illustrate, refer to a simplified capacity diagram of a 6 PMCi call processing system 105 shown in FIGS. 1A-1C, generally consistent with the system 2500 shown in FIG. 25. As shown in each of FIGS. 1A-1C, each box within each PMC1 . . . PMC6 represents a call, with a shaded box 110 representing a voice call, a diagonally hatched box 112 representing a streaming call, and a transparent double-sized box 114 representing an interactive call. Each container 107 represents the capacity of a given PMCi. In FIG. 1A, the PMC1 . . . PMC6 of the multiple processor call processing system 105 are evenly and homogeneously loaded; in FIG. 1B, the load is even but not homogeneous; and in FIG. 1C the load is neither homogeneous nor even.
The risk presented in FIG. 1B is that if there is congestion in a given PMCi, most calls within such PMCi might be of the same nature thus making any call processing remedy more difficult. The risk posed in FIG. 1C is that while there is unused capacity on some PMCis (e.g. PMC2, PMC4, PMC6), other PMCis (e.g. PMC1, PMC3, PMC5) are very close to their nominal load and may not be able to provide sufficient service level guarantees or quality of service to the calls they are handling. As a result, the goal should be to maintain even and homogenous loads, as in FIG. 1A. It should also be noted that even this situation, the call processing system 105 may reach a loading condition where all the PMC1 . . . PMC6 are nominally loaded, and that the system cannot admit further new calls, but this situation happens less often, if the load is even.
In order to load balance a multiple processor call processing system, it is important to be able to estimate the resource utilization (in terms of e.g. bandwidth or processor loading) on each call processing unit at any given time. Once the per PMCi estimated loading is determined, one can prospectively load balance by admitting new calls based on which PMCi has free resources to handle the call. A simple brute force approach is to assume that each call is taking up its peak resource requirement, and that the estimated load is based on this peak resource requirement multiplied by the number of calls being handled. This obviously results in inefficient resource under-utilization, and cuts against some of the perceived variable bandwidth advantages afforded by packet voice transmission.
Another known technique for estimating resource utilization is based on a relationship between peak and average resource requirements for a given call type, e.g.:
                                                                        estimated                                                                                resource                                                                                utilization                                                                                for                                                                                a                                                                                given                                                                                call                                                                                type                                                    =                              2            *            peak            *            average                                peak            +            average                                              (        1        )            Once the estimated resource utilitization for the different call types being or expected to be handled within the call processing system is known, each PMCi's loading can be estimated by determining how many of each type of calls are being serviced and multiplying each by this estimated resource utilization. Resources can be reserved within each of the PMCi consistent with the estimated resource utilization and additional capacity can be determined based on remaining unreserved resources.
FIG. 2 illustrates a plot of the estimated resource utilization curve 202 corresponding to the above equation (1) versus the average resource utilization. It is obvious that in this method, when the average is significantly smaller than the peak resource requirement, the estimated resource utilization approaches twice the average resource requirement (e.g. approaches line 204 having a slope of 2 in FIG. 2). Otherwise, the estimated resource utilization is always a 1 to 2 multiple of the average (e.g. always greater than, but approaching line 206 having a slope of 1). Ergo:average<<peakestimate=2×average  (2)average≅peakestimate=average=peak  (3)
Thus, using this estimated resource utilization technique results in a overly-conservative loading estimation for the PMCis (i.e. more resources are estimated being used than is actually the case) and can potentially result in a false determination that a given PMCi is at nominal loading or overloaded when it still in fact has capacity. The call processing system can refuse to provide additional calls to the so-overloaded PMCi which still in fact has capacity, and worse, may prematurely refuse to admit further calls to the system (assuming the remaining PMCis are estimated at nominal or greater loading). On the other hand, it is unlikely that any one PMCi will be overbooked or oversubscribed, thus this technique is perceived at least being QoS friendly.
Further, this estimated resource utilization technique does not take into account the number of calls of a given call type being handled by a given call processing unit. It is well-known that the greater the number of calls of a given type are being serviced by a given PMCi, the less is the chance that these behave all the same way or utilize the same amount of resources. For example, it is highly improbable that, in the case of packet voice with silence suppression, that all handled calls will be in the more resource demanding active, vs. silent state. To account for this, it is generally known that a provisionable reservation coefficient may be used to augment the above to permit the PMCis and the call processing system generally to accept more calls than the above-described conservative estimation technique calls for, and in the typical and aggressive cases, more than the PMCis and the call processing system as a whole can actually handle. This overbooking is justified, especially as the number of calls increases and the probabilistic nature of the calls with respect to actual resource utilization (the probabilistic nature of calls, as used herein, means that the resource utilization for each call varies by time and may have any of a finite or infinite number of values within known limits). However, in known systems, the reservation coefficient, although provisionable, is constant within different hours of a day or days of a week, unless a system operator manually alters or updates it.
Therefore, it would be advantageous in a multiple processor call processing system if critical resource utilization could be better predicted, and consequently more accurate call admission and load balancing decisions could be made without detracting from overall system performance.

Method and apparatus for call event processing in a multiple processor call processing system


The IBDV VP2 icosahedral superstructures are made up of 12 empty VP2 dodecahedral capsids, lacking genetic material. They have a size of approximately 60–68 nm in diameter and contain 720 IBDV VP2 subunits. These VP2 icosahedral superstructures can be used for vaccinal and diagnostic purposes.

Infectious bursal disease (IBD), or Gumboro Diesease, is an acute course viral disease mainly affecting broiler chickens during the growth stage. This highly contagious disease was first disclosed by Cosgrove in 1962 in the U.S. city of Gumboro (Del.). Currently, this disease is spread worldwide, and the IBD outbreak rate has increased, with a high massive mortality rate (50–75%) caused by highly virulent strains of the virus.
The disease is caused by the infectious bursal disease virus (IBDV), which has a very noticeable tropism of the lymphoid cells located in the bursa of Fabricius, causing a selective elimination of lymphocyte B precursors and, accordingly, the establishment of a severe immunosuppression. Therefore, infection by IBDV causes high massive mortality rates for two reasons: i) the actual infective cycle of IBDV, and ii) opportunistic infections of other pathogens affecting the immunodepressed animals. The immunosuppressive effect of IBDV also reduces the response of the animals to vaccines against other avian pathogens.
The economic importance of this disease is fundamentally based on these two aspects: on one hand, the high mortality rate caused by some IBDV strains in 3-week old chickens, and even older, and on the other hand, the second clinical manifestation of the disease consisting of a prolonged immunosuppression of the birds infected at early ages. The main sequelae associated to said immunosuppression are: dermatitis gangrenosa, anemia-hepatitis syndrome with inclusion bodies, E. coli infections and failures in the efficacy of other vaccinations, such as the vaccinations against the Newcastle disease and infectious bronchitis.
IBDV virions are extraordinarily resistant to environmental conditions and persist in the environment for a period of at least 4 months. The virus is transmitted through water, food or excrement, but there is no vertical transmission through the egg, nor are there chronic carriers of the disease. Therefore, success in controlling Gumboro disease is based on the application of strict hygiene and disinfection programs in the facilities, together with the preventive vaccination of reproducers and progeny. Immunization of reproductive birds has a special importance in the transmission of passive immunity to the progeny; however, the presence of said passive immunity can interfere in the efficacy of the vaccination of the progeny.
IBDV is the prototype of the genus Avibimavirus of the Birnaviridae family, a double-stranded RNA (dsRNA) virus. IBDV virions have a size of 60–65 nm, they are not enveloped and have icosahedral symmetry. The viral capsid, formed by a single layer of an average thickness of 9 nm, is constituted of two proteins: VP2 (40 kDa) and VP3 (32 kDa), which are assembled to form a non-spherical T=13 capsid. The genome of the virus is constituted of two double-stranded RNA segments of 3,129 bp (segment A) and 2,759 bp (B), respectively. Segment A contains two Open Reading Frames (ORF) called A1 and A2. ORF A1 encodes a 106 kDa protein with autoproteolytic capability. Processing of the protein gives way to three mature protean products: VP2 and VP3, which form the viral capsids, and VP4, a non-structural protein with proteolytic activity. ORF A2 encodes for a non-structural 16.5 kDa protein (VP5), the activity of which is unknown. Segment B encodes a single, 90 kDa protein, VP 1, with RNA-dependent RNA polymerase activity, which is found in purified virions associated to the ends of both viral genome fragments.
Segment A encodes for a precursor polyprotein in the 5′-VPX-VP4-VP3-3′ order. The precursor polyprotein is processed through different proteolytic processes to produce the definitive mature viral proteins, VP2 and VP3, structural components of the IBDV virion, and VP4, the viral protease responsible for processing the precursor polyprotein. It is known that during viral infection, VP2 is initially synthesized as a precursor (VPX), the C-terminus end of which is processed by proteolysis to the mature form during capsid assembly, but the exact cutting points and the proteins involved in said processing are unknown. This processing is essential in the capsid assembly process. VP2 contains the antigenic regions responsible for the induction of neutralizing antibodies, serotype and strain specificity, whereas VP3 is considered the group-specific antigen.
The serological response to the virus is mainly focused on the proteins of the capsid, VP2 and VP3. The VP3 protein is immunodominant, being invariably recognized by sera of convalescent chickens and hyperimmune animals. However, the majority of the monoclonal antibodies capable of neutralizing infectiveness of the virus recognize conformational epitopes in the VP2 protein.
Several vaccines have been disclosed which contain attenuated live IBDV (U.S. Pat. No. 5,632,989), as well as vaccines with inactivated IBDV, as well as recombinant subunit vaccines containing the IBDV VP2 protein, expressed in several systems, for example, bacteria, yeasts, viruses, etc., normally in the form of a fusion protein (U.S. Pat. No. 5,605,792 and U.S. Pat. No. 5,605,827). The possibility that VP2 forms empty chimeric capsids in combination with all or part of IBDV VP3 (U.S. Pat. No. 5,788,970, Hu et al., 1999; Wang et al., 2000; Martínez-Torrecuadrada et al., 2000a; Martínez-Torrecuadrada et al., 2000b; Cheng et al., 2001) is also known.

This patent is subject to a terminal disclaimer.

Icosahedral superstructure of VP2 of infectious bursitis virus (IBDV) and the application thereof


Methods and apparatus are provided for programmable decoding of a plurality of code types. A method is provided for decoding data encoded using one of a plurality of code types, where each of the code types correspond to a communication standard. The code type associated with the data is identified and the data is allocated to a plurality of programmable parallel decoders. The programmable parallel decoders can be reconfigured to decode data encoded using each of the plurality of code types. A method is also provided for interleaving data among M parallel decoders using a communications network. An interleaver table is employed, wherein each entry in the interleaver table identifies one of the M parallel decoders as a target decoder and a target address of a communications network for interleaved data. Data is interleaved by writing the data to the target address of the communications network. The communications network can comprise, for example, a cross-bar switch and/or one or more first-in-first-out buffers.

FIG. 1 is a block diagram of a typical digital communication system 100. As shown in FIG. 1, a digital source 110 produces a sequence of binary messages. Thereafter, an exemplary channel encoder 120 uses a forward error-correction coding scheme, to increase the redundancy of the source messages and to transform the source messages into encoded messages (often referred to as codewords). Generally, the error correction coding provides increased resilience to channel noise. A modulator 130 transforms the encoded messages into signals that are appropriate for transmission over a channel 140. These signals enter the channel 140 and are typically corrupted by noise and interference on the channel.
At the receiver, a demodulator 150 receives the noisy signals from the channel 140 and converts the received signals into blocks of symbols. A channel decoder 160 exploits the redundancy introduced by the channel encoder 120 to attempt to correct any errors added by the channel 140 and to restore the original messages. A number of different decoding techniques have been proposed or suggested to decode signals encoded using error correction codes
Error correction encoding techniques for wireless communication systems often employ convolutional or turbo coding of the data before the signal is modulated so that errors introduced by noise and interference on the channel may be corrected. Generally, a convolutional code is an error correction code where each m-bit string is transformed into an n-bit symbol, where m/n is the code rate (n is greater than or equal to m) and the transformation is a function of the previous k information symbols, where k is the constraint length of the code. Turbo codes are another class of error correction codes that are said to approach the theoretical limits imposed by Shannon's theorem with reduced decoding complexity relative to the convolutional codes that would be required for similar performance.
Increasingly, communication devices must support multiple communication standards. For example, each of the WiMAX (Worldwide Interoperability for Microwave Access) (an IEEE 802.16 wireless broadband standard), LTE (Long Term Evolution) (a 3GPP 4G technology), UMB (Ultra Mobile Broadband) (a CDMA Development Group and 3rd Generation Partnership Project 2) and WCDMA (Wideband Code Division Multiple Access) communication standards require support for at least one convolutional encoding technique and at least one convolutional turbo encoding technique (or a combination thereof), at one or more rates.
Thus, a need exists for reconfigurable or programmable decoders that can support multiple communication standards. A further need exists for a programmable coder/decoder (codec) that supports encoding or decoding (or both) and symbol processing functions for a number of different existing and future communication standards.

Methods and apparatus for programmable decoding of a plurality of code types


A video filter unit is described which is implemented as a three-stage filter comprising a vertical filter, a horizontal decimation filter, and a horizontal interpolation filter. The three stages of the filter unit preferably connect serially with the vertical filter comprising the input first stage, the horizontal decimation filter comprising the second stage and the horizontal interpolation filter comprising the third stage which provides the output filtered image from the filter unit. As such, the video data to be filtered is provided to the vertical filter which provides its output to the horizontal decimation filter. After horizontal decimation, which can be disabled if desired (i.e., no horizontal decimation), the video data is then horizontally interpolated. The horizontal interpolation filter stage can also be disabled if desired. The vertical filter can be configured to operate either as a decimation filter or an interpolation filter. The vertical filter is a four-tap filter and thus calculates weighted averages of four video values (e.g. luminance values) at a time. The horizontal decimation filter preferably is implemented as a two-tap filter and thus averages two video values at a time. Lastly, the horizontal interpolation filter comprises an eight-tap filter and, accordingly, calculates a weighted average of eight video values.

Not applicable.
Not applicable.
1. Field of the Invention
The present invention generally relates to video processing systems. More particularly, the present invention relates to filtering pixel data in a, video processing system. More particularly still, the invention relates to filter architecture for a digital video processing system.
2. BACKGROUND OF THE INVENTION
The consumer electronics industry has experienced a dramatic explosion in product development over the last 20 years. This explosion has been fueled by consumer demand coupled with significant advances in semiconductor technology that have lead to lower cost semiconductor devices incorporating significantly more functionality than previously possible. For example, a hand-held calculator from 20 years ago provided the ability to perform rudimentary mathematical operations. Today, a hand-held device can provide much of the functionality of a desktop computer system.
The visual display of information to the user is of particular importance to the consumer electronics industry. The most notable examples of visual displays include televisions and personal computers. Other types of consumer electronics, including stereo receivers and hand-held computers, also include visual displays. Visual displays typically comprise a grid of evenly spaced xe2x80x9cpixels.xe2x80x9d FIG. 1, for example, shows a portion of a pixel grid 20 with a plurality of pixel lines 22. Each line includes multiple pixels denoted by the symbol xe2x80x98Xxe2x80x99. A typical television screen format includes 480 lines of pixels with each line comprising 720 pixels (i.e., 720xc3x97480). The size and spacing of the pixel lines in FIG. 1 have been exaggerated for clarity.
Each pixel in a line is represented by one or more data values. For example, each pixel can be represented in a xe2x80x9cRGBxe2x80x9d format which includes red, green, and blue color components. Alternatively, each pixel can be represented in a xe2x80x9cYUVxe2x80x9d or xe2x80x9cYCrCbxe2x80x9d format. In either the YUV or YCrCb formats, the xe2x80x9cYxe2x80x9d value represents luminance (xe2x80x9clumaxe2x80x9d) which determines the brightness of the pixel. The U and V values represent chrominance (xe2x80x9cchromaxe2x80x9d) components which determine color and are calculated as the difference between the luminance components and the red and blue color values; that is, U=Yxe2x88x92R and V=Yxe2x88x92B. The Cr and Cb values also represent chrominance and are scaled versions of the U and V chrominance values.
Video systems often represent images digitally. That is, each pixel comprising the image is represented by a digital YCrCb value, or a value in accordance with another format. To facilitate the transmission and storage of moving pictures, which generally involve voluminous amounts of pixel data, various encoding and compression techniques are used to process the data. One such technique is the Moving Pictures Experts Group (MPEG) standard commonly implemented in digital video disk (DVD) drives and other types of video equipment.
It is often desirable to filter the digital pixel values which represent a moving image. For example, common interchange format (xe2x80x9cCIFxe2x80x9d) images are formatted as 352xc3x97240 (i.e, 352 columns and 240 lines). To display a CIF image on a 720xc3x97480 television displays requires the conversion of the 352xc3x97240 CIF pixel format to the 720xc3x97480 television format. Part of the conversion involves xe2x80x9cupsamplingxe2x80x9d (also referred to as interpolating 352 pixels in each line to 720 pixels and 240 lines to 480 lines). Filtering pixels across a line is called xe2x80x9chorizontal filteringxe2x80x9d and thus a horizontal filter that converts a line of pixels into more pixels is referred to as a horizontal interpolation filter. It may also be desirable to expand an image vertically. Such a process is performed by a xe2x80x9cvertical interpolation filterxe2x80x9d which filters pixel values in a vertical column of pixels.
Video data must be provided to the display device at a fixed rate which typically is 30 frames of video per second for television. A frame refers to the set of all pixels on the screen (720xc3x97480) at each instance in time. A display rate of 30 frames per second is fast enough to appear to the human eye as a continuous image, and not a series of images captured at discrete points in time. All of the filtering and other processing that is to occur on a single frame therefore must be performed in less than one-thirtieth of a second.
The ability to filter digital video images has fueled a demand for additional types of filtering. For example, it has become desirable to reduce the size of an image. This process is referred to as xe2x80x9cdecimation.xe2x80x9d Additionally, it is desirable to increase the quality of video images. As the requirements for video filters increase, it is imperative to develop high quality video filters that can operate more efficiently and be produced at a lower cost. Such filters will provide high quality video images decimated or interpolated from an initial image at the desired display rate, but do so in an efficient manner so as to minimize system cost.
The deficiencies noted above are solved in large part by a video filter unit implemented as a three-stage filter comprising a vertical filter, a horizontal decimation filter which reduces the horizontal dimension of an image, and a horizontal interpolation filter which expands the horizontal dimension of an image. The three stages of the filter unit preferably are connected serially with the vertical filter comprising the input first stage, the horizontal decimation filter comprising the second stage and the horizontal interpolation filter comprising the third stage. With this filter archtiecture, the input video data to be filtered is provided to the vertical filter which provides its output to the horizontal decimation filter. The vertical filter can be configured to operate either as a decimation filter or an interpolation filter. After horizontal decimation, which can be disabled if desired (i.e., no horizontal decimation), the video data is then horizontally interpolated. The horizontal interpolation filter stage can also be disabled if desired.
The vertical filter is implemented in the preferred embodiment as a four-tap filter and thus calculates weighted averages of four video values (e.g. luminance values) at a time. The horizontal decimation filter preferably is implemented as a two-tap filter and thus averages two video values at a time. Lastly, the horizontal interpolation filter comprises an eight-tap filter and, accordingly, calculates a weighted average of eight video values. By placing the eight-tap horizontal interpolation filter as the last stage in the video unit, the horizontal interpolation filter can provide output video data at the display rate of the video system in which the video filter unit operates. If the horizontal interpolation filter was included in an earlier stage of the filter, the filter would have to operate at a higher rate to produce output values at the required display rate. By permitting the high tap count horizontal interpolation filter to operate at the slowest rate possible, that filter can be implemented with a lower power and lower cost design.

Digital video filter sequence for bandwidth constrained systems


In one embodiment, the bulk input voltage is used to form a reference signal that is used for controlling a switching power supply system to operate in a power overload operating mode.

The present invention relates, in general, to electronics, and more particularly, to methods of forming semiconductor devices and structure.
In the past, the semiconductor industry utilized various methods and structures to implement skip cycle detection and output power overload detection in switching power supply systems such as pulse width modulated (PWM) systems. Skip cycle detection, often referred to as burst-mode detection, was often used to reduce power dissipation in the power supply system during light output load conditions. Power overload detection was used to determine if the amount of output power supplied by the system was greater than the desired maximum power dissipation that was allowable by the particular implementation of the power supply system. One example of a switching power supply controller that had both power overload detection and skip cycle detection was the NCP1231 supplied by ON Semiconductor of Phoenix, Ariz.
Output power overload detection methods generally compared the value of a signal representative of the output voltage formed by the power supply system to a fixed reference voltage within the power supply controller. One problem with this method was that the output power delivered to the load could also increase if the value of the bulk input voltage supplied to the power supply system changed. In such a situation, the power supply controller of the power supply system could not accurately detect the power overload condition.
Skip cycle detection circuits also generally compared a signal representative of the value of the output voltage to a fixed reference voltage within the power supply controller. If the value of the bulk input voltage supplied to the power supply system changed, the skip cycle detection method could cause the power supply system to enter the skip cycle mode before the power required by the load decreased to the desired value. Consequently, the power supply system would not supply enough power to the load.
Accordingly, it is desirable to have a power supply control system and method that more accurately detects the power supplied by the power supply control system, that accurately detects the power supplied by the power supply control system when the bulk input voltage changes, and that more accurately detects the load power at which to enter the skip cycle mode.
For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device that controls current through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel or P-Channel devices, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with the present invention. It will be appreciated by those skilled in the art that the words during, while, and when as used herein are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay between the reaction that is initiated by the initial action.

Power overload detection method and structure therefor

Semiconductor Components Industries, L.L.C.


An anode region 106 is formed on a bottom portion of a trench 105 in which a gate electrode 108 is formed or in a drift region 102 immediately under the trench 105. A contact hole 110 is formed in the trench 105 at a depth reaching the anode region 106. A source electrode 112 is embedded in the contact hole 110 while interposing an inner wall insulating film 111 therebetween. The anode region 106 and the source electrode 112 are electrically connected to each other in a state of being insulated from the gate electrode 108 by the inner wall insulating film 111.

Heretofore, as this type of technology, for example, one described in a literature shown below has been known (refer to Patent Literature: Japanese Patent Laid-Open Publication No. 2005-183563). This literature describes a technology of a semiconductor device including: a trench-type transistor in which a gate electrode is embedded in a trench; and a diode in which a hetero semiconductor region is used as an anode and a drift region is used as a cathode. The hetero semiconductor region that composes the anode of the diode is arranged along such gate electrodes, which are adjacent to each other, at a predetermined interval therewith so as to be sandwiched between the gate electrodes concerned.

Semiconductor device and manufacturing method of the same


The system of the invention includes: a storage portion for storing the information as to installation sites of a plurality of output apparatuses and their functional information (e.g., shop list table in the print service server); and an output apparatus candidate selecting device for extracting the candidates for the nearby output apparatus capable of producing an output of the image data, with reference to the information as to installation sites of the output apparatuses with their functional information stored in the storage portion, based on the image data input via the network from a portable terminal device and the information as to the current position of the portable terminal device. The image data is transferred to the output apparatus selected by the user from the output apparatus candidates presented by the output apparatus candidate selecting device.

(1) Field of the Invention
The present invention relates to a data transmission apparatus (e.g., a print server) for supporting printing of image data on-site or at a site remote from the office. The present invention also relates to an image data communication system in which a data transmission apparatus, a portable terminal device capable of data transmission and reception with the help of a portable telephone, PHS phone or the like, and a printer, are connected to a network.
(2) Description of the Prior Art
The recent development and spread of the internet has made possible exchange of image data etc., via electric mail. As examples of terminal devices, portable terminal devices that can deal with diverse usage environments have been developed. Under such circumstances, the size of the display device provided in such a terminal device is limited to being approximately proportional to the size of the terminal device.
For example, a portable notebook computer may have a relatively large display device and have high enough capacities (of memory and image processing) for displaying image data.
On the contrary, portability-oriented, hand-held information devices such as electronic notebooks etc., use relatively small display devices taking into account their compactness and thinness, and have a simple configuration, and simple capability of processing image information.
Further, with the development in the field of data transmission, not only text data (character data) can be handled as e-mail, but also image documents scanned as electronic data by internet fax, network scanners, or the like can become transmitted as e-mail.
Under these circumstances, there often occur many instances where data needs to be printed on-site. At present, though mobile printing and other technologies are put into practice, it is very difficult for mobile printing to handle data if that data is bulky.
Japanese Patent Application Laid-Open Hei 10 No. 63601 discloses a data printing system for printing data from a site away from the user's office, wherein a print request with printing data is transmitted to the user's office from on-site, and the user is able to immediately obtain printouts with a simple operation when the user returns to the office.
This technology disclosed in the above publication, however, only provides printing at the office, so that it is impossible for the user to obtain the printouts of the data on-site. Further, since the system for the technology disclosed in the above publication needs a dedicated office server, it is not a system which can be openly accessed by any user.
There are businesses that provide printing services from electronic data. However, a person who is a stranger without good knowledge of a certain locale and who does not have information as to the nearby printing service shop that can process their data to be printed will have difficulty in locating such a shop and performing the printing.

Data transmission system for printing data at a site remote from a home location/office


A method for the purification of alcohols from organic soluble impurities has been discovered comprising treating the crude alcohol with a cyclic anhydride followed by an aqueous base and extracting the corresponding half-ester into aqueous solution leaving the impurities in organic solution. This method is particularly useful for the separation of chiral, nonracemic alcohols from the corresponding antipodal ester (the mixture resulting from an enzymatic kinetic resolution) because the separation is non-chromatographic and the enantiomeric integrity of the products is maintained.

Purification as used herein encompasses the separation of an alcohol from other inert contaminants. Although a number of purification techniques for alcohols are known, the separation of a desired alcohol from closely related species is still difficult, especially on a large scale. As known, alcohols are valuable commodity chemicals with a wide range of uses, such as, for example, synthetic intermediates. Simple and versatile methods for purification that may be easily commercialized are badly needed.
One area of particular need is in the separation of chiral, nonracemic alcohols from their corresponding antipodal esters, the mixture of which may result from an enzymatic kinetic resolution. These enzymatic resolution methods typically include enzymatic hydrolysis, transesterification, or esterification. The separation of the antipodal ester from the racemic alcohol is particularly challenging because they are closely related species and the optical purity of product and/or substrate must be substantially maintained. The resulting separated compounds are of growing interest to the pharmaceutical, agricultural, and fragrance industries as optically active synthetic intermediates and building blocks.
There are several known methods for separating enzymatic resolution product mixtures. One known method is used for systems in which the chiral center resides in the carboxylate portion of the molecule (rather than the alcohol portion of the molecule), as shown in Figure I-1, below. In these systems, the enzymatic kinetic resolution (hydrolysis) results in a mixture of the unreacted ester and the corresponding antipodal carboxylic acid. Separation of the product carboxylic acid from the unreacted ester is usually accomplished simply by aqueous base extraction. For enzymatic resolution products where the chiral center resides in the alcohol portion of the molecule, (as shown in Figure I-2, below) separation is often accomplished by liquid chromatography. This technique, however, is generally only useful for small scale operations. Both reaction schemes are shown below in Figure I where R represents general organic substituents.


An earring assembly is described including an earring and an accessory. The earring includes a fastening mechanism and an ornamental portion. The accessory is removably attached with the earring and is configured to corresponding mate with the ornamental portion to enhance and compliment the ornamental appearance of the earring. The accessory is readily removed and replaced by a system of posts that engage catches and lock the accessory in position with the earring. The back of the ornamental portion has posts that mate with notches defined in the catches positioned on the accessory. The ornamental portion also includes a lip. The accessory further includes biasing means augmenting the system of posts and catches to ensure the secure positioning of the accessory against the lip of the ornamental portion of the earring.

1. Technical Field
The present disclosure relates to earrings. More particularly, the present disclosure relates to earrings having at least one attachable accessory.
2. Background of Related Art
Jewelry having additional accessories includes a single replaceable component, interchangeable components, and supplemental components to a permanent setting. The additional components can include costume jewelry or supplemental settings including jewels connected to the earring by mechanisms such as screws into threaded sockets, loops onto wires, biased tongues into sockets, and bias means. These mechanisms strive to bring a balance between providing a secure connection for the additional component and an ease of removing and replacing the components.
A configuration for an earring including removable components is described in U.S. Pat. No. 5,836,176 to Lichtenstein et al. Lichtenstein et al. teaches an ear lobe securing assembly configured as a wire having a terminal end that is secured by a hinge arm when worn. A pin having a loop on one end and a stop on the other is configured for the positioning of the ornamental jewelry. The loop is threaded onto the open end of the wire and is configured to hang freely from the lowest point of the wire. One or more ornamental components can be positioned on the pin between the loop and stop. Lichtenstein et al. is limited in its style of ornamentation by the requirement to thread each component onto the wire. Further, to change the configuration of the Lichtenstein et al. earring is excessively time consuming requiring the steps of taking off the ear of the wearer, disassembled, the pin reassembled with new ornaments, installing the pin back in position on the wire, and positioning the earring in the ear of the wearer.
In U.S. Pat. No. 6,058,737 to Domagala, a closeable loop wire earring is described that enables a supplemental setting gemstone or component to be threaded onto and positioned on the wire. Domagala is constrained, like the Lichtenstein et al. configuration by the necessity for threading the supplemental component along the wire. This also limits the manner and ability of the supplemental component can be positioned relative to a permanent setting.
In U.S. Design Pat. No. 6,131,408 to Gill, a ring having a readily attachable enhancer is described. The enhancer is an additional setting configured for positioning in the vicinity of the primary setting of the ring. The enhancer has a channel type shape configured for being positioned on and at least partially around the inner circumference and sides of the annular surface of the ring below the primary setting. The enhancer has a stem with a bulbous tip positioned in a bottom of the channel configured for positioning into a bore or cavity in the ring. The bore has an o-ring defining an aperture configured for receiving and retaining the bulbous tip. Gill is limited by the method of attachment of the enhancer to the ring because the ability of the enhancer to be properly positioned is totally dependent on the o-ring to stem and bulb interface. Open o-ring interfaces are vulnerable to degradation of the elasticity, tearing, and becoming fouled with dirt over time. Further, while the security of the enhancer is at least partially improved by the position of the wearer's finger. The Gill configuration is stated as reducing the ring by one quarter of a size as a result of the enhancer being mounted on the inner surface of the ring.
A continuing need exists for an earring configured for easily attaching an ornamental accessory to the earring.


Gun for cutting out sheet metal, of the type comprising an electrode (26) within a nozzle (19) with an outlet conduit (23) for a plasmagenic gas, mounted for free axial displacement relative to an electrode carrier (14), characterized by a drive shaft (7) for the rotation of the electrode carrier (14) and of the nozzle (19) about an external axial bearing pivot (22) of the nozzle and an outlet conduit (23) for plasmagenic gas which is eccentric relative to said axial pivot (22).. This gun permits carrying out small cutouts of sheet metal by rotation of a plasma arc issuing from the conduit (25) rotating about the pivot (22).. Application particularly to unbuttoning spot welded sheets.

The present invention relates to a gun for cutting out sheet metal, of the type comprising a body having an axis and supporting coaxially, at one end, a cutting head comprising an electrode-carrying assembly extending into a nozzle comprising a plasmagenic gas outlet, for cutting out circles of sheet metal, particularly for the formation of small cutouts about spot welds between two pieces of sheet metal, so as to separate them. This operation, which is commonly called "unbuttoning" of spot welded metal sheets is at present effected mechanically:
by hammer and chisel;
by grinding;
by a special cutting tool mounted on a drill.
None of these means permits performing properly and rapidly this type of operation, particularly for automobile repair or if access to the welds is limited.
In the first case, manual cutting out is difficult and imprecise and gives rise to deformations in the piece that one would like to reuse. Grinding, although neater, is a long and delicate operation, because the tool used is bulky. Cutting out requires a costly tool, whose use is delicate and which moreover gives rise to deformations of the support sheet metal.


A method and apparatus to control an electro-mechanical transmission during a shift event, including identifying a fault in an off-going clutch, is provided. The method includes deactivating an off-going torque-transfer clutch, monitoring slippage of the off-going torque-transfer clutch, and limiting a change in operation of an electrical machine operatively connected to the transmission until the slippage of the off-going torque-transfer clutch exceeds a threshold. Limiting a change in operation of the electrical machine comprises limiting an output torque of the electrical machine, comprising limiting a time-rate change in the output torque and limiting a magnitude of the output torque. The limit of the change is discontinued when the slippage of the off-going torque-transfer clutch exceeds the threshold.

Fuel/electric hybrid powertrain architectures comprise torque-generative devices, including internal combustion engines and electric machines, which transmit torque through a transmission device to a vehicle driveline. One such transmission includes a two-mode, compound-split, electro-mechanical transmission which utilizes an input member for receiving motive torque from an internal combustion engine, and an output member for delivering motive torque from the transmission to the vehicle driveline. Exemplary electro-mechanical transmissions are selectively operative in fixed gear modes and continuously variable modes through actuation of torque-transfer clutches. A fixed gear mode occurs when rotational speed of the transmission output member is a fixed ratio of rotational speed of the input member from the engine, typically due to actuation of one or more torque-transfer clutches. A continuously variable mode occurs when rotational speed of the transmission output member is variable based upon operating speeds of one or more electrical machines. The electrical machines can be connected to the output shaft via actuation of a clutch, or by direct connection. Clutch actuation and deactivation is typically effected through a hydraulic circuit, including electrically-actuated hydraulic flow management valves, pressure control solenoids, and pressure monitoring devices controlled by a control module.
Engineers implementing powertrain systems having electro-mechanical transmissions are tasked with developing shifting schemes between various operating modes, including the fixed gear modes and the continuously variable modes. Execution of a shift typically includes deactivating an off-going clutch, and continuing operation or actuating an oncoming clutch. A control system is typically programmed to execute tasks during a transmission shift to effect a smooth shift transition substantially imperceptible to the vehicle operator. Such control tasks include synchronizing clutch speed of the oncoming clutch by controlling operating parameters of the engine and electrical machines. Operating parameters include torque outputs and operating speeds of the engine and electrical machines. However, if a fault were to unknowingly occur in deactivating the off-going clutch, the control system may act to control the operating parameters of the engine and electrical machines to effect the shift transition even though the off-going clutch has not deactivated, potentially resulting in operator dissatisfaction.
Therefore, there is a need to for a method and apparatus to control operation of a hybrid transmission during gear shifting events, to address concerns mentioned hereinabove.

Method and apparatus for controlling an electro-mechanical transmission during a shift execution


Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a mixed-mode memory operation in the design. The mixed-mode memory operation specifies memory access having different read and write data widths using a plurality of embedded memory blocks each having a fixed data width. The synthesizing further includes determining a reduced number of embedded memory blocks to implement the mixed-mode memory operation, and modifying the mixed-mode memory operation to remap the memory access to the reduced number of embedded memory blocks.

Programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), field programmable systems on a chip (FPSCs), or other types of programmable devices) may be configured with various user designs to implement desired functionality. Typically, the user designs are synthesized and mapped into configurable resources (e.g., programmable logic gates, look-up tables (LUTs), embedded hardware, or other types of resources) and interconnections available in particular PLDs. Physical placement and routing for the synthesized and mapped user designs may then be determined to generate configuration data for the particular PLDs.
Many PLDs today include dedicated memory resources to facilitate efficient implementation of memory components such as random access memories (RAMs), read only memories (ROMs), and first-in first-out (FIFO) memories as may be needed in the user designs. Such dedicated memory resources are typically embedded in PLDs as one or more blocks of static RAM (SRAM), dynamic RAM (DRAM), and/or flash memory that can be configured together with other configurable resources of PLDs to implement memory components having desired functionalities. For example, some embedded memory blocks include circuitry and logic that can be utilized to implement a memory component that can read and write data having mixed widths. That is, those embedded memory blocks support mixed-width mode or mixed-mode memory access and storage where the read data width and the write data width can be different.
However, incorporating the circuitry and logic to support a mixed-width mode may undesirably increase the size and complexity of PLDs having embedded memory blocks, which is especially problematic for low-power, small-footprint PLD, for example, in mobile devices. On the other hand, implementing mixed-width mode memory components of user designs without dedicated circuitry and logic would require user designs to organize multiple embedded memory blocks into particular groupings, which may under-utilize the embedded memory blocks and waste valuable memory resources.
Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.

Mixed-width memory techniques for programmable logic devices


An apparatus (10) is provided for controlling the flow of a fluid. The apparatus (10) includes a housing (12) having an inlet port (14), an outlet port (16), and a bypass port (18). A throughput block (26) is contained within the housing (12). The throughput block (26) has a number of cylinders (28) formed therein. A number of pistons (34) are received within the cylinders (28). Each piston (34) can move within a corresponding cylinder (28) between a first position and a second position. En the first position, the piston (34) prevents fluid communication between the inlet port (14) and the outlet port (16) and allows fluid communication between the inlet port (14) and the bypass port (18). In the second position, the piston (34) prevents fluid communication between the inlet port (14) and the bypass port (18) and allows fluid communication between the inlet port (14) and the outlet port (16).

It is often desirable to control the rate at which a fluid, such as a gas, is delivered to an intended destination. For example, gas precursors can be used as doping sources in an ultra-high vacuum molecular beampitaxy technique for producing semiconductor device structures. Because dopant concentrations are directly related to the flow rate of the gas precursors, control of such flow rate is necessary. Furthermore, in some applications, the flow rate of a fluid may need to be varied over a broad dynamic range of several orders of magnitude. Referring again to the example of an ultra-high vacuum molecular beampitaxy process, the flow of gas precursors may be varied over three orders of magnitude during processing in order to produce dopant concentrations ranging from 10.sup.16 to 10.sup.19 cm.sup.-3.
According to one prior technique, control of gas flow was achieved by diluting a precursor gas with an inert gas. Such technique, however, is not desirable with an ultra-high vacuum molecular beamepitaxy system because the addition of an inert gas increases the gas load on the vacuum pumping system. Consequently, in other prior techniques, temperature-controlled or pressure-controlled mass flow controllers were used to vary the flow rate of a gas. These previously developed mass flow controllers, however, suffered from numerous problems. For example, such flow controllers included complex electronics which needed to be recalibrated often. Also, these flow controllers employed mechanical valves which extended from the outside of the controllers into the interior. Fluid could escape from the controllers at such mechanical valves. Yet another problem was that the previously developed flow controllers operated within a limited dynamic range of flow rates, and thus were incapable of varying gas flow over several orders of magnitude. Furthermore, specific flow rates could not be consistently reproduced using such mass flow controllers.


The present invention relates to proteins and nucleic acids related to salt tolerance in plants.

1. Field of the Invention
The present invention relates to proteins and nucleic acids related to salt tolerance in plants.
2. Description of the Background
Soil salinity is a major abiotic stress for plant agriculture. Sodium ions in saline soils are toxic to plants due to its adverse effects on K+ nutrition, cytosolic enzyme activities, photosynthesis and metabolism (1, 2). Three mechanisms function cooperatively to prevent the accumulation of Na+ in the cytoplasm, i.e. restriction of Na+ influx, active Na+ efflux and compartmentation of Na+ in the vacuole (1). The wheat high-affinity K+ transporter HKT1 functions as a Na+-K+ cotransporter, which confers low-affinity Na+ uptake at toxic Na+ concentrations (3). Thus HKT1 could represent one of the Na+ uptake pathways in plant roots. The low-affinity cation transporter LCT1 from wheat may also mediate Na+ influx into plant cells (4). In addition, patch clamp studies have shown that non-selective cation channels play important roles in mediating Na+ entry into plants (5). The Arabidopsis thaliana AtNHX1 gene encodes a tonoplast Na+/H+ antiporter and functions in compartmentalizing Na+ into the vacuole (6). Over-expression of AtNHX1 enhances the salt tolerance of Arabidopsis plants (7).
No Na+ efflux transporter has been cloned from plants. Plants do not appear to have a Na+-ATPase at the plasma membrane (1). It is expected that proton motive force created by H+-ATPases would drive Na+ efflux from plant cells through plasma membrane Na+/H+antiporters (8). Fungal cells contain both Na+-ATPases and Na+/H+ antiporters at the plasma membrane. In the yeast Saccharomyces cerevisiae, plasma membrane Na+′-ATPases play a predominant role in Na+ efflux and salt tolerance (9). In contrast, Na+/H+ antiporters are more important for Na+ efflux and salt tolerance in the fungus Schizosaccharomyces pombe (10).
Recently, several Arabidopsis sos (for salt overly sensitive) mutants defective in salt tolerance were characterized (11, 12, 13). The sos mutants are specifically hypersensitive to high external Na+ or Li+ and also unable to grow under very low external K+ concentrations (13). Allelic tests indicated that the sos mutants define three SOS loci, i.e., SOS1, SOS2 and SOS3 (13). The SOS3 gene encodes an EF-hand type calcium-binding protein with similarities to animal neuronal calcium sensors and the yeast calcineurin B subunit (14). In yeast, calcineurin plays a central role in the regulation of Na+ and K+ transport. Mutations in calcineurin B lead to increased sensitivity of yeast cells to growth inhibition by Na+ and Li+ stresses (15). The SOS2 gene was recently cloned and shown to encode a serine/threonine type protein kinase (16). Interestingly, SOS2 physically interacts with and is activated by SOS3 (17). Therefore, SOS2 and SOS3 define a novel regulatory pathway for Na+ and K+ homeostasis and salt tolerance in plants. The SOS3/SOS2 pathway has been predicted to control the expression and/or activity of ion transporters (17). However, the identities of the transporters regulated by this pathway are not known.
Among the three SOS loci, SOS1 plays the greatest role in plant salt tolerance. Compared to sos2 and sos3 mutant plants, sos1 mutant plants are even more sensitive to Na+ and Li+ stresses (13). Double mutant analysis indicated that SOS1 functions in the same pathway as SOS2 and SOS3 (12, 13). Thus, SOS1 may be a target for regulation by the SOS3/SOS2 pathway.
Accordingly, there remains a need in the art to isolate the SOS1 gene and the protein encoded thereby.
Furthermore, because of limited water supplies and the widespread use of irrigation, the soils of many cultivated areas have become increasingly salinized. In particular, modern agricultural practices such as irrigation impart increasing salt concentrations when the available irrigation water evaporates and leaves previously dissolved salts behind. As a result, the development of salt tolerant cultivars of agronomically important crops has become important in many parts of the world. For example, in salty soil found in areas such as Southern California, Arizona, New Mexico and Texas.
Dissolved salts in the soil increase the osmotic pressure of the solution in the soil and tend to decrease the rate at which water from the soil will enter the roots. If the solution in the soil becomes too saturated with dissolved salts, the water may actually be withdrawn from the plant roots. Thus the plants slowly starve though the supply of water and dissolved nutrients may be more than ample. Also, elements such as sodium are known to be toxic to plants when they are taken up by the plants.
Salt tolerant plants can facilitate use of marginal areas for crop production, or allow a wider range of sources of irrigation water. Traditional plant breeding methods have, thus far, not yielded substantial improvements in salt tolerance and growth of crop plants. In addition, such methods require long term selection and testing before new cultivars can be identified.
Accordingly, there is a need to increase salt tolerance in plants, particularly those plants which are advantageously useful as agricultural crops.

Proteins and DNA related to salt tolerance in plants


A method of two-stage injection molding of an air conditioner outlet vent device is provided, the device including a housing, a plurality of blades pivotably supported by the housing and disposed in parallel to each other within the housing, and a link operatively connecting the blades. The plurality of blades are injection-molded in a secondary injection step subsequent to a primary injection step in which the housing is molded. In the secondary injection step, a molten resin is injected into cavities formed within a mold device in a closed mold state from a plurality of gates provided in portions of the mold device corresponding to projections of the blades. It is thus possible to improve the strength of link shafts and the projections while preventing any malfunction of the blades pivoting and any deterioration of the surface appearance, as well as to increase the degrees of freedom in changing the gate diameter.

1. Field of the Invention
The present invention relates to an improvement in a method of two-stage injection molding of an air conditioner outlet vent device that includes a synthetic resin housing, a plurality of synthetic resin blades, and a link, the blades being pivotably supported by the housing and disposed in parallel to each other within the housing, and the link operatively connecting the blades, wherein the plurality of blades are injection-molded in a secondary injection step subsequent to a primary injection step in which the housing is molded.
2. Description of the Related Art
Conventionally, such a two-stage injection molding method is already known from, for example, Japanese Patent Application Laid-open No. 6-166053.
As shown in FIG. 8, when injection-molding, in a secondary injection step, a plurality of blades 19 each integrally having a blade main body 22, a pair of support shafts 23 projecting from the blade main body 22, a pair of projections 24 projecting from the blade main body 22 at positions displaced to the rear of the support shafts 23, and a link shaft 25 having an axis parallel to the support shafts 23 and being connected to the two projections 24, in the above-mentioned conventional method, a gate 51′ is formed in a mold 42′ so as to inject a molten resin into a cavity 49 corresponding to the blade 19, in a portion corresponding to the rear edge of the blade main body 22 at a position away from the two projections 24.
However, when setting the position at which the molten resin is injected as described above, since the link shaft 25 is the last to be molded, there is a possibility that it might not be filled with sufficient molten resin resulting in an incomplete shape, or even if the external shape is molded, the resin density might be insufficient resulting in an inadequate strength.
In order to avoid such a situation, if an attempt is made to fill the portion corresponding to the link shaft 26 with sufficient molten resin, unnecessary filling pressure is exerted on portions other than the link shaft 25, thus causing the generation of flashing, or over-filling the interiors of shaft holes 21A and 21B of a housing 13 for the left and right support shafts 23 to make it difficult for the blades 19 to pivot. Furthermore, in the case where the injection speed for the blades 19 has to be increased in order to control the molding time for the blades 19 so as to synchronize it with molding of the housing 13 having a small volume, or in the case where a synthetic resin having a high injection speed such as PE, which has a low viscosity, is used, the surface of the blade 19 after completion of the two-stage injection-molding tends to have flow marks, etc., thereby degrading the surface appearance.
Moreover, if the molten resin is injected into the interior of the cavity 49 at a position away from the projections 24 as described above, a weld line tends to occur in a base part of the projections 24, and if talc, etc. is mixed with the molten resin in order to improve the rigidity of the blade 19, the weld strength of the base parts of the projections 24 might decrease resulting in that the strength of the link shaft 25 is not sufficient. Furthermore, since the diameter of a part of the gate 51′ through which the molten resin is injected into the cavity 49, and which corresponds to the blade main body 22, cannot be set greater than the thickness of the blade main body 22, the degrees of freedom in changing the gate diameter are limited.

Method of two-stage injection molding of air conditioner outlet vent device


A probe card assembly has a probe contactor substrate having a plurality of probe contactor tips thereon and a probe card wiring board with an interposer disposed between the two. Support posts contacting the probe contactor substrate are vertically adjustable until secured by a locking mechanism which is coupled to the probe card wiring board. When the posts are secured in a fixed position, the position is one in which the plane of the plurality of probe contactor substrates is substantially parallel to a predetermined reference plane.

1. Field of the Invention
Embodiments of the present invention are directed to a probe card assembly and more particularly to a method and apparatus for providing a probe card assembly with a precisely fixed probe substrate position relative to the reference plane of the probe card.
2. Description of Related Art
A modern probe card assembly used to test wafers of semiconductor chips generally consists of a Printed Circuit Board (PCB) (also referred to as a printed wiring board or probe card wiring board), a probe contactor substrate having probes for contacting the wafer (sometimes referred as a probe head), and an interposer connecting the PCB to the probe contactor substrate.
Probes (also referred to as probe contactors) are generally compliant mechanisms including at least one spring which have some limited range of compliance in a vertical direction (the "z" direction). Some probes have minimal or no compliance. When in use, a wafer under test is urged upward to contact the tips of the probes. In practice, there is some manufacturing process-related z error (non-planarity of the probe tips) caused by film stresses, etch control, assembly control, etc. as well as systemic z errors caused by a warping or curving in the surface of the probe contactor substrate. If the probe contactor substrate is curved or warped, so will be the imaginary surface that goes through the tips (assuming that the probes are of uniform height). Thus some probe tips will contact the wafer first (called the first touch z height) and some probe tips will contact the wafer last (last touch z height). Because probes generally have a limited range of compliance (as small as 50 μm or less for many microfabricated technologies), it is desirable to minimize both the process-related and systemic errors in tip z height. Some errors are most directly related to the fabrication of the probes on the probe contactor substrate rather than the probe card assembly design. However, some errors are usually directly related to the probe card assembly and the way the PCB is mounted with the probe contactor substrate or substrates. The minimization of these latter errors is the subject of the present invention.
In older probe card applications, a prober has a surface which has been planarized to that of the chuck that carries the wafer under test. The probe card PCB is generally mounted to this planarized surface of the prober. Thus, all such probe card assemblies require well controlled parallelism between the plane of the probe tips (the best-fit plane that minimizes the overall root-mean-square z error between the probe tips and the plane) and the plane of the PCB (the PCB can be thought of as the "reference plane." If the probe tips are co-planar with the PCB, then they are also co-planar with the chuck, and thus with the wafer under test). Such a design will lead to a more uniform contact of the probes to the wafer under test (less of a distance between first touch z distance and last touch z distance). In newer probe cards, the probe tips are referenced to mounting points on the probe card which are typically kinematic mounts of some type (used here to describe a mount that provides accurate and repeatable mechanical docking of the probe card into the test equipment and provides constraint in at least the three degrees of freedom necessary to achieve parallelism to the plane of the wafer chuck). In either embodiment, it is necessary to align the tips of the probe contactors such that they are parallel to a reference plane which is itself parallel to the plane of the wafer chuck.
There are two common ways that a probe contactor substrate may be mounted to the probe card assembly (which includes the PCB, an associated stiffener ring and/or other mechanical elements) in a planar manner: Fixed Probe Card Assemblies (FPCAs) and Adjustable Probe Card Assemblies (APCAs). FPCAs provide for design simplicity (no moving or adjustable parts) and relatively low cost. However, the machining tolerances required for parallelism, particularly in the case of large area probe cards, can be difficult to achieve. Hence, in practice, shims are often used to provide some degree of adjustability during assembly. Shimming, though a practical alternative, is difficult to perform accurately in a manufacturing environment to the tolerances required (on the order of microns).
FPCAs include typical "Buckling Beam" assemblies, such as that shown FIG. 1A and described in U.S. Pat. No. 3,806,801 entitled "Probe Contactor Having Buckling Beam Probes." Buckling Beam assemblies have a vertical buckling beam probe head, a PCB, and an interposer situated between the probe head and the PCB. In this case the interposer comprises an array of solder balls which electrically connect the substrate to the PCB (terminal to terminal) but other examples are well known in the art where the interposer connects the substrate to the PCB by means of spring-pins. In another version of the Buckling Beam probe card, there is no interposer and the buckling beams connect directly to the terminals of the PCB.
In either type of Buckling Beam assembly the probe head is made to be parallel to the PCB surface by first machining the head so that the surfaces are parallel, and second by shimming between the head and the PCB. It is also common practice in the art to mount the probe card and lap the probe tips parallel to the mount, though this technique introduces unwanted damage to the probe tips and is not practical for coated probes (probes with a thin coating of material that is different from the base spring material).
APCAs are well known in the art and range from providing for small groups of adjustable pins to entire probe-bearing substrates panels or assemblies which are adjustable in place relative to the card's reference plane. The unifying characteristic is that a mechanism is provided for moving groups of probes relative to the probe card reference plane while maintaining electrical contact between them. The advantage of adjustability is that parallelism can be readily achieved, even in the field between uses or during use. However adjustability also has a number of significant disadvantages including drift of the adjustment over time and thermal cycling, cost of the relatively complex precision mechanical assemblies required and difficulty of assembly. Furthermore, the adjustment mechanism can take significant space and limit the density of adjacent blocks of probes.
U.S. Pat. No. 5,974,662 entitled "Method of Planarizing Tips of Probe Elements of a Probe Card Assembly," as shown in FIG. 1B, describes such an APCA and discloses a method of making a probe card with an adjustment of the probe tips relative to the probe card assembly's reference plane. The assembly incorporates a space transformer substrate which is mounted to the probe card in such a way that the orientation can be adjusted. A vertical spring interposer is used to electrically interconnect the probe contactor substrate to the PCB and differential screws bearing on the substrate provide the adjustability. This particular design is particularly expensive, difficult to assemble, and complex. In addition, the large number of mechanical components required to achieve adjustability make the design inherently thermally unstable.
In some cases, it is desirable to have multiple "tiles" of probe card substrates (each with a plurality of probes) attached to the PCB. The assembly of probe card substrates of onto larger assemblies may be accomplished in a variety of ways. Most of these assemblies fall into one of two categories: Fixed Assemblies where the substrates are individually fixed to a carrier without further alignment; and Aligned Assemblies where the substrates are mounted to the card on an adjustable leveling mechanism. Fixed assemblies rely on the tolerances of the various elements and the tooling used to set the overall tolerance of contact points on the various substrates relative to one another. For reference, the desired tolerance in all three orthogonal directions is on the order of +/−5 μm, which number is very difficult to achieve through a fixed assembly. U.S. Patent Publication No. 20040163252, assigned to Form Factor International, is an example of a fixed assembly, as shown in FIG. 2A.
Adjustable assemblies typically require some form of macroscopic adjustable mount with a full six degrees of freedom in order to align substrates relative to one another. The trouble with this method is that the mount is relatively large (so that it does not fit in the conventional envelope provided for probe cards) cumbersome, expensive and unstable (i.e. drifts in position as a function of time, particularly when exposed to thermal excursions). U.S. Pat. No. 5,091,694 entitled "Quartz Probe Apparatus," is an example of an adjustable assembly, as shown in FIG. 2B.
Thus, what is needed is an improved probe card assembly and less expensive, yet stable method of planarizing the probe head(s) to the PCB or other reference plane for such a probe card assembly.

Probe card assembly and method of forming same


A thin film magnetic head of the type including an upper magnetic core adjoining a gap layer having a flat front end face along which a magnetic recording medium is linearly slidable has a front end face of the upper magnetic core retreating from the magnetic recording medium at an end remote from the gap layer. The thin film magnetic head thus constructed provides a reproducing output signal which is free from a reverse output and hence has a waveform of an excellent symmetry, and also has a frequency characteristic curve free from fluctuations. In addition, the thin film magnetic head of this invention is able to obviate a magnetic saturation problem associated with the conventional thin film magnetic head, provide a stable output, and perform a reproducing operation efficiently.

1. Field of the Invention:
The present invention relates to a thin film magnetic head for recording and/or reproducing data on a magnetic recording medium such as a magnetic disk.
2. Description of the Prior Art:
A typical example of conventional thin film magnetic heads is shown here in FIGS. 4(a) and 4(b) of the accompanying drawings. The conventional thin film magnetic head includes a magnetic circuit which is composed of a magnetic substrate made from a magnetic material such as an Mn-Zn ferrite, a gap layer 15, a coil 12, an upper magnetic core 13 and a protective film 14 formed on the magnetic substrate 11 in superposed relation in the order named by using a photolithographic processing of insulating films and conductive films formed by sputtering deposition or vacuum evaporation on the magnetic substrate 11. The magnetic substrate 11 constitutes a lower magnetic core relative to the upper magnetic core 13. As best shown in FIG. 5, the front face of the conventional thin film magnetic head which is adapted to face the recording surface of a magnetic recording medium, not shown, is polished or lapped into a flat surface and the upper magnetic core 13 has a thickness 1 at the front end face.
Since the front end face of the upper magnetic core 13 is flat and has a limited extent in the direction of thickness such as indicated by 1 in FIG. 5, the magnetic flux is able to flow from the front end face of the upper magnetic core 13 over the gap layer 15 into the magnetic substrate 11, thereby reproducing an output other than a desired output.
More specifically, the waveform of an isolated pulse which is reproduced by the conventional thin film magnetic head shown in FIGS. 4(a), 4(b) and 5 includes a distortion appearing in the form of a reverse output C, as shown in FIG. 6. The reverse output C is produced due to the front end face of the upper magnetic core 13 which is flat and has the limited thickness 1 shown in FIG. 5. The position at which the reverse output C is produced is determined by the width of the front end face of the upper magnetic core 13. In addition, the conventional thin film magnetic head has a frequency characteristic curve such as indicated by dash lines in FIG. 7. The frequency characteristic curve includes fluctuations D and E which occur at frequency levels determined by the thickness 1 (FIG. 5) of the upper magnetic core 13 (equal to the width of the front end face of the upper magnetic core 13). In order to reduce the negative influence of the fluctuations, the thickness 1 of the upper magnetic core 13 measured at the front end face is made considerably smaller than the overall thickness of the upper magnetic core 13, as shown in FIG. 5. With this construction, the magnetic flux is likely to saturate due to a sudden increase in the magnetic flux density of the upper magnetic core 13 at a position indicated by B in FIG. 5. Further, even though the thickness 1 of the upper magnetic core 13 at its front end face is considerably reduced, the fluctuations of the reproduced output still occur, affecting the magnetic recording/reproducing characteristics of the thin film magnetic head.

Matsushita Electric Industrial Co., Ltd.


A noise-component removing method for removing a noise component from multipoint spectral data that has been generated through measurements performed at measurement points of a sample surface, the method comprising: a PLS analysis step of determining components of the multipoint spectral data for each measurement point in a descending order of eigenvalues of the components by subjecting the multipoint spectral data to multivariate analysis based on the partial least squares regression using a value obtained by quantifying characteristic information about a characteristic of each measurement point, other than spectral information of the measurement point and using the spectral information as an independent variable in the partial least squares regression; and a spectrum reconstruction step of reconstructing the multipoint spectral data for each measurement point to eliminate a component having an eigenvalue lower than a predetermined value, from the components determined in the PLS analysis step.

Multipoint spectral data, such as mapping data or temporal change data obtained through sample-surface analysis, is subjected to processing to remove noise components therein.
Smoothing is one known technique to reduce the noise bandwidth of multipoint spectral data. After smoothing, however, the multipoint spectral data will have lower peaks in the spectra or will have wavenumber shifts occurring in the spectra.
Principal component analysis (PCA) is another known technique to remove noise from multipoint spectral data. With a conventional noise-component removing method based on PCA, multipoint spectral data that has been generated through measurements performed at multiple measurement points of a sample surface is separated into a plurality of principle components by PCA, and is then reconstructed to eliminate low-order components from the separated components. As a result, noise components are removed from the multipoint spectral data.
Such a noise-component removing method based on PCA has conventionally been applied, for example, to accumulated data (refer, for example, to Unexamined Japanese Patent Application Publication No. 2000-74826). The conventional noise-component removing method described in Unexamined Japanese Patent Application Publication No. 2000-74826 has also been applied to data corresponding to an area.
However, the inventors of the present invention have found that the noise-component removing method based on PCA may fail to reconstruct a spectrum that differs in shape from a large number of other multipoint spectra, or more specifically, may fail to reconstruct, for example, a spectrum representing a different substance contained at only one point in mapping data.
There have been no appropriate techniques to prevent low-order spectra (signal components) of multipoint spectral data from being lost during reconstruction of the multipoint spectral data, although conventional countermeasures to such signal loss have possibilities for improvement.


The present invention is to provide a waterproof connector having an adjusted spacing between terminals or electrical wires for achieving an effective waterproof. The electrical wires received in a terminal receiving portion of an outer housing are guided to a wire seal fit portion, while the electrical wires are pressed with wire holders (displacement limit portions). The electrical wires are then passed through a holder (spacing adjusting portion), a seal member, and another holder (lead-out portion) of a wire seal in the wire seal fit portion. The wire seal is fitted into the wire seal fit portion for achieving waterproof of the waterproof connector. The electrical wires guided out of the lead-out portion have an equal spacing therebetween by expansion of the spacings between the electrical wires or displacements thereof. The equal spacing ensures insertion of the seal member and provides the effective waterproof.

1. Field of the Invention
The present invention relates to a waterproof connector including a terminal receiving portion, which receives a terminal connected with an electrical wire to connect an electronic circuitry, and a wire seal fit portion, which waterproofs the electrical wire guided out of the terminal receiving portion.
2. Description of Related Art
JP2000-208200, A discloses a conventional waterproof connector including a terminal receiving portion and a waterproof portion to prevent water from entering the terminal receiving portion.
FIG. 6 illustrates a configuration of the conventional waterproof connector of JP2000-208200,A. In the waterproof connector 1, a female terminal 104 having a box shaped electrical contact portion 105 is received in a terminal receiving chamber 103 of a housing 102. A mat seal 106 having a plurality of through holes 107 is attached to a rear end of the terminal receiving chamber 103 for sealing an electrical wire. The mat seal 106 is interposed between the housing 102 and a mat seal cover 113 so as to hold the mat seal 106 at the rear end of the terminal receiving chamber 103.
In the conventional waterproof connector, when a spacing or distance between the female terminals 104 becomes smaller than a prescribed value, the spacing between the electrical wires guided out of the female terminals 104 also becomes small. It becomes difficult to put the mat seal 106 between the electrical wires for waterproofing the connector, resulting to a reduction of sealability.
It is necessary to provide a seal member, such as the mat seal, with a thickness and spacing between the terminals and between the electrical wires to effectively waterproof the electrical wires guided out of the terminal. The electrical wires are straight led out of the terminals and the spacing therebetween depends on the spacing between the terminals. The spacing of the terminals has a limit for reduction. The spacings between the terminals and between the electrical wires have an irregular size, wide or narrow portion, so that the uniform and effective waterproofing is difficult. It is desired that the waterproof connector has a small size and is adapted to a variety of the terminals to be received.


An integrated processor is provided with a memory control unit having refresh queue logic for refreshing dynamic random access memory (DRAM) banks during idle memory cycles. The refresh queue logic includes a queue counter and allows the refresh requests to be given a lower priority than other memory transactions until the required refresh rate is in danger of being violated. At this lower priority the refresh requests are honored and retired from a refresh queue only in the absence of other memory transactions. In the event that the refresh queue becomes full, top priority is given to the execution of a refresh request. In this case, a refresh request is honored and retired from the queue immediately after the conclusion of the current memory transaction. This queuing mechanism allows the refresh requests to be buffered until idle memory cycles are available or until absolutely necessary to prevent the violation of refresh timing constraints.

FIELD OF THE INVENTION
The present invention relates generally to the operation of system memory in a personal computer (PC) system. More particularly, this invention relates to a memory controller unit for controlling the refreshing of dynamic random access memory (DRAM) chips, which comprise the system memory. Still more particularly, the present invention relates to a DRAM refresh logic which enhances system performance by performing refresh cycles primarily when the memory bus is idle.
FIG. 1 is a block diagram of a prior art computer system 10 that comprises a microprocessor or central processing unit ("CPU") 12, a CPU local bus 14 coupled to the CPU 12 and to a memory controller unit (MCU) 16, and a local bus peripheral device 18 also coupled to the CPU local bus 14. A system memory 17 is shown coupled to the memory controller 16 through a memory bus 15. In addition, a PCI (peripheral component interconnect) standard bus 20 is coupled to the CPU local bus 14 through a PCI bus bridge 22. A PCI peripheral device 28 is shown coupled to the PCI bus 20. The PCI peripheral device 28 may comprise a PCI Master controller that is capable of asserting ownership of the PCI bus during PCI Master cycles.
The microprocessor 12 shown in FIG. 1 may comprise a model 80486 microprocessor, and the CPU local bus 14 could comprise an 80486-style local bus. Alternatively, the processor 12 may comprise a Pentium-compatible processor, or some other processor design. The CPU local bus 14 includes a set of data lines D31:0!, a set of address lines A31:0!, and a set of control lines (not specifically shown). While the data and address lines are shown as 32-bit busses, one skilled in the art will understand that other bus widths could be used. Details regarding the various bus cycles and protocols of the 80486 CPU local bus 14 are not discussed in detail herein, as they are well known by those in the art, and are available in numerous publications. CPU 12, memory controller 16 and PCI bus bridge 22 have traditionally been fabricated on separate integrated circuit chips. A recent trend in computer systems has developed, however, in which the CPU core is combined with a variety of peripheral devices on a single integrated processor chip. An exemplary integrated processor chip includes a bus bridge that provides a high performance interface between an internal CPU local bus and an external PCI bus. By providing a high performance interface to an external PCI bus, relatively high performance characteristics can be achieved with respect to external data transfers.
The PCI bus bridge 22 provides a standard interface between the CPU local bus 14 and the PCI bus 20. As such, the PCI bus bridge 22 orchestrates the transfer of data, address, and control signals between the two buses. PCI bus 20 typically comprises a high performance peripheral bus that includes multiplexed data/address lines, and which supports burst-mode data transfers.
As noted, the PCI peripheral device 28 may comprise a PCI Master controller. In accordance with conventional techniques, the PCI Master may request "ownership" of the PCI bus, so that it can control transactions on the PCI bus 20. As one skilled in the art will understand, a plurality of PCI Masters may be included in the computer system, any of which may request ownership of the PCI bus 20. The PCI Master submits its request for ownership of the PCI bus 20 to the PCI bridge 22 on a control line in the PCI bus 20. The PCI bus bridge 22 typically arbitrates ownership requests among the various PCI Masters, and among the internal masters such as the CPU 12, and other internal masters. A priority ranking may be assigned to each of the various Masters to assist the bus bridge 22 in its priority determination.
The system memory typically includes banks of dynamic random access memory (DRAM) circuits. The DRAM connects to the MCU 16 via a memory bus 15, comprised of memory address lines, memory data lines, and various control lines. The DRAM banks, according to normal convention, comprises the working memory of the integrated processor. Data generally is transferred between DRAM 17 and other components in a computer system in two steps.
First, the accessing component generates signals on the address bus representing the row address of the desired memory location, which are latched into the DRAM when the row address strobe (RAS) signal is asserted low. At the next, or at subsequent, clock cycles, the memory device latches in the column address signal when the column address strobe (CAS) is asserted low. During an early write transaction, data is written into memory on the falling edge of the CAS signal while WE is active. In a read cycle, data from the selected memory cell is driven onto the data output line shortly after the assertion of the CAS signal while WE is inactive.
The speed of memory circuits is based upon two timing parameters. The first parameter is memory access time, which is the minimum time required by the memory circuit to set up a memory address and produce or capture data on or from the data bus. The second parameter is the memory cycle time, which is the minimum time required between two consecutive accesses to the memory circuit. For DRAM circuits, the cycle time typically is approximately twice the access time. DRAM circuits general have an access time in the approximate range of 60-100 nanoseconds, with cycle times of 120-200 nanoseconds. The extra time required for consecutive memory accesses in a DRAM circuit is necessary because the internal memory circuits require additional time to recharge (or "precharge") to accurately produce data signals. Thus, a microprocessor running at 10 MHz cannot execute two memory accesses, in immediate succession (or in adjacent clock pulses), to the same 100 nanosecond DRAM chip, despite the fact that a clock pulse in such a microprocessor is generated every 100 nanoseconds. Typically, the memory controller unit ("MCU") functions to regulate accesses to the DRAM main memory.
Because of these limitations, memory constructed with DRAM circuits is not always capable of responding to memory accesses within the time interval allotted by the central processing unit ("CPU"). In this event, external circuitry must signal to the CPU that supplementary processor cycles, or wait states, are necessary before the data is ready on the data bus, or before data from the data bus has been stored by the memory circuits. In addition to slowing the processing of the CPU, wait states generally require use of the CPU local bus, thereby limiting access to the bus by other system circuitry.
In addition to the delays caused by access and cycle times, DRAM devices are inherently dynamic devices which require periodic refresh cycles to protect the integrity of the stored data. These cycles consume a significant portion of the time available for memory accesses, and typically are required approximately every 4 milliseconds. If the DRAM circuit is not refreshed periodically, the data stored in the DRAM circuit will be lost.
Most industry standard DRAM devices have 256 rows. All of these rows must be refreshed once every 4 milliseconds, requiring refresh cycles to be run every 16 microseconds to complete the 256 refresh cycles in 4 milliseconds. In addition, system memory typically includes a plurality of DRAM banks. It has become increasing common to have the memory sub-system in a personal computer system support four or more banks of DRAM devices. While some computer systems have attempted to refresh all of the available DRAM banks at one time, the power consumed in such a DRAM refresh may be excessive, especially in portable systems that are battery operated.
As a result, most computer systems stagger the refresh cycles for each DRAM bank due to power considerations. Thus, refresh cycles are run sequentially to each of the DRAM banks provided in the system memory, consuming even more of the available memory access time. As an example, for a 4 bank DRAM memory sub-system with 256 rows, a refresh cycle may be required every 4 microseconds to meet the 4 millisecond refresh rate for each line in each bank of DRAM. This brings the refresh overhead to approximately 5% of the available memory bandwidth. A system with more than 4 banks of DRAM has an even higher refresh overhead, leaving less of a bandwidth available for the processor to access system memory, and thus increasing the frequency of wait states for the processor.
As the operating speed of processors increases and as new generations of processors evolve, it is advantageous to minimize wait states to fully exploit the capabilities of these new processors obtaining the maximum benefit of these new generations of high speed processors in personal computers, however, is especially difficult, because of size and power limitations of other components in the system, such as the DRAM system memory. With memory intensive applications, such as those involving technical or scientific calculations or computer aided design programs, the memory access time can greatly reduce the system performance.

Integrated processor and memory control unit including refresh queue logic for refreshing DRAM during idle cycles