A method of control to synchronize the arrival of images and copy sheets at a transfer station by sensing delay of a copy sheet arrival at the transfer station. There is then a determination that the delay of arrival is incapable of being corrected to synchronize with a given image. In response, the control decides to rewrite the given image on the receiving medium or further delay the arrival of the copy sheet, or a combination of rewrite and delay, in order that the arrival of a given image and copy sheet is synchronized.

The invention relates to image transfer, and more particularly, to the synchronization of transfers of images to copy sheets to reduce shutdowns.
For reliable and rapid movement of copy sheets through a reproduction machine, it is important to synchronize various drives and transports. This is important, in particular, in multi-drive machines such as in color machines wherein efficient registration and movement of sheets is essential to quality output. In addition, in an age demanding a variety of machine features and various machines to provide the features, the use of too many custom designed controls or other drives to provide the features creates an additional obstacle to consistent and reliable performance. For example, in a printing or reproduction machine, there are a variety of control profiles required for various applications such as driving the photoreceptor, driving a recirculating document handler or automatic document feeder, or driving copy sheets at various stages such as from the copy sheet source, to a registration gate, during a transfer operation, entering and exiting a fusing stations, and delivering copy sheets to many finishing stages such as to output trays, sorters, stackers, compilers, and staplers.
It is a generally known technique to provide controlled movement within positioning systems, in particular moving and registering paper within a xerographic reproduction or printing system. For example, U.S. Pat. No. 5,502,544, assigned to the same assignee as the present invention, discloses an imaging machine having a control and movable components including a photosensitive member and copy sheet transports. The control includes a servo system connected to given movable components and provided with control profiles for directing the movement of the component, including acceleration, deceleration, and constant velocity portions. A main controller monitors the operation and predetermined conditions and automatically changes selected portions of the control profile in response to predetermined conditions. In addition, U.S. Pat. No. 5,543,894, also assigned to the same assignee as the present invention, discloses a system for monitoring discrete drives at the time of transitions from one transport to another transport to detect mismatch and surface velocity. Upon detection of mismatch of velocity, a given controller is adjusted through a command bus to correct for the mismatch.
In the prior art, images from an image source are put into a marking subsystem at a constant speed. The paper handling subsystem delivers paper to the marking subsystem at a precisely specified time window in order to receive the image. The precise time of arrival is necessary because the arrival time determines the position that the image ends up on the paper. If the paper is delayed, the machine may be shut down because the image position would be outside the required position specifications. Further, as shown in U.S. Pat. No. 5,086,319 also assigned to the same assignee of the present invention, there is shown a system for automatically adjusting the velocity of a copy sheet to correct for previously determined misregistration of a document at an exposure station.
It would be desirable, however, if the paper handling system experienced a delay in transferring the paper to the marking subsystem, that the machine would be able to alter the marking system in order to match the time delay of the paper path. It would be desirable, therefore, to provide a control that uses bidirectional information feedback between marking and paper subsystems to accommodate paper path problems and registration problems. It is also desirable to provide a control wherein either the copy sheet can be selectively delayed or the marking system selectively rewrite an image, or both for suitable sheet registration.
It is an object, therefore, of the present invention to provide a new and improved control system wherein the marking system can be automatically altered. Another object of the present invention is to be able to change the control wherein either the copy sheet can be selectively delayed or the marking system selectively rewrite an image, or both for suitable sheet registration.
Other advantages of the present invention will become apparent as the following description proceeds, and the features characterizing the invention will be pointed out with particularity in the claims annexed to and forming a part of this specification.

Feedback between marking and paper path subsystems to reduce shutdowns


A vector for eliciting an immune response to a host comprising a gene encoding the gp140 protein of the primary isolate of HIV-1, BX08, under the control of a promotor for expression of the protein in the host, specifically plasmids pCMV.gp140.BX08, pMP83, pMP84 and pMP88. Murine and human MHC class 1-restricted binding motifs contained in BX08 are identified.

Acquired immunodeficiency syndrome (AIDS) is a disease which is the ultimate result of infection with human immunodeficiency virus (HIV). Currently, there is no effective vaccine which can protect the human population from HIV infection and hence the development of an efficacious HIV-vaccine and protocol for administering the same is urgently required. Previously, HIV-1 particles exhaustively inactivated by chemical treatments, a vaccinia vector encoding the whole envelope gene (gp140) of HIV-1, and purified recombinant gp120 have been evaluated as candidate HIV vaccines. Although inactivated HIV-1 virus preparations elicited a T-cell-mediated Delayed-Type Hypersensitivity (DTH) reaction in humans, and vaccinia/gp160 and gp120 recombinant vaccine candidates induced virus neutralizing antibodies, none of these immunogens have been shown to be efficacious human HIV vaccines (ref. 1, throughout this specification, various references are referred to in parenthesis to more fully describe the state of the art to which this invention pertains. Full bibliographic information for each citation is found at the end of the specification, immediately following the claims. The disclosures of these references are hereby incorporated by reference into the present disclosure). The inventors' interest in HIV vaccinology is to develop immunogenic and cost-effective HIV-1 DNA vaccines and consider that their use alone or in conjunction with other forms of HIV-1 vaccine candidates will lead to the elicitation of more effective immune responses against HIV-1.
There has previously been described in granted European Patent No. 470,980 and U.S. Pat. No. 5,639,854, assigned to the assignee hereof, the disclosures of which are incorporated herein by reference, inter alia, the identification and characterization of a T-cell epitope of the core protein, p24E, of HIV-1. There has further been described in granted U.S. Pat. Nos. 5,759,769 and 5,795,955, assigned to the assignee hereof, and disclosures of which are incorporated by reference, the use of the T-cell epitope in the construction of immunogenic synthetic HIV-1 chimeric peptides comprising p24E linked to amino acid sequences of different B-cell epitopes of an envelope or core protein of HIV-1.

Expressing gp140 fragment of primary HIV-1 isolate


Methods and systems enable devices to discover each other when the devices are in a common location. Unique identifiers (UIDs) are associated with one or more location and each UID uniquely identifies a location. Devices that are located in a particular location that has a UID can register to create an association between the device and the UID. In turn, this creates an association between the device and a location. Subsequently, when another device (e.g. a laptop computer or PDA) enters the location, the device can discover the UID of the location and then ascertain which other devices are associated with that location.

As computing environments become more and more mobile, the need to be able to locate devices and services becomes more important. For example, consider an individual with a laptop computer whose job requires them to travel to various geographically-separated company locations. Perhaps in the morning they attend a meeting in Boise, Id., and, in the afternoon have another meeting scheduled in Vancouver, Wash. Assume now that at each of the meeting locations, there are various computing devices or peripherals that would be convenient for the user to use and access using their laptop computer. For example, there may be printers, plotters, facsimile machines (electronic fax machines or services) and the like that are location specific and convenient for the user to use. There may also be electronic equipment in the meeting rooms that would be convenient to use.
While there may be a number of devices that are available for use in each of the locations, the user will be unable to use them if they cannot discover the devices. Accordingly, this invention arose out of concerns associated with providing methods and systems that facilitate local device discovery.

Methods and systems for determining local device proximity

Hewlett-Packard Development Company, L.P.


A nonvolatile memory includes a first block and a second block. The first block comprises a first memory cell and a first source line coupled to a source of the first memory cell. The second block comprises a second memory cell and a second source line coupled to a source of the second memory cell. A first source switch is coupled to the first source line for selectively coupling a first potential, a second potential, and a third potential to the first source line. The second potential has a voltage intermediate between the first potential and the third potential. A second source switch is coupled to the second source line for selectively coupling one of the first, second, and third potentials to the second source line. A block select circuit receives a block address for selecting one of the first and second source switches to couple one of the first, second, and third potentials to its respective one of the first and second source lines. A configuration cell is coupled to the block select circuit for configuring block operations of the first and second blocks. When the configuration cell is in a first voltage state, the configuration cell causes the block select circuit to separately select one of the first and second source switches depending upon the address received. When the configuration cell is in a second voltage state, the configuration cell causes the block select circuit to collectively select the first and second source switches.

One type of prior nonvolatile memory is the flash erasable and electrically programmable read-only memory ("flash EPROM"). A typical flash EPROM is organized into rows and columns. Memory cells are placed at intersections of word lines and bit lines. Each word line is connected to the gates of a plurality of memory cells in one row. Each bit line is connected to the drains of a plurality of memory cells in one column. The sources of all the memory cells are connected to a common source line. The flash EPROM can be programmed, and once programmed, the entire contents of the flash EPROM can be erased by electrical erasure. A high erasing voltage V.sub.PP is made available to the source of all the cells simultaneously. This results in a full array erasure. The flash EPROM may then be reprogrammed with new data.
One disadvantage of this prior flash EPROM structure is the characteristics of array erasure. When changes are sought to be made to a program stored in the array, the entire array must be erased and the entire program be rewritten into the array, even when the changes are minor.
One prior approach to solving this problem is to reorganize the array into blocks so that the high erasing voltage is made available only to the source of every cell within one block to be erased. In this arrangement, each block can be individually addressed for read, programming, and erasure operations. By this arrangement, only a block of memory array is erased, rather than having the entire memory array erased.
FIG. 1 illustrates such a typical prior arrangement. In FIG. 1, memory cells of prior flash EPROM 10 are organized into a plurality of bit line blocks BLOCK0 through BLOCKn. Each block can be individually addressed for read, programming, and erasure operations. Each block includes a plurality of bit lines that are connected to sense amplifiers 34 via a respective one of Y gating circuits 30a through 30n. Each of Y gating circuits 30a-30n includes a plurality of column select transistors for selectively connecting eight bit lines (i.e., one byte) at a time from the respective block to sense amplifiers 34. Therefore, each of Y gating circuits 30a-30n includes eight connection lines connected to sense amplifiers 34, respectively. The outputs of sense amplifiers 34 are coupled to data pins of the prior flash EPROM via data lines 35 and via output buffers in logic circuitry 20. Prior flash EPROM 10 also includes a plurality source switches 32a through 32n, each associated with one of blocks BLOCK0 through BLOCKn.
During the read operation, a Y and block decoder 17 selects one byte of bit lines of a selected block for any given address applied. The selected bit lines of the selected block are then connected to sense amplifiers 34 via the associative Y gating circuit. One of X decoders 13 and 14 selects a word line. Sense amplifiers 34 then sense the voltage levels on the selected bit lines to obtain data from the selected memory cells at intersections of the selected bit lines and the selected word line. Sense amplifiers 34 then apply the sensed data to the data pins of prior flash EPROM 10 via data lines 35 and logic circuitry 20.
During the programming operation, decoder 17 selects one byte of bit lines in a selected block for each address applied. One of X decoders 13-14 selects a word line. Programming potentials are applied to the selected bit lines and the selected word line. Decoder 17 selects the source switch associated with the selected block to couple a ground potential V.sub.SS to the sources of the memory cells of the selected block and to couple a disturb inhibit potential V.sub.DI to the sources of the memory cells of unselected blocks. This is done to help prevent the programming of the selected cells in the selected block from disturbing the memory cells in unselected blocks. During the erasure operation, decoder 17 selects one block by selecting its associative source switch for each address applied. The selected source switch applies the high erasure voltage V.sub.PP to the sources of the memory cells of the selected block, thus allowing block erasure of the selected block.
Disadvantages are, however, associated with this prior blocked flash EPROM structure. One disadvantage is that during erasing of a block, some of the memory cells of the block tend to absorb more erasure current than others. This is typically referred to as current "hogging". Current hogging typically arises when, during erasing, some memory cells enter the "Zener breakdown" state while others do not. When a cell is in the Zener breakdown state, a slight voltage increase on the source may lead to a significant increase in current flow through the cell, and vice versa. When the erasing voltage along the common source line of a block varies from point to point, the voltage variations may cause the cells coupled at one point of the source line that are in the Zener breakdown state to sink most of the erasure current. The voltage variations along a source line are typically relatively significant when the memory blocks are relatively large and contain a relatively large number of memory cells. This typically requires the source line of a block to be long in order to connect to the sources of all memory cells in that block. The relatively long source line typically increases the line impedance, which in turn results in voltage variations along the source line being relatively significant.
Another disadvantage of the above-described prior flash EPROM is that the number of the blocks and the size of each of the blocks are both fixed and cannot be altered. Thus, the user of that prior flash EPROM cannot later change the size and the number of the blocks.

Floating gate nonvolatile memory with configurable erasure blocks


A field emission display (FED) and a manufacturing method thereof are provided. The FED includes a getter portion isolated outwardly from an active display region. This getter portion includes a non-evaporable getter layer for absorbing gas and an electron emission source for activating the getter layer. Accordingly, by activating the non-evaporable getter, the gas generated in the display is easily absorbed, and the FED is maintained in a high vacuum state.

1. Field of the Invention
The present invention relates to a field emission display (FED) and a manufacturing method thereof, and more particularly, to a field emission display (FED), which is maintained in a high vacuum state by absorbing gases in a display panel through the activation of a non-evaporable getter (NEG) layer that is formed on the front plate of the FED, and a manufacturing method thereof.
2. Description of the Related Art
In a field emission display (FED), several hundreds to thousands of micro tips or carbon nanotubes (CNTs) per pixel are provided as an electron emission source on a back plate of FED, and a phosphor layer emitting a light by an electron from the electron emission source is formed on a front plate of FED. A gap between the front plate and the back plate of FED is usually about 200 μm to several mms and the display must be maintained in a high vacuum state so that electrons are moved without energy loss.
A conventional display using electron emission includes a cathode ray tube (CRT) in a TV set. Since the internal volume of the CRT is very large, it is comparatively easy that the CRT is maintained in a vacuum state. However, in the case of the FED, the internal volume of the display is very small, and thus, it is very difficult that the FED is maintained in a vacuum state. This is the reason materials generating gases are relatively widely distributed in the small internal volume of the FED, and thus, vacuum state of FED may be rapidly deteriorated by the gases that is generated from the materials. Thus, the FED must be manufactured in a high vacuum state, and this vacuum state has a great effect on the quality and lifetime of the FED.
FIG. 1 is a schematic cross-sectional view of a conventional FED, and FIG. 2 is a schematic projected top view of the conventional FED.
The conventional FED includes a front plate 10 and a back plate 20 that are spaced from one another by a gap. An anode 12 and a cathode 22 having a striped form are formed on the opposite inner surfaces of the front plate 10 and the back plate 20, respectively. A gate insulating layer 24 in which holes 24a are formed, is disposed on the cathode 22. A gate electrode 26 in which gates 26a corresponding to the holes 24a are formed, is formed on the gate insulating layer 24. An electron emission source 28 such as micro tip and carbon nanotube (CNT), is formed on the surface of the cathode 22 that is exposed at the bottom of the holes 24a.
A phosphor layer 14 having colors corresponding to pixels are coated on the anode 12, and a black matrix 16 for improving contrast and color purity is formed among the phosphor layer 14. A plurality of spacers 18 for maintaining the gap between the front plate 10 and the back plate 20 are positioned between the front plate 10 and the back plate 20, and a sidewall frame 30 for sealing a display panel is positioned at edges between the front plate 10 and the back plate 20.
An exhausting path 40 for exhausting an internal gas is formed at one side of the back plate 20, and a sealing cap 40a for sealing the outlet of the exhausting path 40 is formed at the outlet of the exhausting path 40. A gas path 42 through which the internal gas is flowed into is positioned at another side of the back plate 20, and a getter container 46 including a getter 44 for absorbing gases is connected to the end of the gas path 42.
In the FED having the above structure, the getter container 46 is protruded outwardly from the back plate 20, resulting in an increase in the total thickness of the panel including the getter container 46. Since the absorption of gas is made through the gas path 42 having a narrow section area with very large gas flow resistance, the effective absorption of the gas is difficult. The large gas flow resistance is caused from the narrow gap between the front plate 10 and the back plate 20 that are maintained at a 200 μm to several mms of interval as well as from the gas path 42. Due to the increase in gas flow resistance between the front plate 10 and the back plate 20, it is very difficult that an internal gas, in particular, a gas far from the gas path 42, is passed through the gap between the front plate 10 and the back plate 20 and the gas path 42. Accordingly, the internal gas cannot be effectively removed, and thereby there is a limitation in increasing internal vacuum level.

Field emission display manufacturing method having integrated getter arrangement


A brake pressure control device that prevents the accumulation of contaminants, thereby ensuring that the pressure can rise again during an antilock control operation or provide sufficient pressure during sudden braking, thereby ensuring a high degree of safety. A piston (16), housing a valve plug (24), is mounted inside a cavity (12), wherein a primary variable restrictor (32), formed between the cavity and the piston, and a secondary variable restrictor (33) and a third variable restrictor (34), both formed between the piston and the valve plug, are arranged sequentially. A fluid path with passage to the main brake line on the wheel cylinder side is connected between the secondary variable restrictor and third variable restrictor.

Generally, brake pressure control devices are equipped with a large number of electromagnetically-actuated valves used as inlet valves and exhaust valves. However, in order to reduce the number of these solenoid valves, a variety of brake pressure control devices have been disclosed in which the inlet valves are hydraulically actuated instead of electromagnetically actuated.
For example, in the device disclosed in Publication of Unexamined Japanese Patent Application Heisei 1(1989)-306357, as shown in FIG. 14, a main brake line 62 connects the master cylinder 60 to a wheel cylinder 61, an exhaust line 63 branches from the main brake line 62 with a hydraulically actuated flow control valve 64 provided at the point of the branching, and a conventional electromagnetically-actuated exhaust valve 65 is provided in the exhaust line 63.
The flow control valve 64 includes an inner cylinder 67 housed inside a cavity 66, a spool 69 housed to slide inside the inner cylinder 67 and forming a fixed-diameter orifice 68 therein, and return springs 70 which energize the spool 69 towards the closed end of the cavity 66. A plural number of fluid ducts are bored through the inner cylinder 67 and spool 69 in the radial direction.
The brake pressure control device of a type as described is subject to certain potential problems.
The flow control valve has a large brake fluid path formed from an inlet port 71, fluid ducts 72-76, and a primary outlet port 77.
In order to rise the pressure again during an antilock braking (ABS), the spool 69 drops thereby blocking the large fluid path, wherein the brake fluid is bypassed through the fixed-diameter orifice 68 of small cross section and supplied to the wheel cylinder 61. The cross section diameter of the fixed-diameter orifice 68 is extremely small, of the order between 0.2 mm-0.3 mm, in which case contaminants can readily accumulate and are removable only by physically dismantling and cleaning the device. A buildup of contaminants will block the fluid flow necessary for the brake pressure to rise, and braking force will be inadequate.
During sudden braking when the spool 69 moves towards the return spring chamber 80, the large fluid path becomes constricted or blocked, creating the danger of insufficient braking force. That is, during sudden braking when a strong fluid force acts on the spool 69, it is pushed towards the return spring chamber 80. The brake fluid inside the return spring chamber 80 is thereby compressed and forced around the exterior of the spool 69 and out through the fluid duct 78 which has passage to the wheel cylinder 61. This allows the spool 69 to drop (that is, move farther towards the return spring chamber 80), constricting or blocking the fluid path between the two fluid ducts 75 and 76, resulting in an insufficient braking force.
In the brake pressure control device as described, a plural number of fluid ducts 72, 73, 75, 76, 78, 79 must be bored in the radial direction through the inner cylinder 67 and spool 69. The fabrication of these ducts increases the cost of the device.


A disc apparatus including: a disc tray on which a disc is mounted; an optical pickup unit which irradiates a light beam on the disc; a traverse assembly unit on which the optical pickup unit is mounted; a driving motor which is a power source for operating the disc tray, the optical pickup unit, and the traverse assembly unit; an inner circumference arrival sensor which detects whether the optical pickup unit arrives at the inner circumference of the disc; and an encoder sensor which detects the number of rotations of the driving motor when the driving motor rotates clockwise or counterclockwise, wherein based on the number of rotations of the driving motor in the clockwise direction, the optical pickup unit is moved to the inner circumference of the disc, and then the traverse assembly unit descends, so that the disc tray is opened.

1. Field of the Invention
The present invention relates to a disc apparatus for, for example, a CD and a DVD.
2. Description of the Related Art
In a commonly used disc apparatus (for example, see JP-A-2002-100099, JP-A-6-119698, JP-A-6-338119 and JP-A-2001-216702), a disc tray (tray) is opened or closed (unloading/loading) at a slit-shaped entrance which is provided in a front panel of an exterior housing by driving force of a driving motor.
Generally, the disc apparatus includes a switch (tray open switch) for detecting whether the tray is opened completely, in order to stop the operation of the driving motor for driving the disc tray, when the disc tray is opened (when the opening of the tray is completed).
In addition, there can be different types of disc apparatuses, such as a disc apparatus in which a stopper or the like is provided in the vicinity of a slit-shaped entrance and in which the operation of the driving motor is stopped when the tray comes into contact with the stopper, as disclosed in JP-A-6-338119, and a disc apparatus in which the operation of the driving motor of the disc tray is stopped after a predetermined time elapsed, as disclosed in JP-A-2001-216702.
However, in the case in which the tray open switch is provided in the disc apparatus, the tray open switch must be provided at a position where the tray open switch does not obstruct the operation of an OPU (optical pickup unit) and the driving motor. That is, since the tray open switch is provided in a limited space inside the disc apparatus, which causes the flexibility of the design to be lowered. Further, it is required to provide, for example, a dedicated printed circuit board for controlling the tray open switch, which causes the flexibility of the design to be further lowered.
In addition, the provision of the tray open switch increases the number of components which constitute the disc apparatus, resulting in an increase in the manufacturing costs of the disc apparatus.
Also, in the movement control of the disk tray by time control, it is common to set the time longer than the required time in order to prevent the disc tray from stopping in the middle of an opening operation. In addition, many disc apparatuses include a stopper which is provided in the vicinity of the slit-shaped entrance to stop the disc tray when the disc tray comes into contact with the stopper. Therefore, the disc tray does not stop smoothly, and thus a high-quality operation cannot be performed.


The invention relates to an apparatus and for facilitating the reauthentication of a user using a client computer to a server computer. In one embodiment, the method includes the steps of receiving, by the server, confidential information during a first communication session between the server and a client, encrypting the confidential information with a key to create encrypted confidential information, and storing the encrypted confidential information in the server's memory. The method also includes the steps of transmitting, by the server, the key to the client and deleting, by the server, the key from the server's memory. When the server receives the key from the client during a second communication session, the server uses the key to decrypt the encrypted confidential information.

A user typically provides authentication credentials, such as a login password, to a server computer at the start of or during a communication session. The server computer typically maintains a centralized storage area in the memory of the server computer for the storage of the authentication credentials, which are typically encrypted in some manner. The server computer can then check the authentication credentials received from the user against the encrypted authentication credentials stored in the server's computer's memory to authorize the user's access to the server.
If an established communication session between the user and the server computer abnormally terminates, the user generally has to reestablish the connection by starting a new communication session. To begin the new communication session, the user typically has to retransmit the authentication credentials (e.g., login password) to the server computer so that the server computer can authorize the user for the new communication session. This retransmission of the authentication credentials of a user across multiple communication sessions repeatedly exposes the authentication credentials of that user to potential attackers, thereby decreasing the level of security of the authentication credentials. Thus, it is desirable to provide a technique for reestablishing a communication session between a client computer and a server computer without repeatedly transmitting the authentication credentials.

Method and apparatus for transmitting authentication credentials of a user across communication sessions


A sampling capacitor interface circuit for storing charge on a sampling capacitor related to a sample of an input signal voltage during a charging phase and to transfer the stored charge to an output during a charge transfer phase, such input signal having bipolar voltages within a range above and below an input signal common mode voltage. The interface circuit includes a transistor having: an input electrode fed by the input signal; an output electrode coupled to the sampling capacitor; and, a control electrode. A controller is provided for producing a control signal having a first voltage during the charging phase and a second voltage during the charge transfer phase, such voltages being a unipolar voltage referenced to the input signal common mode voltage. A bias circuit is coupled to the input signal and has a level shifting capacitor coupled between the controller and the control electrode for storing a voltage during the charge transfer phase and for shifting the first voltage by the stored voltage during the charging phase to provide a voltage at the control electrode with a level sufficiently below the input signal common mode voltage to bias the transistor to a conducting condition during the charging phase over the range of input signal voltages.

This invention relates generally to switched capacitor circuits and more particularly to circuits adapted to store charge on a sampling capacitor related to a sample of an analog signal voltage during a charging, or sampling phase and to transfer the stored charge to an output during a charge transfer phase.
As is known in the art, switched capacitor circuits have a variety of applications. For example, in analog to digital converters (ADCs) which are based on either capacitor digital to analog converters (DACs) or oversampling schemes, such as sigma-delta converters, an interface is typically required between the analog input signal voltage being converted into corresponding digital samples and the conversion architecture. The interface typically samples the analog signal voltage and stores such sampled voltage as a corresponding, proportional charge on a sampling capacitor. More particularly, the interface is provided between the analog voltage signal and the sampling capacitor. After storage, the stored charge is converted into a corresponding digital signal representative of the sampled analog input signal voltage by the conversion architecture. In a sigma-delta ADC architecture, the charge is stored on the sampling capacitor during a charging phase and is transferred to an output during a charge transfer phase for conversion. This charging/charge transfer phasing is provided by a switched capacitor circuit.
More particularly, as shown in FIG. 1 and as described in U.S. Pat. No. 5,134,401 issued Jul. 28, 1992 entitled "Delta Sigma Modulator Having Programmable Gain/Attenuation", inventors McCartney et al., assigned to the same assignee as the present invention, the subject matter thereof being incorporated by reference, the switched capacitor circuit 10 includes a sampling capacitor Cs and four transistors m1, m2, m3 and m4. The output of the switched capacitor circuit 10 is coupled to a summing node n3. During the charging phase, control signal Ph2 (FIG. 2B) at the gate electrodes of transistors m1, m2 places transistors m1and m3 in a conducting condition and control signal Ph1 (FIG. 2A) at the gate electrodes of transistors m2, m3 places transistors m2 and m3 in a non-conducting condition. Thus, a charge packet, Cs*Vin is stored on sampling capacitor Cs at the end of the charging phase, where Vin is the analog input signal voltage. During the charge transfer phase, control signal Ph1 switches transistors m1 and m3 to the non-conducting condition and control signal Ph1 places transistors m2 and m3 in the conducting condition thereby transferring the charge packet stored on the sampling capacitor Cs to the summing node n3.
It should be noted that while the circuit in FIG. 1 is for a single ended analog input signal voltage for simplification, the actual implementation may be a fully differential analog input signal voltage. Thus, with this understanding, transistors m2 and m3 are connected to a reference voltage, VREF. The summing node n3 is at one input of an operational amplifier A1, say the non-inverting input, and the reference voltage VREF is at the other input, say the inverting input, of the operational amplifier A1. The reference voltage VREF is typically the common mode, or mid-range voltage of the analog input signal voltage. Thus, when the analog input signal voltage is a unipolar voltage (i.e., a voltage which varies with one polarity relative to ground potential, either a positive (+) voltage or a negative (-) voltage), VREF would be +2.5 volts.
In operation, when the analog input signal voltage is at the +2.5 volt, mid-range voltage, it is noted that node n1 is at this mid-range +2.5 volt level during both the charging phase and the charge transfer phase. Thus, there will be no net charge to the integrating capacitor when the analog input signal voltage is at the mid-range voltage. It should also be noted that when transistor m3 is in conduction during the charging phase, the voltage at the summing node n3 is equal to the reference voltage VREF at the other input to the operational amplifier A1.
It should be noted that, in some applications the analog input signal voltage to be converted into digital samples is produced as a bipolar voltage signal (i.e., a voltage which varies with both polarities relative to ground, both positive (+) and negative (-) voltages). In other applications, the analog signal is produced as a unipolar signal and is then fed to a signal conditioning circuit. The signal conditioning circuit may provide amplification and filtering to the analog input signal voltage. These signal conditioning circuits are usually easier, and less expensive to design when a bipolar voltage supply is used. A bipolar supply is a zero, or ground based voltage supply which provides a positive voltage (i.e., a voltage above ground) and a negative voltage (i.e., a voltage below ground). The conditioned signal, which has voltages above and below ground is then passed to the analog to digital converter (ADC). While the signal conditioning circuits are usually less expensive when a bipolar voltage supply is used, the ADC is typically less expensive when a unipolar, (i.e., 0 to 5 volt supply) is used. More particularly, it may be advantageous to use complementary metal oxide silicon (CMOS) transistor technology in fabricating the ADC and supplying the CMOS ADC with the unipolar voltage supply. Thus, if a bipolar voltage supply is used for the signal conditioning circuitry, the ADC, unipolar powered CMOS circuitry is now fed with a bipolar analog input signal voltage, i.e., the range of analog input signal voltages fed to the ADC will be both above and below ground.
It should be noted that if transistor m1 included a nMOS transistor within an n-type conductivity well of the semiconductor substrate, when the analog input signal voltage is negative, the analog input signal voltage would be clamped to the grounded substrate (i.e., the analog input signal voltage would be diode clamped to the grounded substrate). If a pMOS transistor were used for m1, while a negative analog input signal voltage would not produce diode clamping as with the NMOS transistor, a voltage several volts (i.e., about 2 volt) below the analog input signal voltage would be required at the gate electrode of transistor m1 to turn such transistor m1 to the conduction condition. Thus, when the analog input signal voltage is below ground, i.e., negative, a negative voltage is required at the gate electrode of transistor m1 to place such transistor m1 in the conducting condition. One technique used to provide such negative voltage is to use a bipolar voltage supply. Another technique is to shifted the voltage of the analog input signal voltage so that the voltage range fed to transistor m1 will only vary above ground; i.e., so that the voltage fed to transistor m1 will vary from +1.0 volts to +4.0 volts with VREF being +2.5 volts. One technique used to provide such voltage level shift to the analog input signal voltage is to provide a level shifting voltage. However, such level shifting voltage may tend to change with temperature and noise; unlike a more stable ground.

Switched capacitor circuit adapted to store charge on a sampling capacitor related to a sample for an analog signal voltage and to subsequently transfer such stored charge


An antilock brake controller provides an adaptive pressure hold period that interrupts the release of brake pressure during the pressure release phase of an antilock braking pressure control cycle of a vehicle wheel by holding the brake pressure constant while the wheel slip rate is below a threshold that is adjusted as a predetermined function of wheel slip for the front wheels and as a predetermined function of wheel acceleration for the rear wheels.

This invention relates to an antilock control system and method for controlling vehicle wheel brakes.
When the brakes of a vehicle are applied, a braking force is generated between the wheel and the road surface that is dependent upon various parameters which include the road surface condition and the amount of slip between the wheel and the road surface. This braking force increases as slip increases until a critical slip value is surpassed. Beyond the critical value of slip, the braking force decreases and the wheel rapidly approaches lockup. Therefore, to achieve stable braking, an antilock braking control system (ABS) seeks to operate wheel slip at or near the critical slip value.
In one known ABS, the brake pressure is modulated by means of a DC torque motor driving a piston in a cylinder whose volume is modulated to control the hydraulic pressure at the wheel brake. The motor is controlled to position the piston at an initial, fully extended home position at which a check valve is unseated to couple the brake system master cylinder to the wheel brake to allow normal braking. When antilock brake pressure modulation is required, the motor retracts the piston (which allows the check valve to close to isolate the master cylinder from the wheel brake) to reduce brake pressure at the wheel brake and thereafter modulates the piston position to provide pressure control for antilock braking. When antilock braking is no longer required, the motor returns the piston to its extended home position. Typically, in these prior systems, the hydraulic pressure at the wheel brake is established based upon the relationship between motor current, motor torque and the hydraulic brake pressure acting on the head of the piston (wheel brake pressure). Motor current as a representation of wheel brake pressure then becomes the controlled parameter to establish a desired braking condition via the brake pressure/motor current relationship.
During ABS controlled braking, when an incipient wheel lock condition is sensed, an ABS cycle is initiated beginning with a pressure release phase wherein the value of motor current at the time the incipient wheel lock condition was sensed is stored as a representation of the brake pressure producing the maximum braking force coexisting with the critical slip between the wheel and road surface and the motor current is controlled to quickly retract the piston to release brake pressure to allow recovery from the incipient wheel lock condition. When a recovery from the incipient wheel lock condition is sensed, a pressure apply phase is initiated in which the motor current is controlled to extend the piston to reapply brake pressure. During the pressure apply phase, brake pressure is initially established at some value related to the previously stored motor current value and the current is then ramped at a controlled rate to ramp the brake pressure at a controlled rate in direction applying brake pressure until an incipient wheel lock condition is again sensed after which the ABS cycle is repeated. In some applications, a pressure hold phase is provided in a region where the wheel is substantially recovered from the incipient wheel lock condition.
In the pressure release phase of this ABS cycle, it is desirable to rapidly reduce brake pressure when an incipient wheel lock condition is sensed in order to prevent the wheel from locking while at the same time reducing the brake pressure only enough to effect wheel recovery from the incipient wheel lock condition and return the wheel to the stable braking region. According, during the release phase of the ABS cycle, it is desirable to quickly release the brake pressure to a value that will affect recovery from the incipient wheel lock condition, but not to some lower pressure value.

Antilock brake system with closed loop control of hold during release


A data sampler including a first stage and a second stage. The first stage is configured to receive differential signals and provide a first edge rate in a first output signal and a second edge rate in a second output signal based on the differential signals. The second stage is configured to amplify the difference between the first output signal and the second output signal to provide regenerated output signals. The second stage provides a third edge rate in a first internal signal and a fourth edge rate in a second internal signal based on the first edge rate and the second edge rate.

Typically, a computer system includes a number of integrated circuits that communicate with one another to perform system applications. Often, the computer system includes one or more host controllers and one or more electronic subsystem assemblies, such as a dual in-line memory module (DIMM), a graphics card, an audio card, a facsimile card, and a modem card. To perform system functions, the host controller(s) and subsystem assemblies communicate via communication links, such as serial communication links and parallel communication links. Serial communication links include links that implement the fully buffered DIMM (FB-DIMM) advanced memory buffer (AMB) standard, the peripheral component interconnect express (PCIe) standard, and any other suitable serial communication link interface.
An AMB chip is a key device in a FB-DIMM. The AMB has two serial links, one for upstream traffic and the other for downstream traffic, and a bus to on-board memory, such as dynamic random access memory (DRAM) in the FB-DIMM. Serial data from the host controller sent through the downstream serial link (southbound) is temporarily buffered, and then sent to memory in the FB-DIMM. The serial data contains the address, data, and command information given to the memory, converted in the AMB, and sent out to the memory bus. The AMB writes in and reads out from the memory as instructed by the host controller. The read data is converted to serial data, and sent back to the host controller on the upstream serial link (northbound).
The AMB also performs as a repeater between FB-DIMMs on the same channel. The AMB transfers information from a primary southbound link connected to the host controller or an upper AMB to a lower AMB in the next FB-DIMM via a secondary southbound link. The AMB receives information in the lower FB-DIMM from a secondary northbound link, and after merging the information with information of its own, sends it to the upper AMB or host controller via a primary northbound link. This forms a daisy-chain among FB-DIMMs. A key attribute of the FB-DIMM channel architecture is the high-speed, serial, point-to-point connection between the host controller and FB-DIMMs on the channel. The AMB standard is based on serial differential signaling.
PCIe is also a high-speed, serial link that communicates data via differential signal pairs. A PCIe link is built around a bidirectional, serial, point-to-point connection known as a "lane". At the electrical level, each lane utilizes two unidirectional low voltage differential signaling pairs, a transmit pair and a receive pair, for a total of 4 data wires per lane. A connection between any two PCIe devices is known as a link, and is built up from a collection of 1 or more lanes. All PCIe devices minimally support single-lane (x1) links. Devices may optionally support wider links composed of x2, x4, x8, x12, x16, x32, or more lanes.
High speed communication links, such as AMB and PCIe, often use ground referenced signals, such as current mode logic (CML) signals, to communicate data. The data signals are sampled via data sampling circuits, referred to as data samplers, to recover the data. Typically, the data samplers are n-channel metal oxide semiconductor (NMOS) based circuits and level shifters are used to elevate the common mode level of the ground referenced signals for sampling via the NMOS based data samplers. The level shifters use power, in addition to the power used by the NMOS based data samplers. Manufacturers are continually looking for ways to reduce power consumption, especially in low voltage and/or low power applications.
For these and other reasons there is a need for the present invention.

Data sampler including a first stage and a second stage


A plurality of solar cells and a synthetic resin sheet (PET) with good insulating properties are sealed between a glass plate and a protective film (PVF/Al/PVF) by a sealing resin (EVA). The area of an Al foil of the protective film is larger than the area where the solar cells are present and smaller than the aperture area of an aluminum frame body. The solar cells or their wiring tab protrusions do not come into contact with the Al foil of the protective film. Moreover, the Al foil does not come into contact with the frame body at the edge.

The present invention relates to a solar cell module which is mounted on the roof of a house, etc. for photovoltaic power generation.
Photovoltaic power generation for converting light energy into electrical energy by using a photoelectric conversion effect has been widely used as means for obtaining clean energy. Besides, with an improvement in the photoelectric conversion efficiency of solar cells, a photovoltaic power generation system using a large number of solar cell modules is being operated even in private houses.
FIG. 1 is a view showing the outside structure of a general solar cell module, and FIG. 2 is a cross sectional view of a conventional solar cell module cut along the X-X line of FIG. 1. In these figures, the numeral 7 denotes a rectangular frame body made of aluminum. There is a recessed section in the upper half of the frame body 7, and a glass plate 1 and a protective film 50 are mounted in this upper recessed section at a suitable distance therebetween through a filler 6 made from silicone. The protective film 50 comprises weatherproof sheets 50b made, for example, of PVF (polyvinyl fluoride) and sandwiching an Al foil 50a, and has weatherproof properties, particularly high moisture-proof properties. A plurality of solar cells 2 are sealed between the glass plate 1 and the protective film 50 by a sealing resin 3 made from EVA (ethylene vinyl acetate). In some cases, each solar cell has a wiring tab protrusion 2a.
The solar cell module comprising the moisture-proof protective film 50 including the Al foil 50a has an insulation problem for the following reasons. Specifically, there are cases where the internal solar cell 2 or its wiring tab protrusion 2a comes into contact with the Al foil 50a of the protective film 50 (the part A in FIG. 2) and a short circuit occurs between the Al foil 50a of the protective film 50 and the frame body 7 (the parts B and C in FIG. 2) particularly when it is raining, and consequently the insulating characteristics deteriorate.


A method for forming floating gate regions in non-volatile memory cells each having a floating gate and a control gate is disclosed. First, a plurality of isolation structures in a substrate extending above and below a surface of the substrate is formed. Second, a floating gate layer on the substrate over and between at least a portion of the isolation structures is formed. Finally, the floating gate layer is planarized down to the isolation structures for forming a plurality of the floating gate regions isolated by the isolation structures.

1. Technical Field
The invention relates generally to memory cells, and more specifically, to semiconductor non-volatile memory devices.
2. Background Art
In non-volatile memory devices, the placements of the floating polysilicon (floating gate) and control gate of a cell are critical for the proper operability of a non-volatile storage transistor device. That is, the floating gate is required to overlap an isolation structure of the cell, and the control gate must align with the floating gate to ensure the proper formation of the device.
As feature sizes are reduced to sub-micrometer dimensions to achieve higher packing densities of devices, several problems emerge. First, large steps in the control gate can cause processing problems. Typically, the control gate polysilicon is depositing on a non-planar area, and thus will go up and over the floating gate, creating a large step for the control gate. Hence, during subsequent processing, the step in the control gate may become sufficiently steep to either allow the formation of a spacer or cause breaks in the silicide, ultimately degrading the memory cell.
Second, the depth of focus of the lithography stepper becomes smaller. Thus, the different heights of different features generate a depth of field problem.
Finally, a problem known as the "bird's beak" problem occurs where the isolation structure tapers to the substrate in the source and drain regions. Such a taper results in an electrical width smaller than the mask dimensions.
It is evident that the profusion of different heights during processing and the several alignment steps prevent efficient use of advanced lithography processes and other processes to generate high packing densities of devices on a substrate, since the depth of field reduces with the smaller dimensions that are needed for scaling.
Solutions to some of these problems are found in the following U.S. Patents: U.S. Pat. No. 5,559,048, "Method of Making a Double Layered Floating Gate EPROM With Trench Isolation", issued September 1996 to Inoue; U.S. Pat. No. 5,173,436, "Method of Manufacturing an EEPROM With Trench-Isolated Bitlines", issued December 1992 to Gill et al.; and U.S. Pat. No. 5,091,326, "EPROM Element Employing Self-Aligning Process", issued February 1992 to Haskell. These patents disclose self-alignment methods to eliminate some of the problems with the floating gate alignment.
Although the aforementioned patents use self-alignment techniques, some of the techniques have complex processing, and cell size still may not be reduced. Furthermore, in some cases, the control gate still develops a step, affecting the quality of the cell.

Method for planarized self-aligned floating gate to isolation

International Business Machines Corporation


A storage device according to the present invention has a first volume for storing discontinuous data transmitted from a host computer and a second volume for storing continuous data produced by address-converting discontinuous data, and includes: a data storing unit for converting the discontinuous data transmitted from the host computer into the continuous data and storing the continuous data in one of a plurality of third volumes formed by dividing up the second volume; a data management unit for managing transfer target data that has to be transferred from the third to the first volume, from among the discontinuous data stored in the third volume by the data storing unit; and a volume clearance unit for clearing the third volume having the smallest amount of transfer target data managed by the data management unit by transferring the transfer target data in the relevant third volume to the first volume.

The present invention relates to a storage device and control method for the storage device, and is particularly suited for use in a storage device that performs processing for writing discontinuous data to a physical disk.
Conventionally, data write processing to a physical disk in a storage device is largely divided into random write, i.e., processing for writing discontinuous data to a physical disk, and sequential write, i.e., processing for writing continuous data to a physical disk.
Because data transfer performance during sequential write is far greater than during random write in general, data writing to a physical disk can be performed at high speed during sequential write.
As a method for improving random write performance, data write processing in log format (hereinafter referred to as "log format-write"), in which discontinuous data is address-converted in a storage control unit in a storage device and the address-converted data is used as continuous data, has been proposed (see U.S. Pat. No. 6,516,380 B2). A storage device that employs log format-writing has a primary volume, which is a physical disk area for storing usual data, and a log volume for storing data with sequential-converted addresses.
However, the log volume is limited in log format-writing. Therefore, when the available log volume capacity becomes small, processing (hereinafter referred to as "log clearance processing") for clearing the log volume and address conversion table by transferring data in the log volume to the primary volume is necessary.
Moreover, when executing log clearance processing during log format-writing, random write based on data write to the primary volume, which is relevant to normal access to disks performed during non-log format-writing, is always necessary.
Accordingly, when executing log clearance processing in log format-writing, random write for clearing the log volume also has to be performed in the sequential write to the log volume. The random write processing efficiency is then reduced, which obstructs speeding up of the log format-writing.

Storage device and control method for the same


Image acquisition and interpretation method used for articles of commerce, consisting of one or more gondolas or shelves (A) in which shelves (X) are installed, to which are added four repair marks (B, E) that, in combination with a mobile device with a photographic camera (D), will take and process images in an automated way thanks to areas designed for this purpose (C) where reference marks (F, G) are displayed, correcting the perspective deformation and cutting the image to the area delimited by the repair marks, to then send the processed images to a computer server that can index data such as quantity and details of articles, number of units of each, physical characteristics, prices, etc.

Markets are created as humans go from being nomadic to sedentary. At the moment in which the human being begins to have storage capacity and, as a result of specialization, new needs arise for some people, covered with surpluses from others. With the development of the towns, markets have evolved to meet needs of all kinds and have developed to become, at present, one of the most important economic activities for the development of a society.
Given the circumstances of prominence and the economic engine of an increasingly competitive society, markets, today transformed into commercial areas of the largest possible size to supply all the needs of the inhabitants of an area, have an increasingly reduced economic margin where its management must be adjusted to the maximum. Feasibility studies, constant remodeling to adapt to the constant changes in trends of its consumers, advertising by all available means and a long etcetera make the management of these surfaces increasingly complex and review more variables.
One factor to take into account is stock control. The planning of supplies, the financial calculation and use of spaces is part of that matter.
The invention disclosed herein contributes significantly to improving such management.

Method of acquisition and interpretation of images used for commerce items


An application can be dynamically composed and maintained by creating the application within a component framework. The component framework includes components that each implement an integration interface. The integration interface has a number of methods that allow the component framework to manage the lifetime of the component, and which give the component the ability to communicate with the component framework, other components, and external entities.

Building a software application can be a very timely and tedious process. This process may consist of writing a technical specification, pseudocode, or any combination thereof. Thereafter, an application is written in a selected programming language, compiled, debugged, and executed. Modifying a software application can sometimes be just as tedious since a component must be recompiled every time it is modified.
The traditional software development process statically links needed components (functions, etc.) at link time. This means that any components that are to be modified must be modified before an application that uses the component is executed at runtime. Consequently, if the modifications are being worked on, or are incorrect, the application must be shut down until modifications to the component are complete.

Dynamic composition and maintenance of applications


A system and method for hardening dynamic logic against single event upset is described. A precharge circuit is hardened and then connected to two pull down networks. The two pull down networks are redundant and, under normal operating conditions, provide substantially the same outputs when receiving substantially the same inputs. The two outputs are then voted to provide an output that is hardened against single event upset. Alternatively, the two outputs may be connected to a next stage of dynamic logic circuits or other circuitry for evaluation.

Single Event Effects (SEE) are disturbances in an active semiconductor device caused by a single energetic particle. As semiconductor devices become smaller and smaller, transistor threshold voltages decrease. These lower thresholds reduce the charge per node needed to cause errors. As a result, the semiconductor devices become more and more susceptible to transient upsets.
One type of SEE is a single event upset (SEU). SEU is a radiation-induced error in a semiconductor device caused when charged particles lose energy by ionizing the medium through which they pass, leaving behind a wake of electron-hole pairs. The electron-hole pairs form a parasitic conduction path, which can cause a false transition on a node. The false transition, or glitch, can propagate through the semiconductor device and may ultimately result in the disturbance of a node containing state information, such as an output of a latch, register, or gate.
One type of SEU is a single event transient (SET). An SET may occur when a particle strikes a sensitive node within a combinational logic circuit. A voltage disturbance produced at that node may propagate through the logic. As a result of the SET, the combinational logic circuit may provide an erroneous output, which could impact the proper operation of a system that includes the circuit.
Typically, an SEU is caused by ionizing radiation components, such as neutrons, protons, and heavy ions. The ionizing radiation components are abundant in space and at commercial flight altitudes. Additionally, an SEU may be caused by alpha particles from the decay of trace concentrations of uranium and thorium present in some integrated circuit packaging. As another example, an SEU may be caused by detonating nuclear weapons. When a nuclear weapon is detonated, intense fluxes of gamma rays, x-rays, and other high energy particles are created, which may cause SEU.
One circuit family used to implement logic functions is termed dynamic logic. In a typical dynamic logic family, clock signals are used to alternate between two modes of operation. These two modes of operation are called the precharge phase and the evaluation phase. The behavior of these two phases is defined by the use of two transistors and clock signals to control current flow within a dynamic logic gate.
In the precharge phase, the clock signal causes one of the two transistors to be conductive, while the other transistor is non-conductive, which allows current to either enter or depart the output node. Typically, the output node is either charged or discharged to one of the power supplies. If the final state of the output node is the high power supply, then the precharge phase is referred to as a precharge high state. Conversely, the precharge phase is called a precharge low state when the final state of the output node is the low power supply (e.g., ground).
In the evaluation phase, the clock signal switches the two transistors from their respective states in the precharge phase to their respective opposing states (i.e., from a conducting state to a non-conducting state, or vice versa). If the dynamic logic component, based on inputs provided to the dynamic logic component during the evaluation phase, permits current flow during the evaluation phase, then the output of the dynamic logic circuit changes from the precharge high or low state to the opposing state. If the dynamic logic component, based on inputs provided to it during the evaluation phase, does not permit current flow, then the output of the dynamic logic circuit does not change from the precharge high or low state.
Since dynamic logic retains the precharge state unless the dynamic logic component is enabled to conduct current during the evaluation phase, dynamic logic offers several advantages. Compared to static logic designs, dynamic logic requires nearly half as many components to implement a given logic function and can offer considerably faster switching speeds. Thus, the benefits of dynamic logic are particularly important to high speed computing, telecommunications, and information networks.
Dynamic logic is also valuable to military and space-based applications, but circuits in such environments may be at risk of SEUs. An SEU can occur in the precharge circuitry or the evaluation circuitry. An SEU in the precharge and/or evaluation circuits may be sufficient to cause an erroneous result in a circuit using dynamic logic.
Therefore, it would be beneficial to harden dynamic logic circuits against SEU.


A safety mechanism for preventing door slamming includes a board and a pivot extending from the board. A rotatable arm is attached at a first end to the pivot. Door arresting wedge (AW) is attached substantially perpendicularly to the second end of the arm. One or more magnets are disposed on the board for attracting the arm. One or more magnets disposed on an edge of the arm, and a matching stopper is used to limit the rotation of the arm.

Injuries may occur when hands or fingers are caught in a closing door. Such closing doors can cause relatively minor pain and bruises, but may also inflict a greater damage especially when greater force is involved. Typically children and teenagers may be involved in more serious injuries. Schoolchildren playing at recesses between classes are accident prone.
US patent application US2002/000293779, the contents of which are incorporated herewith by reference, discloses a gravity actuated door safety device, which prevents injury to fingers and pet's tails. a swinging door safety device including a pair of spaced parallel bars connected to one another at one end by a crossbar. At the opposite end of each bar, a counterweight is provided. Each bar has a ring attached at a point between the first and second ends. With the rings mounted to oppositely facing door knobs such that the crossbar spans the leading edge of the door, gravity acting on the counterweight biases the device to rotate such that the bars extend outward from the leading edge and prevent closure of the door by contacting the door jamb.
US patent application US2002/157319, the contents of which are incorporated herewith by reference, discloses a mechanism for preventing injury to a person's hand when a fast-closing door slams a door frame or jamb. The mechanism includes a casing which is positioned within a hollowed out portion of the door. The casing is constructed with an opening disposed along the edge of the door panel. A metallic pendulum is housed and suspended within the casing such that the action of centrifugal force imparted by a fast-closing door will cause the pendulum to swing outwardly through the opening. A raised metal body is attached to the side molding of the door jamb and functions to engage the outwardly swung pendulum to prevent the door from completely closing.


A power supply supplies power from a bus at a hub to a peripheral over a bus which plugs into a connector at the hub, the connector having a plurality of contacts, including at least two power contacts the power supply. When the bus is plugged into the connector, a mated contact is provided in the connector at the hub. When a mating connector on the bus is plugged in, one of the plurality of contacts is shorted to the mated contact. The sensed shorting at the mated contact is used to control the ramping of current on the power lines of connector.

The present invention relates to the supply of power to peripherals in general and more particularly, to a method and apparatus which enables the control of current ramp-up when a peripheral is coupled to a bus.
Computer users have found a need to couple an increasing number of peripherals to their computers. In order to accommodate this, a number of buses have been developed. One such bus is known as the Universal Serial Bus (USB). The USB is a low-to-medium speed serial bus developed by the Intel Corporation to address peripheral expansion outside the PC system box. The USB is a peripheral bus standard that permits the use of plug and play computer peripherals outside the box, reducing the need to install cards into dedicated computer slots and reconfigure the system. In personal computers equipped with USB, computer peripherals can be automatically configured as soon as they are physically attached without the need to reboot or run setup. USB also allows up to 127 devices to run simultaneously on a computer, with peripherals such as monitors and keyboards operating as additional plug-in sites, or hubs.
USB will accommodate telephones, modems, keyboards, mice, 4.times. and 6.times. CD ROM drives, joysticks, tape and floppy drives, scanners and printers. USB's 12 megabit data rate will also accommodate a whole new generation of peripherals, including MPEG-2 video-based products, data gloves and digitizers. Also, since computer-telephony integration is expected to be a big growth area for PCs, USB will provide a low-cost interface for Integrated Services Digital Network (ISDN) and digital PBXs.
Drawing its intelligence from the host PC, USB detects when devices are added and removed. The bus automatically determines the host resource, including driver software and bus bandwidth, each peripheral needs and makes those resources available without user intervention. Users with a USB-equipped PC will be able to switch out compatible peripherals as needed as easily as they would plug in a lamp.
USB transfers signals and power over a four wire cable. The signaling occurs over two wires in point-to-point segments. The cable also carries Vbus (VCC) and GND wires on each segment to deliver power to peripheral devices. Vbus is nominally +5 V at the source. Each USB segment provides a limited amount of power over the cable. The host supplies power for use by USB devices that are directly coupled to it. In addition, any USB device may have its own power supply. USB devices that rely totally on power from the cable are called bus-powered devices. In contrast, those that have an alternate source of power are called self-powered devices. A hub also supplies power for its coupled USB devices.
The connectors used with the bus are four pin connectors in which the pin assignments are as follows:
pin 1 VCC (Cable power or Vbus) PA1 pin 2-Data PA1 pin 3+Data PA1 pin 4 Ground (Cable ground)
Detailed specifications for the USB including the power supply and the connectors may be found in Universal Serial Bus Specification, Revision 1.0, Jan. 15, 1996, Copyright.COPYRGT. 1996, Compaq Computer Corporation, Digital Equipment Corporation, IBM PC Company, Intel Corporation, Microsoft Corporation, NEC, Northern Telecom.


A boat is capable of preventing shocks on gears in meshing engagement with each other and an abrupt movement thereof when a remote control shift lever is quickly rotated to reverse from a cruising mode. A control microcomputer is arranged to control the operation of a shift actuator based on the displacement of a remote control shift lever for remotely switching between forward, neutral, and reverse positions. The control microcomputer has a shift detector arranged to detect whether a shift operation from the neutral position to the forward position or the reverse position was made based on a signal from a lever position sensor arranged to detect the position of the remote control shift lever; and a switch control which does not drive a shift motor when a shift operation from the neutral position to the forward position or the reverse position is detected by the shift detector and the engine rotational speed detected by the engine rotational speed sensor is higher than a prescribed value, and drives the shift motor and controls a shift operating device to start shifting when the engine rotational speed decreases to a value equal to or smaller than the prescribed value.

1. Field of the Invention
The present invention relates to a boat propulsion unit and a boat having the boat propulsion unit in which shifting between forward, neutral, and reverse is electrically performed by remote control.
2. Description of the Related Art
One conventional boat of this type is disclosed in JP-A-2005-297785.
It is described in JP-A-2005-297785 that a shift device includes a remote control operation device having a remote control shift lever for remotely shifting between forward, neutral, and reverse; a boat propulsion unit having a shifting device for shifting between forward, neutral, and reverse, and a shift actuator for driving the shifting device; and a controller for controlling the operation of the shift actuator based on the displacement of the remote control shift lever when the remote control shift lever is operated within a prescribed shift range from a neutral position; wherein the controller controls the operation amount of the actuator with respect to a unit displacement of the remote control shift lever such that it is different in different sections of the shift range.
However, in such a conventional device, when the remote control shift lever is quickly rotated to reverse from an advancing mode to make a shift-in in the opposite direction, a shift-in to reverse is done before the engine rotational speed and the boat speed are sufficiently reduced. Then, a shock at that time may be exerted on the gears in meshing engagement with each other and the boat may have an abrupt movement.
That is, when the remote control shift lever is quickly rotated to reverse from a forward mode to make a shift-in in the opposite direction, since a force urges the propeller to rotate in the opposite direction while the propeller is still rotating in the forward direction and an inertia force in that direction is generated, a large force is generated between the gears on the propeller side and the gears on the engine side. Then, a shock at that time may be exerted on the gears, and the boat may have an abrupt movement.


A system and method of drilling oil and gas wells in arctic or other environments having adverse conditions. A marine hydrocarbon operations structure may comprise a caisson body having a top surface which defines an opening and a shaft positioned within the opening. The shaft has an engagement member positioned on the external surface of the shaft. A lower jack house system is constructed and arranged to change the vertical position of the shaft through interaction with the engagement member. An operations platform supported by the shaft.

This section is intended to introduce various aspects of the art, which may be associated with exemplary embodiments of the present invention. This discussion is believed to assist in providing a framework to facilitate a better understanding of particular aspects of the present invention. Accordingly, it should be understood that this section should be read in this light, and not necessarily as admissions of prior art.
There was never a shortage of challenges facing the offshore industry in deep-water or arctic frontiers. Nowadays, however, the challenge is particularly daunting with the merger of the two frontiers in new arctic deep-water leases, such as the Beaufort Sea, Chuckchi Sea, Kara Sea and elsewhere. These regions typically accumulate extreme amounts of ice during a majority of the year. Even when sheet ice is not present, these Arctic regions often face drifting ice floes. The industry is aware of substantial reserves of hydrocarbons present in such regions, particularly in areas below relatively shallow waters.
Due to the increased interest in oil and natural gas exploration in these regions, consideration is first given to conventional drilling platforms. These, however, are not suitable for the adverse conditions because of their inability to withstand ice loads. Without the proper precautions and designing, drifting ice presents high-levels of risk to the drilling units.
However, known drilling units designed for application in the Arctic and other ice-heavy environments have a variety of issues. One known technique may be collectively referred to as artificial islands and barges. These structures have typically been used in very shallow waters, such as 10 to 15 m. These artificial islands and barges have been utilized in the Canadian, Caspian Seas, to name an example. Unfortunately, their use beyond these water depths is typically impractical and cost-prohibitive, besides their potential environmental impact. Moreover, artificial islands are purpose-built to drill only one well, hence they are not easily mobile.
Another concept utilizes a caisson-type gravity-base structure (GBS). The use of a GBS is typically suitable for shallow waters (20 to 40 m), and the GBS also exhibits significant lateral capacity to resist ice loads. However, due to their constant height, these concepts cannot accommodate a range of water depths. Therefore, that precludes them from providing a constant water clearance which hampers safe lifeboat evacuation
Jack-ups or fortified jack-ups may be applied in the Arctic. While these structures can provide a constant clearance in a range of water depth, they suffer from limited foundation and jack-up leg capacity that typically preclude them from drilling in significant ice conditions. Even in open water season, they may not be able to resist a drifting ice floe or iceberg which may be present even in that season.
Floating systems are designed for deeper water depths (such as 100-150 m). However, known floating systems are limited by their insignificant station-keeping capacity compared to drifting ice or iceberg demands. Hence, they are limited to open water season, and even then require the use of icebreakers and a well-thought ice management plan.
Lastly, variable seafloor conditions, including very soft clays, often occur at Arctic and other sites. GBSs are typically the platform of choice to resist harsh environmental conditions, such as, but not limited to, ice forces experienced in the Arctic. Concrete or steel skirts are generally used to provide extra resistance to prevent the GBS from sliding due to ice forces, but they are expensive to construct and they need to be specifically designed to match site specific soil conditions.
Thus, there is a need for improvement in this field.

Arctic telescoping mobile offshore drilling unit


The present invention relates to a lamp having synthetic ceramic glass electrodes, which comprises a glass tube, a plurality of synthetic ceramic glass electrodes, and a plurality of connecting members. The plurality of connecting members are disposed between the glass tube and the plurality of synthetic ceramic glass electrodes. The plurality of connecting members have different thermal expansion coefficients. Thereby, by using the plurality of connecting members to connect the plurality of synthetic ceramic glass electrodes, the glass tube and the plurality of synthetic ceramic glass electrodes can be sealed tightly.

A daylight lamp, also called a fluorescent lamp, a sun lamp, or a fluorescent light, is a lighting apparatus. It belongs to a kind of arc light and uses electric power to stimulate mercury vapor in argon or neon ambient for forming plasma and emitting ultraviolet light having a short wavelength. After the ultraviolet light is absorbed by phosphorus, the phosphorus will emit visible light for lighting. The light emitted in this method is fluorescent light.
Take a general fluorescent tube for example. A closed fluorescent tube is filled with low-pressure argon or argon-neon mixture gas and mercury gas. The inner surface of the glass fluorescent tube is coated with phosphorus fluorescent paint. Tungsten filament coils are disposed on both ends of the fluorescent tube. When the power is turned on, the current first passes through the filament for heating and electrons are released. The electrons will transform the gases inside the tube into plasma and amplify the current therein. When the voltage across the two filament sets exceeds a certain value, the fluorescent tube starts to discharge, enabling the mercury vapor to emit ultraviolet light with wavelengths of 253.7 nm and 185 nm. The phosphorus fluorescent paint on the inner surface of the fluorescent tube can absorb the ultraviolet light and emit visible light with longer wavelengths. The color of the emitted light is controlled by the proportion of the phosphorus. The adoption of the glass tube is to avoid leakage of hazardous ultraviolet light and other harmful materials such as mercury.
In the fabrication of lamps according to the prior art, electrode members are disposed on both ends of a fluorescent tube. Inside the fluorescent tube, it is a closed space. The gas inside the closed space is pumped out to make it in the vacuum state. Then the required gas, such as argon or argon-neon mixture gas and mercury gas, is added. The electrodes are fixed inside the fluorescent tube at both ends and used for sealing this fluorescent tube and forming a closed space. Then glue is coated inside the tube before fixing the electrodes at both ends. Nonetheless, the difficult part of this technology is that the glue coated inside the tube tends to flow into the closed spaced of the fluorescent tube and is mixed with the gases therein. This affects the light-emitting efficiency of the lamp.
Furthermore, in order to improve the above problem, electrode members are disposed on both ends outside a fluorescent tube. Glass rings are disposed between the electrode members and the fluorescent tube and used for fixing and sealing the gaps therebetween. Nonetheless, due to the difference in thermal expansion coefficients of the electrode members and the fluorescent tube, after cooling and fixing the rings, the electrode members, and the fluorescent tube, gaps occur, resulting in ineffective sealing of the fluorescent tube.
Accordingly, the present invention improves the sealing structure and provides a lamp having synthetic ceramic glass electrodes.

Lamp having synthetic ceramic glass electrodes


The invention relates to a side view mirror assembly (10) comprising a first mirror (12) and a second mirror (12), a lower arm (24, 240) and an upper arm (18, 180) for mounting said assembly to a vehicle, wherein said lower and upper arms (24, 240, 18, 180) are linked by a structural element (30), wherein first and second mirrors (12, 14) are coupled to respective lower and upper arms (24, 240, 18, 180) and in that said structural element (30) integrates the first and second mirrors (12, 14) and is transparent.

A side view mirror is found on the exterior of most motor vehicles for the purposes of assisting the driver to see areas behind and to the sides of the vehicle, outside of the driver's peripheral vision (in the 'blind spot'). Typically, although not necessarily exclusively, a side view mirror is mounted on each side of the front doors of a vehicle, normally at the A-pillar thereof.
For many years, legislation in several countries has required vehicles over a certain size/weight to be fitted with a main side view mirror and also with a wide angle mirror to improve the driver's visibility of pedestrians or cyclists, especially when the vehicle is making a left turn (right hand drive vehicles) or a right turn (left hand drive vehicles). For example, in 2009, a new EU Directive came into force stipulating that all vehicles over 3.5 tons need to be fitted with a wide angle mirror (Class IV) as well as the main mirror (Class II).
Side view mirror assemblies incorporating a Class II and Class IV mirror have been proposed. One such assembly comprises a first and second mirror, each mounted within respective first and second opaque rear housings. The housings are connected together by means of one or more connecting member, such that the mirrors are vertically aligned and, in some cases, spaced apart from each other with a small gap therebetween. Each mirror may be independently pivotally adjustable about a generally central vertical axis to allow the driver to adjust their field of view as required. Upper and lower arms are provided, typically on the larger of the two housings, for affixing the assembly to the vehicle.
There is an ongoing desire to further improve and enhance driver visibility, whereas a side view mirror assembly of the type described above can obstruct the user's forward (direct) field of view which, in some circumstances may be detrimental. Whilst a driver can, in some cases, see through the space between the first and second mirrors in prior art assemblies, their view will inevitably be obstructed by the connecting member between the two housings, as well as the periphery of the housings themselves.
U.S. Pat. No. 4,325,609 discloses a side view mirror arrangement for a heavy duty vehicle comprising a transparent backing means attached to the frame for holding the plane mirror and convex mirror such that the forward view through the mirrors is also through the backing means. Thus, the backing means is transparent and permits viewing through both mirrors in a forward direction. However, such an assembly would not comply with current regulations, which require at least 70% reflection of vehicle mirrors. Furthermore, in the described assembly, the mirrors are provided on the same support, such that there is no possibility of independently adjusting the relative positions thereof.


A programmable size and price setting mechanism for use in a vending machine has a plurality of .eta. access doors aligned horizontally across a front of the vending machine, each of which access doors has a locked condition denying access therethrough and an unlocked condition allowing access therethrough, and each of which is selectably activatable between the locked and unlocked condition. There are a plurality of horizontal shelves each of which has a plurality of partitionable areas corresponding in size to a corresponding one of the .eta. access doors, such that each shelf is selectably partitionable into a plurality of up to .eta. product holding areas. A conveyor mechanism is provided for selectably moving each horizontal shelf into a vending position adjacent to the access doors so that each one of the .eta. partitionable areas is adjacent to a corresponding one the .eta. access doors. A sensor detects when one of the plurality of shelves is positioned adjacent to the plurality of .eta. access doors. A keypad with a plurality of actuatable buttons is pivotably mounted on the vending machine for use by a consumer in a "vending mode" of operation and for use as a programming keypad to set compartment sizes and product prices when in a "service mode" of operation. A money receiving and value detection device is also provided. Programmable control circuitry is operatively interconnected with the keypad to the shelf position sensor and to the money receiving and value detection device for activating a selected one or more of the .eta. access doors from the closed to the opened condition and positioning the selected one of the plurality of shelves and compartments into position adjacent to the access doors, upon detecting a programmed value of money received, and upon actuation of appropriate keypad buttons to select the desired compartment to actuate one or more of the .eta. access doors through which access to one of the desired product holding areas is achieved.

Previously, vending machines of the type which held and displayed products on horizontal shelves have been constructed with a plurality of vertically stacked trays having a fixed number of partition areas on each tray for holding products to be vended. The horizontal shelves permitted display and vending of products having various shapes and sizes, such as fruit, sandwiches, prepared salads, prepared dinner plates, dairy products in containers, fruit drink cans, or other varieties of items which are not necessarily foodstuffs. At each vertical level, there was an openable door behind which a desired partitioned area could be positioned. Payment of a required fee and selection of a particular product by moving the partitioned area to the door permitted the door to be opened for removing the product.
One such device provided a plurality of rotatable circular trays with a display window and a single openable door at each level. The items could be selected by rotating the tray past the display window until a desired selection was adjacent to the openable door. Payment of the indicated purchase price allowed the door to be opened so that the selected item could be removed. Each separate tray would be partitioned into a plurality of product holding areas, each the same size as the others. Upon payment of the appropriate price for a product on a given tray, the vending door was openable only to the extent required to reach the product. In this manner, any given tray would be stocked with products of substantially equal size and equal value so that payment of the amount of money indicated for all of the items on a given tray would allow the door to be opened. A degree of variability was accomplished by providing a door with capabilities of pre-setting its opening size. A small opening was set corresponding to small partitioned areas, and a larger opening was set corresponding to larger partitioned areas. Trays at different levels could have different size partitioned areas, but all of the partitioned areas on a single tray had to be the same size. A given tray construction could be variably partitioned to accommodate different sizes, provided the entire tray was partitioned with the same size areas. A single preset opening size was needed for the entire tray at each level.

Pivot keypad and dual interface for multiple price and size setting vending machine


A method and apparatus for accessing a memory device. The method includes providing control signals for an access command to the memory device via an asynchronous interface and transmitting data for the access command to the memory device. The method also includes encoding, into the transmitted data, a clock signal. The encoded clock signal in the transmitted data is used by the memory device for receiving the data transmission.

Communications within modern computer systems may occur at regular intervals, for example, as governed by a clock signal. For example, during a data transmission, a group of data may be transmitted during each rising edge of the clock signal. Communications performed with a clock signal are often referred to as synchronous communications. Synchronous communications systems may sometimes be preferred over asynchronous communications systems. In asynchronous systems, communications are performed by asserting handshaking signals which indicate when data being transmitted is valid and has been correctly received by the receiving device. Synchronous systems may be preferred over asynchronous systems, for example, because synchronous systems may perform communications more quickly without the overhead of the handshaking signals.
In some cases, different devices in a computers system may inherently perform operations at different speeds, for example, due to differences in both design and manufacturing. Even devices manufactured using the same manufacturing process may also perform operations at different speeds due to process variations between batches and even due to process variations within a single batch. Because different devices in a given system may operate at different speeds with respect to each other and with respect to other systems, it may be difficult to establish a clock frequency to be used with each manufactured system.
In some cases, designers may establish a maximum clock frequency which is low enough so that the majority of components in each manufactured system are capable of performing operations at the established clock frequency. Where a manufactured system is incapable of operating at the established maximum clock frequency, the system may be discarded as defective, thereby increasing waste in the manufacturing process. Furthermore, establishing a common clock frequency for communications systems may result in faster manufactured systems operating unnecessarily slowly at the established clock frequency. Furthermore, operating a system which communicates using a common clock signal may increase power consumption as the common clock signal is continually generated and transmitted to each of the devices in the system.
Accordingly what is need are an improved system, apparatus, and method for performing data transmission.


An automatic method and apparatus in a computer system of cache detection. Accessing of data stored at first specified boundaries in a memory of the computer system corresponding with a first size of a cache is timed to produce a first timing value. Accessing of data stored at second specified boundaries in the memory of the computer system corresponding with a second size of a cache which is greater than the first size is timed to produce a second timing value. If the second timing value exceeds the first timing value by a threshold then the presence of a cache of the first size is indicated. This can also be performed iteratively until the memory of computer system has been completely tested for the presence of any caches. The process may be performed for instruction or data caches wherein the accessing of data for data caches includes memory access instruction, and the accessing of data for instruction caches includes the execution of instructions. Methods and apparatus for determining other cache characteristics are also described including detecting the set associativity of any known caches, and whether the known data and instruction caches are unified or not.

1. Field of the Invention
The present invention relates to caches in computer systems. More specifically, the present invention relates to a method and apparatus which detects the presence of a cache and, if any is present, the characteristics of the cache.
2. Background Information
As part of the normal self-test routine of a computer system, the presence and validity of a cache contained within the system is normally performed. Cache memory in different computer systems varies widely from system to system. Different chipsets report different cache sizes differently. Prior art methods of determining cache size have been limited to programs specific to particular chipsets that query the chipset for the cache size information. That is , a different program needs to be written for each different chipset.
Cache size and characteristics have been set in many previous environments via the use of jumper settings or other hardware configurations on a computer system motherboard. If the hardware configuration does not correspond with the resources in the system, however, the cache size and type will be reported incorrectly.
Prior art techniques have also been lacking in determining specific characteristics of caches, such as multi-levels of caches. Techniques which can apply to any computer system are lacking which allow the determination of the set-associativity of a cache. Lastly, the prior art lacks a generalized method for determining whether data and instruction caches are unified.
Thus, one prior art need is a single methodology which would detect the presence and size of caches in a variety of computer system architectures with different chipsets. In addition to size and presence of a cache, type (e.g., instruction, data, or unified cache) and set associativity of caches as well may be required to be determined. Also, multiple levels of caches should be able to be determined using a single technique applicable across a wide variety of computer system chipsets and computer system architectures to avoid the deficiencies of the prior art.

Cache detection using timing differences