A method for forming a protective barrier layer between the active dye layer and the disc substrate during production of an optical memory disc is provided wherein a pre-treatment/pre-coat solution is applied to the disc substrate. This pre-treatment/pre-coat solution includes a surface modifier having an index of refraction approximately equal to that of the disc substrate. Surface modifiers utilized in this pre-treatment/pre-coat solution include poly vinyl alcohol, poly alpha methyl styrene, cellulose acetate, poly vinyl butyral and nitrocellulose.

The typical structure of a CD-R or DVD-R optical memory disc includes an energy absorbing dye layer formed directly over an injection molded polymeric substrate. Next, a thin film reflective layer is formed directly over the dye layer, usually via magnetron sputtering. Finally, a radiation curable protective lacquer is spin coated directly over the reflective layer. The reflective layer also functions as a barrier to isolate the dye layer from the uncured protective lacquer.
In most optical memory disc structures, dielectric layers are also formed between the active recording layer and adjacent layers, in order to protect the substrate and reflective layers from exposure related damage, and to encapsulate the active recording layer, protecting it against chemical contamination and long term deterioration. In a typical CD-R or DVD-R disc, these additional layers are omitted to reduce manufacturing cost. The dye (active recording layer) is coated directly onto the surface of the polymeric substrate, and the reflective layer is formed directly over the dye layer. Consequently the dye/substrate interface, and the dye/reflective layer interface are directly effected by the recording process. Because CD-R and DVD-R are "write once" formats, cumulative degradation does not develop as it would in a re-writable optical memory disc. However, cumulative degradation is not the only concern. The physical and chemical characteristics of the interface between the dye and substrate, and the dye and the reflective layer effect the exposure and read back performance of the optical memory disc. For example, the energy associated with the exposure process effects the surface of the polymeric substrate at the interface with the active recording layer. This causes an intermixing of decomposed dye and polymer. The degree of intermixing is related to the time at temperature profile created during exposure. When a recording format with a large range of pulse widths is employed, as is the case with CD-R and DVD-R, the longer pulses tend to be distorted by this mechanism. Another problem is distortion of the thin film reflective layer by the heat and pressure created during exposure. This distortion extends beyond the location of the intended mark, and has the effect of increasing the apparent size of the recorded mark. The negative effects of this distortion are most apparent when the spaces between recorded marks are short. Mark length deviation, inter-symbol interference, and jitter performance are all negatively effected by this "doming" effect. The exact profile of this distortion depends on the physical properties of the reflective layer, adhesion between the reflective layer and the underlying layer, and the characteristics of any layers coated on top of the reflective layer, such as a protective lacquer or bonding adhesive.
Reflective films thicker than approximately 100 nm tend to resist distortion caused by the exposure process. However, thick reflective layers typically exhibit higher stress which can lead to a variety of long term reliability problems. Additionally, the high thermal conductivity of typical metallic reflective films effects overall record sensitivity, and alters the thermal profile that develops during the formation of individual recorded marks. Consequently, reflective layer thickness cannot be arbitrarily changed in order to minimize physical distortion.
Disc manufacturing problems also result from inadequate preparation of the polymeric substrate. Due to well-known variables associated with the injection molding of plastics, the surface characteristics of the substrates are not absolutely constant. Without some means to provide a uniform and consistent surface condition, these variations in the substrate will effect the dye coating process and, therefore, achievable disc performance.
Further, the solvents used to prepare the dye for spin coating extract volatiles from the plastic substrate during the spin coating operation. This results in non-uniform spin coating performance, and contamination of the excess dye solution that is spun off of the disc. Typical substances that are leached out of the substrate include stabilizers, molding release agents, degraded polymer, residual monomer (etc.), and various adsorbed contaminants from the local environment. Correcting this situation will improve dye coating consistency, and increase manufacturing yield. Reducing contamination of the excess dye solution will allow the dye to be recycled more times, further reducing manufacturing costs.
The traditional solution to this problem would be to vacuum coat a thin film dielectric barrier onto the substrate prior to spin coating the dye. Unfortunately, this approach is complex and has the added disadvantage of high initial equipment cost.
Alternatively, treating the substrate with ultraviolet light, or a combination of ultraviolet light and ozone, will create a clean, uniform surface. Unfortunately, this is only a surface effect and does not reduce the tendency for volatiles to be leached out of the substrate by the solvents used in the dye solution.
Pre-rinsing the substrate surface with a solution that extracts volatiles, dilutes them, and washes them away will tend to reduce subsequent dye solution leaching of these substances. However, pre-rinsing the substrate surface with a buffered solvent will not guarantee a uniform surface with a stabilized, low level of extractables.
Therefore, it has been found desirable to provide an economical, pre-treatment/pre-coating layer between the disc substrate and the active dye layer of an optical memory disc which not only extracts volatiles, dilutes them, and washes them away, but also provides a uniform barrier to subsequent leaching by the solvents used for the dye solution. Moreover, it has been found desirable to provide a protective barrier layer which does not significantly alter the optical tuning of the disc structure, in order to minimize manufacturing complexity and cost.

Method for forming a protective barrier layer on an optical memory disc substrate


A connector for attaching at least one flexible tube to a fluid passage of another object includes a body and at least one connector port on the body. At least one tube port projects from the body and is adapted for fluid communication with the connector port. A portion of the body at least partially surrounds the tube port and defines an interior space containing at least a portion of the tube port. The tube port is sized and shaped for being received in an end of the flexible tube to establish fluid communication with the flexible tube. A tube retainer is at least partially disposed in the interior space defined by the portion of the body and has an engaging portion disposed in relation to the tube port to restrain the flexible tube from lateral movement with respect to the tube port.

In a medical environment, many devices have a fluid connection to other devices or to a patient that is made by flexible tubing. One example is the connection of an air compressor to an inflatable bladder in a compression device used in deep vein thrombosis therapy. When connecting a medical device to a fluid supply, a non-leaking seal must be made between compatible devices and/or fluid sources. Thus, connections must be designed to provide an adequate seal between sealing surfaces when the devices and/or supply are compatible. Typical devices have a male and female connector that, when pressed together, form a fluid tight seal. The connectors come in different sizes and shapes and typically have ports, O-rings or gaskets to help create a fluid tight seal.
Typical compression therapy devices are wrapped around a limb to prevent peripheral edema and conditions such as deep vein thrombosis. These devices typically include at least one air bladder that is sized and shaped for being applied on or around the limb. The bladder is sequentially inflated and deflated to artificially stimulate blood flow throughout the appendage that would normally result from, for example, walking.
An example of such a device that is configured for disposal about a foot is shown in U.S. Pub. No. 2005/0187499 and a device configured for disposal about the leg is shown in U.S. Pub. No. 2005/0187503. Typically, these compression therapy devices are connected to a tube set which provides fluid communication from a pressure source (e.g., an air compressor) to the compression therapy device. A controller is employed to regulate the flow of fluid from the pressure source to the compression therapy device.
The compression therapy device, tube set and controller each contain connections for connecting and disconnecting the compression therapy device from the pressure source. Often the compression therapy device includes a plurality of bladders and separate tubes for independently inflating each bladder. The connectors include a plastic housing having at least one tube port for connecting to a tube and, in many instances include a plurality of tube ports. The housing is more rigid than the flexible tubing, and also is capable of being connected via a mating connector to other tubes or to the controller.
Typically the tube ports of the connectors are received within the tubes. During disconnection of mating male and female connectors, the practitioner often grasps the tubes and pulls such that the male and female connectors become separated. This causes bending forces to be applied to the tube ports that result in one of the tube ports breaking off from the housing of the connector. This is particularly a problem with connectors that attach to controllers of sequential compression devices as the controller is typically stationary and the connectors are not at the same height as the practitioner.
Hashimoto, U.S. Pat. No. 4,478,436 shows a hose clam shell style sleeve that fits around tubes that are connected to a fitting. The tubes fit in semicircular slots in the sleeve. The separate sleeve is not practical in use and may be come easily lost. Dye, U.S. Pat. No. 4,804,208, shows a connector that has a narrow slot in a cover through which the tubes project into the connector for attachment to ports. The cover is also a separate part that may become lost.

This patent is subject to a terminal disclaimer.


Pulp fiber containing little ash is effectively recovered from a used sanitary product containing the pulp fiber and a polymer absorbent. The method according to the present invention comprises: a step for treating the used sanitary product with an ozone-containing gas and thus decomposing and removing at least a portion of the polymer absorbent in the used sanitary product; and a step for stirring the used sanitary product, that has been treated with the ozone-containing gas, in water or an aqueous solution containing an antiseptic and thus decomposing the used sanitary product into constituents. If required, the method may further comprise a step for separating the pulp fiber from the decomposition product obtained by the decomposition step.

It has been attempted to recycle used sanitary products such as disposable paper diapers. For recycling of used sanitary products, it is common to disintegrate the used sanitary products in water, separating them into the constituent components of the sanitary products, which are then recovered. However, the polymer absorbents that are included in sanitary products absorb moisture and increase in mass, while also gelling and losing their flow property, causing the throughput capacity of the treatment apparatus to be reduced.
Patent Document 1 therefore discloses using lime for dehydration of polymer absorbents in used paper diapers that have absorbed moisture (claim 2). This reduces the weight of the polymer absorbent, while also restoring the gel state to the original state and recovering its flow property, so that reduction in the throughput capacity of the treatment apparatus can be avoided (paragraph [0020]).

Method for recovering pulp fiber from used sanitary product and recycled pulp obtained thereby


A method for transforming radiological image data from a digital receiver obtains digital image data values from the digital receiver and compensates for exposure response differences between a screen film system and the digital receiver. Modulation transfer function differences between the screen film system and the digital receiver are compensated and noise content at frequencies approaching the Nyquist frequency for the digital receiver is suppressed.

Conventional radiography uses photostimulable phosphor screens and photosensitive silver-halide film media for recording images of human anatomy. CAD/CADx algorithms have been developed to assist radiologists and physicians to detect and diagnose various diseases. Before digital radiography (DR) systems became widely available, a considerable amount of research and development effort had been expended, over a period of about twenty years, to train and optimize CAD/CADx algorithms based on film images digitized with film digitizers.
Advances in imaging technology now make it possible to capture radiography images directly as digital data, without the use of photosensitive film. Digital imaging can be performed using computed radiography (CR) apparatus that records image data on an erasable sheet of stimulable storage phosphors and using direct DR apparatus that obtains image data directly from received radiation. In this specification, CR and DR collectively are referred to as digital radiography imaging systems. Digital receivers of these types are particularly advantaged, not only for their wider dynamic range over conventional screen/film imaging, but also because they create new opportunities to separate and individually optimize image capture, processing, and display processes of the overall imaging chain.
Although digital radiography imaging systems enjoy advantages over conventional screen/film-based systems, they impose a new challenge to the existing base of CAD/CADx algorithms. As is well known to those skilled in the diagnostic imaging arts, screen/film, CR, and DR imaging modalities exhibit very different response characteristics with respect to radiation intensity, image sharpness, system noise, and other factors. CAD/CADx algorithms that are particularly trained and optimized for use with digitized data from screen/film systems may not perform well when provided with raw (unprocessed) data from the digital radiography imaging system.
FIG. 1 shows a typical response of the screen/film system between the incident x-ray exposure level (E) and the film density (D), which generally follows a sigmoid shape between D and the logarithm of E. Digital radiography systems, on the other hand, generally record the x-ray exposure level in linear exposure space, then optionally convert this into logarithmic exposure space.
Following the pattern used for the Digital Imaging and Communications in Medicine (DICOM) standard, digital radiography imaging systems output the image data in either of two main formats. These formats differ from each other in function and in data representation and are appropriately termed "For Processing" and "For Presentation" formats. Referring to the block diagram of FIG. 2, raw image data from a digital detector 10 is conditioned by a processor 12 that provides either or both types of output, either For Presentation data for a display 14 or data For Processing by a CAD system 20 or other image processing systems.
For Presentation data are used for input to film printers or diagnostic workstations, so that the displayed films on a light-box or the displayed images on a diagnostic workstation would be directly suitable for visual assessment by radiology personnel for diagnosis. A number of methods were initially devised for improving the appearance of images obtained from CR or DR digital detectors, so that the digital image resembles and improves the corresponding film image. One example technique for improvement of the presentation image is described in commonly assigned U.S. Pat. No. 6,778,691 entitled "Method of Automatically Determining Tone-Scale Parameters for a Digital Image". As radiologists become more familiar with the digital "look" created by digital image processing, their preferences gradually shift toward images with additional spatial processing such as edge sharpening (U.S. Pat. No. 5,369,572) and dynamic range compression (U.S. Pat. No. 5,317,427). Because For Presentation data are optimized for display and visual assessment, edge characteristics associated with various disease features in the image can be artificially modified by the image processing algorithms that improve visual contrast enhancement (for example, spatial processing). However, because of this modification, this same For Presentation data can be unsuitable for the CAD/CADx algorithms that have been trained based on digitized film images.
For Processing data overcome the problem associated with the For Presentation data and are intended for applications such as CAD/CADx. For Processing data is usually the unprocessed raw data of the digital radiography imaging systems, that is, the original image data provided either in linear exposure space or in logarithmic exposure space. However, in practice, such data may not be directly usable by the CAD/CADx algorithms or may yield poor algorithm performance. The digital data needs some amount of preprocessing in order to compensate for differences in imaging characteristics between screen/film systems and digital radiography imaging systems in terms of exposure response, sharpness, noise, and other characteristics.
There is, then a need for data conversion methods for CAD/CADx that allow digital radiography data to more accurately emulate digitized data received from scanned films.

Tone scale transformation for radiological images


A PCI-bus is added to a VESA local bus (VL-bus) computer system using a VL-bus/PCI-bus bridge. The VL-bus/PCI-bus bridge claims a VL-bus cycle by asserting LDEV# to the VL-bus/system-bus bridge. If no other VL-bus device claims the cycle as well, then the VL-bus/PCI-bus bridge translates the cycle onto the PCI-bus and awaits a response from a PCI device. If no PCI device claims a cycle by the PCI-bus device claiming deadline, then the VL-bus/PCI-bus bridge asserts BOFF# to the host and suppresses its assertion of LDEV# when the host repeats the cycle on the VL-bus. The VL-bus/system-bus bridge therefore can translate the repetition of the cycle onto the system bus. When asserting BOFF# to the host, the VL-bus/PCI-bus bridge also asserts the VL-bus device ready signal LRDY# after assertion of BOFF# and releases LRDY# before releasing BOFF#. The VL-bus controller does not receive BOFF# necessarily, but responds to LRDY# by asserting RDYRTN# onto the VL-bus, thereby signifying to all other VL-bus devices that the VL-bus cycle has ended and permitting them to restart their state machines in anticipation of a new VL-bus cycle. The host ignores RDYRTN# while, and only while, BOFF# is asserted.

1. Field of the Invention
The invention relates to IBM PC AT-compatible computer architectures, and more particularly, to enhancements thereof for communicating with I/O peripheral devices.
2. Description of Related Art
The IBM PC/AT.RTM. computer architecture has become an industry standard architecture for personal computers and is typically built around a host CPU such as an 80386, 80486 or Pentium.RTM. microprocessor manufactured by Intel Corporation, or similar microprocessors manufactured by others. The host CPU is coupled to a host bus, capable of performing memory accesses and data transfers at high rates of speed (i.e., on the order of 25-100 MHz with today's technology). The host bus includes 32 or, in the case of computers built around the Pentium, 64 data lines, a plurality of address lines, and various control lines. The typical IBM PC AT-compatible platform also includes DRAM main memory, and in many cases a timer, a real-time clock, and a cache memory.
The typical IBM PC AT-compatible computer also includes an I/O bus, also know as a system bus or AT-bus, which is separate and distinct from the host bus. The system bus usually conforms to one of two industry-established standards known as ISA (Industry Standard Architecture) and EISA (Extended ISA). The system bus is coupled to the host bus via a host-bus/system-bus bridge, and includes, depending on the system bus standard adhered to, 16 or 32 data lines, a plurality of address lines, as well as control lines. The I/O address space is logically distinct from the memory address space and if the CPU desires to access an I/O address, it does so by executing a special I/O instruction. Such an I/O instruction generates memory access signals on the host bus, but also activates an M/IO# signal on the host bus to indicate that this is an access to the I/O address space. The host-bus/system-bus bridge recognizes the I/O signals thereby generated by the CPU, performs the desired operation over the system bus, and if appropriate, returns results to the CPU over the host bus.
In practice, some I/O addresses may reside physically on the host bus and some memory addresses may reside physically on the system bus. More specifically, the devices which respond to accesses to certain I/O space addresses may be connected to the control lines (and usually the address and data lines as well) of the host bus, while the devices which respond to accesses to certain memory space addresses may be connected to the control lines (and usually the address and data lines as well) of the system bus. The host-bus/system-bus bridge is responsible for recognizing that a memory or I/O address access must be emulated by an access to the other bus, and is responsible for doing such emulation. For example, a ROM (or EPROM) BIOS may reside physically on the system bus, but actually form part of the local memory address space. During system boot, when the CPU sends out a non-I/O address which is physically within the ROM BIOS, the host-bus/system-bus bridge recognizes such, enables a buffer (considered herein as being part of the host-bus/system-bus bridge) which couples the address onto the system bus, and activates the chip select for the ROM. The bridge then assembles a data word of the size expected by the host CPU, from the data returned by the ROM, and couples the word onto the host bus for receipt by the CPU. In many systems, at some point during the ROM-based boot-up procedure, the ROM BIOS is copied into equivalent locations in the DRAM main memory, which does reside on the host bus, and thereafter accessed directly.
In the standard architecture, the logical main memory address space is divided into a low memory range (0h-9FFFFh), a reserved memory range (A0000h-FFFFFh) and an extended memory range (10000h to the top of memory). In a typical system the system ROM BIOS is located logically at memory space addresses F0000h FFFFFh, and resides physically on the system bus. Addresses C0000h-EFFFFh contain ROM BIOS portions for specific add-on cards and reside physically on their respective cards on the system bus. Addresses A0000h-BFFFFh contain the video buffer, which is a part of a video controller residing on the system bus. Duplicate memory space is typically provided in DRAM on the host bus for addresses C0000h-FFFFFh, and the user of the system can select during a setup procedure, which portions of the ROM BIOS are to be "shadowed" by being copied into the duplicate DRAM space during boot-up.
In addition to the above elements, a keyboard controller typically also resides on the system bus, as does the timer and real-time clock. A typical IBM PC AT-compatible system may also include a DMA controller which permits peripheral devices on the system bus to read or write directly to or from main memory, as well as an interrupt controller for transmitting interrupts from various add-on cards to the CPU. The add-on cards are cards which may be plugged into slot connectors coupled to the system bus to increase the capabilities of the system. Add-on cards are also sometimes referred to as expansion cards or accessory cards.
General information on the various forms of IBM PC AT-compatible computers can be found in IBM, "Technical Reference, Personal Computer AT" (1985), in Sanchez, "IBM Microcomputers: A Programmer's Handbook" (McGraw-Hill: 1990), in MicroDesign Resources, "PC Chip Sets" (1992), and in Solari, "AT Bus Design" (San Diego: Annabooks, 1990). See also the various data books and data sheets published by Intel Corporation concerning the structure and use of the iAPX-86 family of microprocessors, including Intel Corp., "Pentium.TM. Processor", Preliminary Data Sheet (1993); Intel Corp., "Pentium.TM. Processor User's Manual" (1994); "i486 Microprocessor Hardware Reference Manual", published by Intel Corporation, copyright date 1990, "386 SX Microprocessor", data sheet, published by Intel Corporation (1990), and "386 DX Microprocessor", data sheet, published by Intel Corporation (1990). All the above references are incorporated herein by reference.
The various signals on the host bus include the input/output signals of whichever microprocessor the system is built around. Such signals are therefore well known in the industry and can be determined by reference to the above-incorporated publications. The various signals on the system bus also are well known in the industry. The Solari book incorporated above describes the lines in detail. For present purposes, only the following signals are important:
TABLE I ______________________________________ ISA BUS SIGNALS ISA BUS SIGNAL NAME ISA BUS SIGNAL DESCRIPTION ______________________________________ SA(19:0) 20 address lines. Sufficient to address 1MB of memory. Only SA(15:0) are used to address the 64k I/O address space, and only SA(9:0) are used to address the basic 1k AT I/O address space. LA(23:17) Additional address lines for addressing a 1GMB memory address space on the system bus. The LA lines are valid earlier in an I/O bus cycle, but must be latched if needed later in the cycle. The SA lines are not valid as early as the LA lines, but remain valid longer. BALE Bus address latch enable line. In a CPU initiated system bus cycle, this line indicates when the SA address, AEN and SBHE# lines are valid. In other system bus cycles, the platform circuitry drives BALE high for the entire cycle. SBHE# System byte high enable. When SBHE# is active and SA(0) is low, then a 16- bit access will be performed. AEN When active, informs I/O resources on system bus to ignore the address and I/O command signals. Used primarily in DMA cycles where only the I/O resource which has requested and received a DMA acknowiedgment signal (DACK#) knows to ignore AEN and respond to the system bus signal lines. Some systems include slot- specific AEN.sub.x signal lines. SAID(15:0) 16 data lines. MEMR#, Read request lines to a memory SMEMR# resource on the system bus. 5MEMR# is the same as MEMR# except that SMEMR# becomes active only when the read address is below 1MB (i.e., LA(23:20) = 0). Aiso called MRDC# and SMRDC#; respectively. MEMW# Write request lines to a memory SMEMW# resource on the system bus. SMEMW# becomes active only when the write address is below 1MB. Also called MWTC# and SMWTC#, respectively. IOR# Read request line to an I/O resource on the system bus. Also called IORC#. IOW# Write request line to an I/O resource on the system bus. Also called IOWC#. MEMCS16# Memory chip select 16. Asserted by an addressed memory resource on the system bus if the resource can support a #6-bit memory access cycle. IOCS16# I/O chip select 16. Asserted by an addressed I/O resource on the system bus if the resource can support a 16- bit I/O access cycie. SRDY# Synchronous Ready line. Also sometimes called OWS#, NOWS# or ENDXFR#. Activated by an addressed I/O resource to indicate that it can support a shorter-than-normal access cycle. IOCHRDY I/O channel ready line. If this signal is deactivated by an addressed I/O resource, the cycle will not end until it is reactivated. A deactivated IOCHRDY supersedes an activated SRDY#. Also sometimes called CHRDY. MASTER# After requesting and receiving a DMA- acknowledged (DACK#) signal, a system bus add-on card can assert MASTER# to become the system bus master. REFRESH# Activated by refresh controller to indicate a refresh cycle. IRQ(15, 14, Interrupt request lines to the 12:9, 7:3) interrupt controller for CPU. DRQ(7:5, DMA Request lines from I/O resource on 3:0) system bus to platform DMA controller. DACK(7:5, DMA Acknowledge lines. 3:0) TC DMA terminal count signal. Indicates that all data has been transferred. Also called T/C. BCLK System bus clock signal. 6-8.33MHz square wave. OSC 14.318MHz square wave. ______________________________________
Note that some of the signals described in this specification are asserted high, whereas others are asserted low. As used herein, signals which are asserted low are given a `#` or `B` suffix in their names, whereas those asserted high (or for which an assertion polarity has no meaning) lack a `#` or `B` suffix. Also, two signal names mentioned herein that are identical except that one includes the `#` or `B` suffix while the other omits it, are intended to represent logical compliments of the same signal. It will be understood that one can be generated by inverting the other, or both can be generated by separate logic in response to common predecessor signals.
Recently, efforts have been made to reduce the size and improve the manufacturability of PC AT-compatible computers. Specifically, efforts have been made to minimize the number of integrated circuit chips required to build such a computer. Several manufacturers have developed "PC AT chipsets" (also known as "core logic chipsets" or "I/O bus interface circuitry"), which integrate a large amount of the host-bus/system-bus bridge circuitry and other circuitry onto only a few chips. An example of such a chipset is the 386WB PC/AT chipset manufactured by OPTi, Inc., Santa Clara, Calif. These chipsets implement the host-bus/system bus bridge, the timer, real-time clock (RTC), DMA controller, as well as some additional functionality.
In the original IBM PC AT computers manufactured by IBM Corp., the system bus operated with a data rate of 8 MHz (BCLK=8 MHz). This was an appropriate data rate at that time since it was approximately equivalent to the highest data rates which the CPUs of that era could operate with on the host bus. Numerous third party vendors have since developed peripheral devices and controller cards which are intended to be plugged into an AT (ISA) slot on the system bus, and which rely upon the 8 MHz maximum data rate. The AT standard also requires a wait state (i.e. 125 nS) for 16-bit data transfers, and four wait states (500 nS) for 8-bit data transfers. A zero wait state data transfer is also available, but only if the peripheral device signals, by activating the SRDY# control line on the system bus, that it can handle such fast data transfers.
In the years since the IBM PC AT was originally introduced, technology has improved dramatically to the point where host buses on high-end PC AT-compatible computers can operate on the order of 100 MHz. Despite these advances, however, such computers are still manufactured with a system bus operating at around 8 MHz because of the need to maintain compatibility with previously designed peripheral devices. These devices were designed in reliance upon the 8 MHz data rate and AT wait state protocol, and many such devices are not capable of operating faster. Even modern designs for AT bus peripherals often rely on the 8 MHz maximum data rate, even though very little additional effort or cost would be involved to design them to operate faster.
In addition to the large disparity between data transfer rates on the system bus as compared to the host bus in modern PC AT-compatible computers, the host-bus/system-bus bridge circuitry needs to delay its handling of requests and responses from one bus to the other merely because the clocks are not synchronized. The circuitry therefore must hold a request or response until the appropriate clock edge on the destination bus appears. This can add on the order of 30-200 nS to each system bus cycle. Accordingly, it can be seen that any access to a peripheral device on the system bus imposes a substantial penalty on the performance of PC AT-compatible computers. This penalty will only become worse as the disparity between the host bus and system bus data rates continues to increase.
The penalty applies for most types of peripheral devices, but in the past it has been most noticeable for video display controllers. Video display controllers have a command port which responds to accesses in the I/O address space, as well as a video memory port which responds to accesses in the memory address space. Manufacturers have traditionally placed both ports on the system bus, however, thereby imposing the speed limitations of the system bus on the video memory port as well as the command port. U.S. patent application Ser. No. 07/851,444, filed Mar. 16, 1992 (Attorney Docket No. OPTI3030WSW), owned by the assignee of the present application and incorporated herein by reference in its entirety, describes certain attempts to permit accesses to the video memory port to take place over the host bus instead of the system bus. In addition, some graphics chip vendors have tried incorporating features into their chips for connection directly to a host bus.
For example, see S3, Inc., "86C911 GUI Accelerator", Databook (April 1992), incorporated herein by reference.
However, these solutions all suffer from the problem that they are non-standard. That is, if a vendor of I/O interface chipsets provides for a host bus capability, there is no assurance that it will interface directly with products made by more than one peripheral device controller vendor. A layer of buffers and glue logic therefore may be required to enable such peripheral device controllers to take advantage of the host bus feature, and the glue logic may be different for each different peripheral controller. On the other hand, if a maker of peripheral device controllers, such as a maker of a VGA (Video Graphics Adapter) controller, provides for a host bus capability in the peripheral controller, there is no guarantee that it will interface correctly with the host-bus/system-bus bridge chipsets made by more than one chipset manufacturer. Again, different buffers and glue logic may be required for each vendor of chipsets.
In two different efforts for ameliorating the above problem, instead of creating a private standard, two different organizations have defined different bus protocols and attempted to promulgate them as standards for the entire personal computer industry. One such standard, referred to herein as the VESA (Video Electronics Standards Association) or VL-Bus standard, is defined in VESA, "VESA VL-Bus Local Bus Standard", Revision 1.0 (1992), incorporated herein by reference. Significant aspects of the VL-Bus specifications are described in Appendix A hereto. Further revisions of the VESA standard are in preparation, one recent version being VESA, "VESA VL-Bus Proposal, Version 2.0p, Revision 0.8p (May 17, 1993), also incorporated herein by reference. The other such standard, referred to herein as the PCI standard, is defined in Intel Corp., "Peripheral Component Interconnect (PCI), revision 1.0 Specification" (Jun. 22, 1992) and in PCI Special Interest Group, "PCI Local Bus Specification", Revision 2.0 (Apr. 30, 1993), both incorporated herein by reference. Significant aspects of the PCI 2.0 Bus specifications are described in Appendix B hereto. Each standard has advantages and disadvantages over the other, and depending on the application, one standard or the other may be more beneficial to have in a system.
For example, one advantage of the VL-bus is that it is relatively simple to include in a personal computer system, especially those built around an Intel 486 microprocessor. This is because the VL-bus signal lines are similar to signal lines of the 486 CPU, except for a few additional signal lines included on the VL-bus. Thus the only additional expense required to add a VL-bus to a pre-existing 486-based computer design, is a very small VL-bus controller to handle the additional signal lines. Such a controller has already been included in chipsets. An example of such a chipset includes the OPTi 82C802G and either the 82C601 or 82C602, all incorporated herein by reference. The 82C802G is described in OPTi, Inc., "OPTi PC/AT Single Chip 82C802G Data Book", Version 1.2a (Dec. 1, 1993), and significant aspects are also set forth in Appendix C hereto. The 82C601 and 82C602 are described in OPTi, Inc., "PC/AT Data Buffer Chips, Preliminary, 82C601/82C602 Data Book", Version 1.0e (Oct. 13, 1993), and significant aspects are also set forth in Appendix D hereto. Both data books are incorporated herein by reference in their entirety.
While a minimum VL-bus system requires no additional circuitry, the insertion of a simple host-bus/VL-bus bridge provides buffering for additional VL-bus devices. For Pentium.RTM.-based systems, the host bus of which has a 64-bit wide data path, the bridge could also include circuitry to break up a 64-bit host-bus originated access, into two 32-bit VL-bus accesses. Such circuitry is still relatively simple. (Extension to the 32-bit VL-bus standard have been proposed in order to accommodate 64-bit access in a single VL-bus cycle, but in general, as the data path of host CPUs continues to expand, it can be expected that at least some future system designs will continue to employ a bridge which breaks up a wider-data-path host bus access into two, four, or some other number of narrower-data-path cycles on the VL-bus.)
A primary advantage of the PCI-bus, on the other hand, is its processor independence. The PCI-bus was intended to provide very high-speed accesses using a standard bus protocol, and to interface those accesses with any host processor bus using an appropriate host-bus/PCI-bus bridge. The host-bus/PCI-bus bridge is significantly more expensive than the circuitry required to implement a VL-bus, but the independence it provides from ever-faster and ever-more varied host processor buses provides a stable target for designers of peripheral products. A peripheral device designed for the PCI-bus would not need to be redesigned for each new version of an Intel microprocessor, or indeed, for each new microprocessor that might in the future power a personal computer system.
To date, neither the VL-bus standard nor the PCI-bus standard has achieved dominance in the marketplace for personal computer systems or in the marketplace for peripheral devices. Thus peripheral device manufacturers designing cards intended to bypass the slow system bus, still usually must design one version of the card for the PCI-bus and one version for the VL-bus. Similarly, computer system integrators and chipset manufacturers often find themselves having to double their product offerings since each market segment for VL-bus systems can have an equivalent but separate market segment for PCI-bus systems.
It is possible to overcome these problems by designing a computer system which incorporates both VL-bus expansion slots and PCI-bus expansion slots, in addition to the standard ISA- or EISA-bus expansion slots. The motherboard circuitry to implement this would be expected to include programmable registers which would indicate whether a particular valid cycle definition on the host bus is to be handled by a device on the host bus (such as main memory), a device on the VL-bus (which may be the same as the host bus in 486 systems), by a device on the PCI-bus, or by a device on the system bus. Such motherboard circuitry would be expensive, however, and may require an entirely new chipset design.
In Acer Laboratories, Inc., "M1435 PCI-VL.sub.-- Bus Bridge, Preliminary Datasheet" (Sep. 20, 1993), incorporated by reference herein, there is described a VL-bus/PCI-bus bridge chip which, together with the Acer M1429kG/M1429 VESA chip, permits both a VL-bus and a PCI-bus to be included in a single system. According to the datasheet, when the M1435 chip detects a valid VL-bus cycle, it first determines whether the cycle is intended for system memory or for another VL-bus device. The chip is believed to perform a positive decode of the address to determine whether the cycle is intended for system memory, and it observes the LDEV signal to determine whether the cycle has been claimed by another VL-bus device. If neither is the case, then the M1435 translates the cycle to the PCI-bus. If no PCI agent claims the translated PCI cycle, then the M1435 asserts an ISA REQJ signal to the M1429 chip, thereby informing the M1429 to start an ISA cycle. See also Acer Laboratories, Inc., "M1429G/M1431/M1435 Data Sheet" (October 1993), incorporated herein by reference.
The Acer technique for accommodating both the VL-bus and PCI-bus in a single system is limited in that it operates only with a host-bus/system-bus interface chipset which observes and understands the ISA REQJ signal asserted by the M1435 bridge. Other inter-chip signals may also be required between the M1435 and M1429. Since most interface chipsets do not understand these signals, such chipsets would have to be modified by the chipset manufacturer before they could be used with the M1435 bridge. It would be desirable, therefore, to provide a VL-bus/PCI-bus bridge which does not require modification of any existing VL-bus/system-bus chipset. Such a bridge could be used in conjunction with the chipset of any manufacturer which supports the VL-bus.

Using a back-off signal to bridge a first bus to a second bus


A service deployment method and a network functions acceleration platform are provided. The method includes: when an FPGA is powered on, loading, by the FPGA, an FPGA framework file, so that the FPGA includes M partial reconfigurable PR areas, a configuration module, and a data flow forwarding module; when receiving a service configuration instruction, generating, by a physical machine, a VM, and selecting at least one PR area from the M PR areas to establish a correspondence with the VM; performing, by a configuration module, service resource configuration on the selected PR area according to a PR configuration resource, so that the selected PR area has a service processing capability; adding, by the configuration module, a forwarding entry corresponding to the PR area in a forwarding flow table, so that the data flow forwarding module forwards a received network packet to the corresponding PR area.

Network functions virtualization (NFV) is proposed by an operator alliance, a virtual device may be quickly added and controlled on a network hardware platform based on requirements by using a standard information technology (IT) virtualization technology, and then a virtual network function (VNF) service is deployed by using the virtual device.
Currently, in a multi-core ×86 system, a general-purpose multi-core ×86 system is coupled with a field-programmable gate array (FPGA) module in a peripheral chip by using a bus supporting a single-root input/output virtualization specification (SR-IOV) and an interface standard (peripheral component interconnect express (PCIE)) bus, a virtual machine (VM) is generated in a CPU of the ×86 system by using a hypervisor, and a VNF function is implemented by using the VM.
Generally, service processing is performed by the VM. When the VM performs the service processing, a physical machine CPU needs to be accessed frequently. Therefore, overhead of CPU software is relatively large, and overall communication performance is not high.

Service deployment method and network functions acceleration platform


Disclosed is a process for forming an azomethine compound, comprising:

This invention relates to a process for forming an azomethine compound, comprising reacting a compound having an active methylene group or methine group with an arylprimaryamine compound in the presence of a base and an oxidizing agent and in a solvent medium containing a ketone compound having C1-C4 alkyl groups at a temperature low enough to provide a yield of the azomethine product of at least 50 mole %.
Chemical production ideally requires a process which offers high yield with minimal impact on the environment. These factors, along with careful choice of reagents, can lead to a low cost production process. The most widely used method for producing azomethine compounds consists of the oxidative condensation of an activated methylene or methine group containing compound xe2x80x9cAxe2x80x9d with an arylprimaryamine compound xe2x80x9cBxe2x80x9d in the presence of a base. Both one-phase and two-phase systems have been used.
One-phase systems typically require an organic solvent which adequately solubilizes the organic reactants. Examples which have been used are ethyl acetate, methylene chloride, and methanol. U.S. Pat. No. 5,122,611 describes a method for producing an azomethine dye which comprises oxidatively condensing an active methylene- or methine-containing compound, except those containing a sulfonic or carboxylic acid group, and p-phenylenediamine, except those containing a sulfonic or carboxylic acid group, in the presence of methylene chloride as a solvent under a basic condition. However, the organic reactants can require a large volume of such solvents to be adequately soluble. Lower molecular weight ketones such as acetone, would be thought to be a good choice for a solvent, as it typically has good solubility of the organic reactants and is also environmentally benign. However, these ketones appear to adversely affect the yields, presumably as a result of an unwanted side reaction. Therefore, ketones tend to be regarded as a problem as opposed to a potential solvent for such a reaction.
Two-phase systems (i.e. an organic and an aqueous phase) require that the organic solvent is not water miscible, which therefore limits the solvent choice to those such as methylene chloride (dichloromethane), ethyl acetate, toluene, heptane, propyl acetate, etc. However, to ensure adequate conversion to product, only more polar solvents such as methylene chloride or ethyl acetate can be used. The solvent of choice would be dichloromethane, but this solvent has strong environmental reasons for avoiding its use. Simple N-alkyl acetates would potentially be a good choice as solvent, but do not typically give such good separation of the organic phase from the aqueous phase, resulting in production problems. Also, in two-phase systems, the water phase adds considerable volume to the reaction, reducing productivity and requiring additional process steps for its removal.
It is a problem to be solved to provide a process for preparing an azomethine compound in good yield without significant environmental complications.
The invention provides a process for forming an azomethine compound, comprising:
(a) reacting a compound xe2x80x9cAxe2x80x9d having an active methylene group or methine group with an arylprimaryamine compound xe2x80x9cBxe2x80x9d;
(b) in the presence of a base and an oxidizing agent and in a solvent medium containing a ketone compound having the formula R1C(O)R2 wherein R1 and R2 are independently C1-C4 alkyl groups;
(c) at a temperature low enough to provide a yield of the azomethine product of at least 50 mole % based on compound A.
The process provides good yield without creating environmental concerns associated with other solvent materials such as methanol and methylene chloride.
The invention is generally described above. Compound A contains an active methylene (xe2x80x94CH2xe2x80x94) group or methine (xe2x80x94CH less than ) group. Such compounds include, for example, those with an acylacetamide group such as a xcex2-keto carboxamide group. Specific examples are an acyl acetanilide such as a benzoylacetanilide or a pivaloylacetanilide. These compounds are useful yellow dye-forming couplers in the photographic arena. The methine group may be substituted with an non carbon group such as a halogen, nitrogen, oxygen or sulfur linked group. Compound B is an arylprimaryamine. Typical of such compounds are 1xc2x0 amine developing agents such as a phenylene diamine especially a paraphenylenediamine. As indicated hereinafter, these compounds may be substituted.
The reaction requires the co-presence of a base and an oxidizing agent and in a solvent medium containing a carbonyl compound having the formula R1C(O)R2 wherein R1 and R2 are independently C1-C4 alkyl groups. The base may be any basic material that provides a pH value in the desired range, typically 7 to 13.5. Most useful are the inorganic bases such as the carbonates, bicarbonates, and phosphates. Potassium carbonate is conveniently employed. Any oxidizing agent is suitably employed such as a persulfate. Ammonium persulfate is useful for this purpose. Although the amount of oxidizing agent may vary with the acylacetamide selected, suitable amounts are 0.9 to 4.0 equivalents to Compound A with 0.9-2.1 and 1.9-2.1 being typical. The ketone component is one with relatively short alkyl substituents, ranging up to 4 carbon atoms. Butanone and acetone are readily used with acetone (dimethylketone) being the most useful.
The reaction is carried out at a controlled temperature so that the yield is at least 50 mole % based on compound A. It has been found that temperatures above 25xc2x0 C. cannot be expected to satisfy this requirement. In a preferred mode the temperature is less than 20xc2x0 C. and more desirable form 4-12xc2x0 C. With homologous ketones, slight variations in these temperature ranges can be expected.
The relative equivalents of Compound A to Compound B suitably range form 0.9 to 1.5 and more typically 0.9 to 1.1. The amount of base depends on the specific base and the specific type of acylacetamide employed and typically ranges from 2 (for a dibasic compound) to 30 per mole of compound A, with 4-6 typically employed. The reaction time is dependent on the rate of addition of oxidizing agent and is typically 0.5 to 12 hours with 1-8 and more usually, 2-6 hours being employed.
Typical examples of dyes that are conveniently made using the process of the invention have the following general formula I.
wherein
A is chloro, C1-C4 alkoxy such as methoxy or isopropoxy, methyl or trifluoromethyl;
B is H;
C is H or chloro;
D is H, chloro, carboxyl, sulfonamido, carbonamido, alkoxy, sulfamoyl or sulfonyl;
R is a substituent such as an alkyl group, especially tertiary or methylcyclopropyl, or an aryl group such as a phenyl group; and
Ar is suitably a group having the formula:
where X is H, or a methyl, methoxy or carbonamido group; and each Y and Z are H or an independently selected substituent group; provided that Y and Z may join to form a ring. Ar may also be


A boat lift system for raising and lowering a boat from and into a body of water includes a cradle, a cable and a drive system. The cradle is configured to hold the boat. The cable is connected to the cradle. The drive system includes a reel, a drive mechanism and a cable slack control mechanism. The reel is configured to receive the cable. The reel is rotatable in each of a winding direction to wind the cable onto the reel to raise the cradle and an unwinding direction to unwind the cable from the reel to lower the cradle. The drive mechanism includes a drive member and a motor operable to forcibly rotate the drive member in each of a raising direction and a lowering direction. The drive member is operatively connected to the reel to rotate the reel in the winding direction when the drive member is rotated in the raising direction, and to controllably rotate the reel and/or permit the reel to rotate in the unwinding direction when the drive member is rotated in the lowering direction. The cable slack control mechanism is operative to selectively decouple the drive member from the reel while the drive motor is rotating the drive member in the lowering direction.

It is often desirable or necessary to remove a boat stored at a dock from the water. For example, during a storm, the boat may be damaged as a result of being banged against the dock by wind, waves or surges. Boats that are stored in the water may experience increased maintenance costs due to the need for more frequent painting, floating objects striking the hull and/or growth of crustaceans on the hull that must be removed.
In view of the foregoing, many boat owners need or desire to store their boats out of the water. In response to this demand, boat yards are available that will store a boat on land in a cradle or in a warehouse and, upon demand, will retrieve and place the boat in the water using a crane, forklift or the like. However, this alternative may be expensive and/or inconvenient.

Drive units, drive systems and boat lift systems including the same


An object of the present invention is to provide a method for producing (meth)acrylic-modified polybutadiene free from coloration and white turbidity without using a tin compound. The method for producing (meth)acrylic-modified polybutadiene of the present invention comprises reacting polybutadiene having a hydroxyl group at a terminal and a (meth)acrylic ester in the presence of an organoaluminum compound. As the organoaluminum compound, for example, a compound represented by formula (I) (wherein each of R1, R2, R3, and R4 independently represents a linear or branched C1 to C30 alkyl group) is preferred.

Polybutadiene can be cured by heat, an ultraviolet ray, an electronic beam, or the like. Cured products of polybutadiene are resin materials excellent in water resistance, moisture resistance, chemical resistance, electric characteristics (high insulation resistance, a low dielectric constant, and an arc resisting property), and transparency and showing physical properties having high tenacity. Further, modified polybutadiene heightened in a curing property by heat, an ultraviolet ray, or an electronic beam by introducing a polymerizable functional group such as an acryloyl group or a methacryloyl group into the polybutadiene terminal is proposed (Patent Documents 1 and 2).
In Patent Document 1, terminal (meth)acrylic-modified polybutadiene is produced by the reaction of 1,2-polybutadienediol and a (meth)acrylic ester in the presence of an acid catalyst such as p-toluenesulfonic acid.
In Patent Document 2, (meth)acrylic-modified polybutadiene is produced by the reaction of hydroxyl group-containing polybutadiene and (meth)acrylic ester in the presence of a tetraalkoxytitanium catalyst, a dialkyltin dicarboxylate catalyst, or a dialkyltin oxide catalyst.

Method for producing (meth)acrylic-modified polybutadiene


A photosensitive resin composition comprising (A) an alkaline aqueous solution-soluble novolak resin, (B) a photosensitizer obtained by reacting a polyhydroxy compound with 1,2-naphthoquinone-(2)-diazido-5(or 4)-sulfonyl chloride, and (C) an ultraviolet absorber such as 2-(2'-hydroxy-5'-methylphenyl)-benzotriazole, has a strong absorption against a light of a wavelength of 365 nm and is suitable for producing semiconductor elements, etc.

This invention relates to a positive-type photosensitive resin composition having strong UV light absorption and a process for forming a pattern using the same.
As fine processing technique for semiconductor elements, there is widely employed pattern formation using a positive-type photosensitive resin composition and a g-line (light of 436 nm) projection aligner. In order to improve the resolving power of a photosensitive resin, there are employed an improvement of the photosensitive resin and an improvement of a light exposing device. The light exposing device can be improved by increasing the numerical aperture of lens or making the exposing wavelength shorter. The resolving power is proportional to the exposing wavelength and can be improved by about 16% by changing the g-line to i-line (light of 365 nm). A light exposing device using a shorter wavelength of near 250 nm is now under development, but it requires a much more time to accomplish such a device.
Thus, a light exposing device using i-line is noticed. As a photosensitive resin used in such a device, there is used a composition comprising a novolak resin and 1,2-naphthoquinone-(2)-diazido-sulfonic acid ester as a photosensitizer (e.g. Japanese Patent Examined Publication Nos. 37-18015 and 54-20330, and Japanese Patent Unexamined Publication Nos. 62-28457 and 62-89040). Such a photosensitive resin composition can be used on a silicon oxide film and silicon nitride film, but it causes a problem of narrowing of patterns due to reflected light when used on a substrate having a high light reflectance such as an aluminum film.

Photosensitive quinone diazide and resin composition having high absorbency for a wavelength of 365 nm containing a benzotriazole ultraviolet absorbing compound


A system and method for coordinating multi-media messages across multiple systems. A networked messaging system 10 having a plurality of mailboxes 50 according to the present invention comprises a first mailbox configured to receive a first plurality of messages and a second mailbox operably coupled to the first mailbox and configured to receive a second plurality of messages. A control system 37 is coupled to control the first mailbox and the second mailbox. The control system 37 is configured to generate first tokens corresponding to the first plurality of messages. The control system 37 is further configured to transfer the tokens from the first mailbox to the second mailbox and is configured to use the first tokens to access the first plurality of messages from the first mailbox responsive to the second mailbox itself being accessed.

1. Field of the Invention
The present invention relates to messaging systems and, more particularly, to a system and method for coordinating messages across multiple systems.
2. Description of the Related Art
Many people today employ a variety of messaging systems of multiple types. For example, a user may have a plurality of e-mail accounts, and a plurality of voice mail accounts.
In the case of voice messaging systems, the user may have a work voice telephone number, a cellular telephone voice number and a home telephone voice number. The user may further have more than one work voice telephone number at more than one local and/or remote sites. Typically, each voice number is associated with a voice mailbox. A sender may leave a message at any of the user's mailboxes. The proliferation of various mailboxes at various sites permits the user to be reached at a variety of locations using local telephone calls. However, in order for the user to retrieve his messages, the user must access each of his mailboxes associated with each site. This can be both time-consuming and expensive, particularly since the user typically has no way of knowing whether a message is, in fact, waiting at any of the remote mailboxes.
Similarly, a user may have a plurality of different e-mail accounts. For example, the user may have e-mail at work at one site and e-mail at home. The user may also have an e-mail account at a remote site, for example, one associated with a remote office. Again, the user must access each account individually in order to retrieve all his messages and typically has no way of knowing when a message is pending at a remote location.
Accordingly, it is desirable to provide a system and method whereby a user may access several of a plurality of messaging systems without having to manually access each and every one of his mailbox systems.

System and method for coordination of multimedia messages across multiple systems

Siemens Information and Communication Networks, Inc.


Filled dough producing method is disclosed for making a food product, such as baozi, a traditional Chinese food, by folding and constricting close a circular dough wrapper around a filling in an apparatus including a pocket assembly made of pliable fabric layer with an upper surface and lower surface, a flexible frustro-conical member connected to the lower surface of the pliable fabric layer, and draw strings for making a pouch, wherein the frustro-conical member is configured to be alternately inverted from a first rigid position to a second rigid position.

Baozi is a traditional Chinese food made by folding a flat and circular yeast leavened dough sheet, a dough wrapper, around its filling, and is often steam cooked. The resulting baozi is ball shaped, has many folds at its upper body around the dough wrapper closure, and is smooth at the lower body.
Making a baozi traditionally by hand has been very much like making a handcraft that is time-consuming and requires a relatively high degree of both skill and labor. What is needed in the art is baozi producing method suitable for the everyday consumers.


According to one embodiment, a resistance change memory includes a memory cell array, an address counter, a word line driver, a power supply circuit, and a write driver. Memory cells include resistive storage elements and cell transistors. The power supply circuit generates a stress voltage different from a power supply voltage used to write data into the memory cells in a normal operation. The write driver applies the stress voltage across first bit and source lines to pass a stress current through the memory cell selected by a first word line. The write driver applies the stress voltage across second bit and source lines to pass the stress current through the memory cell selected by a second word line.

Resistance change memories such as a magnetic random access memory (hereinafter referred to as an MRAM) that uses magnetoresistive effects of a ferromagnetic substance have been recently drawing more attention as next-generation solid-state nonvolatile memories capable of high-speed reading and writing, having high capacities, and capable of low-power-consumption operation. In particular, a magnetoresistive element having a magnetic tunnel junction used in the MRAM is also referred to as a magnetic tunnel junction (MTJ) element, and has been dawning attention since it had been proved to show a high magnetoresistance rate. The MTJ element has a three-layer stacked layer structure including a storage layer variable in magnetization direction, an insulator layer, and a reference layer which faces the storage layer and which maintains a predetermined magnetization direction.

Resistance change memory and test method of the same


Methods and apparatus for thermal management of a precursor for use in substrate processing are provided herein. In some embodiments, an apparatus for thermal management of a precursor for use in substrate processing may include a body having an opening sized to receive a storage container having a liquid or solid precursor disposed therein, the body fabricated from thermally conductive material; one or more thermoelectric devices coupled to the body proximate the opening; a heat sink coupled to the one or more thermoelectric devices; and a fan disposed proximate to a back side of the heat sink to provide a flow of air to the heat sink.

Solid and liquid precursors are being used to provide gases in many semiconductor fabrication processes, for example, such as deposition of materials on a substrate. However, the inventors have observed numerous issues with conventional methods typically utilized to control a temperature of the solid or liquid precursor (e.g., a water bath, water jacket, heater jacket, or fire rods). For example, the conventional methods require significant space and support equipment to be implemented. In addition, some precursors are very unstable or water reactive, raising safety concerns regarding the conventionally utilized equipment.
Thus, the inventors have provided improved thermal management systems for processing solid or liquid precursors.

Compact ampoule thermal management system


A method and apparatus that compensates for a velocity of a motor of fuel cell vehicle when a resolver is determined to have failed is provided. In particular, a wheel velocity sensor is configured to detect a wheel velocity of a driving wheel, and an ABS controller is configured to calculate an average wheel velocity and transmit the calculated average to a fuel cell controller (FCU). The FCU is configured to receive information related to the wheel velocity upon detecting that the resolver has failed, and control driving of the motor based on the data related to the wheel velocity so that the motor may maintain operation.

(a) Field of the Invention
The present invention relates to a fuel cell vehicle, and more particularly, to an apparatus for compensating for a velocity of a motor of a fuel cell vehicle, which accurately compensates for velocity of a motor even though a failure has been generated in a resolver that typically, detects the velocity of the motor.
(b) Description of the Related Art
According to a continuous demand for improvement vehicle fuel efficiency and stricter regulations regarding the discharge exhaust each country, the demand for an environmentally-friendly vehicle has been increased, and hybrid vehicles and fuel cell vehicles have been become a realistic alternative for the demand.
Fuel cell vehicles are different from hybrid vehicles and electric vehicles in that they an alternative power source as a means to drive an electric motor. This alternative power source is a fuel cell or more particularly a fuel cell stack.
In particular, the fuel cell stack provides an electric current to an electric motor via a generation of electricity within the fuel cell stack from a chemical reaction between a fuel (typically hydrogen) and an oxidant (typically oxygen).
Depending upon the type of fuel cell that is being used the fuel supplied may be for example hydrogen or natural gas. Regardless, fuel cells are made up of three basic components: an anode, an electrolyte, and a cathode. Two chemical reactions occur at the interfaces of each three different components. The net result of the two reactions is that fuel is consumed, water or carbon dioxide is created, and an electric current is created, which can be used to power electric motor of the vehicle.
As a result fuel cell vehicles have no harmful discharge so that pollution is minimized. Accordingly, fuel cell vehicles have a high probability of quickly becoming the leader in the vehicle industry.
However, at this point the fuel cell vehicles includes a large number of components and have a complex system compared to a general internal combustion engine vehicles. Accordingly, a control algorithm for an abnormal operation of each component is typically necessary. For example, however, currently there is no algorithm that effectively and accurately compensates for velocity of a motor even though a failure has been generated in a resolver that typically detects the velocity of the motor
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

Apparatus and method of compensating for motor velocity of fuel cell vehicle


Fuels that are used nowadays can have a different densities or different heating values. Even when filling the fuel tank (7) the quality of the fuel in the fuel tank (7) can change since different fuels are mixed. For example a low density or a low heating value can lead to reduced performance of the internal combustion engine (1). It is therefore proposed that a fuel-specific factor k be determined using a sensor (2, 2a), with which the characteristic of the combustion chamber pressure and/or a lambda value is measured, and using an algorithm. In a further embodiment the operating parameters (injected quantity, start of injection, end of injection, injection pattern, exhaust gas recirculation rate, etc.) are corrected using the factor k.

It is already known that fuels for internal combustion engines, in particular diesel fuels, may have very different densities or heating values. Diesel fuels are usually mixed with additives which may in particular influence the ignition performance, anti-friction and lubricating qualities and the exhaust emissions. A measure of the quality of the ignition performance of diesel fuels is for example the cetane number CZ which is determined on a specially constructed single-cylinder test engine. Comparative fuels, which are compared with the very ignitable n-cetane C16H34 and the less ignitable α-methyl naphthalene, can be tested on this test engine. The cetane number is fixed in a range between 0 and 100. A cetane number that is too low pollutes the environment, particularly by forming carbon particulate matter in the case of diesel engines. The cetane number CZ is conventionally between 50 and 55 in Germany.
The cetane number of diesel fuels can differ greatly, it is relatively low in the case of bio-diesel in particular. A further problem lies in the fact that when refuelling, the fuels in the fuel tank are mixed with different qualities. As a result it is very difficult for the motor control unit, for example in the case of a common rail injection system, to control a quantity of fuel to be injected in such a way that optimum combustion results with minimal exhaust gas emissions in particular. Added to this is the fact that in the case of a fuel with a lower density, the energy supplied to the internal combustion engine is less than in the case of a fuel with a higher density. The engine performance is also affected to an undesirable extent as a result. A motor control unit must take all of these factors and the current operating parameters into consideration such that an optimum quantity of fuel to be injected can be calculated in the case of a corresponding torque requirement. With known motor control units these requirements are only insufficiently satisfied, however.
Previously this problem has been solved, in particular in the case of diesel fuels, by fitting an optical sensor in the fuel tank. The optical sensor has the task of inferring the quality from the fuel's opaqueness. However this method is relatively unreliable as individual fuel producers add a dye to the fuel. As a result an objective assessment of the fuel used is rendered considerably more difficult.

Method and device for assessing the quality of a fuel, in particular a diesel or petrol fuel


Methods and apparatus for continuation passing in a virtual machine (VM). A method is provided for operating a virtual machine to provide continuation passing in a wireless device. The virtual machine comprises a stack memory. The method comprises encountering a context-creating trigger, constructing a continuation block in response to the trigger that comprises a stack fragment derived from the stack memory, encountering an evaluation instruction, and storing the stack fragment from the continuation block on the stack memory in response to the evaluation instruction.

I. Field
The present invention relates generally to computing systems, and more particularly, to methods and apparatus for providing continuation passing in a virtual machine to provide efficient program flow and memory resource utilization.
II. Description of the Related Art
Advances in technology have resulted in smaller and more powerful wireless devices. For example, there currently exist a variety of portable wireless telephones, personal digital assistants (PDAs), and paging devices that are small, lightweight, and can be easily carried by users. Typically, these devices include an embedded controller with limited memory resources. For example, the amount of available memory may be limited by the small size of the device.
As wireless devices have become more widespread, there is an increasing need for these devices to handle larger amounts of data and to execute programs that are more sophisticated. For example, users are demanding remote access to interactive programs, such as gaming programs, that require wireless devices to provide fast and efficient communication with remote service providers using a wireless network. In addition, users would like to have remote access to specific programs that are typically accessible on larger home or office systems.
In order to meet these demands, device and service providers have the choice of developing their own technology or trying to make use of existing technology. Unfortunately, developing new technology is both time consuming and expensive, and therefore, an unattractive alternative. To use existing technology, such as existing software, compatibility problems must be overcome. For example, software developed for one processing system may not be compatible with another processing system. Thus, compatibility problems need to be addressed when porting software from one or more systems to run on a wireless device.
One technique used to overcome compatibility problems involves the use of a virtual machine (VM). A typical VM comprises software executing on a host system that allows the host system to run non-native program instructions written for some other system (i.e., a remote system). For example, the non-native program instructions written to execute on the remote system are interpreted by the VM software running on the host system. Thus, a VM running on a wireless device allows the device to run software written for various different systems, thereby allowing device developers and service providers to use existing software to provide added functionality to wireless device users.
Unfortunately, implementing a VM on a resource limited wireless device raises other problems. For example, most VM implementations employ a stack for temporary storage that may be used as a scratch pad to store constants, variables, arguments to called procedures, or other information needed for program execution. During bytecode execution, it is possible to encounter a dynamic function that creates an activation record or context, which may include stack pointers, current program counter (PC), code pointers, etc. A closure or block is a bytecode fragment that refers to elements on the stack in the current context (from where the block was created.) Blocks can be returned from contexts to be used elsewhere in application code. An example is a sort block passed to a sorting function. In order to execute the block at a later stage, the creating context cannot be released, i.e., the creating function cannot return. The block can only be passed to function calls made from the creating function. However, being able to return a parameterized block (i.e., a block that refers to data in the creating context) would be extremely useful.
Some systems solve this problem by creating a completely new stack for each activation record. Since the maximum stack size for each activation record can be computed at compile-time, the stack size is bounded. While this technique seems to solve the problem, it penalizes every function call with stack creation and parameter copying, which is costly on systems with low processing power and limited memory, such as a wireless device. Others techniques allow the return of the creating activation record only if the block does not refer to any actual data in the creating activation record (i.e. the block is clean). This technique solves part of the problem, but does not allow the block to be parameterized with data that was available in the creating context.
Therefore, what is needed is a VM for use in a resource-limited wireless device to provide continuation passing to allow a return of a parameterized block that refers to data in the creating context, thereby providing fast program execution while efficiently utilizing the available memory resources.

Method and apparatus for continuation-passing in a virtual machine


A unit for sterilizing a web (2) of packaging material on a machine (1) for packaging pourable food products, the unit having a bath (7) containing a sterilizing agent, in which the web (2) is fed continuously; a process chamber (8) connected to an outlet (12) of the bath (7), and which houses wringing rollers (18) interacting with the web (2), and a nozzle (22) for directing a stream of air on to the web (2) and removing residual sterilizing agent from the web; an aseptic chamber (25) communicating with the process chamber (8) via an opening (27) for passage of the web (2), and in which the web (2) is folded and sealed longitudinally to form a tube (29) which is filled continuously with the product for packaging; and an air processing circuit (24) for controlling process conditions, and having a conduit (56) for feeding a first stream of sterile air into the aseptic chamber (25), a conduit (54) for feeding a second stream of sterile air to the nozzle (22) and housing a heater (69) for controlling the temperature of the air supplied to the nozzle (22), and a distributor for regulating the two streams of air.

Machines for packaging pourable food products—such as fruit juice, wine, tomato sauce, pasteurized or long-storage (UHT) milk, etc.—are known, on which packages are formed from a continuous tube of packaging material defined by a longitudinally sealed web.
The packaging material has a multilayer structure comprising a layer of paper material covered on both sides with layers of heat-seal material, e.g. polyethylene. And, in the case of aseptic packages for long-storage products, e.g. UHT milk, the packaging material comprises a layer of barrier material defined, for example, by aluminium foil, and which is superimposed on a layer of heat-seal plastic material, and is in turn covered with another layer of heat-seal plastic material eventually defining the inner face of the package and therefore contacting the food product.
To produce aseptic packages, the web of packaging material is unwound off a reel and fed through a sterilizing unit, in which it is sterilized, for example, by immersion in a bath of liquid sterilizing agent, such as a concentrated hydrogen peroxide and water solution.
More specifically, the sterilizing unit comprises a bath filled, in use, with the sterilizing agent, into which the web is fed continuously. The bath conveniently comprises two vertical parallel branches connected at the bottom to define a U-shaped path long enough to ensure the packaging material is treated for a sufficient length of time. For effective treatment in a relatively short time, and therefore to reduce the size of the sterilizing chamber, the sterilizing agent must be maintained at a high temperature, e.g. around 70° C.
The sterilizing unit also comprises a process chamber located over the bath, and in which the web of packaging material is dried; and an aseptic chamber, in which the web is folded and sealed longitudinally to form a tube, which is then filled continuously with the product for packaging.
More specifically, in the process chamber, the web is processed to remove any residual sterilizing agent, the acceptable amount of which in the packaged product is governed by strict standards (the maximum permissible amount being in the region of a few fractions of a part per million).
Such processing normally comprises mechanical removal of any drops on the material, followed by air drying.
The drops may be removed, for example, by feeding the material through a pair of wringing rollers conveniently located close to the process chamber inlet, and downstream from which the material is still covered with a film of sterilizing agent, but has no macroscopic drops.
Drying may be performed by directing jets of sterile air on to the material.
Before leaving the aseptic chamber, the web is folded into a cylinder and sealed longitudinally to form, in known manner, a continuous, longitudinally sealed, vertical tube. In other words, the tube of packaging material forms an extension of the aseptic chamber, and is filled continuously with the pourable food product and then fed to a forming and (transverse) sealing unit for forming the individual packages, and on which the tube is gripped and sealed transversely between pairs of jaws to form aseptic pillow packs.
The pillow packs are separated by cutting the seals between the packs, and are then fed to a final folding station where they are folded mechanically into the finished shape.
Packaging machines of the above type are used widely and satisfactorily in a wide range of food industries for producing aseptic packages from web-fed packaging material. Performance of the sterilizing unit, in particular, ensures ample conformance with standards governing sterility of the packages and the amount of residual sterilizing agent.
A need for further improvement, however, is felt within the industry itself, particularly as regards temperature control of the air used to dry the packaging material web in the sterilizing unit.
Tests have shown, in fact, that, besides drying the web, localized hot-air treatment at the outlet of the sterilizing agent bath synergically improves the effectiveness of the sterilizing agent.
In known machines, the pressure and temperature conditions in the process and aseptic chambers are normally controlled by a closed air processing circuit, which draws air from the process chamber and feeds it back into the aseptic chamber, the temperature of which is controlled by a sensor. The airstream directed on to the packaging material may be generated by "air knives" supplied with air from the sterile chamber, e.g. by means of a recirculating conduit, as described in EP-A-1 050 467.
Since, in this solution, the temperature of the air supplied by the air knives cannot be regulated independently, a process parameter balance designed to simultaneously optimize drying and sterilizing efficiency ("killing rate") is extremely difficult to achieve.
In an alternative known solution, drying is performed in a low drying channel, through which the material is fed from the process chamber into the aseptic chamber. In this case, too, however, there is no independent adjustment of the air temperature inside the drying channel.
Another problem connected with poor temperature control of the air fed into the aseptic chamber is the risk, in certain operating conditions, of overheating the packaging material, thus resulting in "blistering" between the layers.

Unit for sterilizing web-fed material on a machine for packaging pourable food products


In a parts mounting apparatus, a suction nozzle is caused to perform a cycloid movement. A part such as an electronic part is sucked into the nozzle at one of bottom dead points of the cycloid movement and mounted onto another component such as a circuit substrate at the other or another bottom dead point. In compensation of the position of the nozzle at the bottom dead point, the nozzle is also caused to perform the cycloid movement. The position of the nozzle at the bottom dead point is monitored by a monitoring camera so that an amount of deviation of the position of the nozzle from the bottom dead point is obtained. The phase of the cycloid movement is compensated so that the amount of deviation of the nozzle is rendered zero. Alternatively, the part sucked in the nozzle positioned at the bottom dead point is monitored by the monitoring camera.

1. Field of the Invention
This invention relates to a parts mounting device wherein a suction and mounting nozzle performs a cycloid movement so that a high speed mounting of parts can be provided.
2. Description of the prior art
In one of conventional high-speed parts mounting apparatus, suction and mounting nozzles are mounted on an outer periphery of a rotating table to be vertically movable. Each nozzle is moved from a parts suction station to a parts mounting station with rotation of the rotating table. The rotating table is temporally stopped and each nozzle is lowered or raised at each station so that parts are sucked by the nozzles at the parts suction station and the parts are mounted on circuit substrates, for example, at the parts mounting station.
According to the above-described construction, the movement of the rotating table is intermittent and accordingly, the operation of each nozzle at each station is intermittent in a sequence of lowering, stop (suction or mounting), raising and stop (standby). The operation of the whole apparatus is thus intermittent, which is one of causes for interrupting the high-speed parts mounting work.
The assignees have jointly developed a parts mounting apparatus wherein the above-described intermittent movement of the apparatus has been changed to a continuous movement so that a high-speed mounting work can be performed. In the developed apparatus, suction and mounting nozzles are mounted on the outer periphery of a rotating carrier rotated in a horizontal direction so that the nozzles are turned in a vertical direction. With rotation of the rotating carrier, each nozzle is turned along the outer periphery of the carrier in the state that each nozzle is directed downward. In this construction, each nozzle performs a cycloid movement in the direction of the outer periphery of the rotating carrier with its rotation. The cycloid movement of each nozzle has a plurality of bottom dead points. A part is sucked in the distal end of the nozzle when the nozzle reaches predetermined one of the bottom dead points corresponding to a part sucking stage and the suction is released when the nozzle reaches another predetermined bottom dead point corresponding to a part mounting stage so that the part is mounted on the circuit substrate.
In the apparatus utilizing the cycloid movement, however, a mounting error and a dimensional error of the nozzle, an error in setting return to origin and the like cause errors in the position of the nozzle at part sucking and mounting points or the position of the nozzle when it reaches the bottom dead point in the cycloid movement. The part is not sucked by the nozzle or is improperly mounted on the substrate when the errors in the position of the nozzle at the part sucking and mounting points are increased. Accordingly, the errors need to be compensated so that the precision in the part sucking and mounting positions of the nozzle can be secured.
It has been proposed that the rotating carrier be stopped so that the positional errors of the nozzle at the bottom dead point are compensated, as in the same manner in the conventional parts mounting apparatus. However, in the apparatus utilizing the cycloid movement, a number of gears are employed in a transmission system for the cycloid movement of the nozzle. Consequently, even when the position of the nozzle is compensated in the state that the rotating carrier is stopped, the position of the nozzle is deviated during the operation from the compensated one by a cumulative error due to some play in the gears of the transmission system. Accordingly, it is difficult to precisely compensate the position of the nozzle at the bottom dead point in the state that the parts mounting apparatus is deenergized. The position of the nozzle at the bottom dead point during the cycloid movement needs to be precisely compensated.


A resource division, allocation, and transmitting/receiving method of downlink for reducing inter-cell interference in an orthogonal frequency division multiplexing system are provided. Entire downlink radio resources are divided into a traffic resource group for a traffic channel and a control resource group for a control channel, the traffic resource group is divided into a first traffic resource group for the intra-cell mobile terminals and a second traffic resource group for a cell-boundary mobile terminal, and a part of the first traffic resource group is imaginarily divided into a (1−1)-th preliminary traffic resource group, the (1−1)-th preliminary traffic resource group being a preliminary resource group for the cell-boundary mobile terminal. The control resource group is allocated to a control channel for the intra-cell mobile terminal; and a resource of the first traffic resource group or the second traffic resource group is allocated to a traffic channel for the mobile terminal according to inter-cell interference affected to the mobile terminal. Radio resources may be reused in each downlink cell of the OFDM system, the traffic may be rapidly transmitted to the cell boundary mobile terminal, a system capacity may be increased, the cell plane may be easily performed, and the system capacity may not be decreased although the mobile terminal number, locations, and traffic density is not uniform.

(a) Field of the Invention
The present invention relates to a resource division, allocation, and transmitting/receiving method of downlink for reducing inter-cell interference in an orthogonal frequency division multiplexing system. More particularly, the present invention relates to a resource division, allocation, and transmitting/receiving method of downlink using an inter-cell interference eliminating scheme in an orthogonal frequency division multiplexing (hereinafter, referred to as "OFDM") system, and a method for improving a system capacity and a data transmission speed of a cell-boundary mobile terminal using the same.
(b) Description of the Related Art
As electronic/communication technology has been rapidly developed, a wireless voice communication service and wireless Internet service has been provided using a wireless network. In order to provide such a wireless voice communication service and wireless Internet service, a mobile communication system uses a code division multiple access (CDMA) scheme, a frequency division multiple access (FDMA:) scheme, and a time division multiple access (TDMA) scheme.
When the mobile communication system uses the conventional FDMA or TDMA scheme, the mobile communication system may not use common resources between adjacent cells, and accordingly, a sufficient signal to interference ratio may be obtained. However, there is a problem in that a system capacity may be decreased due to low frequency reuse efficiency. Since such a FDMA or TDMA scheme is mainly designed to provide a voice service at a constant data rate, the system capacity may be increased by increasing the number of available channels of a sufficient signal to interference ratio by means of a power control.
In order to largely increase frequency reuse efficiency of such a FDMA or TDMA scheme, a CDMA-based voice system has been proposed. The CDMA scheme makes an interference amount of each channel to be less changed by averaging interference amounts, and accordingly, wholly more channel may undergo an appropriate interference.
However, as a main mobile communication service has been converted from the voice service of a constant data rate to a packet service of a variable data rate, the orthogonal frequency division multiplexing and multiple access (OFDM/OFDMA) scheme for easily avoiding interference has replaced the CDMA scheme for controlling interference by averaging interferences. However, the OFDM/OFDMA-based mobile communication system has a problem to manage interference between adjacent cells interference.
In the OFDM/OFDMA-based mobile communication system (hereinafter, referred to as 'OFDM system'), the interference is averaged by a frequency hopping is proposed so as to manage such an interference between the adjacent cells interference problem. The frequency hopping spreads a frequency spectrum by hopping a transmit signal from one center frequency to another center frequency.
In the OFDM system, when each cell is designed to use different frequency hopping patterns, the inter-cell interference may be sufficiently averaged in an encoding packet.
As such an inter-cell interference averaging method, PCT published publication No. WO05/050873, entitled "resource partition, physical channel allocation and power allocation method, and a frequency reuse efficiency increasing method using the same in an orthogonal frequency division multiplexing access (OFDMA)-based cellular system" discloses that an interference is eliminated by averaging interferences so as to increase a frequency reuse, an entire resource is divided into a resource space and a resource sub-space, similar traffics are grouped, and the grouped traffics are allocated to one resource space and one resource sub-space. At this time, each resource area averages interference.
Describing this method in detail, in OFDM system, an entire cell is divided into three frequency reuse patterns and one resource space is divided into three resource sub-spaces. Each cell mainly uses one resource sub-space among the three resource sub-spaces to transmit data at a high power, and uses other two resource sub-spaces at a too low power to affect the adjacent cells. In this manner, the inter-cell interference may be averaged in the encoding packet.
Alternately, an inter-cell interference may be reduced by another method of "Interference Migration Considerations and Results on Frequency Reuse" (2005.6) by Siemens published in a 3GPP RAN WG1 Ad Hoc on LTE conferences. This paper proposes that a first reuse frequency is used between intra-cell mobile terminals and a second reuse frequency is used between cell-boundary mobile terminals. At this time, the intra-cell mobile terminals use some common resource among entire resources, and the cell-boundary terminals use other three-divided resources at each cell.
However, such a method has a problem in that a resource efficiency is decreased when the cell-boundary mobile terminal shares a resource with the intra-cell mobile terminals of the adjacent cell.
Meanwhile, the inter-cell interference of downlink is managed by decreasing a power of the base station largely affecting the mobile terminal. That is, the mobile terminal performs a communication when the power of the base station is decreased in a direction largely affecting the mobile terminal, and accordingly, it obtains a gain.
Since such an inter-cell interference management of downlink is based on interference directionality and interference convergence, a gain of downlink is small, a cell plane is complex, and resources are run by a plurality of resource group including a plurality of resources. And thus, when a normal cell structure is not provided, the mobile terminal is disposed near to the cell boundary line, or a density of the mobile terminal or traffic is not uniformly provided, a system capacity is decreased.
Accordingly, the OFDM system desires a method for solving an adjacent cell interference of the downlink so as to improve a transmission speed of a cell-boundary mobile terminal and increase a system capability.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

Method for resource partition, assignment, transmission and reception for inter-cell interference migration in downlink of OFDM cellular systems

Electronics and Telecommunications Research Institute


Systems and associated methods provide a level of indirection between multiple host computers and multiple data storage resources, such as removable media data storage devices. At least one of the hosts is not provided with direct access to some of the removable media data storage devices. Instead, logical addresses are provided to the host computers, where the logical addresses can relate to physical addresses associated with the data storage resources. A data storage resource handle or logical proxy may be presented to a host, and a management layer determines whether the host receives access to physical data storage resources, or virtual resources that emulate the physical resources.

Data storage needs continue to increase and thus the numbers and types of data storage devices are increasing correspondingly. Information technology personnel need methods to manage high-capacity data storage devices, which are sometimes configured as "libraries." These data storage libraries often include a few tape or disk drives and multiple slots to accommodate tape or disk cartridges. A library controller communicates between the host and a robot to control the movement of cartridges between slots and drives.
In some cases, a single host computer exchanges data with a single library. However, it is more common for several computers to communicate with one or more data storage libraries, or to have a data storage library effectively partitioned for use by multiple hosts.
As a result, there is a need to manage these libraries so that each host computer or user is allocated an appropriate amount of storage capacity and drives. One client software product NETBACKUP™, provided by Veritas of Mountain View, Calif., allows multiple computers to share a library. Each user must run a client-side copy of the NETBACKUP™ software, and the software then provides library management capabilities to the users. As an alternative to a client-side software solution, an intermediate software product, such as the SCALAR DLC™ by Advanced Digital Information Corporation of Redmond, Wash., partitions a library into portions so that the library may be shared by users.
A third library management solution is described in U.S. Patent No. U.S. Pat. No. 06,356,803. Under this patent, a multipath architecture is employed in a system where drives become the interface for the host and the library. Each host is associated with one or more drives, and each drive is then associated with a partitioned set of contiguous slots. The slots are contiguously assigned, with a direct mapping between a partitioned set of slots and a given drive. Other methods of sharing or managing a data storage library may be found in the following U.S. Patents/Applications: U.S. Pat. Nos. 6,044,442, 6,434,090, 6,487,474, 6,328,766, and US2001/0034813.
The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.
In the drawings, the same reference numbers and acronyms identify elements or acts with the same or similar functionality for ease of understanding and convenience. To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the Figure number in which that element is first introduced (e.g., element 1104 is first introduced and discussed with respect to FIG. 11).

Logical library architecture for data storage applications and methods of use