A method of growing a crystal (for example, a GaN system compound semiconductor crystal) on a substrate at least includes forming a first crystalline layer (a GaN system buffer layer), forming a second crystalline layer (a GaN system intermediate layer) and forming a third crystalline layer (a GaN system thick film layer). The three crystalline layers are respectively reared on conditions different from one another.

GaN system compound semiconductors (InxGayAl1-x-yN, 0≦x, y; x+y≦1) such as GaN, InGaN, AlGaN, InGaAlN and the like have been expected as materials of semiconductor electronic devices such as a light emitting device, a power device and the like and have been remarked as materials applicable in other various fields.
In an earlier development, it is difficult to grow a bulk crystal of the GaN system compound semiconductor. Therefore, a substrate obtained, for example, by forming a thin film single crystal such as GaN or the like on a different type crystal such as a sapphire or the like by hetero epitaxy has been used for the electronic device.
However, because lattice mismatching between a sapphire crystal and a GaN system compound semiconductor crystal is large, a dislocation density of the GaN system compound semiconductor crystal grown on the sapphire crystal becomes large. Therefore, a problem has been arisen that crystal defects are generated. Further, a sapphire has a low thermal conductivity not to easily release heat. Therefore, when a substrate having a GaN system compound semiconductor crystal grown on a sapphire crystal is used for an electronic device or the like largely consuming electric power, a problem has been arisen that the electronic device easily becomes a high temperature.
Further, the growth of a GaN system compound semiconductor crystal according to an epitaxial lateral overgrowth (ELO) method or the like using a hydride vapor phase epitaxial growth (hereinafter, abbreviated as HVPE) method has been tried. The ELO method is, for example, a method of forming an insulating film acting as a mask on a sapphire substrate, forming an opening in a portion of the insulating film to use the insulating film as the mask and growing a GaN system compound semiconductor crystal having high crystallinity while using an exposed surface of the sapphire substrate as a seed of the epitaxial growth.
In this method, the growth of the GaN system compound semiconductor crystal starts from the surface of the sapphire substrate placed on the inside of the opening formed in the mask, and a grown layer is spread on the mask. Accordingly, the dislocation density in the crystal can be suppressed to a low value, and a GaN system compound semiconductor crystal having small crystal defects can be obtained.
However, the GaN system compound semiconductor crystal obtained by the ELO method has large thermal distortion. Therefore, when the polishing is performed for the GaN crystal after the growth of the GaN crystal to separate the sapphire substrate from the GaN system compound semiconductor crystal inn order to obtain a GaN system compound semiconductor crystal wafer as a single substance, a problem has been arisen that the wafer is bended due to residual distortion.
Therefore, the inventors have proposed a method of using a rare earth 13 (3B) group perovskite crystal as one of materials of a different type crystal substrate and growing a GaN system compound semiconductor according to a hetero epitaxy while setting a {011} plane or a {101} plane of the perovskite crystal as a growth plane (No. WO95/27815). The {011} plane and the {101} plane denote a set of planes equivalent to a (011) plane and a set of planes equivalent to a (101) plane respectively.
In this growth technique of the above-described previous application, when GaN is, for example, grown on a {011} plane or a {101} plane of a substrate while using NdGaO3 (hereinafter, abbreviated as NGO), which is one of the rare earth 13 (3B) group perovskites, as the substrate, the lattice mismatching is almost 1.2%. Therefore, the lattice mismatching can be considerably lowered as compared with a case where a sapphire or SiC used in place of the sapphire is used as a substrate. Accordingly, because the dislocation density in the crystal is lowered, a GaN system compound semiconductor crystal having small crystal defects can be grown.
Further, the invention obtained by modifying the technique of the previous application has been proposed (Japanese Patent Application Publication No. Tokkai 2000-4045). In this invention, a GaN thin film layer is formed on an NGO substrate at a low temperature (400 to 750° C.), heat treatment is performed for the GaN thin film layer to heat up the GaN thin film layer to a predetermined temperature in an inert gas (N2 gas) atmosphere, and thereafter a GaN thick film layer is grown at a high temperature (800 to 1200° C.) on the GaN thin film layer. In this technique, because the GaN thin film layer is formed as a buffer layer before the formation of the GaN thick film layer, the buffer layer can prevent the NGO substrate from being reduced by reacting with NH3 or the like at a growth temperature (800 to 1200° C.) of the GaN system compound semiconductor. Accordingly, the deterioration of a grown GaN system compound semiconductor crystal caused by the reduction of the NGO substrate can be avoided.
However, in the technique of the above-described previous application (Japanese Patent Application Publication No. Tokkai 2000-4045), it was found out that a problem was arisen that the crystal quality is degraded, because the GaN thin film layer is formed at the temperature (400 to 750° C.) considerably lower than the growth temperature (800 to 1200° C.) of the GaN thick film layer in order not to reduce the NGO substrate. Further, the GaN thin film layer (a lower temperature buffer layer) having inferior crystal quality is required to be thickly formed to prevent the NGO substrate from being reduced during the heating up to the growth temperature of the GaN thick film layer. Therefore, it was found out that a problem was arisen that the crystallinity is further degraded.
Therefore, in the method described above, though the NGO substrate can be prevented from being reduced at the growth temperature of the GaN thick film layer, it is assumed that there is a probability that the GaN thin film layer adversely influences the GaN system compound semiconductor crystal grown on the GaN thin film layer so as to lower the crystal quality of the GaN system compound semiconductor crystal.
An object of the present invention is to provide a technique where, in a GaN system compound semiconductor crystal production method using a substrate (for example, a rare earth 13 (3B) group perovskite such as NGO or the like) capable of reacting with a raw material or being degraded due to heat during the rearing of a GaN system compound semiconductor layer, the crystal quality of the GaN system compound semiconductor crystal can be enhanced by improving the quality of a GaN thin film layer formed between the substrate and a GaN system thick film layer.


A white noise generator comprising a MOSFET operated in its linear region and having zero source-drain DC bias current. This is achieved by connecting the source or drain terminal of the MOSFET to a gate terminal of a MOSFET amplifier that may be implemented as a multi-stage differential amplifier. Such a noise source avoids the effect of DC current responsible for generating 1/f noise and has a small physical size that results in low parasitic capacitance of the device itself.

A source of white noise is a key element in Random Number Generator (RNG) circuits, which are used widely in hardware encryption devices. White noise is a type of random noise that may be generated in electronic circuits mostly as a result of random motion of electrons at non-zero temperature. It is know to generate white noise using linear resistors as well as active devices such as diodes and transistors. A linear resistor generates white noise whose power is proportional to the resistance, so that in order to obtain high amplitude white noise, a high resistance element is required. Usually, high resistance is achieved by increasing the length to width ratio of the resistor. Increasing the dimensions of the resistor in this manner enlarges its parasitic capacitance, which in turn reduces the noise bandwidth and thus reduces the noise amplitude. Thus the parasitic capacitance acts against the increased resistance and it is known that in practice the noise amplitude is actually determined by parasitic capacitance of the resistor and the input capacitance of the load.
"Review of noise in semiconductor devices and modeling of noise in surrounding gate MOSFET" by Bipin Rajendran published by the Department of Electrical Engineering Stanford University, December 2001 presents an introduction to different types of noise associated with CMOS with particular reference to white noise and to the problems associated with thermal noise and 1/f noise, also known as excess or flicker noise. White Gaussian noise is a name for a random process with Gaussian probability distribution behavior and has a autocorrelation function of a Dirac delta function type, which means that if the process is sampled at any two or more points of time the samples will have no correlation to each other. Noise spectral density is a Fourier transform of the autocorrelation function which in the case of white noise is constant (flat) for all frequencies. Any other type of noise is not white and sometimes called "colored". 1/f noise is not white noise because its autocorrelation function is not a Dirac delta function, and samples of a 1/f random variable have pretty strong correlation to each other.
"Prospects for charge sensitive amplifiers in scaled CMOS" (O'Connor et al.) appearing in Nuclear Instruments and Methods in Physics Research, A 480 (2002) 713725 presents a more detailed description of some specific circuit implementations for replacing the feedback resistor commonly used in noise generators by MOSFETs. Thus, a circuit is described in Section 6.4 on page 722 where the feedback resistor is replaced by a MOSFET in the triode region, which uses the gate to channel capacitance with source and drain shorted.
It thus emerges that use of MOSFETs in white noise generators that are used in the linear region to serve as very high impedance resistors is well known. It is also known that a MOSFET does not generate white noise except over a midband region and that the amount of noise generated depends on the quiescent conditions and source resistance. It thus follows that transistors require proper biasing for correct operation and this means that some DC current is always flowing through such a device. DC current is responsible for generating 1/f noise and as a result the generated noise is not white. 1/f noise is a shot noise which is not Gaussian, and in transistors, diodes and other active elements the 1/f noise is directly proportional to a DC current flowing through a device or in some cases to a powered DC current. In addition, the parasitic capacitance of the device also reduces the noise bandwidth, thus reducing the noise amplitude.
It would thus improve the quality of white noise produced by such a MOSFET if the effect of DC bias could be reduced.

International Business Machines Corporation


A vehicle has a drive train comprising a drive unit, a hydrostatic-mechanical power-split gear unit operatively connected to the drive unit and an output, and at least one braking device. An additional actuating device is allocated to the braking device and is operatively connected with a power request element and/or a driving direction selection element. Upon the presence of a deceleration of the vehicle requested by the driver through the power request element and/or the driving direction selection element and, the braking device is actuated to an extent that initiates a braking torque in the drive train. Upon the presence of a requested deceleration of the vehicle, a driving torque on the side of the drive unit is provided in the area of the output for a braking device that is not actuated by the driver. If the rotational speed of the drive unit exceeds a defined threshold of rotational speed, the braking device is operated to an extent that initiates a braking torque in the drive train.

DE 602 12 384 T2 discloses a method for operating a vehicle and/or a method for reversing the driving direction of a moving vehicle, for which a movement of a gear selection device is captured in a position that indicates a new intended driving direction. Such a method for reversing driving direction is often carried out during the operating of a wheel loader. When loading, a wheel loader alternately passes through short routes in the forward and reverse driving directions. Thereby, for example, the vehicle or wheel loader initially moves in the forward driving direction and, upon the presence of a request for a change in driving direction, brakes until it comes to a standstill, and is then operated in a reverse driving direction. Following this, the wheel loader is once again completely braked, and is then operated in the forward driving direction.
In order to avoid a motor of a vehicle being used for the braking of the vehicle when there is a change in driving direction requested by the driver, and the fuel consumption of the motor being increased to an undesired extent, the driving brakes of the vehicle, which are wheel brakes, are actuated depending on the degree of actuation by the driver of a gas pedal of the vehicle, after the gear selection device is transferred into a position equivalent to the new driving direction position. Thereby, it is intended that the extent of the actuation of the driving brakes increases with an increasing actuation of the gas pedal of the vehicle.
A drive train of a vehicle comprises an internal combustion engine in the form of, for example, a diesel engine, an automatic gearbox and/or a main gearbox, and a hydrodynamic torque converter arranged between the main gearbox and the internal combustion engine. The main gearbox is constructed with a forward/reverse gearbox, and a pump for the lift hydraulics of the vehicle is powered by an output shaft of an internal combustion engine. An output shaft of the main gearbox is connected with a differential gearbox of a wheel axle, on which the drive wheels of the vehicle are arranged. Each driving brake is provided in the area of the wheels, in a known manner.
Assuming an operating state of the vehicle, which may be constructed as a wheel loader, with an actual transmission ratio engaged in the main gearbox, is operated with a current vehicle speed in the forward driving direction, and upon a request by the driver for a change in driving direction from a forward to reverse driving direction and the simultaneous selection of a transmission ratio for reverse travel in the main gearbox, the gear selection device is adjusted by the driver into a position equivalent to this. The actuation of the gear selection device by the driver into a new position is recorded by a recording device, which is connected to a control unit.
Based on the movement of the gear selection device and/or the recording of the new position of the gear selection device, the main gearbox of the vehicle is decoupled from the internal combustion engine of the vehicle in the area of the forward/reverse gearbox, by which the motor power is now available in its entirety for the supply of hydraulic functions through the pump and other power consumption devices in the vehicle. Both the motor speed and the braking force provided by the driving brake are increased, while the drive speed is reduced at the same time.
In order to brake the vehicle when change in driving direction is requested, the gas pedal must be pressed by the driver, while at the same time the driving brake is not actuated. This leads to a controlled actuation of driving brakes of the vehicle. For this purpose, the position of the gas pedal is recorded by a second recording device. Thereby, the extent of the actuation of driving brakes is controlled as a function of the position of the gas pedal of the vehicle, whereas the deceleration of the vehicle is adjustable, in a linear or non-linear manner, to a desired extent.
However, it is disadvantageous that, based on the decoupling of the internal combustion engine from the main gearbox, thus from the output of the vehicle, the energy to be expended for the braking of the vehicle is not usable or recoverable for powering the hydraulic consumption devices connected with the internal combustion engine.
For vehicle drive trains without hydrodynamic torque converters constructed with hydrostatic-mechanical power-split gear units, when the driver requests a deceleration of a vehicle, for a simultaneous braking device that is not actuated by the driver, the power flow between a driving unit, such as a diesel engine or the like, and an output is not interrupted, and the drive unit is transferred in an overrun mode, in order to be able to apply a corresponding driving torque on the output. At the same time, the transmission ratio of the gear unit increases during the deceleration process of the vehicle, and the braking action of the drive unit increases, which does not consume any fuel in overrun mode. If, during such an operating state process of a vehicle drive train, an additional consumption device of a vehicle constructed with the vehicle drive train at the same time actuates working hydraulics, the thrust performance of the drive is able to be recovered directly in the vehicle hydraulics, as the power flow in the area of the gearbox between the output and the drive unit is permanently maintained during a deceleration process of the vehicle.
However, it is problematic with this approach that, upon a deceleration process of a vehicle with the starting point of a high speed of the vehicle, the braking action of the drive unit for the implementation of the requested deceleration of the vehicle is able to be realized only if a rotational speed of the drive unit, during the deceleration process of the vehicle, assumes values that adversely affect the functioning of the drive unit under certain circumstances.

Vehicle and method for operating a vehicle


An internal combustion engine combusts a first fuel or a second fuel. A method for controlling the engine comprises supplying first fuel to at least one combustion chambers of the internal combustion engine, stopping the supply of the first fuel to the combustion chamber in response to an engine operating condition, and fueling with the second fuel to the at least one combustion chamber after a predetermined period, so as to maintain an engine speed within a predetermined range.

The present invention generally relates to a dual fuel internal combustion engine selectively combusting first fuel and second fuel, and more particularly relates to switching fuel for a dual fuel internal combustion engine selectively combusting gasoline and gaseous hydrogen.
In recent years, for a lower tailpipe emission from internal combustion engines, dual fuel engines using together gaseous fuel, such as compressed natural gas, liquidized propane gas, or compressed hydrogen, and gasoline have been developed. For example, in Japanese patent application publication no. H03-26835, a dual fuel engine using together gasoline and gaseous hydrogen is described. Also, disclosed in Japanese patent application publication no. H11-311136 is a hybrid automotive vehicle using an electric motor as well as a dual fuel engine using bi-fuel of gasoline and gaseous hydrogen to drive the vehicle.
In a dual fuel engine that is capable of combusting gaseous hydrogen and/or gasoline, fuel injected into the engine cylinders or combustion chambers may be switched from gasoline to gaseous hydrogen. During the transition from gasoline to hydrogen, the initial charge may be ignited earlier than desired, thereby increasing temperature and pressure within the intake manifold. In particular, combustion of gasoline can elevate the temperature of certain combustion chamber surfaces and may also produce residual uncombusted carbon or other matter. These elements that remain in the combustion chamber may cause some of the injected hydrogen to increase temperature and pressure in the intake system. Furthermore, it may be possible during such conditions to combust gasoline that may remain in the intake manifold from prior gasoline injections (abnormal combustion).
Therefore, the inventors herein have recognized the above-mentioned disadvantages and has developed a method to transition an internal combustion engine from gasoline operation to hydrogen operation that offers substantial improvements.


A high-performance reverse-conduction field-stop (RCFS) insulated gate bipolar transistor (IGBT) includes a first conductive type substrate, a plurality of trenches defined on a bottom face of the substrate, a plurality of first conductive type doping regions formed on bottom face of the trenches, a second conductive type doping region formed on bottom face of the substrate, and a first conductive type field stop doping region formed in the substrate and separated from the bottom face of the substrate by a field stop depth, where the field stop depth is larger than a depth of the trench. Due to a separation between the first conductive type doping regions and the second conductive type doping region, Zener diode can be prevented from forming on bottom side of the substrate and the performance of IGBT can be accordingly enhanced.

1. Field of the Invention
The present invention relates to an insulated gate bipolar transistor and method for manufacturing the same, especially to a high-performance insulated gate bipolar transistor and method for manufacturing the same.
2. Description of Prior Art
Insulated gate bipolar transistor (IGBT) is a semiconductor device combining the features of metal-oxide-semiconductor field effect transistor (MOSFET) and bipolar junction transistor (BJT). IGBT has the advantages of gate-controlling ability of MOSFET and low turn-on voltage of BJT and is thus extensively used in high voltage and high power applications.
A conventional IGBT, such as a punch through (PT) IGBT, mainly comprises a P+ type semiconductor substrate and N-type buffer layer arranged thereon. An N type epitaxial layer is formed on the N-type buffer layer and functions as drain of parasitic MOSFET in the IGBT. Moreover, a gate and an emitter are formed in the N type epitaxial layer, and a collector is formed on bottom face of the P+ type substrate. The breakdown voltage of the PT IGBT is determined by the P+ type substrate and N-type buffer layer because a maximum electric field is generated therebetween.
Another conventional IGBT, such as a non-punch through (NPT) IGBT, does not use N-type buffer layer. The breakdown voltage of the NPT IGBT is determined by the avalanche mechanism of the N type epitaxial (N drift) layer. To increase the breakdown voltage, field stop (FS) IGBT was developed, where the N-type buffer layer in PT IGBT is replaced by a field stop ion implantation layer. Therefore, the abrupt junction in the PT IGBT is also replaced by a graded (such as a linearly graded) N type profile. The value of the maximum electric field can be advantageously reduced to enhance breakdown voltage.
However, in above-mentioned three types of IGBTs, a fast return epitaxial diode (FRED) is needed to parallel connect with the IGBT to release turn-off current. Therefore, a reverse-conducted diode is built-in above mentioned IGBTs for soft switching. This kind of IGBT is referred to as reverse conduction field stop (RCFS) IGBT. The conventional RCFS IGBT is first formed with N+ type doped layer on backside of substrate by using metal mask, then formed with P+ type doped layer functioning as collector, and finally formed with N+ type doped layer and P type doped layer by rapid thermal annealing. Nevertheless, lateral Zener diode tends to form in the RCFS because the N+ doped layer and the P type doped layer are on the same horizontal plane of the backside of the substrate.

High-performance reverse-conduction field-stop (RCFS) insulated gate bipolar transistor and method for manufacturing the same


A load control device may control power delivered to an electrical load from an AC power source. The load control device may include a controllably conductive device adapted to be coupled in series electrical connection between the AC power source and the electrical load, a zero-cross detect circuit configured to generate a zero-cross signal representative of the zero-crossings of an AC voltage. The zero-cross signal may be characterized by pulses occurring in time with the zero-crossings of the AC voltage. The load control device may include a control circuit operatively coupled to the controllably conductive device and the zero cross detect circuit. The control circuit may be configured to identify a rising-edge time and a falling-edge time of one of the pulses of the zero-cross signal, and may control a conductive state of the controllably conductive device based on the rising-edge time and the falling-edge time of the pulse.

Load control devices, such as switches, for example, use electrical relays to switch alternating currents being supplied to an electrical load. The life time of such electrical relays may be shortened by arcs or sparks caused at the instant when the relay closes. Some prior art systems seek to suppress arcs by controlling the relay actuation time such that the relay contact(s) close as nearly as possible to a zero cross of the alternating-current (AC) waveform.
FIG. 1 depicts an AC voltage waveform as controlled by an example prior art relay switch control circuit. Waveform 100 depicts the waveform of the AC power source, where the portion in dashed line may represent the voltage of the AC power source, and the portion in solid line may represent the voltage across an electrical load. As shown, the waveform 100 may cross through zero volts at voltage zero crossings such as the zero crossings 110A and 110B. The example prior art relay switch control circuit may include a voltage zero crossing detector for detecting the zero crossings such as the zero crossing 110A. The example prior art relay switch control circuit may store a relay-actuation delay 120, which corresponds to the time interval between the relay actuation time and the time when the relay contact(s) initially close in response to actuation. In operation, the relay switch control circuit may actuate the relay at relay actuation time 130A prior to the next zero crossing 110B. As shown, the relay actuation time 130A leads the next zero crossing 110B, or the target zero crossing for relay closure, by the relay-actuation delay 120 such that the relay contact(s) close at a time corresponding to the target zero crossing 110B.
In operation, the example prior art relay switch control circuit detects the zero crossing 110A, waits for a relay actuation adjustment 150A, and actuates the relay at time 130A. The relay actuation adjustment time period 150A corresponds to the difference between a full AC cycle and the relay-actuation delay time period 120. When the relay contact(s) are closed at the zero crossing 110B, substantially no current flows through the relay contact(s). The value of the relay-actuation delay time period 120 may be updated to account for any variation caused by temperature, and/or aging or deterioration over the life time of the relay.
When a relay closes, however, there is a settling time before the relay contact(s) come to rest in the closed state. For example, as shown in FIG. 1, the relay contact(s) may bounce one or more times for a time period 140 before becoming steadily closed. Bouncing results in wasted energy that may dissipate in the relay contact(s) as heat. This heat may cause the relay contact(s) to weld and become inoperative.
Some prior art systems seek to address this problem by offsetting the relay actuation time by one-half of the relay contact-bounce duration. FIG. 2 depicts an AC waveform as controlled by an example prior art relay switch control circuit with bounce compensation. Here, the relay actuation adjustment time period 150B corresponds to the difference between a full AC line cycle and the sum of relay-actuation delay time period 120 and one-half of the relay contact-bounce duration 140. In other words, the relay actuation adjustment time period 150B is less than the relay actuation adjustment time period 150A by one-half of the relay contact-bounce duration. A relay actuation time 130B leads the target zero crossing for relay closure by the relay-actuation delay time period 120 plus one-half of the relay contact-bounce duration 140. Consequently, as shown in FIG. 2, the relay contact(s) may continue bouncing for a period right after a zero cross possibly during high current conditions, thus suffering from similar behavior as shown in FIG. 1. Relay bouncing during this time period may cause the relay contact(s) to weld. Further, in operation, the duration of the relay bounce period may vary with each closure of the relay, thus the relay may actually become steadily closed at any time within the relay contact-bounce duration 140.
Some prior art systems also control the relay open actuation time such that the relay contact(s) open as nearly as possible to a zero crossing of the AC waveform. The relay actuation time is offset by an open time delay in a time-aligned manner relative to a zero-crossing. The hope is that the relay contact(s) will actually be opened when the power source current is substantially zero amps. Such prior art systems check whether the open time delay is outdated due to hardware aging, and replace the present value with a new value upon detecting that the open time delay is no longer correct. This type of reactive correction may still result in relays opening with a high voltage. Unfortunately, when a relay opens with a high voltage, undesirable arcing may occur and may persist through the next zero crossing. This may significantly shorten the operative life of the relay.

Controlling a controllably conductive device based on zero-crossing detection


A two-step method for cloning restriction modification systems is provided which comprises introducing the modification or methylase gene into a host cell and expressing the gene therein to protect the host cell followed by introducing the restriction or endonuclease gene into the host whereby the restriction gene is expressed at lower levels relative to the modification gene. Related methods for producing restriction enzymes is also disclosed as well as clones containing the BamI and DdeI restriction genes.

The present invention relates to a method for cloning restriction-modification systems, to the clones produced thereby, and to methods for producing restriction and/or modification enzymes from the clones. This invention also relates to clones for the DdeI and BamHI restriction endonucleases and modification methylases, and related methods for the production of these clones and enzymes.
Restriction endonucleases are a class of enzymes that occur naturally in bacteria. When they are purified away from other contaminating bacterial components, restriction endonucleases can be used in the laboratory to break DNA molecules into precise fragments. This property enables DNA molecules to be uniquely identified and to be fractionated into their constituent genes. Restriction endonucleases have proved to be indispensable tools in modern genetic research. They are the biochemical `scissors` by means of which genetic engineering and analysis is performed.
Restriction endonucleases act by recognizing and binding to particular sequences of nucleotides (the `recognition sequence`) along the DNA molecule. Once bound, they cleave the molecule within, or to one side of, the sequence. Different restriction endonucleases have affinity for different recognition sequences. Close to one hundred different restriction endonucleases have been identified among the many hundreds of bacterial species that have been examined to date.
Bacteria tend to possess at most only a small number restriction endonucleases per species. The endonucleases typically are named according to the bacteria from which they are derived. Thus, the species Haemophilus aegyptius, for example synthesizes 3 different restriction endonucleases, named Hae I, Hae II and Hae III. Those enzymes recognize and cleave the sequences (AT)GGCC(AT), PuGCGCPy and GGCC respectively. Escherichia coli RY13, on the other hand, synthesizes only one enzyme, EcoR I, which recognizes the sequence GAATTC.
In nature, restriction endonucleases play a protective role in the welfare of the bacterial cell. They enable bacteria to resist infection by foreign DNA molecules like viruses and plasmids that would otherwise destroy or parasitize them. They impart resistance by scanning the lengths of the infecting DNA molecule and cleaving them each time that the recognition sequence occurs. The break-up that takes place disables many of the infecting genes and renders the DNA susceptible to further degradation by non-specific endonucleases.
A second component of bacterial protective systems are the modification methylases. These enzymes are complementary to restriction endonucleases and they provide the means by which bacteria are able to identify their own DNA and distinguish it from foreign, infecting DNA. Modification methylases recognize and bind to the same nucleotide recognition sequence as the corresponding restriction endonuclease, but instead of breaking the DNA, they chemically modify one or other of the nucleotides within the sequence by the addition of a methyl group. Following this methylation, the recognition sequence is no longer bound or cleaved by the restriction endonuclease. The DNA of a bacterial cell is always fully modified, by virtue of its modification methylase, and it is therefore completely insensitive to the presence of the endogenous restriction endonuclease. It is only unmodified, and therefore identifiably foreign, DNA that is sensitive to restriction endonuclease recognition and attack.
With the advent of genetic engineering technology, it is now possible to clone genes and to produce the proteins and enzymes that they encode in greater quantities than are obtainable by conventional purification techniques. The key to isolating restriction endonuclease clones is to develop a simple and reliable method to identify such clones within complex `libraries`, i.e. populations of clones derived by `shotgun` procedures, when they occur at frequencies as low as 10.sup.-4 to 10.sup.-3. Preferably, the method should be selective, such that the unwanted majority of clones are destroyed while the rare desirable clones survive.
Type II restriction-modification systems are being cloned with increasing rapidity. The first cloned systems used bacteriophage infection as a means of selectively isolating restriction endonuclease clones (for PstI Walder et al., Proc. Nat. Acad. Sci. 74 1503-1507 (1981), HhaII Mann et al. Gene 3: 97-112 (1981). Since the presence of restriction-modification systems in bacteria enable them to resist infection by bacteriophages, cells that carry cloned restriction modification genes can in principle be selectively isolated as survivors from libraries that have been exposed to phage. This method has been found, however, to have only limited value. Specifically, it has been found that cloned restriction-modification genes do not always manifest sufficient phage resistance to confer selective survival. Another cloning approach involves transferring systems initially characterized as plasmid-borne into E. coli cloning plasmids (EcoRV, Bougueleret et al., Nucl. Acid. Res. 129:3659-3676 1984: PaeR7, Gingeras and Brooks, Proc. Natl. Acad. Sci. USA 80:402-406 1983, Theriault and Roy, 1982; PvuII, Blumenthal et al., J. Bacteriol. 164:501-509 1985. Finally, a growing number of systems are now being cloned by selection for an active methylase gene (BsuRI, Kiss et al., Nucl. Acid. Res. 13:6403-6421 1986; TaqI); since the two genes are often closely linked, both genes are cloned simultaneously. However, the methylase selection does not always yield a complete restriction system (BspRI, Szomolanyi et al., Gene 10:219-225 1980; MspI, Walder et al., J. Biol. Chem. 258:1235-1241 1983). Even attempts to clone larger regions adjacent to the methylase gene can fail to produce an active endonuclease gene.
In some systems the cloning problem may lie in trying to introduce the endonuclease gene into a host not adequately protected by methylation. If the methylase gene and endonuclease gene are introduced on a common DNA fragment, the former gene product must modify the host before the latter gene product cleaves the host genome.
Another obstacle to cloning these systems in E. coli was discovered in the process of cloning diverse methylases. Many E. coli strains (including those normally used in cloning) have systems that block introduction of DNA containing heterologous cytosine methylation into the cells (Raleigh and Wilson, submitted for publication). Therefore, it is also necessary to carefully consider which E. coli strain(s) to use for cloning.
Because purified restriction endonucleases, and to a lesser extent, modification methylases, are useful tools for characterizing and rearranging DNA in the laboratory, there is a commercial incentive to develop methods of obtaining strains of bacteria that synthesize these enzymes in abundance. Such strains would be useful because they would simplify the task of purification as well as providing the means for production in commercially useful amounts.

Method for cloning restriction modification system


A level for a hierarchical organizational chart is associated with a virtual attribute and the values for the level are generated from values for the virtual attribute. The organizational chart is derived from distinguished name entries in a lightweight directory access protocol directory and the virtual attribute is not associated with an object in a schema for the directory. The virtual attribute may be a virtual recursive attribute or a virtual reverse attribute.

Lightweight Directory Access Protocol (LDAP) is a networking protocol for TCP/IP network directory services. An LDAP directory typically is represented as a hierarchical tree of entries, each of which consists of a set of named attributes with values. Each entry has a unique identifier known as a Distinguished Name (DN), which consists of a set of attributes and the DN of its parent entry, if any. The set of attributes is referred to as the entry's Relative Distinguished Name (RDN). Each attribute consists of a "name:value" pair and some attributes may be multivalued. Thus, the entry for Jane Smith who works for John Doe in the Sample company may be represented as a string:    dn: cn=Jane Smith, dc=sample, dc=com    manager: cn=John Doe, dc=sample, dc=com    mail: firstname.lastname@example.com dn is the name of the entry, "cn=Jane Smth" is the entry's RDN and "dc=sample, dc=com" is the DN of the parent entry. The other lines show the attributes in the entry. Attribute names are typically mnemonic strings, like "cn" for common name, "dc" for domain component, and "mail" for e-mail address. The attributes for a DN are defined as objects in an LDAP schema. A Directory Information Tree (DIT) defines the logical structure of the hierarchy
Each LDAP server in a network commonly stores a directory subtree rooted at a specific entry, e.g. "dc=sample, dc=com" and will return results of queries on that subtree to the requesting client. An LDAP server may also hold references to other LDAP servers, so that a query on the "ou=Engineering, dc=sample, dc=com" would cause the server to return to the client a reference to another LDAP server that stores that part of the directory tree. Alternatively, an LDAP server may be configured to pass the query onto the appropriate server and then return the result to the client.

Extension of organizational chart dynamic group lists based on LDAP lookups


A signal processor and processing method are provided for measuring current received from a photo-detector. Generally, the processor includes a transimpedance amplifier (TIA) to integrate a current received from a photo-detector in the optical navigation system to generate a voltage signal having a slope that is proportional to the received current, and a comparator having a first input coupled to an output of the TIA to receive the voltage signal, and a second, inverting, input coupled to a threshold voltage. The comparator is configured to compare the voltage signal to the threshold voltage and to generate an output pulse having a predetermined voltage and a duration or width that is a function of the received current.

Signal processors are used in a wide range of applications including, for example, measuring a current output from a photo-detector of an array in an optical navigation system. Optical navigation systems, such as an optical computer mouse or trackball, are well known for inputting data into and interfacing with personal computers and workstations. Such devices allow rapid relocation of a cursor on a monitor, and are useful in many text, database and graphical programs. A user controls the cursor, for example, by moving the mouse over a surface to move the cursor in a direction and over distance proportional to the movement of the mouse. Alternatively, movement of the hand over a stationary device may be used for the same purpose.
One embodiment of an optical computer mouse uses a coherent light source, such as a laser, to illuminate a rough surface, and an array of a number of photo-sensors or detectors, such as photodiodes, to receive light scattered from the surface. Light from the coherent source scattered off of the surface generates a random intensity distribution of light known as speckle. The varying intensity of scattered light detected by the photo sensors in the array as the mouse is moved across the surface is used to detect movement of the mouse.
Although a significant improvement over prior art optical mice, these speckle-based devices have not been wholly satisfactory for a number of reasons. In particular, processing signals from the photodiodes involves measuring the current output from the photodiode through an integrating transimpedance amplifier (TIA). The TIA converts current to voltage by producing a voltage output with a slope proportional to the current. Typically, the TIA is either single ended or differential, and is followed by one or more analog-to-digital-converters (ADCs). The disadvantages of this approach using one or more ADCs include a relatively high complexity and high power consumption. In addition, the above approach does not insure that the measurements are made while the TIA is operating continuously in a linear region, and is not saturating before being read by the ADC.
Another problem arises from the fact that the TIA output is reset at the beginning of each sampling period and then allowed to ramp up for a fixed amount of time. At the end of the ramp time, the voltage output is converted to a digital value in the ADC and the next sampling period begins. Ideally, the TIA output should be reset to exactly the same voltage at the beginning of each sampling period. In actuality, there is a variation in the beginning voltage output from the TIA after reset commonly referred to as reset noise. Because the digital value is derived from the output voltage measured at the end of the ramp, this reset noise shows up as noise in the digital value measured, reducing the accuracy of measurement, and therefore the performance of the optical mouse.
One technique for dealing with the above reset noise problem is to measure a digital value at the beginning of the ramp just after reset and then subtract this from the digital value measured at the end of the sampling period, thereby limiting the effects of the reset noise on the measurement. However, this increase in accuracy is accomplished at the expense of requiring twice as many analog to digital conversions, and hence doubling the sampling rate required of the ADCs, and requiring additional digital circuitry to store the beginning voltage value and do the subtraction.
Accordingly, there is a need for a signal processor or circuit and method for measuring current received from a photo-detector in a photo-detector array that uses a circuit having reduced complexity and power consumption. It is further desirable that the circuit and method accomplish this measurement in a way that is substantially independent of and unaffected by reset noise from an integrating transimpedance amplifier output at the beginning of each sample period.
The present invention provides a solution to these and other problems, and offers further advantages over the prior art.

Signal processing circuit and method using analog voltage signal to pulse width modulation conversion


A reconfigurable integrated circuit includes a plurality of function blocks and a plurality of programmable switches to switchably connect between function blocks included in the plurality of function blocks. The plurality of function blocks each includes at least one operation unit or one memory unit. The plurality of function blocks each includes at least one data input port connected to at least on of the plurality of programmable switches and at least one data output port connected to at least one of the plurality of programmable switches. Further, at least a pair of function blocks included in the plurality of function blocks is connected without intervening the programmable switch and data being output from a direct output port included in one of the pair of function blocks can be input to a direct input port included in the other of the pair of function blocks.

1. Field of the Invention
The present invention relates to a reconfigurable integrated circuit capable of determining a circuit configuration by selecting connection relationship between function blocks.
2. Description of Related Art
As a processor unit for executing various data processes, products called CPU (Central Processing Unit) and MPU (Micro Processor Unit) are coming into practical use. In a data processing system using these processor units, an application program including several instructions and processing data are stored in a memory device. The processor unit reads out the instructions and processing data from the memory device to sequentially execute operations. Such processor unit is able to achieve various data processes by switching application programs. However complicated data processes cannot be executed at high speed as the instructions and processing data are sequentially read out from the memory device to be executed.
On the other hand, a dedicated circuit manufactured using cell-based IC and gate array is referred to as a custom IC and ASIC (Application Specific Integrated Circuit) or the like. As in such dedicated circuit, since a logical circuit for executing data processes is formed by hardware, complicated data processes can be executed at high speed. However the dedicated circuit has a disadvantage that it can be used only for particular data processes and is lacking flexibility as compared to the abovementioned data processing system including CPU.
As a middle device between them, a reconfigurable device is known that is capable of changing circuit configuration depending on the application program or processing data. In the reconfigurable device, various operation units and register files are provided as many small-sized function blocks. Further, in a design or operation of a device, the circuit configuration of the reconfigurable device can be changed by changing operation and connection relationship of the function blocks depending on the application program or processing data.
The configuration of a general reconfigurable device 7 is shown in FIG. 22. A function block 70 includes one or a plurality of operation units and register files. A programmable switch (PSW) 15 is provided to lines for connecting between several function blocks 70 and connected to wiring resource for connecting between the function blocks 70 and to input/output ports of function blocks 70. By the control of the programmable switches 15, connections between the function blocks 70 can be switched. As configuration information memories (CFGM) 16 enables to change the configuration of the reconfigurable device 7, they store configuration information regarding the operation of the function blocks 17 and connection relationship of the programmable switches 15 that is required for configuration definition of the reconfigurable device 7. The circuit configuration can be changed by loading the configuration information stored in the configuration memory 16 to the function blocks 70 and programmable switches 15 depending on application programs or processing data.
An array processor, which is one of the abovementioned reconfigurable devices, is disclosed in Japanese Unexamined Patent Application Publication No. 2001-312481 and No. 2003-76668. Hereinafter, the array processor disclosed in Japanese Unexamined Patent Application Publication No. 2001-312481 and No. 2003-76668 is referred to as a first related art. The array processor of the first related art is described with reference to FIGS. 23 to 25.
FIG. 23 shows a configuration example of an array processor 8 according to the first related art. The array processor 8 has a configuration in which processor elements (PE) 81 and programmable switches 15 for electrically connecting among the processor elements (PE) 81 being arranged in matrix. Further, the array processor 8 includes a State Transition Controller (STC) 82 for controlling changes of a circuit configuration by changes in transitions of processing state of the array processor 8, which is specifically the changes in operation of the processor elements 81 and connection relationship between the processor elements 81.
The STC 82 holds a series of object codes being input externally, generates an instruction pointer (IP) for the processor elements 81 and programmable switches 15 and supplies the generated instruction pointer to the processor elements 81 and programmable switches 15. The instruction pointer here is information for specifying an address of an instruction code stored in an instruction memory 801, which is described later in detail. Further, an instruction code is an identifier for specifying the operation of the processor elements 81 and wiring connections by the programmable switches 15. Specifically, the instruction memory 801 corresponds to the configuration memory 16 and an instruction code corresponds to configuration information stored in the configuration memory 16.
The configuration of the processor element 81 is shown in FIG. 24. The processor element 81 includes operation units such as the instruction memory 801, an instruction decoder 802, register file 140, ALU (Arithmetic and Logical unit) 803, which is an operation unit for performing arithmetic and logic operations) and DMU (Data Management Unit) 804, which is an operation unit with functions such as bit processes. Further, an internal wiring resource 805 is a programmable switch for changing data input destination for data input from the programmable switch 15 and connection relationship between the operation units including the register file 140 and ALU 803.
The instruction memory 801 stores an instruction code for defining operations such as a selection of the operation units in the processor element 81. The instruction decoder 802 decodes the instruction code and controls the operations of the operation units including the ALU 803 and internal wiring resource 805. The instruction memory 801 is able to store a plurality of instruction codes and dynamically change the circuit configuration of the array processor 8 by switching an instruction pointer supplied from the STC 82 to the instruction memory 801.
An example of internal configuration for the ALU 803 is shown in FIG. 25. The ALU 803 includes two data input ports 8031 and 8032 and a data output port 8034. A bit wide of input/output data for these ports is m bit, which is a data processing unit in the array processor 8. Further, the ALU 803 includes a 2-input logic operation unit 128, 2-input selector 129, 2-input m bit wide adder/subtracter 126 and 2-input m bit wide comparator 127 connected in parallel between the input port 8031 and 8032 and output port 8034. A multiplexer 131 is provided between the operation units 127 to 129 and output port 8034. An output from one of the operation units 127 to 129 is selected by the multiplexer 131 and output to the output port 8034.
In response to the instruction code supplied to the ALU 803 via the instruction decoder 802, by selecting the operation units 127 to 129 and input source for the multiplexer 131, the ALU 803 operates as various arithmetic operation units, logic operation unit, selector or comparator.
As described above, the array processor 8 includes a plurality of function blocks including the ALU 803 inside the processor element 81 and the internal wiring resource 805 for switching the connection between the function blocks. The array processor 8 further includes the programmable switches 15 for switching the connection between the processor elements 81. To be more specific, as against to the configuration of the reconfigurable device 7 shown in FIG. 22 in which the function blocks 70 are variably connected through the programmable switches 15, the array processor 8 has a hierarchized configuration by variable connections between the function blocks inside the processor elements 81 and variable connections between the function blocks between the processor elements 81.
The abovementioned reconfigurable device 7 and array processor 8 have an advantage of having better flexibility in the circuit configuration as compared to dedicated circuits such as ASIC and also have a disadvantage of having redundant reconfigurable circuit configuration. The reconfigurable device 7 and array processor 8 have a plurality of function blocks 70 and processor elements 81 that support for switching the circuit configuration, configuration memory 16 for storing circuit configuration information or instruction memory 801 and instruction decoder 802. Further, the programmable switches 15 for switching the connection relationship between the function blocks or processor elements require larger wiring area as compared to a wiring for the dedicated circuits. Therefore, to form a desired circuit by the reconfigurable device 7 or array processor 8, an integration degree is lower as compared to when forming the same circuit by a dedicated circuit, thereby reducing an area efficiency.
As an example, a comparison when a circuit for performing arithmetic operation of (A+B)*(C+D)→Y is formed by the reconfigurable device 7 and a dedicated circuit is shown in FIGS. 26A and 26B. FIG. 26A shows a circuit formed by the dedicated circuit. The circuit of FIG. 26A is comprised of an adding circuit 810a for calculating A+B, adding circuit 810b for calculating C+D and a multiplying circuit 811 for multiplying output data from the two adding circuits. On the other hand, FIG. 26B shows the configuration by the reconfigurable device 7. In such case, in addition to components which are programmable switches 15a to 15c for enabling to switch input data to function blocks 70a to 70c and operation units required to comprise the adding and multiplying circuits, other circuit components included in the function blocks 70a to 70c and configuration information memories 16a to 16c are required. Other circuit components included in the function blocks 70a to 70c and the configuration information memories 16a to 16c are redundant part when forming the circuit by the reconfigurable device 7.
Reconfigurable devices according to the related art including the abovementioned array processor 7 may not be able to achieve an efficient circuit in terms of area efficiency and processing speed, depending on content of application program and processing data.
As an example, a case is described in which the number of inputs to the function block 70 of the reconfigurable device 7 is increased in order to efficiently process multi-inputs that exceeds 2-input. FIG. 27 shows an example in which the function block 70 is made to be a function block for 4-input. The function block 70 shown in FIG. 27 includes a 4-input operation unit 110. Input data is supplied from four input ports 104a to 104d to the 4-input operation unit 110 and the operation result by the 4-input operation unit 110 is output from an output port 105 of the function block 70.
Increased number of inputs to the function block 70 is advantageous in light of improving operation speed. For example to realize a 4-input selector by a 2-input function block, three function blocks having 2-input selectors are required. As the connection between the function blocks are performed via a programmable switch, an operation speed is reduced due to signal delay in the programmable switch and wiring. On the other hand, when using the function block of 4-input shown in FIG. 27, it is possible to avoid reducing the operation speed caused from accumulation of wiring delays.
However increased number of input ports to the function block 70 in the reconfigurable device 7 results to increase the size of the programmable switch 15 for selecting input source for the input ports and configuration memory 16. In the case of FIG. 27, if the input ports to the function block 70 increases from 2-input to 4-input, the size of input selection unit 151 included in the programmable switch 15 doubles as compared to 2-input. This is because that the input source for the input ports 104a to 104d can be selected. Further, the size of the configuration memory 16 for storing configuration information of the input selection units 151a to 151d doubles as compared to 2-input.
Furthermore, this applies to addition and subtraction of data exceeding m bit. To add/subtract data exceeding m bit by combining m bit adder/subtracter, specifically to add/subtract with carry, a carry propagate is required between the m bit adder/subtracters. Therefore the plurality of function blocks 70 must be connected via the programmable switches 15 and this causes to reduce the operation speed due to wiring delays.
Thus as shown in FIG. 28, the adder/subtracter in the function block 70 is referred to as a 2 m bit wide adder/subtracter 122 that divides two 2m bit input data each into upper m bit and lower m bit and input from the four input ports 104a to 104d having m bit wide. Further, output data from the 2 m bit wide adder/subtracter is divided into upper m bit and lower m bit and output from output ports 105a and 105b. With this configuration, a carry propagate between the function blocks is unnecessary while using the programmable switch 15 having m bit wide and wiring resource.
However, as with the configuration to achieve the abovementioned 4-input selector, along with the increase of the number of input ports to the function block 70, size of the programmable switch 15 for selecting and configuration memory 16 also increases. Accordingly this increases hardware size of the reconfigurable device. The increase in the hardware size of the reconfigurable device causes to reduce integration degree of the reconfigurable device and further reduce area efficiency.
Note that even with increased number of input ports to the function block 70, by restricting the number of inputs of the programmable switch 15, it is possible to restrain from increasing the size of the programmable switch 15 and configuration memory 16. However in this way, flexibility of wiring between the function blocks 70 is limited, thereby constraining flexibility of changing circuit configuration.
As described above, we have now discovered a problem in the reconfigurable device according to the first related art in which along with the increase in the input port to the function block, the size of the programmable switch and configuration memory increases and the hardware size also increases.
Incidentally, such problem exists not only in the array processor 8 which is able to dynamically reconfigure depending on the application program. Specifically, this problem is common to reconfigurable integrated circuits having a configuration in which a connection relationship between function blocks are determined by a programmable switch such as a reconfigurable device capable of changing a connection relationship between function blocks including PLD (Programmable Logical Device) and FPGA (Field Programmable Gate array).

Switch coupled function blocks with additional direct coupling and internal data passing from input to output to facilitate more switched inputs to second block


The present invention particularly relates to a newly identified murine genomic polynucleotide that encodes an ortholog of the human P2T receptor which is expressed at high levels in the central nervous system, the use of such polynucleotides and polypeptides, as well as the production of such polynucleotides and polypeptides. The invention relates also to identifying compounds which may be agonists, antagonists and/or inhibitors of P2T, and therefore potentially useful in therapy.

Platelets play a central role in blood clot formation critical to the maintenance of normal homeostasis (Harder et al., 1995). Pathological thrombus formation producing vascular occlusion can result in stroke, myocardial infarction and unstable angina. Platelet aggregation and shape change are induced by ADP released from damaged vessels and red blood cells. ADP also is secreted by platelets from dense granules on activation, potentiating the aggregation response induced by other agents. Three types of purinergic receptors mediate the platelet response to ADP: P2X, an ADP-gated ion channel and two types of G-protein coupled receptors: P2Y1, coupled to increases in intracellular calcium via Gq, and P2T (P2YADP, P2YAC, P2Ycyc, P2TAC), an ADP receptor coupled to inhibition of adenylyl cyclase through Gi (Ralevic and Burnstock, 1998; Kunapuli, 1998; Jantzen et al., 1999; Boeynaerns et al., 2000). Interestingly, the P2T receptor is irreversibly inactivated by active metabolites of the anti-clotting drugs, ticlopidine and clopidogrel (Savi et al., 2000); and patients with a rare heritable clotting disorder lack P2T receptors (Catteneo et al., 1992; Nurden et al., 1995).
In addition, the P2T receptor may have a role in the central nervous system (CNS). ADP receptors with pharmacological properties similar to the platelet P2T receptor have been identified in B10 brain endothelial cells and rat C6 glioma cells (Webb et al., 1996; Boyer et al., 1993). Until recently however, the P2T G-protein-coupled receptor had remained uncloned (Zhang et al., 2001; Hollopeter et al., 2001).
In the CNS, nucleotides and related compounds are often released in concert with other neurotransmitters and act as signal transduction modulators. It has been reported that treatment of astrocytes with P2T selective agonists produces an increase in arachidonic acid release via a pertussis toxin sensitive G-protein-dependent mechanism (Chen and Chen, 1998). ADP-induced arachidonic acid release from astrocytes stimulates glycogenolysis, suggesting that the ADP receptor may be involved in regulation of glycogen metabolism in the CNS. Arachidonic acid acts directly on glial glutamate transporters to inhibit uptake of glutamate (Robinson and Dowd, 1997), further suggesting that glial ADP receptors may regulate neurotransmitter re-uptake. However, the exact role played by the P2T G-protein-coupled receptor in the CNS is not well understood.
It is well established that many medically significant biological processes are mediated by polypeptides participating in cellular signal transduction pathways that involve G proteins and second messengers, e.g., cAMP, IP3 and diacylglycerol (Lefkowitz, 1991). Some examples of these polypeptides include G-proteins and G-protein-coupled receptors themselves (e.g., G-protein-coupled receptor families I, II, III and IV), G-protein-coupled receptors such as those for biogenic amine transmitters (e.g., epinephrine, norepinephrine and dopamine) (Kobilka et al., 1987(a); Kobilka et al., 1987(b); Bunzow et al., 1988), effector polypeptides (e.g., phospholipase C, adenyl cyclase and phosphodiesterase) and actuator polypeptides (e.g., polypeptide kinase A and polypeptide kinase C) (Simon et al., 1991).
One particular pathway of cellular signal transduction is the inositol phospholipid pathway. In this pathway, an extracellular signal molecule (e.g., epinephrine) binds to a G-protein-coupled receptor. The G-protein-coupled receptor (GPCR) subsequently associates with a specific trimeric G-protein, wherein the trimer is comprised of α, β and γ polypeptide subunits. In the GPCR/G-polypeptide associated state, there is an exchange of GDP for GTP at the G-polypeptide α-subunit, resulting in the dissociation of the α-subunit from the β/γ subunits. The GTP bound α-subunit is the active state of the polypeptide. The active α-subunit further activates phospholipase C, which catalyzes the cleavage of PIP2 to IP3 and diacylglycerol (DAG). The IP3 and DAG serve as second messengers in further signal amplification (e.g., Ca2+ release and phosphorylation). Hydrolysis of GTP to GDP, catalyzed by the G-protein itself, returns the G-protein to its basal, inactive form. Thus, following GPCR binding a ligand molecule, the ligand activates a G-protein. The G-protein serves a dual role, as an intermediate that relays the signal from receptor to effector, and as a clock that controls the duration of the signal.
GPCRs are membrane bound polypeptides, comprising a gene superfamily characterized as having seven putative transmembrane domains. GPCRs can be intracellularly coupled by heterotrimeric G-proteins to various intracellular enzymes, ion channels and transporters (see, Johnson et al., 1989). Different G-protein α-subunits preferentially stimulate particular effectors to modulate various biological functions in a cell.
The G-protein-coupled receptors include a wide range of biologically active receptors, such as hormone receptors, viral receptors, growth factor receptors and neuroreceptors. Examples of members of this family include, but are not limited to, dopamine, calcitonin, adrenergic, endothelin, cAMP, adenosine, muscarinic acetylcholine, serotonin, histamine, thrombin, kinin, follicle stimulating hormone, opsins, endothelial differentiation gene-1, rhodopsins, odorant, and cytomegalovirus receptors.
The seven transmembrane domains are believed to represent transmembrane α-helices connected by extracellular or cytoplasmic loops. GPCRs have been characterized as including these seven conserved hydrophobic stretches of about 20 to 30 amino acids, connecting at least eight divergent hydrophilic loops. Most GPCRs (also known as 7TM receptors) have single conserved cysteine residues in each of the first two extracellular loops which form disulfide bonds that are believed to stabilize functional polypeptide structure. The 7 transmembrane regions are designated as TM1, TM2, TM3, TM4, TM5, TM6, and TM7. TM3 has been implicated in several GPCRs as having a ligand binding site, such as the TM3 aspartate residue. TM5 serines, a TM6 asparagine and TM6 or TM7 phenylalanines or tyrosines are also implicated in ligand binding in certain receptor families.
Phosphorylation and lipidation (palmitylation or farnesylation) of cysteine residues can influence signal transduction of some GPCRs. Most GPCRs contain potential phosphorylation sites within the third cytoplasmic loop and/or the carboxy terminus. For several GPCRs, such as the β-adrenoreceptor, phosphorylation by polypeptide kinase A and/or specific receptor kinases mediates receptor desensitization.
Presently, more than 800 GPCRs from various eukaryotic species have been cloned, 140 of which are human GPCRs for which endogenous ligands are known (Stadel et al., 1997). In addition, several hundred therapeutic agents targeting GPCRs such as angiotensin receptors, calcitonin receptors, adrenoceptor receptors, serotonin receptors, leukotriene receptors, oxytocin receptors, prostaglandin receptors, dopamine receptors, histamine receptors, muscarinic acetylcholine receptors, opioid receptors, somatostatin receptors and vasopressin receptors have been successfully introduced onto the market for various indications (see Stadel et al., 1997). This indicates that these receptors have an established, proven history as therapeutic targets. The search for GPCR genes has also identified numerous genes whose products are members of the GPCR family, but for which their natural ligands are not known, commonly refered to as orphan receptors. In fact, more than 100 of the 240 human GPCRs identified (i.e., about 45%) are orphan receptors, and it is estimated that there are at least 400–1000 more GPCR genes that have yet to be identified (Stadel et al., 1997).
Thus, there is clearly a need for the identification and characterization of further GPCRs, their genes and their ligands, which can play a role in preventing, ameliorating or correcting dysfunctions or diseases, including, but not limited to, infections such as bacterial, fungal, protozoan and viral infections, particularly infections caused by HIV-1 or HIV-2; pain; cancers; anorexia; bulimia; asthma; Parkinson's disease; acute heart failure; hypotension; hypertension; platelet formation and aggregation; stroke; urinary retention; osteoporosis; angina pectoris; myocardial infarction; ulcers; asthma; allergies; benign prostatic hypertrophy; and psychotic and neurological disorders, including anxiety, schizophrenia, manic depression, delirium, dementia, severe mental retardation and dyskinesias, such as Huntington's disease or Gilles dela Tourett's syndrome.

Murine genomic polynucleotide sequence encoding a G-protein coupled receptor and methods of use therefor


A reproducing method of reproducing magnetic information written in each of bits of a recording medium using a magnetic head having a reading element configured to measure external magnetic field intensity includes moving, measuring and specifying steps. In the moving step, the magnetic head moves to a position where the reading element covers two bits, one bit having known magnetic information, the other bit being adjacent to the one bit and having unknown magnetic information. In the measuring step, the reading element measures magnetic field intensity coming from the recording medium. In the specifying step, magnetic information of the bit having the unknown magnetic information is specified based on the magnetic field intensity measured in the measuring step and magnetic information of the bit having the known magnetic information.

1. Field of the Invention
The present invention relates to a rework method and apparatus (or reproducing method and apparatus) of reproducing magnetic information written in a record medium (or recoding medium).
2. Description of the Related Art
Various devices such as a personal computer, a music player, and the like are equipped with a recording medium such as, for example, a hard disk. In recent years, the recording medium described above has been developed with a high recording density.
Specifically, writing magnetic information in the recording medium by a shingle write technology may result in a narrowed recording track width of the recording medium (see, for example, Japanese laid-open patent application publication number 2006-294162). In the shingle write technology, magnetic information of one track is overlappingly written in a portion of an adjacent track with respect to a track width direction (a direction orthogonal to the track direction). As a result, the recording medium records the magnetic information with a small track pitch. Therefore, the recording density of the recording medium is improved.
As described above, the magnetic information written in the recording medium is read by a reading element of a magnetic head, and is reproduced. The reading element detects a magnetic direction of each bit of the recording medium. With the configuration, the magnetic head reads the magnetic information written in each bit of the recording medium.
However, when the reading element of the magnetic head is wider than a width of each bit of the recording medium, the reading element is affected by a magnetic field generated from adjacent bits, so that it is occasionally impossible to accurately read the magnetic information of specified bits. Therefore, as the width of each bit of the recording medium becomes narrower, reproducing the magnetic information becomes more difficult.
As a result, it is desired to provide a reproducing method and reproducing apparatus for reading the magnetic information written in a recording medium with a narrow read gap.

Rework method and apparatus of magnetic record medium, information


A steering system for boats includes a control member of the steering wheel type, lever type or the like connected to a driving shaft of a transmission composed of at least two transmission elements dynamically engaged one with the other, of which one is an input and the other one an output elements. The output element drives a member transferring the motion of the control member to an operating unit, such that a movement/rotation of the control member is transmitted to the transfer member through such transmission. Moreover, at least the input element is produced from a material obtained by a sintering process.

The arrangement just described is a standard one for a steering system for boats, particularly for a mechanical steering system for controlling boats.
Such steering systems have a control member, whose movement drives the components of a transmission transferring the movement of the control member through a corresponding operation of an operating unit to control, for example, steering actuators.
The transmission of such steering systems must be particularly efficient, namely, the input element has to dynamically engage the output element without generating "clearances" to efficiently transmit the movement of the control member to the transfer member and to an operating unit.
The components of such transmission system are subject to high stresses. Firstly, such components are subjected to stresses related to mechanical operation, namely, the continuous changes in direction related to boat movements generate continuous fatigue cycles that wear the components out, causing a deterioration that leads to malfunctions and inefficiencies in the performance of the entire steering system.
Secondly, the wear on the transmission components can be due to external agents related to the environment where the steering systems operate, i.e. the marine environment, which is particularly aggressive against the different components.
Finally, "clearances" in the dynamic coupling of the transmission components can create a relative movement between the components affecting the "softness" of the steering system, which is the fluidity of the control member during movement, as well as the quickness of response of the operating unit according to the movement of the control member.
Therefore, there is an unsatisfied need for a steering system for boats, particularly a mechanical steering system, which by means of relatively simple and inexpensive arrangements solves prior art drawbacks, and in particular provides an improvement in the performance and efficiency of transmissions of prior art steering systems.


A technique is provided for resolving a reportable condition. Upon detection of a reportable condition on a processor-based medical system, machine data is provided to a knowledge engine. One or more identified solutions are received from the knowledge engine and implemented on the processor-based medical system. The one or more solutions are verified as they are implemented to determine if the currently implemented solution resolves the reportable condition. Routines implementing some or all of the technique may be provided on a processor-based system or on a machine-readable medium.

The invention relates generally to providing remote service assistance in an automated or semi-automated manner, such as by automatically providing service suggestions which may be automatically implemented or implemented by a customer without on-site assistance.
In a variety of industrial, commercial, medical, and research contexts, various pieces of equipment may be employed on a day-to-day basis to accomplish or facilitate the work being performed at a facility. In many instances, the facility may rely upon a third party to provide service for some or all of the equipment at the site to ensure that the equipment remains operational and available. For example, in an industrial setting, production equipment or computer resources that are in operation in a continuous or near continuous manner may be serviced by an off-site party that provides servicing as needed or requested. Similarly, hospitals, clinics, and research facilities may utilize another party to service some or all of the diagnostic, monitoring, and/or imaging equipment at a site so that the equipment remains available where and when it is needed.
Such an arrangement, however, may impose burdens on the service provider that are difficult to overcome in an efficient and cost effective manner. For example, a service provider may utilize field personnel, such as field engineers, to provide on-site support to a variety of clients. As one might expect, such on-site support is resource and time intensive, requiring highly trained personnel to travel to various customer sites to provide support. As a result, support time is lost to travel, and other factors associated with maintaining field personnel and services. Furthermore, the customer experiences downtime due to system problems that, in some cases, can be addressed without the aid of a field engineer, such as by the customer implementing the fix themselves.
In many instances, a problem being experienced at a client site may be diagnosed based on information, such as error logs or messages, available at the site. In such instances, one or more solutions or fixes to the problem may be indicated. Depending on the problem, implementing such fixes may not require the technical expertise or experience of a field engineer or technician. In such instances, it may be undesirable to provide a costly and time-consuming on-site service call.

Method for resolving conditions of a medical system using solution verification


Sub-millimeter scale three-dimensional (3D) structures are disclosed with customizable chemical properties and/or functionality. The 3D structures are referred to as drop-carrier particles. The drop-carrier particles allow the selective association of one solution (i.e., a dispersed phased) with an interior portion of each of the drop-carrier particles, while a second non-miscible solution (i.e., a continuous phase) associates with an exterior portion of each of the drop-carrier particles due to the specific chemical and/or physical properties of the interior and exterior regions of the drop-carrier particles. The combined drop-carrier particle with the dispersed phase contained therein is referred to as a particle-drop. The selective association results in compartmentalization of the dispersed phase solution into sub-microliter-sized volumes contained in the drop-carrier particles. The compartmentalized volumes can be used for single-molecule assays as well as single-cell, and other single-entity assays.

Single-molecule or single-cell assays (e.g., digital PCR, digital loop-mediated isothermal amplification (LAMP), digital ELISA, Drop-Seq) require fractionating or compartmentalizing a large volume to such a level that each smaller fractionated volume contains either none (0) or a single (1) entity of interest (i.e., a digital assay). Regardless of the compartment type, it is important that each fractionated compartment is relatively uniform in volume in order to allow reactions to proceed with similar properties in each fractionated volume. Currently, the main approaches to perform this compartmentalization in a uniform manner rely on (i) arrays of wells or (ii) the creation of monodisperse emulsions of drops or droplets using microfluidic approaches. However, there are significant disadvantages to microfluidic approaches given the cost for instruments, pumps, and microfluidic chips required to produce the droplets. Also, small sample volumes can be difficult to use because of the large dead-volumes contained within microfluidic pumping systems. In addition, solid surfaces for reaction or to release reagents and unique barcodes are desired for digital ELISA and single-cell RNAseq, but these are not easy to introduce in microwell arrays or droplets, and can be limited by Poisson statistics. For example, for digital ELISA assays there is often a bead that should be introduced into each volume that provides an affinity reagent to detect a protein of interest, while for single-cell nucleic acid amplification and sequencing assays, it is often desired to include a unique molecular barcode into each droplet such that the RNA amplified from each cell can be re-assigned to the cell of origin even after combining or pooling all of the nucleic acids for a sequencing run. Therefore, there is a need to create simply operated methods of creating uniformly sized fluid compartments that also are associated with solid supports that allow reagent introduction into each compartment or volume.

This patent is subject to a terminal disclaimer.

Particle-drop structures and methods for making and using the same

THE REGENTS OF THE UNIVERSITY OF CALIFORNIA


Adjustable gun carriages are disclosed. An example gun carriage includes: a coarse height adjustment brake; a coarse side-to-side adjustment brake; a fine height orientation adjustment mechanism; a fine side-to-side orientation adjustment mechanism; a first control to actuate the coarse height adjustment brake; a second control to actuate the fine height orientation adjustment mechanism; a third control to actuate the coarse side-to-side adjustment brake; and a fourth control to actuate the fine side-to-side orientation adjustment mechanism.

Firearms such as, machine guns, grenade throwers, other automatic weapons, etc., are commonly mounted on adjustable gun carriages. These gun carriages may be positioned on a suitable base (e.g., a tripod) on the ground, on a vehicle, or on a building and are designed to facilitate aiming and firing of the mounted weapon.
An adjustable gun carriage should meet various criteria: For example, it should be smoothly and precisely adjustable to facilitate accurate aiming and target coverage. Also, the gun carriage should not impede the handling of the weapon, but rather, should improve such weapon handling. A gun carriage should also be precise and stable during the adjustment process. If used with, for example, a weapon that shoots grenades, the gun carriage should be height adjustable and side-to-side rotatable in order to increase the ammunition effect in the target area. Gun carriages should also be suitable for use with different types of weapons while providing consistent handling. Traditional gun carriages only meet these requirements partly or inadequately.


The technique of the present invention provides a solution to the problem of routing or redirecting a given client to a replica or proxy server which has a relatively shortest propagation delay to the client. According to the technique of the present invention, a network device referred to as an intercept server sits in front of a host server, and intercepts packets routed to the host server. When desired, packets which are intercepted by the intercept server are replicated, encapsulated and tunneled to selected client servers in the overlay network. The tunneled packets are received and processed by each of the selected client servers, whereupon each of the selected client servers generates a respective spoofed response to the source device identified in the header of the originally intercepted packet. Further, according to the technique of the present invention, each of the selected client servers transmits its respective spoofed response to the identified source device at substantially the same time. The client server associated with the spoofed response which is first received at the identified source device is considered to have the relatively shortest propagation delay to the identified source device, and is identified as the successful client server. Thereafter, the source device will be directed or redirected to communicate directly with the successful client server when subsequently attempting to access information from the host server.

1. Field of the Invention
The present invention relates generally to data networks, and more specifically to a technique for distributed load balancing of network traffic across a data network.
2. Background
Content providers on the World Wide Web are willing to pay a great deal of money to guarantee that their content is delivered quickly and accurately to any given client. Accordingly, a great deal of research has been conducted to address the problem of speeding up HTTP transactions conducted between a client and a server, particularly in situations where there is a relatively large propagation delay between the client and the server.
Although the speed of data transmission across the Internet is continuing to increase, the propagation delay associated with the speed of an electrical signal traveling through a wire or fiberoptic cable (i.e. the speed of light) cannot be reduced. Such delays are becoming a significant factor in the overall propagation delay between the server and client. In order to reduce the overall propagation delay between a given server and a given client, conventional techniques have resorted to replicating the server system, and placing multiple copies of the replicated server system at locations as near as possible to the client.
Thus, for example, a common technique used by content providers is to store content from the host server in co-location spaces that are geographically distributed over a wide area. The co-location spaces form an overlay network that is more costly and less flexible, but provide better service than the traditional Internet. Typically the ISPs which manage the co-location spaces charge the content provider for each megabyte stored in the co-location space. The co-location spaces may be implemented as proxy servers, which pull specific data from the host server in response to specific client requests, or may be implemented as fully replicated servers which include all the information of the host server.
Although the use of co-location spaces will help reduce the overall propagation delay between a server and client, another issue which arises relates to the problem of determining how an arbitrary client is redirected to the nearest replica or proxy server, particularly where it is not known ahead of time which clients will be asking for information and where the clients are located. Some conventional techniques have been implemented to address this problem, but typically require the use of a gateway router.
An alternate technique for predicting, for a given client, the nearest replica or proxy server to that client has been developed by Akamai Technologies, Inc. (of Cambridge, Mass.). The proprietary Akamai routing technique involves constructing a network map of the Internet topology. The network map information is stored in a central network operating center or NOC which is located on a specific Akamai server. When a client attempts to access a content provider's site which is part of the Akamai overlay network of co-location servers, the client will initiate a DNS resolution request, which is resolved by the NOC server. The NOC dynamically resolves the requested domain name to a co-location server address that is nearest topologically to the client, using information from the network map.
However, in order for Akamai's routing technique to be successfully implemented, the network topology map must be continually updated and maintained. According to at least one school of thought, however, maintaining an accurate Internet topology may be nearly impossible since the Internet topology is dynamically changing and is exponentially growing in size and complexity each day.
More importantly, the Akaimi routing technique is limited only to resolving DNS queries implemented using DNS protocol. Currently, the Akaimi technique for re-routing clients to a nearest proxy server is not extendable to other protocols such as, for example, TCP. Thus, for example, when a client obtains a particular IP address of a server, and subsequently attempts to initiate a TCP connection with that server, the Akaimi technique can not be used to re-route the client to establish a TCP connection with a topologically closer proxy server.
Accordingly, in light of the foregoing, there exists a continual need to develop alternative solutions for providing fast and efficient routing and load balancing of web traffic across data networks.

Distributed network traffic load balancing technique implemented without gateway router